From 813cf972c823481ba1c67da250bd47baf30f6b5c Mon Sep 17 00:00:00 2001 From: Liviu Ionescu Date: Wed, 16 May 2018 21:57:40 +0300 Subject: [PATCH] bring extra GME files back, from build.git --- gnu-mcu-eclipse/README.md | 5 + gnu-mcu-eclipse/develop/CortexM.md | 23 + gnu-mcu-eclipse/develop/Eclipse-formatter.xml | 167 + gnu-mcu-eclipse/develop/STM32.md | 38 + gnu-mcu-eclipse/develop/STYLE.md | 45 + gnu-mcu-eclipse/develop/TODO.md | 41 + gnu-mcu-eclipse/develop/irqs.md | 139 + gnu-mcu-eclipse/develop/repos.md | 32 + gnu-mcu-eclipse/develop/templates/stm32-xxx.c | 273 + gnu-mcu-eclipse/develop/templates/stm32-xxx.h | 89 + gnu-mcu-eclipse/devices/README.md | 23 + gnu-mcu-eclipse/devices/STM32F0x1-qemu.json | 30391 +++++++++ gnu-mcu-eclipse/devices/STM32F0x2-qemu.json | 30327 +++++++++ gnu-mcu-eclipse/devices/STM32F103xx-qemu.json | 23622 +++++++ gnu-mcu-eclipse/devices/STM32F107xx-qemu.json | 32530 +++++++++ gnu-mcu-eclipse/devices/STM32F40x-qemu.json | 51027 ++++++++++++++ gnu-mcu-eclipse/devices/STM32F411xx-qemu.json | 23301 +++++++ gnu-mcu-eclipse/devices/STM32F429x-qemu.json | 55348 +++++++++++++++ gnu-mcu-eclipse/devices/support/README.md | 242 + .../devices/support/STM32F0x1-patch.json | 135 + .../devices/support/STM32F0x1-xsvd.json | 30688 +++++++++ .../devices/support/STM32F0x1/adc.c | 324 + .../devices/support/STM32F0x1/adc.h | 209 + .../devices/support/STM32F0x1/can.c | 2560 + .../devices/support/STM32F0x1/can.h | 2603 + .../devices/support/STM32F0x1/cec.c | 290 + .../devices/support/STM32F0x1/cec.h | 167 + .../devices/support/STM32F0x1/comp.c | 255 + .../devices/support/STM32F0x1/comp.h | 122 + .../devices/support/STM32F0x1/crc.c | 253 + .../devices/support/STM32F0x1/crc.h | 126 + .../devices/support/STM32F0x1/crs.c | 272 + .../devices/support/STM32F0x1/crs.h | 145 + .../devices/support/STM32F0x1/dac.c | 269 + .../devices/support/STM32F0x1/dac.h | 148 + .../devices/support/STM32F0x1/dbgmcu.c | 263 + .../devices/support/STM32F0x1/dbgmcu.h | 136 + .../devices/support/STM32F0x1/dma1.c | 490 + .../devices/support/STM32F0x1/dma1.h | 421 + .../devices/support/STM32F0x1/exti.c | 384 + .../devices/support/STM32F0x1/exti.h | 261 + .../devices/support/STM32F0x1/flash.c | 290 + .../devices/support/STM32F0x1/flash.h | 171 + .../devices/support/STM32F0x1/gpioa.c | 449 + .../devices/support/STM32F0x1/gpioa.h | 346 + .../devices/support/STM32F0x1/gpiof.c | 449 + .../devices/support/STM32F0x1/gpiof.h | 346 + .../devices/support/STM32F0x1/i2c1.c | 353 + .../devices/support/STM32F0x1/i2c1.h | 246 + .../devices/support/STM32F0x1/iwdg.c | 256 + .../devices/support/STM32F0x1/iwdg.h | 131 + .../devices/support/STM32F0x1/pwr.c | 259 + .../devices/support/STM32F0x1/pwr.h | 128 + .../devices/support/STM32F0x1/rcc.c | 425 + .../devices/support/STM32F0x1/rcc.h | 318 + .../devices/support/STM32F0x1/rtc.c | 395 + .../devices/support/STM32F0x1/rtc.h | 300 + .../devices/support/STM32F0x1/spi1.c | 318 + .../devices/support/STM32F0x1/spi1.h | 207 + .../devices/support/STM32F0x1/syscfg.c | 291 + .../devices/support/STM32F0x1/syscfg.h | 168 + .../devices/support/STM32F0x1/tim1.c | 427 + .../devices/support/STM32F0x1/tim1.h | 336 + .../devices/support/STM32F0x1/tim14.c | 297 + .../devices/support/STM32F0x1/tim14.h | 186 + .../devices/support/STM32F0x1/tim15.c | 366 + .../devices/support/STM32F0x1/tim15.h | 267 + .../devices/support/STM32F0x1/tim16.c | 339 + .../devices/support/STM32F0x1/tim16.h | 236 + .../devices/support/STM32F0x1/tim2.c | 401 + .../devices/support/STM32F0x1/tim2.h | 306 + .../devices/support/STM32F0x1/tim6.c | 271 + .../devices/support/STM32F0x1/tim6.h | 152 + .../devices/support/STM32F0x1/tsc.c | 415 + .../devices/support/STM32F0x1/tsc.h | 310 + .../devices/support/STM32F0x1/usart1.c | 378 + .../devices/support/STM32F0x1/usart1.h | 277 + .../devices/support/STM32F0x1/usb.c | 406 + .../devices/support/STM32F0x1/usb.h | 301 + .../devices/support/STM32F0x1/wwdg.c | 249 + .../devices/support/STM32F0x1/wwdg.h | 120 + .../devices/support/STM32F0x2-patch.json | 135 + .../devices/support/STM32F0x2-xsvd.json | 30633 +++++++++ .../devices/support/STM32F0x2/adc.c | 311 + .../devices/support/STM32F0x2/adc.h | 137 + .../devices/support/STM32F0x2/can.c | 2468 + .../devices/support/STM32F0x2/can.h | 453 + .../devices/support/STM32F0x2/cec.c | 281 + .../devices/support/STM32F0x2/cec.h | 121 + .../devices/support/STM32F0x2/comp.c | 251 + .../devices/support/STM32F0x2/comp.h | 101 + .../devices/support/STM32F0x2/crc.c | 246 + .../devices/support/STM32F0x2/crc.h | 113 + .../devices/support/STM32F0x2/crs.c | 265 + .../devices/support/STM32F0x2/crs.h | 113 + .../devices/support/STM32F0x2/dac.c | 259 + .../devices/support/STM32F0x2/dac.h | 125 + .../devices/support/STM32F0x2/dbgmcu.c | 256 + .../devices/support/STM32F0x2/dbgmcu.h | 113 + .../devices/support/STM32F0x2/dma1.c | 456 + .../devices/support/STM32F0x2/dma1.h | 227 + .../devices/support/STM32F0x2/exti.c | 375 + .../devices/support/STM32F0x2/exti.h | 121 + .../devices/support/STM32F0x2/flash.c | 279 + .../devices/support/STM32F0x2/flash.h | 129 + .../devices/support/STM32F0x2/gpioa.c | 434 + .../devices/support/STM32F0x2/gpioa.h | 156 + .../devices/support/STM32F0x2/gpiof.c | 434 + .../devices/support/STM32F0x2/gpiof.h | 156 + .../devices/support/STM32F0x2/i2c1.c | 338 + .../devices/support/STM32F0x2/i2c1.h | 152 + .../devices/support/STM32F0x2/iwdg.c | 248 + .../devices/support/STM32F0x2/iwdg.h | 117 + .../devices/support/STM32F0x2/pwr.c | 254 + .../devices/support/STM32F0x2/pwr.h | 105 + .../devices/support/STM32F0x2/rcc.c | 405 + .../devices/support/STM32F0x2/rcc.h | 153 + .../devices/support/STM32F0x2/rtc.c | 372 + .../devices/support/STM32F0x2/rtc.h | 177 + .../devices/support/STM32F0x2/spi1.c | 305 + .../devices/support/STM32F0x2/spi1.h | 144 + .../devices/support/STM32F0x2/syscfg.c | 282 + .../devices/support/STM32F0x2/syscfg.h | 121 + .../devices/support/STM32F0x2/tim1.c | 402 + .../devices/support/STM32F0x2/tim1.h | 185 + .../devices/support/STM32F0x2/tim14.c | 282 + .../devices/support/STM32F0x2/tim14.h | 145 + .../devices/support/STM32F0x2/tim15.c | 345 + .../devices/support/STM32F0x2/tim15.h | 169 + .../devices/support/STM32F0x2/tim16.c | 320 + .../devices/support/STM32F0x2/tim16.h | 161 + .../devices/support/STM32F0x2/tim2.c | 378 + .../devices/support/STM32F0x2/tim2.h | 177 + .../devices/support/STM32F0x2/tim6.c | 260 + .../devices/support/STM32F0x2/tim6.h | 129 + .../devices/support/STM32F0x2/tsc.c | 397 + .../devices/support/STM32F0x2/tsc.h | 157 + .../devices/support/STM32F0x2/usart1.c | 363 + .../devices/support/STM32F0x2/usart1.h | 154 + .../devices/support/STM32F0x2/usb.c | 388 + .../devices/support/STM32F0x2/usb.h | 157 + .../devices/support/STM32F0x2/wwdg.c | 243 + .../devices/support/STM32F0x2/wwdg.h | 109 + .../devices/support/STM32F103xx-patch.json | 151 + .../devices/support/STM32F103xx-xsvd.json | 24302 +++++++ .../devices/support/STM32F103xx/adc1.c | 382 + .../devices/support/STM32F103xx/adc1.h | 294 + .../devices/support/STM32F103xx/adc2.c | 380 + .../devices/support/STM32F103xx/adc2.h | 292 + .../devices/support/STM32F103xx/afio.c | 297 + .../devices/support/STM32F103xx/afio.h | 176 + .../devices/support/STM32F103xx/bkp.c | 422 + .../devices/support/STM32F103xx/bkp.h | 377 + .../devices/support/STM32F103xx/can.c | 1523 + .../devices/support/STM32F103xx/can.h | 1510 + .../devices/support/STM32F103xx/crc.c | 246 + .../devices/support/STM32F103xx/crc.h | 117 + .../devices/support/STM32F103xx/dac.c | 303 + .../devices/support/STM32F103xx/dac.h | 194 + .../devices/support/STM32F103xx/dbg.c | 261 + .../devices/support/STM32F103xx/dbg.h | 130 + .../devices/support/STM32F103xx/dma1.c | 490 + .../devices/support/STM32F103xx/dma1.h | 421 + .../devices/support/STM32F103xx/exti.c | 366 + .../devices/support/STM32F103xx/exti.h | 243 + .../devices/support/STM32F103xx/flash.c | 287 + .../devices/support/STM32F103xx/flash.h | 168 + .../devices/support/STM32F103xx/fsmc.c | 497 + .../devices/support/STM32F103xx/fsmc.h | 416 + .../devices/support/STM32F103xx/gpioa.c | 389 + .../devices/support/STM32F103xx/gpioa.h | 278 + .../devices/support/STM32F103xx/i2c1.c | 319 + .../devices/support/STM32F103xx/i2c1.h | 208 + .../devices/support/STM32F103xx/iwdg.c | 251 + .../devices/support/STM32F103xx/iwdg.h | 124 + .../devices/support/STM32F103xx/pwr.c | 251 + .../devices/support/STM32F103xx/pwr.h | 120 + .../devices/support/STM32F103xx/rcc.c | 406 + .../devices/support/STM32F103xx/rcc.h | 291 + .../devices/support/STM32F103xx/rtc.c | 281 + .../devices/support/STM32F103xx/rtc.h | 166 + .../devices/support/STM32F103xx/sdio.c | 386 + .../devices/support/STM32F103xx/sdio.h | 287 + .../devices/support/STM32F103xx/spi1.c | 309 + .../devices/support/STM32F103xx/spi1.h | 199 + .../devices/support/STM32F103xx/tim1.c | 427 + .../devices/support/STM32F103xx/tim1.h | 336 + .../devices/support/STM32F103xx/tim10.c | 296 + .../devices/support/STM32F103xx/tim10.h | 185 + .../devices/support/STM32F103xx/tim2.c | 390 + .../devices/support/STM32F103xx/tim2.h | 295 + .../devices/support/STM32F103xx/tim6.c | 271 + .../devices/support/STM32F103xx/tim6.h | 152 + .../devices/support/STM32F103xx/tim9.c | 325 + .../devices/support/STM32F103xx/tim9.h | 218 + .../devices/support/STM32F103xx/uart4.c | 294 + .../devices/support/STM32F103xx/uart4.h | 177 + .../devices/support/STM32F103xx/uart5.c | 293 + .../devices/support/STM32F103xx/uart5.h | 176 + .../devices/support/STM32F103xx/usart1.c | 309 + .../devices/support/STM32F103xx/usart1.h | 195 + .../devices/support/STM32F103xx/usb.c | 384 + .../devices/support/STM32F103xx/usb.h | 275 + .../devices/support/STM32F103xx/wwdg.c | 249 + .../devices/support/STM32F103xx/wwdg.h | 120 + .../devices/support/STM32F107xx-patch.json | 151 + .../devices/support/STM32F107xx-xsvd.json | 33373 ++++++++++ .../devices/support/STM32F107xx/adc1.c | 382 + .../devices/support/STM32F107xx/adc1.h | 293 + .../devices/support/STM32F107xx/adc2.c | 380 + .../devices/support/STM32F107xx/adc2.h | 291 + .../devices/support/STM32F107xx/afio.c | 299 + .../devices/support/STM32F107xx/afio.h | 178 + .../devices/support/STM32F107xx/bkp.c | 422 + .../devices/support/STM32F107xx/bkp.h | 377 + .../devices/support/STM32F107xx/can2.c | 2560 + .../devices/support/STM32F107xx/can2.h | 2603 + .../devices/support/STM32F107xx/crc.c | 246 + .../devices/support/STM32F107xx/crc.h | 117 + .../devices/support/STM32F107xx/dac.c | 303 + .../devices/support/STM32F107xx/dac.h | 194 + .../devices/support/STM32F107xx/dbg.c | 260 + .../devices/support/STM32F107xx/dbg.h | 129 + .../devices/support/STM32F107xx/dma1.c | 490 + .../devices/support/STM32F107xx/dma1.h | 421 + .../support/STM32F107xx/ethernet_dma.c | 343 + .../support/STM32F107xx/ethernet_dma.h | 234 + .../support/STM32F107xx/ethernet_mac.c | 369 + .../support/STM32F107xx/ethernet_mac.h | 274 + .../support/STM32F107xx/ethernet_mmc.c | 289 + .../support/STM32F107xx/ethernet_mmc.h | 176 + .../support/STM32F107xx/ethernet_ptp.c | 277 + .../support/STM32F107xx/ethernet_ptp.h | 160 + .../devices/support/STM32F107xx/exti.c | 372 + .../devices/support/STM32F107xx/exti.h | 249 + .../devices/support/STM32F107xx/flash.c | 287 + .../devices/support/STM32F107xx/flash.h | 168 + .../devices/support/STM32F107xx/gpioa.c | 389 + .../devices/support/STM32F107xx/gpioa.h | 277 + .../devices/support/STM32F107xx/i2c1.c | 319 + .../devices/support/STM32F107xx/i2c1.h | 208 + .../devices/support/STM32F107xx/iwdg.c | 251 + .../devices/support/STM32F107xx/iwdg.h | 124 + .../devices/support/STM32F107xx/pwr.c | 251 + .../devices/support/STM32F107xx/pwr.h | 120 + .../devices/support/STM32F107xx/rcc.c | 413 + .../devices/support/STM32F107xx/rcc.h | 302 + .../devices/support/STM32F107xx/rtc.c | 281 + .../devices/support/STM32F107xx/rtc.h | 166 + .../devices/support/STM32F107xx/spi1.c | 309 + .../devices/support/STM32F107xx/spi1.h | 199 + .../devices/support/STM32F107xx/tim1.c | 427 + .../devices/support/STM32F107xx/tim1.h | 336 + .../devices/support/STM32F107xx/tim2.c | 390 + .../devices/support/STM32F107xx/tim2.h | 295 + .../devices/support/STM32F107xx/tim6.c | 271 + .../devices/support/STM32F107xx/tim6.h | 152 + .../devices/support/STM32F107xx/uart4.c | 294 + .../devices/support/STM32F107xx/uart4.h | 177 + .../devices/support/STM32F107xx/uart5.c | 293 + .../devices/support/STM32F107xx/uart5.h | 176 + .../devices/support/STM32F107xx/usart1.c | 309 + .../devices/support/STM32F107xx/usart1.h | 195 + .../support/STM32F107xx/usb_otg_device.c | 552 + .../support/STM32F107xx/usb_otg_device.h | 493 + .../support/STM32F107xx/usb_otg_global.c | 406 + .../support/STM32F107xx/usb_otg_global.h | 309 + .../support/STM32F107xx/usb_otg_host.c | 630 + .../support/STM32F107xx/usb_otg_host.h | 573 + .../support/STM32F107xx/usb_otg_pwrclk.c | 240 + .../support/STM32F107xx/usb_otg_pwrclk.h | 107 + .../devices/support/STM32F107xx/wwdg.c | 249 + .../devices/support/STM32F107xx/wwdg.h | 120 + .../devices/support/STM32F40x-patch.json | 139 + .../devices/support/STM32F40x-xsvd.json | 52083 +++++++++++++++ .../devices/support/STM32F40x/adc1.c | 366 + .../devices/support/STM32F40x/adc1.h | 278 + .../devices/support/STM32F40x/c_adc.c | 270 + .../devices/support/STM32F40x/c_adc.h | 141 + .../devices/support/STM32F40x/can1.c | 2565 + .../devices/support/STM32F40x/can1.h | 2614 + .../devices/support/STM32F40x/crc.c | 246 + .../devices/support/STM32F40x/crc.h | 117 + .../devices/support/STM32F40x/dac.c | 310 + .../devices/support/STM32F40x/dac.h | 203 + .../devices/support/STM32F40x/dbg.c | 279 + .../devices/support/STM32F40x/dbg.h | 152 + .../devices/support/STM32F40x/dcmi.c | 317 + .../devices/support/STM32F40x/dcmi.h | 204 + .../devices/support/STM32F40x/dma2.c | 698 + .../devices/support/STM32F40x/dma2.h | 673 + .../devices/support/STM32F40x/ethernet_dma.c | 349 + .../devices/support/STM32F40x/ethernet_dma.h | 242 + .../devices/support/STM32F40x/ethernet_mac.c | 376 + .../devices/support/STM32F40x/ethernet_mac.h | 281 + .../devices/support/STM32F40x/ethernet_mmc.c | 291 + .../devices/support/STM32F40x/ethernet_mmc.h | 178 + .../devices/support/STM32F40x/ethernet_ptp.c | 297 + .../devices/support/STM32F40x/ethernet_ptp.h | 184 + .../devices/support/STM32F40x/exti.c | 390 + .../devices/support/STM32F40x/exti.h | 267 + .../devices/support/STM32F40x/flash.c | 284 + .../devices/support/STM32F40x/flash.h | 161 + .../devices/support/STM32F40x/fsmc.c | 497 + .../devices/support/STM32F40x/fsmc.h | 416 + .../devices/support/STM32F40x/gpioa.c | 430 + .../devices/support/STM32F40x/gpioa.h | 328 + .../devices/support/STM32F40x/gpiob.c | 430 + .../devices/support/STM32F40x/gpiob.h | 328 + .../devices/support/STM32F40x/gpioi.c | 430 + .../devices/support/STM32F40x/gpioi.h | 328 + .../devices/support/STM32F40x/i2c3.c | 319 + .../devices/support/STM32F40x/i2c3.h | 209 + .../devices/support/STM32F40x/iwdg.c | 251 + .../devices/support/STM32F40x/iwdg.h | 124 + .../devices/support/STM32F40x/otg_fs_device.c | 552 + .../devices/support/STM32F40x/otg_fs_device.h | 493 + .../devices/support/STM32F40x/otg_fs_global.c | 406 + .../devices/support/STM32F40x/otg_fs_global.h | 309 + .../devices/support/STM32F40x/otg_fs_host.c | 630 + .../devices/support/STM32F40x/otg_fs_host.h | 573 + .../devices/support/STM32F40x/otg_fs_pwrclk.c | 240 + .../devices/support/STM32F40x/otg_fs_pwrclk.h | 107 + .../devices/support/STM32F40x/otg_hs_device.c | 832 + .../devices/support/STM32F40x/otg_hs_device.h | 827 + .../devices/support/STM32F40x/otg_hs_global.c | 457 + .../devices/support/STM32F40x/otg_hs_global.h | 372 + .../devices/support/STM32F40x/otg_hs_host.c | 986 + .../devices/support/STM32F40x/otg_hs_host.h | 1009 + .../devices/support/STM32F40x/otg_hs_pwrclk.c | 240 + .../devices/support/STM32F40x/otg_hs_pwrclk.h | 107 + .../devices/support/STM32F40x/pwr.c | 255 + .../devices/support/STM32F40x/pwr.h | 124 + .../devices/support/STM32F40x/rcc.c | 546 + .../devices/support/STM32F40x/rcc.h | 457 + .../devices/support/STM32F40x/rng.c | 251 + .../devices/support/STM32F40x/rng.h | 122 + .../devices/support/STM32F40x/rtc.c | 490 + .../devices/support/STM32F40x/rtc.h | 433 + .../devices/support/STM32F40x/sdio.c | 386 + .../devices/support/STM32F40x/sdio.h | 287 + .../devices/support/STM32F40x/spi1.c | 311 + .../devices/support/STM32F40x/spi1.h | 201 + .../devices/support/STM32F40x/syscfg.c | 275 + .../devices/support/STM32F40x/syscfg.h | 154 + .../devices/support/STM32F40x/tim1.c | 427 + .../devices/support/STM32F40x/tim1.h | 336 + .../devices/support/STM32F40x/tim10.c | 293 + .../devices/support/STM32F40x/tim10.h | 180 + .../devices/support/STM32F40x/tim11.c | 297 + .../devices/support/STM32F40x/tim11.h | 186 + .../devices/support/STM32F40x/tim2.c | 404 + .../devices/support/STM32F40x/tim2.h | 311 + .../devices/support/STM32F40x/tim3.c | 400 + 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gnu-mcu-eclipse/graphics/STM32-P103.jpg create mode 100644 gnu-mcu-eclipse/graphics/STM32-P107.jpg create mode 100644 gnu-mcu-eclipse/graphics/STM32F0-Discovery.jpg create mode 100644 gnu-mcu-eclipse/graphics/STM32F4-Discovery.jpg create mode 100644 gnu-mcu-eclipse/graphics/STM32F4-Discovery.png create mode 100644 gnu-mcu-eclipse/graphics/STM32F429I-Discovery.jpg create mode 100644 gnu-mcu-eclipse/graphics/high-res/STM32F0-Discovery-high.jpg diff --git a/gnu-mcu-eclipse/README.md b/gnu-mcu-eclipse/README.md new file mode 100644 index 0000000000..e4cb78451f --- /dev/null +++ b/gnu-mcu-eclipse/README.md @@ -0,0 +1,5 @@ +These are additional files added to **GNU MCU Eclipse QEMU**. + +- devices: JSON definitions of device peripherals +- graphics: board images +- develop: development notes & misc files diff --git a/gnu-mcu-eclipse/develop/CortexM.md b/gnu-mcu-eclipse/develop/CortexM.md new file mode 100644 index 0000000000..5d60447710 --- /dev/null +++ b/gnu-mcu-eclipse/develop/CortexM.md @@ -0,0 +1,23 @@ +The main purpose of the GNU ARM Eclipse QEMU was to improve Cortex-M support and provide a framework for adding new Cortex-M MCUs. + +The current Cortex-M support includes: + +## ARMv7-M + +The current emulation supports only Cortex-M3, with Cortex-M4 support to be added soon. FPU support will be added to a later date. + +## NVIC + +NVIC support is currently via the more generic GIC implementation. It is fully functional but it is not very accurate and in the future will probably require a rewrite. + +## SysTick + +SysTick is full functional. Currently it is included in the NVIC source file ad in the future will probably be moved to a separate file. + +## ITM + +The ITM currently implements only the stimulus port 0, used by trace streams. + +To simplify things, now the port starts as enabled, but a separate mechanism will be added in the future. + + diff --git a/gnu-mcu-eclipse/develop/Eclipse-formatter.xml b/gnu-mcu-eclipse/develop/Eclipse-formatter.xml new file mode 100644 index 0000000000..ab79c49228 --- /dev/null +++ b/gnu-mcu-eclipse/develop/Eclipse-formatter.xml @@ -0,0 +1,167 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gnu-mcu-eclipse/develop/STM32.md b/gnu-mcu-eclipse/develop/STM32.md new file mode 100644 index 0000000000..b331731dbe --- /dev/null +++ b/gnu-mcu-eclipse/develop/STM32.md @@ -0,0 +1,38 @@ +STM32 is the main Cortex-M family emulated by **GNU ARM Eclipse QEMU**, and as such, provides the most accurate emulation. + +Currently only the F1 family is implemented, but support for F4 and other families is provisioned, there are some switch case branches to be added. + +## RCC + +All RCC registers are present in the emulator, although some provide only limited functionality. + +The peripheral clock enable bits are not yet made available to peripherals. + +## GPIO + +Setting the Set/Reset bits is reflected in the ODR bits, so using the GPIO for output operations is functional, but the input bits are not linked to the output bits, nor interrupts are triggered. + +## FLASH + +The FLASH device is used during the CMSIS initialisation to configure some wait states, and as such is mandatory for the emulator. + +Using this device to reprogram the flash will be implemented at a later date, since it will require the flash region to be persistent. + +## PWR + +The PWR device is used during the CMSIS initialisation and as such it is mandatory for the emulator. + +## EXTI + +The EXTI device is used to route external interrupts to NVIC, and was added when support for the push buttons was needed. + +Support for events is currently not provided. + +## SYSCFG + +The SYSCFG device is used for devices rom the F4 family, among other things, to configure which GPIO bits are connected to EXTI interrupts. + +## USART + +Support for USART is currently experimental, and incomplete. + diff --git a/gnu-mcu-eclipse/develop/STYLE.md b/gnu-mcu-eclipse/develop/STYLE.md new file mode 100644 index 0000000000..d906159068 --- /dev/null +++ b/gnu-mcu-eclipse/develop/STYLE.md @@ -0,0 +1,45 @@ + +## C + +[QEMU Coding Style](http://git.qemu-project.org/?p=qemu.git;a=blob_plain;f=CODING_STYLE;hb=HEAD) + +- indents are four spaces +- tabs are never used +- lines are 80 characters +- variables are **lower\_case\_with\_underscores** +- structured type names are in **CamelCase** +- sScalar type names are **lower\_case\_with\_underscores\_ending\_with\_a\_t** +- declarations should be at the beginning of blocks (?!) + +Block structure: + + if (a == 5) { + printf("a was 5.\n"); + } else if (a == 6) { + printf("a was 6.\n"); + } else { + printf("a was something else entirely.\n"); + } + + void a_function(void) + { + do_something(); + } + +- suffix interrupt handlers with **\_irq\_handler** + - stm32\_gpio\_in\_irq\_handler +- suffix all other callback functions with **_callback** + - .class\_init = stm32\_gpio\_class\_init\_callback, + - .instance\_init = stm32\_gpio\_instance\_init\_callback, + - dc->reset = stm32\_gpio\_reset\_callback; + - dc->realize = stm32\_gpio\_realize\_callback; + - .read = stm32\_gpio\_read\_callback, + - .write = stm32\_gpio\_write\_callback, + + +## QOM (QEMU Object Model) + +[QOM Conventions](http://wiki.qemu.org/QOMConventions) + +- DO use names-separated-by-dashes + diff --git a/gnu-mcu-eclipse/develop/TODO.md b/gnu-mcu-eclipse/develop/TODO.md new file mode 100644 index 0000000000..77e537d6a6 --- /dev/null +++ b/gnu-mcu-eclipse/develop/TODO.md @@ -0,0 +1,41 @@ +# All + +- make the flash persistent (use a file to save at the end, if it was written) + +## System memory +- add flash size + - F1: 0x1FFFF7E0 + - F1: 0x1FFF7A22 +- add device ID + - F1: 1FFFF7E8 (12 bytes) + - F4: 1FFF7A10 (12 bytes) +- add content for System Memory + - F1: 0x1FFFF000-0x1FFFF7FF (2K) + - F4: 0x1FFF0000-0x1FFF77FF +- add Option bytes + +## NVIC + +Reimplement NVIC as a separate object + +## SysTick + +Move the SysTick code outside the NVIC source file. + +## ITM configuration + +Add a configuration mechanism to enable/disable ITM externally, and to configure the stimulus port enable bits. + +## ARMv6-M + +Add separate code to implement the simplified M0/M0+ (armv6m) excetion specifics. + + +# STM32 + +## RCC +- add an API to get access to the clock tree + +## GPIO +- check the peripheral clocks from RCC + diff --git a/gnu-mcu-eclipse/develop/irqs.md b/gnu-mcu-eclipse/develop/irqs.md new file mode 100644 index 0000000000..723d17dd96 --- /dev/null +++ b/gnu-mcu-eclipse/develop/irqs.md @@ -0,0 +1,139 @@ +# Interrupts + +QEMU uses a custom notification mechanism not only to emulate interrupts, but also to pass values from one object to another. + +This mechanism uses `TYPE_IRQ` objects to store the pointer of the interrupt handler. Arrays of such objects are allocated in the incoming end (like NVIC, for actual interrupts, but also other objects that are driven by values set in other parts, like LEDs, etc). + +The outgoing end of this mechanism uses plain pointers to `TYPE_IRQ` objects. + +This simple implementation has limitations, as oposed to usual observer pattern implementations, it is not possible to register any number of listeners to a single notifier; the application must keep separate pointers to different `TYPE_IRQ` objects and explicitly notify them all. + +## Interrupts as named properties of devices + +Althoug interrupts can be created and initialised separately, the recommended way is to create them as named properties associated to `TYPE_DEVICE` objects. The device DeviceState structure includes a list (sugestively named `gpios`) which includes elements of type NamedGPIOList, that basically have a name and a pointer to an array of `TYPE_IRQ` objects. + + +## Incoming + +Incoming interrupts are objects that process raise/lower actions invoked by other objects. + +To create an array of incoming interrupts in a device use `cm_irq_init_in()` in the instance init callback: + +``` +cm_irq_init_in(DEVICE(obj), xxx_irq_handler, "xxx-in", size); + +``` + +The names are arbitrary, but it is recommended to suffix incoming interrupts with `-in`. + +The handler function should have the following prototype: + +``` +static void gpio_led_irq_handler(void *opaque, int index, int level) +{ + // GPIOLEDState *state = GPIO_LED_STATE(opaque); + // ... +} +``` + + +## Outgoing + +Outgoing interrupts are not separate objects, but links to incoming interrupts. Multiple outgoing interrupts can point to the same incoming interrupt. + +Arrays of pointers to `TYPE_DEVICE` objects must be defined in the object state. + +``` +typedef struct { + qemu_irq out_irq[N]; +} XxxState; +``` + +To be able to conveniently address these arrays at global level, use `cm_irq_init_out()` in the instance init callback: + +``` +cm_irq_init_out(DEVICE(obj), &state->irq_out, "xxx-out", N); + +``` + +## Connect + +Each output interrupt must be individually and explicitly connected to its corresponding incoming interrupt. + +For example to connect the button to one GPIO pin, use something like this in the realize callback: + +``` +cm_irq_connect(DEVICE(button), IRQ_BUTTON_GPIO_OUT, 0, + DEVICE(gpio), IRQ_GPIO_IDR_IN, gpio_bit); +``` + +## Use + +Interrupts can be raised or lowered: + +``` +cm_irq_set(state->out_irq[i], condition ? 1 : 0); + +cm_irq_raise(state->out_irq[i]); +cm_irq_lower(state->out_irq[i]); +``` + +Generally each outgoing interrupt should be connected to one and only one incoming interrupt, with multiple outgoing interrupts being allowed to connect to the same incoming interrupt. + +For NVIC exception, each outgoing interrupt should be connected to one NVIC exception, and multiple outgoing interrupt can be connected to the same NVIC exception: + +``` +cm_irq_connect(dev, IRQ_EXTI_OUT, 5, nvic, IRQ_NVIC_IN, STM32F10X_MD_EXTI9_5_IRQn); +cm_irq_connect(dev, IRQ_EXTI_OUT, 6, nvic, IRQ_NVIC_IN, STM32F10X_MD_EXTI9_5_IRQn); +// ... +``` + +## Reset + +The entire outgoing array can be reset during the reset callback: + +``` +static void xxx_reset_callback(DeviceState *dev) +{ + int i; + XxxxState *state = XXX_STATE(dev); + + for (i = 0; i < N; i++) { + cm_irq_lower(state->out_irq[i]); + } +} +``` + +For regular devices this might be redundant, but for some devices, like active low buttons, the inactive value is 1, and must be explicitly set. + +``` +cm_irq_raise(button->out_irq); + +``` + +Note: for this to be effective, the button must be reset **after** the GPIO port. + + +## Core interrupt processing + +In `cpu-exec.c`, `cpu_exec()` prepares a `sigsetjmp()` context for exception handling. The context is restored by `cpu_loop_exit()`, called generally from from `raise_exception()`. + +Then checks `cpu_handle_exception()` and possibly `cpu_handle_interrupt()`. + +`cpu_handle_exception()` uses `cpu->exception_index` and possibly calls `cc->do_interrupt(cpu)`. + +`cpu_handle_interrupt()` calls `cc->cpu_exec_interrupt(cpu, interrupt_request)`, which is pointing to `arm_v7m_cpu_exec_interrupt()`. + + +## Pending an exception + +`cortexm_nvic_set_pending_exception()` + +`gic_set_pending_private()` checks if pending, and, if not sets it (`s->irq_state[irq].pending |= (cm)`), then calls `gic_update()`. + +`gic_update()` enumerates all `s->num_irq`, identifies the highest pending and calls `qemu_set_irq(s->parent_irq[cpu], irq_level)` which calls `arm_cpu_set_irq()`. + +## Pending an interrupt + +`cortexm_nvic_set_pending_interrupt()` + diff --git a/gnu-mcu-eclipse/develop/repos.md b/gnu-mcu-eclipse/develop/repos.md new file mode 100644 index 0000000000..a5e839ceb7 --- /dev/null +++ b/gnu-mcu-eclipse/develop/repos.md @@ -0,0 +1,32 @@ +## Repository URLs + +- the GNU ARM Eclipse git remote URL to clone from is + - `https://github.com/gnuarmeclipse/qemu.git` (remote *origin*) +- the QEMU git remote URL is + - `git://git.qemu-project.org/qemu.git` (remote *qemu*) + +From the remote *qemu*, pull its master → master, then push it to *origin*. + +## Update procedures + +### The gnuarmeclipse-dev branch + +To keep the development repository in sync with the original QEMU repository: + +- checkout `master` +- pull from `qemu/master` +- checkout `gnuarmeclipse-dev` +- merge `master` +- add a tag like `gae-2.3.0-201403261500-dev` after each public release + +### The gnuarmeclipse branch + +To keep the stable development in sync with the development branch: + +- checkout `gnuarmeclipse` +- merge `gnuarmeclipse-dev` +- add a tag like `gae-2.3.0-201403261500` after each public release + + + + diff --git a/gnu-mcu-eclipse/develop/templates/stm32-xxx.c b/gnu-mcu-eclipse/develop/templates/stm32-xxx.c new file mode 100644 index 0000000000..ab2fd3885a --- /dev/null +++ b/gnu-mcu-eclipse/develop/templates/stm32-xxx.c @@ -0,0 +1,273 @@ +/* + * STM32 MCU - XXX emulation. + * + * Copyright (c) 2015 Liviu Ionescu. + * Copyright (c) 2010 Andre Beckus. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "hw/misc/stm32-xxx.h" +#include + +/** + * This file implements the STM32 XXX. + * + * The initial implementation is intended only to pass CMSIS initialisations. + * + * References: + * - ST CD00171190.pdf, Doc ID 13902 Rev 15, "RM0008 Reference Manual, + * STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx + * advanced ARM®-based 32-bit MCUs" + * + * All STM32 reference manuals available from: + * http://www.st.com/stonline/stappl/resourceSelector/\ + * app?page=fullResourceSelector&doctype=reference_manual&FamilyID=141 + */ + + +/* ----- Private ----------------------------------------------------------- */ + + +/* STM32F1[LMHX]D, STM32F1CL */ + +/** + * STM32F1 read 32-bits. + */ +static uint32_t stm32f1_xxx_read32(STM32XxxState *state, uint32_t offset, + unsigned size) +{ + uint32_t value; + + switch (offset) { + case 0x00: + value = state->u.f1.reg.cr; + return value; + + default: + qemu_log_mask(LOG_UNIMP, + "XXX: Read of size %d at offset 0x%x not implemented\n", size, + offset); + break; + } + + return 0; +} + +/** + * STM32F1 write 32-bits. + */ +static void stm32f1_xxx_write32(STM32XxxState *state, uint32_t offset, + uint32_t value, unsigned size) +{ + uint32_t tmp; + + switch (offset) { + case 0x00: + state->u.f1.reg.cr = (value & 0xFFFFFFFF); + break; + + default: + qemu_log_mask(LOG_UNIMP, + "XXX: Write of size %d at offset 0x%x not implemented\n", size, + offset); + } +} + +/* ------------------------------------------------------------------------- */ + +static uint64_t stm32_xxx_read_callback(void *opaque, hwaddr addr, unsigned size) +{ + STM32XxxState *state = (STM32XxxState *) opaque; + uint32_t offset = addr; + + if (size != 4) { + qemu_log_mask(LOG_UNIMP, + "XXX: Read of size %d at offset 0x%x not implemented\n", size, + offset); + return 0; + } + + STM32Capabilities *capabilities = + STM32_SYS_BUS_DEVICE_STATE(state)->capabilities; + + switch (capabilities->stm32.family) { + case STM32_FAMILY_F1: + return stm32f1_xxx_read32(state, offset, size); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "XXX: Read of size %d at offset 0x%x for unknown family %d\n", + size, offset, capabilities->stm32.family); + } + + return 0; +} + +static void stm32_xxx_write_callback(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + STM32XxxState *state = (STM32XxxState *) opaque; + uint32_t offset = addr; + + if (size != 4) { + qemu_log_mask(LOG_UNIMP, + "XXX: Write of size %d at offset 0x%x not implemented\n", size, + offset); + return; + } + + STM32Capabilities *capabilities = + STM32_SYS_BUS_DEVICE_STATE(state)->capabilities; + + switch (capabilities->stm32.family) { + case STM32_FAMILY_F1: + stm32f1_xxx_write32(state, offset, value, size); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "RCC: Write of size %d at offset 0x%x for unknown family %d\n", + size, offset, capabilities->stm32.family); + } +} + +static const MemoryRegionOps stm32_xxx_ops = { + .read = stm32_xxx_read_callback, + .write = stm32_xxx_write_callback, + .endianness = DEVICE_NATIVE_ENDIAN, }; + +/* ------------------------------------------------------------------------- */ + +static PeripheralRegisterInfo stm32f1_flash_acr_info = { + .desc = "Flash access control register (FLASH_ACR)", + .offset = 0x00, + .reset_value = 0x00000030, + .readable_bits = 0x0000003F, + .writable_bits = 0x0000001F, + .bitfields = (RegisterBitfieldInfo[] ) { + { + .name = "latency", + .first_bit = 0, + .last_bit = 2 }, + { + .name = "hlfcya", + .desc = "Flash half cycle access enable", + .first_bit = 3 }, + { + .name = "prftbe", + .desc = "Prefetch buffer enable", + .first_bit = 4 }, + { + .name = "prftbs", + .desc = "Prefetch buffer status", + .first_bit = 5, + .reset_value = 1, + .mode = REGISTER_BITFIELD_MODE_READ, + .follows = "prftbe" }, + { }, /**/ + } , /**/ +}; + +/* ------------------------------------------------------------------------- */ + +static void stm32_xxx_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32XxxState *state = STM32_XXX_STATE(obj); + + /* ... */ +} + +static void stm32_xxx_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + /* Call parent realize(). */ + if (!cm_parent_realize(dev, errp, TYPE_STM32_XXX)) { + return; + } + + STM32XxxState *state = STM32_XXX_STATE(dev); + + STM32Capabilities *capabilities = + STM32_SYS_BUS_DEVICE_STATE(state)->capabilities; + assert(capabilities != NULL); + + uint64_t size; + hwaddr addr; + switch (capabilities->stm32.family) { + case STM32_FAMILY_F1: + size = 0x400; + addr = 0xE0000000; + + Object *reg; + reg = peripheral_register_new(obj, "acr", &stm32f1_flash_acr_info); + cm_object_realize(reg); + state->u.f1.reg.acr = DEVICE(reg); + + break; + default: + size = 0; /* This will trigger an assertion to fail */ + } + + memory_region_init_io(&state->mmio, OBJECT(dev), &stm32_gpio_ops, state, + "mmio", size); + + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &state->mmio); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + /* ... */ +} + +static void stm32_xxx_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + /* Call parent reset(). */ + cm_parent_reset(dev, TYPE_STM32_XXX); + + STM32XxxState *state = STM32_XXX_STATE(dev); + /* ... */ +} + +static void stm32_xxx_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_xxx_reset_callback; + dc->realize = stm32_xxx_realize_callback; + + STM32XxxClass *st_class = STM32_XXX_CLASS(klass); +} + +static const TypeInfo stm32_xxx_type_info = { + .name = TYPE_STM32_XXX, + .parent = TYPE_STM32_XXX_PARENT, + .instance_init = stm32_xxx_instance_init_callback, + .instance_size = sizeof(STM32XxxState), + .class_init = stm32_xxx_class_init_callback, + .class_size = sizeof(STM32XxxClass) }; + +static void stm32_xxx_register_types(void) +{ + type_register_static(&stm32_xxx_type_info); +} + +type_init(stm32_xxx_register_types); + +/* ------------------------------------------------------------------------- */ + diff --git a/gnu-mcu-eclipse/develop/templates/stm32-xxx.h b/gnu-mcu-eclipse/develop/templates/stm32-xxx.h new file mode 100644 index 0000000000..7c6eb850fc --- /dev/null +++ b/gnu-mcu-eclipse/develop/templates/stm32-xxx.h @@ -0,0 +1,89 @@ +/* + * STM32 MCU - XXX emulation. + * + * Copyright (c) 2015 Liviu Ionescu. + * Copyright (c) 2010 Andre Beckus. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + + +#ifndef STM32_XXX_H_ +#define STM32_XXX_H_ + +#include "qemu/osdep.h" + +#include "hw/sysbus.h" +#include "hw/misc/stm32-sys-bus-device.h" + +#include "exec/address-spaces.h" + +/* ------------------------------------------------------------------------- */ + +#define TYPE_STM32_XXX "stm32:xxx-peripheral" + +/* ------------------------------------------------------------------------- */ + +/* Parent definitions. */ +#define TYPE_STM32_XXX_PARENT TYPE_SYS_BUS_DEVICE +typedef STM32SysBusDeviceClass STM32XxxParentClass; +typedef STM32SysBusDeviceState STM32XxxParentState; + +/* ------------------------------------------------------------------------- */ + +/* Class definitions. */ +#define STM32_XXX_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32XxxClass, (obj), TYPE_STM32_XXX) +#define STM32_XXX_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32XxxClass, (klass), TYPE_STM32_XXX) + +typedef struct { + /*< private >*/ + STM32XxxParentClass parent_class; + /*< public >*/ + +} STM32XxxClass; + +/* ------------------------------------------------------------------------- */ + +/* Instance definitions. */ +#define STM32_XXX_STATE(obj) \ + OBJECT_CHECK(STM32XxxState, (obj), TYPE_STM32_XXX) + +typedef struct { + /*< private >*/ + STM32XxxParentState parent_obj; + /*< public >*/ + + MemoryRegion mmio; + + union { + struct { + /* F1 specific registers */ + struct { + Object *acr; + } reg; + } f1; + struct { + /* F4 specific registers */ + struct { + + } reg; + } f4; + } u; +} STM32XxxState; + +/* ------------------------------------------------------------------------- */ + +#endif /* STM32_XXX_H_ */ diff --git a/gnu-mcu-eclipse/devices/README.md b/gnu-mcu-eclipse/devices/README.md new file mode 100644 index 0000000000..8ecacce649 --- /dev/null +++ b/gnu-mcu-eclipse/devices/README.md @@ -0,0 +1,23 @@ +# Device definitions + +## Overview + +In **GNU ARM Eclipse QEMU**, the creation of the Cortex-M devices is entirely data driven by the definitions in these JSON files. + +The files were automatically generated from the original CMSIS SVD files and then slightly patched to better match the QEMU requirements. + +## Sub-family scope + +Groups of similar devices share common definitions; specific devices can differ only by other characteristics, like Flash or RAM size. + +The QEMU grouping reflects the vendor grouping, with one SVD file for each CMSIS sub-family. + +Please note that the peripherals defined in the CMSIS SVD files are for the largest sub-family member, and some smaller members may not provide all the peripherals listed in the SVD files, thus the need for the extra capabilities structures. + +## System peripherals + +Some vendors also provide definitions for some system devices in the SVD files (line NVIC in STM32 files). Because there is no guarantee that the register names and fields are kept consistent, these definitions are ignored and the system peripherals are created using separate definitions. + +## Data lifetime + +During MCU object creation, the JSON is parsed and kept in memory during the entire lifetime of the process. To simplify things, object may refer to strings in the parsed tree (this may be changed in a future version). diff --git a/gnu-mcu-eclipse/devices/STM32F0x1-qemu.json b/gnu-mcu-eclipse/devices/STM32F0x1-qemu.json new file mode 100644 index 0000000000..955528b093 --- /dev/null +++ b/gnu-mcu-eclipse/devices/STM32F0x1-qemu.json @@ -0,0 +1,30391 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F0x1.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.2", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x1.svd", + "--output", + "STM32F0x1-xsvd.json" + ], + "date": "2016-12-14T22:50:48.956Z" + }, + { + "tool": "xcdl", + "version": "1.6.8", + "command": [ + "svd-patch", + "--file", + "STM32F0x1-xsvd.json", + "--patch", + "STM32F0x1-patch.json", + "--output", + "../STM32F0x1-qemu.json", + "--remove", + "NVIC" + ], + "date": "2016-12-19T10:35:22.396Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F0x1", + "version": "1.0", + "description": "STM32F0x1", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADRDY", + "description": "ADC ready", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOSMP", + "description": "End of sampling flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "End of conversion flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOS", + "description": "End of sequence flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OVR", + "description": "ADC overrun", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADRDYIE", + "description": "ADC ready interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOSMPIE", + "description": "End of sampling flag interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "End of conversion interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOSIE", + "description": "End of conversion sequence interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADEN", + "description": "ADC enable command", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADDIS", + "description": "ADC disable command", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADSTART", + "description": "ADC start conversion command", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ADSTP", + "description": "ADC stop conversion command", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ADCAL", + "description": "ADC calibration", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAEN", + "description": "Direct memory access enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMACFG", + "description": "Direct memery access configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SCANDIR", + "description": "Scan sequence direction", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Data resolution", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External trigger selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "EXTEN", + "description": "External trigger enable and polarity selection", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OVRMOD", + "description": "Overrun management mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Single / continuous conversion mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AUTDLY", + "description": "Auto-delayed conversion mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AUTOFF", + "description": "Auto-off mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel or on all channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel selection", + "bitOffset": "26", + "bitWidth": "5" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00008000", + "fields": [ + { + "name": "JITOFF_D2", + "description": "JITOFF_D2", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "JITOFF_D4", + "description": "JITOFF_D4", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR", + "displayName": "SMPR", + "description": "Sampling time register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPR", + "description": "Sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "TR", + "displayName": "TR", + "description": "Watchdog threshold register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "CHSELR", + "displayName": "CHSELR", + "description": "Channel selection register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL0", + "description": "Channel-x selection", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHSEL1", + "description": "Channel-x selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHSEL2", + "description": "Channel-x selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CHSEL3", + "description": "Channel-x selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHSEL4", + "description": "Channel-x selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CHSEL5", + "description": "Channel-x selection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHSEL6", + "description": "Channel-x selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CHSEL7", + "description": "Channel-x selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CHSEL8", + "description": "Channel-x selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CHSEL9", + "description": "Channel-x selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHSEL10", + "description": "Channel-x selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CHSEL11", + "description": "Channel-x selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHSEL12", + "description": "Channel-x selection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CHSEL13", + "description": "Channel-x selection", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHSEL14", + "description": "Channel-x selection", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CHSEL15", + "description": "Channel-x selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CHSEL16", + "description": "Channel-x selection", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CHSEL17", + "description": "Channel-x selection", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHSEL18", + "description": "Channel-x selection", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Converted data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Common configuration register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VREFEN", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSEN", + "description": "Temperature sensor enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "VBATEN", + "description": "VBAT enable", + "bitOffset": "24", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_ESR", + "displayName": "CAN_ESR", + "description": "CAN_ESR", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "CAN_BTR", + "displayName": "CAN_BTR", + "description": "CAN BTR", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TI0R", + "displayName": "CAN_TI0R", + "description": "CAN_TI0R", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT0R", + "displayName": "CAN_TDT0R", + "description": "CAN_TDT0R", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL0R", + "displayName": "CAN_TDL0R", + "description": "CAN_TDL0R", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH0R", + "displayName": "CAN_TDH0R", + "description": "CAN_TDH0R", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI1R", + "displayName": "CAN_TI1R", + "description": "CAN_TI1R", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT1R", + "displayName": "CAN_TDT1R", + "description": "CAN_TDT1R", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL1R", + "displayName": "CAN_TDL1R", + "description": "CAN_TDL1R", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH1R", + "displayName": "CAN_TDH1R", + "description": "CAN_TDH1R", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI2R", + "displayName": "CAN_TI2R", + "description": "CAN_TI2R", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT2R", + "displayName": "CAN_TDT2R", + "description": "CAN_TDT2R", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL2R", + "displayName": "CAN_TDL2R", + "description": "CAN_TDL2R", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH2R", + "displayName": "CAN_TDH2R", + "description": "CAN_TDH2R", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI0R", + "displayName": "CAN_RI0R", + "description": "CAN_RI0R", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_RDT0R", + "displayName": "CAN_RDT0R", + "description": "CAN_RDT0R", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_RDL0R", + "displayName": "CAN_RDL0R", + "description": "CAN_RDL0R", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH0R", + "displayName": "CAN_RDH0R", + "description": "CAN_RDH0R", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI1R", + "displayName": "CAN_RI1R", + "description": "CAN_RI1R", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_RDT1R", + "displayName": "CAN_RDT1R", + "description": "CAN_RDT1R", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_RDL1R", + "displayName": "CAN_RDL1R", + "description": "CAN_RDL1R", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH1R", + "displayName": "CAN_RDH1R", + "description": "CAN_RDH1R", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_FMR", + "displayName": "CAN_FMR", + "description": "CAN_FMR", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CAN2SB", + "description": "CAN2SB", + "bitOffset": "8", + "bitWidth": "6" + } + ] + }, + { + "name": "CAN_FM1R", + "displayName": "CAN_FM1R", + "description": "CAN_FM1R", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FBM14", + "description": "Filter mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FS1R", + "displayName": "CAN_FS1R", + "description": "CAN_FS1R", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CEC", + "description": "HDMI-CEC controller", + "groupName": "CEC", + "baseAddress": "0x40007800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CEC_CAN", + "description": "CEC and CAN global interrupt", + "value": "30" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CECEN", + "description": "CEC Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXSOM", + "description": "Tx start of message", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXEOM", + "description": "Tx End Of Message", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OAR", + "description": "Own Address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LSTN", + "description": "Listen mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SFT", + "description": "Signal Free Time", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "RXTOL", + "description": "Rx-Tolerance", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BRESTP", + "description": "Rx-stop on bit rising error", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BREGEN", + "description": "Generate error-bit on bit rising error", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LBPEGEN", + "description": "Generate Error-Bit on Long Bit Period Error", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Tx data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXD", + "description": "Tx Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Rx Data Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDR", + "description": "CEC Rx Data Register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status Register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXBR", + "description": "Rx-Byte Received", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RXEND", + "description": "End Of Reception", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXOVR", + "description": "Rx-Overrun", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BRE", + "description": "Rx-Bit rising error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SBPE", + "description": "Rx-Short Bit period error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LBPE", + "description": "Rx-Long Bit Period Error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXACKE", + "description": "Rx-Missing Acknowledge", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ARBLST", + "description": "Arbitration Lost", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TXBR", + "description": "Tx-Byte Request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEND", + "description": "End of Transmission", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXUDR", + "description": "Tx-Buffer Underrun", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Tx-Error", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACKE", + "description": "Tx-Missing acknowledge error", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXBRIE", + "description": "Rx-Byte Received Interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RXENDIE", + "description": "End Of Reception Interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXOVRIE", + "description": "Rx-Buffer Overrun Interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BREIE", + "description": "Bit Rising Error Interrupt Enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SBPEIE", + "description": "Short Bit Period Error Interrupt Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LBPEIE", + "description": "Long Bit Period Error Interrupt Enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXACKIE", + "description": "Rx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ARBLSTIE", + "description": "Arbitration Lost Interrupt Enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TXBRIE", + "description": "Tx-Byte Request Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXENDIE", + "description": "Tx-End of message interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXUDRIE", + "description": "Tx-Underrun interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXERRIE", + "description": "Tx-Error Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACKIE", + "description": "Tx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "COMP", + "description": "Comparator", + "groupName": "COMP", + "baseAddress": "0x4001001C", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x5", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "Control and status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COMP1EN", + "description": "Comparator 1 enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1_INP_DAC", + "description": "COMP1_INP_DAC", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1MODE", + "description": "Comparator 1 mode", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1INSEL", + "description": "Comparator 1 inverting input selection", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1OUTSEL", + "description": "Comparator 1 output selection", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1POL", + "description": "Comparator 1 output polarity", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1HYST", + "description": "Comparator 1 hysteresis", + "bitOffset": "12", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1OUT", + "description": "Comparator 1 output", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP1LOCK", + "description": "Comparator 1 lock", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2EN", + "description": "Comparator 2 enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2MODE", + "description": "Comparator 2 mode", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2INSEL", + "description": "Comparator 2 inverting input selection", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "WNDWEN", + "description": "Window mode enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2OUTSEL", + "description": "Comparator 2 output selection", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP2POL", + "description": "Comparator 2 output polarity", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2HYST", + "description": "Comparator 2 hysteresis", + "bitOffset": "28", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2OUT", + "description": "Comparator 2 output", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP2LOCK", + "description": "Comparator 2 lock", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "Cyclic redundancy check calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data register bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "General-purpose 8-bit data register bits", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "POLYSIZE", + "description": "Polynomial size", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "REV_IN", + "description": "Reverse input data", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "REV_OUT", + "description": "Reverse output data", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "INIT", + "displayName": "INIT", + "description": "Initial CRC value", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "INIT", + "description": "Programmable initial CRC value", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "CRS", + "description": "Clock recovery system", + "groupName": "CRS", + "baseAddress": "0x40006C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "SYNCOKIE", + "description": "SYNC event OK interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SYNCWARNIE", + "description": "SYNC warning interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Synchronization or trimming error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ESYNCIE", + "description": "Expected SYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Frequency error counter enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AUTOTRIMEN", + "description": "Automatic trimming enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWSYNC", + "description": "Generate software SYNC event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TRIM", + "description": "HSI48 oscillator smooth trimming", + "bitOffset": "8", + "bitWidth": "6" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2022BB7F", + "fields": [ + { + "name": "RELOAD", + "description": "Counter reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FELIM", + "description": "Frequency error limit", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "SYNCDIV", + "description": "SYNC divider", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SYNCSRC", + "description": "SYNC signal source selection", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "SYNCPOL", + "description": "SYNC polarity selection", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYNCOKF", + "description": "SYNC event OK flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SYNCWARNF", + "description": "SYNC warning flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERRF", + "description": "Error flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ESYNCF", + "description": "Expected SYNC flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SYNCERR", + "description": "SYNC error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SYNCMISS", + "description": "SYNC missed", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TRIMOVF", + "description": "Trimming overflow or underflow", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FEDIR", + "description": "Frequency error direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FECAP", + "description": "Frequency error capture", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYNCOKC", + "description": "SYNC event OK clear flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SYNCWARNC", + "description": "SYNC warning clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERRC", + "description": "Error clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ESYNCC", + "description": "Expected SYNC clear flag", + "bitOffset": "3", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt and DAC underrun interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DBGMCU", + "description": "Debug support", + "groupName": "DBGMCU", + "baseAddress": "0x40015800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "MCU Device ID Code Register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "Device Identifier", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DIV_ID", + "description": "Division Identifier", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "REV_ID", + "description": "Revision Identifier", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Debug MCU Configuration Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_STOP", + "description": "Debug Stop Mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "Debug Standby Mode", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "APBLFZ", + "displayName": "APBLFZ", + "description": "APB Low Freeze Register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER2_STOP", + "description": "Debug Timer 2 stopped when Core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER3_STOP", + "description": "Debug Timer 3 stopped when Core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER6_STOP", + "description": "Debug Timer 6 stopped when Core is halted", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER14_STOP", + "description": "Debug Timer 14 stopped when Core is halted", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_RTC_STOP", + "description": "Debug RTC stopped when Core is halted", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "Debug Window Wachdog stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDG_STOP", + "description": "Debug Independent Wachdog stopped when Core is halted", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C1_SMBUS_TIMEOUT", + "description": "SMBUS timeout mode stopped when Core is halted", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APBHFZ", + "displayName": "APBHFZ", + "description": "APB High Freeze Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER1_STOP", + "description": "Debug Timer 1 stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER15_STO", + "description": "Debug Timer 15 stopped when Core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER16_STO", + "description": "Debug Timer 16 stopped when Core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER17_STO", + "description": "Debug Timer 17 stopped when Core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_CH1", + "description": "DMA1 channel 1 interrupt", + "value": "9" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "derivedFrom": "DMA1", + "baseAddress": "0x40020400", + "interrupts": [ + { + "name": "DMA1_CH2_3_DMA2_CH1_2", + "description": "DMA1 channel 2 and 3 and DMA2 channel 1 and 2 interrupt", + "value": "10" + }, + { + "name": "DMA1_CH4_5_6_7_DMA2_CH3_4_5", + "description": "DMA1 channel 4, 5, 6 and 7 and DMA2 channel 3, 4 and 5 interrupts", + "value": "11" + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD and VDDIO2 supply comparator interrupt", + "value": "1" + }, + { + "name": "EXTI0_1", + "description": "EXTI Line[1:0] interrupts", + "value": "5" + }, + { + "name": "EXTI2_3", + "description": "EXTI Line[3:2] interrupts", + "value": "6" + }, + { + "name": "EXTI4_15", + "description": "EXTI Line15 and EXTI4 interrupts", + "value": "7" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0F940000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Interrupt Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Interrupt Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Interrupt Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Interrupt Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Interrupt Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Event Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Event Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Event Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Event Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Event Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word" + }, + { + "name": "Flash", + "description": "Flash", + "groupName": "Flash", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "3" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "LATENCY", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "PRFTBE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "PRFTBS", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FKEYR", + "description": "Flash Key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEYR", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Flash status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRT", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Flash control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FORCE_OPTLOAD", + "description": "Force option byte loading", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFF2", + "fields": [ + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LEVEL1_PROT", + "description": "Level 1 protection status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LEVEL2_PROT", + "description": "Level 2 protection status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BOOT1", + "description": "BOOT1", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "VDDA_MONITOR", + "description": "VDDA_MONITOR", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "Data1", + "description": "Data1", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x28000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000400", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000800", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000C00", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOF", + "baseAddress": "0x48001000", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48001400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bit 15", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "I2C1", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1", + "description": "I2C1 global interrupt", + "value": "23" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXIE", + "description": "TX Interrupt enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXIE", + "description": "RX Interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADDRIE", + "description": "Address match interrupt enable (slave only)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NACKIE", + "description": "Not acknowledge received interrupt enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "STOPIE", + "description": "STOP detection Interrupt enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TCIE", + "description": "Transfer Complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRIE", + "description": "Error interrupts enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DNF", + "description": "Digital noise filter", + "bitOffset": "8", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "ANFOFF", + "description": "Analog noise filter OFF", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "13", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXDMAEN", + "description": "DMA transmission requests enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXDMAEN", + "description": "DMA reception requests enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SBC", + "description": "Slave byte control", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUPEN", + "description": "Wakeup from STOP enable", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GCEN", + "description": "General call enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBHEN", + "description": "SMBus Host address enable", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBDEN", + "description": "SMBus Device Default address enable", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALERTEN", + "description": "SMBUS alert enable", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECEN", + "description": "PEC enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SADD0", + "description": "Slave address bit 0 (master mode)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SADD1", + "description": "Slave address bit 7:1 (master mode)", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "SADD8", + "description": "Slave address bit 9:8 (master mode)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "RD_WRN", + "description": "Transfer direction (master mode)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "10-bit addressing mode (master mode)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HEAD10R", + "description": "10-bit address header only read direction (master receiver mode)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation (master mode)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "NACK generation (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NBYTES", + "description": "Number of bytes", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "RELOAD", + "description": "NBYTES reload mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AUTOEND", + "description": "Automatic end mode (master mode)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "PECBYTE", + "description": "Packet error checking byte", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA1_0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OA1_1", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA1_8", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OA1MODE", + "description": "Own Address 1 10-bit mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OA1EN", + "description": "Own Address 1 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA2MSK", + "description": "Own Address 2 masks", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "OA2EN", + "description": "Own Address 2 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TIMINGR", + "displayName": "TIMINGR", + "description": "Timing register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SCLL", + "description": "SCL low period (master mode)", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "SCLH", + "description": "SCL high period (master mode)", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "SDADEL", + "description": "Data hold time", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "SCLDEL", + "description": "Data setup time", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "PRESC", + "description": "Timing prescaler", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "TIMEOUTR", + "displayName": "TIMEOUTR", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIMEOUTA", + "description": "Bus timeout A", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "TIDLE", + "description": "Idle clock timeout detection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIMOUTEN", + "description": "Clock timeout enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIMEOUTB", + "description": "Bus timeout B", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "TEXTEN", + "description": "Extended clock timeout enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000001", + "fields": [ + { + "name": "TXE", + "description": "Transmit data register empty (transmitters)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXIS", + "description": "Transmit interrupt status (transmitters)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Receive data register not empty (receivers)", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address matched (slave mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NACKF", + "description": "Not acknowledge received flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transfer Complete (master mode)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCR", + "description": "Transfer Complete Reload", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ARLO", + "description": "Arbitration lost", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun/Underrun (slave mode)", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIMEOUT", + "description": "Timeout or t_low detection flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Transfer direction (Slave mode)", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDCODE", + "description": "Address match code (Slave mode)", + "bitOffset": "17", + "bitWidth": "7", + "access": "read-only" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADDRCF", + "description": "Address Matched flag clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACKCF", + "description": "Not Acknowledge flag clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STOPCF", + "description": "Stop detection flag clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BERRCF", + "description": "Bus error flag clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ARLOCF", + "description": "Arbitration lost flag clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OVRCF", + "description": "Overrun/Underrun flag clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PECCF", + "description": "PEC Error flag clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIMOUTCF", + "description": "Timeout detection flag clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALERTCF", + "description": "Alert flag clear", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "PECR", + "displayName": "PECR", + "description": "PEC register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PEC", + "description": "Packet error checking register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDATA", + "description": "8-bit receive data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXDATA", + "description": "8-bit transmit data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2", + "description": "I2C2 global interrupt", + "value": "24" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WVU", + "description": "Watchdog counter window value update", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "WINR", + "displayName": "WINR", + "description": "Window register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "WIN", + "description": "Watchdog counter window value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "VREFINTRDY", + "description": "VREFINT reference voltage ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP1", + "description": "Enable WKUP pin 1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP2", + "description": "Enable WKUP pin 2", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP3", + "description": "Enable WKUP pin 3", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP4", + "description": "Enable WKUP pin 4", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP5", + "description": "Enable WKUP pin 5", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP6", + "description": "Enable WKUP pin 6", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP7", + "description": "Enable WKUP pin 7", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP8", + "description": "Enable WKUP pin 8", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL input clock source", + "bitOffset": "15", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCOPRE", + "description": "Microcontroller Clock Output Prescaler", + "bitOffset": "28", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PLLNODIV", + "description": "PLL clock not divided for MCO", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14RDYF", + "description": "HSI14 ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48RDYF", + "description": "HSI48 ready interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDYE", + "description": "HSI14 ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDYIE", + "description": "HSI48 ready interrupt enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI14RDYC", + "description": "HSI 14 MHz Ready Interrupt Clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI48RDYC", + "description": "HSI48 Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGRST", + "description": "SYSCFG and COMP reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15RST", + "description": "TIM15 timer reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16RST", + "description": "TIM16 timer reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17RST", + "description": "TIM17 timer reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCURST", + "description": "Debug MCU reset", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 timer reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "Timer 14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4RST", + "description": "USART4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART5RST", + "description": "USART5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANRST", + "description": "CAN interface reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSRST", + "description": "Clock Recovery System interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECRST", + "description": "HDMI CEC reset", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFEN", + "description": "I/O port F clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCEN", + "description": "Touch sensing controller clock enable", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGEN", + "description": "SYSCFG clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCEN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15EN", + "description": "TIM15 timer clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16EN", + "description": "TIM16 timer clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17EN", + "description": "TIM17 timer clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCUEN", + "description": "MCU debug module clock enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 timer clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "Timer 14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4EN", + "description": "USART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART5EN", + "description": "USART5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANEN", + "description": "CAN interface clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSEN", + "description": "Clock Recovery System interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECEN", + "description": "HDMI CEC interface clock enable", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSEDRV", + "description": "LSE oscillator drive capability", + "bitOffset": "3", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OBLRSTF", + "description": "Option byte loader reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "AHBRSTR", + "displayName": "AHBRSTR", + "description": "AHB peripheral reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IOPARST", + "description": "I/O port A reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "I/O port B reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "I/O port C reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "I/O port D reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFRST", + "description": "I/O port F reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCRST", + "description": "Touch sensing controller reset", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Clock configuration register 2", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PREDIV", + "description": "PREDIV division factor", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR3", + "displayName": "CFGR3", + "description": "Clock configuration register 3", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "USART1SW", + "description": "USART1 clock source selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "I2C1SW", + "description": "I2C1 clock source selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CECSW", + "description": "HDMI CEC clock source selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "USBSW", + "description": "USB clock source selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ADCSW", + "description": "ADC clock source selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART2SW", + "description": "USART2 clock source selection", + "bitOffset": "16", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Clock control register 2", + "addressOffset": "0x34", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "HSI14ON", + "description": "HSI14 clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDY", + "description": "HR14 clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14DIS", + "description": "HSI14 clock request from ADC disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14TRIM", + "description": "HSI14 clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSI14CAL", + "description": "HSI14 clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSI48ON", + "description": "HSI48 clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDY", + "description": "HSI48 clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48CAL", + "description": "HSI48 factory clock calibration", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC interrupts", + "value": "2" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REFCKON", + "description": "RTC_REFIN reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BYPSHAD", + "description": "Bypass the shadow registers", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSE", + "description": "Timestamp enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COSEL", + "description": "Calibration output selection", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "RTC_TAMP1 detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "RTC_TAMP2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format.", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format.", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "ADD1S", + "description": "Reserved", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Timestamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Timestamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Time-stamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + }, + { + "name": "CALW16", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALP", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TAMP1E", + "description": "RTC_TAMP1 input detection enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for RTC_TAMP1 input", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "RTC_TAMP2 input detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMP2_TRG", + "description": "Active level for RTC_TAMP2 input", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPFLT", + "description": "RTC_TAMPx filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMP_PRCH", + "description": "RTC_TAMPx precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMP_PUDIS", + "description": "RTC_TAMPx pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PC13VALUE", + "description": "RTC_ALARM output type/PC13 value", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PC13MODE", + "description": "PC13 mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PC14VALUE", + "description": "PC14 value", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PC14MODE", + "description": "PC14 mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PC15VALUE", + "description": "PC15 value", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PC15MODE", + "description": "PC15 mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1_global_interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "NSSP", + "description": "NSS pulse management", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "FRXTH", + "description": "FIFO reception threshold", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LDMA_RX", + "description": "Last DMA transfer for reception", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LDMA_TX", + "description": "Last DMA transfer for transmission", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FRLVL", + "description": "FIFO reception level", + "bitOffset": "9", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FTLVL", + "description": "FIFO transmission level", + "bitOffset": "11", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000010", + "fields": [ + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "26" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1D", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "Memory mapping selection bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ADC_DMA_RMP", + "description": "ADC DMA remapping bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART1_TX_DMA_RMP", + "description": "USART1_TX DMA remapping bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "USART1_RX_DMA_RMP", + "description": "USART1_RX DMA request remapping bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM16_DMA_RMP", + "description": "TIM16 DMA request remapping bit", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM17_DMA_RMP", + "description": "TIM17 DMA request remapping bit", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C_PB6_FM", + "description": "Fast Mode Plus (FM plus) driving capability activation bits.", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2C_PB7_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2C_PB8_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "I2C_PB9_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1_FM_plus", + "description": "FM+ driving capability activation for I2C1", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C2_FM_plus", + "description": "FM+ driving capability activation for I2C2", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SPI2_DMA_RMP", + "description": "SPI2 DMA request remapping bit", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "USART2_DMA_RMP", + "description": "USART2 DMA request remapping bit", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "USART3_DMA_RMP", + "description": "USART3 DMA request remapping bit", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "I2C1_DMA_RMP", + "description": "I2C1 DMA request remapping bit", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "TIM1_DMA_RMP", + "description": "TIM1 DMA request remapping bit", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "TIM2_DMA_RMP", + "description": "TIM2 DMA request remapping bit", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "TIM3_DMA_RMP", + "description": "TIM3 DMA request remapping bit", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI 0 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI 1 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI 2 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI 3 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI 4 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI 5 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI 6 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI 7 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI 8 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI 9 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI 10 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI 11 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI 12 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI 13 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI 14 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI 15 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LOCUP_LOCK", + "description": "Cortex-M0 LOCKUP bit enable bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SRAM_PARITY_LOCK", + "description": "SRAM parity lock bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PVD_LOCK", + "description": "PVD lock enable bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRAM_PEF", + "description": "SRAM parity flag", + "bitOffset": "8", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_UP_TRG_COM", + "description": "TIM1 break, update, trigger and commutation interrupt", + "value": "13" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "14" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM14", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40002000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM14", + "description": "TIM14 global interrupt", + "value": "19" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Timer input 1 remap", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM15", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM15", + "description": "TIM15 global interrupt", + "value": "20" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM16", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM16", + "description": "TIM16 global interrupt", + "value": "21" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM17", + "derivedFrom": "TIM16", + "baseAddress": "0x40014800", + "interrupts": [ + { + "name": "TIM17", + "description": "TIM17 global interrupt", + "value": "22" + } + ] + }, + { + "name": "TIM2", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "15" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAR", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "16" + } + ] + }, + { + "name": "TIM6", + "description": "Basic-timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "18" + } + ] + }, + { + "name": "TSC", + "description": "Touch sensing controller", + "groupName": "TSC", + "baseAddress": "0x40024000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TSC", + "description": "Touch sensing interrupt", + "value": "8" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSCE", + "description": "Touch sensing controller enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start a new acquisition", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AM", + "description": "Acquisition mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCPOL", + "description": "Synchronization pin polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IODEF", + "description": "I/O Default mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCV", + "description": "Max count value", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PGPSC", + "description": "Pulse generator prescaler", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SSPSC", + "description": "Spread spectrum prescaler", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SSE", + "description": "Spread spectrum enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SSD", + "description": "Spread spectrum deviation", + "bitOffset": "17", + "bitWidth": "7" + }, + { + "name": "CTPL", + "description": "Charge transfer pulse low", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CTPH", + "description": "Charge transfer pulse high", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOAIE", + "description": "End of acquisition interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MCEIE", + "description": "Max count error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOAIC", + "description": "End of acquisition interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MCEIC", + "description": "Max count error interrupt clear", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOAF", + "description": "End of acquisition flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MCEF", + "description": "Max count error flag", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "IOHCR", + "displayName": "IOHCR", + "description": "I/O hysteresis control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOASCR", + "displayName": "IOASCR", + "description": "I/O analog switch control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 analog switch enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 analog switch enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 analog switch enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 analog switch enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 analog switch enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 analog switch enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 analog switch enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 analog switch enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 analog switch enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 analog switch enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 analog switch enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 analog switch enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 analog switch enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 analog switch enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 analog switch enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 analog switch enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 analog switch enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 analog switch enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 analog switch enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 analog switch enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 analog switch enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 analog switch enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 analog switch enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 analog switch enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOSCR", + "displayName": "IOSCR", + "description": "I/O sampling control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 sampling mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 sampling mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 sampling mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 sampling mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 sampling mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 sampling mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 sampling mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 sampling mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 sampling mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 sampling mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 sampling mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 sampling mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 sampling mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 sampling mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 sampling mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 sampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 sampling mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 sampling mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 sampling mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 sampling mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 sampling mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 sampling mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 sampling mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 sampling mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOCCR", + "displayName": "IOCCR", + "description": "I/O channel control register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 channel mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 channel mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 channel mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 channel mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 channel mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 channel mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 channel mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 channel mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 channel mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 channel mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 channel mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 channel mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 channel mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 channel mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 channel mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 channel mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 channel mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 channel mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 channel mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 channel mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 channel mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 channel mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 channel mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 channel mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOGCSR", + "displayName": "IOGCSR", + "description": "I/O group control status register", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1E", + "description": "Analog I/O group x enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G2E", + "description": "Analog I/O group x enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G3E", + "description": "Analog I/O group x enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G4E", + "description": "Analog I/O group x enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G5E", + "description": "Analog I/O group x enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G6E", + "description": "Analog I/O group x enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G7E", + "description": "Analog I/O group x enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G8E", + "description": "Analog I/O group x enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G1S", + "description": "Analog I/O group x status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G2S", + "description": "Analog I/O group x status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G3S", + "description": "Analog I/O group x status", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G4S", + "description": "Analog I/O group x status", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G5S", + "description": "Analog I/O group x status", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G6S", + "description": "Analog I/O group x status", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G7S", + "description": "Analog I/O group x status", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G8S", + "description": "Analog I/O group x status", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "IOG1CR", + "displayName": "IOG1CR", + "description": "I/O group x counter register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG2CR", + "displayName": "IOG2CR", + "description": "I/O group x counter register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG3CR", + "displayName": "IOG3CR", + "description": "I/O group x counter register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG4CR", + "displayName": "IOG4CR", + "description": "I/O group x counter register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG5CR", + "displayName": "IOG5CR", + "description": "I/O group x counter register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG6CR", + "displayName": "IOG6CR", + "description": "I/O group x counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UE", + "description": "USART enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UESM", + "description": "USART enable in Stop mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Receiver wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MME", + "description": "Mute mode enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CMIE", + "description": "Character match interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DEDT", + "description": "Driver Enable deassertion time", + "bitOffset": "16", + "bitWidth": "5" + }, + { + "name": "DEAT", + "description": "Driver Enable assertion time", + "bitOffset": "21", + "bitWidth": "5" + }, + { + "name": "RTOIE", + "description": "Receiver timeout interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "EOBIE", + "description": "End of Block interrupt enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "M1", + "description": "Word length", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADDM7", + "description": "7-bit Address Detection/4-bit Address Detection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "LIN break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWAP", + "description": "Swap TX/RX pins", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "RXINV", + "description": "RX pin active level inversion", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TXINV", + "description": "TX pin active level inversion", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DATAINV", + "description": "Binary data inversion", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MSBFIRST", + "description": "Most significant bit first", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ABREN", + "description": "Auto baud rate enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "ABRMOD", + "description": "Auto baud rate mode", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "RTOEN", + "description": "Receiver timeout enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ADD0", + "description": "Address of the USART node", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ADD4", + "description": "Address of the USART node", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OVRDIS", + "description": "Overrun Disable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DDRE", + "description": "DMA Disable on Reception Error", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DEM", + "description": "Driver enable mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DEP", + "description": "Driver enable polarity selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SCARCNT", + "description": "Smartcard auto-retry count", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "WUS", + "description": "Wakeup from Stop mode interrupt flag selection", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "WUFIE", + "description": "Wakeup from Stop mode interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "RTOR", + "displayName": "RTOR", + "description": "Receiver timeout register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RTO", + "description": "Receiver timeout value", + "bitOffset": "0", + "bitWidth": "24" + }, + { + "name": "BLEN", + "description": "Block Length", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RQR", + "displayName": "RQR", + "description": "Request register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ABRRQ", + "description": "Auto baud rate request", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SBKRQ", + "description": "Send break request", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MMRQ", + "description": "Mute mode request", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RXFRQ", + "description": "Receive data flush request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFRQ", + "description": "Transmit data flush request", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt & status register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00C0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLE", + "description": "Idle line detected", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LBDF", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSIF", + "description": "CTS interrupt flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "RTOF", + "description": "Receiver timeout", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "EOBF", + "description": "End of block flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ABRE", + "description": "Auto baud rate error", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ABRF", + "description": "Auto baud rate flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Busy flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CMF", + "description": "Character match flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SBKF", + "description": "Send break flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup from Mute mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "WUF", + "description": "Wakeup from Stop mode flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEACK", + "description": "Transmit enable acknowledge flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "REACK", + "description": "Receive enable acknowledge flag", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PECF", + "description": "Parity error clear flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FECF", + "description": "Framing error clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "NCF", + "description": "Noise detected clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ORECF", + "description": "Overrun error clear flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLECF", + "description": "Idle line detected clear flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCCF", + "description": "Transmission complete clear flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDCF", + "description": "LIN break detection clear flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSCF", + "description": "CTS clear flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTOCF", + "description": "Receiver timeout clear flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "EOBCF", + "description": "End of timeout clear flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMCF", + "description": "Character match clear flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WUCF", + "description": "Wakeup from Stop mode clear flag", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "RDR", + "displayName": "RDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RDR", + "description": "Receive data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TDR", + "displayName": "TDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDR", + "description": "Transmit data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "28" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART4", + "derivedFrom": "USART1", + "baseAddress": "0x40004C00", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART5", + "derivedFrom": "USART1", + "baseAddress": "0x40005000", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART6", + "derivedFrom": "USART1", + "baseAddress": "0x40011400", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART7", + "derivedFrom": "USART1", + "baseAddress": "0x40011800", + "interrupts": [ + { + "name": "USART3_4_5_6_7_8", + "description": "USART3, USART4, USART5, USART6, USART7, USART8 global interrupt", + "value": "29" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART8", + "derivedFrom": "USART1", + "baseAddress": "0x40011C00", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USB", + "description": "Universal serial bus full-speed device interface", + "groupName": "USB", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USB", + "description": "USB global interrupt", + "value": "31" + } + ], + "registers": [ + { + "name": "EP0R", + "displayName": "EP0R", + "description": "Endpoint 0 register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP1R", + "displayName": "EP1R", + "description": "Endpoint 1 register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP2R", + "displayName": "EP2R", + "description": "Endpoint 2 register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP3R", + "displayName": "EP3R", + "description": "Endpoint 3 register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP4R", + "displayName": "EP4R", + "description": "Endpoint 4 register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP5R", + "displayName": "EP5R", + "description": "Endpoint 5 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP6R", + "displayName": "EP6R", + "description": "Endpoint 6 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP7R", + "displayName": "EP7R", + "description": "Endpoint 7 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNTR", + "displayName": "CNTR", + "description": "Control register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000003", + "fields": [ + { + "name": "FRES", + "description": "Force USB Reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDWN", + "description": "Power down", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPMODE", + "description": "Low-power mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSUSP", + "description": "Force suspend", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RESUME", + "description": "Resume request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "L1RESUME", + "description": "LPM L1 Resume request", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "L1REQM", + "description": "LPM L1 state request interrupt mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ESOFM", + "description": "Expected start of frame interrupt mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOFM", + "description": "Start of frame interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESETM", + "description": "USB reset interrupt mask", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSPM", + "description": "Suspend mode interrupt mask", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUPM", + "description": "Wakeup interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRM", + "description": "Error interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVRM", + "description": "Packet memory area over / underrun interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTRM", + "description": "Correct transfer interrupt mask", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ISTR", + "displayName": "ISTR", + "description": "Interrupt status register", + "addressOffset": "0x44", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EP_ID", + "description": "Endpoint Identifier", + "bitOffset": "0", + "bitWidth": "4", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Direction of transaction", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "L1REQ", + "description": "LPM L1 state request", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESOF", + "description": "Expected start frame", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RESET", + "description": "Reset request", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SUSP", + "description": "Suspend mode request", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUP", + "description": "Wakeup", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERR", + "description": "Error", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PMAOVR", + "description": "Packet memory area over / underrun", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTR", + "description": "Correct transfer", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FNR", + "displayName": "FNR", + "description": "Frame number register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FN", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "LSOF", + "description": "Lost SOF", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "LCK", + "description": "Locked", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "RXDM", + "description": "Receive data - line status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXDP", + "description": "Receive data + line status", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DADDR", + "displayName": "DADDR", + "description": "Device address", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Device address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "EF", + "description": "Enable function", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "BTABLE", + "displayName": "BTABLE", + "description": "Buffer table address", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BTABLE", + "description": "Buffer table", + "bitOffset": "3", + "bitWidth": "13" + } + ] + }, + { + "name": "LPMCSR", + "displayName": "LPMCSR", + "description": "LPM control and status register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "LPMEN", + "description": "LPM support enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPMACK", + "description": "LPM Token acknowledge enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REMWAKE", + "description": "BRemoteWake value", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BESL", + "description": "BESL value", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-only" + } + ] + }, + { + "name": "BCDR", + "displayName": "BCDR", + "description": "Battery charging detector", + "addressOffset": "0x58", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "BCDEN", + "description": "Battery charging detector (BCD) enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDEN", + "description": "Data contact detection (DCD) mode enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PDEN", + "description": "Primary detection (PD) mode enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDEN", + "description": "Secondary detection (SD) mode enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDET", + "description": "Data contact detection (DCD) status", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PDET", + "description": "Primary detection (PD) status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SDET", + "description": "Secondary detection (SD) status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PS2DET", + "description": "DM pull-up detection status", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DPPU", + "description": "DP pull-up control", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "T", + "description": "7-bit counter", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + } + ], + "cpu": { + "name": "CM0", + "revision": "r0p0", + "endian": "little", + "mpuPresent": "false", + "fpuPresent": "false", + "nvicPrioBits": "2", + "deviceNumInterrupts": "31", + "vendorSystickConfig": "false", + "qemuItmPresent": false + }, + "qemuAlignment": "any" + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/STM32F0x2-qemu.json b/gnu-mcu-eclipse/devices/STM32F0x2-qemu.json new file mode 100644 index 0000000000..acfa96e387 --- /dev/null +++ b/gnu-mcu-eclipse/devices/STM32F0x2-qemu.json @@ -0,0 +1,30327 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F0x2.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.11", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x2.svd", + "--output", + "STM32F0x2-xsvd.json" + ], + "date": "2017-01-30T20:41:59.999Z" + }, + { + "tool": "xcdl", + "version": "1.6.11", + "command": [ + "svd-patch", + "--file", + "STM32F0x2-xsvd.json", + "--patch", + "STM32F0x2-patch.json", + "--output", + "../STM32F0x2-qemu.json", + "--remove", + "NVIC" + ], + "date": "2017-01-30T20:42:05.020Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F0x2", + "version": "1.0", + "description": "STM32F0x2", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADRDY", + "description": "ADC ready", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOSMP", + "description": "End of sampling flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "End of conversion flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOS", + "description": "End of sequence flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OVR", + "description": "ADC overrun", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADRDYIE", + "description": "ADC ready interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOSMPIE", + "description": "End of sampling flag interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "End of conversion interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOSIE", + "description": "End of conversion sequence interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADEN", + "description": "ADC enable command", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADDIS", + "description": "ADC disable command", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADSTART", + "description": "ADC start conversion command", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ADSTP", + "description": "ADC stop conversion command", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ADCAL", + "description": "ADC calibration", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAEN", + "description": "Direct memory access enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMACFG", + "description": "Direct memery access configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SCANDIR", + "description": "Scan sequence direction", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Data resolution", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External trigger selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "EXTEN", + "description": "External trigger enable and polarity selection", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OVRMOD", + "description": "Overrun management mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Single / continuous conversion mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AUTDLY", + "description": "Auto-delayed conversion mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AUTOFF", + "description": "Auto-off mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel or on all channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel selection", + "bitOffset": "26", + "bitWidth": "5" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00008000", + "fields": [ + { + "name": "JITOFF_D2", + "description": "JITOFF_D2", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "JITOFF_D4", + "description": "JITOFF_D4", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR", + "displayName": "SMPR", + "description": "Sampling time register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPR", + "description": "Sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "TR", + "displayName": "TR", + "description": "Watchdog threshold register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "CHSELR", + "displayName": "CHSELR", + "description": "Channel selection register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL0", + "description": "Channel-x selection", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHSEL1", + "description": "Channel-x selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHSEL2", + "description": "Channel-x selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CHSEL3", + "description": "Channel-x selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHSEL4", + "description": "Channel-x selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CHSEL5", + "description": "Channel-x selection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHSEL6", + "description": "Channel-x selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CHSEL7", + "description": "Channel-x selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CHSEL8", + "description": "Channel-x selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CHSEL9", + "description": "Channel-x selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHSEL10", + "description": "Channel-x selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CHSEL11", + "description": "Channel-x selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHSEL12", + "description": "Channel-x selection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CHSEL13", + "description": "Channel-x selection", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHSEL14", + "description": "Channel-x selection", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CHSEL15", + "description": "Channel-x selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CHSEL16", + "description": "Channel-x selection", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CHSEL17", + "description": "Channel-x selection", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHSEL18", + "description": "Channel-x selection", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Converted data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Common configuration register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VREFEN", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSEN", + "description": "Temperature sensor enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "VBATEN", + "description": "VBAT enable", + "bitOffset": "24", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" 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"name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "CAN_BTR", + "displayName": "CAN_BTR", + "description": "CAN BTR", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": 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"1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CEC", + "description": "HDMI-CEC controller", + "groupName": "CEC", + "baseAddress": "0x40007800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CEC_CAN", + "description": "CEC and CAN global interrupt", + "value": "30" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CECEN", + "description": "CEC Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXSOM", + "description": "Tx start of message", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXEOM", + "description": "Tx End Of Message", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OAR", + "description": "Own Address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LSTN", + "description": "Listen mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SFT", + "description": "Signal Free Time", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "RXTOL", + "description": "Rx-Tolerance", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BRESTP", + "description": "Rx-stop on bit rising error", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BREGEN", + "description": "Generate error-bit on bit rising error", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LBPEGEN", + "description": "Generate Error-Bit on Long Bit Period Error", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Tx data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXD", + "description": "Tx Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Rx Data Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDR", + "description": "CEC Rx Data Register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status Register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXBR", + "description": "Rx-Byte Received", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RXEND", + "description": "End Of Reception", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXOVR", + "description": "Rx-Overrun", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BRE", + "description": "Rx-Bit rising error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SBPE", + "description": "Rx-Short Bit period error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LBPE", + "description": "Rx-Long Bit Period Error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXACKE", + "description": "Rx-Missing Acknowledge", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ARBLST", + "description": "Arbitration Lost", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TXBR", + "description": "Tx-Byte Request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEND", + "description": "End of Transmission", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXUDR", + "description": "Tx-Buffer Underrun", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Tx-Error", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACKE", + "description": "Tx-Missing acknowledge error", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXBRIE", + "description": "Rx-Byte Received Interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RXENDIE", + "description": "End Of Reception Interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXOVRIE", + "description": "Rx-Buffer Overrun Interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BREIE", + "description": "Bit Rising Error Interrupt Enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SBPEIE", + "description": "Short Bit Period Error Interrupt Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LBPEIE", + "description": "Long Bit Period Error Interrupt Enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXACKIE", + "description": "Rx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ARBLSTIE", + "description": "Arbitration Lost Interrupt Enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TXBRIE", + "description": "Tx-Byte Request Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXENDIE", + "description": "Tx-End of message interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXUDRIE", + "description": "Tx-Underrun interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXERRIE", + "description": "Tx-Error Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACKIE", + "description": "Tx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "COMP", + "description": "Comparator", + "groupName": "COMP", + "baseAddress": "0x4001001C", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x5", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "Control and status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COMP1EN", + "description": "Comparator 1 enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1_INP_DAC", + "description": "COMP1_INP_DAC", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1MODE", + "description": "Comparator 1 mode", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1INSEL", + "description": "Comparator 1 inverting input selection", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1OUTSEL", + "description": "Comparator 1 output selection", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1POL", + "description": "Comparator 1 output polarity", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1HYST", + "description": "Comparator 1 hysteresis", + "bitOffset": "12", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1OUT", + "description": "Comparator 1 output", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP1LOCK", + "description": "Comparator 1 lock", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2EN", + "description": "Comparator 2 enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2MODE", + "description": "Comparator 2 mode", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2INSEL", + "description": "Comparator 2 inverting input selection", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "WNDWEN", + "description": "Window mode enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2OUTSEL", + "description": "Comparator 2 output selection", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP2POL", + "description": "Comparator 2 output polarity", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2HYST", + "description": "Comparator 2 hysteresis", + "bitOffset": "28", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2OUT", + "description": "Comparator 2 output", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP2LOCK", + "description": "Comparator 2 lock", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "Cyclic redundancy check calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data register bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "General-purpose 8-bit data register bits", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "POLYSIZE", + "description": "Polynomial size", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "REV_IN", + "description": "Reverse input data", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "REV_OUT", + "description": "Reverse output data", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "INIT", + "displayName": "INIT", + "description": "Initial CRC value", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "INIT", + "description": "Programmable initial CRC value", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "CRS", + "description": "Clock recovery system", + "groupName": "CRS", + "baseAddress": "0x40006C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "SYNCOKIE", + "description": "SYNC event OK interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SYNCWARNIE", + "description": "SYNC warning interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Synchronization or trimming error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ESYNCIE", + "description": "Expected SYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Frequency error counter enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AUTOTRIMEN", + "description": "Automatic trimming enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWSYNC", + "description": "Generate software SYNC event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TRIM", + "description": "HSI48 oscillator smooth trimming", + "bitOffset": "8", + "bitWidth": "6" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2022BB7F", + "fields": [ + { + "name": "RELOAD", + "description": "Counter reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FELIM", + "description": "Frequency error limit", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "SYNCDIV", + "description": "SYNC divider", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SYNCSRC", + "description": "SYNC signal source selection", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "SYNCPOL", + "description": "SYNC polarity selection", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYNCOKF", + "description": "SYNC event OK flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SYNCWARNF", + "description": "SYNC warning flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERRF", + "description": "Error flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ESYNCF", + "description": "Expected SYNC flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SYNCERR", + "description": "SYNC error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SYNCMISS", + "description": "SYNC missed", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TRIMOVF", + "description": "Trimming overflow or underflow", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FEDIR", + "description": "Frequency error direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FECAP", + "description": "Frequency error capture", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYNCOKC", + "description": "SYNC event OK clear flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SYNCWARNC", + "description": "SYNC warning clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERRC", + "description": "Error clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ESYNCC", + "description": "Expected SYNC clear flag", + "bitOffset": "3", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt and DAC underrun interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DBGMCU", + "description": "Debug support", + "groupName": "DBGMCU", + "baseAddress": "0x40015800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "MCU Device ID Code Register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "Device Identifier", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DIV_ID", + "description": "Division Identifier", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "REV_ID", + "description": "Revision Identifier", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Debug MCU Configuration Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_STOP", + "description": "Debug Stop Mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "Debug Standby Mode", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "APBLFZ", + "displayName": "APBLFZ", + "description": "APB Low Freeze Register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER2_STOP", + "description": "Debug Timer 2 stopped when Core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER3_STOP", + "description": "Debug Timer 3 stopped when Core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER6_STOP", + "description": "Debug Timer 6 stopped when Core is halted", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER14_STOP", + "description": "Debug Timer 14 stopped when Core is halted", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_RTC_STOP", + "description": "Debug RTC stopped when Core is halted", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "Debug Window Wachdog stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDG_STOP", + "description": "Debug Independent Wachdog stopped when Core is halted", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C1_SMBUS_TIMEOUT", + "description": "SMBUS timeout mode stopped when Core is halted", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APBHFZ", + "displayName": "APBHFZ", + "description": "APB High Freeze Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER1_STOP", + "description": "Debug Timer 1 stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER15_STO", + "description": "Debug Timer 15 stopped when Core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER16_STO", + "description": "Debug Timer 16 stopped when Core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER17_STO", + "description": "Debug Timer 17 stopped when Core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_CH1", + "description": "DMA1 channel 1 interrupt", + "value": "9" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD and VDDIO2 supply comparator interrupt", + "value": "1" + }, + { + "name": "EXTI0_1", + "description": "EXTI Line[1:0] interrupts", + "value": "5" + }, + { + "name": "EXTI2_3", + "description": "EXTI Line[3:2] interrupts", + "value": "6" + }, + { + "name": "EXTI4_15", + "description": "EXTI Line15 and EXTI4 interrupts", + "value": "7" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0F940000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Interrupt Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Interrupt Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Interrupt Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Interrupt Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Interrupt Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Event Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Event Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Event Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Event Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Event Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word" + }, + { + "name": "Flash", + "description": "Flash", + "groupName": "Flash", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "3" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "LATENCY", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "PRFTBE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "PRFTBS", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FKEYR", + "description": "Flash Key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEYR", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Flash status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRT", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Flash control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FORCE_OPTLOAD", + "description": "Force option byte loading", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFF2", + "fields": [ + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LEVEL1_PROT", + "description": "Level 1 protection status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LEVEL2_PROT", + "description": "Level 2 protection status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BOOT1", + "description": "BOOT1", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "VDDA_MONITOR", + "description": "VDDA_MONITOR", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "Data1", + "description": "Data1", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x28000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000400", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000800", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000C00", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOF", + "baseAddress": "0x48001000", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48001400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bit 15", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "I2C1", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1", + "description": "I2C1 global interrupt", + "value": "23" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXIE", + "description": "TX Interrupt enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXIE", + "description": "RX Interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADDRIE", + "description": "Address match interrupt enable (slave only)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NACKIE", + "description": "Not acknowledge received interrupt enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "STOPIE", + "description": "STOP detection Interrupt enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TCIE", + "description": "Transfer Complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRIE", + "description": "Error interrupts enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DNF", + "description": "Digital noise filter", + "bitOffset": "8", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "ANFOFF", + "description": "Analog noise filter OFF", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "13", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXDMAEN", + "description": "DMA transmission requests enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXDMAEN", + "description": "DMA reception requests enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SBC", + "description": "Slave byte control", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUPEN", + "description": "Wakeup from STOP enable", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GCEN", + "description": "General call enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBHEN", + "description": "SMBus Host address enable", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBDEN", + "description": "SMBus Device Default address enable", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALERTEN", + "description": "SMBUS alert enable", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECEN", + "description": "PEC enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SADD0", + "description": "Slave address bit 0 (master mode)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SADD1", + "description": "Slave address bit 7:1 (master mode)", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "SADD8", + "description": "Slave address bit 9:8 (master mode)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "RD_WRN", + "description": "Transfer direction (master mode)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "10-bit addressing mode (master mode)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HEAD10R", + "description": "10-bit address header only read direction (master receiver mode)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation (master mode)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "NACK generation (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NBYTES", + "description": "Number of bytes", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "RELOAD", + "description": "NBYTES reload mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AUTOEND", + "description": "Automatic end mode (master mode)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "PECBYTE", + "description": "Packet error checking byte", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA1_0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OA1_1", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA1_8", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OA1MODE", + "description": "Own Address 1 10-bit mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OA1EN", + "description": "Own Address 1 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA2MSK", + "description": "Own Address 2 masks", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "OA2EN", + "description": "Own Address 2 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TIMINGR", + "displayName": "TIMINGR", + "description": "Timing register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SCLL", + "description": "SCL low period (master mode)", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "SCLH", + "description": "SCL high period (master mode)", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "SDADEL", + "description": "Data hold time", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "SCLDEL", + "description": "Data setup time", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "PRESC", + "description": "Timing prescaler", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "TIMEOUTR", + "displayName": "TIMEOUTR", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIMEOUTA", + "description": "Bus timeout A", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "TIDLE", + "description": "Idle clock timeout detection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIMOUTEN", + "description": "Clock timeout enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIMEOUTB", + "description": "Bus timeout B", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "TEXTEN", + "description": "Extended clock timeout enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000001", + "fields": [ + { + "name": "TXE", + "description": "Transmit data register empty (transmitters)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXIS", + "description": "Transmit interrupt status (transmitters)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Receive data register not empty (receivers)", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address matched (slave mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NACKF", + "description": "Not acknowledge received flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transfer Complete (master mode)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCR", + "description": "Transfer Complete Reload", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ARLO", + "description": "Arbitration lost", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun/Underrun (slave mode)", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIMEOUT", + "description": "Timeout or t_low detection flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Transfer direction (Slave mode)", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDCODE", + "description": "Address match code (Slave mode)", + "bitOffset": "17", + "bitWidth": "7", + "access": "read-only" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADDRCF", + "description": "Address Matched flag clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACKCF", + "description": "Not Acknowledge flag clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STOPCF", + "description": "Stop detection flag clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BERRCF", + "description": "Bus error flag clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ARLOCF", + "description": "Arbitration lost flag clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OVRCF", + "description": "Overrun/Underrun flag clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PECCF", + "description": "PEC Error flag clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIMOUTCF", + "description": "Timeout detection flag clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALERTCF", + "description": "Alert flag clear", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "PECR", + "displayName": "PECR", + "description": "PEC register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PEC", + "description": "Packet error checking register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDATA", + "description": "8-bit receive data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXDATA", + "description": "8-bit transmit data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2", + "description": "I2C2 global interrupt", + "value": "24" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WVU", + "description": "Watchdog counter window value update", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "WINR", + "displayName": "WINR", + "description": "Window register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "WIN", + "description": "Watchdog counter window value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "VREFINTRDY", + "description": "VREFINT reference voltage ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP1", + "description": "Enable WKUP pin 1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP2", + "description": "Enable WKUP pin 2", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP3", + "description": "Enable WKUP pin 3", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP4", + "description": "Enable WKUP pin 4", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP5", + "description": "Enable WKUP pin 5", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP6", + "description": "Enable WKUP pin 6", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP7", + "description": "Enable WKUP pin 7", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP8", + "description": "Enable WKUP pin 8", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL input clock source", + "bitOffset": "15", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCOPRE", + "description": "Microcontroller Clock Output Prescaler", + "bitOffset": "28", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PLLNODIV", + "description": "PLL clock not divided for MCO", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14RDYF", + "description": "HSI14 ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48RDYF", + "description": "HSI48 ready interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDYE", + "description": "HSI14 ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDYIE", + "description": "HSI48 ready interrupt enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI14RDYC", + "description": "HSI 14 MHz Ready Interrupt Clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI48RDYC", + "description": "HSI48 Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGRST", + "description": "SYSCFG and COMP reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15RST", + "description": "TIM15 timer reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16RST", + "description": "TIM16 timer reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17RST", + "description": "TIM17 timer reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCURST", + "description": "Debug MCU reset", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 timer reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "Timer 14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4RST", + "description": "USART4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANRST", + "description": "CAN interface reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSRST", + "description": "Clock Recovery System interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECRST", + "description": "HDMI CEC reset", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFEN", + "description": "I/O port F clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCEN", + "description": "Touch sensing controller clock enable", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGEN", + "description": "SYSCFG clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCEN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15EN", + "description": "TIM15 timer clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16EN", + "description": "TIM16 timer clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17EN", + "description": "TIM17 timer clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCUEN", + "description": "MCU debug module clock enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 timer clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "Timer 14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4EN", + "description": "USART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANEN", + "description": "CAN interface clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSEN", + "description": "Clock Recovery System interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECEN", + "description": "HDMI CEC interface clock enable", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSEDRV", + "description": "LSE oscillator drive capability", + "bitOffset": "3", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OBLRSTF", + "description": "Option byte loader reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "AHBRSTR", + "displayName": "AHBRSTR", + "description": "AHB peripheral reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IOPARST", + "description": "I/O port A reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "I/O port B reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "I/O port C reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "I/O port D reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFRST", + "description": "I/O port F reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCRST", + "description": "Touch sensing controller reset", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Clock configuration register 2", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PREDIV", + "description": "PREDIV division factor", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR3", + "displayName": "CFGR3", + "description": "Clock configuration register 3", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "USART1SW", + "description": "USART1 clock source selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "I2C1SW", + "description": "I2C1 clock source selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CECSW", + "description": "HDMI CEC clock source selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "USBSW", + "description": "USB clock source selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ADCSW", + "description": "ADC clock source selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART2SW", + "description": "USART2 clock source selection", + "bitOffset": "16", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Clock control register 2", + "addressOffset": "0x34", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "HSI14ON", + "description": "HSI14 clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDY", + "description": "HR14 clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14DIS", + "description": "HSI14 clock request from ADC disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14TRIM", + "description": "HSI14 clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSI14CAL", + "description": "HSI14 clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSI48ON", + "description": "HSI48 clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDY", + "description": "HSI48 clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48CAL", + "description": "HSI48 factory clock calibration", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC interrupts", + "value": "2" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REFCKON", + "description": "RTC_REFIN reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BYPSHAD", + "description": "Bypass the shadow registers", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSE", + "description": "Timestamp enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COSEL", + "description": "Calibration output selection", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "RTC_TAMP1 detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "RTC_TAMP2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format.", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format.", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "ADD1S", + "description": "Reserved", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Timestamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Timestamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Time-stamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + }, + { + "name": "CALW16", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALP", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TAMP1E", + "description": "RTC_TAMP1 input detection enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for RTC_TAMP1 input", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "RTC_TAMP2 input detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMP2_TRG", + "description": "Active level for RTC_TAMP2 input", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPFLT", + "description": "RTC_TAMPx filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMP_PRCH", + "description": "RTC_TAMPx precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMP_PUDIS", + "description": "RTC_TAMPx pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PC13VALUE", + "description": "RTC_ALARM output type/PC13 value", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PC13MODE", + "description": "PC13 mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PC14VALUE", + "description": "PC14 value", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PC14MODE", + "description": "PC14 mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PC15VALUE", + "description": "PC15 value", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PC15MODE", + "description": "PC15 mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1_global_interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "NSSP", + "description": "NSS pulse management", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "FRXTH", + "description": "FIFO reception threshold", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LDMA_RX", + "description": "Last DMA transfer for reception", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LDMA_TX", + "description": "Last DMA transfer for transmission", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FRLVL", + "description": "FIFO reception level", + "bitOffset": "9", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FTLVL", + "description": "FIFO transmission level", + "bitOffset": "11", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000010", + "fields": [ + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "26" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1D", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "Memory mapping selection bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ADC_DMA_RMP", + "description": "ADC DMA remapping bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART1_TX_DMA_RMP", + "description": "USART1_TX DMA remapping bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "USART1_RX_DMA_RMP", + "description": "USART1_RX DMA request remapping bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM16_DMA_RMP", + "description": "TIM16 DMA request remapping bit", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM17_DMA_RMP", + "description": "TIM17 DMA request remapping bit", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C_PB6_FM", + "description": "Fast Mode Plus (FM plus) driving capability activation bits.", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2C_PB7_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2C_PB8_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "I2C_PB9_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1_FM_plus", + "description": "FM+ driving capability activation for I2C1", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C2_FM_plus", + "description": "FM+ driving capability activation for I2C2", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SPI2_DMA_RMP", + "description": "SPI2 DMA request remapping bit", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "USART2_DMA_RMP", + "description": "USART2 DMA request remapping bit", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "USART3_DMA_RMP", + "description": "USART3 DMA request remapping bit", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "I2C1_DMA_RMP", + "description": "I2C1 DMA request remapping bit", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "TIM1_DMA_RMP", + "description": "TIM1 DMA request remapping bit", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "TIM2_DMA_RMP", + "description": "TIM2 DMA request remapping bit", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "TIM3_DMA_RMP", + "description": "TIM3 DMA request remapping bit", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI 0 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI 1 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI 2 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI 3 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI 4 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI 5 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI 6 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI 7 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI 8 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI 9 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI 10 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI 11 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI 12 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI 13 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI 14 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI 15 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LOCUP_LOCK", + "description": "Cortex-M0 LOCKUP bit enable bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SRAM_PARITY_LOCK", + "description": "SRAM parity lock bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PVD_LOCK", + "description": "PVD lock enable bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRAM_PEF", + "description": "SRAM parity flag", + "bitOffset": "8", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_UP_TRG_COM", + "description": "TIM1 break, update, trigger and commutation interrupt", + "value": "13" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "14" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM14", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40002000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM14", + "description": "TIM14 global interrupt", + "value": "19" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Timer input 1 remap", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM15", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM15", + "description": "TIM15 global interrupt", + "value": "20" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM16", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM16", + "description": "TIM16 global interrupt", + "value": "21" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM17", + "derivedFrom": "TIM16", + "baseAddress": "0x40014800", + "interrupts": [ + { + "name": "TIM17", + "description": "TIM17 global interrupt", + "value": "22" + } + ] + }, + { + "name": "TIM2", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "15" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAR", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "16" + } + ] + }, + { + "name": "TIM6", + "description": "Basic-timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "18" + } + ] + }, + { + "name": "TSC", + "description": "Touch sensing controller", + "groupName": "TSC", + "baseAddress": "0x40024000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TSC", + "description": "Touch sensing interrupt", + "value": "8" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSCE", + "description": "Touch sensing controller enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start a new acquisition", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AM", + "description": "Acquisition mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCPOL", + "description": "Synchronization pin polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IODEF", + "description": "I/O Default mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCV", + "description": "Max count value", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PGPSC", + "description": "Pulse generator prescaler", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SSPSC", + "description": "Spread spectrum prescaler", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SSE", + "description": "Spread spectrum enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SSD", + "description": "Spread spectrum deviation", + "bitOffset": "17", + "bitWidth": "7" + }, + { + "name": "CTPL", + "description": "Charge transfer pulse low", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CTPH", + "description": "Charge transfer pulse high", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOAIE", + "description": "End of acquisition interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MCEIE", + "description": "Max count error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOAIC", + "description": "End of acquisition interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MCEIC", + "description": "Max count error interrupt clear", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOAF", + "description": "End of acquisition flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MCEF", + "description": "Max count error flag", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "IOHCR", + "displayName": "IOHCR", + "description": "I/O hysteresis control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOASCR", + "displayName": "IOASCR", + "description": "I/O analog switch control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 analog switch enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 analog switch enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 analog switch enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 analog switch enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 analog switch enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 analog switch enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 analog switch enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 analog switch enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 analog switch enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 analog switch enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 analog switch enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 analog switch enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 analog switch enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 analog switch enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 analog switch enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 analog switch enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 analog switch enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 analog switch enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 analog switch enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 analog switch enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 analog switch enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 analog switch enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 analog switch enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 analog switch enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOSCR", + "displayName": "IOSCR", + "description": "I/O sampling control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 sampling mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 sampling mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 sampling mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 sampling mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 sampling mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 sampling mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 sampling mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 sampling mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 sampling mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 sampling mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 sampling mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 sampling mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 sampling mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 sampling mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 sampling mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 sampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 sampling mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 sampling mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 sampling mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 sampling mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 sampling mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 sampling mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 sampling mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 sampling mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOCCR", + "displayName": "IOCCR", + "description": "I/O channel control register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1_IO1", + "description": "G1_IO1 channel mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 channel mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 channel mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 channel mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 channel mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 channel mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 channel mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 channel mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 channel mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 channel mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 channel mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 channel mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 channel mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 channel mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 channel mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 channel mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 channel mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 channel mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 channel mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 channel mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 channel mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 channel mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 channel mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO4", + "description": "G6_IO4 channel mode", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "IOGCSR", + "displayName": "IOGCSR", + "description": "I/O group control status register", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G1E", + "description": "Analog I/O group x enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G2E", + "description": "Analog I/O group x enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G3E", + "description": "Analog I/O group x enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G4E", + "description": "Analog I/O group x enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G5E", + "description": "Analog I/O group x enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G6E", + "description": "Analog I/O group x enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G7E", + "description": "Analog I/O group x enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G8E", + "description": "Analog I/O group x enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G1S", + "description": "Analog I/O group x status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G2S", + "description": "Analog I/O group x status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G3S", + "description": "Analog I/O group x status", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G4S", + "description": "Analog I/O group x status", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G5S", + "description": "Analog I/O group x status", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G6S", + "description": "Analog I/O group x status", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G7S", + "description": "Analog I/O group x status", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G8S", + "description": "Analog I/O group x status", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "IOG1CR", + "displayName": "IOG1CR", + "description": "I/O group x counter register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG2CR", + "displayName": "IOG2CR", + "description": "I/O group x counter register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG3CR", + "displayName": "IOG3CR", + "description": "I/O group x counter register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG4CR", + "displayName": "IOG4CR", + "description": "I/O group x counter register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG5CR", + "displayName": "IOG5CR", + "description": "I/O group x counter register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG6CR", + "displayName": "IOG6CR", + "description": "I/O group x counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UE", + "description": "USART enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UESM", + "description": "USART enable in Stop mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Receiver wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MME", + "description": "Mute mode enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CMIE", + "description": "Character match interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DEDT", + "description": "Driver Enable deassertion time", + "bitOffset": "16", + "bitWidth": "5" + }, + { + "name": "DEAT", + "description": "Driver Enable assertion time", + "bitOffset": "21", + "bitWidth": "5" + }, + { + "name": "RTOIE", + "description": "Receiver timeout interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "EOBIE", + "description": "End of Block interrupt enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "M1", + "description": "Word length", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADDM7", + "description": "7-bit Address Detection/4-bit Address Detection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "LIN break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWAP", + "description": "Swap TX/RX pins", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "RXINV", + "description": "RX pin active level inversion", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TXINV", + "description": "TX pin active level inversion", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DATAINV", + "description": "Binary data inversion", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MSBFIRST", + "description": "Most significant bit first", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ABREN", + "description": "Auto baud rate enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "ABRMOD", + "description": "Auto baud rate mode", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "RTOEN", + "description": "Receiver timeout enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ADD0", + "description": "Address of the USART node", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ADD4", + "description": "Address of the USART node", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OVRDIS", + "description": "Overrun Disable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DDRE", + "description": "DMA Disable on Reception Error", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DEM", + "description": "Driver enable mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DEP", + "description": "Driver enable polarity selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SCARCNT", + "description": "Smartcard auto-retry count", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "WUS", + "description": "Wakeup from Stop mode interrupt flag selection", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "WUFIE", + "description": "Wakeup from Stop mode interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "RTOR", + "displayName": "RTOR", + "description": "Receiver timeout register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RTO", + "description": "Receiver timeout value", + "bitOffset": "0", + "bitWidth": "24" + }, + { + "name": "BLEN", + "description": "Block Length", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RQR", + "displayName": "RQR", + "description": "Request register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ABRRQ", + "description": "Auto baud rate request", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SBKRQ", + "description": "Send break request", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MMRQ", + "description": "Mute mode request", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RXFRQ", + "description": "Receive data flush request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFRQ", + "description": "Transmit data flush request", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt & status register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00C0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLE", + "description": "Idle line detected", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LBDF", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSIF", + "description": "CTS interrupt flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "RTOF", + "description": "Receiver timeout", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "EOBF", + "description": "End of block flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ABRE", + "description": "Auto baud rate error", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ABRF", + "description": "Auto baud rate flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Busy flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CMF", + "description": "Character match flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SBKF", + "description": "Send break flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup from Mute mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "WUF", + "description": "Wakeup from Stop mode flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEACK", + "description": "Transmit enable acknowledge flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "REACK", + "description": "Receive enable acknowledge flag", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PECF", + "description": "Parity error clear flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FECF", + "description": "Framing error clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "NCF", + "description": "Noise detected clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ORECF", + "description": "Overrun error clear flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLECF", + "description": "Idle line detected clear flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCCF", + "description": "Transmission complete clear flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDCF", + "description": "LIN break detection clear flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSCF", + "description": "CTS clear flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTOCF", + "description": "Receiver timeout clear flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "EOBCF", + "description": "End of timeout clear flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMCF", + "description": "Character match clear flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WUCF", + "description": "Wakeup from Stop mode clear flag", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "RDR", + "displayName": "RDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RDR", + "description": "Receive data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TDR", + "displayName": "TDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDR", + "description": "Transmit data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "28" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3_4", + "description": "USART3 and USART4 global interrupt", + "value": "29" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART4", + "derivedFrom": "USART1", + "baseAddress": "0x40004C00", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USB", + "description": "Universal serial bus full-speed device interface", + "groupName": "USB", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USB", + "description": "USB global interrupt", + "value": "31" + } + ], + "registers": [ + { + "name": "EP0R", + "displayName": "EP0R", + "description": "Endpoint 0 register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP1R", + "displayName": "EP1R", + "description": "Endpoint 1 register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP2R", + "displayName": "EP2R", + "description": "Endpoint 2 register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP3R", + "displayName": "EP3R", + "description": "Endpoint 3 register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP4R", + "displayName": "EP4R", + "description": "Endpoint 4 register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP5R", + "displayName": "EP5R", + "description": "Endpoint 5 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP6R", + "displayName": "EP6R", + "description": "Endpoint 6 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP7R", + "displayName": "EP7R", + "description": "Endpoint 7 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNTR", + "displayName": "CNTR", + "description": "Control register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000003", + "fields": [ + { + "name": "FRES", + "description": "Force USB Reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDWN", + "description": "Power down", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPMODE", + "description": "Low-power mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSUSP", + "description": "Force suspend", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RESUME", + "description": "Resume request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "L1RESUME", + "description": "LPM L1 Resume request", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "L1REQM", + "description": "LPM L1 state request interrupt mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ESOFM", + "description": "Expected start of frame interrupt mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOFM", + "description": "Start of frame interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESETM", + "description": "USB reset interrupt mask", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSPM", + "description": "Suspend mode interrupt mask", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUPM", + "description": "Wakeup interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRM", + "description": "Error interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVRM", + "description": "Packet memory area over / underrun interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTRM", + "description": "Correct transfer interrupt mask", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ISTR", + "displayName": "ISTR", + "description": "Interrupt status register", + "addressOffset": "0x44", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EP_ID", + "description": "Endpoint Identifier", + "bitOffset": "0", + "bitWidth": "4", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Direction of transaction", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "L1REQ", + "description": "LPM L1 state request", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESOF", + "description": "Expected start frame", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RESET", + "description": "Reset request", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SUSP", + "description": "Suspend mode request", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUP", + "description": "Wakeup", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERR", + "description": "Error", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PMAOVR", + "description": "Packet memory area over / underrun", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTR", + "description": "Correct transfer", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FNR", + "displayName": "FNR", + "description": "Frame number register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FN", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "LSOF", + "description": "Lost SOF", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "LCK", + "description": "Locked", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "RXDM", + "description": "Receive data - line status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXDP", + "description": "Receive data + line status", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DADDR", + "displayName": "DADDR", + "description": "Device address", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Device address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "EF", + "description": "Enable function", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "BTABLE", + "displayName": "BTABLE", + "description": "Buffer table address", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BTABLE", + "description": "Buffer table", + "bitOffset": "3", + "bitWidth": "13" + } + ] + }, + { + "name": "LPMCSR", + "displayName": "LPMCSR", + "description": "LPM control and status register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "LPMEN", + "description": "LPM support enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPMACK", + "description": "LPM Token acknowledge enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REMWAKE", + "description": "BRemoteWake value", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BESL", + "description": "BESL value", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-only" + } + ] + }, + { + "name": "BCDR", + "displayName": "BCDR", + "description": "Battery charging detector", + "addressOffset": "0x58", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "BCDEN", + "description": "Battery charging detector (BCD) enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDEN", + "description": "Data contact detection (DCD) mode enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PDEN", + "description": "Primary detection (PD) mode enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDEN", + "description": "Secondary detection (SD) mode enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDET", + "description": "Data contact detection (DCD) status", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PDET", + "description": "Primary detection (PD) status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SDET", + "description": "Secondary detection (SD) status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PS2DET", + "description": "DM pull-up detection status", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DPPU", + "description": "DP pull-up control", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "T", + "description": "7-bit counter", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + } + ], + "cpu": { + "name": "CM0", + "revision": "r0p0", + "endian": "little", + "mpuPresent": "false", + "fpuPresent": "false", + "nvicPrioBits": "2", + "deviceNumInterrupts": "31", + "vendorSystickConfig": "false", + "qemuItmPresent": false + }, + "qemuAlignment": "any" + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/STM32F103xx-qemu.json b/gnu-mcu-eclipse/devices/STM32F103xx-qemu.json new file mode 100644 index 0000000000..c3c31a7ed4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/STM32F103xx-qemu.json @@ -0,0 +1,23622 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F103xx.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.2", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F103xx.svd", + "--output", + "STM32F103xx-xsvd.json" + ], + "date": "2016-12-14T22:50:50.255Z" + }, + { + "tool": "xcdl", + "version": "1.6.8", + "command": [ + "svd-patch", + "--file", + "STM32F103xx-xsvd.json", + "--patch", + "STM32F103xx-patch.json", + "--output", + "../STM32F103xx-qemu.json", + "--remove", + "NVIC" + ], + "date": "2016-12-19T10:35:22.656Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F103xx", + "version": "1.3", + "description": "STM32F103xx", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC1", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "DUALMOD", + "description": "Dual mode selection", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sample time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sample time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ADC2DATA", + "description": "ADC2 data", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sample time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sample time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "derivedFrom": "ADC2", + "baseAddress": "0x40013C00", + "interrupts": [ + { + "name": "ADC3", + "description": "ADC3 global interrupt", + "value": "47" + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "AFIO", + "description": "Alternate function I/O", + "groupName": "AFIO", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "EVCR", + "displayName": "EVCR", + "description": "Event Control Register (AFIO_EVCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PIN", + "description": "Pin selection", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "PORT", + "description": "Port selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "EVOE", + "description": "Event Output Enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "MAPR", + "displayName": "MAPR", + "description": "AF remap and debug I/O configuration register (AFIO_MAPR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SPI1_REMAP", + "description": "SPI1 remapping", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "I2C1_REMAP", + "description": "I2C1 remapping", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART1_REMAP", + "description": "USART1 remapping", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART2_REMAP", + "description": "USART2 remapping", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART3_REMAP", + "description": "USART3 remapping", + "bitOffset": "4", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM1_REMAP", + "description": "TIM1 remapping", + "bitOffset": "6", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM2_REMAP", + "description": "TIM2 remapping", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM3_REMAP", + "description": "TIM3 remapping", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM4_REMAP", + "description": "TIM4 remapping", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CAN_REMAP", + "description": "CAN1 remapping", + "bitOffset": "13", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PD01_REMAP", + "description": "Port D0/Port D1 mapping on OSCIN/OSCOUT", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIM5CH4_IREMAP", + "description": "Set and cleared by software", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC1_ETRGINJ_REMAP", + "description": "ADC 1 External trigger injected conversion remapping", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC1_ETRGREG_REMAP", + "description": "ADC 1 external trigger regular conversion remapping", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC2_ETRGINJ_REMAP", + "description": "ADC 2 external trigger injected conversion remapping", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC2_ETRGREG_REMAP", + "description": "ADC 2 external trigger regular conversion remapping", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWJ_CFG", + "description": "Serial wire JTAG configuration", + "bitOffset": "24", + "bitWidth": "3", + "access": "write-only" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1 (AFIO_EXTICR1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI0 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI1 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI2 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI3 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2 (AFIO_EXTICR2)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI4 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI5 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI6 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI7 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3 (AFIO_EXTICR3)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI8 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI9 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI11 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4 (AFIO_EXTICR4)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI12 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI13 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI14 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI15 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "MAPR2", + "displayName": "MAPR2", + "description": "AF remap and debug I/O configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM9_REMAP", + "description": "TIM9 remapping", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM10_REMAP", + "description": "TIM10 remapping", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM11_REMAP", + "description": "TIM11 remapping", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM13_REMAP", + "description": "TIM13 remapping", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIM14_REMAP", + "description": "TIM14 remapping", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSMC_NADV", + "description": "NADV connect/disconnect", + "bitOffset": "10", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "BKP", + "description": "Backup registers", + "groupName": "BKP", + "baseAddress": "0x40006C04", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR1", + "displayName": "DR1", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D1", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR2", + "displayName": "DR2", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D2", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR3", + "displayName": "DR3", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D3", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR4", + "displayName": "DR4", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D4", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR5", + "displayName": "DR5", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D5", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR6", + "displayName": "DR6", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D6", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR7", + "displayName": "DR7", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D7", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR8", + "displayName": "DR8", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D8", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR9", + "displayName": "DR9", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D9", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR10", + "displayName": "DR10", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D10", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR11", + "displayName": "DR11", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR11", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR12", + "displayName": "DR12", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR12", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR13", + "displayName": "DR13", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR13", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR14", + "displayName": "DR14", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D14", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR15", + "displayName": "DR15", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D15", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR16", + "displayName": "DR16", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D16", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR17", + "displayName": "DR17", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D17", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR18", + "displayName": "DR18", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D18", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR19", + "displayName": "DR19", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D19", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR20", + "displayName": "DR20", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D20", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR21", + "displayName": "DR21", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D21", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR22", + "displayName": "DR22", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D22", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR23", + "displayName": "DR23", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D23", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR24", + "displayName": "DR24", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D24", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR25", + "displayName": "DR25", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D25", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR26", + "displayName": "DR26", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D26", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR27", + "displayName": "DR27", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D27", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR28", + "displayName": "DR28", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D28", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR29", + "displayName": "DR29", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D29", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR30", + "displayName": "DR30", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D30", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR31", + "displayName": "DR31", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D31", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR32", + "displayName": "DR32", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D32", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR33", + "displayName": "DR33", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D33", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR34", + "displayName": "DR34", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D34", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR35", + "displayName": "DR35", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D35", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR36", + "displayName": "DR36", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D36", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR37", + "displayName": "DR37", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D37", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR38", + "displayName": "DR38", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D38", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR39", + "displayName": "DR39", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D39", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR40", + "displayName": "DR40", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D40", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR41", + "displayName": "DR41", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D41", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR42", + "displayName": "DR42", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D42", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RTCCR", + "displayName": "RTCCR", + "description": "RTC clock calibration register (BKP_RTCCR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CAL", + "description": "Calibration value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "CCO", + "description": "Calibration Clock Output", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ASOE", + "description": "Alarm or second output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ASOS", + "description": "Alarm or second output selection", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Backup control register (BKP_CR)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPE", + "description": "Tamper pin enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPAL", + "description": "Tamper pin active level", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "BKP_CSR control/status register (BKP_CSR)", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTE", + "description": "Clear Tamper event", + "bitOffset": "0", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CTI", + "description": "Clear Tamper Interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TPIE", + "description": "Tamper Pin interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TEF", + "description": "Tamper Event Flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIF", + "description": "Tamper Interrupt Flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ] + }, + { + "name": "CAN", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupt", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_ESR", + "displayName": "CAN_ESR", + "description": "CAN_ESR", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "CAN_BTR", + "displayName": "CAN_BTR", + "description": "CAN_BTR", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TI0R", + "displayName": "CAN_TI0R", + "description": "CAN_TI0R", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT0R", + "displayName": "CAN_TDT0R", + "description": "CAN_TDT0R", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL0R", + "displayName": "CAN_TDL0R", + "description": "CAN_TDL0R", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH0R", + "displayName": "CAN_TDH0R", + "description": "CAN_TDH0R", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI1R", + "displayName": "CAN_TI1R", + "description": "CAN_TI1R", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT1R", + "displayName": "CAN_TDT1R", + "description": "CAN_TDT1R", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL1R", + "displayName": "CAN_TDL1R", + "description": "CAN_TDL1R", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH1R", + "displayName": "CAN_TDH1R", + "description": "CAN_TDH1R", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI2R", + "displayName": "CAN_TI2R", + "description": "CAN_TI2R", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT2R", + "displayName": "CAN_TDT2R", + "description": "CAN_TDT2R", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL2R", + "displayName": "CAN_TDL2R", + "description": "CAN_TDL2R", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH2R", + "displayName": "CAN_TDH2R", + "description": "CAN_TDH2R", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI0R", + "displayName": "CAN_RI0R", + "description": "CAN_RI0R", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_RDT0R", + "displayName": "CAN_RDT0R", + "description": "CAN_RDT0R", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_RDL0R", + "displayName": "CAN_RDL0R", + "description": "CAN_RDL0R", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH0R", + "displayName": "CAN_RDH0R", + "description": "CAN_RDH0R", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI1R", + "displayName": "CAN_RI1R", + "description": "CAN_RI1R", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_RDT1R", + "displayName": "CAN_RDT1R", + "description": "CAN_RDT1R", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_RDL1R", + "displayName": "CAN_RDL1R", + "description": "CAN_RDL1R", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH1R", + "displayName": "CAN_RDH1R", + "description": "CAN_RDH1R", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_FMR", + "displayName": "CAN_FMR", + "description": "CAN_FMR", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FM1R", + "displayName": "CAN_FM1R", + "description": "CAN_FM1R", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FS1R", + "displayName": "CAN_FS1R", + "description": "CAN_FS1R", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "CRC calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital to analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (DAC_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "DAC software trigger register (DAC_SWTRIGR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "20", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "DAC channel1 data output register (DAC_DOR1)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "DAC channel2 data output register (DAC_DOR2)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "DBGMCU_IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "DBGMCU_CR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "DBG_IWDG_STOP", + "description": "DBG_IWDG_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBG_TIM1_STOP", + "description": "DBG_TIM1_STOP", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DBG_I2C1_SMBUS_TIMEOUT", + "description": "DBG_I2C1_SMBUS_TIMEOUT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "DBG_TIM8_STOP", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "21", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_Channel1", + "description": "DMA1 Channel1 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Channel2", + "description": "DMA1 Channel2 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Channel3", + "description": "DMA1 Channel3 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Channel4", + "description": "DMA1 Channel4 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Channel5", + "description": "DMA1 Channel5 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Channel6", + "description": "DMA1 Channel6 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Channel7", + "description": "DMA1 Channel7 global interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "derivedFrom": "DMA1", + "baseAddress": "0x40020400", + "interrupts": [ + { + "name": "DMA2_Channel1", + "description": "DMA2 Channel1 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Channel2", + "description": "DMA2 Channel2 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Channel3", + "description": "DMA2 Channel3 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Channel4_5", + "description": "DMA2 Channel4 and DMA2 Channel5 global interrupt", + "value": "59" + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "EXTI", + "description": "EXTI", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMPER", + "description": "Tamper interrupt", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word" + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "HLFCYA", + "description": "Flash half cycle access enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "Prefetch buffer enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "Prefetch buffer status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRTERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFFC", + "fields": [ + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RDPRT", + "description": "Read protection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "10", + "bitWidth": "8" + }, + { + "name": "Data1", + "description": "Data1", + "bitOffset": "18", + "bitWidth": "8" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "FSMC", + "description": "Flexible static memory controller", + "groupName": "FSMC", + "baseAddress": "0xA0000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1000", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FSMC", + "description": "FSMC global interrupt", + "value": "48" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "SRAM/NOR-Flash chip-select control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR1", + "displayName": "BTR1", + "description": "SRAM/NOR-Flash chip-select timing register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "SRAM/NOR-Flash chip-select control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR2", + "displayName": "BTR2", + "description": "SRAM/NOR-Flash chip-select timing register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR3", + "displayName": "BCR3", + "description": "SRAM/NOR-Flash chip-select control register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR3", + "displayName": "BTR3", + "description": "SRAM/NOR-Flash chip-select timing register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR4", + "displayName": "BCR4", + "description": "SRAM/NOR-Flash chip-select control register 4", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR4", + "displayName": "BTR4", + "description": "SRAM/NOR-Flash chip-select timing register 4", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "PCR2", + "displayName": "PCR2", + "description": "PC Card/NAND Flash control register 2", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "FIFO status and interrupt register 2", + "addressOffset": "0x64", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM2", + "displayName": "PMEM2", + "description": "Common memory space timing register 2", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT2", + "displayName": "PATT2", + "description": "Attribute memory space timing register 2", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "Attribute memory x setup time", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "Attribute memory x wait time", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "Attribute memory x hold time", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "Attribute memory x databus HiZ time", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR2", + "displayName": "ECCR2", + "description": "ECC result register 2", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECC result", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR3", + "displayName": "PCR3", + "description": "PC Card/NAND Flash control register 3", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR3", + "displayName": "SR3", + "description": "FIFO status and interrupt register 3", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM3", + "displayName": "PMEM3", + "description": "Common memory space timing register 3", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT3", + "displayName": "PATT3", + "description": "Attribute memory space timing register 3", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR3", + "displayName": "ECCR3", + "description": "ECC result register 3", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR4", + "displayName": "PCR4", + "description": "PC Card/NAND Flash control register 4", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR4", + "displayName": "SR4", + "description": "FIFO status and interrupt register 4", + "addressOffset": "0xA4", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM4", + "displayName": "PMEM4", + "description": "Common memory space timing register 4", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT4", + "displayName": "PATT4", + "description": "Attribute memory space timing register 4", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PIO4", + "displayName": "PIO4", + "description": "I/O space timing register 4", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "IOSETx", + "description": "IOSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IOWAITx", + "description": "IOWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IOHOLDx", + "description": "IOHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IOHIZx", + "description": "IOHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "BWTR1", + "displayName": "BWTR1", + "description": "SRAM/NOR-Flash write timing registers 1", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR2", + "displayName": "BWTR2", + "description": "SRAM/NOR-Flash write timing registers 2", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR3", + "displayName": "BWTR3", + "description": "SRAM/NOR-Flash write timing registers 3", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR4", + "displayName": "BWTR4", + "description": "SRAM/NOR-Flash write timing registers 4", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General purpose I/O", + "groupName": "GPIO", + "baseAddress": "0x40010800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CRL", + "displayName": "CRL", + "description": "Port configuration register low (GPIOn_CRL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE0", + "description": "Port n.0 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF0", + "description": "Port n.0 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE1", + "description": "Port n.1 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF1", + "description": "Port n.1 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE2", + "description": "Port n.2 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF2", + "description": "Port n.2 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE3", + "description": "Port n.3 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF3", + "description": "Port n.3 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE4", + "description": "Port n.4 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF4", + "description": "Port n.4 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE5", + "description": "Port n.5 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF5", + "description": "Port n.5 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE6", + "description": "Port n.6 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF6", + "description": "Port n.6 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE7", + "description": "Port n.7 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF7", + "description": "Port n.7 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "CRH", + "displayName": "CRH", + "description": "Port configuration register high (GPIOn_CRL)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE8", + "description": "Port n.8 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF8", + "description": "Port n.8 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE9", + "description": "Port n.9 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF9", + "description": "Port n.9 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE10", + "description": "Port n.10 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF10", + "description": "Port n.10 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE11", + "description": "Port n.11 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF11", + "description": "Port n.11 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE12", + "description": "Port n.12 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF12", + "description": "Port n.12 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE13", + "description": "Port n.13 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF13", + "description": "Port n.13 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE14", + "description": "Port n.14 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF14", + "description": "Port n.14 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE15", + "description": "Port n.15 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF15", + "description": "Port n.15 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Port input data register (GPIOn_IDR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "Port output data register (GPIOn_ODR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "Port bit set/reset register (GPIOn_BSRR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Set bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Set bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Set bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Set bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Set bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Set bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Set bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Set bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Set bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Set bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Set bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Set bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Set bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Set bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Set bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Set bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 2", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register (GPIOn_BRR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "Port configuration lock register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port A Lock bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port A Lock bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port A Lock bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port A Lock bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port A Lock bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port A Lock bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port A Lock bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port A Lock bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port A Lock bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port A Lock bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port A Lock bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port A Lock bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port A Lock bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port A Lock bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port A Lock bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port A Lock bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Lock key", + "bitOffset": "16", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOA", + "baseAddress": "0x40010C00", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011000", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011400", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011800", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011C00", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOG", + "derivedFrom": "GPIOA", + "baseAddress": "0x40012000" + }, + { + "name": "I2C1", + "description": "Inter integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register (IWDG_KR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register (IWDG_PR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register (IWDG_RLR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (IWDG_SR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low Power Deep Sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power Down Deep Sleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear Wake-up Flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear STANDBY Flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power Voltage Detector Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD Level Selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable Backup Domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wake-Up Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "STANDBY Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD Output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB High speed prescaler (APB2)", + "bitOffset": "11", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL entry clock source", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "OTGFSPRE", + "description": "USB OTG FS prescaler", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000000", + "fields": [ + { + "name": "AFIORST", + "description": "Alternate function I/O reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPARST", + "description": "IO port A reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "IO port B reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "IO port C reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "IO port D reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPERST", + "description": "IO port E reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPFRST", + "description": "IO port F reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IOPGRST", + "description": "IO port G reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC1RST", + "description": "ADC 1 interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2RST", + "description": "ADC 2 interface reset", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIM8RST", + "description": "TIM8 timer reset", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ADC3RST", + "description": "ADC 3 interface reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 timer reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 timer reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TIM11RST", + "description": "TIM11 timer reset", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "Timer 4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "Timer 5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "Timer 7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12RST", + "description": "Timer 12 reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13RST", + "description": "Timer 13 reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "Timer 14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4RST", + "description": "UART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5RST", + "description": "UART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANRST", + "description": "CAN reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BKPRST", + "description": "Backup interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSMCEN", + "description": "FSMC clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFIOEN", + "description": "Alternate function I/O clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPEEN", + "description": "I/O port E clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPFEN", + "description": "I/O port F clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IOPGEN", + "description": "I/O port G clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC 2 interface clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIM8EN", + "description": "TIM8 Timer clock enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ADC3EN", + "description": "ADC3 interface clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 Timer clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 Timer clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TIM11EN", + "description": "TIM11 Timer clock enable", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "Timer 4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "Timer 5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "Timer 7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12EN", + "description": "Timer 12 clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13EN", + "description": "Timer 13 clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "Timer 14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI 3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART 3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART 4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART 5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBEN", + "description": "USB clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANEN", + "description": "CAN clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BKPEN", + "description": "Backup interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "RTC", + "description": "Real time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC global interrupt", + "value": "3" + }, + { + "name": "RTCAlarm", + "description": "RTC Alarms through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "CRH", + "displayName": "CRH", + "description": "RTC Control Register High", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SECIE", + "description": "Second interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ALRIE", + "description": "Alarm interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OWIE", + "description": "Overflow interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "CRL", + "displayName": "CRL", + "description": "RTC Control Register Low", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000020", + "fields": [ + { + "name": "SECF", + "description": "Second Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRF", + "description": "Alarm Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OWF", + "description": "Overflow Flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RSF", + "description": "Registers Synchronized Flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNF", + "description": "Configuration Flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTOFF", + "description": "RTC operation OFF", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRLH", + "displayName": "PRLH", + "description": "RTC Prescaler Load Register High", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRLH", + "description": "RTC Prescaler Load Register High", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "PRLL", + "displayName": "PRLL", + "description": "RTC Prescaler Load Register Low", + "addressOffset": "0xC", + "size": "0x20", + "access": "write-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "PRLL", + "description": "RTC Prescaler Divider Register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DIVH", + "displayName": "DIVH", + "description": "RTC Prescaler Divider Register High", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DIVH", + "description": "RTC prescaler divider register high", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DIVL", + "displayName": "DIVL", + "description": "RTC Prescaler Divider Register Low", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "DIVL", + "description": "RTC prescaler divider register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTH", + "displayName": "CNTH", + "description": "RTC Counter Register High", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTH", + "description": "RTC counter register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTL", + "displayName": "CNTL", + "description": "RTC Counter Register Low", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTL", + "description": "RTC counter register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRH", + "displayName": "ALRH", + "description": "RTC Alarm Register High", + "addressOffset": "0x20", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRH", + "description": "RTC alarm register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRL", + "displayName": "ALRL", + "description": "RTC Alarm Register Low", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRL", + "description": "RTC alarm register low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40018000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Bits 1:0 = PWRCTRL: Power supply control bits", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register (SDIO_CLKCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Bits 31:0 = : Command argument", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "SDIO command register (SDIO_CMD)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDINDEX", + "description": "CMDINDEX", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "WAITRESP", + "description": "WAITRESP", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "WAITINT", + "description": "WAITINT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "WAITPEND", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "CPSMEN", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SDIOSuspend", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "ENCMDcompl", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "NIEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CE_ATACMD", + "description": "CE_ATACMD", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "SDIO command register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "RESPCMD", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESPI1", + "displayName": "RESPI1", + "description": "Bits 31:0 = CARDSTATUS1", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "CARDSTATUS1", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Bits 31:0 = CARDSTATUS2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "CARDSTATUS2", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Bits 31:0 = CARDSTATUS3", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "CARDSTATUS3", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Bits 31:0 = CARDSTATUS4", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "CARDSTATUS4", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Bits 31:0 = DATATIME: Data timeout period", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Bits 24:0 = DATALENGTH: Data length value", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "SDIO data control register (SDIO_DCTRL)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "DTDIR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "DTMODE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMAEN", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "DBLOCKSIZE", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "PWSTART", + "description": "PWSTART", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PWSTOP", + "description": "PWSTOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "RWMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIOEN", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Bits 24:0 = DATACOUNT: Data count value", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "SDIO status register (SDIO_STA)", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAIL", + "description": "CCRCFAIL", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "DCRCFAIL", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "CTIMEOUT", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "DTIMEOUT", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "TXUNDERR", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "RXOVERR", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "CMDREND", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "CMDSENT", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "DATAEND", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "STBITERR", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "DBCKEND", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "CMDACT", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "TXACT", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "RXACT", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "TXFIFOHE", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "RXFIFOHF", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "TXFIFOF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "RXFIFOF", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "TXFIFOE", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "RXFIFOE", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "TXDAVL", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "RXDAVL", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIOIT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAEND", + "description": "CEATAEND", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "SDIO interrupt clear register (SDIO_ICR)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILC", + "description": "CCRCFAILC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAILC", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUTC", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUTC", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERRC", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERRC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDRENDC", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENTC", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAENDC", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERRC", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKENDC", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOITC", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDC", + "description": "CEATAENDC", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "SDIO mask register (SDIO_MASK)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILIE", + "description": "CCRCFAILIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "DCRCFAILIE", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "CTIMEOUTIE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "DTIMEOUTIE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "TXUNDERRIE", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "RXOVERRIE", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "CMDRENDIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "CMDSENTIE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "DATAENDIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "STBITERRIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBACKENDIE", + "description": "DBACKENDIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "CMDACTIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "TXACTIE", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "RXACTIE", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "TXFIFOHEIE", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "RXFIFOHFIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "TXFIFOFIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "RXFIFOFIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "TXFIFOEIE", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "RXFIFOEIE", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "TXDAVLIE", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "RXDAVLIE", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIOITIE", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATENDIE", + "description": "CEATENDIE", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIF0COUNT", + "description": "FIF0COUNT", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Bits 31:0 = FIFOData: Receive and transmit FIFO data", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "FIFOData", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "TIM1", + "description": "Advanced timer", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM10", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40015000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM11", + "derivedFrom": "TIM10", + "baseAddress": "0x40015400", + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ] + }, + { + "name": "TIM12", + "derivedFrom": "TIM9", + "baseAddress": "0x40001800", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + } + ] + }, + { + "name": "TIM13", + "derivedFrom": "TIM10", + "baseAddress": "0x40001C00", + "interrupts": [ + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + } + ] + }, + { + "name": "TIM14", + "derivedFrom": "TIM10", + "baseAddress": "0x40002000", + "interrupts": [ + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM2", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "derivedFrom": "TIM2", + "baseAddress": "0x40000C00", + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ] + }, + { + "name": "TIM6", + "description": "Basic timer", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6", + "description": "TIM6 global interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40013400", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + }, + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + }, + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + }, + { + "name": "TIM8_CC", + "description": "TIM8 Capture Compare interrupt", + "value": "46" + } + ] + }, + { + "name": "TIM9", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40014C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "UART4", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART4_SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART4_DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART4_BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART4_CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART4_CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART4_CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "UART5", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40005000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART4_SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "PE", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "FE", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "NE", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "ORE", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "RXNE", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "TC", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "TXE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LBD", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART4_DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART4_BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART4_CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "SBK", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "RWU", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLEIE", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNEIE", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "TCIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXEIE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PEIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "PS", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "PCE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "WAKE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "M", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "UE", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART4_CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "ADD", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "LBDL", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LBDIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LINEN", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART4_CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USB", + "description": "Universal serial bus full-speed device interface", + "groupName": "USB", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USB_FS_WKUP", + "description": "USB Device FS Wakeup through EXTI line interrupt", + "value": "42" + } + ], + "registers": [ + { + "name": "EP0R", + "displayName": "EP0R", + "description": "Endpoint 0 register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP1R", + "displayName": "EP1R", + "description": "Endpoint 1 register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP2R", + "displayName": "EP2R", + "description": "Endpoint 2 register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP3R", + "displayName": "EP3R", + "description": "Endpoint 3 register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP4R", + "displayName": "EP4R", + "description": "Endpoint 4 register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP5R", + "displayName": "EP5R", + "description": "Endpoint 5 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP6R", + "displayName": "EP6R", + "description": "Endpoint 6 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP7R", + "displayName": "EP7R", + "description": "Endpoint 7 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNTR", + "displayName": "USB_CNTR", + "description": "Control register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000003", + "fields": [ + { + "name": "FRES", + "description": "Force USB Reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDWN", + "description": "Power down", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPMODE", + "description": "Low-power mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSUSP", + "description": "Force suspend", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RESUME", + "description": "Resume request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ESOFM", + "description": "Expected start of frame interrupt mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOFM", + "description": "Start of frame interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESETM", + "description": "USB reset interrupt mask", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSPM", + "description": "Suspend mode interrupt mask", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUPM", + "description": "Wakeup interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRM", + "description": "Error interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVRM", + "description": "Packet memory area over / underrun interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTRM", + "description": "Correct transfer interrupt mask", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ISTR", + "displayName": "ISTR", + "description": "Interrupt status register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EP_ID", + "description": "Endpoint Identifier", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIR", + "description": "Direction of transaction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ESOF", + "description": "Expected start frame", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "Reset request", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSP", + "description": "Suspend mode request", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUP", + "description": "Wakeup", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERR", + "description": "Error", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVR", + "description": "Packet memory area over / underrun", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR", + "description": "Correct transfer", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "FNR", + "displayName": "FNR", + "description": "Frame number register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FN", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "LSOF", + "description": "Lost SOF", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "LCK", + "description": "Locked", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "RXDM", + "description": "Receive data - line status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXDP", + "description": "Receive data + line status", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DADDR", + "displayName": "DADDR", + "description": "Device address", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Device address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "EF", + "description": "Enable function", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "BTABLE", + "displayName": "BTABLE", + "description": "Buffer table address", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BTABLE", + "description": "Buffer table", + "bitOffset": "3", + "bitWidth": "13" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (WWDG_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register (WWDG_CFR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB", + "description": "Timer Base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (WWDG_SR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + } + ], + "cpu": { + "name": "CM3", + "revision": "r1p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "false", + "nvicPrioBits": "4", + "deviceNumInterrupts": "43", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "qemuAlignment": "any" + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/STM32F107xx-qemu.json b/gnu-mcu-eclipse/devices/STM32F107xx-qemu.json new file mode 100644 index 0000000000..132687b23a --- /dev/null +++ b/gnu-mcu-eclipse/devices/STM32F107xx-qemu.json @@ -0,0 +1,32530 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F107xx.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.10", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F107xx.svd", + "--output", + "STM32F107xx-xsvd.json" + ], + "date": "2016-12-26T08:23:50.887Z" + }, + { + "tool": "xcdl", + "version": "1.6.10", + "command": [ + "svd-patch", + "--file", + "STM32F107xx-xsvd.json", + "--patch", + "STM32F107xx-patch.json", + "--output", + "../STM32F107xx-qemu.json", + "--remove", + "NVIC" + ], + "date": "2016-12-26T08:25:36.266Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F107xx", + "version": "1.2", + "description": "STM32F107xx", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC1", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "DUALMOD", + "description": "Dual mode selection", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sampling time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sampling time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ADC2DATA", + "description": "ADC2 data", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupts", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sampling time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sampling time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "AFIO", + "description": "Alternate function I/O", + "groupName": "AFIO", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "EVCR", + "displayName": "EVCR", + "description": "Event Control Register (AFIO_EVCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PIN", + "description": "Pin selection", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "PORT", + "description": "Port selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "EVOE", + "description": "Event Output Enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "MAPR", + "displayName": "MAPR", + "description": "AF remap and debug I/O configuration register (AFIO_MAPR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SPI1_REMAP", + "description": "SPI1 remapping", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "I2C1_REMAP", + "description": "I2C1 remapping", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART1_REMAP", + "description": "USART1 remapping", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART2_REMAP", + "description": "USART2 remapping", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART3_REMAP", + "description": "USART3 remapping", + "bitOffset": "4", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM1_REMAP", + "description": "TIM1 remapping", + "bitOffset": "6", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM2_REMAP", + "description": "TIM2 remapping", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM3_REMAP", + "description": "TIM3 remapping", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM4_REMAP", + "description": "TIM4 remapping", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CAN1_REMAP", + "description": "CAN1 remapping", + "bitOffset": "13", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PD01_REMAP", + "description": "Port D0/Port D1 mapping on OSCIN/OSCOUT", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIM5CH4_IREMAP", + "description": "Set and cleared by software", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETH_REMAP", + "description": "Ethernet MAC I/O remapping", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CAN2_REMAP", + "description": "CAN2 I/O remapping", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MII_RMII_SEL", + "description": "MII or RMII selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWJ_CFG", + "description": "Serial wire JTAG configuration", + "bitOffset": "24", + "bitWidth": "3", + "access": "write-only" + }, + { + "name": "SPI3_REMAP", + "description": "SPI3/I2S3 remapping", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIM2ITR1_IREMAP", + "description": "TIM2 internal trigger 1 remapping", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTP_PPS_REMAP", + "description": "Ethernet PTP PPS remapping", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1 (AFIO_EXTICR1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI0 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI1 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI2 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI3 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2 (AFIO_EXTICR2)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI4 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI5 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI6 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI7 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3 (AFIO_EXTICR3)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI8 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI9 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI11 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4 (AFIO_EXTICR4)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI12 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI13 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI14 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI15 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "MAPR2", + "displayName": "MAPR2", + "description": "AF remap and debug I/O configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM9_REMAP", + "description": "TIM9 remapping", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM10_REMAP", + "description": "TIM10 remapping", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM11_REMAP", + "description": "TIM11 remapping", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM13_REMAP", + "description": "TIM13 remapping", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIM14_REMAP", + "description": "TIM14 remapping", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSMC_NADV", + "description": "NADV connect/disconnect", + "bitOffset": "10", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "BKP", + "description": "Backup registers", + "groupName": "BKP", + "baseAddress": "0x40006C04", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR1", + "displayName": "DR1", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D1", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR2", + "displayName": "DR2", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D2", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR3", + "displayName": "DR3", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D3", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR4", + "displayName": "DR4", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D4", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR5", + "displayName": "DR5", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D5", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR6", + "displayName": "DR6", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D6", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR7", + "displayName": "DR7", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D7", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR8", + "displayName": "DR8", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D8", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR9", + "displayName": "DR9", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D9", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR10", + "displayName": "DR10", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D10", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR11", + "displayName": "DR11", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR11", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR12", + "displayName": "DR12", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR12", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR13", + "displayName": "DR13", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR13", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR14", + "displayName": "DR14", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D14", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR15", + "displayName": "DR15", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D15", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR16", + "displayName": "DR16", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D16", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR17", + "displayName": "DR17", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D17", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR18", + "displayName": "DR18", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D18", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR19", + "displayName": "DR19", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D19", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR20", + "displayName": "DR20", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D20", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR21", + "displayName": "DR21", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D21", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR22", + "displayName": "DR22", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D22", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR23", + "displayName": "DR23", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D23", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR24", + "displayName": "DR24", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D24", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR25", + "displayName": "DR25", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D25", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR26", + "displayName": "DR26", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D26", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR27", + "displayName": "DR27", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D27", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR28", + "displayName": "DR28", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D28", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR29", + "displayName": "DR29", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D29", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR30", + "displayName": "DR30", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D30", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR31", + "displayName": "DR31", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D31", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR32", + "displayName": "DR32", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D32", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR33", + "displayName": "DR33", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D33", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR34", + "displayName": "DR34", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D34", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR35", + "displayName": "DR35", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D35", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR36", + "displayName": "DR36", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D36", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR37", + "displayName": "DR37", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D37", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR38", + "displayName": "DR38", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D38", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR39", + "displayName": "DR39", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D39", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR40", + "displayName": "DR40", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D40", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR41", + "displayName": "DR41", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D41", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR42", + "displayName": "DR42", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D42", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RTCCR", + "displayName": "RTCCR", + "description": "RTC clock calibration register (BKP_RTCCR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CAL", + "description": "Calibration value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "CCO", + "description": "Calibration Clock Output", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ASOE", + "description": "Alarm or second output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ASOS", + "description": "Alarm or second output selection", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Backup control register (BKP_CR)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPE", + "description": "Tamper pin enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPAL", + "description": "Tamper pin active level", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "BKP_CSR control/status register", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTE", + "description": "Clear Tamper event", + "bitOffset": "0", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CTI", + "description": "Clear Tamper Interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TPIE", + "description": "Tamper Pin interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TEF", + "description": "Tamper Event Flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIF", + "description": "Tamper Interrupt Flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ] + }, + { + "name": "CAN1", + "derivedFrom": "CAN2", + "baseAddress": "0x40006400", + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupts", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ] + }, + { + "name": "CAN2", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN2_TX", + "description": "CAN2 TX interrupts", + "value": "63" + }, + { + "name": "CAN2_RX0", + "description": "CAN2 RX0 interrupts", + "value": "64" + }, + { + "name": "CAN2_RX1", + "description": "CAN2 RX1 interrupts", + "value": "65" + }, + { + "name": "CAN2_SCE", + "description": "CAN2 SCE interrupt", + "value": "66" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_ESR", + "displayName": "CAN_ESR", + "description": "CAN_ESR", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "CAN_BTR", + "displayName": "CAN_BTR", + "description": "CAN_BTR", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TI0R", + "displayName": "CAN_TI0R", + "description": "CAN_TI0R", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT0R", + "displayName": "CAN_TDT0R", + "description": "CAN_TDT0R", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL0R", + "displayName": "CAN_TDL0R", + "description": "CAN_TDL0R", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH0R", + "displayName": "CAN_TDH0R", + "description": "CAN_TDH0R", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI1R", + "displayName": "CAN_TI1R", + "description": "CAN_TI1R", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT1R", + "displayName": "CAN_TDT1R", + "description": "CAN_TDT1R", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL1R", + "displayName": "CAN_TDL1R", + "description": "CAN_TDL1R", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH1R", + "displayName": "CAN_TDH1R", + "description": "CAN_TDH1R", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI2R", + "displayName": "CAN_TI2R", + "description": "CAN_TI2R", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_TDT2R", + "displayName": "CAN_TDT2R", + "description": "CAN_TDT2R", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_TDL2R", + "displayName": "CAN_TDL2R", + "description": "CAN_TDL2R", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH2R", + "displayName": "CAN_TDH2R", + "description": "CAN_TDH2R", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI0R", + "displayName": "CAN_RI0R", + "description": "CAN_RI0R", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_RDT0R", + "displayName": "CAN_RDT0R", + "description": "CAN_RDT0R", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_RDL0R", + "displayName": "CAN_RDL0R", + "description": "CAN_RDL0R", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH0R", + "displayName": "CAN_RDH0R", + "description": "CAN_RDH0R", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI1R", + "displayName": "CAN_RI1R", + "description": "CAN_RI1R", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "CAN_RDT1R", + "displayName": "CAN_RDT1R", + "description": "CAN_RDT1R", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CAN_RDL1R", + "displayName": "CAN_RDL1R", + "description": "CAN_RDL1R", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH1R", + "displayName": "CAN_RDH1R", + "description": "CAN_RDH1R", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_FMR", + "displayName": "CAN_FMR", + "description": "CAN_FMR", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CAN2SB", + "description": "CAN2SB", + "bitOffset": "8", + "bitWidth": "6" + } + ] + }, + { + "name": "CAN_FM1R", + "displayName": "CAN_FM1R", + "description": "CAN_FM1R", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FBM14", + "description": "Filter mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FS1R", + "displayName": "CAN_FS1R", + "description": "CAN_FS1R", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "CRC calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital to analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (DAC_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "DAC software trigger register (DAC_SWTRIGR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "20", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "DAC channel1 data output register (DAC_DOR1)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "DAC channel2 data output register (DAC_DOR2)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "DBGMCU_IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "DBGMCU_CR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "DBG_IWDG_STOP", + "description": "DBG_IWDG_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBG_TIM1_STOP", + "description": "DBG_TIM1_STOP", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DBG_I2C1_SMBUS_TIMEOUT", + "description": "DBG_I2C1_SMBUS_TIMEOUT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "21", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_Channel1", + "description": "DMA1 Channel1 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Channel2", + "description": "DMA1 Channel2 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Channel3", + "description": "DMA1 Channel3 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Channel4", + "description": "DMA1 Channel4 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Channel5", + "description": "DMA1 Channel5 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Channel6", + "description": "DMA1 Channel6 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Channel7", + "description": "DMA1 Channel7 global interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "derivedFrom": "DMA1", + "baseAddress": "0x40020400", + "interrupts": [ + { + "name": "DMA2_Channel1", + "description": "DMA2 Channel1 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Channel2", + "description": "DMA2 Channel2 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Channel3", + "description": "DMA2 Channel3 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Channel4", + "description": "DMA2 Channel4 global interrupt", + "value": "59" + }, + { + "name": "DMA2_Channel5", + "description": "DMA2 Channel5 global interrupt", + "value": "60" + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "ETHERNET_DMA", + "description": "Ethernet: DMA controller operation", + "groupName": "ETHERNET", + "baseAddress": "0x40029000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DMABMR", + "displayName": "DMABMR", + "description": "Ethernet DMA bus mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20101", + "fields": [ + { + "name": "SR", + "description": "Software reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DA", + "description": "DMA Arbitration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DSL", + "description": "Descriptor skip length", + "bitOffset": "2", + "bitWidth": "5" + }, + { + "name": "PBL", + "description": "Programmable burst length", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "RTPR", + "description": "Rx Tx priority ratio", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "FB", + "description": "Fixed burst", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Rx DMA PBL", + "bitOffset": "17", + "bitWidth": "6" + }, + { + "name": "USP", + "description": "Use separate PBL", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FPM", + "description": "4xPBL mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AAB", + "description": "Address-aligned beats", + "bitOffset": "25", + "bitWidth": "1" + } + ] + }, + { + "name": "DMATPDR", + "displayName": "DMATPDR", + "description": "Ethernet DMA transmit poll demand register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPD", + "description": "Transmit poll demand", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARPDR", + "displayName": "DMARPDR", + "description": "EHERNET DMA receive poll demand register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RPD", + "description": "Receive poll demand", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARDLAR", + "displayName": "DMARDLAR", + "description": "Ethernet DMA receive descriptor list address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SRL", + "description": "Start of receive list", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMATDLAR", + "displayName": "DMATDLAR", + "description": "Ethernet DMA transmit descriptor list address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STL", + "description": "Start of transmit list", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMASR", + "displayName": "DMASR", + "description": "Ethernet DMA status register", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TS", + "description": "Transmit status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TPSS", + "description": "Transmit process stopped status", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TBUS", + "description": "Transmit buffer unavailable status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TJTS", + "description": "Transmit jabber timeout status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ROS", + "description": "Receive overflow status", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TUS", + "description": "Transmit underflow status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RS", + "description": "Receive status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RBUS", + "description": "Receive buffer unavailable status", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPSS", + "description": "Receive process stopped status", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PWTS", + "description": "Receive watchdog timeout status", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETS", + "description": "Early transmit status", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FBES", + "description": "Fatal bus error status", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERS", + "description": "Early receive status", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AIS", + "description": "Abnormal interrupt summary", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NIS", + "description": "Normal interrupt summary", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPS", + "description": "Receive process state", + "bitOffset": "17", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "TPS", + "description": "Transmit process state", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "EBS", + "description": "Error bits status", + "bitOffset": "23", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "MMC status", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PMTS", + "description": "PMT status", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "Time stamp trigger status", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DMAOMR", + "displayName": "DMAOMR", + "description": "Ethernet DMA operation mode register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SR", + "description": "SR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OSF", + "description": "OSF", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTC", + "description": "RTC", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "FUGF", + "description": "FUGF", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FEF", + "description": "FEF", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "ST", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TTC", + "description": "TTC", + "bitOffset": "14", + "bitWidth": "3" + }, + { + "name": "FTF", + "description": "FTF", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TSF", + "description": "TSF", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DFRF", + "description": "DFRF", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "RSF", + "description": "RSF", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DTCEFD", + "description": "DTCEFD", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAIER", + "displayName": "DMAIER", + "description": "Ethernet DMA interrupt enable register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIE", + "description": "Transmit interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPSIE", + "description": "Transmit process stopped interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TBUIE", + "description": "Transmit buffer unavailable interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TJTIE", + "description": "Transmit jabber timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ROIE", + "description": "Overflow interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TUIE", + "description": "Underflow interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RIE", + "description": "Receive interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RBUIE", + "description": "Receive buffer unavailable interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RPSIE", + "description": "Receive process stopped interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWTIE", + "description": "Receive watchdog timeout interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ETIE", + "description": "Early transmit interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBEIE", + "description": "Fatal bus error interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ERIE", + "description": "Early receive interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AISE", + "description": "Abnormal interrupt summary enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NISE", + "description": "Normal interrupt summary enable", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAMFBOCR", + "displayName": "DMAMFBOCR", + "description": "Ethernet DMA missed frame and buffer overflow counter register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MFC", + "description": "Missed frames by the controller", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OMFC", + "description": "Overflow bit for missed frame counter", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MFA", + "description": "Missed frames by the application", + "bitOffset": "17", + "bitWidth": "11" + }, + { + "name": "OFOC", + "description": "Overflow bit for FIFO overflow counter", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "DMACHTDR", + "displayName": "DMACHTDR", + "description": "Ethernet DMA current host transmit descriptor register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTDAP", + "description": "Host transmit descriptor address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRDR", + "displayName": "DMACHRDR", + "description": "Ethernet DMA current host receive descriptor register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRDAP", + "description": "Host receive descriptor address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHTBAR", + "displayName": "DMACHTBAR", + "description": "Ethernet DMA current host transmit buffer address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTBAP", + "description": "Host transmit buffer address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRBAR", + "displayName": "DMACHRBAR", + "description": "Ethernet DMA current host receive buffer address register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRBAP", + "description": "Host receive buffer address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ETHERNET_MAC", + "description": "Ethernet: media access control", + "groupName": "ETHERNET", + "baseAddress": "0x40028000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ETH", + "description": "Ethernet global interrupt", + "value": "61" + }, + { + "name": "ETH_WKUP", + "description": "Ethernet Wakeup through EXTI line interrupt", + "value": "62" + } + ], + "registers": [ + { + "name": "MACCR", + "displayName": "MACCR", + "description": "Ethernet MAC configuration register (ETH_MACCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00008000", + "fields": [ + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "Deferral check", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BL", + "description": "Back-off limit", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "APCS", + "description": "Automatic pad/CRC stripping", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RD", + "description": "Retry disable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IPCO", + "description": "IPv4 checksum offload", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DM", + "description": "Duplex mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LM", + "description": "Loopback mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ROD", + "description": "Receive own disable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FES", + "description": "Fast Ethernet speed", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CSD", + "description": "Carrier sense disable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "IFG", + "description": "Interframe gap", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JD", + "description": "Jabber disable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WD", + "description": "Watchdog disable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "MACFFR", + "displayName": "MACFFR", + "description": "Ethernet MAC frame filter register (ETH_MACCFFR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "Promiscuous mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hash unicast", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HM", + "description": "Hash multicast", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAIF", + "description": "Destination address inverse filtering", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PAM", + "description": "Pass all multicast", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BFD", + "description": "Broadcast frames disable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PCF", + "description": "Pass control frames", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "SAIF", + "description": "Source address inverse filtering", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SAF", + "description": "Source address filter", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HPF", + "description": "Hash or perfect filter", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "RA", + "description": "Receive all", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACHTHR", + "displayName": "MACHTHR", + "description": "Ethernet MAC hash table high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTH", + "description": "Hash table high", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACHTLR", + "displayName": "MACHTLR", + "description": "Ethernet MAC hash table low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTL", + "description": "Hash table low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACMIIAR", + "displayName": "MACMIIAR", + "description": "Ethernet MAC MII address register (ETH_MACMIIAR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MB", + "description": "MII busy", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MW", + "description": "MII write", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CR", + "description": "Clock range", + "bitOffset": "2", + "bitWidth": "3" + }, + { + "name": "MR", + "description": "MII register", + "bitOffset": "6", + "bitWidth": "5" + }, + { + "name": "PA", + "description": "PHY address", + "bitOffset": "11", + "bitWidth": "5" + } + ] + }, + { + "name": "MACMIIDR", + "displayName": "MACMIIDR", + "description": "Ethernet MAC MII data register (ETH_MACMIIDR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MD", + "description": "MII data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "MACFCR", + "displayName": "MACFCR", + "description": "Ethernet MAC flow control register (ETH_MACFCR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FCB_BPA", + "description": "Flow control busy/back pressure activate", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TFCE", + "description": "Transmit flow control enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RFCE", + "description": "Receive flow control enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UPFD", + "description": "Unicast pause frame detect", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLT", + "description": "Pause low threshold", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ZQPD", + "description": "Zero-quanta pause disable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PT", + "description": "Pass control frames", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "MACVLANTR", + "displayName": "MACVLANTR", + "description": "Ethernet MAC VLAN tag register (ETH_MACVLANTR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VLANTI", + "description": "VLAN tag identifier (for receive frames)", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "VLANTC", + "description": "12-bit VLAN tag comparison", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MACRWUFFR", + "displayName": "MACRWUFFR", + "description": "Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000" + }, + { + "name": "MACPMTCSR", + "displayName": "MACPMTCSR", + "description": "Ethernet MAC PMT control and status register (ETH_MACPMTCSR)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PD", + "description": "Power down", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MPE", + "description": "Magic Packet enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WFE", + "description": "Wakeup frame enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MPR", + "description": "Magic packet received", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WFR", + "description": "Wakeup frame received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GU", + "description": "Global unicast", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WFFRPR", + "description": "Wakeup frame filter register pointer reset", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACSR", + "displayName": "MACSR", + "description": "Ethernet MAC interrupt status register (ETH_MACSR)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTS", + "description": "PMT status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMCS", + "description": "MMC status", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MMCRS", + "description": "MMC receive status", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MMCTS", + "description": "MMC transmit status", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TSTS", + "description": "Time stamp trigger status", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACIMR", + "displayName": "MACIMR", + "description": "Ethernet MAC interrupt mask register (ETH_MACIMR)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTIM", + "description": "PMT interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSTIM", + "description": "Time stamp trigger interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA0HR", + "displayName": "MACA0HR", + "description": "Ethernet MAC address 0 high register (ETH_MACA0HR)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x0010FFFF", + "fields": [ + { + "name": "MACA0H", + "description": "MAC address0 high", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "MO", + "description": "Always 1", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "MACA0LR", + "displayName": "MACA0LR", + "description": "Ethernet MAC address 0 low register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA0L", + "description": "MAC address0 low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA1HR", + "displayName": "MACA1HR", + "description": "Ethernet MAC address 1 high register (ETH_MACA1HR)", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA1H", + "description": "MAC address1 high", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "Mask byte control", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "Source address", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "Address enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA1LR", + "displayName": "MACA1LR", + "description": "Ethernet MAC address1 low register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA1L", + "description": "MAC address1 low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA2HR", + "displayName": "MACA2HR", + "description": "Ethernet MAC address 2 high register (ETH_MACA2HR)", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0050", + "fields": [ + { + "name": "ETH_MACA2HR", + "description": "Ethernet MAC address 2 high register", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "Mask byte control", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "Source address", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "Address enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA2LR", + "displayName": "MACA2LR", + "description": "Ethernet MAC address 2 low register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA2L", + "description": "MAC address2 low", + "bitOffset": "0", + "bitWidth": "31" + } + ] + }, + { + "name": "MACA3HR", + "displayName": "MACA3HR", + "description": "Ethernet MAC address 3 high register (ETH_MACA3HR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA3H", + "description": "MAC address3 high", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "Mask byte control", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "Source address", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "Address enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA3LR", + "displayName": "MACA3LR", + "description": "Ethernet MAC address 3 low register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MBCA3L", + "description": "MAC address3 low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ETHERNET_MMC", + "description": "Ethernet: MAC management counters", + "groupName": "ETHERNET", + "baseAddress": "0x40028100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MMCCR", + "displayName": "MMCCR", + "description": "Ethernet MMC control register (ETH_MMCCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Counter reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "Counter stop rollover", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "Reset on read", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "MMC counter freeze", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIR", + "displayName": "MMCRIR", + "description": "Ethernet MMC receive interrupt register (ETH_MMCRIR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCES", + "description": "Received frames CRC error status", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAES", + "description": "Received frames alignment error status", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFS", + "description": "Received Good Unicast Frames Status", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIR", + "displayName": "MMCTIR", + "description": "Ethernet MMC transmit interrupt register (ETH_MMCTIR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCS", + "description": "Transmitted good frames single collision status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCS", + "description": "Transmitted good frames more single collision status", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFS", + "description": "Transmitted good frames status", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIMR", + "displayName": "MMCRIMR", + "description": "Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCEM", + "description": "Received frame CRC error mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAEM", + "description": "Received frames alignment error mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFM", + "description": "Received good unicast frames mask", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIMR", + "displayName": "MMCTIMR", + "description": "Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCM", + "description": "Transmitted good frames single collision mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCM", + "description": "Transmitted good frames more single collision mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFM", + "description": "Transmitted good frames mask", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTGFSCCR", + "displayName": "MMCTGFSCCR", + "description": "Ethernet MMC transmitted good frames after a single collision counter", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCC", + "description": "Transmitted good frames after a single collision counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFMSCCR", + "displayName": "MMCTGFMSCCR", + "description": "Ethernet MMC transmitted good frames after more than a single collision", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFMSCC", + "description": "Transmitted good frames after more than a single collision counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFCR", + "displayName": "MMCTGFCR", + "description": "Ethernet MMC transmitted good frames counter register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFC", + "description": "Transmitted good frames counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFCECR", + "displayName": "MMCRFCECR", + "description": "Ethernet MMC received frames with CRC error counter register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCFC", + "description": "Received frames with CRC error counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFAECR", + "displayName": "MMCRFAECR", + "description": "Ethernet MMC received frames with alignment error counter register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFAEC", + "description": "Received frames with alignment error counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRGUFCR", + "displayName": "MMCRGUFCR", + "description": "MMC received good unicast frames counter register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RGUFC", + "description": "Received good unicast frames counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ETHERNET_PTP", + "description": "Ethernet: Precision time protocol", + "groupName": "ETHERNET", + "baseAddress": "0x40028700", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "PTPTSCR", + "displayName": "PTPTSCR", + "description": "Ethernet PTP time stamp control register (ETH_PTPTSCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSFCU", + "description": "Time stamp fine or coarse update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSSTI", + "description": "Time stamp system time initialize", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSSTU", + "description": "Time stamp system time update", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSITE", + "description": "Time stamp interrupt trigger enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TSARU", + "description": "Time stamp addend register update", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPSSIR", + "displayName": "PTPSSIR", + "description": "Ethernet PTP subsecond increment register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSSI", + "description": "System time subsecond increment", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PTPTSHR", + "displayName": "PTPTSHR", + "description": "Ethernet PTP time stamp high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STS", + "description": "System time second", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLR", + "displayName": "PTPTSLR", + "description": "Ethernet PTP time stamp low register (ETH_PTPTSLR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSS", + "description": "System time subseconds", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "STPNS", + "description": "System time positive or negative sign", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSHUR", + "displayName": "PTPTSHUR", + "description": "Ethernet PTP time stamp high update register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUS", + "description": "Time stamp update second", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLUR", + "displayName": "PTPTSLUR", + "description": "Ethernet PTP time stamp low update register (ETH_PTPTSLUR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUSS", + "description": "Time stamp update subseconds", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "TSUPNS", + "description": "Time stamp update positive or negative sign", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSAR", + "displayName": "PTPTSAR", + "description": "Ethernet PTP time stamp addend register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSA", + "description": "Time stamp addend", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTHR", + "displayName": "PTPTTHR", + "description": "Ethernet PTP target time high register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSH", + "description": "Target time stamp high", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTLR", + "displayName": "PTPTTLR", + "description": "Ethernet PTP target time low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSL", + "description": "Target time stamp low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "EXTI", + "description": "EXTI", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMPER", + "description": "Tamper interrupt", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word" + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "HLFCYA", + "description": "Flash half cycle access enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "Prefetch buffer enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "Prefetch buffer status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRTERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFFC", + "fields": [ + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RDPRT", + "description": "Read protection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "10", + "bitWidth": "8" + }, + { + "name": "Data1", + "description": "Data1", + "bitOffset": "18", + "bitWidth": "8" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "GPIOA", + "description": "General purpose I/O", + "groupName": "GPIO", + "baseAddress": "0x40010800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CRL", + "displayName": "CRL", + "description": "Port configuration register low (GPIOn_CRL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE0", + "description": "Port n.0 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF0", + "description": "Port n.0 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE1", + "description": "Port n.1 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF1", + "description": "Port n.1 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE2", + "description": "Port n.2 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF2", + "description": "Port n.2 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE3", + "description": "Port n.3 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF3", + "description": "Port n.3 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE4", + "description": "Port n.4 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF4", + "description": "Port n.4 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE5", + "description": "Port n.5 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF5", + "description": "Port n.5 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE6", + "description": "Port n.6 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF6", + "description": "Port n.6 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE7", + "description": "Port n.7 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF7", + "description": "Port n.7 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "CRH", + "displayName": "CRH", + "description": "Port configuration register high (GPIOn_CRL)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE8", + "description": "Port n.8 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF8", + "description": "Port n.8 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE9", + "description": "Port n.9 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF9", + "description": "Port n.9 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE10", + "description": "Port n.10 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF10", + "description": "Port n.10 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE11", + "description": "Port n.11 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF11", + "description": "Port n.11 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE12", + "description": "Port n.12 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF12", + "description": "Port n.12 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE13", + "description": "Port n.13 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF13", + "description": "Port n.13 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE14", + "description": "Port n.14 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF14", + "description": "Port n.14 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE15", + "description": "Port n.15 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF15", + "description": "Port n.15 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Port input data register (GPIOn_IDR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "Port output data register (GPIOn_ODR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "Port bit set/reset register (GPIOn_BSRR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Set bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Set bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Set bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Set bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Set bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Set bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Set bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Set bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Set bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Set bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Set bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Set bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Set bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Set bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Set bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Set bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 2", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register (GPIOn_BRR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "Port configuration lock register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port A Lock bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port A Lock bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port A Lock bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port A Lock bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port A Lock bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port A Lock bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port A Lock bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port A Lock bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port A Lock bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port A Lock bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port A Lock bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port A Lock bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port A Lock bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port A Lock bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port A Lock bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port A Lock bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Lock key", + "bitOffset": "16", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOA", + "baseAddress": "0x40010C00", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011000", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011400", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011800", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "I2C1", + "description": "Inter integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register (IWDG_KR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register (IWDG_PR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register (IWDG_RLR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (IWDG_SR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low Power Deep Sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power Down Deep Sleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear Wake-up Flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear STANDBY Flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power Voltage Detector Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD Level Selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable Backup Domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wake-Up Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "STANDBY Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD Output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL2ON", + "description": "PLL2 enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL2RDY", + "description": "PLL2 clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL3ON", + "description": "PLL3 enable", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL3RDY", + "description": "PLL3 clock ready flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB High speed prescaler (APB2)", + "bitOffset": "11", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL entry clock source", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "OTGFSPRE", + "description": "USB OTG FS prescaler", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "4", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL2RDYF", + "description": "PLL2 Ready Interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL3RDYF", + "description": "PLL3 Ready Interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL2RDYIE", + "description": "PLL2 Ready Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL3RDYIE", + "description": "PLL3 Ready Interrupt Enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLL2RDYC", + "description": "PLL2 Ready Interrupt Clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLL3RDYC", + "description": "PLL3 Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000000", + "fields": [ + { + "name": "AFIORST", + "description": "Alternate function I/O reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPARST", + "description": "IO port A reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "IO port B reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "IO port C reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "IO port D reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPERST", + "description": "IO port E reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ADC1RST", + "description": "ADC 1 interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2RST", + "description": "ADC 2 interface reset", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "Timer 4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "Timer 5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "Timer 7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4RST", + "description": "USART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART5RST", + "description": "USART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CAN1RST", + "description": "CAN1 reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2RST", + "description": "CAN2 reset", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BKPRST", + "description": "Backup interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ETHMACEN", + "description": "Ethernet MAC clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETHMACTXEN", + "description": "Ethernet MAC TX clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ETHMACRXEN", + "description": "Ethernet MAC RX clock enable", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFIOEN", + "description": "Alternate function I/O clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPEEN", + "description": "I/O port E clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC 2 interface clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "Timer 4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "Timer 5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "Timer 7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI 3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART 3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART 4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART 5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CAN1EN", + "description": "CAN1 clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2EN", + "description": "CAN2 clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BKPEN", + "description": "Backup interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "AHBRSTR", + "displayName": "AHBRSTR", + "description": "AHB peripheral clock reset register (RCC_AHBRSTR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSRST", + "description": "USB OTG FS reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ETHMACRST", + "description": "Ethernet MAC reset", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Clock configuration register2 (RCC_CFGR2)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PREDIV1", + "description": "PREDIV1 division factor", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "PREDIV2", + "description": "PREDIV2 division factor", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "PLL2MUL", + "description": "PLL2 Multiplication Factor", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "PLL3MUL", + "description": "PLL3 Multiplication Factor", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "PREDIV1SRC", + "description": "PREDIV1 entry clock source", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2S2SRC", + "description": "I2S2 clock source", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2S3SRC", + "description": "I2S3 clock source", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "any" + }, + { + "name": "RTC", + "description": "Real time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC global interrupt", + "value": "3" + }, + { + "name": "RTCAlarm", + "description": "RTC Alarms through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "CRH", + "displayName": "CRH", + "description": "RTC Control Register High", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SECIE", + "description": "Second interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ALRIE", + "description": "Alarm interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OWIE", + "description": "Overflow interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "CRL", + "displayName": "CRL", + "description": "RTC Control Register Low", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000020", + "fields": [ + { + "name": "SECF", + "description": "Second Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRF", + "description": "Alarm Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OWF", + "description": "Overflow Flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RSF", + "description": "Registers Synchronized Flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNF", + "description": "Configuration Flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTOFF", + "description": "RTC operation OFF", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRLH", + "displayName": "PRLH", + "description": "RTC Prescaler Load Register High", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRLH", + "description": "RTC Prescaler Load Register High", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "PRLL", + "displayName": "PRLL", + "description": "RTC Prescaler Load Register Low", + "addressOffset": "0xC", + "size": "0x20", + "access": "write-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "PRLL", + "description": "RTC Prescaler Divider Register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DIVH", + "displayName": "DIVH", + "description": "RTC Prescaler Divider Register High", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DIVH", + "description": "RTC prescaler divider register high", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DIVL", + "displayName": "DIVL", + "description": "RTC Prescaler Divider Register Low", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "DIVL", + "description": "RTC prescaler divider register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTH", + "displayName": "CNTH", + "description": "RTC Counter Register High", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTH", + "description": "RTC counter register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTL", + "displayName": "CNTL", + "description": "RTC Counter Register Low", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTL", + "description": "RTC counter register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRH", + "displayName": "ALRH", + "description": "RTC Alarm Register High", + "addressOffset": "0x20", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRH", + "description": "RTC alarm register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRL", + "displayName": "ALRL", + "description": "RTC Alarm Register Low", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRL", + "description": "RTC alarm register low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "TIM1", + "description": "Advanced timer", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK", + "description": "TIM1 Break interrupt", + "value": "24" + }, + { + "name": "TIM1_UP", + "description": "TIM1 Update interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM", + "description": "TIM1 Trigger and Commutation interrupts", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM2", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "derivedFrom": "TIM2", + "baseAddress": "0x40000C00", + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ] + }, + { + "name": "TIM6", + "description": "Basic timer", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6", + "description": "TIM6 global interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "UART4", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART4 SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART4 DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART4 BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART4 CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART4 CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART4 CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "UART5", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40005000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART5 SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "PE", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "FE", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "NE", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "ORE", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "RXNE", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "TC", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "TXE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LBD", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART5 DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART5 BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART5 CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "SBK", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "RWU", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLEIE", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNEIE", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "TCIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXEIE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PEIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "PS", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "PCE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "WAKE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "M", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "UE", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART5 CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "ADD", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "LBDL", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LBDIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LINEN", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART5 CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USB_OTG_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "USB_OTG_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "7", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "USB_OTG_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "USB_OTG_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (WWDG_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register (WWDG_CFR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB", + "description": "Timer Base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (WWDG_SR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + } + ], + "cpu": { + "name": "CM3", + "revision": "r1p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "false", + "nvicPrioBits": "4", + "deviceNumInterrupts": "68", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "qemuAlignment": "any" + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/STM32F40x-qemu.json b/gnu-mcu-eclipse/devices/STM32F40x-qemu.json new file mode 100644 index 0000000000..df98ad1ddf --- /dev/null +++ b/gnu-mcu-eclipse/devices/STM32F40x-qemu.json @@ -0,0 +1,51027 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F40x.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.2", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F40x.svd", + "--output", + "STM32F40x-xsvd.json" + ], + "date": "2016-12-14T22:50:52.397Z" + }, + { + "tool": "xcdl", + "version": "1.6.8", + "command": [ + "svd-patch", + "--file", + "STM32F40x-xsvd.json", + "--patch", + "STM32F40x-patch.json", + "--output", + "../STM32F40xx-qemu.json", + "--remove", + "NVIC", + "--group-bitfield", + "RCC/PLLCFGR/PLLQ", + "--group-bitfield", + "RCC/PLLCFGR/PLLP", + "--group-bitfield", + "RCC/PLLCFGR/PLLN", + "--group-bitfield", + "RCC/PLLCFGR/PLLM", + "--group-bitfield", + "RCC/CFGR/SWS", + "--group-bitfield", + "RCC/CFGR/SW", + "--group-bitfield", + "RCC/BDCR/RTCSEL" + ], + "date": "2016-12-19T10:35:22.939Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F40x", + "version": "1.5", + "description": "STM32F40x", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC1", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OVR", + "description": "Overrun", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Resolution", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADON", + "description": "A/D Converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode (for single ADC mode)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DDS", + "description": "DMA disable selection (for single ADC mode)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EOCS", + "description": "End of conversion selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "JEXTEN", + "description": "External trigger enable for injected channels", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "EXTEN", + "description": "External trigger enable for regular channels", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "derivedFrom": "ADC1", + "baseAddress": "0x40012100", + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupts", + "value": "18" + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "derivedFrom": "ADC1", + "baseAddress": "0x40012200", + "interrupts": [ + { + "name": "ADC", + "description": "ADC3 global interrupts", + "value": "18" + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "CAN1", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupts", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ], + "registers": [ + { + "name": "MCR", + "displayName": "MCR", + "description": "Master control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00010002", + "fields": [ + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MSR", + "displayName": "MSR", + "description": "Master status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000C02", + "fields": [ + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "TSR", + "displayName": "TSR", + "description": "Transmit status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x1C000000", + "fields": [ + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "RF0R", + "displayName": "RF0R", + "description": "Receive FIFO 0 register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "RF1R", + "displayName": "RF1R", + "description": "Receive FIFO 1 register", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "ESR", + "displayName": "ESR", + "description": "Interrupt enable register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "BTR", + "displayName": "BTR", + "description": "Bit timing register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "TI0R", + "displayName": "TI0R", + "description": "TX mailbox identifier register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "TDT0R", + "displayName": "TDT0R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "TDL0R", + "displayName": "TDL0R", + "description": "Mailbox data low register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH0R", + "displayName": "TDH0R", + "description": "Mailbox data high register", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TI1R", + "displayName": "TI1R", + "description": "Mailbox identifier register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "TDT1R", + "displayName": "TDT1R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "TDL1R", + "displayName": "TDL1R", + "description": "Mailbox data low register", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH1R", + "displayName": "TDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TI2R", + "displayName": "TI2R", + "description": "Mailbox identifier register", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "TDT2R", + "displayName": "TDT2R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "TDL2R", + "displayName": "TDL2R", + "description": "Mailbox data low register", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH2R", + "displayName": "TDH2R", + "description": "Mailbox data high register", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RI0R", + "displayName": "RI0R", + "description": "Receive FIFO mailbox identifier register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "RDT0R", + "displayName": "RDT0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "RDL0R", + "displayName": "RDL0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH0R", + "displayName": "RDH0R", + "description": "Receive FIFO mailbox data high register", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RI1R", + "displayName": "RI1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "RDT1R", + "displayName": "RDT1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "RDL1R", + "displayName": "RDL1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH1R", + "displayName": "RDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "FMR", + "displayName": "FMR", + "description": "Filter master register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2A1C0E01", + "fields": [ + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CAN2SB", + "description": "CAN2SB", + "bitOffset": "8", + "bitWidth": "6" + } + ] + }, + { + "name": "FM1R", + "displayName": "FM1R", + "description": "Filter mode register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FBM14", + "description": "Filter mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FS1R", + "displayName": "FS1R", + "description": "Filter scale register", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FFA1R", + "displayName": "FFA1R", + "description": "Filter FIFO assignment register", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FA1R", + "displayName": "FA1R", + "description": "Filter activation register", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "CAN" + }, + { + "name": "CAN2", + "derivedFrom": "CAN1", + "baseAddress": "0x40006800", + "interrupts": [ + { + "name": "CAN2_TX", + "description": "CAN2 TX interrupts", + "value": "63" + }, + { + "name": "CAN2_RX0", + "description": "CAN2 RX0 interrupts", + "value": "64" + }, + { + "name": "CAN2_RX1", + "description": "CAN2 RX1 interrupts", + "value": "65" + }, + { + "name": "CAN2_SCE", + "description": "CAN2 SCE interrupt", + "value": "66" + } + ], + "qemuGroupName": "CAN" + }, + { + "name": "CRC", + "description": "Cryptographic processor", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Control regidter", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "C_ADC", + "description": "Common ADC registers", + "groupName": "ADC", + "baseAddress": "0x40012300", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "ADC Common status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD1", + "description": "Analog watchdog flag of ADC 1", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC1", + "description": "End of conversion of ADC 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC1", + "description": "Injected channel end of conversion of ADC 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT1", + "description": "Injected channel Start flag of ADC 1", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT1", + "description": "Regular channel Start flag of ADC 1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OVR1", + "description": "Overrun flag of ADC 1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWD2", + "description": "Analog watchdog flag of ADC 2", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EOC2", + "description": "End of conversion of ADC 2", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JEOC2", + "description": "Injected channel end of conversion of ADC 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "JSTRT2", + "description": "Injected channel Start flag of ADC 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STRT2", + "description": "Regular channel Start flag of ADC 2", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OVR2", + "description": "Overrun flag of ADC 2", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AWD3", + "description": "Analog watchdog flag of ADC 3", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOC3", + "description": "End of conversion of ADC 3", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "JEOC3", + "description": "Injected channel end of conversion of ADC 3", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "JSTRT3", + "description": "Injected channel Start flag of ADC 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STRT3", + "description": "Regular channel Start flag of ADC 3", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "OVR3", + "description": "Overrun flag of ADC3", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "ADC common control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MULT", + "description": "Multi ADC mode selection", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DELAY", + "description": "Delay between 2 sampling phases", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DDS", + "description": "DMA disable selection for multi-ADC mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode for multi ADC mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "VBATE", + "description": "VBAT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "CDR", + "displayName": "CDR", + "description": "ADC common regular data register for dual and triple modes", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA1", + "description": "1st data item of a pair of regular conversions", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "DATA2", + "description": "2nd data item of a pair of regular conversions", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMAUDRIE1", + "description": "DAC channel1 DMA Underrun Interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DMAUDRIE2", + "description": "DAC channel2 DMA underrun interrupt enable", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "Channel2 12-bit right aligned data holding register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "Channel2 12-bit left aligned data holding register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "Channel2 8-bit right-aligned data holding register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "20", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "Channel2 data output register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DBGMCU_IDCODE", + "displayName": "DBGMCU_IDCODE", + "description": "IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x10006411", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DBGMCU_CR", + "displayName": "DBGMCU_CR", + "description": "Control Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "DBG_TIM8_STOP", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB1_FZ", + "displayName": "DBGMCU_APB1_FZ", + "description": "Debug MCU APB1 Freeze registe", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3 _STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DBG_TIM12_STOP", + "description": "DBG_TIM12_STOP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DBG_TIM13_STOP", + "description": "DBG_TIM13_STOP", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DBG_TIM14_STOP", + "description": "DBG_TIM14_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDEG_STOP", + "description": "DBG_IWDEG_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_J2C1_SMBUS_TIMEOUT", + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DBG_J2C2_SMBUS_TIMEOUT", + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBG_J2C3SMBUS_TIMEOUT", + "description": "DBG_J2C3SMBUS_TIMEOUT", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB2_FZ", + "displayName": "DBGMCU_APB2_FZ", + "description": "Debug MCU APB2 Freeze registe", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM1_STOP", + "description": "TIM1 counter stopped when core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "TIM8 counter stopped when core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM9_STOP", + "description": "TIM9 counter stopped when core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM10_STOP", + "description": "TIM10 counter stopped when core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM11_STOP", + "description": "TIM11 counter stopped when core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DCMI", + "description": "Digital camera interface", + "groupName": "DCMI", + "baseAddress": "0x50050000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DCMI", + "description": "DCMI global interrupt", + "value": "78" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CAPTURE", + "description": "Capture enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CM", + "description": "Capture mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CROP", + "description": "Crop feature", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JPEG", + "description": "JPEG format", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ESS", + "description": "Embedded synchronization select", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PCKPOL", + "description": "Pixel clock polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HSPOL", + "description": "Horizontal synchronization polarity", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "VSPOL", + "description": "Vertical synchronization polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FCRC", + "description": "Frame capture rate control", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "EDM", + "description": "Extended data mode", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "ENABLE", + "description": "DCMI enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "HSYNC", + "description": "HSYNC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "VSYNC", + "description": "VSYNC", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FNE", + "description": "FIFO not empty", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "RIS", + "displayName": "RIS", + "description": "Raw interrupt status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_RIS", + "description": "Capture complete raw interrupt status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_RIS", + "description": "Overrun raw interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_RIS", + "description": "Synchronization error raw interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_RIS", + "description": "VSYNC raw interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_RIS", + "description": "Line raw interrupt status", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_IE", + "description": "Capture complete interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_IE", + "description": "Overrun interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_IE", + "description": "Synchronization error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_IE", + "description": "VSYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_IE", + "description": "Line interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "MIS", + "displayName": "MIS", + "description": "Masked interrupt status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_MIS", + "description": "Capture complete masked interrupt status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_MIS", + "description": "Overrun masked interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_MIS", + "description": "Synchronization error masked interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_MIS", + "description": "VSYNC masked interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_MIS", + "description": "Line masked interrupt status", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_ISC", + "description": "Capture complete interrupt status clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_ISC", + "description": "Overrun interrupt status clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_ISC", + "description": "Synchronization error interrupt status clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_ISC", + "description": "Vertical synch interrupt status clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_ISC", + "description": "Line interrupt status clear", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "ESCR", + "displayName": "ESCR", + "description": "Embedded synchronization code register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FSC", + "description": "Frame start delimiter code", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LSC", + "description": "Line start delimiter code", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "LEC", + "description": "Line end delimiter code", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "FEC", + "description": "Frame end delimiter code", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ESUR", + "displayName": "ESUR", + "description": "Embedded synchronization unmask register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FSU", + "description": "Frame start delimiter unmask", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LSU", + "description": "Line start delimiter unmask", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "LEU", + "description": "Line end delimiter unmask", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "FEU", + "description": "Frame end delimiter unmask", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CWSTRT", + "displayName": "CWSTRT", + "description": "Crop window start", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "HOFFCNT", + "description": "Horizontal offset count", + "bitOffset": "0", + "bitWidth": "14" + }, + { + "name": "VST", + "description": "Vertical start line count", + "bitOffset": "16", + "bitWidth": "13" + } + ] + }, + { + "name": "CWSIZE", + "displayName": "CWSIZE", + "description": "Crop window size", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CAPCNT", + "description": "Capture count", + "bitOffset": "0", + "bitWidth": "14" + }, + { + "name": "VLINE", + "description": "Vertical line count", + "bitOffset": "16", + "bitWidth": "14" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "Byte0", + "description": "Data byte 0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "Byte1", + "description": "Data byte 1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "Byte2", + "description": "Data byte 2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "Byte3", + "description": "Data byte 3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "DMA1", + "derivedFrom": "DMA2", + "baseAddress": "0x40026000", + "interrupts": [ + { + "name": "DMA1_Stream0", + "description": "DMA1 Stream0 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Stream1", + "description": "DMA1 Stream1 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Stream2", + "description": "DMA1 Stream2 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Stream3", + "description": "DMA1 Stream3 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Stream4", + "description": "DMA1 Stream4 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Stream5", + "description": "DMA1 Stream5 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Stream6", + "description": "DMA1 Stream6 global interrupt", + "value": "17" + }, + { + "name": "DMA1_Stream7", + "description": "DMA1 Stream7 global interrupt", + "value": "47" + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40026400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA2_Stream0", + "description": "DMA2 Stream0 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Stream1", + "description": "DMA2 Stream1 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Stream2", + "description": "DMA2 Stream2 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Stream3", + "description": "DMA2 Stream3 global interrupt", + "value": "59" + }, + { + "name": "DMA2_Stream4", + "description": "DMA2 Stream4 global interrupt", + "value": "60" + }, + { + "name": "DMA2_Stream5", + "description": "DMA2 Stream5 global interrupt", + "value": "68" + }, + { + "name": "DMA2_Stream6", + "description": "DMA2 Stream6 global interrupt", + "value": "69" + }, + { + "name": "DMA2_Stream7", + "description": "DMA2 Stream7 global interrupt", + "value": "70" + } + ], + "registers": [ + { + "name": "LISR", + "displayName": "LISR", + "description": "Low interrupt status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FEIF0", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIF0", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF0", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "HTIF0", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF0", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FEIF1", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMEIF1", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FEIF2", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMEIF2", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FEIF3", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMEIF3", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "HISR", + "displayName": "HISR", + "description": "High interrupt status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FEIF4", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIF4", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FEIF5", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMEIF5", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FEIF6", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMEIF6", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FEIF7", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMEIF7", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "LIFCR", + "displayName": "LIFCR", + "description": "Low interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFEIF0", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CDMEIF0", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF0", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHTIF0", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF0", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CFEIF1", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CDMEIF1", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CFEIF2", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CDMEIF2", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CFEIF3", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CDMEIF3", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "HIFCR", + "displayName": "HIFCR", + "description": "High interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFEIF4", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CDMEIF4", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CFEIF5", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CDMEIF5", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CFEIF6", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CDMEIF6", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CFEIF7", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CDMEIF7", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "S0CR", + "displayName": "S0CR", + "description": "Stream x configuration register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S0NDTR", + "displayName": "S0NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S0PAR", + "displayName": "S0PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M0AR", + "displayName": "S0M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M1AR", + "displayName": "S0M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0FCR", + "displayName": "S0FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S1CR", + "displayName": "S1CR", + "description": "Stream x configuration register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S1NDTR", + "displayName": "S1NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S1PAR", + "displayName": "S1PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M0AR", + "displayName": "S1M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M1AR", + "displayName": "S1M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1FCR", + "displayName": "S1FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x3C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S2CR", + "displayName": "S2CR", + "description": "Stream x configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S2NDTR", + "displayName": "S2NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S2PAR", + "displayName": "S2PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M0AR", + "displayName": "S2M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M1AR", + "displayName": "S2M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2FCR", + "displayName": "S2FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S3CR", + "displayName": "S3CR", + "description": "Stream x configuration register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S3NDTR", + "displayName": "S3NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S3PAR", + "displayName": "S3PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M0AR", + "displayName": "S3M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M1AR", + "displayName": "S3M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3FCR", + "displayName": "S3FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x6C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S4CR", + "displayName": "S4CR", + "description": "Stream x configuration register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S4NDTR", + "displayName": "S4NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S4PAR", + "displayName": "S4PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M0AR", + "displayName": "S4M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M1AR", + "displayName": "S4M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4FCR", + "displayName": "S4FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S5CR", + "displayName": "S5CR", + "description": "Stream x configuration register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S5NDTR", + "displayName": "S5NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S5PAR", + "displayName": "S5PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M0AR", + "displayName": "S5M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M1AR", + "displayName": "S5M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5FCR", + "displayName": "S5FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x9C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S6CR", + "displayName": "S6CR", + "description": "Stream x configuration register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S6NDTR", + "displayName": "S6NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S6PAR", + "displayName": "S6PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M0AR", + "displayName": "S6M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M1AR", + "displayName": "S6M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6FCR", + "displayName": "S6FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xB4", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S7CR", + "displayName": "S7CR", + "description": "Stream x configuration register", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S7NDTR", + "displayName": "S7NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xBC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S7PAR", + "displayName": "S7PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xC0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M0AR", + "displayName": "S7M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M1AR", + "displayName": "S7M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xC8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7FCR", + "displayName": "S7FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xCC", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40013C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMP_STAMP", + "description": "Tamper and TimeStamp interrupts through the EXTI line", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Rising trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Rising trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Rising trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Falling trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Falling trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Falling trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SWIER20", + "description": "Software Interrupt on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SWIER21", + "description": "Software Interrupt on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWIER22", + "description": "Software Interrupt on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PR20", + "description": "Pending bit 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PR21", + "description": "Pending bit 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PR22", + "description": "Pending bit 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "Ethernet_DMA", + "description": "Ethernet: DMA controller operation", + "groupName": "Ethernet", + "baseAddress": "0x40029000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DMABMR", + "displayName": "DMABMR", + "description": "Ethernet DMA bus mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "SR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DA", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DSL", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "5" + }, + { + "name": "EDFE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PBL", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "RTPR", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "FB", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "6" + }, + { + "name": "USP", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FPM", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AAB", + "description": "No description available", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MB", + "description": "No description available", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMATPDR", + "displayName": "DMATPDR", + "description": "Ethernet DMA transmit poll demand register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARPDR", + "displayName": "DMARPDR", + "description": "EHERNET DMA receive poll demand register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RPD", + "description": "RPD", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARDLAR", + "displayName": "DMARDLAR", + "description": "Ethernet DMA receive descriptor list address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SRL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMATDLAR", + "displayName": "DMATDLAR", + "description": "Ethernet DMA transmit descriptor list address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMASR", + "displayName": "DMASR", + "description": "Ethernet DMA status register", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TPSS", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TBUS", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TJTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ROS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TUS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RBUS", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPSS", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PWTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETS", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FBES", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AIS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NIS", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "TPS", + "description": "No description available", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "EBS", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DMAOMR", + "displayName": "DMAOMR", + "description": "Ethernet DMA operation mode register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SR", + "description": "SR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OSF", + "description": "OSF", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTC", + "description": "RTC", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "FUGF", + "description": "FUGF", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FEF", + "description": "FEF", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "ST", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TTC", + "description": "TTC", + "bitOffset": "14", + "bitWidth": "3" + }, + { + "name": "FTF", + "description": "FTF", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TSF", + "description": "TSF", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DFRF", + "description": "DFRF", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "RSF", + "description": "RSF", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DTCEFD", + "description": "DTCEFD", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAIER", + "displayName": "DMAIER", + "description": "Ethernet DMA interrupt enable register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPSIE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TBUIE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TJTIE", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ROIE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TUIE", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RIE", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RBUIE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RPSIE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWTIE", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ETIE", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBEIE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ERIE", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AISE", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NISE", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAMFBOCR", + "displayName": "DMAMFBOCR", + "description": "Ethernet DMA missed frame and buffer overflow counter register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OMFC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MFA", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "11" + }, + { + "name": "OFOC", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "DMARSWTR", + "displayName": "DMARSWTR", + "description": "Ethernet DMA receive status watchdog timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RSWTC", + "description": "RSWTC", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DMACHTDR", + "displayName": "DMACHTDR", + "description": "Ethernet DMA current host transmit descriptor register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTDAP", + "description": "HTDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRDR", + "displayName": "DMACHRDR", + "description": "Ethernet DMA current host receive descriptor register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRDAP", + "description": "HRDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHTBAR", + "displayName": "DMACHTBAR", + "description": "Ethernet DMA current host transmit buffer address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRBAR", + "displayName": "DMACHRBAR", + "description": "Ethernet DMA current host receive buffer address register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_MAC", + "description": "Ethernet: media access control (MAC)", + "groupName": "Ethernet", + "baseAddress": "0x40028000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ETH", + "description": "Ethernet global interrupt", + "value": "61" + }, + { + "name": "ETH_WKUP", + "description": "Ethernet Wakeup through EXTI line interrupt", + "value": "62" + } + ], + "registers": [ + { + "name": "MACCR", + "displayName": "MACCR", + "description": "Ethernet MAC configuration register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0008000", + "fields": [ + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "DC", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BL", + "description": "BL", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "APCS", + "description": "APCS", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RD", + "description": "RD", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IPCO", + "description": "IPCO", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DM", + "description": "DM", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LM", + "description": "LM", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ROD", + "description": "ROD", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FES", + "description": "FES", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CSD", + "description": "CSD", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "IFG", + "description": "IFG", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JD", + "description": "JD", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WD", + "description": "WD", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CSTF", + "description": "CSTF", + "bitOffset": "25", + "bitWidth": "1" + } + ] + }, + { + "name": "MACFFR", + "displayName": "MACFFR", + "description": "Ethernet MAC frame filter register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HM", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAIF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RAM", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BFD", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PCF", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SAIF", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SAF", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HPF", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RA", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACHTHR", + "displayName": "MACHTHR", + "description": "Ethernet MAC hash table high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACHTLR", + "displayName": "MACHTLR", + "description": "Ethernet MAC hash table low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACMIIAR", + "displayName": "MACMIIAR", + "description": "Ethernet MAC MII address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MW", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "3" + }, + { + "name": "MR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "5" + }, + { + "name": "PA", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "5" + } + ] + }, + { + "name": "MACMIIDR", + "displayName": "MACMIIDR", + "description": "Ethernet MAC MII data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "MACFCR", + "displayName": "MACFCR", + "description": "Ethernet MAC flow control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FCB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TFCE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RFCE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UPFD", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLT", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ZQPD", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "MACVLANTR", + "displayName": "MACVLANTR", + "description": "Ethernet MAC VLAN tag register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VLANTI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "VLANTC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MACPMTCSR", + "displayName": "MACPMTCSR", + "description": "Ethernet MAC PMT control and status register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MPE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WFE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MPR", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WFR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GU", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WFFRPR", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACDBGR", + "displayName": "MACDBGR", + "description": "Ethernet MAC debug register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "CR", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "CSR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "ROR", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "MCF", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "MCP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "MCFHP", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MACSR", + "displayName": "MACSR", + "description": "Ethernet MAC interrupt status register", + "addressOffset": "0x38", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCRS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCTS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "MACIMR", + "displayName": "MACIMR", + "description": "Ethernet MAC interrupt mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTIM", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSTIM", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA0HR", + "displayName": "MACA0HR", + "description": "Ethernet MAC address 0 high register", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x0010FFFF", + "fields": [ + { + "name": "MACA0H", + "description": "MAC address0 high", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "MO", + "description": "Always 1", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "MACA0LR", + "displayName": "MACA0LR", + "description": "Ethernet MAC address 0 low register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA0L", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA1HR", + "displayName": "MACA1HR", + "description": "Ethernet MAC address 1 high register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA1H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA1LR", + "displayName": "MACA1LR", + "description": "Ethernet MAC address1 low register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA1LR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA2HR", + "displayName": "MACA2HR", + "description": "Ethernet MAC address 2 high register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MAC2AH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA2LR", + "displayName": "MACA2LR", + "description": "Ethernet MAC address 2 low register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA2L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + } + ] + }, + { + "name": "MACA3HR", + "displayName": "MACA3HR", + "description": "Ethernet MAC address 3 high register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA3H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA3LR", + "displayName": "MACA3LR", + "description": "Ethernet MAC address 3 low register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MBCA3L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_MMC", + "description": "Ethernet: MAC management counters", + "groupName": "Ethernet", + "baseAddress": "0x40028100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MMCCR", + "displayName": "MMCCR", + "description": "Ethernet MMC control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIR", + "displayName": "MMCRIR", + "description": "Ethernet MMC receive interrupt register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCES", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAES", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIR", + "displayName": "MMCTIR", + "description": "Ethernet MMC transmit interrupt register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFS", + "description": "No description available", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIMR", + "displayName": "MMCRIMR", + "description": "Ethernet MMC receive interrupt mask register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCEM", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAEM", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFM", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIMR", + "displayName": "MMCTIMR", + "description": "Ethernet MMC transmit interrupt mask register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCM", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCM", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFM", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTGFSCCR", + "displayName": "MMCTGFSCCR", + "description": "Ethernet MMC transmitted good frames after a single collision counter", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFMSCCR", + "displayName": "MMCTGFMSCCR", + "description": "Ethernet MMC transmitted good frames after more than a single collision", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFMSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFCR", + "displayName": "MMCTGFCR", + "description": "Ethernet MMC transmitted good frames counter register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFC", + "description": "HTL", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFCECR", + "displayName": "MMCRFCECR", + "description": "Ethernet MMC received frames with CRC error counter register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFAECR", + "displayName": "MMCRFAECR", + "description": "Ethernet MMC received frames with alignment error counter register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFAEC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRGUFCR", + "displayName": "MMCRGUFCR", + "description": "MMC received good unicast frames counter register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RGUFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_PTP", + "description": "Ethernet: Precision time protocol", + "groupName": "Ethernet", + "baseAddress": "0x40028700", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "PTPTSCR", + "displayName": "PTPTSCR", + "description": "Ethernet PTP time stamp control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "TSE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSFCU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSSTI", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSSTU", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSITE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TTSARU", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TSSARFE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TSSSR", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TSPTPPSV2E", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TSSPTPOEFE", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TSSIPV6FE", + "description": "No description available", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TSSIPV4FE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TSSEME", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TSSMRME", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TSCNT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "TSPFFMAE", + "description": "No description available", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPSSIR", + "displayName": "PTPSSIR", + "description": "Ethernet PTP subsecond increment register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSSI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PTPTSHR", + "displayName": "PTPTSHR", + "description": "Ethernet PTP time stamp high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLR", + "displayName": "PTPTSLR", + "description": "Ethernet PTP time stamp low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "STPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSHUR", + "displayName": "PTPTSHUR", + "description": "Ethernet PTP time stamp high update register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLUR", + "displayName": "PTPTSLUR", + "description": "Ethernet PTP time stamp low update register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "TSUPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSAR", + "displayName": "PTPTSAR", + "description": "Ethernet PTP time stamp addend register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSA", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTHR", + "displayName": "PTPTTHR", + "description": "Ethernet PTP target time high register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSH", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTLR", + "displayName": "PTPTTLR", + "description": "Ethernet PTP target time low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSSR", + "displayName": "PTPTSSR", + "description": "Ethernet PTP time stamp status register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPPPSCR", + "displayName": "PTPPPSCR", + "description": "Ethernet PTP PPS control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "TSSO", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "TSTTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40023C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bitOffset": "11", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OPERR", + "description": "Operation error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGPERR", + "description": "Programming parallelism error", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x80000000", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SER", + "description": "Sector Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SNB", + "description": "Sector number", + "bitOffset": "3", + "bitWidth": "4" + }, + { + "name": "PSIZE", + "description": "Program size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OPTCR", + "displayName": "OPTCR", + "description": "Flash option control register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "OPTLOCK", + "description": "Option lock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OPTSTRT", + "description": "Option start", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "WDG_SW", + "description": "WDG_SW User option bytes", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP User option bytes", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY User option bytes", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Read protect", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "FSMC", + "description": "Flexible static memory controller", + "groupName": "FSMC", + "baseAddress": "0xA0000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FSMC", + "description": "FSMC global interrupt", + "value": "48" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "SRAM/NOR-Flash chip-select control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR1", + "displayName": "BTR1", + "description": "SRAM/NOR-Flash chip-select timing register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "SRAM/NOR-Flash chip-select control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR2", + "displayName": "BTR2", + "description": "SRAM/NOR-Flash chip-select timing register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR3", + "displayName": "BCR3", + "description": "SRAM/NOR-Flash chip-select control register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR3", + "displayName": "BTR3", + "description": "SRAM/NOR-Flash chip-select timing register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR4", + "displayName": "BCR4", + "description": "SRAM/NOR-Flash chip-select control register 4", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR4", + "displayName": "BTR4", + "description": "SRAM/NOR-Flash chip-select timing register 4", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "PCR2", + "displayName": "PCR2", + "description": "PC Card/NAND Flash control register 2", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "FIFO status and interrupt register 2", + "addressOffset": "0x64", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM2", + "displayName": "PMEM2", + "description": "Common memory space timing register 2", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT2", + "displayName": "PATT2", + "description": "Attribute memory space timing register 2", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR2", + "displayName": "ECCR2", + "description": "ECC result register 2", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR3", + "displayName": "PCR3", + "description": "PC Card/NAND Flash control register 3", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR3", + "displayName": "SR3", + "description": "FIFO status and interrupt register 3", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM3", + "displayName": "PMEM3", + "description": "Common memory space timing register 3", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT3", + "displayName": "PATT3", + "description": "Attribute memory space timing register 3", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR3", + "displayName": "ECCR3", + "description": "ECC result register 3", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR4", + "displayName": "PCR4", + "description": "PC Card/NAND Flash control register 4", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR4", + "displayName": "SR4", + "description": "FIFO status and interrupt register 4", + "addressOffset": "0xA4", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM4", + "displayName": "PMEM4", + "description": "Common memory space timing register 4", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT4", + "displayName": "PATT4", + "description": "Attribute memory space timing register 4", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PIO4", + "displayName": "PIO4", + "description": "I/O space timing register 4", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "IOSETx", + "description": "IOSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IOWAITx", + "description": "IOWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IOHOLDx", + "description": "IOHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IOHIZx", + "description": "IOHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "BWTR1", + "displayName": "BWTR1", + "description": "SRAM/NOR-Flash write timing registers 1", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR2", + "displayName": "BWTR2", + "description": "SRAM/NOR-Flash write timing registers 2", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR3", + "displayName": "BWTR3", + "description": "SRAM/NOR-Flash write timing registers 3", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR4", + "displayName": "BWTR4", + "description": "SRAM/NOR-Flash write timing registers 4", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xA8000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x64000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000280", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000C0", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000100", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOI", + "baseAddress": "0x40020800", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOI", + "baseAddress": "0X40020C00", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021000", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021400", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOG", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021800", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOH", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021C00", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOI", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "I2C1", + "derivedFrom": "I2C3", + "baseAddress": "0x40005400", + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "derivedFrom": "I2C3", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C3", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2S2ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40003400" + }, + { + "name": "I2S3ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40004000" + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value (write only, read 0000h)", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_FS_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS_WKUP", + "description": "USB On-The-Go FS Wakeup through EXTI line interrupt", + "value": "42" + }, + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "OTG_FS_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_HS_DEVICE", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_DCFG", + "displayName": "OTG_HS_DCFG", + "description": "OTG_HS device configuration register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Nonzero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic (micro)frame interval", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "PERSCHIVL", + "description": "Periodic scheduling interval", + "bitOffset": "24", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DCTL", + "displayName": "OTG_HS_DCTL", + "description": "OTG_HS device control register", + "addressOffset": "0x4", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DSTS", + "displayName": "OTG_HS_DSTS", + "description": "OTG_HS device status register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "OTG_HS_DIEPMSK", + "displayName": "OTG_HS_DIEPMSK", + "description": "OTG_HS device IN endpoint common interrupt mask register", + "addressOffset": "0x10", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPMSK", + "displayName": "OTG_HS_DOEPMSK", + "description": "OTG_HS device OUT endpoint common interrupt mask register", + "addressOffset": "0x14", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OPEM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BOIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DAINT", + "displayName": "OTG_HS_DAINT", + "description": "OTG_HS device all endpoints interrupt register", + "addressOffset": "0x18", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DAINTMSK", + "displayName": "OTG_HS_DAINTMSK", + "description": "OTG_HS all endpoints interrupt mask register", + "addressOffset": "0x1C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPM", + "description": "OUT EP interrupt mask bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSDIS", + "displayName": "OTG_HS_DVBUSDIS", + "description": "OTG_HS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSPULSE", + "displayName": "OTG_HS_DVBUSPULSE", + "description": "OTG_HS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "OTG_HS_DTHRCTL", + "displayName": "OTG_HS_DTHRCTL", + "description": "OTG_HS Device threshold control register", + "addressOffset": "0x30", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "NONISOTHREN", + "description": "Nonisochronous IN endpoints threshold enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ISOTHREN", + "description": "ISO IN endpoint threshold enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXTHRLEN", + "description": "Transmit threshold length", + "bitOffset": "2", + "bitWidth": "9" + }, + { + "name": "RXTHREN", + "description": "Receive threshold enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXTHRLEN", + "description": "Receive threshold length", + "bitOffset": "17", + "bitWidth": "9" + }, + { + "name": "ARPEN", + "description": "Arbiter parking enable", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEMPMSK", + "displayName": "OTG_HS_DIEPEMPMSK", + "description": "OTG_HS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DEACHINT", + "displayName": "OTG_HS_DEACHINT", + "description": "OTG_HS device each endpoint interrupt register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INT", + "description": "IN endpoint 1interrupt bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INT", + "description": "OUT endpoint 1 interrupt bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DEACHINTMSK", + "displayName": "OTG_HS_DEACHINTMSK", + "description": "OTG_HS device each endpoint interrupt register mask", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INTM", + "description": "IN Endpoint 1 interrupt mask bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INTM", + "description": "OUT Endpoint 1 interrupt mask bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEACHMSK1", + "displayName": "OTG_HS_DIEPEACHMSK1", + "description": "OTG_HS device each in endpoint-1 interrupt register", + "addressOffset": "0x40", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPEACHMSK1", + "displayName": "OTG_HS_DOEPEACHMSK1", + "description": "OTG_HS device each OUT endpoint-1 interrupt register", + "addressOffset": "0x80", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BERRM", + "description": "Bubble error interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "NYETM", + "description": "NYET interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL0", + "displayName": "OTG_HS_DIEPCTL0", + "description": "OTG device endpoint-0 control register", + "addressOffset": "0x100", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL1", + "displayName": "OTG_HS_DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL2", + "displayName": "OTG_HS_DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL3", + "displayName": "OTG_HS_DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL4", + "displayName": "OTG_HS_DIEPCTL4", + "description": "OTG device endpoint-4 control register", + "addressOffset": "0x180", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL5", + "displayName": "OTG_HS_DIEPCTL5", + "description": "OTG device endpoint-5 control register", + "addressOffset": "0x1A0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL6", + "displayName": "OTG_HS_DIEPCTL6", + "description": "OTG device endpoint-6 control register", + "addressOffset": "0x1C0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL7", + "displayName": "OTG_HS_DIEPCTL7", + "description": "OTG device endpoint-7 control register", + "addressOffset": "0x1E0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT0", + "displayName": "OTG_HS_DIEPINT0", + "description": "OTG device endpoint-0 interrupt register", + "addressOffset": "0x108", + "size": "32", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT1", + "displayName": "OTG_HS_DIEPINT1", + "description": "OTG device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT2", + "displayName": "OTG_HS_DIEPINT2", + "description": "OTG device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT3", + "displayName": "OTG_HS_DIEPINT3", + "description": "OTG device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT4", + "displayName": "OTG_HS_DIEPINT4", + "description": "OTG device endpoint-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT5", + "displayName": "OTG_HS_DIEPINT5", + "description": "OTG device endpoint-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT6", + "displayName": "OTG_HS_DIEPINT6", + "description": "OTG device endpoint-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT7", + "displayName": "OTG_HS_DIEPINT7", + "description": "OTG device endpoint-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ0", + "displayName": "OTG_HS_DIEPTSIZ0", + "description": "OTG_HS device IN endpoint 0 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA1", + "displayName": "OTG_HS_DIEPDMA1", + "description": "OTG_HS device endpoint-1 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA2", + "displayName": "OTG_HS_DIEPDMA2", + "description": "OTG_HS device endpoint-2 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA3", + "displayName": "OTG_HS_DIEPDMA3", + "description": "OTG_HS device endpoint-3 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA4", + "displayName": "OTG_HS_DIEPDMA4", + "description": "OTG_HS device endpoint-4 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA5", + "displayName": "OTG_HS_DIEPDMA5", + "description": "OTG_HS device endpoint-5 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS0", + "displayName": "OTG_HS_DTXFSTS0", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS1", + "displayName": "OTG_HS_DTXFSTS1", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS2", + "displayName": "OTG_HS_DTXFSTS2", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS3", + "displayName": "OTG_HS_DTXFSTS3", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS4", + "displayName": "OTG_HS_DTXFSTS4", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x198", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS5", + "displayName": "OTG_HS_DTXFSTS5", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x1B8", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ1", + "displayName": "OTG_HS_DIEPTSIZ1", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ2", + "displayName": "OTG_HS_DIEPTSIZ2", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ3", + "displayName": "OTG_HS_DIEPTSIZ3", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ4", + "displayName": "OTG_HS_DIEPTSIZ4", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ5", + "displayName": "OTG_HS_DIEPTSIZ5", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL0", + "displayName": "OTG_HS_DOEPCTL0", + "description": "OTG_HS device control OUT endpoint 0 control register", + "addressOffset": "0x300", + "size": "32", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL1", + "displayName": "OTG_HS_DOEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x320", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL2", + "displayName": "OTG_HS_DOEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x340", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL3", + "displayName": "OTG_HS_DOEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x360", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPINT0", + "displayName": "OTG_HS_DOEPINT0", + "description": "OTG_HS device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "32", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT1", + "displayName": "OTG_HS_DOEPINT1", + "description": "OTG_HS device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT2", + "displayName": "OTG_HS_DOEPINT2", + "description": "OTG_HS device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT3", + "displayName": "OTG_HS_DOEPINT3", + "description": "OTG_HS device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT4", + "displayName": "OTG_HS_DOEPINT4", + "description": "OTG_HS device endpoint-4 interrupt register", + "addressOffset": "0x388", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT5", + "displayName": "OTG_HS_DOEPINT5", + "description": "OTG_HS device endpoint-5 interrupt register", + "addressOffset": "0x3A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT6", + "displayName": "OTG_HS_DOEPINT6", + "description": "OTG_HS device endpoint-6 interrupt register", + "addressOffset": "0x3C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT7", + "displayName": "OTG_HS_DOEPINT7", + "description": "OTG_HS device endpoint-7 interrupt register", + "addressOffset": "0x3E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ0", + "displayName": "OTG_HS_DOEPTSIZ0", + "description": "OTG_HS device endpoint-1 transfer size register", + "addressOffset": "0x310", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ1", + "displayName": "OTG_HS_DOEPTSIZ1", + "description": "OTG_HS device endpoint-2 transfer size register", + "addressOffset": "0x330", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ2", + "displayName": "OTG_HS_DOEPTSIZ2", + "description": "OTG_HS device endpoint-3 transfer size register", + "addressOffset": "0x350", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ3", + "displayName": "OTG_HS_DOEPTSIZ3", + "description": "OTG_HS device endpoint-4 transfer size register", + "addressOffset": "0x370", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ4", + "displayName": "OTG_HS_DOEPTSIZ4", + "description": "OTG_HS device endpoint-5 transfer size register", + "addressOffset": "0x390", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_HS_GLOBAL", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0xFFFC0400", + "usage": "registers" + }, + { + "offset": "0xFFFC0400", + "size": "0x40000", + "usage": "reserved" + } + ], + "interrupts": [ + { + "name": "OTG_HS_EP1_OUT", + "description": "USB On The Go HS End Point 1 Out global interrupt", + "value": "74" + }, + { + "name": "OTG_HS_EP1_IN", + "description": "USB On The Go HS End Point 1 In global interrupt", + "value": "75" + }, + { + "name": "OTG_HS_WKUP", + "description": "USB On The Go HS Wakeup through EXTI interrupt", + "value": "76" + }, + { + "name": "OTG_HS", + "description": "USB On The Go HS global interrupt", + "value": "77" + } + ], + "registers": [ + { + "name": "OTG_HS_GOTGCTL", + "displayName": "OTG_HS_GOTGCTL", + "description": "OTG_HS control and status register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GOTGINT", + "displayName": "OTG_HS_GOTGINT", + "description": "OTG_HS interrupt register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GAHBCFG", + "displayName": "OTG_HS_GAHBCFG", + "description": "OTG_HS AHB configuration register", + "addressOffset": "0x8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HBSTLEN", + "description": "Burst length/type", + "bitOffset": "1", + "bitWidth": "4" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GUSBCFG", + "displayName": "OTG_HS_GUSBCFG", + "description": "OTG_HS USB configuration register", + "addressOffset": "0xC", + "size": "32", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PHYLPCS", + "description": "PHY Low-power clock select", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIFSLS", + "description": "ULPI FS/LS select", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIAR", + "description": "ULPI Auto-resume", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPICSM", + "description": "ULPI Clock SuspendM", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSD", + "description": "ULPI External VBUS Drive", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSI", + "description": "ULPI external VBUS indicator", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSDPS", + "description": "TermSel DLine pulsing selection", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PCCI", + "description": "Indicator complement", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCI", + "description": "Indicator pass through", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIIPD", + "description": "ULPI interface protect disable", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Forced host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Forced peripheral mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRSTCTL", + "displayName": "OTG_HS_GRSTCTL", + "description": "OTG_HS reset register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "DMAREQ", + "description": "DMA request signal", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GINTSTS", + "displayName": "OTG_HS_GINTSTS", + "description": "OTG_HS core interrupt register", + "addressOffset": "0x14", + "size": "32", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO nonempty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Nonperiodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN nonperiodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DATAFSUSP", + "description": "Data fetch suspended", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GINTMSK", + "displayName": "OTG_HS_GINTMSK", + "description": "OTG_HS interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO nonempty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Nonperiodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global nonperiodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FSUSPM", + "description": "Data fetch suspended mask", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Host", + "displayName": "OTG_HS_GRXSTSR_Host", + "description": "OTG_HS Receive status debug read register (host mode)", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Host", + "displayName": "OTG_HS_GRXSTSP_Host", + "description": "OTG_HS status read and pop register (host mode)", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXFSIZ", + "displayName": "OTG_HS_GRXFSIZ", + "description": "OTG_HS Receive FIFO size register", + "addressOffset": "0x24", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXFSIZ_Host", + "displayName": "OTG_HS_GNPTXFSIZ_Host", + "description": "OTG_HS nonperiodic transmit FIFO size register (host mode)", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Nonperiodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Nonperiodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_TX0FSIZ_Peripheral", + "displayName": "OTG_HS_TX0FSIZ_Peripheral", + "description": "Endpoint 0 transmit FIFO size (peripheral mode)", + "headerStructName": "OTG_HS_GNPTXFSIZ_Host", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXSTS", + "displayName": "OTG_HS_GNPTXSTS", + "description": "OTG_HS nonperiodic transmit FIFO/queue status register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Nonperiodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Nonperiodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the nonperiodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "OTG_HS_GCCFG", + "displayName": "OTG_HS_GCCFG", + "description": "OTG_HS general core configuration register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2CPADEN", + "description": "Enable I2C bus connection for the external I2C PHY interface", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "NOVBUSSENS", + "description": "VBUS sensing disable option", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_CID", + "displayName": "OTG_HS_CID", + "description": "OTG_HS core ID register", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x00001200", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HPTXFSIZ", + "displayName": "OTG_HS_HPTXFSIZ", + "description": "OTG_HS Host periodic transmit FIFO size register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFD", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF1", + "displayName": "OTG_HS_DIEPTXF1", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF2", + "displayName": "OTG_HS_DIEPTXF2", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF3", + "displayName": "OTG_HS_DIEPTXF3", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x11C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF4", + "displayName": "OTG_HS_DIEPTXF4", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF5", + "displayName": "OTG_HS_DIEPTXF5", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF6", + "displayName": "OTG_HS_DIEPTXF6", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF7", + "displayName": "OTG_HS_DIEPTXF7", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Peripheral", + "displayName": "OTG_HS_GRXSTSR_Peripheral", + "description": "OTG_HS Receive status debug read register (peripheral mode mode)", + "headerStructName": "OTG_HS_GRXSTSR_Host", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Peripheral", + "displayName": "OTG_HS_GRXSTSP_Peripheral", + "description": "OTG_HS status read and pop register (peripheral mode)", + "headerStructName": "OTG_HS_GRXSTSP_Host", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "OTG_HS_HOST", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_HCFG", + "displayName": "OTG_HS_HCFG", + "description": "OTG_HS host configuration register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HFIR", + "displayName": "OTG_HS_HFIR", + "description": "OTG_HS Host frame interval register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HFNUM", + "displayName": "OTG_HS_HFNUM", + "description": "OTG_HS host frame number/frame time remaining register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPTXSTS", + "displayName": "OTG_HS_HPTXSTS", + "description": "OTG_HS_Host periodic transmit FIFO/queue status register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HAINT", + "displayName": "OTG_HS_HAINT", + "description": "OTG_HS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HAINTMSK", + "displayName": "OTG_HS_HAINTMSK", + "description": "OTG_HS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPRT", + "displayName": "OTG_HS_HPRT", + "description": "OTG_HS host port control and status register", + "addressOffset": "0x40", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HCCHAR0", + "displayName": "OTG_HS_HCCHAR0", + "description": "OTG_HS host channel-0 characteristics register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR1", + "displayName": "OTG_HS_HCCHAR1", + "description": "OTG_HS host channel-1 characteristics register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR2", + "displayName": "OTG_HS_HCCHAR2", + "description": "OTG_HS host channel-2 characteristics register", + "addressOffset": "0x140", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR3", + "displayName": "OTG_HS_HCCHAR3", + "description": "OTG_HS host channel-3 characteristics register", + "addressOffset": "0x160", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR4", + "displayName": "OTG_HS_HCCHAR4", + "description": "OTG_HS host channel-4 characteristics register", + "addressOffset": "0x180", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR5", + "displayName": "OTG_HS_HCCHAR5", + "description": "OTG_HS host channel-5 characteristics register", + "addressOffset": "0x1A0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR6", + "displayName": "OTG_HS_HCCHAR6", + "description": "OTG_HS host channel-6 characteristics register", + "addressOffset": "0x1C0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR7", + "displayName": "OTG_HS_HCCHAR7", + "description": "OTG_HS host channel-7 characteristics register", + "addressOffset": "0x1E0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR8", + "displayName": "OTG_HS_HCCHAR8", + "description": "OTG_HS host channel-8 characteristics register", + "addressOffset": "0x200", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR9", + "displayName": "OTG_HS_HCCHAR9", + "description": "OTG_HS host channel-9 characteristics register", + "addressOffset": "0x220", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR10", + "displayName": "OTG_HS_HCCHAR10", + "description": "OTG_HS host channel-10 characteristics register", + "addressOffset": "0x240", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR11", + "displayName": "OTG_HS_HCCHAR11", + "description": "OTG_HS host channel-11 characteristics register", + "addressOffset": "0x260", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT0", + "displayName": "OTG_HS_HCSPLT0", + "description": "OTG_HS host channel-0 split control register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT1", + "displayName": "OTG_HS_HCSPLT1", + "description": "OTG_HS host channel-1 split control register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT2", + "displayName": "OTG_HS_HCSPLT2", + "description": "OTG_HS host channel-2 split control register", + "addressOffset": "0x144", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT3", + "displayName": "OTG_HS_HCSPLT3", + "description": "OTG_HS host channel-3 split control register", + "addressOffset": "0x164", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT4", + "displayName": "OTG_HS_HCSPLT4", + "description": "OTG_HS host channel-4 split control register", + "addressOffset": "0x184", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT5", + "displayName": "OTG_HS_HCSPLT5", + "description": "OTG_HS host channel-5 split control register", + "addressOffset": "0x1A4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT6", + "displayName": "OTG_HS_HCSPLT6", + "description": "OTG_HS host channel-6 split control register", + "addressOffset": "0x1C4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT7", + "displayName": "OTG_HS_HCSPLT7", + "description": "OTG_HS host channel-7 split control register", + "addressOffset": "0x1E4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT8", + "displayName": "OTG_HS_HCSPLT8", + "description": "OTG_HS host channel-8 split control register", + "addressOffset": "0x204", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT9", + "displayName": "OTG_HS_HCSPLT9", + "description": "OTG_HS host channel-9 split control register", + "addressOffset": "0x224", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT10", + "displayName": "OTG_HS_HCSPLT10", + "description": "OTG_HS host channel-10 split control register", + "addressOffset": "0x244", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT11", + "displayName": "OTG_HS_HCSPLT11", + "description": "OTG_HS host channel-11 split control register", + "addressOffset": "0x264", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT0", + "displayName": "OTG_HS_HCINT0", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT1", + "displayName": "OTG_HS_HCINT1", + "description": "OTG_HS host channel-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT2", + "displayName": "OTG_HS_HCINT2", + "description": "OTG_HS host channel-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT3", + "displayName": "OTG_HS_HCINT3", + "description": "OTG_HS host channel-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT4", + "displayName": "OTG_HS_HCINT4", + "description": "OTG_HS host channel-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT5", + "displayName": "OTG_HS_HCINT5", + "description": "OTG_HS host channel-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT6", + "displayName": "OTG_HS_HCINT6", + "description": "OTG_HS host channel-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT7", + "displayName": "OTG_HS_HCINT7", + "description": "OTG_HS host channel-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT8", + "displayName": "OTG_HS_HCINT8", + "description": "OTG_HS host channel-8 interrupt register", + "addressOffset": "0x208", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT9", + "displayName": "OTG_HS_HCINT9", + "description": "OTG_HS host channel-9 interrupt register", + "addressOffset": "0x228", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT10", + "displayName": "OTG_HS_HCINT10", + "description": "OTG_HS host channel-10 interrupt register", + "addressOffset": "0x248", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT11", + "displayName": "OTG_HS_HCINT11", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x268", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK0", + "displayName": "OTG_HS_HCINTMSK0", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x10C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK1", + "displayName": "OTG_HS_HCINTMSK1", + "description": "OTG_HS host channel-1 interrupt mask register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK2", + "displayName": "OTG_HS_HCINTMSK2", + "description": "OTG_HS host channel-2 interrupt mask register", + "addressOffset": "0x14C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK3", + "displayName": "OTG_HS_HCINTMSK3", + "description": "OTG_HS host channel-3 interrupt mask register", + "addressOffset": "0x16C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK4", + "displayName": "OTG_HS_HCINTMSK4", + "description": "OTG_HS host channel-4 interrupt mask register", + "addressOffset": "0x18C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK5", + "displayName": "OTG_HS_HCINTMSK5", + "description": "OTG_HS host channel-5 interrupt mask register", + "addressOffset": "0x1AC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK6", + "displayName": "OTG_HS_HCINTMSK6", + "description": "OTG_HS host channel-6 interrupt mask register", + "addressOffset": "0x1CC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK7", + "displayName": "OTG_HS_HCINTMSK7", + "description": "OTG_HS host channel-7 interrupt mask register", + "addressOffset": "0x1EC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK8", + "displayName": "OTG_HS_HCINTMSK8", + "description": "OTG_HS host channel-8 interrupt mask register", + "addressOffset": "0x20C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK9", + "displayName": "OTG_HS_HCINTMSK9", + "description": "OTG_HS host channel-9 interrupt mask register", + "addressOffset": "0x22C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK10", + "displayName": "OTG_HS_HCINTMSK10", + "description": "OTG_HS host channel-10 interrupt mask register", + "addressOffset": "0x24C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK11", + "displayName": "OTG_HS_HCINTMSK11", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x26C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ0", + "displayName": "OTG_HS_HCTSIZ0", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ1", + "displayName": "OTG_HS_HCTSIZ1", + "description": "OTG_HS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ2", + "displayName": "OTG_HS_HCTSIZ2", + "description": "OTG_HS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ3", + "displayName": "OTG_HS_HCTSIZ3", + "description": "OTG_HS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ4", + "displayName": "OTG_HS_HCTSIZ4", + "description": "OTG_HS host channel-4 transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ5", + "displayName": "OTG_HS_HCTSIZ5", + "description": "OTG_HS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ6", + "displayName": "OTG_HS_HCTSIZ6", + "description": "OTG_HS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ7", + "displayName": "OTG_HS_HCTSIZ7", + "description": "OTG_HS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ8", + "displayName": "OTG_HS_HCTSIZ8", + "description": "OTG_HS host channel-8 transfer size register", + "addressOffset": "0x210", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ9", + "displayName": "OTG_HS_HCTSIZ9", + "description": "OTG_HS host channel-9 transfer size register", + "addressOffset": "0x230", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ10", + "displayName": "OTG_HS_HCTSIZ10", + "description": "OTG_HS host channel-10 transfer size register", + "addressOffset": "0x250", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ11", + "displayName": "OTG_HS_HCTSIZ11", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x270", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCDMA0", + "displayName": "OTG_HS_HCDMA0", + "description": "OTG_HS host channel-0 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA1", + "displayName": "OTG_HS_HCDMA1", + "description": "OTG_HS host channel-1 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA2", + "displayName": "OTG_HS_HCDMA2", + "description": "OTG_HS host channel-2 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA3", + "displayName": "OTG_HS_HCDMA3", + "description": "OTG_HS host channel-3 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA4", + "displayName": "OTG_HS_HCDMA4", + "description": "OTG_HS host channel-4 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA5", + "displayName": "OTG_HS_HCDMA5", + "description": "OTG_HS host channel-5 DMA address register", + "addressOffset": "0x1B4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA6", + "displayName": "OTG_HS_HCDMA6", + "description": "OTG_HS host channel-6 DMA address register", + "addressOffset": "0x1D4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA7", + "displayName": "OTG_HS_HCDMA7", + "description": "OTG_HS host channel-7 DMA address register", + "addressOffset": "0x1F4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA8", + "displayName": "OTG_HS_HCDMA8", + "description": "OTG_HS host channel-8 DMA address register", + "addressOffset": "0x214", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA9", + "displayName": "OTG_HS_HCDMA9", + "description": "OTG_HS host channel-9 DMA address register", + "addressOffset": "0x234", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA10", + "displayName": "OTG_HS_HCDMA10", + "description": "OTG_HS host channel-10 DMA address register", + "addressOffset": "0x254", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA11", + "displayName": "OTG_HS_HCDMA11", + "description": "OTG_HS host channel-11 DMA address register", + "addressOffset": "0x274", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "OTG_HS_PWRCLK", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x3F200", + "usage": "registers" + }, + { + "offset": "0x3F200", + "size": "0xFFFC1200", + "usage": "reserved" + } + ], + "registers": [ + { + "name": "OTG_HS_PCGCR", + "displayName": "OTG_HS_PCGCR", + "description": "Power and clock gating control register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FPDS", + "description": "Flash power down in Stop mode", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BRR", + "description": "Backup regulator ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BRE", + "description": "Backup regulator enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VOSRDY", + "description": "Regulator voltage scaling output selection ready bit", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40023800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal high-speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal high-speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal high-speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal high-speed clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "HSE clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "HSE clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "HSE clock bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock security system enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "Main PLL (PLL) enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "Main PLL (PLL) clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SON", + "description": "PLLI2S enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLI2SRDY", + "description": "PLLI2S clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PLLCFGR", + "displayName": "PLLCFGR", + "description": "PLL configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003010", + "fields": [ + { + "name": "PLLM", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "PLLN", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLP", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PLLSRC", + "description": "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PLLQ", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System clock switch status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "10", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB high-speed prescaler (APB2)", + "bitOffset": "13", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "RTCPRE", + "description": "HSE division factor for RTC clock", + "bitOffset": "16", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "MCO1", + "description": "Microcontroller clock output 1", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "I2SSRC", + "description": "I2S clock selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO1PRE", + "description": "MCO1 prescaler", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO2PRE", + "description": "MCO2 prescaler", + "bitOffset": "27", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO2", + "description": "Microcontroller clock output 2", + "bitOffset": "30", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI ready interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE ready interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI ready interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE ready interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "Main PLL (PLL) ready interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SRDYF", + "description": "PLLI2S ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock security system interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI ready interrupt enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE ready interrupt enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI ready interrupt enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE ready interrupt enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "Main PLL (PLL) ready interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLI2SRDYIE", + "description": "PLLI2S ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI ready interrupt clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE ready interrupt clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI ready interrupt clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE ready interrupt clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "Main PLL(PLL) ready interrupt clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYC", + "description": "PLLI2S ready interrupt clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "AHB1RSTR", + "displayName": "AHB1RSTR", + "description": "AHB1 peripheral reset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GPIOARST", + "description": "IO port A reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBRST", + "description": "IO port B reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCRST", + "description": "IO port C reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODRST", + "description": "IO port D reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOERST", + "description": "IO port E reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOFRST", + "description": "IO port F reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOGRST", + "description": "IO port G reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOHRST", + "description": "IO port H reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOIRST", + "description": "IO port I reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CRCRST", + "description": "CRC reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMA1RST", + "description": "DMA2 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2RST", + "description": "DMA2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "ETHMACRST", + "description": "Ethernet MAC reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "OTGHSRST", + "description": "USB OTG HS module reset", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2RSTR", + "displayName": "AHB2RSTR", + "description": "AHB2 peripheral reset register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCMIRST", + "description": "Camera interface reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RNGRST", + "description": "Random number generator module reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSRST", + "description": "USB OTG FS module reset", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3RSTR", + "displayName": "AHB3RSTR", + "description": "AHB3 peripheral reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSMCRST", + "description": "Flexible static memory controller module reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "TIM2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "TIM3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "TIM4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "TIM5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "TIM6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12RST", + "description": "TIM12 reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13RST", + "description": "TIM13 reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "TIM14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI 2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI 3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "UART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4RST", + "description": "USART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5RST", + "description": "USART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C 1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C 2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3RST", + "description": "I2C3 reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1RST", + "description": "CAN1 reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2RST", + "description": "CAN2 reset", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC reset", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1RST", + "description": "TIM1 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8RST", + "description": "TIM8 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6RST", + "description": "USART6 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset (common to all ADCs)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIORST", + "description": "SDIO reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SYSCFGRST", + "description": "System configuration controller reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11RST", + "description": "TIM11 reset", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1ENR", + "displayName": "AHB1ENR", + "description": "AHB1 peripheral clock register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00100000", + "fields": [ + { + "name": "GPIOAEN", + "description": "IO port A clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBEN", + "description": "IO port B clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCEN", + "description": "IO port C clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODEN", + "description": "IO port D clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOEEN", + "description": "IO port E clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOFEN", + "description": "IO port F clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOGEN", + "description": "IO port G clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOHEN", + "description": "IO port H clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOIEN", + "description": "IO port I clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKPSRAMEN", + "description": "Backup SRAM interface clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "ETHMACEN", + "description": "Ethernet MAC clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "ETHMACTXEN", + "description": "Ethernet Transmission clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACRXEN", + "description": "Ethernet Reception clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPEN", + "description": "Ethernet PTP clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "OTGHSEN", + "description": "USB OTG HS clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "OTGHSULPIEN", + "description": "USB OTG HSULPI clock enable", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2ENR", + "displayName": "AHB2ENR", + "description": "AHB2 peripheral clock enable register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCMIEN", + "description": "Camera interface enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RNGEN", + "description": "Random number generator clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3ENR", + "displayName": "AHB3ENR", + "description": "AHB3 peripheral clock enable register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSMCEN", + "description": "Flexible static memory controller module clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "TIM2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "TIM3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "TIM4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "TIM5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "TIM6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12EN", + "description": "TIM12 clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13EN", + "description": "TIM13 clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "TIM14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3EN", + "description": "I2C3 clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1EN", + "description": "CAN 1 clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2EN", + "description": "CAN 2 clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1EN", + "description": "TIM1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8EN", + "description": "TIM8 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6EN", + "description": "USART6 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC1 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC2 clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC3EN", + "description": "ADC3 clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SYSCFGEN", + "description": "System configuration controller clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11EN", + "description": "TIM11 clock enable", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1LPENR", + "displayName": "AHB1LPENR", + "description": "AHB1 peripheral clock enable in low power mode register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7E6791FF", + "fields": [ + { + "name": "GPIOALPEN", + "description": "IO port A clock enable during sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBLPEN", + "description": "IO port B clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCLPEN", + "description": "IO port C clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODLPEN", + "description": "IO port D clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOELPEN", + "description": "IO port E clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOFLPEN", + "description": "IO port F clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOGLPEN", + "description": "IO port G clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOHLPEN", + "description": "IO port H clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOILPEN", + "description": "IO port I clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CRCLPEN", + "description": "CRC clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FLITFLPEN", + "description": "Flash interface clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SRAM1LPEN", + "description": "SRAM 1interface clock enable during Sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SRAM2LPEN", + "description": "SRAM 2 interface clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BKPSRAMLPEN", + "description": "Backup SRAM interface clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DMA1LPEN", + "description": "DMA1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2LPEN", + "description": "DMA2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "ETHMACLPEN", + "description": "Ethernet MAC clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "ETHMACTXLPEN", + "description": "Ethernet transmission clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACRXLPEN", + "description": "Ethernet reception clock enable during Sleep mode", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPLPEN", + "description": "Ethernet PTP clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "OTGHSLPEN", + "description": "USB OTG HS clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "OTGHSULPILPEN", + "description": "USB OTG HS ULPI clock enable during Sleep mode", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2LPENR", + "displayName": "AHB2LPENR", + "description": "AHB2 peripheral clock enable in low power mode register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000F1", + "fields": [ + { + "name": "DCMILPEN", + "description": "Camera interface enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RNGLPEN", + "description": "Random number generator clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSLPEN", + "description": "USB OTG FS clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3LPENR", + "displayName": "AHB3LPENR", + "description": "AHB3 peripheral clock enable in low power mode register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000001", + "fields": [ + { + "name": "FSMCLPEN", + "description": "Flexible static memory controller module clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1LPENR", + "displayName": "APB1LPENR", + "description": "APB1 peripheral clock enable in low power mode register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x36FEC9FF", + "fields": [ + { + "name": "TIM2LPEN", + "description": "TIM2 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3LPEN", + "description": "TIM3 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4LPEN", + "description": "TIM4 clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5LPEN", + "description": "TIM5 clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6LPEN", + "description": "TIM6 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7LPEN", + "description": "TIM7 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12LPEN", + "description": "TIM12 clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13LPEN", + "description": "TIM13 clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14LPEN", + "description": "TIM14 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGLPEN", + "description": "Window watchdog clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2LPEN", + "description": "SPI2 clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3LPEN", + "description": "SPI3 clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2LPEN", + "description": "USART2 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3LPEN", + "description": "USART3 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4LPEN", + "description": "UART4 clock enable during Sleep mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5LPEN", + "description": "UART5 clock enable during Sleep mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1LPEN", + "description": "I2C1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2LPEN", + "description": "I2C2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3LPEN", + "description": "I2C3 clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1LPEN", + "description": "CAN 1 clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2LPEN", + "description": "CAN 2 clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWRLPEN", + "description": "Power interface clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACLPEN", + "description": "DAC interface clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2LPENR", + "displayName": "APB2LPENR", + "description": "APB2 peripheral clock enabled in low power mode register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00075F33", + "fields": [ + { + "name": "TIM1LPEN", + "description": "TIM1 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8LPEN", + "description": "TIM8 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1LPEN", + "description": "USART1 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6LPEN", + "description": "USART6 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1LPEN", + "description": "ADC1 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC2LPEN", + "description": "ADC2 clock enable during Sleep mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC3LPEN", + "description": "ADC 3 clock enable during Sleep mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOLPEN", + "description": "SDIO clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1LPEN", + "description": "SPI 1 clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SYSCFGLPEN", + "description": "System configuration controller clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9LPEN", + "description": "TIM9 clock enable during sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10LPEN", + "description": "TIM10 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11LPEN", + "description": "TIM11 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register", + "addressOffset": "0x70", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External low-speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Clock control & status register", + "addressOffset": "0x74", + "size": "0x20", + "resetValue": "0x0E000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BORRSTF", + "description": "BOR reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PADRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SSCGR", + "displayName": "SSCGR", + "description": "Spread spectrum clock generation register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODPER", + "description": "Modulation period", + "bitOffset": "0", + "bitWidth": "13" + }, + { + "name": "INCSTEP", + "description": "Incrementation step", + "bitOffset": "13", + "bitWidth": "15" + }, + { + "name": "SPREADSEL", + "description": "Spread Select", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SSCGEN", + "description": "Spread spectrum modulation enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PLLI2SCFGR", + "displayName": "PLLI2SCFGR", + "description": "PLLI2S configuration register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20003000", + "fields": [ + { + "name": "PLLI2SNx", + "description": "PLLI2S multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLI2SRx", + "description": "PLLI2S division factor for I2S clocks", + "bitOffset": "28", + "bitWidth": "3" + } + ] + } + ] + }, + { + "name": "RNG", + "description": "Random number generator", + "groupName": "RNG", + "baseAddress": "0x50060800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FPU", + "description": "FPU interrupt", + "value": "81" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RNGEN", + "description": "Random number generator enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IE", + "description": "Interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DRDY", + "description": "Data ready", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CECS", + "description": "Clock error current status", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SECS", + "description": "Seed error current status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CEIS", + "description": "Clock error interrupt status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SEIS", + "description": "Seed error interrupt status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RNDATA", + "description": "Random data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC_WKUP", + "description": "RTC Wakeup interrupt through the EXTI line", + "value": "3" + }, + { + "name": "RTC_Alarm", + "description": "RTC Alarms (A and B) through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WCKSEL", + "description": "Wakeup clock selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "REFCKON", + "description": "Reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCE", + "description": "Coarse digital calibration enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ALRBE", + "description": "Alarm B enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WUTE", + "description": "Wakeup timer enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALRBIE", + "description": "Alarm B interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WUTIE", + "description": "Wakeup timer interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALRBWF", + "description": "Alarm B write flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "WUTWF", + "description": "Wakeup timer write flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRBF", + "description": "Alarm B flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUTF", + "description": "Wakeup timer flag", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "Tamper detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "TAMPER2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + } + ] + }, + { + "name": "WUTR", + "displayName": "WUTR", + "description": "Wakeup timer register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "WUT", + "description": "Wakeup auto-reload value bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALIBR", + "displayName": "CALIBR", + "description": "Calibration register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DC", + "description": "Digital calibration", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DCS", + "description": "Digital calibration sign", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMBR", + "displayName": "ALRMBR", + "description": "Alarm B register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm B seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm B minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm B hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm B date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "ADD1S", + "description": "Add one second", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Time stamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Time stamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Timestamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + }, + { + "name": "CALW16", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALP", + "description": "Increase frequency of RTC by 488.5 ppm", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "Tamper 2 detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMP2TRG", + "description": "Active level for tamper 2", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPFLT", + "description": "Tamper filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPPRCH", + "description": "Tamper precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPPUDIS", + "description": "TAMPER pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "ALRMBSSR", + "displayName": "ALRMBSSR", + "description": "Alarm B sub second register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP5R", + "displayName": "BKP5R", + "description": "Backup register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP6R", + "displayName": "BKP6R", + "description": "Backup register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP7R", + "displayName": "BKP7R", + "description": "Backup register", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP8R", + "displayName": "BKP8R", + "description": "Backup register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP9R", + "displayName": "BKP9R", + "description": "Backup register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP10R", + "displayName": "BKP10R", + "description": "Backup register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP11R", + "displayName": "BKP11R", + "description": "Backup register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP12R", + "displayName": "BKP12R", + "description": "Backup register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP13R", + "displayName": "BKP13R", + "description": "Backup register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP14R", + "displayName": "BKP14R", + "description": "Backup register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP15R", + "displayName": "BKP15R", + "description": "Backup register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP16R", + "displayName": "BKP16R", + "description": "Backup register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP17R", + "displayName": "BKP17R", + "description": "Backup register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP18R", + "displayName": "BKP18R", + "description": "Backup register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP19R", + "displayName": "BKP19R", + "description": "Backup register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Argument register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "Command register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDINDEX", + "description": "Command index", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "WAITRESP", + "description": "Wait for response bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "WAITINT", + "description": "CPSM waits for interrupt request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "CPSM Waits for ends of data transfer (CmdPend internal signal).", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "Command path state machine (CPSM) Enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SD I/O suspend command", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "Enable CMD completion", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "Not Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CE_ATACMD", + "description": "CE-ATA command", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "Command response register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "Response command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESP1", + "displayName": "RESP1", + "description": "Response 1..4 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Response 1..4 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Response 1..4 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Response 1..4 register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Data timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Data length register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "Data control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "Data transfer direction selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "Data transfer mode selection 1: Stream or SDIO multibyte data transfer.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA enable bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "Data block size", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "RWSTART", + "description": "Read wait start", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWSTOP", + "description": "Read wait stop", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "Read wait mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SD I/O enable functions", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Data counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAIL", + "description": "Command response received (CRC check failed)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "Data block sent/received (CRC check failed)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "Command response timeout", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "Data timeout", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "Transmit FIFO underrun error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "Received FIFO overrun error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "Command response received (CRC check passed)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "Command sent (no response required)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "Data end (data counter, SDIDCOUNT, is zero)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "Start bit not detected on all data signals in wide bus mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "Data block sent/received (CRC check passed)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "Command transfer in progress", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "Data transmit in progress", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "Data receive in progress", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "Transmit FIFO half empty: at least 8 words can be written into the FIFO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "Receive FIFO half full: there are at least 8 words in the FIFO", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "Transmit FIFO full", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "Receive FIFO full", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "Transmit FIFO empty", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "Receive FIFO empty", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "Data available in transmit FIFO", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "Data available in receive FIFO", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIO interrupt received", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAEND", + "description": "CE-ATA command completion signal received for CMD61", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILC", + "description": "CCRCFAIL flag clear bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAIL flag clear bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUT flag clear bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUT flag clear bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERR flag clear bit", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERR flag clear bit", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDREND flag clear bit", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENT flag clear bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAEND flag clear bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERR flag clear bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKEND flag clear bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOIT flag clear bit", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDC", + "description": "CEATAEND flag clear bit", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "Mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILIE", + "description": "Command CRC fail interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "Data CRC fail interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "Command timeout interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "Data timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "Tx FIFO underrun error interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "Rx FIFO overrun error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "Command response received interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "Command sent interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "Data end interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "Start bit error interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDIE", + "description": "Data block end interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "Command acting interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "Data transmit acting interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "Data receive acting interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "Tx FIFO half empty interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "Rx FIFO half full interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "Tx FIFO full interrupt enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "Rx FIFO full interrupt enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "Tx FIFO empty interrupt enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "Rx FIFO empty interrupt enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "Data available in Tx FIFO interrupt enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "Data available in Rx FIFO interrupt enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIO mode interrupt received interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDIE", + "description": "CE-ATA command completion signal received interrupt enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "FIFO counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOCOUNT", + "description": "Remaining number of words to be written to or read from the FIFO.", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Data FIFO register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "Receive and transmit FIFO data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MEMRM", + "displayName": "MEMRM", + "description": "Memory remap register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "MEM_MODE", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PMC", + "displayName": "PMC", + "description": "Peripheral mode configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MII_RMII_SEL", + "description": "Ethernet PHY interface selection", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CMPCR", + "displayName": "CMPCR", + "description": "Compensation cell control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMP_PD", + "description": "Compensation cell power-down", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "READY", + "description": "READY", + "bitOffset": "8", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM10", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM11", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Input 1 remapping capability", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM12", + "derivedFrom": "TIM9", + "baseAddress": "0x40001800", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + } + ] + }, + { + "name": "TIM13", + "derivedFrom": "TIM10", + "baseAddress": "0x40001C00", + "interrupts": [ + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + } + ] + }, + { + "name": "TIM14", + "derivedFrom": "TIM10", + "baseAddress": "0x40002000", + "interrupts": [ + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ITR1_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM3", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM3", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "IT4_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "6", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM6", + "description": "Basic timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40010400", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + }, + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + }, + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + }, + { + "name": "TIM8_CC", + "description": "TIM8 Capture Compare interrupt", + "value": "46" + } + ] + }, + { + "name": "TIM9", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "UART4", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "UART5", + "derivedFrom": "UART4", + "baseAddress": "0x40005000", + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "USART1", + "derivedFrom": "USART6", + "baseAddress": "0x40011000", + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART2", + "derivedFrom": "USART6", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART3", + "derivedFrom": "USART6", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART6", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40011400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART6", + "description": "USART6 global interrupt", + "value": "71" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB0", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "WDGTB1", + "description": "Timer base", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + } + ], + "cpu": { + "name": "CM4", + "revision": "r0p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "true", + "nvicPrioBits": "4", + "deviceNumInterrupts": "82", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "qemuAlignment": "any" + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/STM32F411xx-qemu.json b/gnu-mcu-eclipse/devices/STM32F411xx-qemu.json new file mode 100644 index 0000000000..e55f11ff98 --- /dev/null +++ b/gnu-mcu-eclipse/devices/STM32F411xx-qemu.json @@ -0,0 +1,23301 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F411xx.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.10", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F411xx.svd", + "--output", + "STM32F411xx-xsvd.json" + ], + "date": "2016-12-25T11:51:46.377Z" + }, + { + "tool": "xcdl", + "version": "1.6.10", + "command": [ + "svd-patch", + "--file", + "STM32F411xx-xsvd.json", + "--patch", + "STM32F411xx-patch.json", + "--output", + "../STM32F411xx-qemu.json", + "--remove", + "NVIC", + "--group-bitfield", + "RCC/PLLCFGR/PLLQ", + "--group-bitfield", + "RCC/PLLCFGR/PLLP", + "--group-bitfield", + "RCC/PLLCFGR/PLLN", + "--group-bitfield", + "RCC/PLLCFGR/PLLM", + "--group-bitfield", + "RCC/CFGR/SWS", + "--group-bitfield", + "RCC/CFGR/SW", + "--group-bitfield", + "RCC/BDCR/RTCSEL" + ], + "date": "2016-12-25T11:56:45.871Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F411xx", + "version": "1.0", + "description": "STM32F411xx", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC1", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OVR", + "description": "Overrun", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Resolution", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADON", + "description": "A/D Converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode (for single ADC mode)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DDS", + "description": "DMA disable selection (for single ADC mode)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EOCS", + "description": "End of conversion selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "JEXTEN", + "description": "External trigger enable for injected channels", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "EXTEN", + "description": "External trigger enable for regular channels", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC_Common", + "description": "ADC common registers", + "groupName": "ADC", + "baseAddress": "0x40012300", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x100", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FPU", + "description": "FPU interrupt", + "value": "81" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "ADC Common status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD1", + "description": "Analog watchdog flag of ADC 1", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC1", + "description": "End of conversion of ADC 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC1", + "description": "Injected channel end of conversion of ADC 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT1", + "description": "Injected channel Start flag of ADC 1", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT1", + "description": "Regular channel Start flag of ADC 1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OVR1", + "description": "Overrun flag of ADC 1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWD2", + "description": "Analog watchdog flag of ADC 2", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EOC2", + "description": "End of conversion of ADC 2", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JEOC2", + "description": "Injected channel end of conversion of ADC 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "JSTRT2", + "description": "Injected channel Start flag of ADC 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STRT2", + "description": "Regular channel Start flag of ADC 2", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OVR2", + "description": "Overrun flag of ADC 2", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AWD3", + "description": "Analog watchdog flag of ADC 3", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOC3", + "description": "End of conversion of ADC 3", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "JEOC3", + "description": "Injected channel end of conversion of ADC 3", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "JSTRT3", + "description": "Injected channel Start flag of ADC 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STRT3", + "description": "Regular channel Start flag of ADC 3", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "OVR3", + "description": "Overrun flag of ADC3", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "ADC common control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DELAY", + "description": "Delay between 2 sampling phases", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DDS", + "description": "DMA disable selection for multi-ADC mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode for multi ADC mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "VBATE", + "description": "VBAT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "Cryptographic processor", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Control regidter", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DBGMCU_IDCODE", + "displayName": "DBGMCU_IDCODE", + "description": "IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x10006411", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DBGMCU_CR", + "displayName": "DBGMCU_CR", + "description": "Control Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + } + ] + }, + { + "name": "DBGMCU_APB1_FZ", + "displayName": "DBGMCU_APB1_FZ", + "description": "Debug MCU APB1 Freeze registe", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3 _STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBG_RTC_Stop", + "description": "RTC stopped when Core is halted", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDEG_STOP", + "description": "DBG_IWDEG_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_I2C1_SMBUS_TIMEOUT", + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBG_I2C3SMBUS_TIMEOUT", + "description": "DBG_J2C3SMBUS_TIMEOUT", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB2_FZ", + "displayName": "DBGMCU_APB2_FZ", + "description": "Debug MCU APB2 Freeze registe", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM1_STOP", + "description": "TIM1 counter stopped when core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM9_STOP", + "description": "TIM9 counter stopped when core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM10_STOP", + "description": "TIM10 counter stopped when core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM11_STOP", + "description": "TIM11 counter stopped when core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA1", + "derivedFrom": "DMA2", + "baseAddress": "0x40026000", + "interrupts": [ + { + "name": "RTC_WKUP", + "description": "RTC Wakeup interrupt through the EXTI line", + "value": "3" + }, + { + "name": "RTC_Alarm", + "description": "RTC Alarms (A and B) through EXTI line interrupt", + "value": "41" + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40026400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "LISR", + "displayName": "LISR", + "description": "Low interrupt status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FEIF0", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIF0", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF0", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "HTIF0", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF0", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FEIF1", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMEIF1", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FEIF2", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMEIF2", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FEIF3", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMEIF3", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "HISR", + "displayName": "HISR", + "description": "High interrupt status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FEIF4", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIF4", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FEIF5", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMEIF5", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FEIF6", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMEIF6", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FEIF7", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMEIF7", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "LIFCR", + "displayName": "LIFCR", + "description": "Low interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFEIF0", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CDMEIF0", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF0", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHTIF0", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF0", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CFEIF1", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CDMEIF1", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CFEIF2", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CDMEIF2", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CFEIF3", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CDMEIF3", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "HIFCR", + "displayName": "HIFCR", + "description": "High interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFEIF4", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CDMEIF4", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CFEIF5", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CDMEIF5", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CFEIF6", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CDMEIF6", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CFEIF7", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CDMEIF7", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "S0CR", + "displayName": "S0CR", + "description": "Stream x configuration register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S0NDTR", + "displayName": "S0NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S0PAR", + "displayName": "S0PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M0AR", + "displayName": "S0M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M1AR", + "displayName": "S0M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0FCR", + "displayName": "S0FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S1CR", + "displayName": "S1CR", + "description": "Stream x configuration register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S1NDTR", + "displayName": "S1NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S1PAR", + "displayName": "S1PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M0AR", + "displayName": "S1M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M1AR", + "displayName": "S1M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1FCR", + "displayName": "S1FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x3C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S2CR", + "displayName": "S2CR", + "description": "Stream x configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S2NDTR", + "displayName": "S2NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S2PAR", + "displayName": "S2PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M0AR", + "displayName": "S2M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M1AR", + "displayName": "S2M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2FCR", + "displayName": "S2FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S3CR", + "displayName": "S3CR", + "description": "Stream x configuration register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S3NDTR", + "displayName": "S3NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S3PAR", + "displayName": "S3PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M0AR", + "displayName": "S3M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M1AR", + "displayName": "S3M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3FCR", + "displayName": "S3FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x6C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S4CR", + "displayName": "S4CR", + "description": "Stream x configuration register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S4NDTR", + "displayName": "S4NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S4PAR", + "displayName": "S4PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M0AR", + "displayName": "S4M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M1AR", + "displayName": "S4M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4FCR", + "displayName": "S4FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S5CR", + "displayName": "S5CR", + "description": "Stream x configuration register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S5NDTR", + "displayName": "S5NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S5PAR", + "displayName": "S5PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M0AR", + "displayName": "S5M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M1AR", + "displayName": "S5M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5FCR", + "displayName": "S5FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x9C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S6CR", + "displayName": "S6CR", + "description": "Stream x configuration register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S6NDTR", + "displayName": "S6NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S6PAR", + "displayName": "S6PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M0AR", + "displayName": "S6M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M1AR", + "displayName": "S6M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6FCR", + "displayName": "S6FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xB4", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S7CR", + "displayName": "S7CR", + "description": "Stream x configuration register", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S7NDTR", + "displayName": "S7NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xBC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S7PAR", + "displayName": "S7PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xC0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M0AR", + "displayName": "S7M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M1AR", + "displayName": "S7M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xC8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7FCR", + "displayName": "S7FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xCC", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40013C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMP_STAMP", + "description": "Tamper and TimeStamp interrupts through the EXTI line", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Rising trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Rising trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Rising trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Falling trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Falling trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Falling trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SWIER20", + "description": "Software Interrupt on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SWIER21", + "description": "Software Interrupt on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWIER22", + "description": "Software Interrupt on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PR20", + "description": "Pending bit 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PR21", + "description": "Pending bit 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PR22", + "description": "Pending bit 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40023C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "FLASH global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bitOffset": "11", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OPERR", + "description": "Operation error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGPERR", + "description": "Programming parallelism error", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x80000000", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SER", + "description": "Sector Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SNB", + "description": "Sector number", + "bitOffset": "3", + "bitWidth": "4" + }, + { + "name": "PSIZE", + "description": "Program size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OPTCR", + "displayName": "OPTCR", + "description": "Flash option control register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "OPTLOCK", + "description": "Option lock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OPTSTRT", + "description": "Option start", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "WDG_SW", + "description": "WDG_SW User option bytes", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP User option bytes", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY User option bytes", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Read protect", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xA8000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x64000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000280", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000C0", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000100", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOH", + "baseAddress": "0x40020800", + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOH", + "baseAddress": "0X40020C00", + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOH", + "baseAddress": "0x40021000", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOH", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40021C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "I2C1", + "derivedFrom": "I2C3", + "baseAddress": "0x40005400", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "derivedFrom": "I2C3", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C3", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2S2ext", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40003400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "I2S3ext", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40004000" + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_FS_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "OTG_FS_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FPDS", + "description": "Flash power down in Stop mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADCDC1", + "description": "ADCDC1", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "VOS", + "description": "Regulator voltage scaling output selection", + "bitOffset": "14", + "bitWidth": "2" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BRR", + "description": "Backup regulator ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BRE", + "description": "Backup regulator enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VOSRDY", + "description": "Regulator voltage scaling output selection ready bit", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40023800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal high-speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal high-speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal high-speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal high-speed clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "HSE clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "HSE clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "HSE clock bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock security system enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "Main PLL (PLL) enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "Main PLL (PLL) clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SON", + "description": "PLLI2S enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLI2SRDY", + "description": "PLLI2S clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PLLCFGR", + "displayName": "PLLCFGR", + "description": "PLL configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003010", + "fields": [ + { + "name": "PLLM", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "PLLN", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLP", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PLLSRC", + "description": "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PLLQ", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System clock switch status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "10", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB high-speed prescaler (APB2)", + "bitOffset": "13", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "RTCPRE", + "description": "HSE division factor for RTC clock", + "bitOffset": "16", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "MCO1", + "description": "Microcontroller clock output 1", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "I2SSRC", + "description": "I2S clock selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO1PRE", + "description": "MCO1 prescaler", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO2PRE", + "description": "MCO2 prescaler", + "bitOffset": "27", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO2", + "description": "Microcontroller clock output 2", + "bitOffset": "30", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI ready interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE ready interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI ready interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE ready interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "Main PLL (PLL) ready interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SRDYF", + "description": "PLLI2S ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock security system interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI ready interrupt enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE ready interrupt enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI ready interrupt enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE ready interrupt enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "Main PLL (PLL) ready interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLI2SRDYIE", + "description": "PLLI2S ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI ready interrupt clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE ready interrupt clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI ready interrupt clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE ready interrupt clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "Main PLL(PLL) ready interrupt clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYC", + "description": "PLLI2S ready interrupt clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "AHB1RSTR", + "displayName": "AHB1RSTR", + "description": "AHB1 peripheral reset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GPIOARST", + "description": "IO port A reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBRST", + "description": "IO port B reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCRST", + "description": "IO port C reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODRST", + "description": "IO port D reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOERST", + "description": "IO port E reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOHRST", + "description": "IO port H reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CRCRST", + "description": "CRC reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMA1RST", + "description": "DMA2 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2RST", + "description": "DMA2 reset", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2RSTR", + "displayName": "AHB2RSTR", + "description": "AHB2 peripheral reset register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSRST", + "description": "USB OTG FS module reset", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "TIM2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "TIM3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "TIM4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "TIM5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI 2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI 3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C 1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C 2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3RST", + "description": "I2C3 reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1RST", + "description": "TIM1 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6RST", + "description": "USART6 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset (common to all ADCs)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIORST", + "description": "SDIO reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SYSCFGRST", + "description": "System configuration controller reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11RST", + "description": "TIM11 reset", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1ENR", + "displayName": "AHB1ENR", + "description": "AHB1 peripheral clock register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00100000", + "fields": [ + { + "name": "GPIOAEN", + "description": "IO port A clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBEN", + "description": "IO port B clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCEN", + "description": "IO port C clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODEN", + "description": "IO port D clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOEEN", + "description": "IO port E clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOHEN", + "description": "IO port H clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2ENR", + "displayName": "AHB2ENR", + "description": "AHB2 peripheral clock enable register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "TIM2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "TIM3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "TIM4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "TIM5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3EN", + "description": "I2C3 clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1EN", + "description": "TIM1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6EN", + "description": "USART6 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC1 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4EN", + "description": "SPI4 clock enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGEN", + "description": "System configuration controller clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11EN", + "description": "TIM11 clock enable", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1LPENR", + "displayName": "AHB1LPENR", + "description": "AHB1 peripheral clock enable in low power mode register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7E6791FF", + "fields": [ + { + "name": "GPIOALPEN", + "description": "IO port A clock enable during sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBLPEN", + "description": "IO port B clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCLPEN", + "description": "IO port C clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODLPEN", + "description": "IO port D clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOELPEN", + "description": "IO port E clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOHLPEN", + "description": "IO port H clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CRCLPEN", + "description": "CRC clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FLITFLPEN", + "description": "Flash interface clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SRAM1LPEN", + "description": "SRAM 1interface clock enable during Sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMA1LPEN", + "description": "DMA1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2LPEN", + "description": "DMA2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2LPENR", + "displayName": "AHB2LPENR", + "description": "AHB2 peripheral clock enable in low power mode register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000F1", + "fields": [ + { + "name": "OTGFSLPEN", + "description": "USB OTG FS clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1LPENR", + "displayName": "APB1LPENR", + "description": "APB1 peripheral clock enable in low power mode register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x36FEC9FF", + "fields": [ + { + "name": "TIM2LPEN", + "description": "TIM2 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3LPEN", + "description": "TIM3 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4LPEN", + "description": "TIM4 clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5LPEN", + "description": "TIM5 clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WWDGLPEN", + "description": "Window watchdog clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2LPEN", + "description": "SPI2 clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3LPEN", + "description": "SPI3 clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2LPEN", + "description": "USART2 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2C1LPEN", + "description": "I2C1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2LPEN", + "description": "I2C2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3LPEN", + "description": "I2C3 clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PWRLPEN", + "description": "Power interface clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2LPENR", + "displayName": "APB2LPENR", + "description": "APB2 peripheral clock enabled in low power mode register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00075F33", + "fields": [ + { + "name": "TIM1LPEN", + "description": "TIM1 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "USART1LPEN", + "description": "USART1 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6LPEN", + "description": "USART6 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1LPEN", + "description": "ADC1 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIOLPEN", + "description": "SDIO clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1LPEN", + "description": "SPI 1 clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4LPEN", + "description": "SPI4 clock enable during Sleep mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGLPEN", + "description": "System configuration controller clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9LPEN", + "description": "TIM9 clock enable during sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10LPEN", + "description": "TIM10 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11LPEN", + "description": "TIM11 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register", + "addressOffset": "0x70", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External low-speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Clock control & status register", + "addressOffset": "0x74", + "size": "0x20", + "resetValue": "0x0E000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BORRSTF", + "description": "BOR reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PADRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SSCGR", + "displayName": "SSCGR", + "description": "Spread spectrum clock generation register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODPER", + "description": "Modulation period", + "bitOffset": "0", + "bitWidth": "13" + }, + { + "name": "INCSTEP", + "description": "Incrementation step", + "bitOffset": "13", + "bitWidth": "15" + }, + { + "name": "SPREADSEL", + "description": "Spread Select", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SSCGEN", + "description": "Spread spectrum modulation enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PLLI2SCFGR", + "displayName": "PLLI2SCFGR", + "description": "PLLI2S configuration register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20003000", + "fields": [ + { + "name": "PLLI2SNx", + "description": "PLLI2S multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLI2SRx", + "description": "PLLI2S division factor for I2S clocks", + "bitOffset": "28", + "bitWidth": "3" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WCKSEL", + "description": "Wakeup clock selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "REFCKON", + "description": "Reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BYPSHAD", + "description": "Bypass the shadow registers", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCE", + "description": "Coarse digital calibration enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ALRBE", + "description": "Alarm B enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WUTE", + "description": "Wakeup timer enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALRBIE", + "description": "Alarm B interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WUTIE", + "description": "Wakeup timer interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "COSEL", + "description": "Calibration Output selection", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALRBWF", + "description": "Alarm B write flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "WUTWF", + "description": "Wakeup timer write flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRBF", + "description": "Alarm B flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUTF", + "description": "Wakeup timer flag", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "Tamper detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "TAMPER2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + } + ] + }, + { + "name": "WUTR", + "displayName": "WUTR", + "description": "Wakeup timer register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "WUT", + "description": "Wakeup auto-reload value bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALIBR", + "displayName": "CALIBR", + "description": "Calibration register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DC", + "description": "Digital calibration", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DCS", + "description": "Digital calibration sign", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMBR", + "displayName": "ALRMBR", + "description": "Alarm B register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm B seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm B minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm B hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm B date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "ADD1S", + "description": "Add one second", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Time stamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Time stamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Timestamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + }, + { + "name": "CALW16", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALP", + "description": "Increase frequency of RTC by 488.5 ppm", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "Tamper 2 detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMP2TRG", + "description": "Active level for tamper 2", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPFLT", + "description": "Tamper filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPPRCH", + "description": "Tamper precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPPUDIS", + "description": "TAMPER pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "ALRMBSSR", + "displayName": "ALRMBSSR", + "description": "Alarm B sub second register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP5R", + "displayName": "BKP5R", + "description": "Backup register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP6R", + "displayName": "BKP6R", + "description": "Backup register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP7R", + "displayName": "BKP7R", + "description": "Backup register", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP8R", + "displayName": "BKP8R", + "description": "Backup register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP9R", + "displayName": "BKP9R", + "description": "Backup register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP10R", + "displayName": "BKP10R", + "description": "Backup register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP11R", + "displayName": "BKP11R", + "description": "Backup register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP12R", + "displayName": "BKP12R", + "description": "Backup register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP13R", + "displayName": "BKP13R", + "description": "Backup register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP14R", + "displayName": "BKP14R", + "description": "Backup register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP15R", + "displayName": "BKP15R", + "description": "Backup register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP16R", + "displayName": "BKP16R", + "description": "Backup register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP17R", + "displayName": "BKP17R", + "description": "Backup register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP18R", + "displayName": "BKP18R", + "description": "Backup register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP19R", + "displayName": "BKP19R", + "description": "Backup register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Argument register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "Command register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDINDEX", + "description": "Command index", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "WAITRESP", + "description": "Wait for response bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "WAITINT", + "description": "CPSM waits for interrupt request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "CPSM Waits for ends of data transfer (CmdPend internal signal).", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "Command path state machine (CPSM) Enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SD I/O suspend command", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "Enable CMD completion", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "Not Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CE_ATACMD", + "description": "CE-ATA command", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "Command response register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "Response command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESP1", + "displayName": "RESP1", + "description": "Response 1..4 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Response 1..4 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Response 1..4 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Response 1..4 register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Data timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Data length register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "Data control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "Data transfer direction selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "Data transfer mode selection 1: Stream or SDIO multibyte data transfer.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA enable bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "Data block size", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "RWSTART", + "description": "Read wait start", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWSTOP", + "description": "Read wait stop", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "Read wait mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SD I/O enable functions", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Data counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAIL", + "description": "Command response received (CRC check failed)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "Data block sent/received (CRC check failed)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "Command response timeout", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "Data timeout", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "Transmit FIFO underrun error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "Received FIFO overrun error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "Command response received (CRC check passed)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "Command sent (no response required)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "Data end (data counter, SDIDCOUNT, is zero)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "Start bit not detected on all data signals in wide bus mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "Data block sent/received (CRC check passed)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "Command transfer in progress", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "Data transmit in progress", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "Data receive in progress", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "Transmit FIFO half empty: at least 8 words can be written into the FIFO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "Receive FIFO half full: there are at least 8 words in the FIFO", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "Transmit FIFO full", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "Receive FIFO full", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "Transmit FIFO empty", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "Receive FIFO empty", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "Data available in transmit FIFO", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "Data available in receive FIFO", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIO interrupt received", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAEND", + "description": "CE-ATA command completion signal received for CMD61", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILC", + "description": "CCRCFAIL flag clear bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAIL flag clear bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUT flag clear bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUT flag clear bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERR flag clear bit", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERR flag clear bit", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDREND flag clear bit", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENT flag clear bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAEND flag clear bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERR flag clear bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKEND flag clear bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOIT flag clear bit", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDC", + "description": "CEATAEND flag clear bit", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "Mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILIE", + "description": "Command CRC fail interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "Data CRC fail interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "Command timeout interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "Data timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "Tx FIFO underrun error interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "Rx FIFO overrun error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "Command response received interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "Command sent interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "Data end interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "Start bit error interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDIE", + "description": "Data block end interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "Command acting interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "Data transmit acting interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "Data receive acting interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "Tx FIFO half empty interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "Rx FIFO half full interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "Tx FIFO full interrupt enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "Rx FIFO full interrupt enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "Tx FIFO empty interrupt enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "Rx FIFO empty interrupt enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "Data available in Tx FIFO interrupt enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "Data available in Rx FIFO interrupt enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIO mode interrupt received interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDIE", + "description": "CE-ATA command completion signal received interrupt enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "FIFO counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOCOUNT", + "description": "Remaining number of words to be written to or read from the FIFO.", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Data FIFO register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "Receive and transmit FIFO data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SPI1", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40013000", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI4", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40013400", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ] + }, + { + "name": "SPI5", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40015000" + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MEMRM", + "displayName": "MEMRM", + "description": "Memory remap register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "MEM_MODE", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PMC", + "displayName": "PMC", + "description": "Peripheral mode configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADC1DC2", + "description": "ADC1DC2", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CMPCR", + "displayName": "CMPCR", + "description": "Compensation cell control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMP_PD", + "description": "Compensation cell power-down", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "READY", + "description": "READY", + "bitOffset": "8", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM10", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM11", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Input 1 remapping capability", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ITR1_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM3", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI4", + "description": "SPI4 global interrupt", + "value": "84" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM3", + "baseAddress": "0x40000800" + }, + { + "name": "TIM5", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "IT4_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "6", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40010400" + }, + { + "name": "TIM9", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40011000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS_WKUP", + "description": "USB On-The-Go FS Wakeup through EXTI line interrupt", + "value": "42" + }, + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART6", + "derivedFrom": "USART1", + "baseAddress": "0x40011400", + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB0", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "WDGTB1", + "description": "Timer base", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + } + ], + "cpu": { + "name": "CM4", + "revision": "r0p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "true", + "nvicPrioBits": "4", + "deviceNumInterrupts": "86", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "qemuAlignment": "any" + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/STM32F429x-qemu.json b/gnu-mcu-eclipse/devices/STM32F429x-qemu.json new file mode 100644 index 0000000000..c825d23b9e --- /dev/null +++ b/gnu-mcu-eclipse/devices/STM32F429x-qemu.json @@ -0,0 +1,55348 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F429x.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.9", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F429x.svd", + "--output", + "STM32F429x-xsvd.json" + ], + "date": "2016-12-20T10:25:56.691Z" + }, + { + "tool": "xcdl", + "version": "1.6.9", + "command": [ + "svd-patch", + "--file", + "STM32F429x-xsvd.json", + "--patch", + "STM32F429x-patch.json", + "--output", + "../STM32F429x-qemu.json", + "--group-bitfield", + "RCC/PLLCFGR/PLLQ", + "--group-bitfield", + "RCC/PLLCFGR/PLLP", + "--group-bitfield", + "RCC/PLLCFGR/PLLN", + "--group-bitfield", + "RCC/PLLCFGR/PLLM", + "--group-bitfield", + "RCC/CFGR/SWS", + "--group-bitfield", + "RCC/CFGR/SW", + "--group-bitfield", + "RCC/BDCR/RTCSEL" + ], + "date": "2016-12-20T11:12:20.463Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F429x", + "version": "1.0", + "description": "STM32F429x", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC1", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OVR", + "description": "Overrun", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Resolution", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADON", + "description": "A/D Converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode (for single ADC mode)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DDS", + "description": "DMA disable selection (for single ADC mode)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EOCS", + "description": "End of conversion selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "JEXTEN", + "description": "External trigger enable for injected channels", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "EXTEN", + "description": "External trigger enable for regular channels", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "derivedFrom": "ADC1", + "baseAddress": "0x40012100", + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupts", + "value": "18" + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "derivedFrom": "ADC1", + "baseAddress": "0x40012200", + "interrupts": [ + { + "name": "ADC", + "description": "ADC3 global interrupts", + "value": "18" + } + ], + "qemuGroupName": "ADC" + }, + { + "name": "CAN1", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupts", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ], + "registers": [ + { + "name": "MCR", + "displayName": "MCR", + "description": "Master control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00010002", + "fields": [ + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MSR", + "displayName": "MSR", + "description": "Master status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000C02", + "fields": [ + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "TSR", + "displayName": "TSR", + "description": "Transmit status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x1C000000", + "fields": [ + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "RF0R", + "displayName": "RF0R", + "description": "Receive FIFO 0 register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "RF1R", + "displayName": "RF1R", + "description": "Receive FIFO 1 register", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "ESR", + "displayName": "ESR", + "description": "Interrupt enable register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "BTR", + "displayName": "BTR", + "description": "Bit timing register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "TI0R", + "displayName": "TI0R", + "description": "TX mailbox identifier register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "TDT0R", + "displayName": "TDT0R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "TDL0R", + "displayName": "TDL0R", + "description": "Mailbox data low register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH0R", + "displayName": "TDH0R", + "description": "Mailbox data high register", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TI1R", + "displayName": "TI1R", + "description": "Mailbox identifier register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "TDT1R", + "displayName": "TDT1R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "TDL1R", + "displayName": "TDL1R", + "description": "Mailbox data low register", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH1R", + "displayName": "TDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TI2R", + "displayName": "TI2R", + "description": "Mailbox identifier register", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "TDT2R", + "displayName": "TDT2R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "TDL2R", + "displayName": "TDL2R", + "description": "Mailbox data low register", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH2R", + "displayName": "TDH2R", + "description": "Mailbox data high register", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RI0R", + "displayName": "RI0R", + "description": "Receive FIFO mailbox identifier register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "RDT0R", + "displayName": "RDT0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "RDL0R", + "displayName": "RDL0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH0R", + "displayName": "RDH0R", + "description": "Receive FIFO mailbox data high register", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RI1R", + "displayName": "RI1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + } + ] + }, + { + "name": "RDT1R", + "displayName": "RDT1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "RDL1R", + "displayName": "RDL1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH1R", + "displayName": "RDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "FMR", + "displayName": "FMR", + "description": "Filter master register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2A1C0E01", + "fields": [ + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CAN2SB", + "description": "CAN2SB", + "bitOffset": "8", + "bitWidth": "6" + } + ] + }, + { + "name": "FM1R", + "displayName": "FM1R", + "description": "Filter mode register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FBM14", + "description": "Filter mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FS1R", + "displayName": "FS1R", + "description": "Filter scale register", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FFA1R", + "displayName": "FFA1R", + "description": "Filter FIFO assignment register", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FA1R", + "displayName": "FA1R", + "description": "Filter activation register", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "CAN" + }, + { + "name": "CAN2", + "derivedFrom": "CAN1", + "baseAddress": "0x40006800", + "interrupts": [ + { + "name": "CAN2_TX", + "description": "CAN2 TX interrupts", + "value": "63" + }, + { + "name": "CAN2_RX0", + "description": "CAN2 RX0 interrupts", + "value": "64" + }, + { + "name": "CAN2_RX1", + "description": "CAN2 RX1 interrupts", + "value": "65" + }, + { + "name": "CAN2_SCE", + "description": "CAN2 SCE interrupt", + "value": "66" + } + ], + "qemuGroupName": "CAN" + }, + { + "name": "CRC", + "description": "Cryptographic processor", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Control regidter", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "C_ADC", + "description": "Common ADC registers", + "groupName": "ADC", + "baseAddress": "0x40012300", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "ADC Common status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD1", + "description": "Analog watchdog flag of ADC 1", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EOC1", + "description": "End of conversion of ADC 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "JEOC1", + "description": "Injected channel end of conversion of ADC 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JSTRT1", + "description": "Injected channel Start flag of ADC 1", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "STRT1", + "description": "Regular channel Start flag of ADC 1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OVR1", + "description": "Overrun flag of ADC 1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWD2", + "description": "Analog watchdog flag of ADC 2", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EOC2", + "description": "End of conversion of ADC 2", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "JEOC2", + "description": "Injected channel end of conversion of ADC 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "JSTRT2", + "description": "Injected channel Start flag of ADC 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STRT2", + "description": "Regular channel Start flag of ADC 2", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OVR2", + "description": "Overrun flag of ADC 2", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AWD3", + "description": "Analog watchdog flag of ADC 3", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOC3", + "description": "End of conversion of ADC 3", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "JEOC3", + "description": "Injected channel end of conversion of ADC 3", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "JSTRT3", + "description": "Injected channel Start flag of ADC 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STRT3", + "description": "Regular channel Start flag of ADC 3", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "OVR3", + "description": "Overrun flag of ADC3", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "ADC common control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MULT", + "description": "Multi ADC mode selection", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DELAY", + "description": "Delay between 2 sampling phases", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DDS", + "description": "DMA disable selection for multi-ADC mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode for multi ADC mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "VBATE", + "description": "VBAT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "CDR", + "displayName": "CDR", + "description": "ADC common regular data register for dual and triple modes", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA1", + "description": "1st data item of a pair of regular conversions", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "DATA2", + "description": "2nd data item of a pair of regular conversions", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMAUDRIE1", + "description": "DAC channel1 DMA Underrun Interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DMAUDRIE2", + "description": "DAC channel2 DMA underrun interrupt enable", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "Channel2 12-bit right aligned data holding register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "Channel2 12-bit left aligned data holding register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "Channel2 8-bit right-aligned data holding register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "20", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "Channel2 data output register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DBGMCU_IDCODE", + "displayName": "DBGMCU_IDCODE", + "description": "IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x10006411", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DBGMCU_CR", + "displayName": "DBGMCU_CR", + "description": "Control Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + } + ] + }, + { + "name": "DBGMCU_APB1_FZ", + "displayName": "DBGMCU_APB1_FZ", + "description": "Debug MCU APB1 Freeze registe", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3 _STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DBG_TIM12_STOP", + "description": "DBG_TIM12_STOP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DBG_TIM13_STOP", + "description": "DBG_TIM13_STOP", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DBG_TIM14_STOP", + "description": "DBG_TIM14_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDEG_STOP", + "description": "DBG_IWDEG_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_J2C1_SMBUS_TIMEOUT", + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DBG_J2C2_SMBUS_TIMEOUT", + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBG_J2C3SMBUS_TIMEOUT", + "description": "DBG_J2C3SMBUS_TIMEOUT", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB2_FZ", + "displayName": "DBGMCU_APB2_FZ", + "description": "Debug MCU APB2 Freeze registe", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM1_STOP", + "description": "TIM1 counter stopped when core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "TIM8 counter stopped when core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM9_STOP", + "description": "TIM9 counter stopped when core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM10_STOP", + "description": "TIM10 counter stopped when core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM11_STOP", + "description": "TIM11 counter stopped when core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DCMI", + "description": "Digital camera interface", + "groupName": "DCMI", + "baseAddress": "0x50050000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DCMI", + "description": "DCMI global interrupt", + "value": "78" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CAPTURE", + "description": "Capture enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CM", + "description": "Capture mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CROP", + "description": "Crop feature", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "JPEG", + "description": "JPEG format", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ESS", + "description": "Embedded synchronization select", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PCKPOL", + "description": "Pixel clock polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HSPOL", + "description": "Horizontal synchronization polarity", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "VSPOL", + "description": "Vertical synchronization polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FCRC", + "description": "Frame capture rate control", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "EDM", + "description": "Extended data mode", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "ENABLE", + "description": "DCMI enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "HSYNC", + "description": "HSYNC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "VSYNC", + "description": "VSYNC", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FNE", + "description": "FIFO not empty", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "RIS", + "displayName": "RIS", + "description": "Raw interrupt status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_RIS", + "description": "Capture complete raw interrupt status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_RIS", + "description": "Overrun raw interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_RIS", + "description": "Synchronization error raw interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_RIS", + "description": "VSYNC raw interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_RIS", + "description": "Line raw interrupt status", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_IE", + "description": "Capture complete interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_IE", + "description": "Overrun interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_IE", + "description": "Synchronization error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_IE", + "description": "VSYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_IE", + "description": "Line interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "MIS", + "displayName": "MIS", + "description": "Masked interrupt status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_MIS", + "description": "Capture complete masked interrupt status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_MIS", + "description": "Overrun masked interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_MIS", + "description": "Synchronization error masked interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_MIS", + "description": "VSYNC masked interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_MIS", + "description": "Line masked interrupt status", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FRAME_ISC", + "description": "Capture complete interrupt status clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OVR_ISC", + "description": "Overrun interrupt status clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ERR_ISC", + "description": "Synchronization error interrupt status clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC_ISC", + "description": "Vertical synch interrupt status clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LINE_ISC", + "description": "Line interrupt status clear", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "ESCR", + "displayName": "ESCR", + "description": "Embedded synchronization code register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FSC", + "description": "Frame start delimiter code", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LSC", + "description": "Line start delimiter code", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "LEC", + "description": "Line end delimiter code", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "FEC", + "description": "Frame end delimiter code", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ESUR", + "displayName": "ESUR", + "description": "Embedded synchronization unmask register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FSU", + "description": "Frame start delimiter unmask", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LSU", + "description": "Line start delimiter unmask", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "LEU", + "description": "Line end delimiter unmask", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "FEU", + "description": "Frame end delimiter unmask", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "CWSTRT", + "displayName": "CWSTRT", + "description": "Crop window start", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "HOFFCNT", + "description": "Horizontal offset count", + "bitOffset": "0", + "bitWidth": "14" + }, + { + "name": "VST", + "description": "Vertical start line count", + "bitOffset": "16", + "bitWidth": "13" + } + ] + }, + { + "name": "CWSIZE", + "displayName": "CWSIZE", + "description": "Crop window size", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CAPCNT", + "description": "Capture count", + "bitOffset": "0", + "bitWidth": "14" + }, + { + "name": "VLINE", + "description": "Vertical line count", + "bitOffset": "16", + "bitWidth": "14" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "Byte0", + "description": "Data byte 0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "Byte1", + "description": "Data byte 1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "Byte2", + "description": "Data byte 2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "Byte3", + "description": "Data byte 3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "DMA1", + "derivedFrom": "DMA2", + "baseAddress": "0x40026000", + "interrupts": [ + { + "name": "DMA1_Stream0", + "description": "DMA1 Stream0 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Stream1", + "description": "DMA1 Stream1 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Stream2", + "description": "DMA1 Stream2 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Stream3", + "description": "DMA1 Stream3 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Stream4", + "description": "DMA1 Stream4 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Stream5", + "description": "DMA1 Stream5 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Stream6", + "description": "DMA1 Stream6 global interrupt", + "value": "17" + }, + { + "name": "DMA1_Stream7", + "description": "DMA1 Stream7 global interrupt", + "value": "47" + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40026400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA2_Stream0", + "description": "DMA2 Stream0 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Stream1", + "description": "DMA2 Stream1 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Stream2", + "description": "DMA2 Stream2 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Stream3", + "description": "DMA2 Stream3 global interrupt", + "value": "59" + }, + { + "name": "DMA2_Stream4", + "description": "DMA2 Stream4 global interrupt", + "value": "60" + }, + { + "name": "DMA2_Stream5", + "description": "DMA2 Stream5 global interrupt", + "value": "68" + }, + { + "name": "DMA2_Stream6", + "description": "DMA2 Stream6 global interrupt", + "value": "69" + }, + { + "name": "DMA2_Stream7", + "description": "DMA2 Stream7 global interrupt", + "value": "70" + } + ], + "registers": [ + { + "name": "LISR", + "displayName": "LISR", + "description": "Low interrupt status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FEIF0", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIF0", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF0", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "HTIF0", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF0", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FEIF1", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMEIF1", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FEIF2", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMEIF2", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FEIF3", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMEIF3", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "HISR", + "displayName": "HISR", + "description": "High interrupt status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FEIF4", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIF4", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FEIF5", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMEIF5", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FEIF6", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMEIF6", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FEIF7", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMEIF7", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "LIFCR", + "displayName": "LIFCR", + "description": "Low interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFEIF0", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CDMEIF0", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF0", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHTIF0", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF0", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CFEIF1", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CDMEIF1", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CFEIF2", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CDMEIF2", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CFEIF3", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CDMEIF3", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "HIFCR", + "displayName": "HIFCR", + "description": "High interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFEIF4", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CDMEIF4", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CFEIF5", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CDMEIF5", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CFEIF6", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CDMEIF6", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CFEIF7", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CDMEIF7", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "S0CR", + "displayName": "S0CR", + "description": "Stream x configuration register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S0NDTR", + "displayName": "S0NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S0PAR", + "displayName": "S0PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M0AR", + "displayName": "S0M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M1AR", + "displayName": "S0M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0FCR", + "displayName": "S0FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S1CR", + "displayName": "S1CR", + "description": "Stream x configuration register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S1NDTR", + "displayName": "S1NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S1PAR", + "displayName": "S1PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M0AR", + "displayName": "S1M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M1AR", + "displayName": "S1M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1FCR", + "displayName": "S1FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x3C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S2CR", + "displayName": "S2CR", + "description": "Stream x configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S2NDTR", + "displayName": "S2NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S2PAR", + "displayName": "S2PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M0AR", + "displayName": "S2M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M1AR", + "displayName": "S2M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2FCR", + "displayName": "S2FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S3CR", + "displayName": "S3CR", + "description": "Stream x configuration register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S3NDTR", + "displayName": "S3NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S3PAR", + "displayName": "S3PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M0AR", + "displayName": "S3M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M1AR", + "displayName": "S3M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3FCR", + "displayName": "S3FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x6C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S4CR", + "displayName": "S4CR", + "description": "Stream x configuration register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S4NDTR", + "displayName": "S4NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S4PAR", + "displayName": "S4PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M0AR", + "displayName": "S4M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M1AR", + "displayName": "S4M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4FCR", + "displayName": "S4FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S5CR", + "displayName": "S5CR", + "description": "Stream x configuration register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S5NDTR", + "displayName": "S5NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S5PAR", + "displayName": "S5PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M0AR", + "displayName": "S5M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M1AR", + "displayName": "S5M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5FCR", + "displayName": "S5FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x9C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S6CR", + "displayName": "S6CR", + "description": "Stream x configuration register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S6NDTR", + "displayName": "S6NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S6PAR", + "displayName": "S6PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M0AR", + "displayName": "S6M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M1AR", + "displayName": "S6M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6FCR", + "displayName": "S6FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xB4", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "S7CR", + "displayName": "S7CR", + "description": "Stream x configuration register", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + } + ] + }, + { + "name": "S7NDTR", + "displayName": "S7NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xBC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S7PAR", + "displayName": "S7PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xC0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M0AR", + "displayName": "S7M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M1AR", + "displayName": "S7M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xC8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7FCR", + "displayName": "S7FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xCC", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ], + "qemuGroupName": "DMA" + }, + { + "name": "DMA2D", + "description": "DMA2D controller", + "groupName": "DMA2D", + "baseAddress": "0x4002B000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0xC00", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA2D", + "description": "DMA2D global interrupt", + "value": "90" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "START", + "description": "Start", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SUSP", + "description": "Suspend", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ABORT", + "description": "Abort", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TWIE", + "description": "Transfer watermark interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CAEIE", + "description": "CLUT access error interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTCIE", + "description": "CLUT transfer complete interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CEIE", + "description": "Configuration Error Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MODE", + "description": "DMA2D mode", + "bitOffset": "16", + "bitWidth": "2" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt Status Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TEIF", + "description": "Transfer error interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF", + "description": "Transfer complete interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TWIF", + "description": "Transfer watermark interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CAEIF", + "description": "CLUT access error interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTCIF", + "description": "CLUT transfer complete interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CEIF", + "description": "Configuration error interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "Interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTEIF", + "description": "Clear Transfer error interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CTCIF", + "description": "Clear transfer complete interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTWIF", + "description": "Clear transfer watermark interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CAECIF", + "description": "Clear CLUT access error interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCTCIF", + "description": "Clear CLUT transfer complete interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CCEIF", + "description": "Clear configuration error interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "FGMAR", + "displayName": "FGMAR", + "description": "Foreground memory address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FGOR", + "displayName": "FGOR", + "description": "Foreground offset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LO", + "description": "Line offset", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "BGMAR", + "displayName": "BGMAR", + "description": "Background memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BGOR", + "displayName": "BGOR", + "description": "Background offset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LO", + "description": "Line offset", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "FGPFCCR", + "displayName": "FGPFCCR", + "description": "Foreground PFC control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CM", + "description": "Color mode", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "CCM", + "description": "CLUT color mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CS", + "description": "CLUT size", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "AM", + "description": "Alpha mode", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "ALPHA", + "description": "Alpha value", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "FGCOLR", + "displayName": "FGCOLR", + "description": "Foreground color register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BLUE", + "description": "Blue Value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green Value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red Value", + "bitOffset": "16", + "bitWidth": "8" + } + ] + }, + { + "name": "BGPFCCR", + "displayName": "BGPFCCR", + "description": "Background PFC control register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CM", + "description": "Color mode", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "CCM", + "description": "CLUT Color mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CS", + "description": "CLUT size", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "AM", + "description": "Alpha mode", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "ALPHA", + "description": "Alpha value", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "BGCOLR", + "displayName": "BGCOLR", + "description": "Background color register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BLUE", + "description": "Blue Value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green Value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red Value", + "bitOffset": "16", + "bitWidth": "8" + } + ] + }, + { + "name": "FGCMAR", + "displayName": "FGCMAR", + "description": "Foreground CLUT memory address register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BGCMAR", + "displayName": "BGCMAR", + "description": "Background CLUT memory address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPFCCR", + "displayName": "OPFCCR", + "description": "Output PFC control register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CM", + "description": "Color mode", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "OCOLR", + "displayName": "OCOLR", + "description": "Output color register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BLUE", + "description": "Blue Value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green Value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red Value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "APLHA", + "description": "Alpha Channel Value", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "OMAR", + "displayName": "OMAR", + "description": "Output memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OOR", + "displayName": "OOR", + "description": "Output offset register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LO", + "description": "Line Offset", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "NLR", + "displayName": "NLR", + "description": "Number of line register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NL", + "description": "Number of lines", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PL", + "description": "Pixel per lines", + "bitOffset": "16", + "bitWidth": "14" + } + ] + }, + { + "name": "LWR", + "displayName": "LWR", + "description": "Line watermark register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LW", + "description": "Line watermark", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "AMTCR", + "displayName": "AMTCR", + "description": "AHB master timer configuration register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Dead Time", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "FGCLUT", + "displayName": "FGCLUT", + "description": "FGCLUT", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BLUE", + "description": "BLUE", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "GREEN", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "RED", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "APLHA", + "description": "APLHA", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "BGCLUT", + "displayName": "BGCLUT", + "description": "BGCLUT", + "addressOffset": "0x800", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BLUE", + "description": "BLUE", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "GREEN", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "RED", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "APLHA", + "description": "APLHA", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40013C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMP_STAMP", + "description": "Tamper and TimeStamp interrupts through the EXTI line", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Rising trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Rising trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Rising trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Falling trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Falling trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Falling trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SWIER20", + "description": "Software Interrupt on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SWIER21", + "description": "Software Interrupt on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWIER22", + "description": "Software Interrupt on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PR20", + "description": "Pending bit 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PR21", + "description": "Pending bit 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PR22", + "description": "Pending bit 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "Ethernet_DMA", + "description": "Ethernet: DMA controller operation", + "groupName": "Ethernet", + "baseAddress": "0x40029000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DMABMR", + "displayName": "DMABMR", + "description": "Ethernet DMA bus mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "SR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DA", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DSL", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "5" + }, + { + "name": "EDFE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PBL", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "RTPR", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "FB", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "6" + }, + { + "name": "USP", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FPM", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AAB", + "description": "No description available", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MB", + "description": "No description available", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMATPDR", + "displayName": "DMATPDR", + "description": "Ethernet DMA transmit poll demand register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARPDR", + "displayName": "DMARPDR", + "description": "EHERNET DMA receive poll demand register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RPD", + "description": "RPD", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARDLAR", + "displayName": "DMARDLAR", + "description": "Ethernet DMA receive descriptor list address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SRL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMATDLAR", + "displayName": "DMATDLAR", + "description": "Ethernet DMA transmit descriptor list address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMASR", + "displayName": "DMASR", + "description": "Ethernet DMA status register", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TPSS", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TBUS", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TJTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ROS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TUS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RBUS", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPSS", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PWTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETS", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FBES", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AIS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NIS", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "TPS", + "description": "No description available", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "EBS", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DMAOMR", + "displayName": "DMAOMR", + "description": "Ethernet DMA operation mode register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SR", + "description": "SR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OSF", + "description": "OSF", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTC", + "description": "RTC", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "FUGF", + "description": "FUGF", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FEF", + "description": "FEF", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "ST", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TTC", + "description": "TTC", + "bitOffset": "14", + "bitWidth": "3" + }, + { + "name": "FTF", + "description": "FTF", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TSF", + "description": "TSF", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DFRF", + "description": "DFRF", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "RSF", + "description": "RSF", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DTCEFD", + "description": "DTCEFD", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAIER", + "displayName": "DMAIER", + "description": "Ethernet DMA interrupt enable register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPSIE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TBUIE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TJTIE", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ROIE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TUIE", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RIE", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RBUIE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RPSIE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWTIE", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ETIE", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBEIE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ERIE", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AISE", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NISE", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAMFBOCR", + "displayName": "DMAMFBOCR", + "description": "Ethernet DMA missed frame and buffer overflow counter register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OMFC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MFA", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "11" + }, + { + "name": "OFOC", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "DMARSWTR", + "displayName": "DMARSWTR", + "description": "Ethernet DMA receive status watchdog timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RSWTC", + "description": "RSWTC", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DMACHTDR", + "displayName": "DMACHTDR", + "description": "Ethernet DMA current host transmit descriptor register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTDAP", + "description": "HTDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRDR", + "displayName": "DMACHRDR", + "description": "Ethernet DMA current host receive descriptor register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRDAP", + "description": "HRDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHTBAR", + "displayName": "DMACHTBAR", + "description": "Ethernet DMA current host transmit buffer address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRBAR", + "displayName": "DMACHRBAR", + "description": "Ethernet DMA current host receive buffer address register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_MAC", + "description": "Ethernet: media access control (MAC)", + "groupName": "Ethernet", + "baseAddress": "0x40028000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ETH", + "description": "Ethernet global interrupt", + "value": "61" + }, + { + "name": "ETH_WKUP", + "description": "Ethernet Wakeup through EXTI line interrupt", + "value": "62" + } + ], + "registers": [ + { + "name": "MACCR", + "displayName": "MACCR", + "description": "Ethernet MAC configuration register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0008000", + "fields": [ + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "DC", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BL", + "description": "BL", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "APCS", + "description": "APCS", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RD", + "description": "RD", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IPCO", + "description": "IPCO", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DM", + "description": "DM", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LM", + "description": "LM", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ROD", + "description": "ROD", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FES", + "description": "FES", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CSD", + "description": "CSD", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "IFG", + "description": "IFG", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JD", + "description": "JD", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WD", + "description": "WD", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CSTF", + "description": "CSTF", + "bitOffset": "25", + "bitWidth": "1" + } + ] + }, + { + "name": "MACFFR", + "displayName": "MACFFR", + "description": "Ethernet MAC frame filter register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HM", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAIF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RAM", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BFD", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PCF", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SAIF", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SAF", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HPF", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RA", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACHTHR", + "displayName": "MACHTHR", + "description": "Ethernet MAC hash table high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACHTLR", + "displayName": "MACHTLR", + "description": "Ethernet MAC hash table low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACMIIAR", + "displayName": "MACMIIAR", + "description": "Ethernet MAC MII address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MW", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "3" + }, + { + "name": "MR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "5" + }, + { + "name": "PA", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "5" + } + ] + }, + { + "name": "MACMIIDR", + "displayName": "MACMIIDR", + "description": "Ethernet MAC MII data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "MACFCR", + "displayName": "MACFCR", + "description": "Ethernet MAC flow control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FCB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TFCE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RFCE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UPFD", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLT", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ZQPD", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "MACVLANTR", + "displayName": "MACVLANTR", + "description": "Ethernet MAC VLAN tag register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VLANTI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "VLANTC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MACPMTCSR", + "displayName": "MACPMTCSR", + "description": "Ethernet MAC PMT control and status register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MPE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WFE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MPR", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WFR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GU", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WFFRPR", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACDBGR", + "displayName": "MACDBGR", + "description": "Ethernet MAC debug register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "CR", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "CSR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "ROR", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "MCF", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "MCP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "MCFHP", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MACSR", + "displayName": "MACSR", + "description": "Ethernet MAC interrupt status register", + "addressOffset": "0x38", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCRS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCTS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "MACIMR", + "displayName": "MACIMR", + "description": "Ethernet MAC interrupt mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTIM", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSTIM", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA0HR", + "displayName": "MACA0HR", + "description": "Ethernet MAC address 0 high register", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x0010FFFF", + "fields": [ + { + "name": "MACA0H", + "description": "MAC address0 high", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "MO", + "description": "Always 1", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "MACA0LR", + "displayName": "MACA0LR", + "description": "Ethernet MAC address 0 low register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA0L", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA1HR", + "displayName": "MACA1HR", + "description": "Ethernet MAC address 1 high register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA1H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA1LR", + "displayName": "MACA1LR", + "description": "Ethernet MAC address1 low register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA1LR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA2HR", + "displayName": "MACA2HR", + "description": "Ethernet MAC address 2 high register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MAC2AH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA2LR", + "displayName": "MACA2LR", + "description": "Ethernet MAC address 2 low register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA2L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + } + ] + }, + { + "name": "MACA3HR", + "displayName": "MACA3HR", + "description": "Ethernet MAC address 3 high register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA3H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA3LR", + "displayName": "MACA3LR", + "description": "Ethernet MAC address 3 low register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MBCA3L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_MMC", + "description": "Ethernet: MAC management counters", + "groupName": "Ethernet", + "baseAddress": "0x40028100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MMCCR", + "displayName": "MMCCR", + "description": "Ethernet MMC control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIR", + "displayName": "MMCRIR", + "description": "Ethernet MMC receive interrupt register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCES", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAES", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIR", + "displayName": "MMCTIR", + "description": "Ethernet MMC transmit interrupt register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFS", + "description": "No description available", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIMR", + "displayName": "MMCRIMR", + "description": "Ethernet MMC receive interrupt mask register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCEM", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAEM", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFM", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIMR", + "displayName": "MMCTIMR", + "description": "Ethernet MMC transmit interrupt mask register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCM", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCM", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFM", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTGFSCCR", + "displayName": "MMCTGFSCCR", + "description": "Ethernet MMC transmitted good frames after a single collision counter", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFMSCCR", + "displayName": "MMCTGFMSCCR", + "description": "Ethernet MMC transmitted good frames after more than a single collision", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFMSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFCR", + "displayName": "MMCTGFCR", + "description": "Ethernet MMC transmitted good frames counter register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFC", + "description": "HTL", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFCECR", + "displayName": "MMCRFCECR", + "description": "Ethernet MMC received frames with CRC error counter register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFAECR", + "displayName": "MMCRFAECR", + "description": "Ethernet MMC received frames with alignment error counter register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFAEC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRGUFCR", + "displayName": "MMCRGUFCR", + "description": "MMC received good unicast frames counter register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RGUFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_PTP", + "description": "Ethernet: Precision time protocol", + "groupName": "Ethernet", + "baseAddress": "0x40028700", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "PTPTSCR", + "displayName": "PTPTSCR", + "description": "Ethernet PTP time stamp control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "TSE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSFCU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSSTI", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSSTU", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSITE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TTSARU", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TSSARFE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TSSSR", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TSPTPPSV2E", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TSSPTPOEFE", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TSSIPV6FE", + "description": "No description available", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TSSIPV4FE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TSSEME", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TSSMRME", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TSCNT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "TSPFFMAE", + "description": "No description available", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPSSIR", + "displayName": "PTPSSIR", + "description": "Ethernet PTP subsecond increment register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSSI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PTPTSHR", + "displayName": "PTPTSHR", + "description": "Ethernet PTP time stamp high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLR", + "displayName": "PTPTSLR", + "description": "Ethernet PTP time stamp low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "STPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSHUR", + "displayName": "PTPTSHUR", + "description": "Ethernet PTP time stamp high update register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLUR", + "displayName": "PTPTSLUR", + "description": "Ethernet PTP time stamp low update register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "TSUPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSAR", + "displayName": "PTPTSAR", + "description": "Ethernet PTP time stamp addend register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSA", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTHR", + "displayName": "PTPTTHR", + "description": "Ethernet PTP target time high register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSH", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTLR", + "displayName": "PTPTTLR", + "description": "Ethernet PTP target time low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSSR", + "displayName": "PTPTSSR", + "description": "Ethernet PTP time stamp status register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPPPSCR", + "displayName": "PTPPPSCR", + "description": "Ethernet PTP PPS control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "TSSO", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "TSTTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40023C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bitOffset": "11", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OPERR", + "description": "Operation error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGPERR", + "description": "Programming parallelism error", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x80000000", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SER", + "description": "Sector Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase of sectors 0 to 11", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SNB", + "description": "Sector number", + "bitOffset": "3", + "bitWidth": "5" + }, + { + "name": "PSIZE", + "description": "Program size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MER1", + "description": "Mass Erase of sectors 12 to 23", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OPTCR", + "displayName": "OPTCR", + "description": "Flash option control register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFAAED", + "fields": [ + { + "name": "OPTLOCK", + "description": "Option lock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OPTSTRT", + "description": "Option start", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "WDG_SW", + "description": "WDG_SW User option bytes", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP User option bytes", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY User option bytes", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Read protect", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "OPTCR1", + "displayName": "OPTCR1", + "description": "Flash option control register 1", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFF0000", + "fields": [ + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "FMC", + "description": "Flexible memory controller", + "groupName": "FSMC", + "baseAddress": "0xA0000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FMC", + "description": "FMC global interrupt", + "value": "48" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "SRAM/NOR-Flash chip-select control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CCLKEN", + "description": "CCLKEN", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR1", + "displayName": "BTR1", + "description": "SRAM/NOR-Flash chip-select timing register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "SRAM/NOR-Flash chip-select control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR2", + "displayName": "BTR2", + "description": "SRAM/NOR-Flash chip-select timing register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR3", + "displayName": "BCR3", + "description": "SRAM/NOR-Flash chip-select control register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR3", + "displayName": "BTR3", + "description": "SRAM/NOR-Flash chip-select timing register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR4", + "displayName": "BCR4", + "description": "SRAM/NOR-Flash chip-select control register 4", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR4", + "displayName": "BTR4", + "description": "SRAM/NOR-Flash chip-select timing register 4", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "PCR2", + "displayName": "PCR2", + "description": "PC Card/NAND Flash control register 2", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "FIFO status and interrupt register 2", + "addressOffset": "0x64", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM2", + "displayName": "PMEM2", + "description": "Common memory space timing register 2", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT2", + "displayName": "PATT2", + "description": "Attribute memory space timing register 2", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR2", + "displayName": "ECCR2", + "description": "ECC result register 2", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR3", + "displayName": "PCR3", + "description": "PC Card/NAND Flash control register 3", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR3", + "displayName": "SR3", + "description": "FIFO status and interrupt register 3", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM3", + "displayName": "PMEM3", + "description": "Common memory space timing register 3", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT3", + "displayName": "PATT3", + "description": "Attribute memory space timing register 3", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR3", + "displayName": "ECCR3", + "description": "ECC result register 3", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR4", + "displayName": "PCR4", + "description": "PC Card/NAND Flash control register 4", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + } + ] + }, + { + "name": "SR4", + "displayName": "SR4", + "description": "FIFO status and interrupt register 4", + "addressOffset": "0xA4", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PMEM4", + "displayName": "PMEM4", + "description": "Common memory space timing register 4", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT4", + "displayName": "PATT4", + "description": "Attribute memory space timing register 4", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "PIO4", + "displayName": "PIO4", + "description": "I/O space timing register 4", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "IOSETx", + "description": "IOSETx", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IOWAITx", + "description": "IOWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IOHOLDx", + "description": "IOHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IOHIZx", + "description": "IOHIZx", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "BWTR1", + "displayName": "BWTR1", + "description": "SRAM/NOR-Flash write timing registers 1", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR2", + "displayName": "BWTR2", + "description": "SRAM/NOR-Flash write timing registers 2", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR3", + "displayName": "BWTR3", + "description": "SRAM/NOR-Flash write timing registers 3", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "BWTR4", + "displayName": "BWTR4", + "description": "SRAM/NOR-Flash write timing registers 4", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + } + ] + }, + { + "name": "SDCR1", + "displayName": "SDCR1", + "description": "SDRAM Control Register 1", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000002D0", + "fields": [ + { + "name": "NC", + "description": "Number of column address bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NR", + "description": "Number of row address bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "Memory data bus width", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "NB", + "description": "Number of internal banks", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CAS", + "description": "CAS latency", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "WP", + "description": "Write protection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SDCLK", + "description": "SDRAM clock configuration", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "RBURST", + "description": "Burst read", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RPIPE", + "description": "Read pipe", + "bitOffset": "13", + "bitWidth": "2" + } + ] + }, + { + "name": "SDCR2", + "displayName": "SDCR2", + "description": "SDRAM Control Register 2", + "addressOffset": "0x144", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000002D0", + "fields": [ + { + "name": "NC", + "description": "Number of column address bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NR", + "description": "Number of row address bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "Memory data bus width", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "NB", + "description": "Number of internal banks", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CAS", + "description": "CAS latency", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "WP", + "description": "Write protection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SDCLK", + "description": "SDRAM clock configuration", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "RBURST", + "description": "Burst read", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RPIPE", + "description": "Read pipe", + "bitOffset": "13", + "bitWidth": "2" + } + ] + }, + { + "name": "SDTR1", + "displayName": "SDTR1", + "description": "SDRAM Timing register 1", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "TMRD", + "description": "Load Mode Register to Active", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TXSR", + "description": "Exit self-refresh delay", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "TRAS", + "description": "Self refresh time", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "TRC", + "description": "Row cycle delay", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "TWR", + "description": "Recovery delay", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TRP", + "description": "Row precharge delay", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "TRCD", + "description": "Row to column delay", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "SDTR2", + "displayName": "SDTR2", + "description": "SDRAM Timing register 2", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "TMRD", + "description": "Load Mode Register to Active", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TXSR", + "description": "Exit self-refresh delay", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "TRAS", + "description": "Self refresh time", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "TRC", + "description": "Row cycle delay", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "TWR", + "description": "Recovery delay", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TRP", + "description": "Row precharge delay", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "TRCD", + "description": "Row to column delay", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "SDCMR", + "displayName": "SDCMR", + "description": "SDRAM Command Mode register", + "addressOffset": "0x150", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODE", + "description": "Command mode", + "bitOffset": "0", + "bitWidth": "3", + "access": "write-only" + }, + { + "name": "CTB2", + "description": "Command target bank 2", + "bitOffset": "3", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CTB1", + "description": "Command target bank 1", + "bitOffset": "4", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "NRFS", + "description": "Number of Auto-refresh", + "bitOffset": "5", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "MRD", + "description": "Mode Register definition", + "bitOffset": "9", + "bitWidth": "13", + "access": "read-write" + } + ] + }, + { + "name": "SDRTR", + "displayName": "SDRTR", + "description": "SDRAM Refresh Timer register", + "addressOffset": "0x154", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CRE", + "description": "Clear Refresh error flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "COUNT", + "description": "Refresh Timer Count", + "bitOffset": "1", + "bitWidth": "13", + "access": "read-write" + }, + { + "name": "REIE", + "description": "RES Interrupt Enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SDSR", + "displayName": "SDSR", + "description": "SDRAM Status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RE", + "description": "Refresh error flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MODES1", + "description": "Status Mode for Bank 1", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "MODES2", + "description": "Status Mode for Bank 2", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "BUSY", + "description": "Busy status", + "bitOffset": "5", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xA8000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x64000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000280", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000C0", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000100", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOK", + "baseAddress": "0x40020800", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOK", + "baseAddress": "0X40020C00", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021000", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021400", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOG", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021800", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOH", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021C00", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOI", + "derivedFrom": "GPIOK", + "baseAddress": "0x40022000", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOJ", + "derivedFrom": "GPIOK", + "baseAddress": "0x40022400", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOK", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40022800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + } + ] + } + ], + "qemuGroupName": "GPIO" + }, + { + "name": "I2C1", + "derivedFrom": "I2C3", + "baseAddress": "0x40005400", + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "derivedFrom": "I2C3", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2C3", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "FLTR", + "displayName": "FLTR", + "description": "I2C FLTR register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DNF", + "description": "Digital noise filter", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ANOFF", + "description": "Analog noise filter OFF", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "I2C" + }, + { + "name": "I2S2ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40003400" + }, + { + "name": "I2S3ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40004000" + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value (write only, read 0000h)", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "LTDC", + "description": "LCD-TFT Controller", + "groupName": "LTDC", + "baseAddress": "0x40016800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "LCD_TFT", + "description": "LTDC global interrupt", + "value": "88" + }, + { + "name": "LCD_TFT_1", + "description": "LTDC global error interrupt", + "value": "89" + } + ], + "registers": [ + { + "name": "SSCR", + "displayName": "SSCR", + "description": "Synchronization Size Configuration Register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VSH", + "description": "Vertical Synchronization Height (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "HSW", + "description": "Horizontal Synchronization Width (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "BPCR", + "displayName": "BPCR", + "description": "Back Porch Configuration Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AVBP", + "description": "Accumulated Vertical back porch (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "AHBP", + "description": "Accumulated Horizontal back porch (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "AWCR", + "displayName": "AWCR", + "description": "Active Width Configuration Register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AAH", + "description": "Accumulated Active Height (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "AAW", + "description": "Accumulated Active Width (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "TWCR", + "displayName": "TWCR", + "description": "Total Width Configuration Register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TOTALH", + "description": "Total Height (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "TOTALW", + "description": "Total Width (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "GCR", + "displayName": "GCR", + "description": "Global Control Register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00002220", + "fields": [ + { + "name": "LTDCEN", + "description": "LCD-TFT controller enable bit", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DBW", + "description": "Dither Blue Width", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DGW", + "description": "Dither Green Width", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DRW", + "description": "Dither Red Width", + "bitOffset": "12", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DEN", + "description": "Dither Enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PCPOL", + "description": "Pixel Clock Polarity", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DEPOL", + "description": "Data Enable Polarity", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VSPOL", + "description": "Vertical Synchronization Polarity", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSPOL", + "description": "Horizontal Synchronization Polarity", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SRCR", + "displayName": "SRCR", + "description": "Shadow Reload Configuration Register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IMR", + "description": "Immediate Reload", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "VBR", + "description": "Vertical Blanking Reload", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "BCCR", + "displayName": "BCCR", + "description": "Background Color Configuration Register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BC", + "description": "Background Color Red value", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt Enable Register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LIE", + "description": "Line Interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FUIE", + "description": "FIFO Underrun Interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TERRIE", + "description": "Transfer Error Interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RRIE", + "description": "Register Reload interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt Status Register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LIF", + "description": "Line Interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FUIF", + "description": "FIFO Underrun Interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TERRIF", + "description": "Transfer Error interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RRIF", + "description": "Register Reload Interrupt Flag", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt Clear Register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLIF", + "description": "Clears the Line Interrupt Flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CFUIF", + "description": "Clears the FIFO Underrun Interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTERRIF", + "description": "Clears the Transfer Error Interrupt Flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CRRIF", + "description": "Clears Register Reload Interrupt Flag", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "LIPCR", + "displayName": "LIPCR", + "description": "Line Interrupt Position Configuration Register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LIPOS", + "description": "Line Interrupt Position", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "CPSR", + "displayName": "CPSR", + "description": "Current Position Status Register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CYPOS", + "description": "Current Y Position", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CXPOS", + "description": "Current X Position", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CDSR", + "displayName": "CDSR", + "description": "Current Display Status Register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000000F", + "fields": [ + { + "name": "VDES", + "description": "Vertical Data Enable display Status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HDES", + "description": "Horizontal Data Enable display Status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "VSYNCS", + "description": "Vertical Synchronization display Status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HSYNCS", + "description": "Horizontal Synchronization display Status", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "L1CR", + "displayName": "L1CR", + "description": "Layerx Control Register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LEN", + "description": "Layer Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "COLKEN", + "description": "Color Keying Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CLUTEN", + "description": "Color Look-Up Table Enable", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "L1WHPCR", + "displayName": "L1WHPCR", + "description": "Layerx Window Horizontal Position Configuration Register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WHSTPOS", + "description": "Window Horizontal Start Position", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "WHSPPOS", + "description": "Window Horizontal Stop Position", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "L1WVPCR", + "displayName": "L1WVPCR", + "description": "Layerx Window Vertical Position Configuration Register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WVSTPOS", + "description": "Window Vertical Start Position", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "WVSPPOS", + "description": "Window Vertical Stop Position", + "bitOffset": "16", + "bitWidth": "11" + } + ] + }, + { + "name": "L1CKCR", + "displayName": "L1CKCR", + "description": "Layerx Color Keying Configuration Register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CKBLUE", + "description": "Color Key Blue value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "CKGREEN", + "description": "Color Key Green value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CKRED", + "description": "Color Key Red value", + "bitOffset": "16", + "bitWidth": "8" + } + ] + }, + { + "name": "L1PFCR", + "displayName": "L1PFCR", + "description": "Layerx Pixel Format Configuration Register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PF", + "description": "Pixel Format", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "L1CACR", + "displayName": "L1CACR", + "description": "Layerx Constant Alpha Configuration Register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CONSTA", + "description": "Constant Alpha", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L1DCCR", + "displayName": "L1DCCR", + "description": "Layerx Default Color Configuration Register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCBLUE", + "description": "Default Color Blue", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DCGREEN", + "description": "Default Color Green", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DCRED", + "description": "Default Color Red", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DCALPHA", + "description": "Default Color Alpha", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "L1BFCR", + "displayName": "L1BFCR", + "description": "Layerx Blending Factors Configuration Register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000607", + "fields": [ + { + "name": "BF2", + "description": "Blending Factor 2", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "BF1", + "description": "Blending Factor 1", + "bitOffset": "8", + "bitWidth": "3" + } + ] + }, + { + "name": "L1CFBAR", + "displayName": "L1CFBAR", + "description": "Layerx Color Frame Buffer Address Register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBADD", + "description": "Color Frame Buffer Start Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "L1CFBLR", + "displayName": "L1CFBLR", + "description": "Layerx Color Frame Buffer Length Register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBLL", + "description": "Color Frame Buffer Line Length", + "bitOffset": "0", + "bitWidth": "13" + }, + { + "name": "CFBP", + "description": "Color Frame Buffer Pitch in bytes", + "bitOffset": "16", + "bitWidth": "13" + } + ] + }, + { + "name": "L1CFBLNR", + "displayName": "L1CFBLNR", + "description": "Layerx ColorFrame Buffer Line Number Register", + "addressOffset": "0xB4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBLNBR", + "description": "Frame Buffer Line Number", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "L1CLUTWR", + "displayName": "L1CLUTWR", + "description": "Layerx CLUT Write Register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BLUE", + "description": "Blue value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "CLUTADD", + "description": "CLUT Address", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "L2CR", + "displayName": "L2CR", + "description": "Layerx Control Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LEN", + "description": "Layer Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "COLKEN", + "description": "Color Keying Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CLUTEN", + "description": "Color Look-Up Table Enable", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "L2WHPCR", + "displayName": "L2WHPCR", + "description": "Layerx Window Horizontal Position Configuration Register", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WHSTPOS", + "description": "Window Horizontal Start Position", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "WHSPPOS", + "description": "Window Horizontal Stop Position", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "L2WVPCR", + "displayName": "L2WVPCR", + "description": "Layerx Window Vertical Position Configuration Register", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WVSTPOS", + "description": "Window Vertical Start Position", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "WVSPPOS", + "description": "Window Vertical Stop Position", + "bitOffset": "16", + "bitWidth": "11" + } + ] + }, + { + "name": "L2CKCR", + "displayName": "L2CKCR", + "description": "Layerx Color Keying Configuration Register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CKBLUE", + "description": "Color Key Blue value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "CKGREEN", + "description": "Color Key Green value", + "bitOffset": "8", + "bitWidth": "7" + }, + { + "name": "CKRED", + "description": "Color Key Red value", + "bitOffset": "15", + "bitWidth": "9" + } + ] + }, + { + "name": "L2PFCR", + "displayName": "L2PFCR", + "description": "Layerx Pixel Format Configuration Register", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PF", + "description": "Pixel Format", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "L2CACR", + "displayName": "L2CACR", + "description": "Layerx Constant Alpha Configuration Register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CONSTA", + "description": "Constant Alpha", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L2DCCR", + "displayName": "L2DCCR", + "description": "Layerx Default Color Configuration Register", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCBLUE", + "description": "Default Color Blue", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DCGREEN", + "description": "Default Color Green", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DCRED", + "description": "Default Color Red", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DCALPHA", + "description": "Default Color Alpha", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "L2BFCR", + "displayName": "L2BFCR", + "description": "Layerx Blending Factors Configuration Register", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000607", + "fields": [ + { + "name": "BF2", + "description": "Blending Factor 2", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "BF1", + "description": "Blending Factor 1", + "bitOffset": "8", + "bitWidth": "3" + } + ] + }, + { + "name": "L2CFBAR", + "displayName": "L2CFBAR", + "description": "Layerx Color Frame Buffer Address Register", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBADD", + "description": "Color Frame Buffer Start Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "L2CFBLR", + "displayName": "L2CFBLR", + "description": "Layerx Color Frame Buffer Length Register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBLL", + "description": "Color Frame Buffer Line Length", + "bitOffset": "0", + "bitWidth": "13" + }, + { + "name": "CFBP", + "description": "Color Frame Buffer Pitch in bytes", + "bitOffset": "16", + "bitWidth": "13" + } + ] + }, + { + "name": "L2CFBLNR", + "displayName": "L2CFBLNR", + "description": "Layerx ColorFrame Buffer Line Number Register", + "addressOffset": "0x134", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBLNBR", + "description": "Frame Buffer Line Number", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "L2CLUTWR", + "displayName": "L2CLUTWR", + "description": "Layerx CLUT Write Register", + "addressOffset": "0x144", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BLUE", + "description": "Blue value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "CLUTADD", + "description": "CLUT Address", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1001", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ICTR", + "displayName": "ICTR", + "description": "Interrupt Controller Type Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTLINESNUM", + "description": "Total number of interrupt lines in groups", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "STIR", + "displayName": "STIR", + "description": "Software Triggered Interrupt Register", + "addressOffset": "0xF00", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTID", + "description": "Interrupt to be triggered", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "ISER0", + "displayName": "ISER0", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER1", + "displayName": "ISER1", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER2", + "displayName": "ISER2", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER0", + "displayName": "ICER0", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER1", + "displayName": "ICER1", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER2", + "displayName": "ICER2", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR0", + "displayName": "ISPR0", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR1", + "displayName": "ISPR1", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR2", + "displayName": "ISPR2", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x208", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR0", + "displayName": "ICPR0", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR1", + "displayName": "ICPR1", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR2", + "displayName": "ICPR2", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR0", + "displayName": "IABR0", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR1", + "displayName": "IABR1", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR2", + "displayName": "IABR2", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register", + "addressOffset": "0x404", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register", + "addressOffset": "0x408", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register", + "addressOffset": "0x40C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register", + "addressOffset": "0x410", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register", + "addressOffset": "0x414", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register", + "addressOffset": "0x418", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register", + "addressOffset": "0x41C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR8", + "displayName": "IPR8", + "description": "Interrupt Priority Register", + "addressOffset": "0x420", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR9", + "displayName": "IPR9", + "description": "Interrupt Priority Register", + "addressOffset": "0x424", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR10", + "displayName": "IPR10", + "description": "Interrupt Priority Register", + "addressOffset": "0x428", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR11", + "displayName": "IPR11", + "description": "Interrupt Priority Register", + "addressOffset": "0x42C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR12", + "displayName": "IPR12", + "description": "Interrupt Priority Register", + "addressOffset": "0x430", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR13", + "displayName": "IPR13", + "description": "Interrupt Priority Register", + "addressOffset": "0x434", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR14", + "displayName": "IPR14", + "description": "Interrupt Priority Register", + "addressOffset": "0x438", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR15", + "displayName": "IPR15", + "description": "Interrupt Priority Register", + "addressOffset": "0x43C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR16", + "displayName": "IPR16", + "description": "Interrupt Priority Register", + "addressOffset": "0x440", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR17", + "displayName": "IPR17", + "description": "Interrupt Priority Register", + "addressOffset": "0x444", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR18", + "displayName": "IPR18", + "description": "Interrupt Priority Register", + "addressOffset": "0x448", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR19", + "displayName": "IPR19", + "description": "Interrupt Priority Register", + "addressOffset": "0x44C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR20", + "displayName": "IPR20", + "description": "Interrupt Priority Register", + "addressOffset": "0x450", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "OTG_FS_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS_WKUP", + "description": "USB On-The-Go FS Wakeup through EXTI line interrupt", + "value": "42" + }, + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "OTG_FS_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_HS_DEVICE", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_DCFG", + "displayName": "OTG_HS_DCFG", + "description": "OTG_HS device configuration register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Nonzero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic (micro)frame interval", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "PERSCHIVL", + "description": "Periodic scheduling interval", + "bitOffset": "24", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DCTL", + "displayName": "OTG_HS_DCTL", + "description": "OTG_HS device control register", + "addressOffset": "0x4", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DSTS", + "displayName": "OTG_HS_DSTS", + "description": "OTG_HS device status register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "OTG_HS_DIEPMSK", + "displayName": "OTG_HS_DIEPMSK", + "description": "OTG_HS device IN endpoint common interrupt mask register", + "addressOffset": "0x10", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPMSK", + "displayName": "OTG_HS_DOEPMSK", + "description": "OTG_HS device OUT endpoint common interrupt mask register", + "addressOffset": "0x14", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OPEM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BOIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DAINT", + "displayName": "OTG_HS_DAINT", + "description": "OTG_HS device all endpoints interrupt register", + "addressOffset": "0x18", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DAINTMSK", + "displayName": "OTG_HS_DAINTMSK", + "description": "OTG_HS all endpoints interrupt mask register", + "addressOffset": "0x1C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPM", + "description": "OUT EP interrupt mask bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSDIS", + "displayName": "OTG_HS_DVBUSDIS", + "description": "OTG_HS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSPULSE", + "displayName": "OTG_HS_DVBUSPULSE", + "description": "OTG_HS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "OTG_HS_DTHRCTL", + "displayName": "OTG_HS_DTHRCTL", + "description": "OTG_HS Device threshold control register", + "addressOffset": "0x30", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "NONISOTHREN", + "description": "Nonisochronous IN endpoints threshold enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ISOTHREN", + "description": "ISO IN endpoint threshold enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXTHRLEN", + "description": "Transmit threshold length", + "bitOffset": "2", + "bitWidth": "9" + }, + { + "name": "RXTHREN", + "description": "Receive threshold enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXTHRLEN", + "description": "Receive threshold length", + "bitOffset": "17", + "bitWidth": "9" + }, + { + "name": "ARPEN", + "description": "Arbiter parking enable", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEMPMSK", + "displayName": "OTG_HS_DIEPEMPMSK", + "description": "OTG_HS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DEACHINT", + "displayName": "OTG_HS_DEACHINT", + "description": "OTG_HS device each endpoint interrupt register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INT", + "description": "IN endpoint 1interrupt bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INT", + "description": "OUT endpoint 1 interrupt bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DEACHINTMSK", + "displayName": "OTG_HS_DEACHINTMSK", + "description": "OTG_HS device each endpoint interrupt register mask", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INTM", + "description": "IN Endpoint 1 interrupt mask bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INTM", + "description": "OUT Endpoint 1 interrupt mask bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEACHMSK1", + "displayName": "OTG_HS_DIEPEACHMSK1", + "description": "OTG_HS device each in endpoint-1 interrupt register", + "addressOffset": "0x40", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPEACHMSK1", + "displayName": "OTG_HS_DOEPEACHMSK1", + "description": "OTG_HS device each OUT endpoint-1 interrupt register", + "addressOffset": "0x80", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BERRM", + "description": "Bubble error interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "NYETM", + "description": "NYET interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL0", + "displayName": "OTG_HS_DIEPCTL0", + "description": "OTG device endpoint-0 control register", + "addressOffset": "0x100", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL1", + "displayName": "OTG_HS_DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL2", + "displayName": "OTG_HS_DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL3", + "displayName": "OTG_HS_DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL4", + "displayName": "OTG_HS_DIEPCTL4", + "description": "OTG device endpoint-4 control register", + "addressOffset": "0x180", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL5", + "displayName": "OTG_HS_DIEPCTL5", + "description": "OTG device endpoint-5 control register", + "addressOffset": "0x1A0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL6", + "displayName": "OTG_HS_DIEPCTL6", + "description": "OTG device endpoint-6 control register", + "addressOffset": "0x1C0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL7", + "displayName": "OTG_HS_DIEPCTL7", + "description": "OTG device endpoint-7 control register", + "addressOffset": "0x1E0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT0", + "displayName": "OTG_HS_DIEPINT0", + "description": "OTG device endpoint-0 interrupt register", + "addressOffset": "0x108", + "size": "32", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT1", + "displayName": "OTG_HS_DIEPINT1", + "description": "OTG device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT2", + "displayName": "OTG_HS_DIEPINT2", + "description": "OTG device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT3", + "displayName": "OTG_HS_DIEPINT3", + "description": "OTG device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT4", + "displayName": "OTG_HS_DIEPINT4", + "description": "OTG device endpoint-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT5", + "displayName": "OTG_HS_DIEPINT5", + "description": "OTG device endpoint-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT6", + "displayName": "OTG_HS_DIEPINT6", + "description": "OTG device endpoint-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT7", + "displayName": "OTG_HS_DIEPINT7", + "description": "OTG device endpoint-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ0", + "displayName": "OTG_HS_DIEPTSIZ0", + "description": "OTG_HS device IN endpoint 0 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA1", + "displayName": "OTG_HS_DIEPDMA1", + "description": "OTG_HS device endpoint-1 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA2", + "displayName": "OTG_HS_DIEPDMA2", + "description": "OTG_HS device endpoint-2 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA3", + "displayName": "OTG_HS_DIEPDMA3", + "description": "OTG_HS device endpoint-3 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA4", + "displayName": "OTG_HS_DIEPDMA4", + "description": "OTG_HS device endpoint-4 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA5", + "displayName": "OTG_HS_DIEPDMA5", + "description": "OTG_HS device endpoint-5 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS0", + "displayName": "OTG_HS_DTXFSTS0", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS1", + "displayName": "OTG_HS_DTXFSTS1", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS2", + "displayName": "OTG_HS_DTXFSTS2", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS3", + "displayName": "OTG_HS_DTXFSTS3", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS4", + "displayName": "OTG_HS_DTXFSTS4", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x198", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS5", + "displayName": "OTG_HS_DTXFSTS5", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x1B8", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ1", + "displayName": "OTG_HS_DIEPTSIZ1", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ2", + "displayName": "OTG_HS_DIEPTSIZ2", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ3", + "displayName": "OTG_HS_DIEPTSIZ3", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ4", + "displayName": "OTG_HS_DIEPTSIZ4", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ5", + "displayName": "OTG_HS_DIEPTSIZ5", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL0", + "displayName": "OTG_HS_DOEPCTL0", + "description": "OTG_HS device control OUT endpoint 0 control register", + "addressOffset": "0x300", + "size": "32", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL1", + "displayName": "OTG_HS_DOEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x320", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL2", + "displayName": "OTG_HS_DOEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x340", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL3", + "displayName": "OTG_HS_DOEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x360", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPINT0", + "displayName": "OTG_HS_DOEPINT0", + "description": "OTG_HS device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "32", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT1", + "displayName": "OTG_HS_DOEPINT1", + "description": "OTG_HS device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT2", + "displayName": "OTG_HS_DOEPINT2", + "description": "OTG_HS device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT3", + "displayName": "OTG_HS_DOEPINT3", + "description": "OTG_HS device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT4", + "displayName": "OTG_HS_DOEPINT4", + "description": "OTG_HS device endpoint-4 interrupt register", + "addressOffset": "0x388", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT5", + "displayName": "OTG_HS_DOEPINT5", + "description": "OTG_HS device endpoint-5 interrupt register", + "addressOffset": "0x3A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT6", + "displayName": "OTG_HS_DOEPINT6", + "description": "OTG_HS device endpoint-6 interrupt register", + "addressOffset": "0x3C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT7", + "displayName": "OTG_HS_DOEPINT7", + "description": "OTG_HS device endpoint-7 interrupt register", + "addressOffset": "0x3E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ0", + "displayName": "OTG_HS_DOEPTSIZ0", + "description": "OTG_HS device endpoint-1 transfer size register", + "addressOffset": "0x310", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ1", + "displayName": "OTG_HS_DOEPTSIZ1", + "description": "OTG_HS device endpoint-2 transfer size register", + "addressOffset": "0x330", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ2", + "displayName": "OTG_HS_DOEPTSIZ2", + "description": "OTG_HS device endpoint-3 transfer size register", + "addressOffset": "0x350", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ3", + "displayName": "OTG_HS_DOEPTSIZ3", + "description": "OTG_HS device endpoint-4 transfer size register", + "addressOffset": "0x370", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ4", + "displayName": "OTG_HS_DOEPTSIZ4", + "description": "OTG_HS device endpoint-5 transfer size register", + "addressOffset": "0x390", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_HS_GLOBAL", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_HS_EP1_OUT", + "description": "USB On The Go HS End Point 1 Out global interrupt", + "value": "74" + }, + { + "name": "OTG_HS_EP1_IN", + "description": "USB On The Go HS End Point 1 In global interrupt", + "value": "75" + }, + { + "name": "OTG_HS_WKUP", + "description": "USB On The Go HS Wakeup through EXTI interrupt", + "value": "76" + }, + { + "name": "OTG_HS", + "description": "USB On The Go HS global interrupt", + "value": "77" + } + ], + "registers": [ + { + "name": "OTG_HS_GOTGCTL", + "displayName": "OTG_HS_GOTGCTL", + "description": "OTG_HS control and status register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GOTGINT", + "displayName": "OTG_HS_GOTGINT", + "description": "OTG_HS interrupt register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GAHBCFG", + "displayName": "OTG_HS_GAHBCFG", + "description": "OTG_HS AHB configuration register", + "addressOffset": "0x8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HBSTLEN", + "description": "Burst length/type", + "bitOffset": "1", + "bitWidth": "4" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GUSBCFG", + "displayName": "OTG_HS_GUSBCFG", + "description": "OTG_HS USB configuration register", + "addressOffset": "0xC", + "size": "32", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PHYLPCS", + "description": "PHY Low-power clock select", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIFSLS", + "description": "ULPI FS/LS select", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIAR", + "description": "ULPI Auto-resume", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPICSM", + "description": "ULPI Clock SuspendM", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSD", + "description": "ULPI External VBUS Drive", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSI", + "description": "ULPI external VBUS indicator", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSDPS", + "description": "TermSel DLine pulsing selection", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PCCI", + "description": "Indicator complement", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCI", + "description": "Indicator pass through", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIIPD", + "description": "ULPI interface protect disable", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Forced host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Forced peripheral mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRSTCTL", + "displayName": "OTG_HS_GRSTCTL", + "description": "OTG_HS reset register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "DMAREQ", + "description": "DMA request signal", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GINTSTS", + "displayName": "OTG_HS_GINTSTS", + "description": "OTG_HS core interrupt register", + "addressOffset": "0x14", + "size": "32", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO nonempty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Nonperiodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN nonperiodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DATAFSUSP", + "description": "Data fetch suspended", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GINTMSK", + "displayName": "OTG_HS_GINTMSK", + "description": "OTG_HS interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO nonempty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Nonperiodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global nonperiodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FSUSPM", + "description": "Data fetch suspended mask", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Host", + "displayName": "OTG_HS_GRXSTSR_Host", + "description": "OTG_HS Receive status debug read register (host mode)", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Host", + "displayName": "OTG_HS_GRXSTSP_Host", + "description": "OTG_HS status read and pop register (host mode)", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXFSIZ", + "displayName": "OTG_HS_GRXFSIZ", + "description": "OTG_HS Receive FIFO size register", + "addressOffset": "0x24", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXFSIZ_Host", + "displayName": "OTG_HS_GNPTXFSIZ_Host", + "description": "OTG_HS nonperiodic transmit FIFO size register (host mode)", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Nonperiodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Nonperiodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_TX0FSIZ_Peripheral", + "displayName": "OTG_HS_TX0FSIZ_Peripheral", + "description": "Endpoint 0 transmit FIFO size (peripheral mode)", + "headerStructName": "OTG_HS_GNPTXFSIZ_Host", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXSTS", + "displayName": "OTG_HS_GNPTXSTS", + "description": "OTG_HS nonperiodic transmit FIFO/queue status register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Nonperiodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Nonperiodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the nonperiodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "OTG_HS_GCCFG", + "displayName": "OTG_HS_GCCFG", + "description": "OTG_HS general core configuration register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2CPADEN", + "description": "Enable I2C bus connection for the external I2C PHY interface", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "NOVBUSSENS", + "description": "VBUS sensing disable option", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_CID", + "displayName": "OTG_HS_CID", + "description": "OTG_HS core ID register", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x00001200", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HPTXFSIZ", + "displayName": "OTG_HS_HPTXFSIZ", + "description": "OTG_HS Host periodic transmit FIFO size register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFD", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF1", + "displayName": "OTG_HS_DIEPTXF1", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF2", + "displayName": "OTG_HS_DIEPTXF2", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF3", + "displayName": "OTG_HS_DIEPTXF3", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x11C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF4", + "displayName": "OTG_HS_DIEPTXF4", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF5", + "displayName": "OTG_HS_DIEPTXF5", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF6", + "displayName": "OTG_HS_DIEPTXF6", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF7", + "displayName": "OTG_HS_DIEPTXF7", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Peripheral", + "displayName": "OTG_HS_GRXSTSR_Peripheral", + "description": "OTG_HS Receive status debug read register (peripheral mode mode)", + "headerStructName": "OTG_HS_GRXSTSR_Host", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Peripheral", + "displayName": "OTG_HS_GRXSTSP_Peripheral", + "description": "OTG_HS status read and pop register (peripheral mode)", + "headerStructName": "OTG_HS_GRXSTSP_Host", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "OTG_HS_HOST", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_HCFG", + "displayName": "OTG_HS_HCFG", + "description": "OTG_HS host configuration register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HFIR", + "displayName": "OTG_HS_HFIR", + "description": "OTG_HS Host frame interval register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HFNUM", + "displayName": "OTG_HS_HFNUM", + "description": "OTG_HS host frame number/frame time remaining register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPTXSTS", + "displayName": "OTG_HS_HPTXSTS", + "description": "OTG_HS_Host periodic transmit FIFO/queue status register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HAINT", + "displayName": "OTG_HS_HAINT", + "description": "OTG_HS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HAINTMSK", + "displayName": "OTG_HS_HAINTMSK", + "description": "OTG_HS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPRT", + "displayName": "OTG_HS_HPRT", + "description": "OTG_HS host port control and status register", + "addressOffset": "0x40", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HCCHAR0", + "displayName": "OTG_HS_HCCHAR0", + "description": "OTG_HS host channel-0 characteristics register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR1", + "displayName": "OTG_HS_HCCHAR1", + "description": "OTG_HS host channel-1 characteristics register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR2", + "displayName": "OTG_HS_HCCHAR2", + "description": "OTG_HS host channel-2 characteristics register", + "addressOffset": "0x140", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR3", + "displayName": "OTG_HS_HCCHAR3", + "description": "OTG_HS host channel-3 characteristics register", + "addressOffset": "0x160", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR4", + "displayName": "OTG_HS_HCCHAR4", + "description": "OTG_HS host channel-4 characteristics register", + "addressOffset": "0x180", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR5", + "displayName": "OTG_HS_HCCHAR5", + "description": "OTG_HS host channel-5 characteristics register", + "addressOffset": "0x1A0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR6", + "displayName": "OTG_HS_HCCHAR6", + "description": "OTG_HS host channel-6 characteristics register", + "addressOffset": "0x1C0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR7", + "displayName": "OTG_HS_HCCHAR7", + "description": "OTG_HS host channel-7 characteristics register", + "addressOffset": "0x1E0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR8", + "displayName": "OTG_HS_HCCHAR8", + "description": "OTG_HS host channel-8 characteristics register", + "addressOffset": "0x200", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR9", + "displayName": "OTG_HS_HCCHAR9", + "description": "OTG_HS host channel-9 characteristics register", + "addressOffset": "0x220", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR10", + "displayName": "OTG_HS_HCCHAR10", + "description": "OTG_HS host channel-10 characteristics register", + "addressOffset": "0x240", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR11", + "displayName": "OTG_HS_HCCHAR11", + "description": "OTG_HS host channel-11 characteristics register", + "addressOffset": "0x260", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT0", + "displayName": "OTG_HS_HCSPLT0", + "description": "OTG_HS host channel-0 split control register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT1", + "displayName": "OTG_HS_HCSPLT1", + "description": "OTG_HS host channel-1 split control register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT2", + "displayName": "OTG_HS_HCSPLT2", + "description": "OTG_HS host channel-2 split control register", + "addressOffset": "0x144", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT3", + "displayName": "OTG_HS_HCSPLT3", + "description": "OTG_HS host channel-3 split control register", + "addressOffset": "0x164", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT4", + "displayName": "OTG_HS_HCSPLT4", + "description": "OTG_HS host channel-4 split control register", + "addressOffset": "0x184", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT5", + "displayName": "OTG_HS_HCSPLT5", + "description": "OTG_HS host channel-5 split control register", + "addressOffset": "0x1A4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT6", + "displayName": "OTG_HS_HCSPLT6", + "description": "OTG_HS host channel-6 split control register", + "addressOffset": "0x1C4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT7", + "displayName": "OTG_HS_HCSPLT7", + "description": "OTG_HS host channel-7 split control register", + "addressOffset": "0x1E4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT8", + "displayName": "OTG_HS_HCSPLT8", + "description": "OTG_HS host channel-8 split control register", + "addressOffset": "0x204", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT9", + "displayName": "OTG_HS_HCSPLT9", + "description": "OTG_HS host channel-9 split control register", + "addressOffset": "0x224", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT10", + "displayName": "OTG_HS_HCSPLT10", + "description": "OTG_HS host channel-10 split control register", + "addressOffset": "0x244", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT11", + "displayName": "OTG_HS_HCSPLT11", + "description": "OTG_HS host channel-11 split control register", + "addressOffset": "0x264", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT0", + "displayName": "OTG_HS_HCINT0", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT1", + "displayName": "OTG_HS_HCINT1", + "description": "OTG_HS host channel-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT2", + "displayName": "OTG_HS_HCINT2", + "description": "OTG_HS host channel-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT3", + "displayName": "OTG_HS_HCINT3", + "description": "OTG_HS host channel-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT4", + "displayName": "OTG_HS_HCINT4", + "description": "OTG_HS host channel-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT5", + "displayName": "OTG_HS_HCINT5", + "description": "OTG_HS host channel-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT6", + "displayName": "OTG_HS_HCINT6", + "description": "OTG_HS host channel-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT7", + "displayName": "OTG_HS_HCINT7", + "description": "OTG_HS host channel-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT8", + "displayName": "OTG_HS_HCINT8", + "description": "OTG_HS host channel-8 interrupt register", + "addressOffset": "0x208", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT9", + "displayName": "OTG_HS_HCINT9", + "description": "OTG_HS host channel-9 interrupt register", + "addressOffset": "0x228", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT10", + "displayName": "OTG_HS_HCINT10", + "description": "OTG_HS host channel-10 interrupt register", + "addressOffset": "0x248", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT11", + "displayName": "OTG_HS_HCINT11", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x268", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK0", + "displayName": "OTG_HS_HCINTMSK0", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x10C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK1", + "displayName": "OTG_HS_HCINTMSK1", + "description": "OTG_HS host channel-1 interrupt mask register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK2", + "displayName": "OTG_HS_HCINTMSK2", + "description": "OTG_HS host channel-2 interrupt mask register", + "addressOffset": "0x14C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK3", + "displayName": "OTG_HS_HCINTMSK3", + "description": "OTG_HS host channel-3 interrupt mask register", + "addressOffset": "0x16C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK4", + "displayName": "OTG_HS_HCINTMSK4", + "description": "OTG_HS host channel-4 interrupt mask register", + "addressOffset": "0x18C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK5", + "displayName": "OTG_HS_HCINTMSK5", + "description": "OTG_HS host channel-5 interrupt mask register", + "addressOffset": "0x1AC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK6", + "displayName": "OTG_HS_HCINTMSK6", + "description": "OTG_HS host channel-6 interrupt mask register", + "addressOffset": "0x1CC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK7", + "displayName": "OTG_HS_HCINTMSK7", + "description": "OTG_HS host channel-7 interrupt mask register", + "addressOffset": "0x1EC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK8", + "displayName": "OTG_HS_HCINTMSK8", + "description": "OTG_HS host channel-8 interrupt mask register", + "addressOffset": "0x20C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK9", + "displayName": "OTG_HS_HCINTMSK9", + "description": "OTG_HS host channel-9 interrupt mask register", + "addressOffset": "0x22C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK10", + "displayName": "OTG_HS_HCINTMSK10", + "description": "OTG_HS host channel-10 interrupt mask register", + "addressOffset": "0x24C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK11", + "displayName": "OTG_HS_HCINTMSK11", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x26C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ0", + "displayName": "OTG_HS_HCTSIZ0", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ1", + "displayName": "OTG_HS_HCTSIZ1", + "description": "OTG_HS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ2", + "displayName": "OTG_HS_HCTSIZ2", + "description": "OTG_HS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ3", + "displayName": "OTG_HS_HCTSIZ3", + "description": "OTG_HS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ4", + "displayName": "OTG_HS_HCTSIZ4", + "description": "OTG_HS host channel-4 transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ5", + "displayName": "OTG_HS_HCTSIZ5", + "description": "OTG_HS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ6", + "displayName": "OTG_HS_HCTSIZ6", + "description": "OTG_HS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ7", + "displayName": "OTG_HS_HCTSIZ7", + "description": "OTG_HS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ8", + "displayName": "OTG_HS_HCTSIZ8", + "description": "OTG_HS host channel-8 transfer size register", + "addressOffset": "0x210", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ9", + "displayName": "OTG_HS_HCTSIZ9", + "description": "OTG_HS host channel-9 transfer size register", + "addressOffset": "0x230", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ10", + "displayName": "OTG_HS_HCTSIZ10", + "description": "OTG_HS host channel-10 transfer size register", + "addressOffset": "0x250", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ11", + "displayName": "OTG_HS_HCTSIZ11", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x270", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCDMA0", + "displayName": "OTG_HS_HCDMA0", + "description": "OTG_HS host channel-0 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA1", + "displayName": "OTG_HS_HCDMA1", + "description": "OTG_HS host channel-1 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA2", + "displayName": "OTG_HS_HCDMA2", + "description": "OTG_HS host channel-2 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA3", + "displayName": "OTG_HS_HCDMA3", + "description": "OTG_HS host channel-3 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA4", + "displayName": "OTG_HS_HCDMA4", + "description": "OTG_HS host channel-4 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA5", + "displayName": "OTG_HS_HCDMA5", + "description": "OTG_HS host channel-5 DMA address register", + "addressOffset": "0x1B4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA6", + "displayName": "OTG_HS_HCDMA6", + "description": "OTG_HS host channel-6 DMA address register", + "addressOffset": "0x1D4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA7", + "displayName": "OTG_HS_HCDMA7", + "description": "OTG_HS host channel-7 DMA address register", + "addressOffset": "0x1F4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA8", + "displayName": "OTG_HS_HCDMA8", + "description": "OTG_HS host channel-8 DMA address register", + "addressOffset": "0x214", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA9", + "displayName": "OTG_HS_HCDMA9", + "description": "OTG_HS host channel-9 DMA address register", + "addressOffset": "0x234", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA10", + "displayName": "OTG_HS_HCDMA10", + "description": "OTG_HS host channel-10 DMA address register", + "addressOffset": "0x254", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA11", + "displayName": "OTG_HS_HCDMA11", + "description": "OTG_HS host channel-11 DMA address register", + "addressOffset": "0x274", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "OTG_HS_PWRCLK", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x3F200", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_PCGCR", + "displayName": "OTG_HS_PCGCR", + "description": "Power and clock gating control register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000C000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FPDS", + "description": "Flash power down in Stop mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LPUDS", + "description": "Low-Power Regulator Low Voltage in deepsleep", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MRUDS", + "description": "Main regulator low voltage in deepsleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ADCDC1", + "description": "ADCDC1", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "VOS", + "description": "Regulator voltage scaling output selection", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "ODEN", + "description": "Over-drive enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ODSWEN", + "description": "Over-drive switching enabled", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "UDEN", + "description": "Under-drive enable in stop mode", + "bitOffset": "18", + "bitWidth": "2" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BRR", + "description": "Backup regulator ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BRE", + "description": "Backup regulator enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VOSRDY", + "description": "Regulator voltage scaling output selection ready bit", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ODRDY", + "description": "Over-drive mode ready", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ODSWRDY", + "description": "Over-drive mode switching ready", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDRDY", + "description": "Under-drive ready flag", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40023800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal high-speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal high-speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal high-speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal high-speed clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "HSE clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "HSE clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "HSE clock bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock security system enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "Main PLL (PLL) enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "Main PLL (PLL) clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SON", + "description": "PLLI2S enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLI2SRDY", + "description": "PLLI2S clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PLLCFGR", + "displayName": "PLLCFGR", + "description": "PLL configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003010", + "fields": [ + { + "name": "PLLM", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "PLLN", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLP", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PLLSRC", + "description": "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PLLQ", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System clock switch status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "10", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB high-speed prescaler (APB2)", + "bitOffset": "13", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "RTCPRE", + "description": "HSE division factor for RTC clock", + "bitOffset": "16", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "MCO1", + "description": "Microcontroller clock output 1", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "I2SSRC", + "description": "I2S clock selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO1PRE", + "description": "MCO1 prescaler", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO2PRE", + "description": "MCO2 prescaler", + "bitOffset": "27", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO2", + "description": "Microcontroller clock output 2", + "bitOffset": "30", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI ready interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE ready interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI ready interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE ready interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "Main PLL (PLL) ready interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SRDYF", + "description": "PLLI2S ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLSAIRDYF", + "description": "PLLSAI ready interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock security system interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI ready interrupt enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE ready interrupt enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI ready interrupt enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE ready interrupt enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "Main PLL (PLL) ready interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLI2SRDYIE", + "description": "PLLI2S ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLSAIRDYIE", + "description": "PLLSAI Ready Interrupt Enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI ready interrupt clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE ready interrupt clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI ready interrupt clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE ready interrupt clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "Main PLL(PLL) ready interrupt clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYC", + "description": "PLLI2S ready interrupt clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLSAIRDYC", + "description": "PLLSAI Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "AHB1RSTR", + "displayName": "AHB1RSTR", + "description": "AHB1 peripheral reset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GPIOARST", + "description": "IO port A reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBRST", + "description": "IO port B reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCRST", + "description": "IO port C reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODRST", + "description": "IO port D reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOERST", + "description": "IO port E reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOFRST", + "description": "IO port F reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOGRST", + "description": "IO port G reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOHRST", + "description": "IO port H reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOIRST", + "description": "IO port I reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOJRST", + "description": "IO port J reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "GPIOKRST", + "description": "IO port K reset", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CRCRST", + "description": "CRC reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMA1RST", + "description": "DMA2 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2RST", + "description": "DMA2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA2DRST", + "description": "DMA2D reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ETHMACRST", + "description": "Ethernet MAC reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "OTGHSRST", + "description": "USB OTG HS module reset", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2RSTR", + "displayName": "AHB2RSTR", + "description": "AHB2 peripheral reset register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCMIRST", + "description": "Camera interface reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RNGRST", + "description": "Random number generator module reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSRST", + "description": "USB OTG FS module reset", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3RSTR", + "displayName": "AHB3RSTR", + "description": "AHB3 peripheral reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMCRST", + "description": "Flexible memory controller module reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "TIM2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "TIM3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "TIM4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "TIM5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "TIM6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12RST", + "description": "TIM12 reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13RST", + "description": "TIM13 reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "TIM14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI 2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI 3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "UART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4RST", + "description": "USART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5RST", + "description": "USART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C 1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C 2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3RST", + "description": "I2C3 reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1RST", + "description": "CAN1 reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2RST", + "description": "CAN2 reset", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "UART7RST", + "description": "UART7 reset", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "UART8RST", + "description": "UART8 reset", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1RST", + "description": "TIM1 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8RST", + "description": "TIM8 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6RST", + "description": "USART6 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset (common to all ADCs)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIORST", + "description": "SDIO reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4RST", + "description": "SPI4 reset", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGRST", + "description": "System configuration controller reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11RST", + "description": "TIM11 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SPI5RST", + "description": "SPI5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SPI6RST", + "description": "SPI6 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SAI1RST", + "description": "SAI1 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "LTDCRST", + "description": "LTDC reset", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1ENR", + "displayName": "AHB1ENR", + "description": "AHB1 peripheral clock register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00100000", + "fields": [ + { + "name": "GPIOAEN", + "description": "IO port A clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBEN", + "description": "IO port B clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCEN", + "description": "IO port C clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODEN", + "description": "IO port D clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOEEN", + "description": "IO port E clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOFEN", + "description": "IO port F clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOGEN", + "description": "IO port G clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOHEN", + "description": "IO port H clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOIEN", + "description": "IO port I clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOJEN", + "description": "IO port J clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "GPIOKEN", + "description": "IO port K clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKPSRAMEN", + "description": "Backup SRAM interface clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CCMDATARAMEN", + "description": "CCM data RAM clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA2DEN", + "description": "DMA2D clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ETHMACEN", + "description": "Ethernet MAC clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "ETHMACTXEN", + "description": "Ethernet Transmission clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACRXEN", + "description": "Ethernet Reception clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPEN", + "description": "Ethernet PTP clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "OTGHSEN", + "description": "USB OTG HS clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "OTGHSULPIEN", + "description": "USB OTG HSULPI clock enable", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2ENR", + "displayName": "AHB2ENR", + "description": "AHB2 peripheral clock enable register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCMIEN", + "description": "Camera interface enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RNGEN", + "description": "Random number generator clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3ENR", + "displayName": "AHB3ENR", + "description": "AHB3 peripheral clock enable register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMCEN", + "description": "Flexible memory controller module clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "TIM2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "TIM3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "TIM4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "TIM5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "TIM6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12EN", + "description": "TIM12 clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13EN", + "description": "TIM13 clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "TIM14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3EN", + "description": "I2C3 clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1EN", + "description": "CAN 1 clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2EN", + "description": "CAN 2 clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "UART7ENR", + "description": "UART7 clock enable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "UART8ENR", + "description": "UART8 clock enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1EN", + "description": "TIM1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8EN", + "description": "TIM8 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6EN", + "description": "USART6 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC1 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC2 clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC3EN", + "description": "ADC3 clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4ENR", + "description": "SPI4 clock enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGEN", + "description": "System configuration controller clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11EN", + "description": "TIM11 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SPI5ENR", + "description": "SPI5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SPI6ENR", + "description": "SPI6 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SAI1EN", + "description": "SAI1 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "LTDCEN", + "description": "LTDC clock enable", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1LPENR", + "displayName": "AHB1LPENR", + "description": "AHB1 peripheral clock enable in low power mode register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7E6791FF", + "fields": [ + { + "name": "GPIOALPEN", + "description": "IO port A clock enable during sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBLPEN", + "description": "IO port B clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCLPEN", + "description": "IO port C clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODLPEN", + "description": "IO port D clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOELPEN", + "description": "IO port E clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOFLPEN", + "description": "IO port F clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOGLPEN", + "description": "IO port G clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOHLPEN", + "description": "IO port H clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOILPEN", + "description": "IO port I clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOJLPEN", + "description": "IO port J clock enable during Sleep mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "GPIOKLPEN", + "description": "IO port K clock enable during Sleep mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CRCLPEN", + "description": "CRC clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FLITFLPEN", + "description": "Flash interface clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SRAM1LPEN", + "description": "SRAM 1interface clock enable during Sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SRAM2LPEN", + "description": "SRAM 2 interface clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BKPSRAMLPEN", + "description": "Backup SRAM interface clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SRAM3LPEN", + "description": "SRAM 3 interface clock enable during Sleep mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMA1LPEN", + "description": "DMA1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2LPEN", + "description": "DMA2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA2DLPEN", + "description": "DMA2D clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ETHMACLPEN", + "description": "Ethernet MAC clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "ETHMACTXLPEN", + "description": "Ethernet transmission clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACRXLPEN", + "description": "Ethernet reception clock enable during Sleep mode", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPLPEN", + "description": "Ethernet PTP clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "OTGHSLPEN", + "description": "USB OTG HS clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "OTGHSULPILPEN", + "description": "USB OTG HS ULPI clock enable during Sleep mode", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2LPENR", + "displayName": "AHB2LPENR", + "description": "AHB2 peripheral clock enable in low power mode register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000F1", + "fields": [ + { + "name": "DCMILPEN", + "description": "Camera interface enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RNGLPEN", + "description": "Random number generator clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSLPEN", + "description": "USB OTG FS clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3LPENR", + "displayName": "AHB3LPENR", + "description": "AHB3 peripheral clock enable in low power mode register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000001", + "fields": [ + { + "name": "FMCLPEN", + "description": "Flexible memory controller module clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1LPENR", + "displayName": "APB1LPENR", + "description": "APB1 peripheral clock enable in low power mode register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x36FEC9FF", + "fields": [ + { + "name": "TIM2LPEN", + "description": "TIM2 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3LPEN", + "description": "TIM3 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4LPEN", + "description": "TIM4 clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5LPEN", + "description": "TIM5 clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6LPEN", + "description": "TIM6 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7LPEN", + "description": "TIM7 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12LPEN", + "description": "TIM12 clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13LPEN", + "description": "TIM13 clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14LPEN", + "description": "TIM14 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGLPEN", + "description": "Window watchdog clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2LPEN", + "description": "SPI2 clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3LPEN", + "description": "SPI3 clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2LPEN", + "description": "USART2 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3LPEN", + "description": "USART3 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4LPEN", + "description": "UART4 clock enable during Sleep mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5LPEN", + "description": "UART5 clock enable during Sleep mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1LPEN", + "description": "I2C1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2LPEN", + "description": "I2C2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3LPEN", + "description": "I2C3 clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1LPEN", + "description": "CAN 1 clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2LPEN", + "description": "CAN 2 clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWRLPEN", + "description": "Power interface clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACLPEN", + "description": "DAC interface clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "UART7LPEN", + "description": "UART7 clock enable during Sleep mode", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "UART8LPEN", + "description": "UART8 clock enable during Sleep mode", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2LPENR", + "displayName": "APB2LPENR", + "description": "APB2 peripheral clock enabled in low power mode register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00075F33", + "fields": [ + { + "name": "TIM1LPEN", + "description": "TIM1 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8LPEN", + "description": "TIM8 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1LPEN", + "description": "USART1 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6LPEN", + "description": "USART6 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1LPEN", + "description": "ADC1 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC2LPEN", + "description": "ADC2 clock enable during Sleep mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC3LPEN", + "description": "ADC 3 clock enable during Sleep mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOLPEN", + "description": "SDIO clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1LPEN", + "description": "SPI 1 clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4LPEN", + "description": "SPI 4 clock enable during Sleep mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGLPEN", + "description": "System configuration controller clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9LPEN", + "description": "TIM9 clock enable during sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10LPEN", + "description": "TIM10 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11LPEN", + "description": "TIM11 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SPI5LPEN", + "description": "SPI 5 clock enable during Sleep mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SPI6LPEN", + "description": "SPI 6 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SAI1LPEN", + "description": "SAI1 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "LTDCLPEN", + "description": "LTDC clock enable", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register", + "addressOffset": "0x70", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External low-speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Clock control & status register", + "addressOffset": "0x74", + "size": "0x20", + "resetValue": "0x0E000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BORRSTF", + "description": "BOR reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PADRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SSCGR", + "displayName": "SSCGR", + "description": "Spread spectrum clock generation register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODPER", + "description": "Modulation period", + "bitOffset": "0", + "bitWidth": "13" + }, + { + "name": "INCSTEP", + "description": "Incrementation step", + "bitOffset": "13", + "bitWidth": "15" + }, + { + "name": "SPREADSEL", + "description": "Spread Select", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SSCGEN", + "description": "Spread spectrum modulation enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PLLI2SCFGR", + "displayName": "PLLI2SCFGR", + "description": "PLLI2S configuration register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20003000", + "fields": [ + { + "name": "PLLI2SN", + "description": "PLLI2S multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLI2SQ", + "description": "PLLI2S division factor for SAI1 clock", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "PLLI2SR", + "description": "PLLI2S division factor for I2S clocks", + "bitOffset": "28", + "bitWidth": "3" + } + ] + }, + { + "name": "PLLSAICFGR", + "displayName": "PLLSAICFGR", + "description": "PLLSAICFGR", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003000", + "fields": [ + { + "name": "PLLSAIN", + "description": "PLLSAIN", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLSAIQ", + "description": "PLLSAIN", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "PLLSAIR", + "description": "PLLSAIN", + "bitOffset": "28", + "bitWidth": "3" + } + ] + }, + { + "name": "DCKCFGR", + "displayName": "DCKCFGR", + "description": "DCKCFGR", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PLLI2SDIVQ", + "description": "PLLI2SDIVQ", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "PLLSAIDIVQ", + "description": "PLLSAIDIVQ", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "PLLSAIDIVR", + "description": "PLLSAIDIVR", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "SAI1ASRC", + "description": "SAI1ASRC", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "SAI1BSRC", + "description": "SAI1BSRC", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "TIMPRE", + "description": "TIMPRE", + "bitOffset": "24", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "RNG", + "description": "Random number generator", + "groupName": "RNG", + "baseAddress": "0x50060800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FPU", + "description": "FPU interrupt", + "value": "81" + }, + { + "name": "RNG", + "description": "Rng global interrupt", + "value": "80" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RNGEN", + "description": "Random number generator enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IE", + "description": "Interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DRDY", + "description": "Data ready", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CECS", + "description": "Clock error current status", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SECS", + "description": "Seed error current status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CEIS", + "description": "Clock error interrupt status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SEIS", + "description": "Seed error interrupt status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RNDATA", + "description": "Random data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC_WKUP", + "description": "RTC Wakeup interrupt through the EXTI line", + "value": "3" + }, + { + "name": "RTC_Alarm", + "description": "RTC Alarms (A and B) through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WCKSEL", + "description": "Wakeup clock selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "REFCKON", + "description": "Reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCE", + "description": "Coarse digital calibration enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ALRBE", + "description": "Alarm B enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WUTE", + "description": "Wakeup timer enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ALRBIE", + "description": "Alarm B interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WUTIE", + "description": "Wakeup timer interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALRBWF", + "description": "Alarm B write flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "WUTWF", + "description": "Wakeup timer write flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRBF", + "description": "Alarm B flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUTF", + "description": "Wakeup timer flag", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "Tamper detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "TAMPER2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + } + ] + }, + { + "name": "WUTR", + "displayName": "WUTR", + "description": "Wakeup timer register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "WUT", + "description": "Wakeup auto-reload value bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALIBR", + "displayName": "CALIBR", + "description": "Calibration register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DC", + "description": "Digital calibration", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DCS", + "description": "Digital calibration sign", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMBR", + "displayName": "ALRMBR", + "description": "Alarm B register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSK1", + "description": "Alarm B seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MSK2", + "description": "Alarm B minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MSK3", + "description": "Alarm B hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "MSK4", + "description": "Alarm B date mask", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "ADD1S", + "description": "Add one second", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Time stamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Time stamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Timestamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + }, + { + "name": "CALW16", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALP", + "description": "Increase frequency of RTC by 488.5 ppm", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "Tamper 2 detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMP2TRG", + "description": "Active level for tamper 2", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPFLT", + "description": "Tamper filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPPRCH", + "description": "Tamper precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPPUDIS", + "description": "TAMPER pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "ALRMBSSR", + "displayName": "ALRMBSSR", + "description": "Alarm B sub second register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + }, + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP5R", + "displayName": "BKP5R", + "description": "Backup register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP6R", + "displayName": "BKP6R", + "description": "Backup register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP7R", + "displayName": "BKP7R", + "description": "Backup register", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP8R", + "displayName": "BKP8R", + "description": "Backup register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP9R", + "displayName": "BKP9R", + "description": "Backup register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP10R", + "displayName": "BKP10R", + "description": "Backup register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP11R", + "displayName": "BKP11R", + "description": "Backup register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP12R", + "displayName": "BKP12R", + "description": "Backup register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP13R", + "displayName": "BKP13R", + "description": "Backup register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP14R", + "displayName": "BKP14R", + "description": "Backup register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP15R", + "displayName": "BKP15R", + "description": "Backup register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP16R", + "displayName": "BKP16R", + "description": "Backup register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP17R", + "displayName": "BKP17R", + "description": "Backup register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP18R", + "displayName": "BKP18R", + "description": "Backup register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP19R", + "displayName": "BKP19R", + "description": "Backup register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SAI", + "description": "Serial audio interface", + "groupName": "SAI", + "baseAddress": "0x40015800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SAI1", + "description": "SAI1 global interrupt", + "value": "87" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "BConfiguration register 1", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000040", + "fields": [ + { + "name": "MODE", + "description": "Audio block mode", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MONO", + "description": "Mono mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OutDri", + "description": "Output drive", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SAIBEN", + "description": "Audio block B enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "NODIV", + "description": "No divider", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MCJDIV", + "description": "Master clock divider", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "BConfiguration register 2", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "FFLUS", + "description": "FIFO flush", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TRIS", + "description": "Tristate management on data line", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MUTE", + "description": "Mute", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MUTEVAL", + "description": "Mute value", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MUTECN", + "description": "Mute counter", + "bitOffset": "7", + "bitWidth": "6" + }, + { + "name": "CPL", + "description": "Complement bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "COMP", + "description": "Companding mode", + "bitOffset": "14", + "bitWidth": "2" + } + ] + }, + { + "name": "BFRCR", + "displayName": "BFRCR", + "description": "BFRCR", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000007", + "fields": [ + { + "name": "FRL", + "description": "Frame length", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length", + "bitOffset": "8", + "bitWidth": "7" + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSOFF", + "description": "Frame synchronization offset", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "BSLOTR", + "displayName": "BSLOTR", + "description": "BSlot register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBOFF", + "description": "First bit offset", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SLOTSZ", + "description": "Slot size", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "SLOTEN", + "description": "Slot enable", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "BIM", + "displayName": "BIM", + "description": "BInterrupt mask register2", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LFSDETIE", + "description": "Late frame synchronization detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "BSR", + "displayName": "BSR", + "description": "BStatus register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRUDR", + "description": "Overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "FIFO request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Codec not ready", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FLVL", + "description": "FIFO level threshold", + "bitOffset": "16", + "bitWidth": "3" + } + ] + }, + { + "name": "BCLRFR", + "displayName": "BCLRFR", + "description": "BClear flag register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRUDR", + "description": "Clear overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Clear wrong clock configuration flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Clear codec not ready flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LFSDET", + "description": "Clear late frame synchronization detection flag", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "BDR", + "displayName": "BDR", + "description": "BData register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ACR1", + "displayName": "ACR1", + "description": "AConfiguration register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000040", + "fields": [ + { + "name": "MODE", + "description": "Audio block mode", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MONO", + "description": "Mono mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OutDri", + "description": "Output drive", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SAIAEN", + "description": "Audio block A enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "NODIV", + "description": "No divider", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MCJDIV", + "description": "Master clock divider", + "bitOffset": "20", + "bitWidth": "4" + } + ] + }, + { + "name": "ACR2", + "displayName": "ACR2", + "description": "AConfiguration register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "FFLUS", + "description": "FIFO flush", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TRIS", + "description": "Tristate management on data line", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MUTE", + "description": "Mute", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MUTEVAL", + "description": "Mute value", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MUTECN", + "description": "Mute counter", + "bitOffset": "7", + "bitWidth": "6" + }, + { + "name": "CPL", + "description": "Complement bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "COMP", + "description": "Companding mode", + "bitOffset": "14", + "bitWidth": "2" + } + ] + }, + { + "name": "AFRCR", + "displayName": "AFRCR", + "description": "AFRCR", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000007", + "fields": [ + { + "name": "FRL", + "description": "Frame length", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length", + "bitOffset": "8", + "bitWidth": "7" + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSOFF", + "description": "Frame synchronization offset", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "ASLOTR", + "displayName": "ASLOTR", + "description": "ASlot register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBOFF", + "description": "First bit offset", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "SLOTSZ", + "description": "Slot size", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "SLOTEN", + "description": "Slot enable", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "AIM", + "displayName": "AIM", + "description": "AInterrupt mask register2", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "ASR", + "displayName": "ASR", + "description": "AStatus register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRUDR", + "description": "Overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag. This bit is read only.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "FIFO request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Codec not ready", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FLVL", + "description": "FIFO level threshold", + "bitOffset": "16", + "bitWidth": "3" + } + ] + }, + { + "name": "ACLRFR", + "displayName": "ACLRFR", + "description": "AClear flag register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRUDR", + "description": "Clear overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Clear wrong clock configuration flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Clear codec not ready flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag.", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LFSDET", + "description": "Clear late frame synchronization detection flag", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "ADR", + "displayName": "ADR", + "description": "AData register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Argument register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "Command register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDINDEX", + "description": "Command index", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "WAITRESP", + "description": "Wait for response bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "WAITINT", + "description": "CPSM waits for interrupt request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "CPSM Waits for ends of data transfer (CmdPend internal signal).", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "Command path state machine (CPSM) Enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SD I/O suspend command", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "Enable CMD completion", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "Not Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CE_ATACMD", + "description": "CE-ATA command", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "Command response register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "Response command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESP1", + "displayName": "RESP1", + "description": "Response 1..4 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Response 1..4 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Response 1..4 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Response 1..4 register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Data timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Data length register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "Data control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "Data transfer direction selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "Data transfer mode selection 1: Stream or SDIO multibyte data transfer.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA enable bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "Data block size", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "RWSTART", + "description": "Read wait start", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWSTOP", + "description": "Read wait stop", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "Read wait mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SD I/O enable functions", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Data counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAIL", + "description": "Command response received (CRC check failed)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "Data block sent/received (CRC check failed)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "Command response timeout", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "Data timeout", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "Transmit FIFO underrun error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "Received FIFO overrun error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "Command response received (CRC check passed)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "Command sent (no response required)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "Data end (data counter, SDIDCOUNT, is zero)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "Start bit not detected on all data signals in wide bus mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "Data block sent/received (CRC check passed)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "Command transfer in progress", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "Data transmit in progress", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "Data receive in progress", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "Transmit FIFO half empty: at least 8 words can be written into the FIFO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "Receive FIFO half full: there are at least 8 words in the FIFO", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "Transmit FIFO full", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "Receive FIFO full", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "Transmit FIFO empty", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "Receive FIFO empty", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "Data available in transmit FIFO", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "Data available in receive FIFO", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIO interrupt received", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAEND", + "description": "CE-ATA command completion signal received for CMD61", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILC", + "description": "CCRCFAIL flag clear bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAIL flag clear bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUT flag clear bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUT flag clear bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERR flag clear bit", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERR flag clear bit", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDREND flag clear bit", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENT flag clear bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAEND flag clear bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERR flag clear bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKEND flag clear bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOIT flag clear bit", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDC", + "description": "CEATAEND flag clear bit", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "Mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILIE", + "description": "Command CRC fail interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "Data CRC fail interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "Command timeout interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "Data timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "Tx FIFO underrun error interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "Rx FIFO overrun error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "Command response received interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "Command sent interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "Data end interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "Start bit error interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDIE", + "description": "Data block end interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "Command acting interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "Data transmit acting interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "Data receive acting interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "Tx FIFO half empty interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "Rx FIFO half full interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "Tx FIFO full interrupt enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "Rx FIFO full interrupt enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "Tx FIFO empty interrupt enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "Rx FIFO empty interrupt enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "Data available in Tx FIFO interrupt enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "Data available in Rx FIFO interrupt enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIO mode interrupt received interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDIE", + "description": "CE-ATA command completion signal received interrupt enable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "FIFO counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOCOUNT", + "description": "Remaining number of words to be written to or read from the FIFO.", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Data FIFO register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "Receive and transmit FIFO data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + } + ] + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ], + "qemuGroupName": "SPI" + }, + { + "name": "SPI4", + "derivedFrom": "SPI1", + "baseAddress": "0x40013400", + "interrupts": [ + { + "name": "SPI4", + "description": "SPI 4 global interrupt", + "value": "84" + } + ] + }, + { + "name": "SPI5", + "derivedFrom": "SPI1", + "baseAddress": "0x40015000", + "interrupts": [ + { + "name": "SPI5", + "description": "SPI 5 global interrupt", + "value": "85" + } + ] + }, + { + "name": "SPI6", + "derivedFrom": "SPI1", + "baseAddress": "0x40015400", + "interrupts": [ + { + "name": "SPI6", + "description": "SPI 6 global interrupt", + "value": "86" + } + ] + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MEMRM", + "displayName": "MEMRM", + "description": "Memory remap register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "Memory mapping selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "FB_MODE", + "description": "Flash bank mode selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWP_FMC", + "description": "FMC memory mapping swap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + }, + { + "name": "PMC", + "displayName": "PMC", + "description": "Peripheral mode configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADC1DC2", + "description": "ADC1DC2", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ADC2DC2", + "description": "ADC2DC2", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADC3DC2", + "description": "ADC3DC2", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MII_RMII_SEL", + "description": "Ethernet PHY interface selection", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CMPCR", + "displayName": "CMPCR", + "description": "Compensation cell control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMP_PD", + "description": "Compensation cell power-down", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "READY", + "description": "READY", + "bitOffset": "8", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM10", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM11", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Input 1 remapping capability", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM12", + "derivedFrom": "TIM9", + "baseAddress": "0x40001800", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + } + ] + }, + { + "name": "TIM13", + "derivedFrom": "TIM10", + "baseAddress": "0x40001C00", + "interrupts": [ + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + } + ] + }, + { + "name": "TIM14", + "derivedFrom": "TIM10", + "baseAddress": "0x40002000", + "interrupts": [ + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ITR1_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM3", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM3", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "IT4_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "6", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM6", + "description": "Basic timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40010400", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + }, + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + }, + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + }, + { + "name": "TIM8_CC", + "description": "TIM8 Capture Compare interrupt", + "value": "46" + } + ] + }, + { + "name": "TIM9", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "3" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "UART4", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "UART5", + "derivedFrom": "UART4", + "baseAddress": "0x40005000", + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "UART" + }, + { + "name": "UART7", + "derivedFrom": "USART6", + "baseAddress": "0x40007800", + "interrupts": [ + { + "name": "UART7", + "description": "UART 7 global interrupt", + "value": "82" + } + ] + }, + { + "name": "UART8", + "derivedFrom": "USART6", + "baseAddress": "0x40007C00", + "interrupts": [ + { + "name": "UART8", + "description": "UART 8 global interrupt", + "value": "83" + } + ] + }, + { + "name": "USART1", + "derivedFrom": "USART6", + "baseAddress": "0x40011000", + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART2", + "derivedFrom": "USART6", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART3", + "derivedFrom": "USART6", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "USART6", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40011400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART6", + "description": "USART6 global interrupt", + "value": "71" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + } + ] + } + ], + "qemuAlignment": "word-halfWord", + "qemuGroupName": "USART" + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB0", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "WDGTB1", + "description": "Timer base", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + } + ], + "cpu": { + "name": "CM4", + "revision": "r0p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "true", + "nvicPrioBits": "4", + "deviceNumInterrupts": "91", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "qemuAlignment": "any" + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/README.md b/gnu-mcu-eclipse/devices/support/README.md new file mode 100644 index 0000000000..af21f03003 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/README.md @@ -0,0 +1,242 @@ +# Original content & patches + +The `*-svd.json` files were generated from the original CMSIS files: + +The `*-patch.json` are patches to add content required by QEMU. + + +## CPUID + +The `cpu.revision` value (a string like r0p0) is the value that should be read from SCB.CPUID, address 0xE000ED00. + +For the STM devices, this value is usually given in the _Programming manual_, the _Core peripherals_ chapter. + +## Custom definitions + +### CPU core capabilities + +These definitions are from the [CMSIS SVD](http://www.keil.com/pack/doc/CMSIS/SVD/html/elem_cpu.html) `` element, with some extensions. + +- `name` (CM0, CM0PLUS, CM0+, CM1, CM3, CM4, CM7) +- `revision` (r0p0, values 0-15) +- `endian` (**little**/big/selectable) +- `mpuPresent` (true/**false**) +- `fpuPresent` (true/**false**) +- `fpuDP` (true/false, but only when FPU present) +- `nvicPrioBits` - the number of significant bits on he left of the NVIC byte; 4 for most STM, 2 for F0 +- `deviceNumInterrupts` - does not include the 16 system exceptions +- `vendorSystickConfig` (true/**false**) + +QEMU extensions + +- `qemuItmPresent` (true/**false**) +- `qemuEtmPresent` (true/**false**) + +### qemuAlignment + +The alignment extension can be defined for the device, peripherals, clusters or registers nodes. If the peripheral does not define it but is derived, the value of the original peripheral is checked. + +Possible values are: + +- `any` +- `word-halfWord` +- `word` + +### qemuGroupName + +This property is added to peripherals that have multiple instances, like GPIOA, GPIOB, USART1, USART2, etc. + +It is used to correctly generate the support code. + +## xsvd + +The external tool used to process the SVD files is [`xsvd`](https://www.npmjs.com/package/xsvd). + +## Devices + +The commands used to generate the specifc xsvd files are: + +### STM32F0x1 + +``` +xsvd convert \ +--file "/Users/ilg/Library/xPacks/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x1.svd" \ +--output "STM32F0x1-xsvd.json" \ +--verbose + +xsvd patch \ +--file "STM32F0x1-xsvd.json" \ +--patch "STM32F0x1-patch.json" \ +--output "../STM32F0x1-qemu.json" \ +--remove "NVIC" \ +--verbose + +xsvd code \ +--file "../STM32F0x1-qemu.json" \ +--verbose + +``` + +### STM32F0x2 + +``` +xsvd convert \ +--file "/Users/ilg/Library/xPacks/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x2.svd" \ +--output "STM32F0x2-xsvd.json" \ +--verbose + +xsvd patch \ +--file "STM32F0x2-xsvd.json" \ +--patch "STM32F0x2-patch.json" \ +--output "../STM32F0x2-qemu.json" \ +--remove "NVIC" \ +--verbose + +xsvd code \ +--file "../STM32F0x2-qemu.json" \ +--verbose + +``` + +### STM32F103xx + +``` +xsvd convert \ +--file "/Users/ilg/Library/xPacks/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F103xx.svd" \ +--output "STM32F103xx-xsvd.json" \ +--verbose + +xsvd patch \ +--file "STM32F103xx-xsvd.json" \ +--patch "STM32F103xx-patch.json" \ +--output "../STM32F103xx-qemu.json" \ +--remove "NVIC" \ +--verbose + +xsvd code \ +--file "../STM32F103xx-qemu.json" \ +--verbose + +``` + +### STM32F107xx + +``` +xsvd convert \ +--file "/Users/ilg/Library/xPacks/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F107xx.svd" \ +--output "STM32F107xx-xsvd.json" \ +--verbose + +xsvd patch \ +--file "STM32F107xx-xsvd.json" \ +--patch "STM32F107xx-patch.json" \ +--output "../STM32F107xx-qemu.json" \ +--remove "NVIC" \ +--verbose + +xsvd code \ +--file "../STM32F107xx-qemu.json" \ +--verbose + +``` + +### STM32F40x + +``` +xsvd convert \ +--file "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F40x.svd" \ +--output "STM32F40x-xsvd.json" \ +--verbose + +xsvd patch \ +--file "STM32F40x-xsvd.json" \ +--patch "STM32F40x-patch.json" \ +--output "../STM32F40x-qemu.json" \ +--remove "NVIC" \ +--group-bitfield "RCC/PLLCFGR/PLLQ" \ +--group-bitfield "RCC/PLLCFGR/PLLP" \ +--group-bitfield "RCC/PLLCFGR/PLLN" \ +--group-bitfield "RCC/PLLCFGR/PLLM" \ +--group-bitfield "RCC/CFGR/SWS" \ +--group-bitfield "RCC/CFGR/SW" \ +--group-bitfield "RCC/BDCR/RTCSEL" \ +--verbose + +xsvd code \ +--file "../STM32F40x-qemu.json" \ +--verbose + +``` + +### STM32F411xx + +``` +xsvd convert \ +--file "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F411xx.svd" \ +--output "STM32F411xx-xsvd.json" \ +--verbose + +xsvd patch \ +--file "STM32F411xx-xsvd.json" \ +--patch "STM32F411xx-patch.json" \ +--output "../STM32F411xx-qemu.json" \ +--remove "NVIC" \ +--group-bitfield "RCC/PLLCFGR/PLLQ" \ +--group-bitfield "RCC/PLLCFGR/PLLP" \ +--group-bitfield "RCC/PLLCFGR/PLLN" \ +--group-bitfield "RCC/PLLCFGR/PLLM" \ +--group-bitfield "RCC/CFGR/SWS" \ +--group-bitfield "RCC/CFGR/SW" \ +--group-bitfield "RCC/BDCR/RTCSEL" \ +--verbose + +xsvd code \ +--file "../STM32F411xx-qemu.json" \ +--verbose + +``` + +### STM32F429x + +``` +xsvd \ +svd-convert \ +--file "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F429x.svd" \ +--output "STM32F429x-xsvd.json" + +xsvd \ +svd-patch \ +--file "STM32F429x-xsvd.json" \ +--patch "STM32F429x-patch.json" \ +--output "../STM32F429x-qemu.json" \ +--group-bitfield "RCC/PLLCFGR/PLLQ" \ +--group-bitfield "RCC/PLLCFGR/PLLP" \ +--group-bitfield "RCC/PLLCFGR/PLLN" \ +--group-bitfield "RCC/PLLCFGR/PLLM" \ +--group-bitfield "RCC/CFGR/SWS" \ +--group-bitfield "RCC/CFGR/SW" \ +--group-bitfield "RCC/BDCR/RTCSEL" + +xsvd \ +svd-code \ +--file "../STM32F429x-qemu.json" + +``` + +# Missing from CMSIS SVD + +- alignment for registers & peripherals: choice of word/word-halfword/any (see `qemuAlignment`) + +- bitband regions (array of {name, address}) + + +# Development environment details + +These details are relevant in my development environments, and are here as a convenience, to easily copy/paste them to the terminal. + +The location of the folder: + +``` +cd /Users/ilg/Work/qemu/gnuarmeclipse-qemu.git/gnuarmeclipse/devices/support +cd /Users/ilg/My\ Files/MacBookPro\ Projects/GNU\ ARM\ Eclipse/gnuarmeclipse-qemu.git/gnuarmeclipse/devices/support +``` diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1-patch.json b/gnu-mcu-eclipse/devices/support/STM32F0x1-patch.json new file mode 100644 index 0000000000..822bc6d017 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1-patch.json @@ -0,0 +1,135 @@ +{ + "comment": "Patch for QEMU use.", + "device": { + "name": "STM32F0x1", + "cpu": { + "name": "CM0", + "revision": "r0p0", + "endian": "little", + "mpuPresent": "false", + "fpuPresent": "false", + "nvicPrioBits": "2", + "deviceNumInterrupts": "31", + "vendorSystickConfig": "false", + "qemuItmPresent": false + }, + "access": "read-write", + "qemuAlignment": "any", + "peripherals": [ + { + "name": "EXTI", + "qemuAlignment": "word" + }, + { + "name": "FLASH", + "qemuAlignment": "word" + }, + { + "name": "PWR", + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "qemuAlignment": "any" + }, + { + "name": "SYSCFG", + "qemuAlignment": "any" + }, + { + "name": "GPIOA", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "USART1", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART2", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART3", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART4", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART5", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART6", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART7", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART8", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "SPI1", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "qemuGroupName": "SPI" + }, + { + "name": "I2C1", + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "qemuGroupName": "I2C" + }, + { + "name": "DMA1", + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "qemuGroupName": "DMA" + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1-xsvd.json b/gnu-mcu-eclipse/devices/support/STM32F0x1-xsvd.json new file mode 100644 index 0000000000..432d0cd4ca --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1-xsvd.json @@ -0,0 +1,30688 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F0x1.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.2", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x1.svd", + "--output", + "STM32F0x1-xsvd.json" + ], + "date": "2016-12-14T22:50:48.956Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F0x1", + "version": "1.0", + "description": "STM32F0x1", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "CRC", + "description": "Cyclic redundancy check calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data register bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "General-purpose 8-bit data register bits", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "POLYSIZE", + "description": "Polynomial size", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "REV_IN", + "description": "Reverse input data", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "REV_OUT", + "description": "Reverse output data", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "INIT", + "displayName": "INIT", + "description": "Initial CRC value", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "INIT", + "description": "Programmable initial CRC value", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "GPIOF", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48001400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bit 0", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000C00" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000800" + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000400" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOF", + "baseAddress": "0x48001000" + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x28000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1_global_interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "NSSP", + "description": "NSS pulse management", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "FRXTH", + "description": "FIFO reception threshold", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LDMA_RX", + "description": "Last DMA transfer for reception", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LDMA_TX", + "description": "Last DMA transfer for transmission", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FRLVL", + "description": "FIFO reception level", + "bitOffset": "9", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FTLVL", + "description": "FIFO transmission level", + "bitOffset": "11", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000010", + "fields": [ + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "26" + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt and DAC underrun interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "VREFINTRDY", + "description": "VREFINT reference voltage ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP1", + "description": "Enable WKUP pin 1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP2", + "description": "Enable WKUP pin 2", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP3", + "description": "Enable WKUP pin 3", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP4", + "description": "Enable WKUP pin 4", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP5", + "description": "Enable WKUP pin 5", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP6", + "description": "Enable WKUP pin 6", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP7", + "description": "Enable WKUP pin 7", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP8", + "description": "Enable WKUP pin 8", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "I2C1", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1", + "description": "I2C1 global interrupt", + "value": "23" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXIE", + "description": "TX Interrupt enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXIE", + "description": "RX Interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADDRIE", + "description": "Address match interrupt enable (slave only)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NACKIE", + "description": "Not acknowledge received interrupt enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "STOPIE", + "description": "STOP detection Interrupt enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TCIE", + "description": "Transfer Complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRIE", + "description": "Error interrupts enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DNF", + "description": "Digital noise filter", + "bitOffset": "8", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "ANFOFF", + "description": "Analog noise filter OFF", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "13", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXDMAEN", + "description": "DMA transmission requests enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXDMAEN", + "description": "DMA reception requests enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SBC", + "description": "Slave byte control", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUPEN", + "description": "Wakeup from STOP enable", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GCEN", + "description": "General call enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBHEN", + "description": "SMBus Host address enable", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBDEN", + "description": "SMBus Device Default address enable", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALERTEN", + "description": "SMBUS alert enable", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECEN", + "description": "PEC enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PECBYTE", + "description": "Packet error checking byte", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "AUTOEND", + "description": "Automatic end mode (master mode)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "RELOAD", + "description": "NBYTES reload mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "NBYTES", + "description": "Number of bytes", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NACK", + "description": "NACK generation (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation (master mode)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HEAD10R", + "description": "10-bit address header only read direction (master receiver mode)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "10-bit addressing mode (master mode)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RD_WRN", + "description": "Transfer direction (master mode)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SADD8", + "description": "Slave address bit 9:8 (master mode)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "SADD1", + "description": "Slave address bit 7:1 (master mode)", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "SADD0", + "description": "Slave address bit 0 (master mode)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA1_0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OA1_1", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA1_8", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OA1MODE", + "description": "Own Address 1 10-bit mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OA1EN", + "description": "Own Address 1 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA2MSK", + "description": "Own Address 2 masks", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "OA2EN", + "description": "Own Address 2 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TIMINGR", + "displayName": "TIMINGR", + "description": "Timing register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SCLL", + "description": "SCL low period (master mode)", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "SCLH", + "description": "SCL high period (master mode)", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "SDADEL", + "description": "Data hold time", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "SCLDEL", + "description": "Data setup time", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "PRESC", + "description": "Timing prescaler", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "TIMEOUTR", + "displayName": "TIMEOUTR", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIMEOUTA", + "description": "Bus timeout A", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "TIDLE", + "description": "Idle clock timeout detection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIMOUTEN", + "description": "Clock timeout enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIMEOUTB", + "description": "Bus timeout B", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "TEXTEN", + "description": "Extended clock timeout enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000001", + "fields": [ + { + "name": "ADDCODE", + "description": "Address match code (Slave mode)", + "bitOffset": "17", + "bitWidth": "7", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Transfer direction (Slave mode)", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIMEOUT", + "description": "Timeout or t_low detection flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun/Underrun (slave mode)", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ARLO", + "description": "Arbitration lost", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCR", + "description": "Transfer Complete Reload", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transfer Complete (master mode)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NACKF", + "description": "Not acknowledge received flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address matched (slave mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Receive data register not empty (receivers)", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXIS", + "description": "Transmit interrupt status (transmitters)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty (transmitters)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALERTCF", + "description": "Alert flag clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TIMOUTCF", + "description": "Timeout detection flag clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PECCF", + "description": "PEC Error flag clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OVRCF", + "description": "Overrun/Underrun flag clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ARLOCF", + "description": "Arbitration lost flag clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BERRCF", + "description": "Bus error flag clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STOPCF", + "description": "Stop detection flag clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACKCF", + "description": "Not Acknowledge flag clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ADDRCF", + "description": "Address Matched flag clear", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "PECR", + "displayName": "PECR", + "description": "PEC register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PEC", + "description": "Packet error checking register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDATA", + "description": "8-bit receive data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXDATA", + "description": "8-bit transmit data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2", + "description": "I2C2 global interrupt", + "value": "24" + } + ] + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WVU", + "description": "Watchdog counter window value update", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "WINR", + "displayName": "WINR", + "description": "Window register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "WIN", + "description": "Watchdog counter window value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "T", + "description": "7-bit counter", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WDGTB", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_UP_TRG_COM", + "description": "TIM1 break, update, trigger and commutation interrupt", + "value": "13" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "14" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM2", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "15" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAR", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "16" + } + ] + }, + { + "name": "TIM14", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40002000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM14", + "description": "TIM14 global interrupt", + "value": "19" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Timer input 1 remap", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM6", + "description": "Basic-timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "18" + } + ] + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD and VDDIO2 supply comparator interrupt", + "value": "1" + }, + { + "name": "EXTI0_1", + "description": "EXTI Line[1:0] interrupts", + "value": "5" + }, + { + "name": "EXTI2_3", + "description": "EXTI Line[3:2] interrupts", + "value": "6" + }, + { + "name": "EXTI4_15", + "description": "EXTI Line15 and EXTI4 interrupts", + "value": "7" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0F940000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Interrupt Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Interrupt Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Interrupt Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Interrupt Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Interrupt Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Event Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Event Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Event Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Event Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Event Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x33D", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ISER", + "displayName": "ISER", + "description": "Interrupt Set Enable Register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER", + "displayName": "ICER", + "description": "Interrupt Clear Enable Register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR", + "displayName": "ISPR", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR", + "displayName": "ICPR", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register 0", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_00", + "description": "PRI_00", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_01", + "description": "PRI_01", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_02", + "description": "PRI_02", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_03", + "description": "PRI_03", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register 1", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_40", + "description": "PRI_40", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_41", + "description": "PRI_41", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_42", + "description": "PRI_42", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_43", + "description": "PRI_43", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register 2", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_80", + "description": "PRI_80", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_81", + "description": "PRI_81", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_82", + "description": "PRI_82", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_83", + "description": "PRI_83", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register 3", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_120", + "description": "PRI_120", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_121", + "description": "PRI_121", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_122", + "description": "PRI_122", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_123", + "description": "PRI_123", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register 4", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_160", + "description": "PRI_160", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_161", + "description": "PRI_161", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_162", + "description": "PRI_162", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_163", + "description": "PRI_163", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register 5", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_200", + "description": "PRI_200", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_201", + "description": "PRI_201", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_202", + "description": "PRI_202", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_203", + "description": "PRI_203", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register 6", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_240", + "description": "PRI_240", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_241", + "description": "PRI_241", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_242", + "description": "PRI_242", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_243", + "description": "PRI_243", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register 7", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_280", + "description": "PRI_280", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_281", + "description": "PRI_281", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_282", + "description": "PRI_282", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_283", + "description": "PRI_283", + "bitOffset": "30", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_CH1", + "description": "DMA1 channel 1 interrupt", + "value": "9" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DMA2", + "derivedFrom": "DMA1", + "baseAddress": "0x40020400", + "interrupts": [ + { + "name": "DMA1_CH2_3_DMA2_CH1_2", + "description": "DMA1 channel 2 and 3 and DMA2 channel 1 and 2 interrupt", + "value": "10" + }, + { + "name": "DMA1_CH4_5_6_7_DMA2_CH3_4_5", + "description": "DMA1 channel 4, 5, 6 and 7 and DMA2 channel 3, 4 and 5 interrupts", + "value": "11" + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL input clock source", + "bitOffset": "15", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCOPRE", + "description": "Microcontroller Clock Output Prescaler", + "bitOffset": "28", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PLLNODIV", + "description": "PLL clock not divided for MCO", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14RDYF", + "description": "HSI14 ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48RDYF", + "description": "HSI48 ready interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDYE", + "description": "HSI14 ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDYIE", + "description": "HSI48 ready interrupt enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI14RDYC", + "description": "HSI 14 MHz Ready Interrupt Clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI48RDYC", + "description": "HSI48 Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGRST", + "description": "SYSCFG and COMP reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15RST", + "description": "TIM15 timer reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16RST", + "description": "TIM16 timer reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17RST", + "description": "TIM17 timer reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCURST", + "description": "Debug MCU reset", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 timer reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "Timer 14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4RST", + "description": "USART4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART5RST", + "description": "USART5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANRST", + "description": "CAN interface reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSRST", + "description": "Clock Recovery System interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECRST", + "description": "HDMI CEC reset", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFEN", + "description": "I/O port F clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCEN", + "description": "Touch sensing controller clock enable", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGEN", + "description": "SYSCFG clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCEN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15EN", + "description": "TIM15 timer clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16EN", + "description": "TIM16 timer clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17EN", + "description": "TIM17 timer clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCUEN", + "description": "MCU debug module clock enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 timer clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "Timer 14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4EN", + "description": "USART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART5EN", + "description": "USART5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANEN", + "description": "CAN interface clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSEN", + "description": "Clock Recovery System interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECEN", + "description": "HDMI CEC interface clock enable", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSEDRV", + "description": "LSE oscillator drive capability", + "bitOffset": "3", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OBLRSTF", + "description": "Option byte loader reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "AHBRSTR", + "displayName": "AHBRSTR", + "description": "AHB peripheral reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IOPARST", + "description": "I/O port A reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "I/O port B reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "I/O port C reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "I/O port D reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFRST", + "description": "I/O port F reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCRST", + "description": "Touch sensing controller reset", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Clock configuration register 2", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PREDIV", + "description": "PREDIV division factor", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR3", + "displayName": "CFGR3", + "description": "Clock configuration register 3", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "USART1SW", + "description": "USART1 clock source selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "I2C1SW", + "description": "I2C1 clock source selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CECSW", + "description": "HDMI CEC clock source selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "USBSW", + "description": "USB clock source selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ADCSW", + "description": "ADC clock source selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART2SW", + "description": "USART2 clock source selection", + "bitOffset": "16", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Clock control register 2", + "addressOffset": "0x34", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "HSI14ON", + "description": "HSI14 clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDY", + "description": "HR14 clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14DIS", + "description": "HSI14 clock request from ADC disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14TRIM", + "description": "HSI14 clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSI14CAL", + "description": "HSI14 clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSI48ON", + "description": "HSI48 clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDY", + "description": "HSI48 clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48CAL", + "description": "HSI48 factory clock calibration", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ] + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1D", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "Memory mapping selection bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ADC_DMA_RMP", + "description": "ADC DMA remapping bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART1_TX_DMA_RMP", + "description": "USART1_TX DMA remapping bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "USART1_RX_DMA_RMP", + "description": "USART1_RX DMA request remapping bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM16_DMA_RMP", + "description": "TIM16 DMA request remapping bit", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM17_DMA_RMP", + "description": "TIM17 DMA request remapping bit", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C_PB6_FM", + "description": "Fast Mode Plus (FM plus) driving capability activation bits.", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2C_PB7_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2C_PB8_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "I2C_PB9_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1_FM_plus", + "description": "FM+ driving capability activation for I2C1", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C2_FM_plus", + "description": "FM+ driving capability activation for I2C2", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SPI2_DMA_RMP", + "description": "SPI2 DMA request remapping bit", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "USART2_DMA_RMP", + "description": "USART2 DMA request remapping bit", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "USART3_DMA_RMP", + "description": "USART3 DMA request remapping bit", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "I2C1_DMA_RMP", + "description": "I2C1 DMA request remapping bit", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "TIM1_DMA_RMP", + "description": "TIM1 DMA request remapping bit", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "TIM2_DMA_RMP", + "description": "TIM2 DMA request remapping bit", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "TIM3_DMA_RMP", + "description": "TIM3 DMA request remapping bit", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI3", + "description": "EXTI 3 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI 2 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI 1 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI0", + "description": "EXTI 0 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI7", + "description": "EXTI 7 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI 6 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI 5 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI4", + "description": "EXTI 4 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI11", + "description": "EXTI 11 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI 10 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI 9 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI8", + "description": "EXTI 8 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI15", + "description": "EXTI 15 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI 14 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI 13 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI12", + "description": "EXTI 12 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SRAM_PEF", + "description": "SRAM parity flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PVD_LOCK", + "description": "PVD lock enable bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRAM_PARITY_LOCK", + "description": "SRAM parity lock bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LOCUP_LOCK", + "description": "Cortex-M0 LOCKUP bit enable bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "ADC", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OVR", + "description": "ADC overrun", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "EOS", + "description": "End of sequence flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "End of conversion flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOSMP", + "description": "End of sampling flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADRDY", + "description": "ADC ready", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "EOSIE", + "description": "End of conversion sequence interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "End of conversion interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOSMPIE", + "description": "End of sampling flag interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADRDYIE", + "description": "ADC ready interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADCAL", + "description": "ADC calibration", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "ADSTP", + "description": "ADC stop conversion command", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ADSTART", + "description": "ADC start conversion command", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ADDIS", + "description": "ADC disable command", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADEN", + "description": "ADC enable command", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel selection", + "bitOffset": "26", + "bitWidth": "5" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel or on all channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "AUTOFF", + "description": "Auto-off mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AUTDLY", + "description": "Auto-delayed conversion mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Single / continuous conversion mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVRMOD", + "description": "Overrun management mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "EXTEN", + "description": "External trigger enable and polarity selection", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "EXTSEL", + "description": "External trigger selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Data resolution", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "SCANDIR", + "description": "Scan sequence direction", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMACFG", + "description": "Direct memery access configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "Direct memory access enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00008000", + "fields": [ + { + "name": "JITOFF_D4", + "description": "JITOFF_D4", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "JITOFF_D2", + "description": "JITOFF_D2", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR", + "displayName": "SMPR", + "description": "Sampling time register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPR", + "description": "Sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "TR", + "displayName": "TR", + "description": "Watchdog threshold register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "CHSELR", + "displayName": "CHSELR", + "description": "Channel selection register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL18", + "description": "Channel-x selection", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CHSEL17", + "description": "Channel-x selection", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHSEL16", + "description": "Channel-x selection", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CHSEL15", + "description": "Channel-x selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CHSEL14", + "description": "Channel-x selection", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CHSEL13", + "description": "Channel-x selection", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHSEL12", + "description": "Channel-x selection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CHSEL11", + "description": "Channel-x selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHSEL10", + "description": "Channel-x selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CHSEL9", + "description": "Channel-x selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHSEL8", + "description": "Channel-x selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CHSEL7", + "description": "Channel-x selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CHSEL6", + "description": "Channel-x selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CHSEL5", + "description": "Channel-x selection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHSEL4", + "description": "Channel-x selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CHSEL3", + "description": "Channel-x selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHSEL2", + "description": "Channel-x selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CHSEL1", + "description": "Channel-x selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHSEL0", + "description": "Channel-x selection", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Converted data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Common configuration register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VBATEN", + "description": "VBAT enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TSEN", + "description": "Temperature sensor enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "VREFEN", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UE", + "description": "USART enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UESM", + "description": "USART enable in Stop mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Receiver wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MME", + "description": "Mute mode enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CMIE", + "description": "Character match interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DEDT", + "description": "Driver Enable deassertion time", + "bitOffset": "16", + "bitWidth": "5" + }, + { + "name": "DEAT", + "description": "Driver Enable assertion time", + "bitOffset": "21", + "bitWidth": "5" + }, + { + "name": "RTOIE", + "description": "Receiver timeout interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "EOBIE", + "description": "End of Block interrupt enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "M1", + "description": "Word length", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD4", + "description": "Address of the USART node", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "ADD0", + "description": "Address of the USART node", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "RTOEN", + "description": "Receiver timeout enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ABRMOD", + "description": "Auto baud rate mode", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ABREN", + "description": "Auto baud rate enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MSBFIRST", + "description": "Most significant bit first", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DATAINV", + "description": "Binary data inversion", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TXINV", + "description": "TX pin active level inversion", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "RXINV", + "description": "RX pin active level inversion", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWAP", + "description": "Swap TX/RX pins", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "LIN break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADDM7", + "description": "7-bit Address Detection/4-bit Address Detection", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "WUFIE", + "description": "Wakeup from Stop mode interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WUS", + "description": "Wakeup from Stop mode interrupt flag selection", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "SCARCNT", + "description": "Smartcard auto-retry count", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "DEP", + "description": "Driver enable polarity selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DEM", + "description": "Driver enable mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DDRE", + "description": "DMA Disable on Reception Error", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVRDIS", + "description": "Overrun Disable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RTOR", + "displayName": "RTOR", + "description": "Receiver timeout register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BLEN", + "description": "Block Length", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "RTO", + "description": "Receiver timeout value", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "RQR", + "displayName": "RQR", + "description": "Request register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TXFRQ", + "description": "Transmit data flush request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXFRQ", + "description": "Receive data flush request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMRQ", + "description": "Mute mode request", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SBKRQ", + "description": "Send break request", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ABRRQ", + "description": "Auto baud rate request", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt & status register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00C0", + "fields": [ + { + "name": "REACK", + "description": "Receive enable acknowledge flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEACK", + "description": "Transmit enable acknowledge flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "WUF", + "description": "Wakeup from Stop mode flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup from Mute mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SBKF", + "description": "Send break flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CMF", + "description": "Character match flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Busy flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ABRF", + "description": "Auto baud rate flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ABRE", + "description": "Auto baud rate error", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "EOBF", + "description": "End of block flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RTOF", + "description": "Receiver timeout", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSIF", + "description": "CTS interrupt flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBDF", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLE", + "description": "Idle line detected", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "WUCF", + "description": "Wakeup from Stop mode clear flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CMCF", + "description": "Character match clear flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EOBCF", + "description": "End of timeout clear flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RTOCF", + "description": "Receiver timeout clear flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTSCF", + "description": "CTS clear flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBDCF", + "description": "LIN break detection clear flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCCF", + "description": "Transmission complete clear flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDLECF", + "description": "Idle line detected clear flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ORECF", + "description": "Overrun error clear flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NCF", + "description": "Noise detected clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FECF", + "description": "Framing error clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PECF", + "description": "Parity error clear flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "RDR", + "displayName": "RDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RDR", + "description": "Receive data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TDR", + "displayName": "TDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDR", + "description": "Transmit data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + } + ] + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "28" + } + ] + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800" + }, + { + "name": "USART4", + "derivedFrom": "USART1", + "baseAddress": "0x40004C00" + }, + { + "name": "USART6", + "derivedFrom": "USART1", + "baseAddress": "0x40011400" + }, + { + "name": "USART7", + "derivedFrom": "USART1", + "baseAddress": "0x40011800", + "interrupts": [ + { + "name": "USART3_4_5_6_7_8", + "description": "USART3, USART4, USART5, USART6, USART7, USART8 global interrupt", + "value": "29" + } + ] + }, + { + "name": "USART8", + "derivedFrom": "USART1", + "baseAddress": "0x40011C00" + }, + { + "name": "USART5", + "derivedFrom": "USART1", + "baseAddress": "0x40005000" + }, + { + "name": "COMP", + "description": "Comparator", + "groupName": "COMP", + "baseAddress": "0x4001001C", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x5", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "Control and status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COMP1EN", + "description": "Comparator 1 enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1_INP_DAC", + "description": "COMP1_INP_DAC", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1MODE", + "description": "Comparator 1 mode", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1INSEL", + "description": "Comparator 1 inverting input selection", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1OUTSEL", + "description": "Comparator 1 output selection", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1POL", + "description": "Comparator 1 output polarity", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1HYST", + "description": "Comparator 1 hysteresis", + "bitOffset": "12", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1OUT", + "description": "Comparator 1 output", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP1LOCK", + "description": "Comparator 1 lock", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2EN", + "description": "Comparator 2 enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2MODE", + "description": "Comparator 2 mode", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2INSEL", + "description": "Comparator 2 inverting input selection", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "WNDWEN", + "description": "Window mode enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2OUTSEL", + "description": "Comparator 2 output selection", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP2POL", + "description": "Comparator 2 output polarity", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2HYST", + "description": "Comparator 2 hysteresis", + "bitOffset": "28", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2OUT", + "description": "Comparator 2 output", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP2LOCK", + "description": "Comparator 2 lock", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC interrupts", + "value": "2" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REFCKON", + "description": "RTC_REFIN reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BYPSHAD", + "description": "Bypass the shadow registers", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSE", + "description": "Timestamp enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COSEL", + "description": "Calibration output selection", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "RTC_TAMP1 detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "RTC_TAMP2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + }, + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format.", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format.", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADD1S", + "description": "Reserved", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Timestamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Timestamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Time-stamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALP", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALW16", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PC15MODE", + "description": "PC15 mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PC15VALUE", + "description": "PC15 value", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PC14MODE", + "description": "PC14 mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PC14VALUE", + "description": "PC14 value", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PC13MODE", + "description": "PC13 mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PC13VALUE", + "description": "RTC_ALARM output type/PC13 value", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TAMP_PUDIS", + "description": "RTC_TAMPx pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMP_PRCH", + "description": "RTC_TAMPx precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPFLT", + "description": "RTC_TAMPx filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMP2_TRG", + "description": "Active level for RTC_TAMP2 input", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "RTC_TAMP2 input detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for RTC_TAMP1 input", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMP1E", + "description": "RTC_TAMP1 input detection enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "TIM15", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM15", + "description": "TIM15 global interrupt", + "value": "20" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM16", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM16", + "description": "TIM16 global interrupt", + "value": "21" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM17", + "derivedFrom": "TIM16", + "baseAddress": "0x40014800", + "interrupts": [ + { + "name": "TIM17", + "description": "TIM17 global interrupt", + "value": "22" + } + ] + }, + { + "name": "TSC", + "description": "Touch sensing controller", + "groupName": "TSC", + "baseAddress": "0x40024000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TSC", + "description": "Touch sensing interrupt", + "value": "8" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTPH", + "description": "Charge transfer pulse high", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "CTPL", + "description": "Charge transfer pulse low", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SSD", + "description": "Spread spectrum deviation", + "bitOffset": "17", + "bitWidth": "7" + }, + { + "name": "SSE", + "description": "Spread spectrum enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SSPSC", + "description": "Spread spectrum prescaler", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PGPSC", + "description": "Pulse generator prescaler", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MCV", + "description": "Max count value", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "IODEF", + "description": "I/O Default mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SYNCPOL", + "description": "Synchronization pin polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "AM", + "description": "Acquisition mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start a new acquisition", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSCE", + "description": "Touch sensing controller enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCEIE", + "description": "Max count error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOAIE", + "description": "End of acquisition interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCEIC", + "description": "Max count error interrupt clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOAIC", + "description": "End of acquisition interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCEF", + "description": "Max count error flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOAF", + "description": "End of acquisition flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOHCR", + "displayName": "IOHCR", + "description": "I/O hysteresis control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOASCR", + "displayName": "IOASCR", + "description": "I/O analog switch control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 analog switch enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 analog switch enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 analog switch enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 analog switch enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 analog switch enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 analog switch enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 analog switch enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 analog switch enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 analog switch enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 analog switch enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 analog switch enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 analog switch enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 analog switch enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 analog switch enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 analog switch enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 analog switch enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 analog switch enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 analog switch enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 analog switch enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 analog switch enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 analog switch enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 analog switch enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 analog switch enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 analog switch enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOSCR", + "displayName": "IOSCR", + "description": "I/O sampling control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 sampling mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 sampling mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 sampling mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 sampling mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 sampling mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 sampling mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 sampling mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 sampling mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 sampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 sampling mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 sampling mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 sampling mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 sampling mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 sampling mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 sampling mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 sampling mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 sampling mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 sampling mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 sampling mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 sampling mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 sampling mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 sampling mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 sampling mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 sampling mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOCCR", + "displayName": "IOCCR", + "description": "I/O channel control register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 channel mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 channel mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 channel mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 channel mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 channel mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 channel mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 channel mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 channel mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 channel mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 channel mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 channel mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 channel mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 channel mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 channel mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 channel mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 channel mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 channel mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 channel mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 channel mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 channel mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 channel mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 channel mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 channel mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 channel mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOGCSR", + "displayName": "IOGCSR", + "description": "I/O group control status register", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G8S", + "description": "Analog I/O group x status", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G7S", + "description": "Analog I/O group x status", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G6S", + "description": "Analog I/O group x status", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G5S", + "description": "Analog I/O group x status", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G4S", + "description": "Analog I/O group x status", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G3S", + "description": "Analog I/O group x status", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G2S", + "description": "Analog I/O group x status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G1S", + "description": "Analog I/O group x status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G8E", + "description": "Analog I/O group x enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G7E", + "description": "Analog I/O group x enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G6E", + "description": "Analog I/O group x enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G5E", + "description": "Analog I/O group x enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G4E", + "description": "Analog I/O group x enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G3E", + "description": "Analog I/O group x enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G2E", + "description": "Analog I/O group x enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G1E", + "description": "Analog I/O group x enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "IOG1CR", + "displayName": "IOG1CR", + "description": "I/O group x counter register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG2CR", + "displayName": "IOG2CR", + "description": "I/O group x counter register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG3CR", + "displayName": "IOG3CR", + "description": "I/O group x counter register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG4CR", + "displayName": "IOG4CR", + "description": "I/O group x counter register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG5CR", + "displayName": "IOG5CR", + "description": "I/O group x counter register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG6CR", + "displayName": "IOG6CR", + "description": "I/O group x counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + } + ] + }, + { + "name": "CEC", + "description": "HDMI-CEC controller", + "groupName": "CEC", + "baseAddress": "0x40007800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CEC_CAN", + "description": "CEC and CAN global interrupt", + "value": "30" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXEOM", + "description": "Tx End Of Message", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TXSOM", + "description": "Tx start of message", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CECEN", + "description": "CEC Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LBPEGEN", + "description": "Generate Error-Bit on Long Bit Period Error", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BREGEN", + "description": "Generate error-bit on bit rising error", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BRESTP", + "description": "Rx-stop on bit rising error", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXTOL", + "description": "Rx-Tolerance", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SFT", + "description": "Signal Free Time", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "LSTN", + "description": "Listen mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OAR", + "description": "Own Address", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Tx data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXD", + "description": "Tx Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Rx Data Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDR", + "description": "CEC Rx Data Register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status Register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXACKE", + "description": "Tx-Missing acknowledge error", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Tx-Error", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXUDR", + "description": "Tx-Buffer Underrun", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXEND", + "description": "End of Transmission", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXBR", + "description": "Tx-Byte Request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ARBLST", + "description": "Arbitration Lost", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXACKE", + "description": "Rx-Missing Acknowledge", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBPE", + "description": "Rx-Long Bit Period Error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SBPE", + "description": "Rx-Short Bit period error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BRE", + "description": "Rx-Bit rising error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RXOVR", + "description": "Rx-Overrun", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RXEND", + "description": "End Of Reception", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXBR", + "description": "Rx-Byte Received", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXACKIE", + "description": "Tx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TXERRIE", + "description": "Tx-Error Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXUDRIE", + "description": "Tx-Underrun interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXENDIE", + "description": "Tx-End of message interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXBRIE", + "description": "Tx-Byte Request Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ARBLSTIE", + "description": "Arbitration Lost Interrupt Enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXACKIE", + "description": "Rx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBPEIE", + "description": "Long Bit Period Error Interrupt Enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SBPEIE", + "description": "Short Bit Period Error Interrupt Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BREIE", + "description": "Bit Rising Error Interrupt Enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RXOVRIE", + "description": "Rx-Buffer Overrun Interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RXENDIE", + "description": "End Of Reception Interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXBRIE", + "description": "Rx-Byte Received Interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "Flash", + "description": "Flash", + "groupName": "Flash", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "3" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "LATENCY", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "PRFTBE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "PRFTBS", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FKEYR", + "description": "Flash Key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEYR", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Flash status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRT", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Flash control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "FORCE_OPTLOAD", + "description": "Force option byte loading", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFF2", + "fields": [ + { + "name": "Data1", + "description": "Data1", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "VDDA_MONITOR", + "description": "VDDA_MONITOR", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BOOT1", + "description": "BOOT1", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LEVEL2_PROT", + "description": "Level 2 protection status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LEVEL1_PROT", + "description": "Level 1 protection status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DBGMCU", + "description": "Debug support", + "groupName": "DBGMCU", + "baseAddress": "0x40015800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "MCU Device ID Code Register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "Device Identifier", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DIV_ID", + "description": "Division Identifier", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "REV_ID", + "description": "Revision Identifier", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Debug MCU Configuration Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_STOP", + "description": "Debug Stop Mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "Debug Standby Mode", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "APBLFZ", + "displayName": "APBLFZ", + "description": "APB Low Freeze Register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER2_STOP", + "description": "Debug Timer 2 stopped when Core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER3_STOP", + "description": "Debug Timer 3 stopped when Core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER6_STOP", + "description": "Debug Timer 6 stopped when Core is halted", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER14_STOP", + "description": "Debug Timer 14 stopped when Core is halted", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_RTC_STOP", + "description": "Debug RTC stopped when Core is halted", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "Debug Window Wachdog stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDG_STOP", + "description": "Debug Independent Wachdog stopped when Core is halted", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C1_SMBUS_TIMEOUT", + "description": "SMBUS timeout mode stopped when Core is halted", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APBHFZ", + "displayName": "APBHFZ", + "description": "APB High Freeze Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER1_STOP", + "description": "Debug Timer 1 stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER15_STO", + "description": "Debug Timer 15 stopped when Core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER16_STO", + "description": "Debug Timer 16 stopped when Core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER17_STO", + "description": "Debug Timer 17 stopped when Core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "USB", + "description": "Universal serial bus full-speed device interface", + "groupName": "USB", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USB", + "description": "USB global interrupt", + "value": "31" + } + ], + "registers": [ + { + "name": "EP0R", + "displayName": "EP0R", + "description": "Endpoint 0 register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP1R", + "displayName": "EP1R", + "description": "Endpoint 1 register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP2R", + "displayName": "EP2R", + "description": "Endpoint 2 register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP3R", + "displayName": "EP3R", + "description": "Endpoint 3 register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP4R", + "displayName": "EP4R", + "description": "Endpoint 4 register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP5R", + "displayName": "EP5R", + "description": "Endpoint 5 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP6R", + "displayName": "EP6R", + "description": "Endpoint 6 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP7R", + "displayName": "EP7R", + "description": "Endpoint 7 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNTR", + "displayName": "CNTR", + "description": "Control register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000003", + "fields": [ + { + "name": "FRES", + "description": "Force USB Reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDWN", + "description": "Power down", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPMODE", + "description": "Low-power mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSUSP", + "description": "Force suspend", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RESUME", + "description": "Resume request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "L1RESUME", + "description": "LPM L1 Resume request", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "L1REQM", + "description": "LPM L1 state request interrupt mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ESOFM", + "description": "Expected start of frame interrupt mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOFM", + "description": "Start of frame interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESETM", + "description": "USB reset interrupt mask", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSPM", + "description": "Suspend mode interrupt mask", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUPM", + "description": "Wakeup interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRM", + "description": "Error interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVRM", + "description": "Packet memory area over / underrun interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTRM", + "description": "Correct transfer interrupt mask", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ISTR", + "displayName": "ISTR", + "description": "Interrupt status register", + "addressOffset": "0x44", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EP_ID", + "description": "Endpoint Identifier", + "bitOffset": "0", + "bitWidth": "4", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Direction of transaction", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "L1REQ", + "description": "LPM L1 state request", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESOF", + "description": "Expected start frame", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RESET", + "description": "Reset request", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SUSP", + "description": "Suspend mode request", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUP", + "description": "Wakeup", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERR", + "description": "Error", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PMAOVR", + "description": "Packet memory area over / underrun", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTR", + "description": "Correct transfer", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FNR", + "displayName": "FNR", + "description": "Frame number register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FN", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "LSOF", + "description": "Lost SOF", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "LCK", + "description": "Locked", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "RXDM", + "description": "Receive data - line status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXDP", + "description": "Receive data + line status", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DADDR", + "displayName": "DADDR", + "description": "Device address", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Device address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "EF", + "description": "Enable function", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "BTABLE", + "displayName": "BTABLE", + "description": "Buffer table address", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BTABLE", + "description": "Buffer table", + "bitOffset": "3", + "bitWidth": "13" + } + ] + }, + { + "name": "LPMCSR", + "displayName": "LPMCSR", + "description": "LPM control and status register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "LPMEN", + "description": "LPM support enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPMACK", + "description": "LPM Token acknowledge enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REMWAKE", + "description": "BRemoteWake value", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BESL", + "description": "BESL value", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-only" + } + ] + }, + { + "name": "BCDR", + "displayName": "BCDR", + "description": "Battery charging detector", + "addressOffset": "0x58", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "BCDEN", + "description": "Battery charging detector (BCD) enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDEN", + "description": "Data contact detection (DCD) mode enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PDEN", + "description": "Primary detection (PD) mode enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDEN", + "description": "Secondary detection (SD) mode enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDET", + "description": "Data contact detection (DCD) status", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PDET", + "description": "Primary detection (PD) status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SDET", + "description": "Secondary detection (SD) status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PS2DET", + "description": "DM pull-up detection status", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DPPU", + "description": "DP pull-up control", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "CRS", + "description": "Clock recovery system", + "groupName": "CRS", + "baseAddress": "0x40006C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "TRIM", + "description": "HSI48 oscillator smooth trimming", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "SWSYNC", + "description": "Generate software SYNC event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AUTOTRIMEN", + "description": "Automatic trimming enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Frequency error counter enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ESYNCIE", + "description": "Expected SYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Synchronization or trimming error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCWARNIE", + "description": "SYNC warning interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SYNCOKIE", + "description": "SYNC event OK interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2022BB7F", + "fields": [ + { + "name": "SYNCPOL", + "description": "SYNC polarity selection", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SYNCSRC", + "description": "SYNC signal source selection", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "SYNCDIV", + "description": "SYNC divider", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "FELIM", + "description": "Frequency error limit", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "RELOAD", + "description": "Counter reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FECAP", + "description": "Frequency error capture", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FEDIR", + "description": "Frequency error direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TRIMOVF", + "description": "Trimming overflow or underflow", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SYNCMISS", + "description": "SYNC missed", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SYNCERR", + "description": "SYNC error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ESYNCF", + "description": "Expected SYNC flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERRF", + "description": "Error flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCWARNF", + "description": "SYNC warning flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SYNCOKF", + "description": "SYNC event OK flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ESYNCC", + "description": "Expected SYNC clear flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERRC", + "description": "Error clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCWARNC", + "description": "SYNC warning clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SYNCOKC", + "description": "SYNC event OK clear flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_ESR", + "displayName": "CAN_ESR", + "description": "CAN_ESR", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_BTR", + "displayName": "CAN_BTR", + "description": "CAN BTR", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + } + ] + }, + { + "name": "CAN_TI0R", + "displayName": "CAN_TI0R", + "description": "CAN_TI0R", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + 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"Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/adc.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/adc.c new file mode 100644 index 0000000000..558ed18763 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/adc.c @@ -0,0 +1,324 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.ier = cm_object_get_child_by_name(obj, "IER"); + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.cfgr1 = cm_object_get_child_by_name(obj, "CFGR1"); + state->u.f0.reg.cfgr2 = cm_object_get_child_by_name(obj, "CFGR2"); + state->u.f0.reg.smpr = cm_object_get_child_by_name(obj, "SMPR"); + state->u.f0.reg.tr = cm_object_get_child_by_name(obj, "TR"); + state->u.f0.reg.chselr = cm_object_get_child_by_name(obj, "CHSELR"); + state->u.f0.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f0.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + + + // ISR bitfields. + state->u.f0.fld.isr.adrdy = cm_object_get_child_by_name(state->u.f0.reg.isr, "ADRDY"); + state->u.f0.fld.isr.eosmp = cm_object_get_child_by_name(state->u.f0.reg.isr, "EOSMP"); + state->u.f0.fld.isr.eoc = cm_object_get_child_by_name(state->u.f0.reg.isr, "EOC"); + state->u.f0.fld.isr.eos = cm_object_get_child_by_name(state->u.f0.reg.isr, "EOS"); + state->u.f0.fld.isr.ovr = cm_object_get_child_by_name(state->u.f0.reg.isr, "OVR"); + state->u.f0.fld.isr.awd = cm_object_get_child_by_name(state->u.f0.reg.isr, "AWD"); + + // IER bitfields. + state->u.f0.fld.ier.adrdyie = cm_object_get_child_by_name(state->u.f0.reg.ier, "ADRDYIE"); + state->u.f0.fld.ier.eosmpie = cm_object_get_child_by_name(state->u.f0.reg.ier, "EOSMPIE"); + state->u.f0.fld.ier.eocie = cm_object_get_child_by_name(state->u.f0.reg.ier, "EOCIE"); + state->u.f0.fld.ier.eosie = cm_object_get_child_by_name(state->u.f0.reg.ier, "EOSIE"); + state->u.f0.fld.ier.ovrie = cm_object_get_child_by_name(state->u.f0.reg.ier, "OVRIE"); + state->u.f0.fld.ier.awdie = cm_object_get_child_by_name(state->u.f0.reg.ier, "AWDIE"); + + // CR bitfields. + state->u.f0.fld.cr.aden = cm_object_get_child_by_name(state->u.f0.reg.cr, "ADEN"); + state->u.f0.fld.cr.addis = cm_object_get_child_by_name(state->u.f0.reg.cr, "ADDIS"); + state->u.f0.fld.cr.adstart = cm_object_get_child_by_name(state->u.f0.reg.cr, "ADSTART"); + state->u.f0.fld.cr.adstp = cm_object_get_child_by_name(state->u.f0.reg.cr, "ADSTP"); + state->u.f0.fld.cr.adcal = cm_object_get_child_by_name(state->u.f0.reg.cr, "ADCAL"); + + // CFGR1 bitfields. + state->u.f0.fld.cfgr1.dmaen = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "DMAEN"); + state->u.f0.fld.cfgr1.dmacfg = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "DMACFG"); + state->u.f0.fld.cfgr1.scandir = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "SCANDIR"); + state->u.f0.fld.cfgr1.res = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "RES"); + state->u.f0.fld.cfgr1.align = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "ALIGN"); + state->u.f0.fld.cfgr1.extsel = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "EXTSEL"); + state->u.f0.fld.cfgr1.exten = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "EXTEN"); + state->u.f0.fld.cfgr1.ovrmod = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "OVRMOD"); + state->u.f0.fld.cfgr1.cont = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "CONT"); + state->u.f0.fld.cfgr1.autdly = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AUTDLY"); + state->u.f0.fld.cfgr1.autoff = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AUTOFF"); + state->u.f0.fld.cfgr1.discen = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "DISCEN"); + state->u.f0.fld.cfgr1.awdsgl = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AWDSGL"); + state->u.f0.fld.cfgr1.awden = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AWDEN"); + state->u.f0.fld.cfgr1.awdch = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AWDCH"); + + // CFGR2 bitfields. + state->u.f0.fld.cfgr2.jitoff_d2 = cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "JITOFF_D2"); + state->u.f0.fld.cfgr2.jitoff_d4 = cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "JITOFF_D4"); + + // SMPR bitfields. + state->u.f0.fld.smpr.smpr = cm_object_get_child_by_name(state->u.f0.reg.smpr, "SMPR"); + + // TR bitfields. + state->u.f0.fld.tr.lt = cm_object_get_child_by_name(state->u.f0.reg.tr, "LT"); + state->u.f0.fld.tr.ht = cm_object_get_child_by_name(state->u.f0.reg.tr, "HT"); + + // CHSELR bitfields. + state->u.f0.fld.chselr.chsel0 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL0"); + state->u.f0.fld.chselr.chsel1 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL1"); + state->u.f0.fld.chselr.chsel2 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL2"); + state->u.f0.fld.chselr.chsel3 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL3"); + state->u.f0.fld.chselr.chsel4 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL4"); + state->u.f0.fld.chselr.chsel5 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL5"); + state->u.f0.fld.chselr.chsel6 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL6"); + state->u.f0.fld.chselr.chsel7 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL7"); + state->u.f0.fld.chselr.chsel8 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL8"); + state->u.f0.fld.chselr.chsel9 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL9"); + state->u.f0.fld.chselr.chsel10 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL10"); + state->u.f0.fld.chselr.chsel11 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL11"); + state->u.f0.fld.chselr.chsel12 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL12"); + state->u.f0.fld.chselr.chsel13 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL13"); + state->u.f0.fld.chselr.chsel14 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL14"); + state->u.f0.fld.chselr.chsel15 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL15"); + state->u.f0.fld.chselr.chsel16 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL16"); + state->u.f0.fld.chselr.chsel17 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL17"); + state->u.f0.fld.chselr.chsel18 = cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL18"); + + // DR bitfields. + state->u.f0.fld.dr.data = cm_object_get_child_by_name(state->u.f0.reg.dr, "DATA"); + + // CCR bitfields. + state->u.f0.fld.ccr.vrefen = cm_object_get_child_by_name(state->u.f0.reg.ccr, "VREFEN"); + state->u.f0.fld.ccr.tsen = cm_object_get_child_by_name(state->u.f0.reg.ccr, "TSEN"); + state->u.f0.fld.ccr.vbaten = cm_object_get_child_by_name(state->u.f0.reg.ccr, "VBATEN"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/adc.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/adc.h new file mode 100644 index 0000000000..42ff45ea63 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/adc.h @@ -0,0 +1,209 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 ADC (Analog-to-digital converter) registers. + struct { + Object *isr; // 0x0 (Interrupt and status register) + Object *ier; // 0x4 (Interrupt enable register) + Object *cr; // 0x8 (Control register) + Object *cfgr1; // 0xC (Configuration register 1) + Object *cfgr2; // 0x10 (Configuration register 2) + Object *smpr; // 0x14 (Sampling time register) + Object *tr; // 0x20 (Watchdog threshold register) + Object *chselr; // 0x28 (Channel selection register) + Object *dr; // 0x40 (Data register) + Object *ccr; // 0x308 (Common configuration register) + } reg; + + struct { + + // ISR (Interrupt and status register) bitfields. + struct { + Object *adrdy; // [0:0] ADC ready + Object *eosmp; // [1:1] End of sampling flag + Object *eoc; // [2:2] End of conversion flag + Object *eos; // [3:3] End of sequence flag + Object *ovr; // [4:4] ADC overrun + Object *awd; // [7:7] Analog watchdog flag + } isr; + + // IER (Interrupt enable register) bitfields. + struct { + Object *adrdyie; // [0:0] ADC ready interrupt enable + Object *eosmpie; // [1:1] End of sampling flag interrupt enable + Object *eocie; // [2:2] End of conversion interrupt enable + Object *eosie; // [3:3] End of conversion sequence interrupt enable + Object *ovrie; // [4:4] Overrun interrupt enable + Object *awdie; // [7:7] Analog watchdog interrupt enable + } ier; + + // CR (Control register) bitfields. + struct { + Object *aden; // [0:0] ADC enable command + Object *addis; // [1:1] ADC disable command + Object *adstart; // [2:2] ADC start conversion command + Object *adstp; // [4:4] ADC stop conversion command + Object *adcal; // [31:31] ADC calibration + } cr; + + // CFGR1 (Configuration register 1) bitfields. + struct { + Object *dmaen; // [0:0] Direct memory access enable + Object *dmacfg; // [1:1] Direct memery access configuration + Object *scandir; // [2:2] Scan sequence direction + Object *res; // [3:4] Data resolution + Object *align; // [5:5] Data alignment + Object *extsel; // [6:8] External trigger selection + Object *exten; // [10:11] External trigger enable and polarity selection + Object *ovrmod; // [12:12] Overrun management mode + Object *cont; // [13:13] Single / continuous conversion mode + Object *autdly; // [14:14] Auto-delayed conversion mode + Object *autoff; // [15:15] Auto-off mode + Object *discen; // [16:16] Discontinuous mode + Object *awdsgl; // [22:22] Enable the watchdog on a single channel or on all channels + Object *awden; // [23:23] Analog watchdog enable + Object *awdch; // [26:30] Analog watchdog channel selection + } cfgr1; + + // CFGR2 (Configuration register 2) bitfields. + struct { + Object *jitoff_d2; // [30:30] JITOFF_D2 + Object *jitoff_d4; // [31:31] JITOFF_D4 + } cfgr2; + + // SMPR (Sampling time register) bitfields. + struct { + Object *smpr; // [0:2] Sampling time selection + } smpr; + + // TR (Watchdog threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + Object *ht; // [16:27] Analog watchdog higher threshold + } tr; + + // CHSELR (Channel selection register) bitfields. + struct { + Object *chsel0; // [0:0] Channel-x selection + Object *chsel1; // [1:1] Channel-x selection + Object *chsel2; // [2:2] Channel-x selection + Object *chsel3; // [3:3] Channel-x selection + Object *chsel4; // [4:4] Channel-x selection + Object *chsel5; // [5:5] Channel-x selection + Object *chsel6; // [6:6] Channel-x selection + Object *chsel7; // [7:7] Channel-x selection + Object *chsel8; // [8:8] Channel-x selection + Object *chsel9; // [9:9] Channel-x selection + Object *chsel10; // [10:10] Channel-x selection + Object *chsel11; // [11:11] Channel-x selection + Object *chsel12; // [12:12] Channel-x selection + Object *chsel13; // [13:13] Channel-x selection + Object *chsel14; // [14:14] Channel-x selection + Object *chsel15; // [15:15] Channel-x selection + Object *chsel16; // [16:16] Channel-x selection + Object *chsel17; // [17:17] Channel-x selection + Object *chsel18; // [18:18] Channel-x selection + } chselr; + + // DR (Data register) bitfields. + struct { + Object *data; // [0:15] Converted data + } dr; + + // CCR (Common configuration register) bitfields. + struct { + Object *vrefen; // [22:22] Temperature sensor and VREFINT enable + Object *tsen; // [23:23] Temperature sensor enable + Object *vbaten; // [24:24] VBAT enable + } ccr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/can.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/can.c new file mode 100644 index 0000000000..aaf0ad38bc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/can.c @@ -0,0 +1,2560 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_can_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.can_mcr = cm_object_get_child_by_name(obj, "CAN_MCR"); + state->u.f0.reg.can_msr = cm_object_get_child_by_name(obj, "CAN_MSR"); + state->u.f0.reg.can_tsr = cm_object_get_child_by_name(obj, "CAN_TSR"); + state->u.f0.reg.can_rf0r = cm_object_get_child_by_name(obj, "CAN_RF0R"); + state->u.f0.reg.can_rf1r = cm_object_get_child_by_name(obj, "CAN_RF1R"); + state->u.f0.reg.can_ier = cm_object_get_child_by_name(obj, "CAN_IER"); + state->u.f0.reg.can_esr = cm_object_get_child_by_name(obj, "CAN_ESR"); + state->u.f0.reg.can_btr = cm_object_get_child_by_name(obj, "CAN_BTR"); + state->u.f0.reg.can_ti0r = cm_object_get_child_by_name(obj, "CAN_TI0R"); + state->u.f0.reg.can_tdt0r = cm_object_get_child_by_name(obj, "CAN_TDT0R"); + state->u.f0.reg.can_tdl0r = cm_object_get_child_by_name(obj, "CAN_TDL0R"); + state->u.f0.reg.can_tdh0r = cm_object_get_child_by_name(obj, "CAN_TDH0R"); + state->u.f0.reg.can_ti1r = cm_object_get_child_by_name(obj, "CAN_TI1R"); + state->u.f0.reg.can_tdt1r = cm_object_get_child_by_name(obj, "CAN_TDT1R"); + state->u.f0.reg.can_tdl1r = cm_object_get_child_by_name(obj, "CAN_TDL1R"); + state->u.f0.reg.can_tdh1r = cm_object_get_child_by_name(obj, "CAN_TDH1R"); + state->u.f0.reg.can_ti2r = cm_object_get_child_by_name(obj, "CAN_TI2R"); + state->u.f0.reg.can_tdt2r = cm_object_get_child_by_name(obj, "CAN_TDT2R"); + state->u.f0.reg.can_tdl2r = cm_object_get_child_by_name(obj, "CAN_TDL2R"); + state->u.f0.reg.can_tdh2r = cm_object_get_child_by_name(obj, "CAN_TDH2R"); + state->u.f0.reg.can_ri0r = cm_object_get_child_by_name(obj, "CAN_RI0R"); + state->u.f0.reg.can_rdt0r = cm_object_get_child_by_name(obj, "CAN_RDT0R"); + state->u.f0.reg.can_rdl0r = cm_object_get_child_by_name(obj, "CAN_RDL0R"); + state->u.f0.reg.can_rdh0r = cm_object_get_child_by_name(obj, "CAN_RDH0R"); + state->u.f0.reg.can_ri1r = cm_object_get_child_by_name(obj, "CAN_RI1R"); + state->u.f0.reg.can_rdt1r = cm_object_get_child_by_name(obj, "CAN_RDT1R"); + state->u.f0.reg.can_rdl1r = cm_object_get_child_by_name(obj, "CAN_RDL1R"); + state->u.f0.reg.can_rdh1r = cm_object_get_child_by_name(obj, "CAN_RDH1R"); + state->u.f0.reg.can_fmr = cm_object_get_child_by_name(obj, "CAN_FMR"); + state->u.f0.reg.can_fm1r = cm_object_get_child_by_name(obj, "CAN_FM1R"); + state->u.f0.reg.can_fs1r = cm_object_get_child_by_name(obj, "CAN_FS1R"); + state->u.f0.reg.can_ffa1r = cm_object_get_child_by_name(obj, "CAN_FFA1R"); + state->u.f0.reg.can_fa1r = cm_object_get_child_by_name(obj, "CAN_FA1R"); + state->u.f0.reg.f0r1 = cm_object_get_child_by_name(obj, "F0R1"); + state->u.f0.reg.f0r2 = cm_object_get_child_by_name(obj, "F0R2"); + state->u.f0.reg.f1r1 = cm_object_get_child_by_name(obj, "F1R1"); + state->u.f0.reg.f1r2 = cm_object_get_child_by_name(obj, "F1R2"); + state->u.f0.reg.f2r1 = cm_object_get_child_by_name(obj, "F2R1"); + state->u.f0.reg.f2r2 = cm_object_get_child_by_name(obj, "F2R2"); + state->u.f0.reg.f3r1 = cm_object_get_child_by_name(obj, "F3R1"); + state->u.f0.reg.f3r2 = cm_object_get_child_by_name(obj, "F3R2"); + state->u.f0.reg.f4r1 = cm_object_get_child_by_name(obj, "F4R1"); + state->u.f0.reg.f4r2 = cm_object_get_child_by_name(obj, "F4R2"); + state->u.f0.reg.f5r1 = cm_object_get_child_by_name(obj, "F5R1"); + state->u.f0.reg.f5r2 = cm_object_get_child_by_name(obj, "F5R2"); + state->u.f0.reg.f6r1 = cm_object_get_child_by_name(obj, "F6R1"); + state->u.f0.reg.f6r2 = cm_object_get_child_by_name(obj, "F6R2"); + state->u.f0.reg.f7r1 = cm_object_get_child_by_name(obj, "F7R1"); + state->u.f0.reg.f7r2 = cm_object_get_child_by_name(obj, "F7R2"); + state->u.f0.reg.f8r1 = cm_object_get_child_by_name(obj, "F8R1"); + state->u.f0.reg.f8r2 = cm_object_get_child_by_name(obj, "F8R2"); + state->u.f0.reg.f9r1 = cm_object_get_child_by_name(obj, "F9R1"); + state->u.f0.reg.f9r2 = cm_object_get_child_by_name(obj, "F9R2"); + state->u.f0.reg.f10r1 = cm_object_get_child_by_name(obj, "F10R1"); + state->u.f0.reg.f10r2 = cm_object_get_child_by_name(obj, "F10R2"); + state->u.f0.reg.f11r1 = cm_object_get_child_by_name(obj, "F11R1"); + state->u.f0.reg.f11r2 = cm_object_get_child_by_name(obj, "F11R2"); + state->u.f0.reg.f12r1 = cm_object_get_child_by_name(obj, "F12R1"); + state->u.f0.reg.f12r2 = cm_object_get_child_by_name(obj, "F12R2"); + state->u.f0.reg.f13r1 = cm_object_get_child_by_name(obj, "F13R1"); + state->u.f0.reg.f13r2 = cm_object_get_child_by_name(obj, "F13R2"); + state->u.f0.reg.f14r1 = cm_object_get_child_by_name(obj, "F14R1"); + state->u.f0.reg.f14r2 = cm_object_get_child_by_name(obj, "F14R2"); + state->u.f0.reg.f15r1 = cm_object_get_child_by_name(obj, "F15R1"); + state->u.f0.reg.f15r2 = cm_object_get_child_by_name(obj, "F15R2"); + state->u.f0.reg.f16r1 = cm_object_get_child_by_name(obj, "F16R1"); + state->u.f0.reg.f16r2 = cm_object_get_child_by_name(obj, "F16R2"); + state->u.f0.reg.f17r1 = cm_object_get_child_by_name(obj, "F17R1"); + state->u.f0.reg.f17r2 = cm_object_get_child_by_name(obj, "F17R2"); + state->u.f0.reg.f18r1 = cm_object_get_child_by_name(obj, "F18R1"); + state->u.f0.reg.f18r2 = cm_object_get_child_by_name(obj, "F18R2"); + state->u.f0.reg.f19r1 = cm_object_get_child_by_name(obj, "F19R1"); + state->u.f0.reg.f19r2 = cm_object_get_child_by_name(obj, "F19R2"); + state->u.f0.reg.f20r1 = cm_object_get_child_by_name(obj, "F20R1"); + state->u.f0.reg.f20r2 = cm_object_get_child_by_name(obj, "F20R2"); + state->u.f0.reg.f21r1 = cm_object_get_child_by_name(obj, "F21R1"); + state->u.f0.reg.f21r2 = cm_object_get_child_by_name(obj, "F21R2"); + state->u.f0.reg.f22r1 = cm_object_get_child_by_name(obj, "F22R1"); + state->u.f0.reg.f22r2 = cm_object_get_child_by_name(obj, "F22R2"); + state->u.f0.reg.f23r1 = cm_object_get_child_by_name(obj, "F23R1"); + state->u.f0.reg.f23r2 = cm_object_get_child_by_name(obj, "F23R2"); + state->u.f0.reg.f24r1 = cm_object_get_child_by_name(obj, "F24R1"); + state->u.f0.reg.f24r2 = cm_object_get_child_by_name(obj, "F24R2"); + state->u.f0.reg.f25r1 = cm_object_get_child_by_name(obj, "F25R1"); + state->u.f0.reg.f25r2 = cm_object_get_child_by_name(obj, "F25R2"); + state->u.f0.reg.f26r1 = cm_object_get_child_by_name(obj, "F26R1"); + state->u.f0.reg.f26r2 = cm_object_get_child_by_name(obj, "F26R2"); + state->u.f0.reg.f27r1 = cm_object_get_child_by_name(obj, "F27R1"); + state->u.f0.reg.f27r2 = cm_object_get_child_by_name(obj, "F27R2"); + + + // CAN_MCR bitfields. + state->u.f0.fld.can_mcr.inrq = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "INRQ"); + state->u.f0.fld.can_mcr.sleep = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "SLEEP"); + state->u.f0.fld.can_mcr.txfp = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "TXFP"); + state->u.f0.fld.can_mcr.rflm = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "RFLM"); + state->u.f0.fld.can_mcr.nart = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "NART"); + state->u.f0.fld.can_mcr.awum = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "AWUM"); + state->u.f0.fld.can_mcr.abom = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "ABOM"); + state->u.f0.fld.can_mcr.ttcm = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "TTCM"); + state->u.f0.fld.can_mcr.reset = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "RESET"); + state->u.f0.fld.can_mcr.dbf = cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "DBF"); + + // CAN_MSR bitfields. + state->u.f0.fld.can_msr.inak = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "INAK"); + state->u.f0.fld.can_msr.slak = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "SLAK"); + state->u.f0.fld.can_msr.erri = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "ERRI"); + state->u.f0.fld.can_msr.wkui = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "WKUI"); + state->u.f0.fld.can_msr.slaki = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "SLAKI"); + state->u.f0.fld.can_msr.txm = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "TXM"); + state->u.f0.fld.can_msr.rxm = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "RXM"); + state->u.f0.fld.can_msr.samp = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "SAMP"); + state->u.f0.fld.can_msr.rx = cm_object_get_child_by_name(state->u.f0.reg.can_msr, "RX"); + + // CAN_TSR bitfields. + state->u.f0.fld.can_tsr.rqcp0 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "RQCP0"); + state->u.f0.fld.can_tsr.txok0 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TXOK0"); + state->u.f0.fld.can_tsr.alst0 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ALST0"); + state->u.f0.fld.can_tsr.terr0 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TERR0"); + state->u.f0.fld.can_tsr.abrq0 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ABRQ0"); + state->u.f0.fld.can_tsr.rqcp1 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "RQCP1"); + state->u.f0.fld.can_tsr.txok1 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TXOK1"); + state->u.f0.fld.can_tsr.alst1 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ALST1"); + state->u.f0.fld.can_tsr.terr1 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TERR1"); + state->u.f0.fld.can_tsr.abrq1 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ABRQ1"); + state->u.f0.fld.can_tsr.rqcp2 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "RQCP2"); + state->u.f0.fld.can_tsr.txok2 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TXOK2"); + state->u.f0.fld.can_tsr.alst2 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ALST2"); + state->u.f0.fld.can_tsr.terr2 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TERR2"); + state->u.f0.fld.can_tsr.abrq2 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ABRQ2"); + state->u.f0.fld.can_tsr.code = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "CODE"); + state->u.f0.fld.can_tsr.tme0 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TME0"); + state->u.f0.fld.can_tsr.tme1 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TME1"); + state->u.f0.fld.can_tsr.tme2 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TME2"); + state->u.f0.fld.can_tsr.low0 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "LOW0"); + state->u.f0.fld.can_tsr.low1 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "LOW1"); + state->u.f0.fld.can_tsr.low2 = cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "LOW2"); + + // CAN_RF0R bitfields. + state->u.f0.fld.can_rf0r.fmp0 = cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "FMP0"); + state->u.f0.fld.can_rf0r.full0 = cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "FULL0"); + state->u.f0.fld.can_rf0r.fovr0 = cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "FOVR0"); + state->u.f0.fld.can_rf0r.rfom0 = cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "RFOM0"); + + // CAN_RF1R bitfields. + state->u.f0.fld.can_rf1r.fmp1 = cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "FMP1"); + state->u.f0.fld.can_rf1r.full1 = cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "FULL1"); + state->u.f0.fld.can_rf1r.fovr1 = cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "FOVR1"); + state->u.f0.fld.can_rf1r.rfom1 = cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "RFOM1"); + + // CAN_IER bitfields. + state->u.f0.fld.can_ier.tmeie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "TMEIE"); + state->u.f0.fld.can_ier.fmpie0 = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FMPIE0"); + state->u.f0.fld.can_ier.ffie0 = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FFIE0"); + state->u.f0.fld.can_ier.fovie0 = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FOVIE0"); + state->u.f0.fld.can_ier.fmpie1 = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FMPIE1"); + state->u.f0.fld.can_ier.ffie1 = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FFIE1"); + state->u.f0.fld.can_ier.fovie1 = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FOVIE1"); + state->u.f0.fld.can_ier.ewgie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "EWGIE"); + state->u.f0.fld.can_ier.epvie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "EPVIE"); + state->u.f0.fld.can_ier.bofie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "BOFIE"); + state->u.f0.fld.can_ier.lecie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "LECIE"); + state->u.f0.fld.can_ier.errie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "ERRIE"); + state->u.f0.fld.can_ier.wkuie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "WKUIE"); + state->u.f0.fld.can_ier.slkie = cm_object_get_child_by_name(state->u.f0.reg.can_ier, "SLKIE"); + + // CAN_ESR bitfields. + state->u.f0.fld.can_esr.ewgf = cm_object_get_child_by_name(state->u.f0.reg.can_esr, "EWGF"); + state->u.f0.fld.can_esr.epvf = cm_object_get_child_by_name(state->u.f0.reg.can_esr, "EPVF"); + state->u.f0.fld.can_esr.boff = cm_object_get_child_by_name(state->u.f0.reg.can_esr, "BOFF"); + state->u.f0.fld.can_esr.lec = cm_object_get_child_by_name(state->u.f0.reg.can_esr, "LEC"); + state->u.f0.fld.can_esr.tec = cm_object_get_child_by_name(state->u.f0.reg.can_esr, "TEC"); + state->u.f0.fld.can_esr.rec = cm_object_get_child_by_name(state->u.f0.reg.can_esr, "REC"); + + // CAN_BTR bitfields. + state->u.f0.fld.can_btr.brp = cm_object_get_child_by_name(state->u.f0.reg.can_btr, "BRP"); + state->u.f0.fld.can_btr.ts1 = cm_object_get_child_by_name(state->u.f0.reg.can_btr, "TS1"); + state->u.f0.fld.can_btr.ts2 = cm_object_get_child_by_name(state->u.f0.reg.can_btr, "TS2"); + state->u.f0.fld.can_btr.sjw = cm_object_get_child_by_name(state->u.f0.reg.can_btr, "SJW"); + state->u.f0.fld.can_btr.lbkm = cm_object_get_child_by_name(state->u.f0.reg.can_btr, "LBKM"); + state->u.f0.fld.can_btr.silm = cm_object_get_child_by_name(state->u.f0.reg.can_btr, "SILM"); + + // CAN_TI0R bitfields. + state->u.f0.fld.can_ti0r.txrq = cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "TXRQ"); + state->u.f0.fld.can_ti0r.rtr = cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "RTR"); + state->u.f0.fld.can_ti0r.ide = cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "IDE"); + state->u.f0.fld.can_ti0r.exid = cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "EXID"); + state->u.f0.fld.can_ti0r.stid = cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "STID"); + + // CAN_TDT0R bitfields. + state->u.f0.fld.can_tdt0r.dlc = cm_object_get_child_by_name(state->u.f0.reg.can_tdt0r, "DLC"); + state->u.f0.fld.can_tdt0r.tgt = cm_object_get_child_by_name(state->u.f0.reg.can_tdt0r, "TGT"); + state->u.f0.fld.can_tdt0r.time = cm_object_get_child_by_name(state->u.f0.reg.can_tdt0r, "TIME"); + + // CAN_TDL0R bitfields. + state->u.f0.fld.can_tdl0r.data0 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA0"); + state->u.f0.fld.can_tdl0r.data1 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA1"); + state->u.f0.fld.can_tdl0r.data2 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA2"); + state->u.f0.fld.can_tdl0r.data3 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA3"); + + // CAN_TDH0R bitfields. + state->u.f0.fld.can_tdh0r.data4 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA4"); + state->u.f0.fld.can_tdh0r.data5 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA5"); + state->u.f0.fld.can_tdh0r.data6 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA6"); + state->u.f0.fld.can_tdh0r.data7 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA7"); + + // CAN_TI1R bitfields. + state->u.f0.fld.can_ti1r.txrq = cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "TXRQ"); + state->u.f0.fld.can_ti1r.rtr = cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "RTR"); + state->u.f0.fld.can_ti1r.ide = cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "IDE"); + state->u.f0.fld.can_ti1r.exid = cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "EXID"); + state->u.f0.fld.can_ti1r.stid = cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "STID"); + + // CAN_TDT1R bitfields. + state->u.f0.fld.can_tdt1r.dlc = cm_object_get_child_by_name(state->u.f0.reg.can_tdt1r, "DLC"); + state->u.f0.fld.can_tdt1r.tgt = cm_object_get_child_by_name(state->u.f0.reg.can_tdt1r, "TGT"); + state->u.f0.fld.can_tdt1r.time = cm_object_get_child_by_name(state->u.f0.reg.can_tdt1r, "TIME"); + + // CAN_TDL1R bitfields. + state->u.f0.fld.can_tdl1r.data0 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA0"); + state->u.f0.fld.can_tdl1r.data1 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA1"); + state->u.f0.fld.can_tdl1r.data2 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA2"); + state->u.f0.fld.can_tdl1r.data3 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA3"); + + // CAN_TDH1R bitfields. + state->u.f0.fld.can_tdh1r.data4 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA4"); + state->u.f0.fld.can_tdh1r.data5 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA5"); + state->u.f0.fld.can_tdh1r.data6 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA6"); + state->u.f0.fld.can_tdh1r.data7 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA7"); + + // CAN_TI2R bitfields. + state->u.f0.fld.can_ti2r.txrq = cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "TXRQ"); + state->u.f0.fld.can_ti2r.rtr = cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "RTR"); + state->u.f0.fld.can_ti2r.ide = cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "IDE"); + state->u.f0.fld.can_ti2r.exid = cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "EXID"); + state->u.f0.fld.can_ti2r.stid = cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "STID"); + + // CAN_TDT2R bitfields. + state->u.f0.fld.can_tdt2r.dlc = cm_object_get_child_by_name(state->u.f0.reg.can_tdt2r, "DLC"); + state->u.f0.fld.can_tdt2r.tgt = cm_object_get_child_by_name(state->u.f0.reg.can_tdt2r, "TGT"); + state->u.f0.fld.can_tdt2r.time = cm_object_get_child_by_name(state->u.f0.reg.can_tdt2r, "TIME"); + + // CAN_TDL2R bitfields. + state->u.f0.fld.can_tdl2r.data0 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA0"); + state->u.f0.fld.can_tdl2r.data1 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA1"); + state->u.f0.fld.can_tdl2r.data2 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA2"); + state->u.f0.fld.can_tdl2r.data3 = cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA3"); + + // CAN_TDH2R bitfields. + state->u.f0.fld.can_tdh2r.data4 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA4"); + state->u.f0.fld.can_tdh2r.data5 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA5"); + state->u.f0.fld.can_tdh2r.data6 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA6"); + state->u.f0.fld.can_tdh2r.data7 = cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA7"); + + // CAN_RI0R bitfields. + state->u.f0.fld.can_ri0r.rtr = cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "RTR"); + state->u.f0.fld.can_ri0r.ide = cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "IDE"); + state->u.f0.fld.can_ri0r.exid = cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "EXID"); + state->u.f0.fld.can_ri0r.stid = cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "STID"); + + // CAN_RDT0R bitfields. + state->u.f0.fld.can_rdt0r.dlc = cm_object_get_child_by_name(state->u.f0.reg.can_rdt0r, "DLC"); + state->u.f0.fld.can_rdt0r.fmi = cm_object_get_child_by_name(state->u.f0.reg.can_rdt0r, "FMI"); + state->u.f0.fld.can_rdt0r.time = cm_object_get_child_by_name(state->u.f0.reg.can_rdt0r, "TIME"); + + // CAN_RDL0R bitfields. + state->u.f0.fld.can_rdl0r.data0 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA0"); + state->u.f0.fld.can_rdl0r.data1 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA1"); + state->u.f0.fld.can_rdl0r.data2 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA2"); + state->u.f0.fld.can_rdl0r.data3 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA3"); + + // CAN_RDH0R bitfields. + state->u.f0.fld.can_rdh0r.data4 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA4"); + state->u.f0.fld.can_rdh0r.data5 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA5"); + state->u.f0.fld.can_rdh0r.data6 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA6"); + state->u.f0.fld.can_rdh0r.data7 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA7"); + + // CAN_RI1R bitfields. + state->u.f0.fld.can_ri1r.rtr = cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "RTR"); + state->u.f0.fld.can_ri1r.ide = cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "IDE"); + state->u.f0.fld.can_ri1r.exid = cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "EXID"); + state->u.f0.fld.can_ri1r.stid = cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "STID"); + + // CAN_RDT1R bitfields. + state->u.f0.fld.can_rdt1r.dlc = cm_object_get_child_by_name(state->u.f0.reg.can_rdt1r, "DLC"); + state->u.f0.fld.can_rdt1r.fmi = cm_object_get_child_by_name(state->u.f0.reg.can_rdt1r, "FMI"); + state->u.f0.fld.can_rdt1r.time = cm_object_get_child_by_name(state->u.f0.reg.can_rdt1r, "TIME"); + + // CAN_RDL1R bitfields. + state->u.f0.fld.can_rdl1r.data0 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA0"); + state->u.f0.fld.can_rdl1r.data1 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA1"); + state->u.f0.fld.can_rdl1r.data2 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA2"); + state->u.f0.fld.can_rdl1r.data3 = cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA3"); + + // CAN_RDH1R bitfields. + state->u.f0.fld.can_rdh1r.data4 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA4"); + state->u.f0.fld.can_rdh1r.data5 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA5"); + state->u.f0.fld.can_rdh1r.data6 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA6"); + state->u.f0.fld.can_rdh1r.data7 = cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA7"); + + // CAN_FMR bitfields. + state->u.f0.fld.can_fmr.finit = cm_object_get_child_by_name(state->u.f0.reg.can_fmr, "FINIT"); + state->u.f0.fld.can_fmr.can2sb = cm_object_get_child_by_name(state->u.f0.reg.can_fmr, "CAN2SB"); + + // CAN_FM1R bitfields. + state->u.f0.fld.can_fm1r.fbm0 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM0"); + state->u.f0.fld.can_fm1r.fbm1 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM1"); + state->u.f0.fld.can_fm1r.fbm2 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM2"); + state->u.f0.fld.can_fm1r.fbm3 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM3"); + state->u.f0.fld.can_fm1r.fbm4 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM4"); + state->u.f0.fld.can_fm1r.fbm5 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM5"); + state->u.f0.fld.can_fm1r.fbm6 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM6"); + state->u.f0.fld.can_fm1r.fbm7 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM7"); + state->u.f0.fld.can_fm1r.fbm8 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM8"); + state->u.f0.fld.can_fm1r.fbm9 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM9"); + state->u.f0.fld.can_fm1r.fbm10 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM10"); + state->u.f0.fld.can_fm1r.fbm11 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM11"); + state->u.f0.fld.can_fm1r.fbm12 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM12"); + state->u.f0.fld.can_fm1r.fbm13 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM13"); + state->u.f0.fld.can_fm1r.fbm14 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM14"); + state->u.f0.fld.can_fm1r.fbm15 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM15"); + state->u.f0.fld.can_fm1r.fbm16 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM16"); + state->u.f0.fld.can_fm1r.fbm17 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM17"); + state->u.f0.fld.can_fm1r.fbm18 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM18"); + state->u.f0.fld.can_fm1r.fbm19 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM19"); + state->u.f0.fld.can_fm1r.fbm20 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM20"); + state->u.f0.fld.can_fm1r.fbm21 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM21"); + state->u.f0.fld.can_fm1r.fbm22 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM22"); + state->u.f0.fld.can_fm1r.fbm23 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM23"); + state->u.f0.fld.can_fm1r.fbm24 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM24"); + state->u.f0.fld.can_fm1r.fbm25 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM25"); + state->u.f0.fld.can_fm1r.fbm26 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM26"); + state->u.f0.fld.can_fm1r.fbm27 = cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM27"); + + // CAN_FS1R bitfields. + state->u.f0.fld.can_fs1r.fsc0 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC0"); + state->u.f0.fld.can_fs1r.fsc1 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC1"); + state->u.f0.fld.can_fs1r.fsc2 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC2"); + state->u.f0.fld.can_fs1r.fsc3 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC3"); + state->u.f0.fld.can_fs1r.fsc4 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC4"); + state->u.f0.fld.can_fs1r.fsc5 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC5"); + state->u.f0.fld.can_fs1r.fsc6 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC6"); + state->u.f0.fld.can_fs1r.fsc7 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC7"); + state->u.f0.fld.can_fs1r.fsc8 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC8"); + state->u.f0.fld.can_fs1r.fsc9 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC9"); + state->u.f0.fld.can_fs1r.fsc10 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC10"); + state->u.f0.fld.can_fs1r.fsc11 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC11"); + state->u.f0.fld.can_fs1r.fsc12 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC12"); + state->u.f0.fld.can_fs1r.fsc13 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC13"); + state->u.f0.fld.can_fs1r.fsc14 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC14"); + state->u.f0.fld.can_fs1r.fsc15 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC15"); + state->u.f0.fld.can_fs1r.fsc16 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC16"); + state->u.f0.fld.can_fs1r.fsc17 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC17"); + state->u.f0.fld.can_fs1r.fsc18 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC18"); + state->u.f0.fld.can_fs1r.fsc19 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC19"); + state->u.f0.fld.can_fs1r.fsc20 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC20"); + state->u.f0.fld.can_fs1r.fsc21 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC21"); + state->u.f0.fld.can_fs1r.fsc22 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC22"); + state->u.f0.fld.can_fs1r.fsc23 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC23"); + state->u.f0.fld.can_fs1r.fsc24 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC24"); + state->u.f0.fld.can_fs1r.fsc25 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC25"); + state->u.f0.fld.can_fs1r.fsc26 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC26"); + state->u.f0.fld.can_fs1r.fsc27 = cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC27"); + + // CAN_FFA1R bitfields. + state->u.f0.fld.can_ffa1r.ffa0 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA0"); + state->u.f0.fld.can_ffa1r.ffa1 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA1"); + state->u.f0.fld.can_ffa1r.ffa2 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA2"); + state->u.f0.fld.can_ffa1r.ffa3 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA3"); + state->u.f0.fld.can_ffa1r.ffa4 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA4"); + state->u.f0.fld.can_ffa1r.ffa5 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA5"); + state->u.f0.fld.can_ffa1r.ffa6 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA6"); + state->u.f0.fld.can_ffa1r.ffa7 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA7"); + state->u.f0.fld.can_ffa1r.ffa8 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA8"); + state->u.f0.fld.can_ffa1r.ffa9 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA9"); + state->u.f0.fld.can_ffa1r.ffa10 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA10"); + state->u.f0.fld.can_ffa1r.ffa11 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA11"); + state->u.f0.fld.can_ffa1r.ffa12 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA12"); + state->u.f0.fld.can_ffa1r.ffa13 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA13"); + state->u.f0.fld.can_ffa1r.ffa14 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA14"); + state->u.f0.fld.can_ffa1r.ffa15 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA15"); + state->u.f0.fld.can_ffa1r.ffa16 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA16"); + state->u.f0.fld.can_ffa1r.ffa17 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA17"); + state->u.f0.fld.can_ffa1r.ffa18 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA18"); + state->u.f0.fld.can_ffa1r.ffa19 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA19"); + state->u.f0.fld.can_ffa1r.ffa20 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA20"); + state->u.f0.fld.can_ffa1r.ffa21 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA21"); + state->u.f0.fld.can_ffa1r.ffa22 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA22"); + state->u.f0.fld.can_ffa1r.ffa23 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA23"); + state->u.f0.fld.can_ffa1r.ffa24 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA24"); + state->u.f0.fld.can_ffa1r.ffa25 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA25"); + state->u.f0.fld.can_ffa1r.ffa26 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA26"); + state->u.f0.fld.can_ffa1r.ffa27 = cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA27"); + + // CAN_FA1R bitfields. + state->u.f0.fld.can_fa1r.fact0 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT0"); + state->u.f0.fld.can_fa1r.fact1 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT1"); + state->u.f0.fld.can_fa1r.fact2 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT2"); + state->u.f0.fld.can_fa1r.fact3 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT3"); + state->u.f0.fld.can_fa1r.fact4 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT4"); + state->u.f0.fld.can_fa1r.fact5 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT5"); + state->u.f0.fld.can_fa1r.fact6 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT6"); + state->u.f0.fld.can_fa1r.fact7 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT7"); + state->u.f0.fld.can_fa1r.fact8 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT8"); + state->u.f0.fld.can_fa1r.fact9 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT9"); + state->u.f0.fld.can_fa1r.fact10 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT10"); + state->u.f0.fld.can_fa1r.fact11 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT11"); + state->u.f0.fld.can_fa1r.fact12 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT12"); + state->u.f0.fld.can_fa1r.fact13 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT13"); + state->u.f0.fld.can_fa1r.fact14 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT14"); + state->u.f0.fld.can_fa1r.fact15 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT15"); + state->u.f0.fld.can_fa1r.fact16 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT16"); + state->u.f0.fld.can_fa1r.fact17 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT17"); + state->u.f0.fld.can_fa1r.fact18 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT18"); + state->u.f0.fld.can_fa1r.fact19 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT19"); + state->u.f0.fld.can_fa1r.fact20 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT20"); + state->u.f0.fld.can_fa1r.fact21 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT21"); + state->u.f0.fld.can_fa1r.fact22 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT22"); + state->u.f0.fld.can_fa1r.fact23 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT23"); + state->u.f0.fld.can_fa1r.fact24 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT24"); + state->u.f0.fld.can_fa1r.fact25 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT25"); + state->u.f0.fld.can_fa1r.fact26 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT26"); + state->u.f0.fld.can_fa1r.fact27 = cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT27"); + + // F0R1 bitfields. + state->u.f0.fld.f0r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB0"); + state->u.f0.fld.f0r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB1"); + state->u.f0.fld.f0r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB2"); + state->u.f0.fld.f0r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB3"); + state->u.f0.fld.f0r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB4"); + state->u.f0.fld.f0r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB5"); + state->u.f0.fld.f0r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB6"); + state->u.f0.fld.f0r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB7"); + state->u.f0.fld.f0r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB8"); + state->u.f0.fld.f0r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB9"); + state->u.f0.fld.f0r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB10"); + state->u.f0.fld.f0r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB11"); + state->u.f0.fld.f0r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB12"); + state->u.f0.fld.f0r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB13"); + state->u.f0.fld.f0r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB14"); + state->u.f0.fld.f0r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB15"); + state->u.f0.fld.f0r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB16"); + state->u.f0.fld.f0r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB17"); + state->u.f0.fld.f0r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB18"); + state->u.f0.fld.f0r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB19"); + state->u.f0.fld.f0r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB20"); + state->u.f0.fld.f0r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB21"); + state->u.f0.fld.f0r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB22"); + state->u.f0.fld.f0r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB23"); + state->u.f0.fld.f0r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB24"); + state->u.f0.fld.f0r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB25"); + state->u.f0.fld.f0r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB26"); + state->u.f0.fld.f0r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB27"); + state->u.f0.fld.f0r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB28"); + state->u.f0.fld.f0r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB29"); + state->u.f0.fld.f0r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB30"); + state->u.f0.fld.f0r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB31"); + + // F0R2 bitfields. + state->u.f0.fld.f0r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB0"); + state->u.f0.fld.f0r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB1"); + state->u.f0.fld.f0r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB2"); + state->u.f0.fld.f0r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB3"); + state->u.f0.fld.f0r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB4"); + state->u.f0.fld.f0r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB5"); + state->u.f0.fld.f0r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB6"); + state->u.f0.fld.f0r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB7"); + state->u.f0.fld.f0r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB8"); + state->u.f0.fld.f0r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB9"); + state->u.f0.fld.f0r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB10"); + state->u.f0.fld.f0r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB11"); + state->u.f0.fld.f0r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB12"); + state->u.f0.fld.f0r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB13"); + state->u.f0.fld.f0r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB14"); + state->u.f0.fld.f0r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB15"); + state->u.f0.fld.f0r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB16"); + state->u.f0.fld.f0r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB17"); + state->u.f0.fld.f0r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB18"); + state->u.f0.fld.f0r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB19"); + state->u.f0.fld.f0r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB20"); + state->u.f0.fld.f0r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB21"); + state->u.f0.fld.f0r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB22"); + state->u.f0.fld.f0r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB23"); + state->u.f0.fld.f0r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB24"); + state->u.f0.fld.f0r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB25"); + state->u.f0.fld.f0r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB26"); + state->u.f0.fld.f0r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB27"); + state->u.f0.fld.f0r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB28"); + state->u.f0.fld.f0r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB29"); + state->u.f0.fld.f0r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB30"); + state->u.f0.fld.f0r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB31"); + + // F1R1 bitfields. + state->u.f0.fld.f1r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB0"); + state->u.f0.fld.f1r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB1"); + state->u.f0.fld.f1r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB2"); + state->u.f0.fld.f1r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB3"); + state->u.f0.fld.f1r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB4"); + state->u.f0.fld.f1r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB5"); + state->u.f0.fld.f1r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB6"); + state->u.f0.fld.f1r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB7"); + state->u.f0.fld.f1r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB8"); + state->u.f0.fld.f1r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB9"); + state->u.f0.fld.f1r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB10"); + state->u.f0.fld.f1r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB11"); + state->u.f0.fld.f1r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB12"); + state->u.f0.fld.f1r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB13"); + state->u.f0.fld.f1r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB14"); + state->u.f0.fld.f1r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB15"); + state->u.f0.fld.f1r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB16"); + state->u.f0.fld.f1r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB17"); + state->u.f0.fld.f1r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB18"); + state->u.f0.fld.f1r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB19"); + state->u.f0.fld.f1r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB20"); + state->u.f0.fld.f1r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB21"); + state->u.f0.fld.f1r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB22"); + state->u.f0.fld.f1r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB23"); + state->u.f0.fld.f1r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB24"); + state->u.f0.fld.f1r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB25"); + state->u.f0.fld.f1r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB26"); + state->u.f0.fld.f1r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB27"); + state->u.f0.fld.f1r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB28"); + state->u.f0.fld.f1r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB29"); + state->u.f0.fld.f1r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB30"); + state->u.f0.fld.f1r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB31"); + + // F1R2 bitfields. + state->u.f0.fld.f1r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB0"); + state->u.f0.fld.f1r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB1"); + state->u.f0.fld.f1r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB2"); + state->u.f0.fld.f1r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB3"); + state->u.f0.fld.f1r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB4"); + state->u.f0.fld.f1r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB5"); + state->u.f0.fld.f1r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB6"); + state->u.f0.fld.f1r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB7"); + state->u.f0.fld.f1r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB8"); + state->u.f0.fld.f1r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB9"); + state->u.f0.fld.f1r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB10"); + state->u.f0.fld.f1r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB11"); + state->u.f0.fld.f1r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB12"); + state->u.f0.fld.f1r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB13"); + state->u.f0.fld.f1r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB14"); + state->u.f0.fld.f1r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB15"); + state->u.f0.fld.f1r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB16"); + state->u.f0.fld.f1r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB17"); + state->u.f0.fld.f1r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB18"); + state->u.f0.fld.f1r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB19"); + state->u.f0.fld.f1r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB20"); + state->u.f0.fld.f1r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB21"); + state->u.f0.fld.f1r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB22"); + state->u.f0.fld.f1r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB23"); + state->u.f0.fld.f1r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB24"); + state->u.f0.fld.f1r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB25"); + state->u.f0.fld.f1r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB26"); + state->u.f0.fld.f1r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB27"); + state->u.f0.fld.f1r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB28"); + state->u.f0.fld.f1r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB29"); + state->u.f0.fld.f1r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB30"); + state->u.f0.fld.f1r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB31"); + + // F2R1 bitfields. + state->u.f0.fld.f2r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB0"); + state->u.f0.fld.f2r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB1"); + state->u.f0.fld.f2r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB2"); + state->u.f0.fld.f2r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB3"); + state->u.f0.fld.f2r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB4"); + state->u.f0.fld.f2r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB5"); + state->u.f0.fld.f2r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB6"); + state->u.f0.fld.f2r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB7"); + state->u.f0.fld.f2r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB8"); + state->u.f0.fld.f2r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB9"); + state->u.f0.fld.f2r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB10"); + state->u.f0.fld.f2r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB11"); + state->u.f0.fld.f2r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB12"); + state->u.f0.fld.f2r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB13"); + state->u.f0.fld.f2r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB14"); + state->u.f0.fld.f2r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB15"); + state->u.f0.fld.f2r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB16"); + state->u.f0.fld.f2r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB17"); + state->u.f0.fld.f2r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB18"); + state->u.f0.fld.f2r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB19"); + state->u.f0.fld.f2r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB20"); + state->u.f0.fld.f2r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB21"); + state->u.f0.fld.f2r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB22"); + state->u.f0.fld.f2r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB23"); + state->u.f0.fld.f2r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB24"); + state->u.f0.fld.f2r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB25"); + state->u.f0.fld.f2r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB26"); + state->u.f0.fld.f2r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB27"); + state->u.f0.fld.f2r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB28"); + state->u.f0.fld.f2r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB29"); + state->u.f0.fld.f2r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB30"); + state->u.f0.fld.f2r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB31"); + + // F2R2 bitfields. + state->u.f0.fld.f2r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB0"); + state->u.f0.fld.f2r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB1"); + state->u.f0.fld.f2r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB2"); + state->u.f0.fld.f2r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB3"); + state->u.f0.fld.f2r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB4"); + state->u.f0.fld.f2r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB5"); + state->u.f0.fld.f2r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB6"); + state->u.f0.fld.f2r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB7"); + state->u.f0.fld.f2r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB8"); + state->u.f0.fld.f2r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB9"); + state->u.f0.fld.f2r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB10"); + state->u.f0.fld.f2r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB11"); + state->u.f0.fld.f2r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB12"); + state->u.f0.fld.f2r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB13"); + state->u.f0.fld.f2r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB14"); + state->u.f0.fld.f2r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB15"); + state->u.f0.fld.f2r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB16"); + state->u.f0.fld.f2r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB17"); + state->u.f0.fld.f2r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB18"); + state->u.f0.fld.f2r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB19"); + state->u.f0.fld.f2r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB20"); + state->u.f0.fld.f2r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB21"); + state->u.f0.fld.f2r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB22"); + state->u.f0.fld.f2r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB23"); + state->u.f0.fld.f2r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB24"); + state->u.f0.fld.f2r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB25"); + state->u.f0.fld.f2r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB26"); + state->u.f0.fld.f2r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB27"); + state->u.f0.fld.f2r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB28"); + state->u.f0.fld.f2r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB29"); + state->u.f0.fld.f2r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB30"); + state->u.f0.fld.f2r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB31"); + + // F3R1 bitfields. + state->u.f0.fld.f3r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB0"); + state->u.f0.fld.f3r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB1"); + state->u.f0.fld.f3r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB2"); + state->u.f0.fld.f3r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB3"); + state->u.f0.fld.f3r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB4"); + state->u.f0.fld.f3r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB5"); + state->u.f0.fld.f3r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB6"); + state->u.f0.fld.f3r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB7"); + state->u.f0.fld.f3r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB8"); + state->u.f0.fld.f3r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB9"); + state->u.f0.fld.f3r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB10"); + state->u.f0.fld.f3r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB11"); + state->u.f0.fld.f3r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB12"); + state->u.f0.fld.f3r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB13"); + state->u.f0.fld.f3r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB14"); + state->u.f0.fld.f3r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB15"); + state->u.f0.fld.f3r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB16"); + state->u.f0.fld.f3r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB17"); + state->u.f0.fld.f3r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB18"); + state->u.f0.fld.f3r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB19"); + state->u.f0.fld.f3r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB20"); + state->u.f0.fld.f3r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB21"); + state->u.f0.fld.f3r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB22"); + state->u.f0.fld.f3r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB23"); + state->u.f0.fld.f3r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB24"); + state->u.f0.fld.f3r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB25"); + state->u.f0.fld.f3r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB26"); + state->u.f0.fld.f3r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB27"); + state->u.f0.fld.f3r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB28"); + state->u.f0.fld.f3r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB29"); + state->u.f0.fld.f3r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB30"); + state->u.f0.fld.f3r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB31"); + + // F3R2 bitfields. + state->u.f0.fld.f3r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB0"); + state->u.f0.fld.f3r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB1"); + state->u.f0.fld.f3r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB2"); + state->u.f0.fld.f3r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB3"); + state->u.f0.fld.f3r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB4"); + state->u.f0.fld.f3r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB5"); + state->u.f0.fld.f3r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB6"); + state->u.f0.fld.f3r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB7"); + state->u.f0.fld.f3r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB8"); + state->u.f0.fld.f3r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB9"); + state->u.f0.fld.f3r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB10"); + state->u.f0.fld.f3r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB11"); + state->u.f0.fld.f3r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB12"); + state->u.f0.fld.f3r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB13"); + state->u.f0.fld.f3r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB14"); + state->u.f0.fld.f3r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB15"); + state->u.f0.fld.f3r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB16"); + state->u.f0.fld.f3r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB17"); + state->u.f0.fld.f3r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB18"); + state->u.f0.fld.f3r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB19"); + state->u.f0.fld.f3r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB20"); + state->u.f0.fld.f3r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB21"); + state->u.f0.fld.f3r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB22"); + state->u.f0.fld.f3r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB23"); + state->u.f0.fld.f3r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB24"); + state->u.f0.fld.f3r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB25"); + state->u.f0.fld.f3r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB26"); + state->u.f0.fld.f3r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB27"); + state->u.f0.fld.f3r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB28"); + state->u.f0.fld.f3r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB29"); + state->u.f0.fld.f3r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB30"); + state->u.f0.fld.f3r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB31"); + + // F4R1 bitfields. + state->u.f0.fld.f4r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB0"); + state->u.f0.fld.f4r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB1"); + state->u.f0.fld.f4r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB2"); + state->u.f0.fld.f4r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB3"); + state->u.f0.fld.f4r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB4"); + state->u.f0.fld.f4r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB5"); + state->u.f0.fld.f4r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB6"); + state->u.f0.fld.f4r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB7"); + state->u.f0.fld.f4r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB8"); + state->u.f0.fld.f4r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB9"); + state->u.f0.fld.f4r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB10"); + state->u.f0.fld.f4r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB11"); + state->u.f0.fld.f4r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB12"); + state->u.f0.fld.f4r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB13"); + state->u.f0.fld.f4r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB14"); + state->u.f0.fld.f4r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB15"); + state->u.f0.fld.f4r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB16"); + state->u.f0.fld.f4r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB17"); + state->u.f0.fld.f4r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB18"); + state->u.f0.fld.f4r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB19"); + state->u.f0.fld.f4r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB20"); + state->u.f0.fld.f4r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB21"); + state->u.f0.fld.f4r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB22"); + state->u.f0.fld.f4r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB23"); + state->u.f0.fld.f4r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB24"); + state->u.f0.fld.f4r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB25"); + state->u.f0.fld.f4r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB26"); + state->u.f0.fld.f4r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB27"); + state->u.f0.fld.f4r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB28"); + state->u.f0.fld.f4r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB29"); + state->u.f0.fld.f4r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB30"); + state->u.f0.fld.f4r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB31"); + + // F4R2 bitfields. + state->u.f0.fld.f4r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB0"); + state->u.f0.fld.f4r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB1"); + state->u.f0.fld.f4r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB2"); + state->u.f0.fld.f4r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB3"); + state->u.f0.fld.f4r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB4"); + state->u.f0.fld.f4r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB5"); + state->u.f0.fld.f4r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB6"); + state->u.f0.fld.f4r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB7"); + state->u.f0.fld.f4r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB8"); + state->u.f0.fld.f4r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB9"); + state->u.f0.fld.f4r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB10"); + state->u.f0.fld.f4r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB11"); + state->u.f0.fld.f4r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB12"); + state->u.f0.fld.f4r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB13"); + state->u.f0.fld.f4r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB14"); + state->u.f0.fld.f4r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB15"); + state->u.f0.fld.f4r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB16"); + state->u.f0.fld.f4r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB17"); + state->u.f0.fld.f4r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB18"); + state->u.f0.fld.f4r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB19"); + state->u.f0.fld.f4r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB20"); + state->u.f0.fld.f4r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB21"); + state->u.f0.fld.f4r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB22"); + state->u.f0.fld.f4r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB23"); + state->u.f0.fld.f4r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB24"); + state->u.f0.fld.f4r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB25"); + state->u.f0.fld.f4r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB26"); + state->u.f0.fld.f4r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB27"); + state->u.f0.fld.f4r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB28"); + state->u.f0.fld.f4r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB29"); + state->u.f0.fld.f4r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB30"); + state->u.f0.fld.f4r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB31"); + + // F5R1 bitfields. + state->u.f0.fld.f5r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB0"); + state->u.f0.fld.f5r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB1"); + state->u.f0.fld.f5r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB2"); + state->u.f0.fld.f5r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB3"); + state->u.f0.fld.f5r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB4"); + state->u.f0.fld.f5r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB5"); + state->u.f0.fld.f5r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB6"); + state->u.f0.fld.f5r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB7"); + state->u.f0.fld.f5r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB8"); + state->u.f0.fld.f5r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB9"); + state->u.f0.fld.f5r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB10"); + state->u.f0.fld.f5r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB11"); + state->u.f0.fld.f5r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB12"); + state->u.f0.fld.f5r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB13"); + state->u.f0.fld.f5r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB14"); + state->u.f0.fld.f5r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB15"); + state->u.f0.fld.f5r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB16"); + state->u.f0.fld.f5r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB17"); + state->u.f0.fld.f5r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB18"); + state->u.f0.fld.f5r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB19"); + state->u.f0.fld.f5r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB20"); + state->u.f0.fld.f5r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB21"); + state->u.f0.fld.f5r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB22"); + state->u.f0.fld.f5r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB23"); + state->u.f0.fld.f5r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB24"); + state->u.f0.fld.f5r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB25"); + state->u.f0.fld.f5r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB26"); + state->u.f0.fld.f5r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB27"); + state->u.f0.fld.f5r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB28"); + state->u.f0.fld.f5r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB29"); + state->u.f0.fld.f5r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB30"); + state->u.f0.fld.f5r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB31"); + + // F5R2 bitfields. + state->u.f0.fld.f5r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB0"); + state->u.f0.fld.f5r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB1"); + state->u.f0.fld.f5r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB2"); + state->u.f0.fld.f5r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB3"); + state->u.f0.fld.f5r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB4"); + state->u.f0.fld.f5r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB5"); + state->u.f0.fld.f5r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB6"); + state->u.f0.fld.f5r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB7"); + state->u.f0.fld.f5r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB8"); + state->u.f0.fld.f5r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB9"); + state->u.f0.fld.f5r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB10"); + state->u.f0.fld.f5r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB11"); + state->u.f0.fld.f5r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB12"); + state->u.f0.fld.f5r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB13"); + state->u.f0.fld.f5r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB14"); + state->u.f0.fld.f5r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB15"); + state->u.f0.fld.f5r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB16"); + state->u.f0.fld.f5r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB17"); + state->u.f0.fld.f5r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB18"); + state->u.f0.fld.f5r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB19"); + state->u.f0.fld.f5r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB20"); + state->u.f0.fld.f5r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB21"); + state->u.f0.fld.f5r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB22"); + state->u.f0.fld.f5r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB23"); + state->u.f0.fld.f5r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB24"); + state->u.f0.fld.f5r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB25"); + state->u.f0.fld.f5r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB26"); + state->u.f0.fld.f5r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB27"); + state->u.f0.fld.f5r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB28"); + state->u.f0.fld.f5r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB29"); + state->u.f0.fld.f5r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB30"); + state->u.f0.fld.f5r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB31"); + + // F6R1 bitfields. + state->u.f0.fld.f6r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB0"); + state->u.f0.fld.f6r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB1"); + state->u.f0.fld.f6r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB2"); + state->u.f0.fld.f6r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB3"); + state->u.f0.fld.f6r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB4"); + state->u.f0.fld.f6r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB5"); + state->u.f0.fld.f6r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB6"); + state->u.f0.fld.f6r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB7"); + state->u.f0.fld.f6r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB8"); + state->u.f0.fld.f6r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB9"); + state->u.f0.fld.f6r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB10"); + state->u.f0.fld.f6r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB11"); + state->u.f0.fld.f6r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB12"); + state->u.f0.fld.f6r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB13"); + state->u.f0.fld.f6r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB14"); + state->u.f0.fld.f6r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB15"); + state->u.f0.fld.f6r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB16"); + state->u.f0.fld.f6r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB17"); + state->u.f0.fld.f6r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB18"); + state->u.f0.fld.f6r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB19"); + state->u.f0.fld.f6r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB20"); + state->u.f0.fld.f6r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB21"); + state->u.f0.fld.f6r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB22"); + state->u.f0.fld.f6r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB23"); + state->u.f0.fld.f6r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB24"); + state->u.f0.fld.f6r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB25"); + state->u.f0.fld.f6r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB26"); + state->u.f0.fld.f6r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB27"); + state->u.f0.fld.f6r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB28"); + state->u.f0.fld.f6r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB29"); + state->u.f0.fld.f6r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB30"); + state->u.f0.fld.f6r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB31"); + + // F6R2 bitfields. + state->u.f0.fld.f6r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB0"); + state->u.f0.fld.f6r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB1"); + state->u.f0.fld.f6r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB2"); + state->u.f0.fld.f6r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB3"); + state->u.f0.fld.f6r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB4"); + state->u.f0.fld.f6r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB5"); + state->u.f0.fld.f6r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB6"); + state->u.f0.fld.f6r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB7"); + state->u.f0.fld.f6r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB8"); + state->u.f0.fld.f6r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB9"); + state->u.f0.fld.f6r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB10"); + state->u.f0.fld.f6r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB11"); + state->u.f0.fld.f6r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB12"); + state->u.f0.fld.f6r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB13"); + state->u.f0.fld.f6r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB14"); + state->u.f0.fld.f6r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB15"); + state->u.f0.fld.f6r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB16"); + state->u.f0.fld.f6r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB17"); + state->u.f0.fld.f6r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB18"); + state->u.f0.fld.f6r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB19"); + state->u.f0.fld.f6r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB20"); + state->u.f0.fld.f6r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB21"); + state->u.f0.fld.f6r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB22"); + state->u.f0.fld.f6r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB23"); + state->u.f0.fld.f6r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB24"); + state->u.f0.fld.f6r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB25"); + state->u.f0.fld.f6r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB26"); + state->u.f0.fld.f6r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB27"); + state->u.f0.fld.f6r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB28"); + state->u.f0.fld.f6r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB29"); + state->u.f0.fld.f6r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB30"); + state->u.f0.fld.f6r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB31"); + + // F7R1 bitfields. + state->u.f0.fld.f7r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB0"); + state->u.f0.fld.f7r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB1"); + state->u.f0.fld.f7r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB2"); + state->u.f0.fld.f7r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB3"); + state->u.f0.fld.f7r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB4"); + state->u.f0.fld.f7r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB5"); + state->u.f0.fld.f7r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB6"); + state->u.f0.fld.f7r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB7"); + state->u.f0.fld.f7r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB8"); + state->u.f0.fld.f7r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB9"); + state->u.f0.fld.f7r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB10"); + state->u.f0.fld.f7r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB11"); + state->u.f0.fld.f7r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB12"); + state->u.f0.fld.f7r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB13"); + state->u.f0.fld.f7r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB14"); + state->u.f0.fld.f7r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB15"); + state->u.f0.fld.f7r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB16"); + state->u.f0.fld.f7r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB17"); + state->u.f0.fld.f7r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB18"); + state->u.f0.fld.f7r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB19"); + state->u.f0.fld.f7r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB20"); + state->u.f0.fld.f7r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB21"); + state->u.f0.fld.f7r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB22"); + state->u.f0.fld.f7r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB23"); + state->u.f0.fld.f7r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB24"); + state->u.f0.fld.f7r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB25"); + state->u.f0.fld.f7r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB26"); + state->u.f0.fld.f7r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB27"); + state->u.f0.fld.f7r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB28"); + state->u.f0.fld.f7r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB29"); + state->u.f0.fld.f7r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB30"); + state->u.f0.fld.f7r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB31"); + + // F7R2 bitfields. + state->u.f0.fld.f7r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB0"); + state->u.f0.fld.f7r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB1"); + state->u.f0.fld.f7r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB2"); + state->u.f0.fld.f7r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB3"); + state->u.f0.fld.f7r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB4"); + state->u.f0.fld.f7r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB5"); + state->u.f0.fld.f7r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB6"); + state->u.f0.fld.f7r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB7"); + state->u.f0.fld.f7r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB8"); + state->u.f0.fld.f7r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB9"); + state->u.f0.fld.f7r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB10"); + state->u.f0.fld.f7r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB11"); + state->u.f0.fld.f7r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB12"); + state->u.f0.fld.f7r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB13"); + state->u.f0.fld.f7r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB14"); + state->u.f0.fld.f7r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB15"); + state->u.f0.fld.f7r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB16"); + state->u.f0.fld.f7r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB17"); + state->u.f0.fld.f7r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB18"); + state->u.f0.fld.f7r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB19"); + state->u.f0.fld.f7r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB20"); + state->u.f0.fld.f7r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB21"); + state->u.f0.fld.f7r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB22"); + state->u.f0.fld.f7r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB23"); + state->u.f0.fld.f7r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB24"); + state->u.f0.fld.f7r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB25"); + state->u.f0.fld.f7r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB26"); + state->u.f0.fld.f7r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB27"); + state->u.f0.fld.f7r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB28"); + state->u.f0.fld.f7r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB29"); + state->u.f0.fld.f7r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB30"); + state->u.f0.fld.f7r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB31"); + + // F8R1 bitfields. + state->u.f0.fld.f8r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB0"); + state->u.f0.fld.f8r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB1"); + state->u.f0.fld.f8r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB2"); + state->u.f0.fld.f8r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB3"); + state->u.f0.fld.f8r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB4"); + state->u.f0.fld.f8r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB5"); + state->u.f0.fld.f8r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB6"); + state->u.f0.fld.f8r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB7"); + state->u.f0.fld.f8r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB8"); + state->u.f0.fld.f8r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB9"); + state->u.f0.fld.f8r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB10"); + state->u.f0.fld.f8r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB11"); + state->u.f0.fld.f8r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB12"); + state->u.f0.fld.f8r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB13"); + state->u.f0.fld.f8r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB14"); + state->u.f0.fld.f8r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB15"); + state->u.f0.fld.f8r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB16"); + state->u.f0.fld.f8r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB17"); + state->u.f0.fld.f8r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB18"); + state->u.f0.fld.f8r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB19"); + state->u.f0.fld.f8r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB20"); + state->u.f0.fld.f8r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB21"); + state->u.f0.fld.f8r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB22"); + state->u.f0.fld.f8r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB23"); + state->u.f0.fld.f8r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB24"); + state->u.f0.fld.f8r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB25"); + state->u.f0.fld.f8r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB26"); + state->u.f0.fld.f8r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB27"); + state->u.f0.fld.f8r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB28"); + state->u.f0.fld.f8r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB29"); + state->u.f0.fld.f8r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB30"); + state->u.f0.fld.f8r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB31"); + + // F8R2 bitfields. + state->u.f0.fld.f8r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB0"); + state->u.f0.fld.f8r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB1"); + state->u.f0.fld.f8r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB2"); + state->u.f0.fld.f8r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB3"); + state->u.f0.fld.f8r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB4"); + state->u.f0.fld.f8r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB5"); + state->u.f0.fld.f8r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB6"); + state->u.f0.fld.f8r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB7"); + state->u.f0.fld.f8r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB8"); + state->u.f0.fld.f8r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB9"); + state->u.f0.fld.f8r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB10"); + state->u.f0.fld.f8r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB11"); + state->u.f0.fld.f8r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB12"); + state->u.f0.fld.f8r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB13"); + state->u.f0.fld.f8r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB14"); + state->u.f0.fld.f8r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB15"); + state->u.f0.fld.f8r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB16"); + state->u.f0.fld.f8r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB17"); + state->u.f0.fld.f8r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB18"); + state->u.f0.fld.f8r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB19"); + state->u.f0.fld.f8r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB20"); + state->u.f0.fld.f8r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB21"); + state->u.f0.fld.f8r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB22"); + state->u.f0.fld.f8r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB23"); + state->u.f0.fld.f8r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB24"); + state->u.f0.fld.f8r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB25"); + state->u.f0.fld.f8r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB26"); + state->u.f0.fld.f8r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB27"); + state->u.f0.fld.f8r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB28"); + state->u.f0.fld.f8r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB29"); + state->u.f0.fld.f8r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB30"); + state->u.f0.fld.f8r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB31"); + + // F9R1 bitfields. + state->u.f0.fld.f9r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB0"); + state->u.f0.fld.f9r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB1"); + state->u.f0.fld.f9r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB2"); + state->u.f0.fld.f9r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB3"); + state->u.f0.fld.f9r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB4"); + state->u.f0.fld.f9r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB5"); + state->u.f0.fld.f9r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB6"); + state->u.f0.fld.f9r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB7"); + state->u.f0.fld.f9r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB8"); + state->u.f0.fld.f9r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB9"); + state->u.f0.fld.f9r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB10"); + state->u.f0.fld.f9r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB11"); + state->u.f0.fld.f9r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB12"); + state->u.f0.fld.f9r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB13"); + state->u.f0.fld.f9r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB14"); + state->u.f0.fld.f9r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB15"); + state->u.f0.fld.f9r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB16"); + state->u.f0.fld.f9r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB17"); + state->u.f0.fld.f9r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB18"); + state->u.f0.fld.f9r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB19"); + state->u.f0.fld.f9r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB20"); + state->u.f0.fld.f9r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB21"); + state->u.f0.fld.f9r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB22"); + state->u.f0.fld.f9r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB23"); + state->u.f0.fld.f9r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB24"); + state->u.f0.fld.f9r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB25"); + state->u.f0.fld.f9r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB26"); + state->u.f0.fld.f9r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB27"); + state->u.f0.fld.f9r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB28"); + state->u.f0.fld.f9r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB29"); + state->u.f0.fld.f9r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB30"); + state->u.f0.fld.f9r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB31"); + + // F9R2 bitfields. + state->u.f0.fld.f9r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB0"); + state->u.f0.fld.f9r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB1"); + state->u.f0.fld.f9r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB2"); + state->u.f0.fld.f9r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB3"); + state->u.f0.fld.f9r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB4"); + state->u.f0.fld.f9r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB5"); + state->u.f0.fld.f9r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB6"); + state->u.f0.fld.f9r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB7"); + state->u.f0.fld.f9r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB8"); + state->u.f0.fld.f9r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB9"); + state->u.f0.fld.f9r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB10"); + state->u.f0.fld.f9r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB11"); + state->u.f0.fld.f9r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB12"); + state->u.f0.fld.f9r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB13"); + state->u.f0.fld.f9r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB14"); + state->u.f0.fld.f9r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB15"); + state->u.f0.fld.f9r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB16"); + state->u.f0.fld.f9r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB17"); + state->u.f0.fld.f9r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB18"); + state->u.f0.fld.f9r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB19"); + state->u.f0.fld.f9r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB20"); + state->u.f0.fld.f9r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB21"); + state->u.f0.fld.f9r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB22"); + state->u.f0.fld.f9r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB23"); + state->u.f0.fld.f9r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB24"); + state->u.f0.fld.f9r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB25"); + state->u.f0.fld.f9r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB26"); + state->u.f0.fld.f9r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB27"); + state->u.f0.fld.f9r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB28"); + state->u.f0.fld.f9r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB29"); + state->u.f0.fld.f9r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB30"); + state->u.f0.fld.f9r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB31"); + + // F10R1 bitfields. + state->u.f0.fld.f10r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB0"); + state->u.f0.fld.f10r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB1"); + state->u.f0.fld.f10r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB2"); + state->u.f0.fld.f10r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB3"); + state->u.f0.fld.f10r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB4"); + state->u.f0.fld.f10r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB5"); + state->u.f0.fld.f10r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB6"); + state->u.f0.fld.f10r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB7"); + state->u.f0.fld.f10r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB8"); + state->u.f0.fld.f10r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB9"); + state->u.f0.fld.f10r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB10"); + state->u.f0.fld.f10r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB11"); + state->u.f0.fld.f10r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB12"); + state->u.f0.fld.f10r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB13"); + state->u.f0.fld.f10r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB14"); + state->u.f0.fld.f10r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB15"); + state->u.f0.fld.f10r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB16"); + state->u.f0.fld.f10r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB17"); + state->u.f0.fld.f10r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB18"); + state->u.f0.fld.f10r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB19"); + state->u.f0.fld.f10r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB20"); + state->u.f0.fld.f10r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB21"); + state->u.f0.fld.f10r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB22"); + state->u.f0.fld.f10r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB23"); + state->u.f0.fld.f10r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB24"); + state->u.f0.fld.f10r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB25"); + state->u.f0.fld.f10r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB26"); + state->u.f0.fld.f10r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB27"); + state->u.f0.fld.f10r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB28"); + state->u.f0.fld.f10r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB29"); + state->u.f0.fld.f10r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB30"); + state->u.f0.fld.f10r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB31"); + + // F10R2 bitfields. + state->u.f0.fld.f10r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB0"); + state->u.f0.fld.f10r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB1"); + state->u.f0.fld.f10r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB2"); + state->u.f0.fld.f10r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB3"); + state->u.f0.fld.f10r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB4"); + state->u.f0.fld.f10r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB5"); + state->u.f0.fld.f10r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB6"); + state->u.f0.fld.f10r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB7"); + state->u.f0.fld.f10r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB8"); + state->u.f0.fld.f10r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB9"); + state->u.f0.fld.f10r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB10"); + state->u.f0.fld.f10r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB11"); + state->u.f0.fld.f10r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB12"); + state->u.f0.fld.f10r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB13"); + state->u.f0.fld.f10r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB14"); + state->u.f0.fld.f10r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB15"); + state->u.f0.fld.f10r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB16"); + state->u.f0.fld.f10r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB17"); + state->u.f0.fld.f10r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB18"); + state->u.f0.fld.f10r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB19"); + state->u.f0.fld.f10r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB20"); + state->u.f0.fld.f10r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB21"); + state->u.f0.fld.f10r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB22"); + state->u.f0.fld.f10r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB23"); + state->u.f0.fld.f10r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB24"); + state->u.f0.fld.f10r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB25"); + state->u.f0.fld.f10r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB26"); + state->u.f0.fld.f10r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB27"); + state->u.f0.fld.f10r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB28"); + state->u.f0.fld.f10r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB29"); + state->u.f0.fld.f10r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB30"); + state->u.f0.fld.f10r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB31"); + + // F11R1 bitfields. + state->u.f0.fld.f11r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB0"); + state->u.f0.fld.f11r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB1"); + state->u.f0.fld.f11r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB2"); + state->u.f0.fld.f11r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB3"); + state->u.f0.fld.f11r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB4"); + state->u.f0.fld.f11r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB5"); + state->u.f0.fld.f11r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB6"); + state->u.f0.fld.f11r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB7"); + state->u.f0.fld.f11r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB8"); + state->u.f0.fld.f11r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB9"); + state->u.f0.fld.f11r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB10"); + state->u.f0.fld.f11r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB11"); + state->u.f0.fld.f11r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB12"); + state->u.f0.fld.f11r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB13"); + state->u.f0.fld.f11r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB14"); + state->u.f0.fld.f11r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB15"); + state->u.f0.fld.f11r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB16"); + state->u.f0.fld.f11r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB17"); + state->u.f0.fld.f11r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB18"); + state->u.f0.fld.f11r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB19"); + state->u.f0.fld.f11r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB20"); + state->u.f0.fld.f11r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB21"); + state->u.f0.fld.f11r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB22"); + state->u.f0.fld.f11r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB23"); + state->u.f0.fld.f11r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB24"); + state->u.f0.fld.f11r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB25"); + state->u.f0.fld.f11r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB26"); + state->u.f0.fld.f11r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB27"); + state->u.f0.fld.f11r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB28"); + state->u.f0.fld.f11r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB29"); + state->u.f0.fld.f11r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB30"); + state->u.f0.fld.f11r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB31"); + + // F11R2 bitfields. + state->u.f0.fld.f11r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB0"); + state->u.f0.fld.f11r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB1"); + state->u.f0.fld.f11r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB2"); + state->u.f0.fld.f11r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB3"); + state->u.f0.fld.f11r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB4"); + state->u.f0.fld.f11r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB5"); + state->u.f0.fld.f11r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB6"); + state->u.f0.fld.f11r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB7"); + state->u.f0.fld.f11r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB8"); + state->u.f0.fld.f11r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB9"); + state->u.f0.fld.f11r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB10"); + state->u.f0.fld.f11r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB11"); + state->u.f0.fld.f11r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB12"); + state->u.f0.fld.f11r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB13"); + state->u.f0.fld.f11r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB14"); + state->u.f0.fld.f11r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB15"); + state->u.f0.fld.f11r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB16"); + state->u.f0.fld.f11r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB17"); + state->u.f0.fld.f11r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB18"); + state->u.f0.fld.f11r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB19"); + state->u.f0.fld.f11r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB20"); + state->u.f0.fld.f11r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB21"); + state->u.f0.fld.f11r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB22"); + state->u.f0.fld.f11r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB23"); + state->u.f0.fld.f11r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB24"); + state->u.f0.fld.f11r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB25"); + state->u.f0.fld.f11r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB26"); + state->u.f0.fld.f11r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB27"); + state->u.f0.fld.f11r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB28"); + state->u.f0.fld.f11r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB29"); + state->u.f0.fld.f11r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB30"); + state->u.f0.fld.f11r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB31"); + + // F12R1 bitfields. + state->u.f0.fld.f12r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB0"); + state->u.f0.fld.f12r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB1"); + state->u.f0.fld.f12r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB2"); + state->u.f0.fld.f12r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB3"); + state->u.f0.fld.f12r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB4"); + state->u.f0.fld.f12r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB5"); + state->u.f0.fld.f12r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB6"); + state->u.f0.fld.f12r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB7"); + state->u.f0.fld.f12r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB8"); + state->u.f0.fld.f12r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB9"); + state->u.f0.fld.f12r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB10"); + state->u.f0.fld.f12r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB11"); + state->u.f0.fld.f12r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB12"); + state->u.f0.fld.f12r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB13"); + state->u.f0.fld.f12r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB14"); + state->u.f0.fld.f12r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB15"); + state->u.f0.fld.f12r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB16"); + state->u.f0.fld.f12r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB17"); + state->u.f0.fld.f12r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB18"); + state->u.f0.fld.f12r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB19"); + state->u.f0.fld.f12r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB20"); + state->u.f0.fld.f12r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB21"); + state->u.f0.fld.f12r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB22"); + state->u.f0.fld.f12r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB23"); + state->u.f0.fld.f12r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB24"); + state->u.f0.fld.f12r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB25"); + state->u.f0.fld.f12r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB26"); + state->u.f0.fld.f12r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB27"); + state->u.f0.fld.f12r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB28"); + state->u.f0.fld.f12r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB29"); + state->u.f0.fld.f12r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB30"); + state->u.f0.fld.f12r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB31"); + + // F12R2 bitfields. + state->u.f0.fld.f12r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB0"); + state->u.f0.fld.f12r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB1"); + state->u.f0.fld.f12r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB2"); + state->u.f0.fld.f12r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB3"); + state->u.f0.fld.f12r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB4"); + state->u.f0.fld.f12r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB5"); + state->u.f0.fld.f12r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB6"); + state->u.f0.fld.f12r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB7"); + state->u.f0.fld.f12r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB8"); + state->u.f0.fld.f12r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB9"); + state->u.f0.fld.f12r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB10"); + state->u.f0.fld.f12r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB11"); + state->u.f0.fld.f12r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB12"); + state->u.f0.fld.f12r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB13"); + state->u.f0.fld.f12r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB14"); + state->u.f0.fld.f12r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB15"); + state->u.f0.fld.f12r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB16"); + state->u.f0.fld.f12r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB17"); + state->u.f0.fld.f12r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB18"); + state->u.f0.fld.f12r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB19"); + state->u.f0.fld.f12r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB20"); + state->u.f0.fld.f12r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB21"); + state->u.f0.fld.f12r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB22"); + state->u.f0.fld.f12r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB23"); + state->u.f0.fld.f12r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB24"); + state->u.f0.fld.f12r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB25"); + state->u.f0.fld.f12r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB26"); + state->u.f0.fld.f12r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB27"); + state->u.f0.fld.f12r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB28"); + state->u.f0.fld.f12r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB29"); + state->u.f0.fld.f12r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB30"); + state->u.f0.fld.f12r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB31"); + + // F13R1 bitfields. + state->u.f0.fld.f13r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB0"); + state->u.f0.fld.f13r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB1"); + state->u.f0.fld.f13r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB2"); + state->u.f0.fld.f13r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB3"); + state->u.f0.fld.f13r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB4"); + state->u.f0.fld.f13r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB5"); + state->u.f0.fld.f13r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB6"); + state->u.f0.fld.f13r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB7"); + state->u.f0.fld.f13r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB8"); + state->u.f0.fld.f13r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB9"); + state->u.f0.fld.f13r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB10"); + state->u.f0.fld.f13r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB11"); + state->u.f0.fld.f13r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB12"); + state->u.f0.fld.f13r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB13"); + state->u.f0.fld.f13r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB14"); + state->u.f0.fld.f13r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB15"); + state->u.f0.fld.f13r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB16"); + state->u.f0.fld.f13r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB17"); + state->u.f0.fld.f13r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB18"); + state->u.f0.fld.f13r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB19"); + state->u.f0.fld.f13r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB20"); + state->u.f0.fld.f13r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB21"); + state->u.f0.fld.f13r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB22"); + state->u.f0.fld.f13r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB23"); + state->u.f0.fld.f13r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB24"); + state->u.f0.fld.f13r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB25"); + state->u.f0.fld.f13r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB26"); + state->u.f0.fld.f13r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB27"); + state->u.f0.fld.f13r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB28"); + state->u.f0.fld.f13r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB29"); + state->u.f0.fld.f13r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB30"); + state->u.f0.fld.f13r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB31"); + + // F13R2 bitfields. + state->u.f0.fld.f13r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB0"); + state->u.f0.fld.f13r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB1"); + state->u.f0.fld.f13r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB2"); + state->u.f0.fld.f13r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB3"); + state->u.f0.fld.f13r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB4"); + state->u.f0.fld.f13r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB5"); + state->u.f0.fld.f13r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB6"); + state->u.f0.fld.f13r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB7"); + state->u.f0.fld.f13r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB8"); + state->u.f0.fld.f13r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB9"); + state->u.f0.fld.f13r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB10"); + state->u.f0.fld.f13r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB11"); + state->u.f0.fld.f13r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB12"); + state->u.f0.fld.f13r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB13"); + state->u.f0.fld.f13r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB14"); + state->u.f0.fld.f13r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB15"); + state->u.f0.fld.f13r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB16"); + state->u.f0.fld.f13r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB17"); + state->u.f0.fld.f13r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB18"); + state->u.f0.fld.f13r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB19"); + state->u.f0.fld.f13r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB20"); + state->u.f0.fld.f13r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB21"); + state->u.f0.fld.f13r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB22"); + state->u.f0.fld.f13r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB23"); + state->u.f0.fld.f13r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB24"); + state->u.f0.fld.f13r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB25"); + state->u.f0.fld.f13r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB26"); + state->u.f0.fld.f13r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB27"); + state->u.f0.fld.f13r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB28"); + state->u.f0.fld.f13r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB29"); + state->u.f0.fld.f13r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB30"); + state->u.f0.fld.f13r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB31"); + + // F14R1 bitfields. + state->u.f0.fld.f14r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB0"); + state->u.f0.fld.f14r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB1"); + state->u.f0.fld.f14r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB2"); + state->u.f0.fld.f14r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB3"); + state->u.f0.fld.f14r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB4"); + state->u.f0.fld.f14r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB5"); + state->u.f0.fld.f14r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB6"); + state->u.f0.fld.f14r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB7"); + state->u.f0.fld.f14r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB8"); + state->u.f0.fld.f14r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB9"); + state->u.f0.fld.f14r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB10"); + state->u.f0.fld.f14r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB11"); + state->u.f0.fld.f14r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB12"); + state->u.f0.fld.f14r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB13"); + state->u.f0.fld.f14r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB14"); + state->u.f0.fld.f14r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB15"); + state->u.f0.fld.f14r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB16"); + state->u.f0.fld.f14r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB17"); + state->u.f0.fld.f14r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB18"); + state->u.f0.fld.f14r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB19"); + state->u.f0.fld.f14r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB20"); + state->u.f0.fld.f14r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB21"); + state->u.f0.fld.f14r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB22"); + state->u.f0.fld.f14r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB23"); + state->u.f0.fld.f14r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB24"); + state->u.f0.fld.f14r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB25"); + state->u.f0.fld.f14r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB26"); + state->u.f0.fld.f14r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB27"); + state->u.f0.fld.f14r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB28"); + state->u.f0.fld.f14r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB29"); + state->u.f0.fld.f14r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB30"); + state->u.f0.fld.f14r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB31"); + + // F14R2 bitfields. + state->u.f0.fld.f14r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB0"); + state->u.f0.fld.f14r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB1"); + state->u.f0.fld.f14r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB2"); + state->u.f0.fld.f14r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB3"); + state->u.f0.fld.f14r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB4"); + state->u.f0.fld.f14r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB5"); + state->u.f0.fld.f14r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB6"); + state->u.f0.fld.f14r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB7"); + state->u.f0.fld.f14r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB8"); + state->u.f0.fld.f14r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB9"); + state->u.f0.fld.f14r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB10"); + state->u.f0.fld.f14r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB11"); + state->u.f0.fld.f14r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB12"); + state->u.f0.fld.f14r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB13"); + state->u.f0.fld.f14r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB14"); + state->u.f0.fld.f14r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB15"); + state->u.f0.fld.f14r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB16"); + state->u.f0.fld.f14r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB17"); + state->u.f0.fld.f14r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB18"); + state->u.f0.fld.f14r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB19"); + state->u.f0.fld.f14r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB20"); + state->u.f0.fld.f14r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB21"); + state->u.f0.fld.f14r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB22"); + state->u.f0.fld.f14r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB23"); + state->u.f0.fld.f14r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB24"); + state->u.f0.fld.f14r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB25"); + state->u.f0.fld.f14r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB26"); + state->u.f0.fld.f14r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB27"); + state->u.f0.fld.f14r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB28"); + state->u.f0.fld.f14r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB29"); + state->u.f0.fld.f14r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB30"); + state->u.f0.fld.f14r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB31"); + + // F15R1 bitfields. + state->u.f0.fld.f15r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB0"); + state->u.f0.fld.f15r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB1"); + state->u.f0.fld.f15r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB2"); + state->u.f0.fld.f15r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB3"); + state->u.f0.fld.f15r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB4"); + state->u.f0.fld.f15r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB5"); + state->u.f0.fld.f15r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB6"); + state->u.f0.fld.f15r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB7"); + state->u.f0.fld.f15r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB8"); + state->u.f0.fld.f15r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB9"); + state->u.f0.fld.f15r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB10"); + state->u.f0.fld.f15r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB11"); + state->u.f0.fld.f15r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB12"); + state->u.f0.fld.f15r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB13"); + state->u.f0.fld.f15r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB14"); + state->u.f0.fld.f15r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB15"); + state->u.f0.fld.f15r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB16"); + state->u.f0.fld.f15r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB17"); + state->u.f0.fld.f15r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB18"); + state->u.f0.fld.f15r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB19"); + state->u.f0.fld.f15r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB20"); + state->u.f0.fld.f15r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB21"); + state->u.f0.fld.f15r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB22"); + state->u.f0.fld.f15r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB23"); + state->u.f0.fld.f15r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB24"); + state->u.f0.fld.f15r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB25"); + state->u.f0.fld.f15r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB26"); + state->u.f0.fld.f15r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB27"); + state->u.f0.fld.f15r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB28"); + state->u.f0.fld.f15r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB29"); + state->u.f0.fld.f15r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB30"); + state->u.f0.fld.f15r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB31"); + + // F15R2 bitfields. + state->u.f0.fld.f15r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB0"); + state->u.f0.fld.f15r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB1"); + state->u.f0.fld.f15r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB2"); + state->u.f0.fld.f15r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB3"); + state->u.f0.fld.f15r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB4"); + state->u.f0.fld.f15r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB5"); + state->u.f0.fld.f15r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB6"); + state->u.f0.fld.f15r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB7"); + state->u.f0.fld.f15r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB8"); + state->u.f0.fld.f15r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB9"); + state->u.f0.fld.f15r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB10"); + state->u.f0.fld.f15r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB11"); + state->u.f0.fld.f15r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB12"); + state->u.f0.fld.f15r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB13"); + state->u.f0.fld.f15r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB14"); + state->u.f0.fld.f15r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB15"); + state->u.f0.fld.f15r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB16"); + state->u.f0.fld.f15r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB17"); + state->u.f0.fld.f15r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB18"); + state->u.f0.fld.f15r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB19"); + state->u.f0.fld.f15r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB20"); + state->u.f0.fld.f15r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB21"); + state->u.f0.fld.f15r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB22"); + state->u.f0.fld.f15r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB23"); + state->u.f0.fld.f15r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB24"); + state->u.f0.fld.f15r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB25"); + state->u.f0.fld.f15r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB26"); + state->u.f0.fld.f15r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB27"); + state->u.f0.fld.f15r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB28"); + state->u.f0.fld.f15r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB29"); + state->u.f0.fld.f15r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB30"); + state->u.f0.fld.f15r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB31"); + + // F16R1 bitfields. + state->u.f0.fld.f16r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB0"); + state->u.f0.fld.f16r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB1"); + state->u.f0.fld.f16r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB2"); + state->u.f0.fld.f16r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB3"); + state->u.f0.fld.f16r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB4"); + state->u.f0.fld.f16r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB5"); + state->u.f0.fld.f16r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB6"); + state->u.f0.fld.f16r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB7"); + state->u.f0.fld.f16r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB8"); + state->u.f0.fld.f16r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB9"); + state->u.f0.fld.f16r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB10"); + state->u.f0.fld.f16r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB11"); + state->u.f0.fld.f16r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB12"); + state->u.f0.fld.f16r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB13"); + state->u.f0.fld.f16r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB14"); + state->u.f0.fld.f16r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB15"); + state->u.f0.fld.f16r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB16"); + state->u.f0.fld.f16r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB17"); + state->u.f0.fld.f16r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB18"); + state->u.f0.fld.f16r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB19"); + state->u.f0.fld.f16r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB20"); + state->u.f0.fld.f16r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB21"); + state->u.f0.fld.f16r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB22"); + state->u.f0.fld.f16r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB23"); + state->u.f0.fld.f16r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB24"); + state->u.f0.fld.f16r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB25"); + state->u.f0.fld.f16r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB26"); + state->u.f0.fld.f16r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB27"); + state->u.f0.fld.f16r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB28"); + state->u.f0.fld.f16r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB29"); + state->u.f0.fld.f16r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB30"); + state->u.f0.fld.f16r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB31"); + + // F16R2 bitfields. + state->u.f0.fld.f16r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB0"); + state->u.f0.fld.f16r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB1"); + state->u.f0.fld.f16r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB2"); + state->u.f0.fld.f16r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB3"); + state->u.f0.fld.f16r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB4"); + state->u.f0.fld.f16r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB5"); + state->u.f0.fld.f16r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB6"); + state->u.f0.fld.f16r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB7"); + state->u.f0.fld.f16r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB8"); + state->u.f0.fld.f16r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB9"); + state->u.f0.fld.f16r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB10"); + state->u.f0.fld.f16r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB11"); + state->u.f0.fld.f16r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB12"); + state->u.f0.fld.f16r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB13"); + state->u.f0.fld.f16r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB14"); + state->u.f0.fld.f16r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB15"); + state->u.f0.fld.f16r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB16"); + state->u.f0.fld.f16r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB17"); + state->u.f0.fld.f16r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB18"); + state->u.f0.fld.f16r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB19"); + state->u.f0.fld.f16r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB20"); + state->u.f0.fld.f16r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB21"); + state->u.f0.fld.f16r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB22"); + state->u.f0.fld.f16r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB23"); + state->u.f0.fld.f16r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB24"); + state->u.f0.fld.f16r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB25"); + state->u.f0.fld.f16r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB26"); + state->u.f0.fld.f16r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB27"); + state->u.f0.fld.f16r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB28"); + state->u.f0.fld.f16r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB29"); + state->u.f0.fld.f16r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB30"); + state->u.f0.fld.f16r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB31"); + + // F17R1 bitfields. + state->u.f0.fld.f17r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB0"); + state->u.f0.fld.f17r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB1"); + state->u.f0.fld.f17r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB2"); + state->u.f0.fld.f17r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB3"); + state->u.f0.fld.f17r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB4"); + state->u.f0.fld.f17r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB5"); + state->u.f0.fld.f17r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB6"); + state->u.f0.fld.f17r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB7"); + state->u.f0.fld.f17r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB8"); + state->u.f0.fld.f17r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB9"); + state->u.f0.fld.f17r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB10"); + state->u.f0.fld.f17r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB11"); + state->u.f0.fld.f17r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB12"); + state->u.f0.fld.f17r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB13"); + state->u.f0.fld.f17r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB14"); + state->u.f0.fld.f17r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB15"); + state->u.f0.fld.f17r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB16"); + state->u.f0.fld.f17r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB17"); + state->u.f0.fld.f17r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB18"); + state->u.f0.fld.f17r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB19"); + state->u.f0.fld.f17r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB20"); + state->u.f0.fld.f17r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB21"); + state->u.f0.fld.f17r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB22"); + state->u.f0.fld.f17r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB23"); + state->u.f0.fld.f17r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB24"); + state->u.f0.fld.f17r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB25"); + state->u.f0.fld.f17r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB26"); + state->u.f0.fld.f17r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB27"); + state->u.f0.fld.f17r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB28"); + state->u.f0.fld.f17r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB29"); + state->u.f0.fld.f17r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB30"); + state->u.f0.fld.f17r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB31"); + + // F17R2 bitfields. + state->u.f0.fld.f17r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB0"); + state->u.f0.fld.f17r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB1"); + state->u.f0.fld.f17r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB2"); + state->u.f0.fld.f17r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB3"); + state->u.f0.fld.f17r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB4"); + state->u.f0.fld.f17r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB5"); + state->u.f0.fld.f17r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB6"); + state->u.f0.fld.f17r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB7"); + state->u.f0.fld.f17r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB8"); + state->u.f0.fld.f17r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB9"); + state->u.f0.fld.f17r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB10"); + state->u.f0.fld.f17r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB11"); + state->u.f0.fld.f17r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB12"); + state->u.f0.fld.f17r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB13"); + state->u.f0.fld.f17r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB14"); + state->u.f0.fld.f17r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB15"); + state->u.f0.fld.f17r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB16"); + state->u.f0.fld.f17r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB17"); + state->u.f0.fld.f17r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB18"); + state->u.f0.fld.f17r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB19"); + state->u.f0.fld.f17r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB20"); + state->u.f0.fld.f17r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB21"); + state->u.f0.fld.f17r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB22"); + state->u.f0.fld.f17r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB23"); + state->u.f0.fld.f17r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB24"); + state->u.f0.fld.f17r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB25"); + state->u.f0.fld.f17r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB26"); + state->u.f0.fld.f17r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB27"); + state->u.f0.fld.f17r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB28"); + state->u.f0.fld.f17r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB29"); + state->u.f0.fld.f17r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB30"); + state->u.f0.fld.f17r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB31"); + + // F18R1 bitfields. + state->u.f0.fld.f18r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB0"); + state->u.f0.fld.f18r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB1"); + state->u.f0.fld.f18r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB2"); + state->u.f0.fld.f18r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB3"); + state->u.f0.fld.f18r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB4"); + state->u.f0.fld.f18r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB5"); + state->u.f0.fld.f18r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB6"); + state->u.f0.fld.f18r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB7"); + state->u.f0.fld.f18r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB8"); + state->u.f0.fld.f18r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB9"); + state->u.f0.fld.f18r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB10"); + state->u.f0.fld.f18r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB11"); + state->u.f0.fld.f18r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB12"); + state->u.f0.fld.f18r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB13"); + state->u.f0.fld.f18r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB14"); + state->u.f0.fld.f18r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB15"); + state->u.f0.fld.f18r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB16"); + state->u.f0.fld.f18r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB17"); + state->u.f0.fld.f18r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB18"); + state->u.f0.fld.f18r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB19"); + state->u.f0.fld.f18r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB20"); + state->u.f0.fld.f18r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB21"); + state->u.f0.fld.f18r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB22"); + state->u.f0.fld.f18r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB23"); + state->u.f0.fld.f18r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB24"); + state->u.f0.fld.f18r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB25"); + state->u.f0.fld.f18r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB26"); + state->u.f0.fld.f18r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB27"); + state->u.f0.fld.f18r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB28"); + state->u.f0.fld.f18r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB29"); + state->u.f0.fld.f18r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB30"); + state->u.f0.fld.f18r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB31"); + + // F18R2 bitfields. + state->u.f0.fld.f18r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB0"); + state->u.f0.fld.f18r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB1"); + state->u.f0.fld.f18r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB2"); + state->u.f0.fld.f18r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB3"); + state->u.f0.fld.f18r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB4"); + state->u.f0.fld.f18r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB5"); + state->u.f0.fld.f18r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB6"); + state->u.f0.fld.f18r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB7"); + state->u.f0.fld.f18r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB8"); + state->u.f0.fld.f18r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB9"); + state->u.f0.fld.f18r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB10"); + state->u.f0.fld.f18r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB11"); + state->u.f0.fld.f18r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB12"); + state->u.f0.fld.f18r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB13"); + state->u.f0.fld.f18r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB14"); + state->u.f0.fld.f18r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB15"); + state->u.f0.fld.f18r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB16"); + state->u.f0.fld.f18r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB17"); + state->u.f0.fld.f18r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB18"); + state->u.f0.fld.f18r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB19"); + state->u.f0.fld.f18r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB20"); + state->u.f0.fld.f18r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB21"); + state->u.f0.fld.f18r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB22"); + state->u.f0.fld.f18r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB23"); + state->u.f0.fld.f18r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB24"); + state->u.f0.fld.f18r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB25"); + state->u.f0.fld.f18r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB26"); + state->u.f0.fld.f18r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB27"); + state->u.f0.fld.f18r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB28"); + state->u.f0.fld.f18r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB29"); + state->u.f0.fld.f18r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB30"); + state->u.f0.fld.f18r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB31"); + + // F19R1 bitfields. + state->u.f0.fld.f19r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB0"); + state->u.f0.fld.f19r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB1"); + state->u.f0.fld.f19r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB2"); + state->u.f0.fld.f19r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB3"); + state->u.f0.fld.f19r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB4"); + state->u.f0.fld.f19r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB5"); + state->u.f0.fld.f19r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB6"); + state->u.f0.fld.f19r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB7"); + state->u.f0.fld.f19r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB8"); + state->u.f0.fld.f19r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB9"); + state->u.f0.fld.f19r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB10"); + state->u.f0.fld.f19r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB11"); + state->u.f0.fld.f19r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB12"); + state->u.f0.fld.f19r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB13"); + state->u.f0.fld.f19r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB14"); + state->u.f0.fld.f19r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB15"); + state->u.f0.fld.f19r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB16"); + state->u.f0.fld.f19r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB17"); + state->u.f0.fld.f19r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB18"); + state->u.f0.fld.f19r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB19"); + state->u.f0.fld.f19r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB20"); + state->u.f0.fld.f19r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB21"); + state->u.f0.fld.f19r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB22"); + state->u.f0.fld.f19r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB23"); + state->u.f0.fld.f19r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB24"); + state->u.f0.fld.f19r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB25"); + state->u.f0.fld.f19r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB26"); + state->u.f0.fld.f19r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB27"); + state->u.f0.fld.f19r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB28"); + state->u.f0.fld.f19r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB29"); + state->u.f0.fld.f19r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB30"); + state->u.f0.fld.f19r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB31"); + + // F19R2 bitfields. + state->u.f0.fld.f19r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB0"); + state->u.f0.fld.f19r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB1"); + state->u.f0.fld.f19r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB2"); + state->u.f0.fld.f19r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB3"); + state->u.f0.fld.f19r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB4"); + state->u.f0.fld.f19r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB5"); + state->u.f0.fld.f19r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB6"); + state->u.f0.fld.f19r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB7"); + state->u.f0.fld.f19r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB8"); + state->u.f0.fld.f19r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB9"); + state->u.f0.fld.f19r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB10"); + state->u.f0.fld.f19r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB11"); + state->u.f0.fld.f19r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB12"); + state->u.f0.fld.f19r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB13"); + state->u.f0.fld.f19r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB14"); + state->u.f0.fld.f19r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB15"); + state->u.f0.fld.f19r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB16"); + state->u.f0.fld.f19r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB17"); + state->u.f0.fld.f19r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB18"); + state->u.f0.fld.f19r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB19"); + state->u.f0.fld.f19r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB20"); + state->u.f0.fld.f19r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB21"); + state->u.f0.fld.f19r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB22"); + state->u.f0.fld.f19r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB23"); + state->u.f0.fld.f19r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB24"); + state->u.f0.fld.f19r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB25"); + state->u.f0.fld.f19r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB26"); + state->u.f0.fld.f19r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB27"); + state->u.f0.fld.f19r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB28"); + state->u.f0.fld.f19r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB29"); + state->u.f0.fld.f19r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB30"); + state->u.f0.fld.f19r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB31"); + + // F20R1 bitfields. + state->u.f0.fld.f20r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB0"); + state->u.f0.fld.f20r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB1"); + state->u.f0.fld.f20r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB2"); + state->u.f0.fld.f20r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB3"); + state->u.f0.fld.f20r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB4"); + state->u.f0.fld.f20r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB5"); + state->u.f0.fld.f20r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB6"); + state->u.f0.fld.f20r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB7"); + state->u.f0.fld.f20r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB8"); + state->u.f0.fld.f20r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB9"); + state->u.f0.fld.f20r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB10"); + state->u.f0.fld.f20r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB11"); + state->u.f0.fld.f20r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB12"); + state->u.f0.fld.f20r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB13"); + state->u.f0.fld.f20r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB14"); + state->u.f0.fld.f20r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB15"); + state->u.f0.fld.f20r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB16"); + state->u.f0.fld.f20r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB17"); + state->u.f0.fld.f20r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB18"); + state->u.f0.fld.f20r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB19"); + state->u.f0.fld.f20r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB20"); + state->u.f0.fld.f20r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB21"); + state->u.f0.fld.f20r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB22"); + state->u.f0.fld.f20r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB23"); + state->u.f0.fld.f20r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB24"); + state->u.f0.fld.f20r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB25"); + state->u.f0.fld.f20r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB26"); + state->u.f0.fld.f20r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB27"); + state->u.f0.fld.f20r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB28"); + state->u.f0.fld.f20r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB29"); + state->u.f0.fld.f20r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB30"); + state->u.f0.fld.f20r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB31"); + + // F20R2 bitfields. + state->u.f0.fld.f20r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB0"); + state->u.f0.fld.f20r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB1"); + state->u.f0.fld.f20r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB2"); + state->u.f0.fld.f20r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB3"); + state->u.f0.fld.f20r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB4"); + state->u.f0.fld.f20r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB5"); + state->u.f0.fld.f20r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB6"); + state->u.f0.fld.f20r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB7"); + state->u.f0.fld.f20r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB8"); + state->u.f0.fld.f20r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB9"); + state->u.f0.fld.f20r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB10"); + state->u.f0.fld.f20r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB11"); + state->u.f0.fld.f20r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB12"); + state->u.f0.fld.f20r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB13"); + state->u.f0.fld.f20r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB14"); + state->u.f0.fld.f20r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB15"); + state->u.f0.fld.f20r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB16"); + state->u.f0.fld.f20r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB17"); + state->u.f0.fld.f20r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB18"); + state->u.f0.fld.f20r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB19"); + state->u.f0.fld.f20r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB20"); + state->u.f0.fld.f20r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB21"); + state->u.f0.fld.f20r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB22"); + state->u.f0.fld.f20r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB23"); + state->u.f0.fld.f20r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB24"); + state->u.f0.fld.f20r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB25"); + state->u.f0.fld.f20r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB26"); + state->u.f0.fld.f20r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB27"); + state->u.f0.fld.f20r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB28"); + state->u.f0.fld.f20r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB29"); + state->u.f0.fld.f20r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB30"); + state->u.f0.fld.f20r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB31"); + + // F21R1 bitfields. + state->u.f0.fld.f21r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB0"); + state->u.f0.fld.f21r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB1"); + state->u.f0.fld.f21r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB2"); + state->u.f0.fld.f21r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB3"); + state->u.f0.fld.f21r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB4"); + state->u.f0.fld.f21r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB5"); + state->u.f0.fld.f21r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB6"); + state->u.f0.fld.f21r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB7"); + state->u.f0.fld.f21r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB8"); + state->u.f0.fld.f21r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB9"); + state->u.f0.fld.f21r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB10"); + state->u.f0.fld.f21r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB11"); + state->u.f0.fld.f21r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB12"); + state->u.f0.fld.f21r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB13"); + state->u.f0.fld.f21r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB14"); + state->u.f0.fld.f21r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB15"); + state->u.f0.fld.f21r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB16"); + state->u.f0.fld.f21r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB17"); + state->u.f0.fld.f21r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB18"); + state->u.f0.fld.f21r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB19"); + state->u.f0.fld.f21r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB20"); + state->u.f0.fld.f21r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB21"); + state->u.f0.fld.f21r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB22"); + state->u.f0.fld.f21r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB23"); + state->u.f0.fld.f21r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB24"); + state->u.f0.fld.f21r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB25"); + state->u.f0.fld.f21r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB26"); + state->u.f0.fld.f21r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB27"); + state->u.f0.fld.f21r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB28"); + state->u.f0.fld.f21r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB29"); + state->u.f0.fld.f21r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB30"); + state->u.f0.fld.f21r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB31"); + + // F21R2 bitfields. + state->u.f0.fld.f21r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB0"); + state->u.f0.fld.f21r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB1"); + state->u.f0.fld.f21r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB2"); + state->u.f0.fld.f21r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB3"); + state->u.f0.fld.f21r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB4"); + state->u.f0.fld.f21r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB5"); + state->u.f0.fld.f21r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB6"); + state->u.f0.fld.f21r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB7"); + state->u.f0.fld.f21r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB8"); + state->u.f0.fld.f21r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB9"); + state->u.f0.fld.f21r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB10"); + state->u.f0.fld.f21r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB11"); + state->u.f0.fld.f21r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB12"); + state->u.f0.fld.f21r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB13"); + state->u.f0.fld.f21r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB14"); + state->u.f0.fld.f21r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB15"); + state->u.f0.fld.f21r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB16"); + state->u.f0.fld.f21r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB17"); + state->u.f0.fld.f21r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB18"); + state->u.f0.fld.f21r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB19"); + state->u.f0.fld.f21r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB20"); + state->u.f0.fld.f21r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB21"); + state->u.f0.fld.f21r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB22"); + state->u.f0.fld.f21r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB23"); + state->u.f0.fld.f21r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB24"); + state->u.f0.fld.f21r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB25"); + state->u.f0.fld.f21r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB26"); + state->u.f0.fld.f21r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB27"); + state->u.f0.fld.f21r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB28"); + state->u.f0.fld.f21r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB29"); + state->u.f0.fld.f21r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB30"); + state->u.f0.fld.f21r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB31"); + + // F22R1 bitfields. + state->u.f0.fld.f22r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB0"); + state->u.f0.fld.f22r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB1"); + state->u.f0.fld.f22r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB2"); + state->u.f0.fld.f22r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB3"); + state->u.f0.fld.f22r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB4"); + state->u.f0.fld.f22r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB5"); + state->u.f0.fld.f22r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB6"); + state->u.f0.fld.f22r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB7"); + state->u.f0.fld.f22r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB8"); + state->u.f0.fld.f22r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB9"); + state->u.f0.fld.f22r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB10"); + state->u.f0.fld.f22r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB11"); + state->u.f0.fld.f22r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB12"); + state->u.f0.fld.f22r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB13"); + state->u.f0.fld.f22r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB14"); + state->u.f0.fld.f22r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB15"); + state->u.f0.fld.f22r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB16"); + state->u.f0.fld.f22r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB17"); + state->u.f0.fld.f22r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB18"); + state->u.f0.fld.f22r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB19"); + state->u.f0.fld.f22r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB20"); + state->u.f0.fld.f22r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB21"); + state->u.f0.fld.f22r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB22"); + state->u.f0.fld.f22r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB23"); + state->u.f0.fld.f22r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB24"); + state->u.f0.fld.f22r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB25"); + state->u.f0.fld.f22r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB26"); + state->u.f0.fld.f22r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB27"); + state->u.f0.fld.f22r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB28"); + state->u.f0.fld.f22r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB29"); + state->u.f0.fld.f22r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB30"); + state->u.f0.fld.f22r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB31"); + + // F22R2 bitfields. + state->u.f0.fld.f22r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB0"); + state->u.f0.fld.f22r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB1"); + state->u.f0.fld.f22r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB2"); + state->u.f0.fld.f22r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB3"); + state->u.f0.fld.f22r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB4"); + state->u.f0.fld.f22r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB5"); + state->u.f0.fld.f22r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB6"); + state->u.f0.fld.f22r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB7"); + state->u.f0.fld.f22r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB8"); + state->u.f0.fld.f22r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB9"); + state->u.f0.fld.f22r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB10"); + state->u.f0.fld.f22r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB11"); + state->u.f0.fld.f22r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB12"); + state->u.f0.fld.f22r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB13"); + state->u.f0.fld.f22r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB14"); + state->u.f0.fld.f22r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB15"); + state->u.f0.fld.f22r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB16"); + state->u.f0.fld.f22r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB17"); + state->u.f0.fld.f22r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB18"); + state->u.f0.fld.f22r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB19"); + state->u.f0.fld.f22r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB20"); + state->u.f0.fld.f22r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB21"); + state->u.f0.fld.f22r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB22"); + state->u.f0.fld.f22r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB23"); + state->u.f0.fld.f22r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB24"); + state->u.f0.fld.f22r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB25"); + state->u.f0.fld.f22r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB26"); + state->u.f0.fld.f22r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB27"); + state->u.f0.fld.f22r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB28"); + state->u.f0.fld.f22r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB29"); + state->u.f0.fld.f22r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB30"); + state->u.f0.fld.f22r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB31"); + + // F23R1 bitfields. + state->u.f0.fld.f23r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB0"); + state->u.f0.fld.f23r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB1"); + state->u.f0.fld.f23r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB2"); + state->u.f0.fld.f23r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB3"); + state->u.f0.fld.f23r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB4"); + state->u.f0.fld.f23r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB5"); + state->u.f0.fld.f23r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB6"); + state->u.f0.fld.f23r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB7"); + state->u.f0.fld.f23r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB8"); + state->u.f0.fld.f23r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB9"); + state->u.f0.fld.f23r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB10"); + state->u.f0.fld.f23r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB11"); + state->u.f0.fld.f23r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB12"); + state->u.f0.fld.f23r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB13"); + state->u.f0.fld.f23r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB14"); + state->u.f0.fld.f23r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB15"); + state->u.f0.fld.f23r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB16"); + state->u.f0.fld.f23r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB17"); + state->u.f0.fld.f23r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB18"); + state->u.f0.fld.f23r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB19"); + state->u.f0.fld.f23r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB20"); + state->u.f0.fld.f23r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB21"); + state->u.f0.fld.f23r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB22"); + state->u.f0.fld.f23r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB23"); + state->u.f0.fld.f23r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB24"); + state->u.f0.fld.f23r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB25"); + state->u.f0.fld.f23r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB26"); + state->u.f0.fld.f23r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB27"); + state->u.f0.fld.f23r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB28"); + state->u.f0.fld.f23r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB29"); + state->u.f0.fld.f23r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB30"); + state->u.f0.fld.f23r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB31"); + + // F23R2 bitfields. + state->u.f0.fld.f23r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB0"); + state->u.f0.fld.f23r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB1"); + state->u.f0.fld.f23r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB2"); + state->u.f0.fld.f23r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB3"); + state->u.f0.fld.f23r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB4"); + state->u.f0.fld.f23r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB5"); + state->u.f0.fld.f23r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB6"); + state->u.f0.fld.f23r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB7"); + state->u.f0.fld.f23r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB8"); + state->u.f0.fld.f23r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB9"); + state->u.f0.fld.f23r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB10"); + state->u.f0.fld.f23r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB11"); + state->u.f0.fld.f23r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB12"); + state->u.f0.fld.f23r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB13"); + state->u.f0.fld.f23r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB14"); + state->u.f0.fld.f23r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB15"); + state->u.f0.fld.f23r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB16"); + state->u.f0.fld.f23r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB17"); + state->u.f0.fld.f23r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB18"); + state->u.f0.fld.f23r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB19"); + state->u.f0.fld.f23r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB20"); + state->u.f0.fld.f23r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB21"); + state->u.f0.fld.f23r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB22"); + state->u.f0.fld.f23r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB23"); + state->u.f0.fld.f23r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB24"); + state->u.f0.fld.f23r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB25"); + state->u.f0.fld.f23r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB26"); + state->u.f0.fld.f23r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB27"); + state->u.f0.fld.f23r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB28"); + state->u.f0.fld.f23r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB29"); + state->u.f0.fld.f23r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB30"); + state->u.f0.fld.f23r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB31"); + + // F24R1 bitfields. + state->u.f0.fld.f24r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB0"); + state->u.f0.fld.f24r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB1"); + state->u.f0.fld.f24r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB2"); + state->u.f0.fld.f24r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB3"); + state->u.f0.fld.f24r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB4"); + state->u.f0.fld.f24r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB5"); + state->u.f0.fld.f24r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB6"); + state->u.f0.fld.f24r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB7"); + state->u.f0.fld.f24r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB8"); + state->u.f0.fld.f24r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB9"); + state->u.f0.fld.f24r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB10"); + state->u.f0.fld.f24r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB11"); + state->u.f0.fld.f24r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB12"); + state->u.f0.fld.f24r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB13"); + state->u.f0.fld.f24r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB14"); + state->u.f0.fld.f24r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB15"); + state->u.f0.fld.f24r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB16"); + state->u.f0.fld.f24r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB17"); + state->u.f0.fld.f24r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB18"); + state->u.f0.fld.f24r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB19"); + state->u.f0.fld.f24r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB20"); + state->u.f0.fld.f24r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB21"); + state->u.f0.fld.f24r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB22"); + state->u.f0.fld.f24r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB23"); + state->u.f0.fld.f24r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB24"); + state->u.f0.fld.f24r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB25"); + state->u.f0.fld.f24r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB26"); + state->u.f0.fld.f24r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB27"); + state->u.f0.fld.f24r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB28"); + state->u.f0.fld.f24r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB29"); + state->u.f0.fld.f24r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB30"); + state->u.f0.fld.f24r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB31"); + + // F24R2 bitfields. + state->u.f0.fld.f24r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB0"); + state->u.f0.fld.f24r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB1"); + state->u.f0.fld.f24r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB2"); + state->u.f0.fld.f24r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB3"); + state->u.f0.fld.f24r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB4"); + state->u.f0.fld.f24r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB5"); + state->u.f0.fld.f24r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB6"); + state->u.f0.fld.f24r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB7"); + state->u.f0.fld.f24r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB8"); + state->u.f0.fld.f24r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB9"); + state->u.f0.fld.f24r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB10"); + state->u.f0.fld.f24r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB11"); + state->u.f0.fld.f24r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB12"); + state->u.f0.fld.f24r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB13"); + state->u.f0.fld.f24r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB14"); + state->u.f0.fld.f24r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB15"); + state->u.f0.fld.f24r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB16"); + state->u.f0.fld.f24r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB17"); + state->u.f0.fld.f24r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB18"); + state->u.f0.fld.f24r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB19"); + state->u.f0.fld.f24r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB20"); + state->u.f0.fld.f24r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB21"); + state->u.f0.fld.f24r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB22"); + state->u.f0.fld.f24r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB23"); + state->u.f0.fld.f24r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB24"); + state->u.f0.fld.f24r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB25"); + state->u.f0.fld.f24r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB26"); + state->u.f0.fld.f24r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB27"); + state->u.f0.fld.f24r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB28"); + state->u.f0.fld.f24r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB29"); + state->u.f0.fld.f24r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB30"); + state->u.f0.fld.f24r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB31"); + + // F25R1 bitfields. + state->u.f0.fld.f25r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB0"); + state->u.f0.fld.f25r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB1"); + state->u.f0.fld.f25r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB2"); + state->u.f0.fld.f25r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB3"); + state->u.f0.fld.f25r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB4"); + state->u.f0.fld.f25r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB5"); + state->u.f0.fld.f25r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB6"); + state->u.f0.fld.f25r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB7"); + state->u.f0.fld.f25r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB8"); + state->u.f0.fld.f25r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB9"); + state->u.f0.fld.f25r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB10"); + state->u.f0.fld.f25r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB11"); + state->u.f0.fld.f25r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB12"); + state->u.f0.fld.f25r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB13"); + state->u.f0.fld.f25r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB14"); + state->u.f0.fld.f25r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB15"); + state->u.f0.fld.f25r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB16"); + state->u.f0.fld.f25r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB17"); + state->u.f0.fld.f25r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB18"); + state->u.f0.fld.f25r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB19"); + state->u.f0.fld.f25r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB20"); + state->u.f0.fld.f25r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB21"); + state->u.f0.fld.f25r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB22"); + state->u.f0.fld.f25r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB23"); + state->u.f0.fld.f25r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB24"); + state->u.f0.fld.f25r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB25"); + state->u.f0.fld.f25r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB26"); + state->u.f0.fld.f25r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB27"); + state->u.f0.fld.f25r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB28"); + state->u.f0.fld.f25r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB29"); + state->u.f0.fld.f25r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB30"); + state->u.f0.fld.f25r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB31"); + + // F25R2 bitfields. + state->u.f0.fld.f25r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB0"); + state->u.f0.fld.f25r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB1"); + state->u.f0.fld.f25r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB2"); + state->u.f0.fld.f25r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB3"); + state->u.f0.fld.f25r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB4"); + state->u.f0.fld.f25r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB5"); + state->u.f0.fld.f25r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB6"); + state->u.f0.fld.f25r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB7"); + state->u.f0.fld.f25r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB8"); + state->u.f0.fld.f25r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB9"); + state->u.f0.fld.f25r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB10"); + state->u.f0.fld.f25r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB11"); + state->u.f0.fld.f25r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB12"); + state->u.f0.fld.f25r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB13"); + state->u.f0.fld.f25r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB14"); + state->u.f0.fld.f25r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB15"); + state->u.f0.fld.f25r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB16"); + state->u.f0.fld.f25r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB17"); + state->u.f0.fld.f25r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB18"); + state->u.f0.fld.f25r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB19"); + state->u.f0.fld.f25r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB20"); + state->u.f0.fld.f25r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB21"); + state->u.f0.fld.f25r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB22"); + state->u.f0.fld.f25r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB23"); + state->u.f0.fld.f25r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB24"); + state->u.f0.fld.f25r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB25"); + state->u.f0.fld.f25r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB26"); + state->u.f0.fld.f25r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB27"); + state->u.f0.fld.f25r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB28"); + state->u.f0.fld.f25r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB29"); + state->u.f0.fld.f25r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB30"); + state->u.f0.fld.f25r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB31"); + + // F26R1 bitfields. + state->u.f0.fld.f26r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB0"); + state->u.f0.fld.f26r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB1"); + state->u.f0.fld.f26r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB2"); + state->u.f0.fld.f26r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB3"); + state->u.f0.fld.f26r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB4"); + state->u.f0.fld.f26r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB5"); + state->u.f0.fld.f26r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB6"); + state->u.f0.fld.f26r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB7"); + state->u.f0.fld.f26r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB8"); + state->u.f0.fld.f26r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB9"); + state->u.f0.fld.f26r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB10"); + state->u.f0.fld.f26r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB11"); + state->u.f0.fld.f26r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB12"); + state->u.f0.fld.f26r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB13"); + state->u.f0.fld.f26r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB14"); + state->u.f0.fld.f26r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB15"); + state->u.f0.fld.f26r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB16"); + state->u.f0.fld.f26r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB17"); + state->u.f0.fld.f26r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB18"); + state->u.f0.fld.f26r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB19"); + state->u.f0.fld.f26r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB20"); + state->u.f0.fld.f26r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB21"); + state->u.f0.fld.f26r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB22"); + state->u.f0.fld.f26r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB23"); + state->u.f0.fld.f26r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB24"); + state->u.f0.fld.f26r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB25"); + state->u.f0.fld.f26r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB26"); + state->u.f0.fld.f26r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB27"); + state->u.f0.fld.f26r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB28"); + state->u.f0.fld.f26r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB29"); + state->u.f0.fld.f26r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB30"); + state->u.f0.fld.f26r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB31"); + + // F26R2 bitfields. + state->u.f0.fld.f26r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB0"); + state->u.f0.fld.f26r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB1"); + state->u.f0.fld.f26r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB2"); + state->u.f0.fld.f26r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB3"); + state->u.f0.fld.f26r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB4"); + state->u.f0.fld.f26r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB5"); + state->u.f0.fld.f26r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB6"); + state->u.f0.fld.f26r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB7"); + state->u.f0.fld.f26r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB8"); + state->u.f0.fld.f26r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB9"); + state->u.f0.fld.f26r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB10"); + state->u.f0.fld.f26r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB11"); + state->u.f0.fld.f26r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB12"); + state->u.f0.fld.f26r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB13"); + state->u.f0.fld.f26r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB14"); + state->u.f0.fld.f26r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB15"); + state->u.f0.fld.f26r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB16"); + state->u.f0.fld.f26r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB17"); + state->u.f0.fld.f26r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB18"); + state->u.f0.fld.f26r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB19"); + state->u.f0.fld.f26r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB20"); + state->u.f0.fld.f26r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB21"); + state->u.f0.fld.f26r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB22"); + state->u.f0.fld.f26r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB23"); + state->u.f0.fld.f26r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB24"); + state->u.f0.fld.f26r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB25"); + state->u.f0.fld.f26r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB26"); + state->u.f0.fld.f26r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB27"); + state->u.f0.fld.f26r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB28"); + state->u.f0.fld.f26r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB29"); + state->u.f0.fld.f26r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB30"); + state->u.f0.fld.f26r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB31"); + + // F27R1 bitfields. + state->u.f0.fld.f27r1.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB0"); + state->u.f0.fld.f27r1.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB1"); + state->u.f0.fld.f27r1.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB2"); + state->u.f0.fld.f27r1.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB3"); + state->u.f0.fld.f27r1.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB4"); + state->u.f0.fld.f27r1.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB5"); + state->u.f0.fld.f27r1.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB6"); + state->u.f0.fld.f27r1.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB7"); + state->u.f0.fld.f27r1.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB8"); + state->u.f0.fld.f27r1.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB9"); + state->u.f0.fld.f27r1.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB10"); + state->u.f0.fld.f27r1.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB11"); + state->u.f0.fld.f27r1.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB12"); + state->u.f0.fld.f27r1.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB13"); + state->u.f0.fld.f27r1.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB14"); + state->u.f0.fld.f27r1.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB15"); + state->u.f0.fld.f27r1.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB16"); + state->u.f0.fld.f27r1.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB17"); + state->u.f0.fld.f27r1.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB18"); + state->u.f0.fld.f27r1.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB19"); + state->u.f0.fld.f27r1.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB20"); + state->u.f0.fld.f27r1.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB21"); + state->u.f0.fld.f27r1.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB22"); + state->u.f0.fld.f27r1.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB23"); + state->u.f0.fld.f27r1.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB24"); + state->u.f0.fld.f27r1.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB25"); + state->u.f0.fld.f27r1.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB26"); + state->u.f0.fld.f27r1.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB27"); + state->u.f0.fld.f27r1.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB28"); + state->u.f0.fld.f27r1.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB29"); + state->u.f0.fld.f27r1.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB30"); + state->u.f0.fld.f27r1.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB31"); + + // F27R2 bitfields. + state->u.f0.fld.f27r2.fb0 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB0"); + state->u.f0.fld.f27r2.fb1 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB1"); + state->u.f0.fld.f27r2.fb2 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB2"); + state->u.f0.fld.f27r2.fb3 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB3"); + state->u.f0.fld.f27r2.fb4 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB4"); + state->u.f0.fld.f27r2.fb5 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB5"); + state->u.f0.fld.f27r2.fb6 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB6"); + state->u.f0.fld.f27r2.fb7 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB7"); + state->u.f0.fld.f27r2.fb8 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB8"); + state->u.f0.fld.f27r2.fb9 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB9"); + state->u.f0.fld.f27r2.fb10 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB10"); + state->u.f0.fld.f27r2.fb11 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB11"); + state->u.f0.fld.f27r2.fb12 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB12"); + state->u.f0.fld.f27r2.fb13 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB13"); + state->u.f0.fld.f27r2.fb14 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB14"); + state->u.f0.fld.f27r2.fb15 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB15"); + state->u.f0.fld.f27r2.fb16 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB16"); + state->u.f0.fld.f27r2.fb17 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB17"); + state->u.f0.fld.f27r2.fb18 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB18"); + state->u.f0.fld.f27r2.fb19 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB19"); + state->u.f0.fld.f27r2.fb20 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB20"); + state->u.f0.fld.f27r2.fb21 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB21"); + state->u.f0.fld.f27r2.fb22 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB22"); + state->u.f0.fld.f27r2.fb23 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB23"); + state->u.f0.fld.f27r2.fb24 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB24"); + state->u.f0.fld.f27r2.fb25 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB25"); + state->u.f0.fld.f27r2.fb26 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB26"); + state->u.f0.fld.f27r2.fb27 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB27"); + state->u.f0.fld.f27r2.fb28 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB28"); + state->u.f0.fld.f27r2.fb29 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB29"); + state->u.f0.fld.f27r2.fb30 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB30"); + state->u.f0.fld.f27r2.fb31 = cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB31"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_can_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_can_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_can_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_can_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_can_is_enabled(Object *obj) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_can_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CANState *state = STM32_CAN_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_can_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CAN)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CANState *state = STM32_CAN_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CAN"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_can_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_can_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_can_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_can_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_can_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CANEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_can_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CAN); +} + +static void stm32_can_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_can_reset_callback; + dc->realize = stm32_can_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_can_is_enabled; +} + +static const TypeInfo stm32_can_type_info = { + .name = TYPE_STM32_CAN, + .parent = TYPE_STM32_CAN_PARENT, + .instance_init = stm32_can_instance_init_callback, + .instance_size = sizeof(STM32CANState), + .class_init = stm32_can_class_init_callback, + .class_size = sizeof(STM32CANClass) }; + +static void stm32_can_register_types(void) +{ + type_register_static(&stm32_can_type_info); +} + +type_init(stm32_can_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/can.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/can.h new file mode 100644 index 0000000000..4ecbe715e7 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/can.h @@ -0,0 +1,2603 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CAN_H_ +#define STM32_CAN_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CAN DEVICE_PATH_STM32 "CAN" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CAN TYPE_STM32_PREFIX "can" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CAN_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CANParentClass; +typedef PeripheralState STM32CANParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CAN_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CANClass, (obj), TYPE_STM32_CAN) +#define STM32_CAN_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CANClass, (klass), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentClass parent_class; + // public: + + // None, so far. +} STM32CANClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CAN_STATE(obj) \ + OBJECT_CHECK(STM32CANState, (obj), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 CAN (Controller area network) registers. + struct { + Object *can_mcr; // 0x0 (CAN_MCR) + Object *can_msr; // 0x4 (CAN_MSR) + Object *can_tsr; // 0x8 (CAN_TSR) + Object *can_rf0r; // 0xC (CAN_RF0R) + Object *can_rf1r; // 0x10 (CAN_RF1R) + Object *can_ier; // 0x14 (CAN_IER) + Object *can_esr; // 0x18 (CAN_ESR) + Object *can_btr; // 0x1C (CAN BTR) + Object *can_ti0r; // 0x180 (CAN_TI0R) + Object *can_tdt0r; // 0x184 (CAN_TDT0R) + Object *can_tdl0r; // 0x188 (CAN_TDL0R) + Object *can_tdh0r; // 0x18C (CAN_TDH0R) + Object *can_ti1r; // 0x190 (CAN_TI1R) + Object *can_tdt1r; // 0x194 (CAN_TDT1R) + Object *can_tdl1r; // 0x198 (CAN_TDL1R) + Object *can_tdh1r; // 0x19C (CAN_TDH1R) + Object *can_ti2r; // 0x1A0 (CAN_TI2R) + Object *can_tdt2r; // 0x1A4 (CAN_TDT2R) + Object *can_tdl2r; // 0x1A8 (CAN_TDL2R) + Object *can_tdh2r; // 0x1AC (CAN_TDH2R) + Object *can_ri0r; // 0x1B0 (CAN_RI0R) + Object *can_rdt0r; // 0x1B4 (CAN_RDT0R) + Object *can_rdl0r; // 0x1B8 (CAN_RDL0R) + Object *can_rdh0r; // 0x1BC (CAN_RDH0R) + Object *can_ri1r; // 0x1C0 (CAN_RI1R) + Object *can_rdt1r; // 0x1C4 (CAN_RDT1R) + Object *can_rdl1r; // 0x1C8 (CAN_RDL1R) + Object *can_rdh1r; // 0x1CC (CAN_RDH1R) + Object *can_fmr; // 0x200 (CAN_FMR) + Object *can_fm1r; // 0x204 (CAN_FM1R) + Object *can_fs1r; // 0x20C (CAN_FS1R) + Object *can_ffa1r; // 0x214 (CAN_FFA1R) + Object *can_fa1r; // 0x21C (CAN_FA1R) + Object *f0r1; // 0x240 (Filter bank 0 register 1) + Object *f0r2; // 0x244 (Filter bank 0 register 2) + Object *f1r1; // 0x248 (Filter bank 1 register 1) + Object *f1r2; // 0x24C (Filter bank 1 register 2) + Object *f2r1; // 0x250 (Filter bank 2 register 1) + Object *f2r2; // 0x254 (Filter bank 2 register 2) + Object *f3r1; // 0x258 (Filter bank 3 register 1) + Object *f3r2; // 0x25C (Filter bank 3 register 2) + Object *f4r1; // 0x260 (Filter bank 4 register 1) + Object *f4r2; // 0x264 (Filter bank 4 register 2) + Object *f5r1; // 0x268 (Filter bank 5 register 1) + Object *f5r2; // 0x26C (Filter bank 5 register 2) + Object *f6r1; // 0x270 (Filter bank 6 register 1) + Object *f6r2; // 0x274 (Filter bank 6 register 2) + Object *f7r1; // 0x278 (Filter bank 7 register 1) + Object *f7r2; // 0x27C (Filter bank 7 register 2) + Object *f8r1; // 0x280 (Filter bank 8 register 1) + Object *f8r2; // 0x284 (Filter bank 8 register 2) + Object *f9r1; // 0x288 (Filter bank 9 register 1) + Object *f9r2; // 0x28C (Filter bank 9 register 2) + Object *f10r1; // 0x290 (Filter bank 10 register 1) + Object *f10r2; // 0x294 (Filter bank 10 register 2) + Object *f11r1; // 0x298 (Filter bank 11 register 1) + Object *f11r2; // 0x29C (Filter bank 11 register 2) + Object *f12r1; // 0x2A0 (Filter bank 4 register 1) + Object *f12r2; // 0x2A4 (Filter bank 12 register 2) + Object *f13r1; // 0x2A8 (Filter bank 13 register 1) + Object *f13r2; // 0x2AC (Filter bank 13 register 2) + Object *f14r1; // 0x2B0 (Filter bank 14 register 1) + Object *f14r2; // 0x2B4 (Filter bank 14 register 2) + Object *f15r1; // 0x2B8 (Filter bank 15 register 1) + Object *f15r2; // 0x2BC (Filter bank 15 register 2) + Object *f16r1; // 0x2C0 (Filter bank 16 register 1) + Object *f16r2; // 0x2C4 (Filter bank 16 register 2) + Object *f17r1; // 0x2C8 (Filter bank 17 register 1) + Object *f17r2; // 0x2CC (Filter bank 17 register 2) + Object *f18r1; // 0x2D0 (Filter bank 18 register 1) + Object *f18r2; // 0x2D4 (Filter bank 18 register 2) + Object *f19r1; // 0x2D8 (Filter bank 19 register 1) + Object *f19r2; // 0x2DC (Filter bank 19 register 2) + Object *f20r1; // 0x2E0 (Filter bank 20 register 1) + Object *f20r2; // 0x2E4 (Filter bank 20 register 2) + Object *f21r1; // 0x2E8 (Filter bank 21 register 1) + Object *f21r2; // 0x2EC (Filter bank 21 register 2) + Object *f22r1; // 0x2F0 (Filter bank 22 register 1) + Object *f22r2; // 0x2F4 (Filter bank 22 register 2) + Object *f23r1; // 0x2F8 (Filter bank 23 register 1) + Object *f23r2; // 0x2FC (Filter bank 23 register 2) + Object *f24r1; // 0x300 (Filter bank 24 register 1) + Object *f24r2; // 0x304 (Filter bank 24 register 2) + Object *f25r1; // 0x308 (Filter bank 25 register 1) + Object *f25r2; // 0x30C (Filter bank 25 register 2) + Object *f26r1; // 0x310 (Filter bank 26 register 1) + Object *f26r2; // 0x314 (Filter bank 26 register 2) + Object *f27r1; // 0x318 (Filter bank 27 register 1) + Object *f27r2; // 0x31C (Filter bank 27 register 2) + } reg; + + struct { + + // CAN_MCR (CAN_MCR) bitfields. + struct { + Object *inrq; // [0:0] INRQ + Object *sleep; // [1:1] SLEEP + Object *txfp; // [2:2] TXFP + Object *rflm; // [3:3] RFLM + Object *nart; // [4:4] NART + Object *awum; // [5:5] AWUM + Object *abom; // [6:6] ABOM + Object *ttcm; // [7:7] TTCM + Object *reset; // [15:15] RESET + Object *dbf; // [16:16] DBF + } can_mcr; + + // CAN_MSR (CAN_MSR) bitfields. + struct { + Object *inak; // [0:0] INAK + Object *slak; // [1:1] SLAK + Object *erri; // [2:2] ERRI + Object *wkui; // [3:3] WKUI + Object *slaki; // [4:4] SLAKI + Object *txm; // [8:8] TXM + Object *rxm; // [9:9] RXM + Object *samp; // [10:10] SAMP + Object *rx; // [11:11] RX + } can_msr; + + // CAN_TSR (CAN_TSR) bitfields. + struct { + Object *rqcp0; // [0:0] RQCP0 + Object *txok0; // [1:1] TXOK0 + Object *alst0; // [2:2] ALST0 + Object *terr0; // [3:3] TERR0 + Object *abrq0; // [7:7] ABRQ0 + Object *rqcp1; // [8:8] RQCP1 + Object *txok1; // [9:9] TXOK1 + Object *alst1; // [10:10] ALST1 + Object *terr1; // [11:11] TERR1 + Object *abrq1; // [15:15] ABRQ1 + Object *rqcp2; // [16:16] RQCP2 + Object *txok2; // [17:17] TXOK2 + Object *alst2; // [18:18] ALST2 + Object *terr2; // [19:19] TERR2 + Object *abrq2; // [23:23] ABRQ2 + Object *code; // [24:25] CODE + Object *tme0; // [26:26] Lowest priority flag for mailbox 0 + Object *tme1; // [27:27] Lowest priority flag for mailbox 1 + Object *tme2; // [28:28] Lowest priority flag for mailbox 2 + Object *low0; // [29:29] Lowest priority flag for mailbox 0 + Object *low1; // [30:30] Lowest priority flag for mailbox 1 + Object *low2; // [31:31] Lowest priority flag for mailbox 2 + } can_tsr; + + // CAN_RF0R (CAN_RF0R) bitfields. + struct { + Object *fmp0; // [0:1] FMP0 + Object *full0; // [3:3] FULL0 + Object *fovr0; // [4:4] FOVR0 + Object *rfom0; // [5:5] RFOM0 + } can_rf0r; + + // CAN_RF1R (CAN_RF1R) bitfields. + struct { + Object *fmp1; // [0:1] FMP1 + Object *full1; // [3:3] FULL1 + Object *fovr1; // [4:4] FOVR1 + Object *rfom1; // [5:5] RFOM1 + } can_rf1r; + + // CAN_IER (CAN_IER) bitfields. + struct { + Object *tmeie; // [0:0] TMEIE + Object *fmpie0; // [1:1] FMPIE0 + Object *ffie0; // [2:2] FFIE0 + Object *fovie0; // [3:3] FOVIE0 + Object *fmpie1; // [4:4] FMPIE1 + Object *ffie1; // [5:5] FFIE1 + Object *fovie1; // [6:6] FOVIE1 + Object *ewgie; // [8:8] EWGIE + Object *epvie; // [9:9] EPVIE + Object *bofie; // [10:10] BOFIE + Object *lecie; // [11:11] LECIE + Object *errie; // [15:15] ERRIE + Object *wkuie; // [16:16] WKUIE + Object *slkie; // [17:17] SLKIE + } can_ier; + + // CAN_ESR (CAN_ESR) bitfields. + struct { + Object *ewgf; // [0:0] EWGF + Object *epvf; // [1:1] EPVF + Object *boff; // [2:2] BOFF + Object *lec; // [4:6] LEC + Object *tec; // [16:23] TEC + Object *rec; // [24:31] REC + } can_esr; + + // CAN_BTR (CAN BTR) bitfields. + struct { + Object *brp; // [0:9] BRP + Object *ts1; // [16:19] TS1 + Object *ts2; // [20:22] TS2 + Object *sjw; // [24:25] SJW + Object *lbkm; // [30:30] LBKM + Object *silm; // [31:31] SILM + } can_btr; + + // CAN_TI0R (CAN_TI0R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti0r; + + // CAN_TDT0R (CAN_TDT0R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt0r; + + // CAN_TDL0R (CAN_TDL0R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl0r; + + // CAN_TDH0R (CAN_TDH0R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh0r; + + // CAN_TI1R (CAN_TI1R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti1r; + + // CAN_TDT1R (CAN_TDT1R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt1r; + + // CAN_TDL1R (CAN_TDL1R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl1r; + + // CAN_TDH1R (CAN_TDH1R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh1r; + + // CAN_TI2R (CAN_TI2R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti2r; + + // CAN_TDT2R (CAN_TDT2R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt2r; + + // CAN_TDL2R (CAN_TDL2R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl2r; + + // CAN_TDH2R (CAN_TDH2R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh2r; + + // CAN_RI0R (CAN_RI0R) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ri0r; + + // CAN_RDT0R (CAN_RDT0R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } can_rdt0r; + + // CAN_RDL0R (CAN_RDL0R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_rdl0r; + + // CAN_RDH0R (CAN_RDH0R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_rdh0r; + + // CAN_RI1R (CAN_RI1R) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ri1r; + + // CAN_RDT1R (CAN_RDT1R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } can_rdt1r; + + // CAN_RDL1R (CAN_RDL1R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_rdl1r; + + // CAN_RDH1R (CAN_RDH1R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_rdh1r; + + // CAN_FMR (CAN_FMR) bitfields. + struct { + Object *finit; // [0:0] FINIT + Object *can2sb; // [8:13] CAN2SB + } can_fmr; + + // CAN_FM1R (CAN_FM1R) bitfields. + struct { + Object *fbm0; // [0:0] Filter mode + Object *fbm1; // [1:1] Filter mode + Object *fbm2; // [2:2] Filter mode + Object *fbm3; // [3:3] Filter mode + Object *fbm4; // [4:4] Filter mode + Object *fbm5; // [5:5] Filter mode + Object *fbm6; // [6:6] Filter mode + Object *fbm7; // [7:7] Filter mode + Object *fbm8; // [8:8] Filter mode + Object *fbm9; // [9:9] Filter mode + Object *fbm10; // [10:10] Filter mode + Object *fbm11; // [11:11] Filter mode + Object *fbm12; // [12:12] Filter mode + Object *fbm13; // [13:13] Filter mode + Object *fbm14; // [14:14] Filter mode + Object *fbm15; // [15:15] Filter mode + Object *fbm16; // [16:16] Filter mode + Object *fbm17; // [17:17] Filter mode + Object *fbm18; // [18:18] Filter mode + Object *fbm19; // [19:19] Filter mode + Object *fbm20; // [20:20] Filter mode + Object *fbm21; // [21:21] Filter mode + Object *fbm22; // [22:22] Filter mode + Object *fbm23; // [23:23] Filter mode + Object *fbm24; // [24:24] Filter mode + Object *fbm25; // [25:25] Filter mode + Object *fbm26; // [26:26] Filter mode + Object *fbm27; // [27:27] Filter mode + } can_fm1r; + + // CAN_FS1R (CAN_FS1R) bitfields. + struct { + Object *fsc0; // [0:0] Filter scale configuration + Object *fsc1; // [1:1] Filter scale configuration + Object *fsc2; // [2:2] Filter scale configuration + Object *fsc3; // [3:3] Filter scale configuration + Object *fsc4; // [4:4] Filter scale configuration + Object *fsc5; // [5:5] Filter scale configuration + Object *fsc6; // [6:6] Filter scale configuration + Object *fsc7; // [7:7] Filter scale configuration + Object *fsc8; // [8:8] Filter scale configuration + Object *fsc9; // [9:9] Filter scale configuration + Object *fsc10; // [10:10] Filter scale configuration + Object *fsc11; // [11:11] Filter scale configuration + Object *fsc12; // [12:12] Filter scale configuration + Object *fsc13; // [13:13] Filter scale configuration + Object *fsc14; // [14:14] Filter scale configuration + Object *fsc15; // [15:15] Filter scale configuration + Object *fsc16; // [16:16] Filter scale configuration + Object *fsc17; // [17:17] Filter scale configuration + Object *fsc18; // [18:18] Filter scale configuration + Object *fsc19; // [19:19] Filter scale configuration + Object *fsc20; // [20:20] Filter scale configuration + Object *fsc21; // [21:21] Filter scale configuration + Object *fsc22; // [22:22] Filter scale configuration + Object *fsc23; // [23:23] Filter scale configuration + Object *fsc24; // [24:24] Filter scale configuration + Object *fsc25; // [25:25] Filter scale configuration + Object *fsc26; // [26:26] Filter scale configuration + Object *fsc27; // [27:27] Filter scale configuration + } can_fs1r; + + // CAN_FFA1R (CAN_FFA1R) bitfields. + struct { + Object *ffa0; // [0:0] Filter FIFO assignment for filter 0 + Object *ffa1; // [1:1] Filter FIFO assignment for filter 1 + Object *ffa2; // [2:2] Filter FIFO assignment for filter 2 + Object *ffa3; // [3:3] Filter FIFO assignment for filter 3 + Object *ffa4; // [4:4] Filter FIFO assignment for filter 4 + Object *ffa5; // [5:5] Filter FIFO assignment for filter 5 + Object *ffa6; // [6:6] Filter FIFO assignment for filter 6 + Object *ffa7; // [7:7] Filter FIFO assignment for filter 7 + Object *ffa8; // [8:8] Filter FIFO assignment for filter 8 + Object *ffa9; // [9:9] Filter FIFO assignment for filter 9 + Object *ffa10; // [10:10] Filter FIFO assignment for filter 10 + Object *ffa11; // [11:11] Filter FIFO assignment for filter 11 + Object *ffa12; // [12:12] Filter FIFO assignment for filter 12 + Object *ffa13; // [13:13] Filter FIFO assignment for filter 13 + Object *ffa14; // [14:14] Filter FIFO assignment for filter 14 + Object *ffa15; // [15:15] Filter FIFO assignment for filter 15 + Object *ffa16; // [16:16] Filter FIFO assignment for filter 16 + Object *ffa17; // [17:17] Filter FIFO assignment for filter 17 + Object *ffa18; // [18:18] Filter FIFO assignment for filter 18 + Object *ffa19; // [19:19] Filter FIFO assignment for filter 19 + Object *ffa20; // [20:20] Filter FIFO assignment for filter 20 + Object *ffa21; // [21:21] Filter FIFO assignment for filter 21 + Object *ffa22; // [22:22] Filter FIFO assignment for filter 22 + Object *ffa23; // [23:23] Filter FIFO assignment for filter 23 + Object *ffa24; // [24:24] Filter FIFO assignment for filter 24 + Object *ffa25; // [25:25] Filter FIFO assignment for filter 25 + Object *ffa26; // [26:26] Filter FIFO assignment for filter 26 + Object *ffa27; // [27:27] Filter FIFO assignment for filter 27 + } can_ffa1r; + + // CAN_FA1R (CAN_FA1R) bitfields. + struct { + Object *fact0; // [0:0] Filter active + Object *fact1; // [1:1] Filter active + Object *fact2; // [2:2] Filter active + Object *fact3; // [3:3] Filter active + Object *fact4; // [4:4] Filter active + Object *fact5; // [5:5] Filter active + Object *fact6; // [6:6] Filter active + Object *fact7; // [7:7] Filter active + Object *fact8; // [8:8] Filter active + Object *fact9; // [9:9] Filter active + Object *fact10; // [10:10] Filter active + Object *fact11; // [11:11] Filter active + Object *fact12; // [12:12] Filter active + Object *fact13; // [13:13] Filter active + Object *fact14; // [14:14] Filter active + Object *fact15; // [15:15] Filter active + Object *fact16; // [16:16] Filter active + Object *fact17; // [17:17] Filter active + Object *fact18; // [18:18] Filter active + Object *fact19; // [19:19] Filter active + Object *fact20; // [20:20] Filter active + Object *fact21; // [21:21] Filter active + Object *fact22; // [22:22] Filter active + Object *fact23; // [23:23] Filter active + Object *fact24; // [24:24] Filter active + Object *fact25; // [25:25] Filter active + Object *fact26; // [26:26] Filter active + Object *fact27; // [27:27] Filter active + } can_fa1r; + + // F0R1 (Filter bank 0 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r1; + + // F0R2 (Filter bank 0 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r2; + + // F1R1 (Filter bank 1 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r1; + + // F1R2 (Filter bank 1 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r2; + + // F2R1 (Filter bank 2 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r1; + + // F2R2 (Filter bank 2 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r2; + + // F3R1 (Filter bank 3 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r1; + + // F3R2 (Filter bank 3 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r2; + + // F4R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r1; + + // F4R2 (Filter bank 4 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r2; + + // F5R1 (Filter bank 5 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r1; + + // F5R2 (Filter bank 5 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r2; + + // F6R1 (Filter bank 6 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r1; + + // F6R2 (Filter bank 6 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r2; + + // F7R1 (Filter bank 7 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r1; + + // F7R2 (Filter bank 7 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r2; + + // F8R1 (Filter bank 8 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r1; + + // F8R2 (Filter bank 8 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r2; + + // F9R1 (Filter bank 9 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r1; + + // F9R2 (Filter bank 9 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r2; + + // F10R1 (Filter bank 10 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r1; + + // F10R2 (Filter bank 10 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r2; + + // F11R1 (Filter bank 11 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r1; + + // F11R2 (Filter bank 11 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r2; + + // F12R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r1; + + // F12R2 (Filter bank 12 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r2; + + // F13R1 (Filter bank 13 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r1; + + // F13R2 (Filter bank 13 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r2; + + // F14R1 (Filter bank 14 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r1; + + // F14R2 (Filter bank 14 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r2; + + // F15R1 (Filter bank 15 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r1; + + // F15R2 (Filter bank 15 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r2; + + // F16R1 (Filter bank 16 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r1; + + // F16R2 (Filter bank 16 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r2; + + // F17R1 (Filter bank 17 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r1; + + // F17R2 (Filter bank 17 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r2; + + // F18R1 (Filter bank 18 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r1; + + // F18R2 (Filter bank 18 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r2; + + // F19R1 (Filter bank 19 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r1; + + // F19R2 (Filter bank 19 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r2; + + // F20R1 (Filter bank 20 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r1; + + // F20R2 (Filter bank 20 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r2; + + // F21R1 (Filter bank 21 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r1; + + // F21R2 (Filter bank 21 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r2; + + // F22R1 (Filter bank 22 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r1; + + // F22R2 (Filter bank 22 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r2; + + // F23R1 (Filter bank 23 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r1; + + // F23R2 (Filter bank 23 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r2; + + // F24R1 (Filter bank 24 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r1; + + // F24R2 (Filter bank 24 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r2; + + // F25R1 (Filter bank 25 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r1; + + // F25R2 (Filter bank 25 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r2; + + // F26R1 (Filter bank 26 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r1; + + // F26R2 (Filter bank 26 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r2; + + // F27R1 (Filter bank 27 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r1; + + // F27R2 (Filter bank 27 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r2; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CANState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CAN_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/cec.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/cec.c new file mode 100644 index 0000000000..58a1d13dbd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/cec.c @@ -0,0 +1,290 @@ +/* + * STM32 - CEC (HDMI-CEC controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_cec_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CECState *state = STM32_CEC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f0.reg.txdr = cm_object_get_child_by_name(obj, "TXDR"); + state->u.f0.reg.rxdr = cm_object_get_child_by_name(obj, "RXDR"); + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.ier = cm_object_get_child_by_name(obj, "IER"); + + + // CR bitfields. + state->u.f0.fld.cr.cecen = cm_object_get_child_by_name(state->u.f0.reg.cr, "CECEN"); + state->u.f0.fld.cr.txsom = cm_object_get_child_by_name(state->u.f0.reg.cr, "TXSOM"); + state->u.f0.fld.cr.txeom = cm_object_get_child_by_name(state->u.f0.reg.cr, "TXEOM"); + + // CFGR bitfields. + state->u.f0.fld.cfgr.oar = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "OAR"); + state->u.f0.fld.cfgr.lstn = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "LSTN"); + state->u.f0.fld.cfgr.sft = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SFT"); + state->u.f0.fld.cfgr.rxtol = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "RXTOL"); + state->u.f0.fld.cfgr.brestp = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "BRESTP"); + state->u.f0.fld.cfgr.bregen = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "BREGEN"); + state->u.f0.fld.cfgr.lbpegen = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "LBPEGEN"); + + // TXDR bitfields. + state->u.f0.fld.txdr.txd = cm_object_get_child_by_name(state->u.f0.reg.txdr, "TXD"); + + // RXDR bitfields. + state->u.f0.fld.rxdr.rxdr = cm_object_get_child_by_name(state->u.f0.reg.rxdr, "RXDR"); + + // ISR bitfields. + state->u.f0.fld.isr.rxbr = cm_object_get_child_by_name(state->u.f0.reg.isr, "RXBR"); + state->u.f0.fld.isr.rxend = cm_object_get_child_by_name(state->u.f0.reg.isr, "RXEND"); + state->u.f0.fld.isr.rxovr = cm_object_get_child_by_name(state->u.f0.reg.isr, "RXOVR"); + state->u.f0.fld.isr.bre = cm_object_get_child_by_name(state->u.f0.reg.isr, "BRE"); + state->u.f0.fld.isr.sbpe = cm_object_get_child_by_name(state->u.f0.reg.isr, "SBPE"); + state->u.f0.fld.isr.lbpe = cm_object_get_child_by_name(state->u.f0.reg.isr, "LBPE"); + state->u.f0.fld.isr.rxacke = cm_object_get_child_by_name(state->u.f0.reg.isr, "RXACKE"); + state->u.f0.fld.isr.arblst = cm_object_get_child_by_name(state->u.f0.reg.isr, "ARBLST"); + state->u.f0.fld.isr.txbr = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXBR"); + state->u.f0.fld.isr.txend = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXEND"); + state->u.f0.fld.isr.txudr = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXUDR"); + state->u.f0.fld.isr.txerr = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXERR"); + state->u.f0.fld.isr.txacke = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXACKE"); + + // IER bitfields. + state->u.f0.fld.ier.rxbrie = cm_object_get_child_by_name(state->u.f0.reg.ier, "RXBRIE"); + state->u.f0.fld.ier.rxendie = cm_object_get_child_by_name(state->u.f0.reg.ier, "RXENDIE"); + state->u.f0.fld.ier.rxovrie = cm_object_get_child_by_name(state->u.f0.reg.ier, "RXOVRIE"); + state->u.f0.fld.ier.breie = cm_object_get_child_by_name(state->u.f0.reg.ier, "BREIE"); + state->u.f0.fld.ier.sbpeie = cm_object_get_child_by_name(state->u.f0.reg.ier, "SBPEIE"); + state->u.f0.fld.ier.lbpeie = cm_object_get_child_by_name(state->u.f0.reg.ier, "LBPEIE"); + state->u.f0.fld.ier.rxackie = cm_object_get_child_by_name(state->u.f0.reg.ier, "RXACKIE"); + state->u.f0.fld.ier.arblstie = cm_object_get_child_by_name(state->u.f0.reg.ier, "ARBLSTIE"); + state->u.f0.fld.ier.txbrie = cm_object_get_child_by_name(state->u.f0.reg.ier, "TXBRIE"); + state->u.f0.fld.ier.txendie = cm_object_get_child_by_name(state->u.f0.reg.ier, "TXENDIE"); + state->u.f0.fld.ier.txudrie = cm_object_get_child_by_name(state->u.f0.reg.ier, "TXUDRIE"); + state->u.f0.fld.ier.txerrie = cm_object_get_child_by_name(state->u.f0.reg.ier, "TXERRIE"); + state->u.f0.fld.ier.txackie = cm_object_get_child_by_name(state->u.f0.reg.ier, "TXACKIE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_cec_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_cec_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_cec_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_cec_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_cec_is_enabled(Object *obj) +{ + STM32CECState *state = STM32_CEC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_cec_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CECState *state = STM32_CEC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_cec_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CEC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CECState *state = STM32_CEC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CEC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_cec_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_cec_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_cec_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_cec_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_cec_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CECEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_cec_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CEC); +} + +static void stm32_cec_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_cec_reset_callback; + dc->realize = stm32_cec_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_cec_is_enabled; +} + +static const TypeInfo stm32_cec_type_info = { + .name = TYPE_STM32_CEC, + .parent = TYPE_STM32_CEC_PARENT, + .instance_init = stm32_cec_instance_init_callback, + .instance_size = sizeof(STM32CECState), + .class_init = stm32_cec_class_init_callback, + .class_size = sizeof(STM32CECClass) }; + +static void stm32_cec_register_types(void) +{ + type_register_static(&stm32_cec_type_info); +} + +type_init(stm32_cec_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/cec.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/cec.h new file mode 100644 index 0000000000..633d5c276a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/cec.h @@ -0,0 +1,167 @@ +/* + * STM32 - CEC (HDMI-CEC controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CEC_H_ +#define STM32_CEC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CEC DEVICE_PATH_STM32 "CEC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CEC TYPE_STM32_PREFIX "cec" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CEC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CECParentClass; +typedef PeripheralState STM32CECParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CEC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CECClass, (obj), TYPE_STM32_CEC) +#define STM32_CEC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CECClass, (klass), TYPE_STM32_CEC) + +typedef struct { + // private: + STM32CECParentClass parent_class; + // public: + + // None, so far. +} STM32CECClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CEC_STATE(obj) \ + OBJECT_CHECK(STM32CECState, (obj), TYPE_STM32_CEC) + +typedef struct { + // private: + STM32CECParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 CEC (HDMI-CEC controller) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *cfgr; // 0x4 (Configuration register) + Object *txdr; // 0x8 (Tx data register) + Object *rxdr; // 0xC (Rx Data Register) + Object *isr; // 0x10 (Interrupt and Status Register) + Object *ier; // 0x14 (Interrupt enable register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *cecen; // [0:0] CEC Enable + Object *txsom; // [1:1] Tx start of message + Object *txeom; // [2:2] Tx End Of Message + } cr; + + // CFGR (Configuration register) bitfields. + struct { + Object *oar; // [0:3] Own Address + Object *lstn; // [4:4] Listen mode + Object *sft; // [5:7] Signal Free Time + Object *rxtol; // [8:8] Rx-Tolerance + Object *brestp; // [9:9] Rx-stop on bit rising error + Object *bregen; // [10:10] Generate error-bit on bit rising error + Object *lbpegen; // [11:11] Generate Error-Bit on Long Bit Period Error + } cfgr; + + // TXDR (Tx data register) bitfields. + struct { + Object *txd; // [0:7] Tx Data register + } txdr; + + // RXDR (Rx Data Register) bitfields. + struct { + Object *rxdr; // [0:7] CEC Rx Data Register + } rxdr; + + // ISR (Interrupt and Status Register) bitfields. + struct { + Object *rxbr; // [0:0] Rx-Byte Received + Object *rxend; // [1:1] End Of Reception + Object *rxovr; // [2:2] Rx-Overrun + Object *bre; // [3:3] Rx-Bit rising error + Object *sbpe; // [4:4] Rx-Short Bit period error + Object *lbpe; // [5:5] Rx-Long Bit Period Error + Object *rxacke; // [6:6] Rx-Missing Acknowledge + Object *arblst; // [7:7] Arbitration Lost + Object *txbr; // [8:8] Tx-Byte Request + Object *txend; // [9:9] End of Transmission + Object *txudr; // [10:10] Tx-Buffer Underrun + Object *txerr; // [11:11] Tx-Error + Object *txacke; // [12:12] Tx-Missing acknowledge error + } isr; + + // IER (Interrupt enable register) bitfields. + struct { + Object *rxbrie; // [0:0] Rx-Byte Received Interrupt Enable + Object *rxendie; // [1:1] End Of Reception Interrupt Enable + Object *rxovrie; // [2:2] Rx-Buffer Overrun Interrupt Enable + Object *breie; // [3:3] Bit Rising Error Interrupt Enable + Object *sbpeie; // [4:4] Short Bit Period Error Interrupt Enable + Object *lbpeie; // [5:5] Long Bit Period Error Interrupt Enable + Object *rxackie; // [6:6] Rx-Missing Acknowledge Error Interrupt Enable + Object *arblstie; // [7:7] Arbitration Lost Interrupt Enable + Object *txbrie; // [8:8] Tx-Byte Request Interrupt Enable + Object *txendie; // [9:9] Tx-End of message interrupt enable + Object *txudrie; // [10:10] Tx-Underrun interrupt enable + Object *txerrie; // [11:11] Tx-Error Interrupt Enable + Object *txackie; // [12:12] Tx-Missing Acknowledge Error Interrupt Enable + } ier; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CECState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CEC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/comp.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/comp.c new file mode 100644 index 0000000000..c3b30cca62 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/comp.c @@ -0,0 +1,255 @@ +/* + * STM32 - COMP (Comparator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_comp_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32COMPState *state = STM32_COMP_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CSR bitfields. + state->u.f0.fld.csr.comp1en = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1EN"); + state->u.f0.fld.csr.comp1_inp_dac = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1_INP_DAC"); + state->u.f0.fld.csr.comp1mode = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1MODE"); + state->u.f0.fld.csr.comp1insel = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1INSEL"); + state->u.f0.fld.csr.comp1outsel = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1OUTSEL"); + state->u.f0.fld.csr.comp1pol = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1POL"); + state->u.f0.fld.csr.comp1hyst = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1HYST"); + state->u.f0.fld.csr.comp1out = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1OUT"); + state->u.f0.fld.csr.comp1lock = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1LOCK"); + state->u.f0.fld.csr.comp2en = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2EN"); + state->u.f0.fld.csr.comp2mode = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2MODE"); + state->u.f0.fld.csr.comp2insel = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2INSEL"); + state->u.f0.fld.csr.wndwen = cm_object_get_child_by_name(state->u.f0.reg.csr, "WNDWEN"); + state->u.f0.fld.csr.comp2outsel = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2OUTSEL"); + state->u.f0.fld.csr.comp2pol = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2POL"); + state->u.f0.fld.csr.comp2hyst = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2HYST"); + state->u.f0.fld.csr.comp2out = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2OUT"); + state->u.f0.fld.csr.comp2lock = cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2LOCK"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_comp_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_comp_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_comp_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_comp_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_comp_is_enabled(Object *obj) +{ + STM32COMPState *state = STM32_COMP_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_comp_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32COMPState *state = STM32_COMP_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_comp_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_COMP)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32COMPState *state = STM32_COMP_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "COMP"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_comp_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_comp_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_comp_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_comp_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_comp_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/COMPEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_comp_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_COMP); +} + +static void stm32_comp_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_comp_reset_callback; + dc->realize = stm32_comp_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_comp_is_enabled; +} + +static const TypeInfo stm32_comp_type_info = { + .name = TYPE_STM32_COMP, + .parent = TYPE_STM32_COMP_PARENT, + .instance_init = stm32_comp_instance_init_callback, + .instance_size = sizeof(STM32COMPState), + .class_init = stm32_comp_class_init_callback, + .class_size = sizeof(STM32COMPClass) }; + +static void stm32_comp_register_types(void) +{ + type_register_static(&stm32_comp_type_info); +} + +type_init(stm32_comp_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/comp.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/comp.h new file mode 100644 index 0000000000..5cc9bdd3be --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/comp.h @@ -0,0 +1,122 @@ +/* + * STM32 - COMP (Comparator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_COMP_H_ +#define STM32_COMP_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_COMP DEVICE_PATH_STM32 "COMP" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_COMP TYPE_STM32_PREFIX "comp" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_COMP_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32COMPParentClass; +typedef PeripheralState STM32COMPParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_COMP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32COMPClass, (obj), TYPE_STM32_COMP) +#define STM32_COMP_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32COMPClass, (klass), TYPE_STM32_COMP) + +typedef struct { + // private: + STM32COMPParentClass parent_class; + // public: + + // None, so far. +} STM32COMPClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_COMP_STATE(obj) \ + OBJECT_CHECK(STM32COMPState, (obj), TYPE_STM32_COMP) + +typedef struct { + // private: + STM32COMPParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 COMP (Comparator) registers. + struct { + Object *csr; // 0x0 (Control and status register) + } reg; + + struct { + + // CSR (Control and status register) bitfields. + struct { + Object *comp1en; // [0:0] Comparator 1 enable + Object *comp1_inp_dac; // [1:1] COMP1_INP_DAC + Object *comp1mode; // [2:3] Comparator 1 mode + Object *comp1insel; // [4:6] Comparator 1 inverting input selection + Object *comp1outsel; // [8:10] Comparator 1 output selection + Object *comp1pol; // [11:11] Comparator 1 output polarity + Object *comp1hyst; // [12:13] Comparator 1 hysteresis + Object *comp1out; // [14:14] Comparator 1 output + Object *comp1lock; // [15:15] Comparator 1 lock + Object *comp2en; // [16:16] Comparator 2 enable + Object *comp2mode; // [18:19] Comparator 2 mode + Object *comp2insel; // [20:22] Comparator 2 inverting input selection + Object *wndwen; // [23:23] Window mode enable + Object *comp2outsel; // [24:26] Comparator 2 output selection + Object *comp2pol; // [27:27] Comparator 2 output polarity + Object *comp2hyst; // [28:29] Comparator 2 hysteresis + Object *comp2out; // [30:30] Comparator 2 output + Object *comp2lock; // [31:31] Comparator 2 lock + } csr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32COMPState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_COMP_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/crc.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/crc.c new file mode 100644 index 0000000000..14e3018a19 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/crc.c @@ -0,0 +1,253 @@ +/* + * STM32 - CRC (Cyclic redundancy check calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_crc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f0.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.init = cm_object_get_child_by_name(obj, "INIT"); + + + // DR bitfields. + state->u.f0.fld.dr.dr = cm_object_get_child_by_name(state->u.f0.reg.dr, "DR"); + + // IDR bitfields. + state->u.f0.fld.idr.idr = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR"); + + // CR bitfields. + state->u.f0.fld.cr.reset = cm_object_get_child_by_name(state->u.f0.reg.cr, "RESET"); + state->u.f0.fld.cr.polysize = cm_object_get_child_by_name(state->u.f0.reg.cr, "POLYSIZE"); + state->u.f0.fld.cr.rev_in = cm_object_get_child_by_name(state->u.f0.reg.cr, "REV_IN"); + state->u.f0.fld.cr.rev_out = cm_object_get_child_by_name(state->u.f0.reg.cr, "REV_OUT"); + + // INIT bitfields. + state->u.f0.fld.init.init = cm_object_get_child_by_name(state->u.f0.reg.init, "INIT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crc_is_enabled(Object *obj) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRCState *state = STM32_CRC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRCState *state = STM32_CRC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_crc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_crc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_crc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRC); +} + +static void stm32_crc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crc_reset_callback; + dc->realize = stm32_crc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crc_is_enabled; +} + +static const TypeInfo stm32_crc_type_info = { + .name = TYPE_STM32_CRC, + .parent = TYPE_STM32_CRC_PARENT, + .instance_init = stm32_crc_instance_init_callback, + .instance_size = sizeof(STM32CRCState), + .class_init = stm32_crc_class_init_callback, + .class_size = sizeof(STM32CRCClass) }; + +static void stm32_crc_register_types(void) +{ + type_register_static(&stm32_crc_type_info); +} + +type_init(stm32_crc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/crc.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/crc.h new file mode 100644 index 0000000000..962b21cb4c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/crc.h @@ -0,0 +1,126 @@ +/* + * STM32 - CRC (Cyclic redundancy check calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRC_H_ +#define STM32_CRC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRC DEVICE_PATH_STM32 "CRC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRC TYPE_STM32_PREFIX "crc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRCParentClass; +typedef PeripheralState STM32CRCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRCClass, (obj), TYPE_STM32_CRC) +#define STM32_CRC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRCClass, (klass), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentClass parent_class; + // public: + + // None, so far. +} STM32CRCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRC_STATE(obj) \ + OBJECT_CHECK(STM32CRCState, (obj), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 CRC (Cyclic redundancy check calculation unit) registers. + struct { + Object *dr; // 0x0 (Data register) + Object *idr; // 0x4 (Independent data register) + Object *cr; // 0x8 (Control register) + Object *init; // 0xC (Initial CRC value) + } reg; + + struct { + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:31] Data register bits + } dr; + + // IDR (Independent data register) bitfields. + struct { + Object *idr; // [0:7] General-purpose 8-bit data register bits + } idr; + + // CR (Control register) bitfields. + struct { + Object *reset; // [0:0] Reset bit + Object *polysize; // [3:4] Polynomial size + Object *rev_in; // [5:6] Reverse input data + Object *rev_out; // [7:7] Reverse output data + } cr; + + // INIT (Initial CRC value) bitfields. + struct { + Object *init; // [0:31] Programmable initial CRC value + } init; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/crs.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/crs.c new file mode 100644 index 0000000000..b59cd1eecd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/crs.c @@ -0,0 +1,272 @@ +/* + * STM32 - CRS (Clock recovery system) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_crs_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRSState *state = STM32_CRS_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + + + // CR bitfields. + state->u.f0.fld.cr.syncokie = cm_object_get_child_by_name(state->u.f0.reg.cr, "SYNCOKIE"); + state->u.f0.fld.cr.syncwarnie = cm_object_get_child_by_name(state->u.f0.reg.cr, "SYNCWARNIE"); + state->u.f0.fld.cr.errie = cm_object_get_child_by_name(state->u.f0.reg.cr, "ERRIE"); + state->u.f0.fld.cr.esyncie = cm_object_get_child_by_name(state->u.f0.reg.cr, "ESYNCIE"); + state->u.f0.fld.cr.cen = cm_object_get_child_by_name(state->u.f0.reg.cr, "CEN"); + state->u.f0.fld.cr.autotrimen = cm_object_get_child_by_name(state->u.f0.reg.cr, "AUTOTRIMEN"); + state->u.f0.fld.cr.swsync = cm_object_get_child_by_name(state->u.f0.reg.cr, "SWSYNC"); + state->u.f0.fld.cr.trim = cm_object_get_child_by_name(state->u.f0.reg.cr, "TRIM"); + + // CFGR bitfields. + state->u.f0.fld.cfgr.reload = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "RELOAD"); + state->u.f0.fld.cfgr.felim = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "FELIM"); + state->u.f0.fld.cfgr.syncdiv = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SYNCDIV"); + state->u.f0.fld.cfgr.syncsrc = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SYNCSRC"); + state->u.f0.fld.cfgr.syncpol = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SYNCPOL"); + + // ISR bitfields. + state->u.f0.fld.isr.syncokf = cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCOKF"); + state->u.f0.fld.isr.syncwarnf = cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCWARNF"); + state->u.f0.fld.isr.errf = cm_object_get_child_by_name(state->u.f0.reg.isr, "ERRF"); + state->u.f0.fld.isr.esyncf = cm_object_get_child_by_name(state->u.f0.reg.isr, "ESYNCF"); + state->u.f0.fld.isr.syncerr = cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCERR"); + state->u.f0.fld.isr.syncmiss = cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCMISS"); + state->u.f0.fld.isr.trimovf = cm_object_get_child_by_name(state->u.f0.reg.isr, "TRIMOVF"); + state->u.f0.fld.isr.fedir = cm_object_get_child_by_name(state->u.f0.reg.isr, "FEDIR"); + state->u.f0.fld.isr.fecap = cm_object_get_child_by_name(state->u.f0.reg.isr, "FECAP"); + + // ICR bitfields. + state->u.f0.fld.icr.syncokc = cm_object_get_child_by_name(state->u.f0.reg.icr, "SYNCOKC"); + state->u.f0.fld.icr.syncwarnc = cm_object_get_child_by_name(state->u.f0.reg.icr, "SYNCWARNC"); + state->u.f0.fld.icr.errc = cm_object_get_child_by_name(state->u.f0.reg.icr, "ERRC"); + state->u.f0.fld.icr.esyncc = cm_object_get_child_by_name(state->u.f0.reg.icr, "ESYNCC"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crs_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crs_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crs_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crs_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crs_is_enabled(Object *obj) +{ + STM32CRSState *state = STM32_CRS_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crs_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRSState *state = STM32_CRS_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crs_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRS)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRSState *state = STM32_CRS_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRS"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_crs_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crs_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_crs_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crs_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_crs_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRSEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crs_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRS); +} + +static void stm32_crs_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crs_reset_callback; + dc->realize = stm32_crs_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crs_is_enabled; +} + +static const TypeInfo stm32_crs_type_info = { + .name = TYPE_STM32_CRS, + .parent = TYPE_STM32_CRS_PARENT, + .instance_init = stm32_crs_instance_init_callback, + .instance_size = sizeof(STM32CRSState), + .class_init = stm32_crs_class_init_callback, + .class_size = sizeof(STM32CRSClass) }; + +static void stm32_crs_register_types(void) +{ + type_register_static(&stm32_crs_type_info); +} + +type_init(stm32_crs_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/crs.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/crs.h new file mode 100644 index 0000000000..bc689276aa --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/crs.h @@ -0,0 +1,145 @@ +/* + * STM32 - CRS (Clock recovery system) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRS_H_ +#define STM32_CRS_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRS DEVICE_PATH_STM32 "CRS" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRS TYPE_STM32_PREFIX "crs" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRS_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRSParentClass; +typedef PeripheralState STM32CRSParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRSClass, (obj), TYPE_STM32_CRS) +#define STM32_CRS_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRSClass, (klass), TYPE_STM32_CRS) + +typedef struct { + // private: + STM32CRSParentClass parent_class; + // public: + + // None, so far. +} STM32CRSClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRS_STATE(obj) \ + OBJECT_CHECK(STM32CRSState, (obj), TYPE_STM32_CRS) + +typedef struct { + // private: + STM32CRSParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 CRS (Clock recovery system) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *cfgr; // 0x4 (Configuration register) + Object *isr; // 0x8 (Interrupt and status register) + Object *icr; // 0xC (Interrupt flag clear register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *syncokie; // [0:0] SYNC event OK interrupt enable + Object *syncwarnie; // [1:1] SYNC warning interrupt enable + Object *errie; // [2:2] Synchronization or trimming error interrupt enable + Object *esyncie; // [3:3] Expected SYNC interrupt enable + Object *cen; // [5:5] Frequency error counter enable + Object *autotrimen; // [6:6] Automatic trimming enable + Object *swsync; // [7:7] Generate software SYNC event + Object *trim; // [8:13] HSI48 oscillator smooth trimming + } cr; + + // CFGR (Configuration register) bitfields. + struct { + Object *reload; // [0:15] Counter reload value + Object *felim; // [16:23] Frequency error limit + Object *syncdiv; // [24:26] SYNC divider + Object *syncsrc; // [28:29] SYNC signal source selection + Object *syncpol; // [31:31] SYNC polarity selection + } cfgr; + + // ISR (Interrupt and status register) bitfields. + struct { + Object *syncokf; // [0:0] SYNC event OK flag + Object *syncwarnf; // [1:1] SYNC warning flag + Object *errf; // [2:2] Error flag + Object *esyncf; // [3:3] Expected SYNC flag + Object *syncerr; // [8:8] SYNC error + Object *syncmiss; // [9:9] SYNC missed + Object *trimovf; // [10:10] Trimming overflow or underflow + Object *fedir; // [15:15] Frequency error direction + Object *fecap; // [16:31] Frequency error capture + } isr; + + // ICR (Interrupt flag clear register) bitfields. + struct { + Object *syncokc; // [0:0] SYNC event OK clear flag + Object *syncwarnc; // [1:1] SYNC warning clear flag + Object *errc; // [2:2] Error clear flag + Object *esyncc; // [3:3] Expected SYNC clear flag + } icr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRSState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRS_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/dac.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/dac.c new file mode 100644 index 0000000000..841c11e6cd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/dac.c @@ -0,0 +1,269 @@ +/* + * STM32 - DAC (Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_dac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.swtrigr = cm_object_get_child_by_name(obj, "SWTRIGR"); + state->u.f0.reg.dhr12r1 = cm_object_get_child_by_name(obj, "DHR12R1"); + state->u.f0.reg.dhr12l1 = cm_object_get_child_by_name(obj, "DHR12L1"); + state->u.f0.reg.dhr8r1 = cm_object_get_child_by_name(obj, "DHR8R1"); + state->u.f0.reg.dor1 = cm_object_get_child_by_name(obj, "DOR1"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f0.fld.cr.lpds = cm_object_get_child_by_name(state->u.f0.reg.cr, "LPDS"); + state->u.f0.fld.cr.pdds = cm_object_get_child_by_name(state->u.f0.reg.cr, "PDDS"); + state->u.f0.fld.cr.cwuf = cm_object_get_child_by_name(state->u.f0.reg.cr, "CWUF"); + state->u.f0.fld.cr.csbf = cm_object_get_child_by_name(state->u.f0.reg.cr, "CSBF"); + state->u.f0.fld.cr.pvde = cm_object_get_child_by_name(state->u.f0.reg.cr, "PVDE"); + state->u.f0.fld.cr.pls = cm_object_get_child_by_name(state->u.f0.reg.cr, "PLS"); + state->u.f0.fld.cr.dbp = cm_object_get_child_by_name(state->u.f0.reg.cr, "DBP"); + + // SWTRIGR bitfields. + state->u.f0.fld.swtrigr.swtrig1 = cm_object_get_child_by_name(state->u.f0.reg.swtrigr, "SWTRIG1"); + + // DHR12R1 bitfields. + state->u.f0.fld.dhr12r1.dacc1dhr = cm_object_get_child_by_name(state->u.f0.reg.dhr12r1, "DACC1DHR"); + + // DHR12L1 bitfields. + state->u.f0.fld.dhr12l1.dacc1dhr = cm_object_get_child_by_name(state->u.f0.reg.dhr12l1, "DACC1DHR"); + + // DHR8R1 bitfields. + state->u.f0.fld.dhr8r1.dacc1dhr = cm_object_get_child_by_name(state->u.f0.reg.dhr8r1, "DACC1DHR"); + + // DOR1 bitfields. + state->u.f0.fld.dor1.dacc1dor = cm_object_get_child_by_name(state->u.f0.reg.dor1, "DACC1DOR"); + + // SR bitfields. + state->u.f0.fld.sr.dmaudr1 = cm_object_get_child_by_name(state->u.f0.reg.sr, "DMAUDR1"); + state->u.f0.fld.sr.dmaudr2 = cm_object_get_child_by_name(state->u.f0.reg.sr, "DMAUDR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dac_is_enabled(Object *obj) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DACState *state = STM32_DAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DACState *state = STM32_DAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_dac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_dac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_dac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DAC); +} + +static void stm32_dac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dac_reset_callback; + dc->realize = stm32_dac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dac_is_enabled; +} + +static const TypeInfo stm32_dac_type_info = { + .name = TYPE_STM32_DAC, + .parent = TYPE_STM32_DAC_PARENT, + .instance_init = stm32_dac_instance_init_callback, + .instance_size = sizeof(STM32DACState), + .class_init = stm32_dac_class_init_callback, + .class_size = sizeof(STM32DACClass) }; + +static void stm32_dac_register_types(void) +{ + type_register_static(&stm32_dac_type_info); +} + +type_init(stm32_dac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/dac.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/dac.h new file mode 100644 index 0000000000..8479ecfaba --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/dac.h @@ -0,0 +1,148 @@ +/* + * STM32 - DAC (Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DAC_H_ +#define STM32_DAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DAC DEVICE_PATH_STM32 "DAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DAC TYPE_STM32_PREFIX "dac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DACParentClass; +typedef PeripheralState STM32DACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DACClass, (obj), TYPE_STM32_DAC) +#define STM32_DAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DACClass, (klass), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentClass parent_class; + // public: + + // None, so far. +} STM32DACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DAC_STATE(obj) \ + OBJECT_CHECK(STM32DACState, (obj), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 DAC (Digital-to-analog converter) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *swtrigr; // 0x4 (Software trigger register) + Object *dhr12r1; // 0x8 (Channel1 12-bit right-aligned data holding register) + Object *dhr12l1; // 0xC (Channel1 12-bit left aligned data holding register) + Object *dhr8r1; // 0x10 (Channel1 8-bit right aligned data holding register) + Object *dor1; // 0x2C (Channel1 data output register) + Object *sr; // 0x34 (Status register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *lpds; // [0:0] Low-power deep sleep + Object *pdds; // [1:1] Power down deepsleep + Object *cwuf; // [2:2] Clear wakeup flag + Object *csbf; // [3:3] Clear standby flag + Object *pvde; // [4:4] Power voltage detector enable + Object *pls; // [5:7] PVD level selection + Object *dbp; // [8:8] Disable backup domain write protection + } cr; + + // SWTRIGR (Software trigger register) bitfields. + struct { + Object *swtrig1; // [0:0] DAC channel1 software trigger + } swtrigr; + + // DHR12R1 (Channel1 12-bit right-aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + } dhr12r1; + + // DHR12L1 (Channel1 12-bit left aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + } dhr12l1; + + // DHR8R1 (Channel1 8-bit right aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + } dhr8r1; + + // DOR1 (Channel1 data output register) bitfields. + struct { + Object *dacc1dor; // [0:11] DAC channel1 data output + } dor1; + + // SR (Status register) bitfields. + struct { + Object *dmaudr1; // [13:13] DAC channel1 DMA underrun flag + Object *dmaudr2; // [29:29] DAC channel2 DMA underrun flag + } sr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/dbgmcu.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/dbgmcu.c new file mode 100644 index 0000000000..9a03df407a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/dbgmcu.c @@ -0,0 +1,263 @@ +/* + * STM32 - DBGMCU (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_dbgmcu_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.idcode = cm_object_get_child_by_name(obj, "IDCODE"); + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.apblfz = cm_object_get_child_by_name(obj, "APBLFZ"); + state->u.f0.reg.apbhfz = cm_object_get_child_by_name(obj, "APBHFZ"); + + + // IDCODE bitfields. + state->u.f0.fld.idcode.dev_id = cm_object_get_child_by_name(state->u.f0.reg.idcode, "DEV_ID"); + state->u.f0.fld.idcode.div_id = cm_object_get_child_by_name(state->u.f0.reg.idcode, "DIV_ID"); + state->u.f0.fld.idcode.rev_id = cm_object_get_child_by_name(state->u.f0.reg.idcode, "REV_ID"); + + // CR bitfields. + state->u.f0.fld.cr.dbg_stop = cm_object_get_child_by_name(state->u.f0.reg.cr, "DBG_STOP"); + state->u.f0.fld.cr.dbg_standby = cm_object_get_child_by_name(state->u.f0.reg.cr, "DBG_STANDBY"); + + // APBLFZ bitfields. + state->u.f0.fld.apblfz.dbg_timer2_stop = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER2_STOP"); + state->u.f0.fld.apblfz.dbg_timer3_stop = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER3_STOP"); + state->u.f0.fld.apblfz.dbg_timer6_stop = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER6_STOP"); + state->u.f0.fld.apblfz.dbg_timer14_stop = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER14_STOP"); + state->u.f0.fld.apblfz.dbg_rtc_stop = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_RTC_STOP"); + state->u.f0.fld.apblfz.dbg_wwdg_stop = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_WWDG_STOP"); + state->u.f0.fld.apblfz.dbg_iwdg_stop = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_IWDG_STOP"); + state->u.f0.fld.apblfz.i2c1_smbus_timeout = cm_object_get_child_by_name(state->u.f0.reg.apblfz, "I2C1_SMBUS_TIMEOUT"); + + // APBHFZ bitfields. + state->u.f0.fld.apbhfz.dbg_timer1_stop = cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER1_STOP"); + state->u.f0.fld.apbhfz.dbg_timer15_sto = cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER15_STO"); + state->u.f0.fld.apbhfz.dbg_timer16_sto = cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER16_STO"); + state->u.f0.fld.apbhfz.dbg_timer17_sto = cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER17_STO"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dbgmcu_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dbgmcu_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dbgmcu_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dbgmcu_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dbgmcu_is_enabled(Object *obj) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dbgmcu_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DBGMCUState *state = STM32_DBGMCU_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dbgmcu_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DBGMCU)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DBGMCUState *state = STM32_DBGMCU_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DBGMCU"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_dbgmcu_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dbgmcu_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_dbgmcu_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dbgmcu_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_dbgmcu_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DBGMCUEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dbgmcu_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DBGMCU); +} + +static void stm32_dbgmcu_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dbgmcu_reset_callback; + dc->realize = stm32_dbgmcu_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dbgmcu_is_enabled; +} + +static const TypeInfo stm32_dbgmcu_type_info = { + .name = TYPE_STM32_DBGMCU, + .parent = TYPE_STM32_DBGMCU_PARENT, + .instance_init = stm32_dbgmcu_instance_init_callback, + .instance_size = sizeof(STM32DBGMCUState), + .class_init = stm32_dbgmcu_class_init_callback, + .class_size = sizeof(STM32DBGMCUClass) }; + +static void stm32_dbgmcu_register_types(void) +{ + type_register_static(&stm32_dbgmcu_type_info); +} + +type_init(stm32_dbgmcu_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/dbgmcu.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/dbgmcu.h new file mode 100644 index 0000000000..b0a8a73a83 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/dbgmcu.h @@ -0,0 +1,136 @@ +/* + * STM32 - DBGMCU (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DBGMCU_H_ +#define STM32_DBGMCU_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DBGMCU DEVICE_PATH_STM32 "DBGMCU" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DBGMCU TYPE_STM32_PREFIX "dbgmcu" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DBGMCU_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DBGMCUParentClass; +typedef PeripheralState STM32DBGMCUParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DBGMCU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DBGMCUClass, (obj), TYPE_STM32_DBGMCU) +#define STM32_DBGMCU_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DBGMCUClass, (klass), TYPE_STM32_DBGMCU) + +typedef struct { + // private: + STM32DBGMCUParentClass parent_class; + // public: + + // None, so far. +} STM32DBGMCUClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DBGMCU_STATE(obj) \ + OBJECT_CHECK(STM32DBGMCUState, (obj), TYPE_STM32_DBGMCU) + +typedef struct { + // private: + STM32DBGMCUParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 DBGMCU (Debug support) registers. + struct { + Object *idcode; // 0x0 (MCU Device ID Code Register) + Object *cr; // 0x4 (Debug MCU Configuration Register) + Object *apblfz; // 0x8 (APB Low Freeze Register) + Object *apbhfz; // 0xC (APB High Freeze Register) + } reg; + + struct { + + // IDCODE (MCU Device ID Code Register) bitfields. + struct { + Object *dev_id; // [0:11] Device Identifier + Object *div_id; // [12:15] Division Identifier + Object *rev_id; // [16:31] Revision Identifier + } idcode; + + // CR (Debug MCU Configuration Register) bitfields. + struct { + Object *dbg_stop; // [1:1] Debug Stop Mode + Object *dbg_standby; // [2:2] Debug Standby Mode + } cr; + + // APBLFZ (APB Low Freeze Register) bitfields. + struct { + Object *dbg_timer2_stop; // [0:0] Debug Timer 2 stopped when Core is halted + Object *dbg_timer3_stop; // [1:1] Debug Timer 3 stopped when Core is halted + Object *dbg_timer6_stop; // [4:4] Debug Timer 6 stopped when Core is halted + Object *dbg_timer14_stop; // [8:8] Debug Timer 14 stopped when Core is halted + Object *dbg_rtc_stop; // [10:10] Debug RTC stopped when Core is halted + Object *dbg_wwdg_stop; // [11:11] Debug Window Wachdog stopped when Core is halted + Object *dbg_iwdg_stop; // [12:12] Debug Independent Wachdog stopped when Core is halted + Object *i2c1_smbus_timeout; // [21:21] SMBUS timeout mode stopped when Core is halted + } apblfz; + + // APBHFZ (APB High Freeze Register) bitfields. + struct { + Object *dbg_timer1_stop; // [11:11] Debug Timer 1 stopped when Core is halted + Object *dbg_timer15_sto; // [16:16] Debug Timer 15 stopped when Core is halted + Object *dbg_timer16_sto; // [17:17] Debug Timer 16 stopped when Core is halted + Object *dbg_timer17_sto; // [18:18] Debug Timer 17 stopped when Core is halted + } apbhfz; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DBGMCUState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DBGMCU_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/dma1.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/dma1.c new file mode 100644 index 0000000000..7ee71deca0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/dma1.c @@ -0,0 +1,490 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.ifcr = cm_object_get_child_by_name(obj, "IFCR"); + state->u.f0.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f0.reg.cndtr1 = cm_object_get_child_by_name(obj, "CNDTR1"); + state->u.f0.reg.cpar1 = cm_object_get_child_by_name(obj, "CPAR1"); + state->u.f0.reg.cmar1 = cm_object_get_child_by_name(obj, "CMAR1"); + state->u.f0.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f0.reg.cndtr2 = cm_object_get_child_by_name(obj, "CNDTR2"); + state->u.f0.reg.cpar2 = cm_object_get_child_by_name(obj, "CPAR2"); + state->u.f0.reg.cmar2 = cm_object_get_child_by_name(obj, "CMAR2"); + state->u.f0.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f0.reg.cndtr3 = cm_object_get_child_by_name(obj, "CNDTR3"); + state->u.f0.reg.cpar3 = cm_object_get_child_by_name(obj, "CPAR3"); + state->u.f0.reg.cmar3 = cm_object_get_child_by_name(obj, "CMAR3"); + state->u.f0.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f0.reg.cndtr4 = cm_object_get_child_by_name(obj, "CNDTR4"); + state->u.f0.reg.cpar4 = cm_object_get_child_by_name(obj, "CPAR4"); + state->u.f0.reg.cmar4 = cm_object_get_child_by_name(obj, "CMAR4"); + state->u.f0.reg.ccr5 = cm_object_get_child_by_name(obj, "CCR5"); + state->u.f0.reg.cndtr5 = cm_object_get_child_by_name(obj, "CNDTR5"); + state->u.f0.reg.cpar5 = cm_object_get_child_by_name(obj, "CPAR5"); + state->u.f0.reg.cmar5 = cm_object_get_child_by_name(obj, "CMAR5"); + state->u.f0.reg.ccr6 = cm_object_get_child_by_name(obj, "CCR6"); + state->u.f0.reg.cndtr6 = cm_object_get_child_by_name(obj, "CNDTR6"); + state->u.f0.reg.cpar6 = cm_object_get_child_by_name(obj, "CPAR6"); + state->u.f0.reg.cmar6 = cm_object_get_child_by_name(obj, "CMAR6"); + state->u.f0.reg.ccr7 = cm_object_get_child_by_name(obj, "CCR7"); + state->u.f0.reg.cndtr7 = cm_object_get_child_by_name(obj, "CNDTR7"); + state->u.f0.reg.cpar7 = cm_object_get_child_by_name(obj, "CPAR7"); + state->u.f0.reg.cmar7 = cm_object_get_child_by_name(obj, "CMAR7"); + + + // ISR bitfields. + state->u.f0.fld.isr.gif1 = cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF1"); + state->u.f0.fld.isr.tcif1 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF1"); + state->u.f0.fld.isr.htif1 = cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF1"); + state->u.f0.fld.isr.teif1 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF1"); + state->u.f0.fld.isr.gif2 = cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF2"); + state->u.f0.fld.isr.tcif2 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF2"); + state->u.f0.fld.isr.htif2 = cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF2"); + state->u.f0.fld.isr.teif2 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF2"); + state->u.f0.fld.isr.gif3 = cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF3"); + state->u.f0.fld.isr.tcif3 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF3"); + state->u.f0.fld.isr.htif3 = cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF3"); + state->u.f0.fld.isr.teif3 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF3"); + state->u.f0.fld.isr.gif4 = cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF4"); + state->u.f0.fld.isr.tcif4 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF4"); + state->u.f0.fld.isr.htif4 = cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF4"); + state->u.f0.fld.isr.teif4 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF4"); + state->u.f0.fld.isr.gif5 = cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF5"); + state->u.f0.fld.isr.tcif5 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF5"); + state->u.f0.fld.isr.htif5 = cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF5"); + state->u.f0.fld.isr.teif5 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF5"); + state->u.f0.fld.isr.gif6 = cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF6"); + state->u.f0.fld.isr.tcif6 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF6"); + state->u.f0.fld.isr.htif6 = cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF6"); + state->u.f0.fld.isr.teif6 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF6"); + state->u.f0.fld.isr.gif7 = cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF7"); + state->u.f0.fld.isr.tcif7 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF7"); + state->u.f0.fld.isr.htif7 = cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF7"); + state->u.f0.fld.isr.teif7 = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF7"); + + // IFCR bitfields. + state->u.f0.fld.ifcr.cgif1 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF1"); + state->u.f0.fld.ifcr.ctcif1 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF1"); + state->u.f0.fld.ifcr.chtif1 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF1"); + state->u.f0.fld.ifcr.cteif1 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF1"); + state->u.f0.fld.ifcr.cgif2 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF2"); + state->u.f0.fld.ifcr.ctcif2 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF2"); + state->u.f0.fld.ifcr.chtif2 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF2"); + state->u.f0.fld.ifcr.cteif2 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF2"); + state->u.f0.fld.ifcr.cgif3 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF3"); + state->u.f0.fld.ifcr.ctcif3 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF3"); + state->u.f0.fld.ifcr.chtif3 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF3"); + state->u.f0.fld.ifcr.cteif3 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF3"); + state->u.f0.fld.ifcr.cgif4 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF4"); + state->u.f0.fld.ifcr.ctcif4 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF4"); + state->u.f0.fld.ifcr.chtif4 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF4"); + state->u.f0.fld.ifcr.cteif4 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF4"); + state->u.f0.fld.ifcr.cgif5 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF5"); + state->u.f0.fld.ifcr.ctcif5 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF5"); + state->u.f0.fld.ifcr.chtif5 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF5"); + state->u.f0.fld.ifcr.cteif5 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF5"); + state->u.f0.fld.ifcr.cgif6 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF6"); + state->u.f0.fld.ifcr.ctcif6 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF6"); + state->u.f0.fld.ifcr.chtif6 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF6"); + state->u.f0.fld.ifcr.cteif6 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF6"); + state->u.f0.fld.ifcr.cgif7 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF7"); + state->u.f0.fld.ifcr.ctcif7 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF7"); + state->u.f0.fld.ifcr.chtif7 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF7"); + state->u.f0.fld.ifcr.cteif7 = cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF7"); + + // CCR1 bitfields. + state->u.f0.fld.ccr1.en = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "EN"); + state->u.f0.fld.ccr1.tcie = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "TCIE"); + state->u.f0.fld.ccr1.htie = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "HTIE"); + state->u.f0.fld.ccr1.teie = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "TEIE"); + state->u.f0.fld.ccr1.dir = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "DIR"); + state->u.f0.fld.ccr1.circ = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CIRC"); + state->u.f0.fld.ccr1.pinc = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "PINC"); + state->u.f0.fld.ccr1.minc = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "MINC"); + state->u.f0.fld.ccr1.psize = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "PSIZE"); + state->u.f0.fld.ccr1.msize = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "MSIZE"); + state->u.f0.fld.ccr1.pl = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "PL"); + state->u.f0.fld.ccr1.mem2mem = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "MEM2MEM"); + + // CNDTR1 bitfields. + state->u.f0.fld.cndtr1.ndt = cm_object_get_child_by_name(state->u.f0.reg.cndtr1, "NDT"); + + // CPAR1 bitfields. + state->u.f0.fld.cpar1.pa = cm_object_get_child_by_name(state->u.f0.reg.cpar1, "PA"); + + // CMAR1 bitfields. + state->u.f0.fld.cmar1.ma = cm_object_get_child_by_name(state->u.f0.reg.cmar1, "MA"); + + // CCR2 bitfields. + state->u.f0.fld.ccr2.en = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "EN"); + state->u.f0.fld.ccr2.tcie = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "TCIE"); + state->u.f0.fld.ccr2.htie = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "HTIE"); + state->u.f0.fld.ccr2.teie = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "TEIE"); + state->u.f0.fld.ccr2.dir = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "DIR"); + state->u.f0.fld.ccr2.circ = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CIRC"); + state->u.f0.fld.ccr2.pinc = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "PINC"); + state->u.f0.fld.ccr2.minc = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "MINC"); + state->u.f0.fld.ccr2.psize = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "PSIZE"); + state->u.f0.fld.ccr2.msize = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "MSIZE"); + state->u.f0.fld.ccr2.pl = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "PL"); + state->u.f0.fld.ccr2.mem2mem = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "MEM2MEM"); + + // CNDTR2 bitfields. + state->u.f0.fld.cndtr2.ndt = cm_object_get_child_by_name(state->u.f0.reg.cndtr2, "NDT"); + + // CPAR2 bitfields. + state->u.f0.fld.cpar2.pa = cm_object_get_child_by_name(state->u.f0.reg.cpar2, "PA"); + + // CMAR2 bitfields. + state->u.f0.fld.cmar2.ma = cm_object_get_child_by_name(state->u.f0.reg.cmar2, "MA"); + + // CCR3 bitfields. + state->u.f0.fld.ccr3.en = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "EN"); + state->u.f0.fld.ccr3.tcie = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "TCIE"); + state->u.f0.fld.ccr3.htie = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "HTIE"); + state->u.f0.fld.ccr3.teie = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "TEIE"); + state->u.f0.fld.ccr3.dir = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "DIR"); + state->u.f0.fld.ccr3.circ = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CIRC"); + state->u.f0.fld.ccr3.pinc = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "PINC"); + state->u.f0.fld.ccr3.minc = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "MINC"); + state->u.f0.fld.ccr3.psize = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "PSIZE"); + state->u.f0.fld.ccr3.msize = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "MSIZE"); + state->u.f0.fld.ccr3.pl = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "PL"); + state->u.f0.fld.ccr3.mem2mem = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "MEM2MEM"); + + // CNDTR3 bitfields. + state->u.f0.fld.cndtr3.ndt = cm_object_get_child_by_name(state->u.f0.reg.cndtr3, "NDT"); + + // CPAR3 bitfields. + state->u.f0.fld.cpar3.pa = cm_object_get_child_by_name(state->u.f0.reg.cpar3, "PA"); + + // CMAR3 bitfields. + state->u.f0.fld.cmar3.ma = cm_object_get_child_by_name(state->u.f0.reg.cmar3, "MA"); + + // CCR4 bitfields. + state->u.f0.fld.ccr4.en = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "EN"); + state->u.f0.fld.ccr4.tcie = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "TCIE"); + state->u.f0.fld.ccr4.htie = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "HTIE"); + state->u.f0.fld.ccr4.teie = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "TEIE"); + state->u.f0.fld.ccr4.dir = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "DIR"); + state->u.f0.fld.ccr4.circ = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CIRC"); + state->u.f0.fld.ccr4.pinc = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "PINC"); + state->u.f0.fld.ccr4.minc = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "MINC"); + state->u.f0.fld.ccr4.psize = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "PSIZE"); + state->u.f0.fld.ccr4.msize = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "MSIZE"); + state->u.f0.fld.ccr4.pl = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "PL"); + state->u.f0.fld.ccr4.mem2mem = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "MEM2MEM"); + + // CNDTR4 bitfields. + state->u.f0.fld.cndtr4.ndt = cm_object_get_child_by_name(state->u.f0.reg.cndtr4, "NDT"); + + // CPAR4 bitfields. + state->u.f0.fld.cpar4.pa = cm_object_get_child_by_name(state->u.f0.reg.cpar4, "PA"); + + // CMAR4 bitfields. + state->u.f0.fld.cmar4.ma = cm_object_get_child_by_name(state->u.f0.reg.cmar4, "MA"); + + // CCR5 bitfields. + state->u.f0.fld.ccr5.en = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "EN"); + state->u.f0.fld.ccr5.tcie = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "TCIE"); + state->u.f0.fld.ccr5.htie = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "HTIE"); + state->u.f0.fld.ccr5.teie = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "TEIE"); + state->u.f0.fld.ccr5.dir = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "DIR"); + state->u.f0.fld.ccr5.circ = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "CIRC"); + state->u.f0.fld.ccr5.pinc = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "PINC"); + state->u.f0.fld.ccr5.minc = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "MINC"); + state->u.f0.fld.ccr5.psize = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "PSIZE"); + state->u.f0.fld.ccr5.msize = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "MSIZE"); + state->u.f0.fld.ccr5.pl = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "PL"); + state->u.f0.fld.ccr5.mem2mem = cm_object_get_child_by_name(state->u.f0.reg.ccr5, "MEM2MEM"); + + // CNDTR5 bitfields. + state->u.f0.fld.cndtr5.ndt = cm_object_get_child_by_name(state->u.f0.reg.cndtr5, "NDT"); + + // CPAR5 bitfields. + state->u.f0.fld.cpar5.pa = cm_object_get_child_by_name(state->u.f0.reg.cpar5, "PA"); + + // CMAR5 bitfields. + state->u.f0.fld.cmar5.ma = cm_object_get_child_by_name(state->u.f0.reg.cmar5, "MA"); + + // CCR6 bitfields. + state->u.f0.fld.ccr6.en = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "EN"); + state->u.f0.fld.ccr6.tcie = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "TCIE"); + state->u.f0.fld.ccr6.htie = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "HTIE"); + state->u.f0.fld.ccr6.teie = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "TEIE"); + state->u.f0.fld.ccr6.dir = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "DIR"); + state->u.f0.fld.ccr6.circ = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "CIRC"); + state->u.f0.fld.ccr6.pinc = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "PINC"); + state->u.f0.fld.ccr6.minc = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "MINC"); + state->u.f0.fld.ccr6.psize = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "PSIZE"); + state->u.f0.fld.ccr6.msize = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "MSIZE"); + state->u.f0.fld.ccr6.pl = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "PL"); + state->u.f0.fld.ccr6.mem2mem = cm_object_get_child_by_name(state->u.f0.reg.ccr6, "MEM2MEM"); + + // CNDTR6 bitfields. + state->u.f0.fld.cndtr6.ndt = cm_object_get_child_by_name(state->u.f0.reg.cndtr6, "NDT"); + + // CPAR6 bitfields. + state->u.f0.fld.cpar6.pa = cm_object_get_child_by_name(state->u.f0.reg.cpar6, "PA"); + + // CMAR6 bitfields. + state->u.f0.fld.cmar6.ma = cm_object_get_child_by_name(state->u.f0.reg.cmar6, "MA"); + + // CCR7 bitfields. + state->u.f0.fld.ccr7.en = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "EN"); + state->u.f0.fld.ccr7.tcie = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "TCIE"); + state->u.f0.fld.ccr7.htie = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "HTIE"); + state->u.f0.fld.ccr7.teie = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "TEIE"); + state->u.f0.fld.ccr7.dir = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "DIR"); + state->u.f0.fld.ccr7.circ = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "CIRC"); + state->u.f0.fld.ccr7.pinc = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "PINC"); + state->u.f0.fld.ccr7.minc = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "MINC"); + state->u.f0.fld.ccr7.psize = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "PSIZE"); + state->u.f0.fld.ccr7.msize = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "MSIZE"); + state->u.f0.fld.ccr7.pl = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "PL"); + state->u.f0.fld.ccr7.mem2mem = cm_object_get_child_by_name(state->u.f0.reg.ccr7, "MEM2MEM"); + + // CNDTR7 bitfields. + state->u.f0.fld.cndtr7.ndt = cm_object_get_child_by_name(state->u.f0.reg.cndtr7, "NDT"); + + // CPAR7 bitfields. + state->u.f0.fld.cpar7.pa = cm_object_get_child_by_name(state->u.f0.reg.cpar7, "PA"); + + // CMAR7 bitfields. + state->u.f0.fld.cmar7.ma = cm_object_get_child_by_name(state->u.f0.reg.cmar7, "MA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma_is_enabled(Object *obj) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMAState *state = STM32_DMA_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_DMA_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMAState *state = STM32_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA%dEN", + 1 + state->port_index - STM32_PORT_DMA1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA); +} + +static void stm32_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma_reset_callback; + dc->realize = stm32_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma_is_enabled; +} + +static const TypeInfo stm32_dma_type_info = { + .name = TYPE_STM32_DMA, + .parent = TYPE_STM32_DMA_PARENT, + .instance_init = stm32_dma_instance_init_callback, + .instance_size = sizeof(STM32DMAState), + .class_init = stm32_dma_class_init_callback, + .class_size = sizeof(STM32DMAClass) }; + +static void stm32_dma_register_types(void) +{ + type_register_static(&stm32_dma_type_info); +} + +type_init(stm32_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/dma1.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/dma1.h new file mode 100644 index 0000000000..9d4b28d5ad --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/dma1.h @@ -0,0 +1,421 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA_H_ +#define STM32_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMA DEVICE_PATH_STM32 "DMA" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_DMA1, + STM32_PORT_DMA2, + STM32_PORT_DMA_UNDEFINED = 0xFF, +} stm32_dma_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMA TYPE_STM32_PREFIX "dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMAParentClass; +typedef PeripheralState STM32DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMAClass, (obj), TYPE_STM32_DMA) +#define STM32_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMAClass, (klass), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentClass parent_class; + // public: + + // None, so far. +} STM32DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA_STATE(obj) \ + OBJECT_CHECK(STM32DMAState, (obj), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_dma_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 DMA (DMA controller) registers. + struct { + Object *isr; // 0x0 (DMA interrupt status register (DMA_ISR)) + Object *ifcr; // 0x4 (DMA interrupt flag clear register (DMA_IFCR)) + Object *ccr1; // 0x8 (DMA channel configuration register (DMA_CCR)) + Object *cndtr1; // 0xC (DMA channel 1 number of data register) + Object *cpar1; // 0x10 (DMA channel 1 peripheral address register) + Object *cmar1; // 0x14 (DMA channel 1 memory address register) + Object *ccr2; // 0x1C (DMA channel configuration register (DMA_CCR)) + Object *cndtr2; // 0x20 (DMA channel 2 number of data register) + Object *cpar2; // 0x24 (DMA channel 2 peripheral address register) + Object *cmar2; // 0x28 (DMA channel 2 memory address register) + Object *ccr3; // 0x30 (DMA channel configuration register (DMA_CCR)) + Object *cndtr3; // 0x34 (DMA channel 3 number of data register) + Object *cpar3; // 0x38 (DMA channel 3 peripheral address register) + Object *cmar3; // 0x3C (DMA channel 3 memory address register) + Object *ccr4; // 0x44 (DMA channel configuration register (DMA_CCR)) + Object *cndtr4; // 0x48 (DMA channel 4 number of data register) + Object *cpar4; // 0x4C (DMA channel 4 peripheral address register) + Object *cmar4; // 0x50 (DMA channel 4 memory address register) + Object *ccr5; // 0x58 (DMA channel configuration register (DMA_CCR)) + Object *cndtr5; // 0x5C (DMA channel 5 number of data register) + Object *cpar5; // 0x60 (DMA channel 5 peripheral address register) + Object *cmar5; // 0x64 (DMA channel 5 memory address register) + Object *ccr6; // 0x6C (DMA channel configuration register (DMA_CCR)) + Object *cndtr6; // 0x70 (DMA channel 6 number of data register) + Object *cpar6; // 0x74 (DMA channel 6 peripheral address register) + Object *cmar6; // 0x78 (DMA channel 6 memory address register) + Object *ccr7; // 0x80 (DMA channel configuration register (DMA_CCR)) + Object *cndtr7; // 0x84 (DMA channel 7 number of data register) + Object *cpar7; // 0x88 (DMA channel 7 peripheral address register) + Object *cmar7; // 0x8C (DMA channel 7 memory address register) + } reg; + + struct { + + // ISR (DMA interrupt status register (DMA_ISR)) bitfields. + struct { + Object *gif1; // [0:0] Channel 1 Global interrupt flag + Object *tcif1; // [1:1] Channel 1 Transfer Complete flag + Object *htif1; // [2:2] Channel 1 Half Transfer Complete flag + Object *teif1; // [3:3] Channel 1 Transfer Error flag + Object *gif2; // [4:4] Channel 2 Global interrupt flag + Object *tcif2; // [5:5] Channel 2 Transfer Complete flag + Object *htif2; // [6:6] Channel 2 Half Transfer Complete flag + Object *teif2; // [7:7] Channel 2 Transfer Error flag + Object *gif3; // [8:8] Channel 3 Global interrupt flag + Object *tcif3; // [9:9] Channel 3 Transfer Complete flag + Object *htif3; // [10:10] Channel 3 Half Transfer Complete flag + Object *teif3; // [11:11] Channel 3 Transfer Error flag + Object *gif4; // [12:12] Channel 4 Global interrupt flag + Object *tcif4; // [13:13] Channel 4 Transfer Complete flag + Object *htif4; // [14:14] Channel 4 Half Transfer Complete flag + Object *teif4; // [15:15] Channel 4 Transfer Error flag + Object *gif5; // [16:16] Channel 5 Global interrupt flag + Object *tcif5; // [17:17] Channel 5 Transfer Complete flag + Object *htif5; // [18:18] Channel 5 Half Transfer Complete flag + Object *teif5; // [19:19] Channel 5 Transfer Error flag + Object *gif6; // [20:20] Channel 6 Global interrupt flag + Object *tcif6; // [21:21] Channel 6 Transfer Complete flag + Object *htif6; // [22:22] Channel 6 Half Transfer Complete flag + Object *teif6; // [23:23] Channel 6 Transfer Error flag + Object *gif7; // [24:24] Channel 7 Global interrupt flag + Object *tcif7; // [25:25] Channel 7 Transfer Complete flag + Object *htif7; // [26:26] Channel 7 Half Transfer Complete flag + Object *teif7; // [27:27] Channel 7 Transfer Error flag + } isr; + + // IFCR (DMA interrupt flag clear register (DMA_IFCR)) bitfields. + struct { + Object *cgif1; // [0:0] Channel 1 Global interrupt clear + Object *ctcif1; // [1:1] Channel 1 Transfer Complete clear + Object *chtif1; // [2:2] Channel 1 Half Transfer clear + Object *cteif1; // [3:3] Channel 1 Transfer Error clear + Object *cgif2; // [4:4] Channel 2 Global interrupt clear + Object *ctcif2; // [5:5] Channel 2 Transfer Complete clear + Object *chtif2; // [6:6] Channel 2 Half Transfer clear + Object *cteif2; // [7:7] Channel 2 Transfer Error clear + Object *cgif3; // [8:8] Channel 3 Global interrupt clear + Object *ctcif3; // [9:9] Channel 3 Transfer Complete clear + Object *chtif3; // [10:10] Channel 3 Half Transfer clear + Object *cteif3; // [11:11] Channel 3 Transfer Error clear + Object *cgif4; // [12:12] Channel 4 Global interrupt clear + Object *ctcif4; // [13:13] Channel 4 Transfer Complete clear + Object *chtif4; // [14:14] Channel 4 Half Transfer clear + Object *cteif4; // [15:15] Channel 4 Transfer Error clear + Object *cgif5; // [16:16] Channel 5 Global interrupt clear + Object *ctcif5; // [17:17] Channel 5 Transfer Complete clear + Object *chtif5; // [18:18] Channel 5 Half Transfer clear + Object *cteif5; // [19:19] Channel 5 Transfer Error clear + Object *cgif6; // [20:20] Channel 6 Global interrupt clear + Object *ctcif6; // [21:21] Channel 6 Transfer Complete clear + Object *chtif6; // [22:22] Channel 6 Half Transfer clear + Object *cteif6; // [23:23] Channel 6 Transfer Error clear + Object *cgif7; // [24:24] Channel 7 Global interrupt clear + Object *ctcif7; // [25:25] Channel 7 Transfer Complete clear + Object *chtif7; // [26:26] Channel 7 Half Transfer clear + Object *cteif7; // [27:27] Channel 7 Transfer Error clear + } ifcr; + + // CCR1 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr1; + + // CNDTR1 (DMA channel 1 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr1; + + // CPAR1 (DMA channel 1 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar1; + + // CMAR1 (DMA channel 1 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar1; + + // CCR2 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr2; + + // CNDTR2 (DMA channel 2 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr2; + + // CPAR2 (DMA channel 2 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar2; + + // CMAR2 (DMA channel 2 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar2; + + // CCR3 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr3; + + // CNDTR3 (DMA channel 3 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr3; + + // CPAR3 (DMA channel 3 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar3; + + // CMAR3 (DMA channel 3 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar3; + + // CCR4 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr4; + + // CNDTR4 (DMA channel 4 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr4; + + // CPAR4 (DMA channel 4 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar4; + + // CMAR4 (DMA channel 4 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar4; + + // CCR5 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr5; + + // CNDTR5 (DMA channel 5 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr5; + + // CPAR5 (DMA channel 5 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar5; + + // CMAR5 (DMA channel 5 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar5; + + // CCR6 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr6; + + // CNDTR6 (DMA channel 6 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr6; + + // CPAR6 (DMA channel 6 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar6; + + // CMAR6 (DMA channel 6 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar6; + + // CCR7 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr7; + + // CNDTR7 (DMA channel 7 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr7; + + // CPAR7 (DMA channel 7 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar7; + + // CMAR7 (DMA channel 7 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar7; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/exti.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/exti.c new file mode 100644 index 0000000000..20525ad908 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/exti.c @@ -0,0 +1,384 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_exti_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.imr = cm_object_get_child_by_name(obj, "IMR"); + state->u.f0.reg.emr = cm_object_get_child_by_name(obj, "EMR"); + state->u.f0.reg.rtsr = cm_object_get_child_by_name(obj, "RTSR"); + state->u.f0.reg.ftsr = cm_object_get_child_by_name(obj, "FTSR"); + state->u.f0.reg.swier = cm_object_get_child_by_name(obj, "SWIER"); + state->u.f0.reg.pr = cm_object_get_child_by_name(obj, "PR"); + + + // IMR bitfields. + state->u.f0.fld.imr.mr0 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR0"); + state->u.f0.fld.imr.mr1 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR1"); + state->u.f0.fld.imr.mr2 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR2"); + state->u.f0.fld.imr.mr3 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR3"); + state->u.f0.fld.imr.mr4 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR4"); + state->u.f0.fld.imr.mr5 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR5"); + state->u.f0.fld.imr.mr6 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR6"); + state->u.f0.fld.imr.mr7 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR7"); + state->u.f0.fld.imr.mr8 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR8"); + state->u.f0.fld.imr.mr9 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR9"); + state->u.f0.fld.imr.mr10 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR10"); + state->u.f0.fld.imr.mr11 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR11"); + state->u.f0.fld.imr.mr12 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR12"); + state->u.f0.fld.imr.mr13 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR13"); + state->u.f0.fld.imr.mr14 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR14"); + state->u.f0.fld.imr.mr15 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR15"); + state->u.f0.fld.imr.mr16 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR16"); + state->u.f0.fld.imr.mr17 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR17"); + state->u.f0.fld.imr.mr18 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR18"); + state->u.f0.fld.imr.mr19 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR19"); + state->u.f0.fld.imr.mr20 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR20"); + state->u.f0.fld.imr.mr21 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR21"); + state->u.f0.fld.imr.mr22 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR22"); + state->u.f0.fld.imr.mr23 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR23"); + state->u.f0.fld.imr.mr24 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR24"); + state->u.f0.fld.imr.mr25 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR25"); + state->u.f0.fld.imr.mr26 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR26"); + state->u.f0.fld.imr.mr27 = cm_object_get_child_by_name(state->u.f0.reg.imr, "MR27"); + + // EMR bitfields. + state->u.f0.fld.emr.mr0 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR0"); + state->u.f0.fld.emr.mr1 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR1"); + state->u.f0.fld.emr.mr2 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR2"); + state->u.f0.fld.emr.mr3 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR3"); + state->u.f0.fld.emr.mr4 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR4"); + state->u.f0.fld.emr.mr5 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR5"); + state->u.f0.fld.emr.mr6 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR6"); + state->u.f0.fld.emr.mr7 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR7"); + state->u.f0.fld.emr.mr8 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR8"); + state->u.f0.fld.emr.mr9 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR9"); + state->u.f0.fld.emr.mr10 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR10"); + state->u.f0.fld.emr.mr11 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR11"); + state->u.f0.fld.emr.mr12 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR12"); + state->u.f0.fld.emr.mr13 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR13"); + state->u.f0.fld.emr.mr14 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR14"); + state->u.f0.fld.emr.mr15 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR15"); + state->u.f0.fld.emr.mr16 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR16"); + state->u.f0.fld.emr.mr17 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR17"); + state->u.f0.fld.emr.mr18 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR18"); + state->u.f0.fld.emr.mr19 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR19"); + state->u.f0.fld.emr.mr20 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR20"); + state->u.f0.fld.emr.mr21 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR21"); + state->u.f0.fld.emr.mr22 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR22"); + state->u.f0.fld.emr.mr23 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR23"); + state->u.f0.fld.emr.mr24 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR24"); + state->u.f0.fld.emr.mr25 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR25"); + state->u.f0.fld.emr.mr26 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR26"); + state->u.f0.fld.emr.mr27 = cm_object_get_child_by_name(state->u.f0.reg.emr, "MR27"); + + // RTSR bitfields. + state->u.f0.fld.rtsr.tr0 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR0"); + state->u.f0.fld.rtsr.tr1 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR1"); + state->u.f0.fld.rtsr.tr2 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR2"); + state->u.f0.fld.rtsr.tr3 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR3"); + state->u.f0.fld.rtsr.tr4 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR4"); + state->u.f0.fld.rtsr.tr5 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR5"); + state->u.f0.fld.rtsr.tr6 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR6"); + state->u.f0.fld.rtsr.tr7 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR7"); + state->u.f0.fld.rtsr.tr8 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR8"); + state->u.f0.fld.rtsr.tr9 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR9"); + state->u.f0.fld.rtsr.tr10 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR10"); + state->u.f0.fld.rtsr.tr11 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR11"); + state->u.f0.fld.rtsr.tr12 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR12"); + state->u.f0.fld.rtsr.tr13 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR13"); + state->u.f0.fld.rtsr.tr14 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR14"); + state->u.f0.fld.rtsr.tr15 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR15"); + state->u.f0.fld.rtsr.tr16 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR16"); + state->u.f0.fld.rtsr.tr17 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR17"); + state->u.f0.fld.rtsr.tr19 = cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR19"); + + // FTSR bitfields. + state->u.f0.fld.ftsr.tr0 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR0"); + state->u.f0.fld.ftsr.tr1 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR1"); + state->u.f0.fld.ftsr.tr2 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR2"); + state->u.f0.fld.ftsr.tr3 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR3"); + state->u.f0.fld.ftsr.tr4 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR4"); + state->u.f0.fld.ftsr.tr5 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR5"); + state->u.f0.fld.ftsr.tr6 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR6"); + state->u.f0.fld.ftsr.tr7 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR7"); + state->u.f0.fld.ftsr.tr8 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR8"); + state->u.f0.fld.ftsr.tr9 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR9"); + state->u.f0.fld.ftsr.tr10 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR10"); + state->u.f0.fld.ftsr.tr11 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR11"); + state->u.f0.fld.ftsr.tr12 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR12"); + state->u.f0.fld.ftsr.tr13 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR13"); + state->u.f0.fld.ftsr.tr14 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR14"); + state->u.f0.fld.ftsr.tr15 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR15"); + state->u.f0.fld.ftsr.tr16 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR16"); + state->u.f0.fld.ftsr.tr17 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR17"); + state->u.f0.fld.ftsr.tr19 = cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR19"); + + // SWIER bitfields. + state->u.f0.fld.swier.swier0 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER0"); + state->u.f0.fld.swier.swier1 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER1"); + state->u.f0.fld.swier.swier2 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER2"); + state->u.f0.fld.swier.swier3 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER3"); + state->u.f0.fld.swier.swier4 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER4"); + state->u.f0.fld.swier.swier5 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER5"); + state->u.f0.fld.swier.swier6 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER6"); + state->u.f0.fld.swier.swier7 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER7"); + state->u.f0.fld.swier.swier8 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER8"); + state->u.f0.fld.swier.swier9 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER9"); + state->u.f0.fld.swier.swier10 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER10"); + state->u.f0.fld.swier.swier11 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER11"); + state->u.f0.fld.swier.swier12 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER12"); + state->u.f0.fld.swier.swier13 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER13"); + state->u.f0.fld.swier.swier14 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER14"); + state->u.f0.fld.swier.swier15 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER15"); + state->u.f0.fld.swier.swier16 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER16"); + state->u.f0.fld.swier.swier17 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER17"); + state->u.f0.fld.swier.swier19 = cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER19"); + + // PR bitfields. + state->u.f0.fld.pr.pr0 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR0"); + state->u.f0.fld.pr.pr1 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR1"); + state->u.f0.fld.pr.pr2 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR2"); + state->u.f0.fld.pr.pr3 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR3"); + state->u.f0.fld.pr.pr4 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR4"); + state->u.f0.fld.pr.pr5 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR5"); + state->u.f0.fld.pr.pr6 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR6"); + state->u.f0.fld.pr.pr7 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR7"); + state->u.f0.fld.pr.pr8 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR8"); + state->u.f0.fld.pr.pr9 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR9"); + state->u.f0.fld.pr.pr10 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR10"); + state->u.f0.fld.pr.pr11 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR11"); + state->u.f0.fld.pr.pr12 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR12"); + state->u.f0.fld.pr.pr13 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR13"); + state->u.f0.fld.pr.pr14 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR14"); + state->u.f0.fld.pr.pr15 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR15"); + state->u.f0.fld.pr.pr16 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR16"); + state->u.f0.fld.pr.pr17 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR17"); + state->u.f0.fld.pr.pr19 = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR19"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_exti_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_exti_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_exti_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_exti_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_exti_is_enabled(Object *obj) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_exti_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_exti_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_EXTI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32EXTIState *state = STM32_EXTI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "EXTI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_exti_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_exti_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_exti_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_exti_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_exti_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/EXTIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_exti_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_EXTI); +} + +static void stm32_exti_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_exti_reset_callback; + dc->realize = stm32_exti_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_exti_is_enabled; +} + +static const TypeInfo stm32_exti_type_info = { + .name = TYPE_STM32_EXTI, + .parent = TYPE_STM32_EXTI_PARENT, + .instance_init = stm32_exti_instance_init_callback, + .instance_size = sizeof(STM32EXTIState), + .class_init = stm32_exti_class_init_callback, + .class_size = sizeof(STM32EXTIClass) }; + +static void stm32_exti_register_types(void) +{ + type_register_static(&stm32_exti_type_info); +} + +type_init(stm32_exti_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/exti.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/exti.h new file mode 100644 index 0000000000..86bed47ce8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/exti.h @@ -0,0 +1,261 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_EXTI_H_ +#define STM32_EXTI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_EXTI DEVICE_PATH_STM32 "EXTI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_EXTI TYPE_STM32_PREFIX "exti" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_EXTI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32EXTIParentClass; +typedef PeripheralState STM32EXTIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_EXTI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32EXTIClass, (obj), TYPE_STM32_EXTI) +#define STM32_EXTI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32EXTIClass, (klass), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentClass parent_class; + // public: + + // None, so far. +} STM32EXTIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_EXTI_STATE(obj) \ + OBJECT_CHECK(STM32EXTIState, (obj), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 EXTI (External interrupt/event controller) registers. + struct { + Object *imr; // 0x0 (Interrupt mask register (EXTI_IMR)) + Object *emr; // 0x4 (Event mask register (EXTI_EMR)) + Object *rtsr; // 0x8 (Rising Trigger selection register (EXTI_RTSR)) + Object *ftsr; // 0xC (Falling Trigger selection register (EXTI_FTSR)) + Object *swier; // 0x10 (Software interrupt event register (EXTI_SWIER)) + Object *pr; // 0x14 (Pending register (EXTI_PR)) + } reg; + + struct { + + // IMR (Interrupt mask register (EXTI_IMR)) bitfields. + struct { + Object *mr0; // [0:0] Interrupt Mask on line 0 + Object *mr1; // [1:1] Interrupt Mask on line 1 + Object *mr2; // [2:2] Interrupt Mask on line 2 + Object *mr3; // [3:3] Interrupt Mask on line 3 + Object *mr4; // [4:4] Interrupt Mask on line 4 + Object *mr5; // [5:5] Interrupt Mask on line 5 + Object *mr6; // [6:6] Interrupt Mask on line 6 + Object *mr7; // [7:7] Interrupt Mask on line 7 + Object *mr8; // [8:8] Interrupt Mask on line 8 + Object *mr9; // [9:9] Interrupt Mask on line 9 + Object *mr10; // [10:10] Interrupt Mask on line 10 + Object *mr11; // [11:11] Interrupt Mask on line 11 + Object *mr12; // [12:12] Interrupt Mask on line 12 + Object *mr13; // [13:13] Interrupt Mask on line 13 + Object *mr14; // [14:14] Interrupt Mask on line 14 + Object *mr15; // [15:15] Interrupt Mask on line 15 + Object *mr16; // [16:16] Interrupt Mask on line 16 + Object *mr17; // [17:17] Interrupt Mask on line 17 + Object *mr18; // [18:18] Interrupt Mask on line 18 + Object *mr19; // [19:19] Interrupt Mask on line 19 + Object *mr20; // [20:20] Interrupt Mask on line 20 + Object *mr21; // [21:21] Interrupt Mask on line 21 + Object *mr22; // [22:22] Interrupt Mask on line 22 + Object *mr23; // [23:23] Interrupt Mask on line 23 + Object *mr24; // [24:24] Interrupt Mask on line 24 + Object *mr25; // [25:25] Interrupt Mask on line 25 + Object *mr26; // [26:26] Interrupt Mask on line 26 + Object *mr27; // [27:27] Interrupt Mask on line 27 + } imr; + + // EMR (Event mask register (EXTI_EMR)) bitfields. + struct { + Object *mr0; // [0:0] Event Mask on line 0 + Object *mr1; // [1:1] Event Mask on line 1 + Object *mr2; // [2:2] Event Mask on line 2 + Object *mr3; // [3:3] Event Mask on line 3 + Object *mr4; // [4:4] Event Mask on line 4 + Object *mr5; // [5:5] Event Mask on line 5 + Object *mr6; // [6:6] Event Mask on line 6 + Object *mr7; // [7:7] Event Mask on line 7 + Object *mr8; // [8:8] Event Mask on line 8 + Object *mr9; // [9:9] Event Mask on line 9 + Object *mr10; // [10:10] Event Mask on line 10 + Object *mr11; // [11:11] Event Mask on line 11 + Object *mr12; // [12:12] Event Mask on line 12 + Object *mr13; // [13:13] Event Mask on line 13 + Object *mr14; // [14:14] Event Mask on line 14 + Object *mr15; // [15:15] Event Mask on line 15 + Object *mr16; // [16:16] Event Mask on line 16 + Object *mr17; // [17:17] Event Mask on line 17 + Object *mr18; // [18:18] Event Mask on line 18 + Object *mr19; // [19:19] Event Mask on line 19 + Object *mr20; // [20:20] Event Mask on line 20 + Object *mr21; // [21:21] Event Mask on line 21 + Object *mr22; // [22:22] Event Mask on line 22 + Object *mr23; // [23:23] Event Mask on line 23 + Object *mr24; // [24:24] Event Mask on line 24 + Object *mr25; // [25:25] Event Mask on line 25 + Object *mr26; // [26:26] Event Mask on line 26 + Object *mr27; // [27:27] Event Mask on line 27 + } emr; + + // RTSR (Rising Trigger selection register (EXTI_RTSR)) bitfields. + struct { + Object *tr0; // [0:0] Rising trigger event configuration of line 0 + Object *tr1; // [1:1] Rising trigger event configuration of line 1 + Object *tr2; // [2:2] Rising trigger event configuration of line 2 + Object *tr3; // [3:3] Rising trigger event configuration of line 3 + Object *tr4; // [4:4] Rising trigger event configuration of line 4 + Object *tr5; // [5:5] Rising trigger event configuration of line 5 + Object *tr6; // [6:6] Rising trigger event configuration of line 6 + Object *tr7; // [7:7] Rising trigger event configuration of line 7 + Object *tr8; // [8:8] Rising trigger event configuration of line 8 + Object *tr9; // [9:9] Rising trigger event configuration of line 9 + Object *tr10; // [10:10] Rising trigger event configuration of line 10 + Object *tr11; // [11:11] Rising trigger event configuration of line 11 + Object *tr12; // [12:12] Rising trigger event configuration of line 12 + Object *tr13; // [13:13] Rising trigger event configuration of line 13 + Object *tr14; // [14:14] Rising trigger event configuration of line 14 + Object *tr15; // [15:15] Rising trigger event configuration of line 15 + Object *tr16; // [16:16] Rising trigger event configuration of line 16 + Object *tr17; // [17:17] Rising trigger event configuration of line 17 + Object *tr19; // [19:19] Rising trigger event configuration of line 19 + } rtsr; + + // FTSR (Falling Trigger selection register (EXTI_FTSR)) bitfields. + struct { + Object *tr0; // [0:0] Falling trigger event configuration of line 0 + Object *tr1; // [1:1] Falling trigger event configuration of line 1 + Object *tr2; // [2:2] Falling trigger event configuration of line 2 + Object *tr3; // [3:3] Falling trigger event configuration of line 3 + Object *tr4; // [4:4] Falling trigger event configuration of line 4 + Object *tr5; // [5:5] Falling trigger event configuration of line 5 + Object *tr6; // [6:6] Falling trigger event configuration of line 6 + Object *tr7; // [7:7] Falling trigger event configuration of line 7 + Object *tr8; // [8:8] Falling trigger event configuration of line 8 + Object *tr9; // [9:9] Falling trigger event configuration of line 9 + Object *tr10; // [10:10] Falling trigger event configuration of line 10 + Object *tr11; // [11:11] Falling trigger event configuration of line 11 + Object *tr12; // [12:12] Falling trigger event configuration of line 12 + Object *tr13; // [13:13] Falling trigger event configuration of line 13 + Object *tr14; // [14:14] Falling trigger event configuration of line 14 + Object *tr15; // [15:15] Falling trigger event configuration of line 15 + Object *tr16; // [16:16] Falling trigger event configuration of line 16 + Object *tr17; // [17:17] Falling trigger event configuration of line 17 + Object *tr19; // [19:19] Falling trigger event configuration of line 19 + } ftsr; + + // SWIER (Software interrupt event register (EXTI_SWIER)) bitfields. + struct { + Object *swier0; // [0:0] Software Interrupt on line 0 + Object *swier1; // [1:1] Software Interrupt on line 1 + Object *swier2; // [2:2] Software Interrupt on line 2 + Object *swier3; // [3:3] Software Interrupt on line 3 + Object *swier4; // [4:4] Software Interrupt on line 4 + Object *swier5; // [5:5] Software Interrupt on line 5 + Object *swier6; // [6:6] Software Interrupt on line 6 + Object *swier7; // [7:7] Software Interrupt on line 7 + Object *swier8; // [8:8] Software Interrupt on line 8 + Object *swier9; // [9:9] Software Interrupt on line 9 + Object *swier10; // [10:10] Software Interrupt on line 10 + Object *swier11; // [11:11] Software Interrupt on line 11 + Object *swier12; // [12:12] Software Interrupt on line 12 + Object *swier13; // [13:13] Software Interrupt on line 13 + Object *swier14; // [14:14] Software Interrupt on line 14 + Object *swier15; // [15:15] Software Interrupt on line 15 + Object *swier16; // [16:16] Software Interrupt on line 16 + Object *swier17; // [17:17] Software Interrupt on line 17 + Object *swier19; // [19:19] Software Interrupt on line 19 + } swier; + + // PR (Pending register (EXTI_PR)) bitfields. + struct { + Object *pr0; // [0:0] Pending bit 0 + Object *pr1; // [1:1] Pending bit 1 + Object *pr2; // [2:2] Pending bit 2 + Object *pr3; // [3:3] Pending bit 3 + Object *pr4; // [4:4] Pending bit 4 + Object *pr5; // [5:5] Pending bit 5 + Object *pr6; // [6:6] Pending bit 6 + Object *pr7; // [7:7] Pending bit 7 + Object *pr8; // [8:8] Pending bit 8 + Object *pr9; // [9:9] Pending bit 9 + Object *pr10; // [10:10] Pending bit 10 + Object *pr11; // [11:11] Pending bit 11 + Object *pr12; // [12:12] Pending bit 12 + Object *pr13; // [13:13] Pending bit 13 + Object *pr14; // [14:14] Pending bit 14 + Object *pr15; // [15:15] Pending bit 15 + Object *pr16; // [16:16] Pending bit 16 + Object *pr17; // [17:17] Pending bit 17 + Object *pr19; // [19:19] Pending bit 19 + } pr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32EXTIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_EXTI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/flash.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/flash.c new file mode 100644 index 0000000000..91effed77f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/flash.c @@ -0,0 +1,290 @@ +/* + * STM32 - Flash (Flash) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_flash_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FlashState *state = STM32_Flash_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.acr = cm_object_get_child_by_name(obj, "ACR"); + state->u.f0.reg.keyr = cm_object_get_child_by_name(obj, "KEYR"); + state->u.f0.reg.optkeyr = cm_object_get_child_by_name(obj, "OPTKEYR"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.ar = cm_object_get_child_by_name(obj, "AR"); + state->u.f0.reg.obr = cm_object_get_child_by_name(obj, "OBR"); + state->u.f0.reg.wrpr = cm_object_get_child_by_name(obj, "WRPR"); + + + // ACR bitfields. + state->u.f0.fld.acr.latency = cm_object_get_child_by_name(state->u.f0.reg.acr, "LATENCY"); + state->u.f0.fld.acr.prftbe = cm_object_get_child_by_name(state->u.f0.reg.acr, "PRFTBE"); + state->u.f0.fld.acr.prftbs = cm_object_get_child_by_name(state->u.f0.reg.acr, "PRFTBS"); + + // KEYR bitfields. + state->u.f0.fld.keyr.fkeyr = cm_object_get_child_by_name(state->u.f0.reg.keyr, "FKEYR"); + + // OPTKEYR bitfields. + state->u.f0.fld.optkeyr.optkeyr = cm_object_get_child_by_name(state->u.f0.reg.optkeyr, "OPTKEYR"); + + // SR bitfields. + state->u.f0.fld.sr.bsy = cm_object_get_child_by_name(state->u.f0.reg.sr, "BSY"); + state->u.f0.fld.sr.pgerr = cm_object_get_child_by_name(state->u.f0.reg.sr, "PGERR"); + state->u.f0.fld.sr.wrprt = cm_object_get_child_by_name(state->u.f0.reg.sr, "WRPRT"); + state->u.f0.fld.sr.eop = cm_object_get_child_by_name(state->u.f0.reg.sr, "EOP"); + + // CR bitfields. + state->u.f0.fld.cr.pg = cm_object_get_child_by_name(state->u.f0.reg.cr, "PG"); + state->u.f0.fld.cr.per = cm_object_get_child_by_name(state->u.f0.reg.cr, "PER"); + state->u.f0.fld.cr.mer = cm_object_get_child_by_name(state->u.f0.reg.cr, "MER"); + state->u.f0.fld.cr.optpg = cm_object_get_child_by_name(state->u.f0.reg.cr, "OPTPG"); + state->u.f0.fld.cr.opter = cm_object_get_child_by_name(state->u.f0.reg.cr, "OPTER"); + state->u.f0.fld.cr.strt = cm_object_get_child_by_name(state->u.f0.reg.cr, "STRT"); + state->u.f0.fld.cr.lock = cm_object_get_child_by_name(state->u.f0.reg.cr, "LOCK"); + state->u.f0.fld.cr.optwre = cm_object_get_child_by_name(state->u.f0.reg.cr, "OPTWRE"); + state->u.f0.fld.cr.errie = cm_object_get_child_by_name(state->u.f0.reg.cr, "ERRIE"); + state->u.f0.fld.cr.eopie = cm_object_get_child_by_name(state->u.f0.reg.cr, "EOPIE"); + state->u.f0.fld.cr.force_optload = cm_object_get_child_by_name(state->u.f0.reg.cr, "FORCE_OPTLOAD"); + + // AR bitfields. + state->u.f0.fld.ar.far_ = cm_object_get_child_by_name(state->u.f0.reg.ar, "FAR"); + + // OBR bitfields. + state->u.f0.fld.obr.opterr = cm_object_get_child_by_name(state->u.f0.reg.obr, "OPTERR"); + state->u.f0.fld.obr.level1_prot = cm_object_get_child_by_name(state->u.f0.reg.obr, "LEVEL1_PROT"); + state->u.f0.fld.obr.level2_prot = cm_object_get_child_by_name(state->u.f0.reg.obr, "LEVEL2_PROT"); + state->u.f0.fld.obr.wdg_sw = cm_object_get_child_by_name(state->u.f0.reg.obr, "WDG_SW"); + state->u.f0.fld.obr.nrst_stop = cm_object_get_child_by_name(state->u.f0.reg.obr, "nRST_STOP"); + state->u.f0.fld.obr.nrst_stdby = cm_object_get_child_by_name(state->u.f0.reg.obr, "nRST_STDBY"); + state->u.f0.fld.obr.boot1 = cm_object_get_child_by_name(state->u.f0.reg.obr, "BOOT1"); + state->u.f0.fld.obr.vdda_monitor = cm_object_get_child_by_name(state->u.f0.reg.obr, "VDDA_MONITOR"); + state->u.f0.fld.obr.data0 = cm_object_get_child_by_name(state->u.f0.reg.obr, "Data0"); + state->u.f0.fld.obr.data1 = cm_object_get_child_by_name(state->u.f0.reg.obr, "Data1"); + + // WRPR bitfields. + state->u.f0.fld.wrpr.wrp = cm_object_get_child_by_name(state->u.f0.reg.wrpr, "WRP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_flash_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_flash_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_flash_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_flash_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_flash_is_enabled(Object *obj) +{ + STM32FlashState *state = STM32_Flash_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_flash_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FlashState *state = STM32_Flash_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_flash_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Flash)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FlashState *state = STM32_Flash_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Flash"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_flash_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_flash_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_flash_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_flash_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_flash_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FlashEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_flash_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Flash); +} + +static void stm32_flash_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_flash_reset_callback; + dc->realize = stm32_flash_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_flash_is_enabled; +} + +static const TypeInfo stm32_flash_type_info = { + .name = TYPE_STM32_Flash, + .parent = TYPE_STM32_Flash_PARENT, + .instance_init = stm32_flash_instance_init_callback, + .instance_size = sizeof(STM32FlashState), + .class_init = stm32_flash_class_init_callback, + .class_size = sizeof(STM32FlashClass) }; + +static void stm32_flash_register_types(void) +{ + type_register_static(&stm32_flash_type_info); +} + +type_init(stm32_flash_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/flash.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/flash.h new file mode 100644 index 0000000000..1828e93d1a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/flash.h @@ -0,0 +1,171 @@ +/* + * STM32 - Flash (Flash) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Flash_H_ +#define STM32_Flash_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Flash DEVICE_PATH_STM32 "Flash" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Flash TYPE_STM32_PREFIX "flash" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Flash_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FlashParentClass; +typedef PeripheralState STM32FlashParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Flash_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FlashClass, (obj), TYPE_STM32_Flash) +#define STM32_Flash_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FlashClass, (klass), TYPE_STM32_Flash) + +typedef struct { + // private: + STM32FlashParentClass parent_class; + // public: + + // None, so far. +} STM32FlashClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Flash_STATE(obj) \ + OBJECT_CHECK(STM32FlashState, (obj), TYPE_STM32_Flash) + +typedef struct { + // private: + STM32FlashParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 Flash (Flash) registers. + struct { + Object *acr; // 0x0 (Flash access control register) + Object *keyr; // 0x4 (Flash key register) + Object *optkeyr; // 0x8 (Flash option key register) + Object *sr; // 0xC (Flash status register) + Object *cr; // 0x10 (Flash control register) + Object *ar; // 0x14 (Flash address register) + Object *obr; // 0x1C (Option byte register) + Object *wrpr; // 0x20 (Write protection register) + } reg; + + struct { + + // ACR (Flash access control register) bitfields. + struct { + Object *latency; // [0:2] LATENCY + Object *prftbe; // [4:4] PRFTBE + Object *prftbs; // [5:5] PRFTBS + } acr; + + // KEYR (Flash key register) bitfields. + struct { + Object *fkeyr; // [0:31] Flash Key + } keyr; + + // OPTKEYR (Flash option key register) bitfields. + struct { + Object *optkeyr; // [0:31] Option byte key + } optkeyr; + + // SR (Flash status register) bitfields. + struct { + Object *bsy; // [0:0] Busy + Object *pgerr; // [2:2] Programming error + Object *wrprt; // [4:4] Write protection error + Object *eop; // [5:5] End of operation + } sr; + + // CR (Flash control register) bitfields. + struct { + Object *pg; // [0:0] Programming + Object *per; // [1:1] Page erase + Object *mer; // [2:2] Mass erase + Object *optpg; // [4:4] Option byte programming + Object *opter; // [5:5] Option byte erase + Object *strt; // [6:6] Start + Object *lock; // [7:7] Lock + Object *optwre; // [9:9] Option bytes write enable + Object *errie; // [10:10] Error interrupt enable + Object *eopie; // [12:12] End of operation interrupt enable + Object *force_optload; // [13:13] Force option byte loading + } cr; + + // AR (Flash address register) bitfields. + struct { + Object *far_; // [0:31] Flash address + } ar; + + // OBR (Option byte register) bitfields. + struct { + Object *opterr; // [0:0] Option byte error + Object *level1_prot; // [1:1] Level 1 protection status + Object *level2_prot; // [2:2] Level 2 protection status + Object *wdg_sw; // [8:8] WDG_SW + Object *nrst_stop; // [9:9] NRST_STOP + Object *nrst_stdby; // [10:10] NRST_STDBY + Object *boot1; // [12:12] BOOT1 + Object *vdda_monitor; // [13:13] VDDA_MONITOR + Object *data0; // [16:23] Data0 + Object *data1; // [24:31] Data1 + } obr; + + // WRPR (Write protection register) bitfields. + struct { + Object *wrp; // [0:31] Write protect + } wrpr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FlashState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Flash_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/gpioa.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpioa.c new file mode 100644 index 0000000000..15aa0acf65 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpioa.c @@ -0,0 +1,449 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f0.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f0.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f0.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f0.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f0.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f0.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f0.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f0.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f0.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + state->u.f0.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + + + // MODER bitfields. + state->u.f0.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER0"); + state->u.f0.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER1"); + state->u.f0.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER2"); + state->u.f0.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER3"); + state->u.f0.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER4"); + state->u.f0.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER5"); + state->u.f0.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER6"); + state->u.f0.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER7"); + state->u.f0.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER8"); + state->u.f0.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER9"); + state->u.f0.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER10"); + state->u.f0.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER11"); + state->u.f0.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER12"); + state->u.f0.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER13"); + state->u.f0.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER14"); + state->u.f0.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f0.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT0"); + state->u.f0.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT1"); + state->u.f0.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT2"); + state->u.f0.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT3"); + state->u.f0.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT4"); + state->u.f0.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT5"); + state->u.f0.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT6"); + state->u.f0.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT7"); + state->u.f0.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT8"); + state->u.f0.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT9"); + state->u.f0.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT10"); + state->u.f0.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT11"); + state->u.f0.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT12"); + state->u.f0.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT13"); + state->u.f0.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT14"); + state->u.f0.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f0.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR0"); + state->u.f0.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR1"); + state->u.f0.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR2"); + state->u.f0.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR3"); + state->u.f0.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR4"); + state->u.f0.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR5"); + state->u.f0.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR6"); + state->u.f0.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR7"); + state->u.f0.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR8"); + state->u.f0.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR9"); + state->u.f0.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR10"); + state->u.f0.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR11"); + state->u.f0.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR12"); + state->u.f0.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR13"); + state->u.f0.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR14"); + state->u.f0.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f0.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR0"); + state->u.f0.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR1"); + state->u.f0.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR2"); + state->u.f0.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR3"); + state->u.f0.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR4"); + state->u.f0.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR5"); + state->u.f0.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR6"); + state->u.f0.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR7"); + state->u.f0.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR8"); + state->u.f0.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR9"); + state->u.f0.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR10"); + state->u.f0.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR11"); + state->u.f0.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR12"); + state->u.f0.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR13"); + state->u.f0.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR14"); + state->u.f0.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f0.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR0"); + state->u.f0.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR1"); + state->u.f0.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR2"); + state->u.f0.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR3"); + state->u.f0.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR4"); + state->u.f0.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR5"); + state->u.f0.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR6"); + state->u.f0.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR7"); + state->u.f0.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR8"); + state->u.f0.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR9"); + state->u.f0.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR10"); + state->u.f0.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR11"); + state->u.f0.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR12"); + state->u.f0.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR13"); + state->u.f0.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR14"); + state->u.f0.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f0.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR0"); + state->u.f0.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR1"); + state->u.f0.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR2"); + state->u.f0.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR3"); + state->u.f0.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR4"); + state->u.f0.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR5"); + state->u.f0.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR6"); + state->u.f0.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR7"); + state->u.f0.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR8"); + state->u.f0.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR9"); + state->u.f0.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR10"); + state->u.f0.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR11"); + state->u.f0.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR12"); + state->u.f0.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR13"); + state->u.f0.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR14"); + state->u.f0.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f0.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS0"); + state->u.f0.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS1"); + state->u.f0.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS2"); + state->u.f0.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS3"); + state->u.f0.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS4"); + state->u.f0.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS5"); + state->u.f0.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS6"); + state->u.f0.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS7"); + state->u.f0.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS8"); + state->u.f0.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS9"); + state->u.f0.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS10"); + state->u.f0.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS11"); + state->u.f0.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS12"); + state->u.f0.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS13"); + state->u.f0.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS14"); + state->u.f0.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS15"); + state->u.f0.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR0"); + state->u.f0.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR1"); + state->u.f0.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR2"); + state->u.f0.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR3"); + state->u.f0.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR4"); + state->u.f0.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR5"); + state->u.f0.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR6"); + state->u.f0.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR7"); + state->u.f0.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR8"); + state->u.f0.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR9"); + state->u.f0.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR10"); + state->u.f0.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR11"); + state->u.f0.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR12"); + state->u.f0.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR13"); + state->u.f0.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR14"); + state->u.f0.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f0.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK0"); + state->u.f0.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK1"); + state->u.f0.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK2"); + state->u.f0.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK3"); + state->u.f0.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK4"); + state->u.f0.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK5"); + state->u.f0.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK6"); + state->u.f0.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK7"); + state->u.f0.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK8"); + state->u.f0.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK9"); + state->u.f0.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK10"); + state->u.f0.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK11"); + state->u.f0.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK12"); + state->u.f0.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK13"); + state->u.f0.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK14"); + state->u.f0.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK15"); + state->u.f0.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f0.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL0"); + state->u.f0.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL1"); + state->u.f0.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL2"); + state->u.f0.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL3"); + state->u.f0.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL4"); + state->u.f0.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL5"); + state->u.f0.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL6"); + state->u.f0.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f0.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH8"); + state->u.f0.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH9"); + state->u.f0.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH10"); + state->u.f0.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH11"); + state->u.f0.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH12"); + state->u.f0.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH13"); + state->u.f0.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH14"); + state->u.f0.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH15"); + + // BRR bitfields. + state->u.f0.fld.brr.br0 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR0"); + state->u.f0.fld.brr.br1 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR1"); + state->u.f0.fld.brr.br2 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR2"); + state->u.f0.fld.brr.br3 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR3"); + state->u.f0.fld.brr.br4 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR4"); + state->u.f0.fld.brr.br5 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR5"); + state->u.f0.fld.brr.br6 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR6"); + state->u.f0.fld.brr.br7 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR7"); + state->u.f0.fld.brr.br8 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR8"); + state->u.f0.fld.brr.br9 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR9"); + state->u.f0.fld.brr.br10 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR10"); + state->u.f0.fld.brr.br11 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR11"); + state->u.f0.fld.brr.br12 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR12"); + state->u.f0.fld.brr.br13 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR13"); + state->u.f0.fld.brr.br14 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR14"); + state->u.f0.fld.brr.br15 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/gpioa.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpioa.h new file mode 100644 index 0000000000..4ab16fcdc9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpioa.h @@ -0,0 +1,346 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + Object *brr; // 0x28 (Port bit reset register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + + // BRR (Port bit reset register) bitfields. + struct { + Object *br0; // [0:0] Port x Reset bit y + Object *br1; // [1:1] Port x Reset bit y + Object *br2; // [2:2] Port x Reset bit y + Object *br3; // [3:3] Port x Reset bit y + Object *br4; // [4:4] Port x Reset bit y + Object *br5; // [5:5] Port x Reset bit y + Object *br6; // [6:6] Port x Reset bit y + Object *br7; // [7:7] Port x Reset bit y + Object *br8; // [8:8] Port x Reset bit y + Object *br9; // [9:9] Port x Reset bit y + Object *br10; // [10:10] Port x Reset bit y + Object *br11; // [11:11] Port x Reset bit y + Object *br12; // [12:12] Port x Reset bit y + Object *br13; // [13:13] Port x Reset bit y + Object *br14; // [14:14] Port x Reset bit y + Object *br15; // [15:15] Port x Reset bit y + } brr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/gpiof.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpiof.c new file mode 100644 index 0000000000..15aa0acf65 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpiof.c @@ -0,0 +1,449 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f0.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f0.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f0.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f0.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f0.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f0.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f0.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f0.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f0.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + state->u.f0.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + + + // MODER bitfields. + state->u.f0.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER0"); + state->u.f0.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER1"); + state->u.f0.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER2"); + state->u.f0.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER3"); + state->u.f0.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER4"); + state->u.f0.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER5"); + state->u.f0.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER6"); + state->u.f0.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER7"); + state->u.f0.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER8"); + state->u.f0.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER9"); + state->u.f0.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER10"); + state->u.f0.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER11"); + state->u.f0.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER12"); + state->u.f0.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER13"); + state->u.f0.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER14"); + state->u.f0.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f0.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT0"); + state->u.f0.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT1"); + state->u.f0.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT2"); + state->u.f0.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT3"); + state->u.f0.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT4"); + state->u.f0.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT5"); + state->u.f0.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT6"); + state->u.f0.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT7"); + state->u.f0.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT8"); + state->u.f0.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT9"); + state->u.f0.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT10"); + state->u.f0.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT11"); + state->u.f0.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT12"); + state->u.f0.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT13"); + state->u.f0.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT14"); + state->u.f0.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f0.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR0"); + state->u.f0.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR1"); + state->u.f0.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR2"); + state->u.f0.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR3"); + state->u.f0.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR4"); + state->u.f0.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR5"); + state->u.f0.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR6"); + state->u.f0.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR7"); + state->u.f0.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR8"); + state->u.f0.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR9"); + state->u.f0.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR10"); + state->u.f0.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR11"); + state->u.f0.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR12"); + state->u.f0.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR13"); + state->u.f0.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR14"); + state->u.f0.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f0.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR0"); + state->u.f0.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR1"); + state->u.f0.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR2"); + state->u.f0.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR3"); + state->u.f0.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR4"); + state->u.f0.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR5"); + state->u.f0.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR6"); + state->u.f0.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR7"); + state->u.f0.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR8"); + state->u.f0.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR9"); + state->u.f0.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR10"); + state->u.f0.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR11"); + state->u.f0.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR12"); + state->u.f0.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR13"); + state->u.f0.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR14"); + state->u.f0.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f0.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR0"); + state->u.f0.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR1"); + state->u.f0.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR2"); + state->u.f0.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR3"); + state->u.f0.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR4"); + state->u.f0.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR5"); + state->u.f0.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR6"); + state->u.f0.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR7"); + state->u.f0.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR8"); + state->u.f0.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR9"); + state->u.f0.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR10"); + state->u.f0.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR11"); + state->u.f0.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR12"); + state->u.f0.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR13"); + state->u.f0.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR14"); + state->u.f0.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f0.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR0"); + state->u.f0.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR1"); + state->u.f0.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR2"); + state->u.f0.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR3"); + state->u.f0.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR4"); + state->u.f0.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR5"); + state->u.f0.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR6"); + state->u.f0.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR7"); + state->u.f0.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR8"); + state->u.f0.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR9"); + state->u.f0.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR10"); + state->u.f0.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR11"); + state->u.f0.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR12"); + state->u.f0.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR13"); + state->u.f0.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR14"); + state->u.f0.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f0.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS0"); + state->u.f0.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS1"); + state->u.f0.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS2"); + state->u.f0.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS3"); + state->u.f0.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS4"); + state->u.f0.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS5"); + state->u.f0.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS6"); + state->u.f0.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS7"); + state->u.f0.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS8"); + state->u.f0.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS9"); + state->u.f0.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS10"); + state->u.f0.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS11"); + state->u.f0.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS12"); + state->u.f0.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS13"); + state->u.f0.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS14"); + state->u.f0.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS15"); + state->u.f0.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR0"); + state->u.f0.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR1"); + state->u.f0.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR2"); + state->u.f0.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR3"); + state->u.f0.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR4"); + state->u.f0.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR5"); + state->u.f0.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR6"); + state->u.f0.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR7"); + state->u.f0.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR8"); + state->u.f0.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR9"); + state->u.f0.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR10"); + state->u.f0.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR11"); + state->u.f0.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR12"); + state->u.f0.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR13"); + state->u.f0.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR14"); + state->u.f0.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f0.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK0"); + state->u.f0.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK1"); + state->u.f0.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK2"); + state->u.f0.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK3"); + state->u.f0.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK4"); + state->u.f0.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK5"); + state->u.f0.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK6"); + state->u.f0.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK7"); + state->u.f0.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK8"); + state->u.f0.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK9"); + state->u.f0.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK10"); + state->u.f0.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK11"); + state->u.f0.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK12"); + state->u.f0.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK13"); + state->u.f0.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK14"); + state->u.f0.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK15"); + state->u.f0.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f0.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL0"); + state->u.f0.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL1"); + state->u.f0.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL2"); + state->u.f0.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL3"); + state->u.f0.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL4"); + state->u.f0.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL5"); + state->u.f0.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL6"); + state->u.f0.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f0.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH8"); + state->u.f0.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH9"); + state->u.f0.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH10"); + state->u.f0.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH11"); + state->u.f0.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH12"); + state->u.f0.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH13"); + state->u.f0.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH14"); + state->u.f0.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH15"); + + // BRR bitfields. + state->u.f0.fld.brr.br0 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR0"); + state->u.f0.fld.brr.br1 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR1"); + state->u.f0.fld.brr.br2 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR2"); + state->u.f0.fld.brr.br3 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR3"); + state->u.f0.fld.brr.br4 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR4"); + state->u.f0.fld.brr.br5 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR5"); + state->u.f0.fld.brr.br6 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR6"); + state->u.f0.fld.brr.br7 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR7"); + state->u.f0.fld.brr.br8 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR8"); + state->u.f0.fld.brr.br9 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR9"); + state->u.f0.fld.brr.br10 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR10"); + state->u.f0.fld.brr.br11 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR11"); + state->u.f0.fld.brr.br12 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR12"); + state->u.f0.fld.brr.br13 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR13"); + state->u.f0.fld.brr.br14 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR14"); + state->u.f0.fld.brr.br15 = cm_object_get_child_by_name(state->u.f0.reg.brr, "BR15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/gpiof.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpiof.h new file mode 100644 index 0000000000..50be6a9569 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/gpiof.h @@ -0,0 +1,346 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + Object *brr; // 0x28 (Port bit reset register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bit 0 + Object *ot1; // [1:1] Port x configuration bit 1 + Object *ot2; // [2:2] Port x configuration bit 2 + Object *ot3; // [3:3] Port x configuration bit 3 + Object *ot4; // [4:4] Port x configuration bit 4 + Object *ot5; // [5:5] Port x configuration bit 5 + Object *ot6; // [6:6] Port x configuration bit 6 + Object *ot7; // [7:7] Port x configuration bit 7 + Object *ot8; // [8:8] Port x configuration bit 8 + Object *ot9; // [9:9] Port x configuration bit 9 + Object *ot10; // [10:10] Port x configuration bit 10 + Object *ot11; // [11:11] Port x configuration bit 11 + Object *ot12; // [12:12] Port x configuration bit 12 + Object *ot13; // [13:13] Port x configuration bit 13 + Object *ot14; // [14:14] Port x configuration bit 14 + Object *ot15; // [15:15] Port x configuration bit 15 + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + + // BRR (Port bit reset register) bitfields. + struct { + Object *br0; // [0:0] Port x Reset bit y + Object *br1; // [1:1] Port x Reset bit y + Object *br2; // [2:2] Port x Reset bit y + Object *br3; // [3:3] Port x Reset bit y + Object *br4; // [4:4] Port x Reset bit y + Object *br5; // [5:5] Port x Reset bit y + Object *br6; // [6:6] Port x Reset bit y + Object *br7; // [7:7] Port x Reset bit y + Object *br8; // [8:8] Port x Reset bit y + Object *br9; // [9:9] Port x Reset bit y + Object *br10; // [10:10] Port x Reset bit y + Object *br11; // [11:11] Port x Reset bit y + Object *br12; // [12:12] Port x Reset bit y + Object *br13; // [13:13] Port x Reset bit y + Object *br14; // [14:14] Port x Reset bit y + Object *br15; // [15:15] Port x Reset bit y + } brr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/i2c1.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/i2c1.c new file mode 100644 index 0000000000..ac3605e5fd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/i2c1.c @@ -0,0 +1,353 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_i2c_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.oar1 = cm_object_get_child_by_name(obj, "OAR1"); + state->u.f0.reg.oar2 = cm_object_get_child_by_name(obj, "OAR2"); + state->u.f0.reg.timingr = cm_object_get_child_by_name(obj, "TIMINGR"); + state->u.f0.reg.timeoutr = cm_object_get_child_by_name(obj, "TIMEOUTR"); + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f0.reg.pecr = cm_object_get_child_by_name(obj, "PECR"); + state->u.f0.reg.rxdr = cm_object_get_child_by_name(obj, "RXDR"); + state->u.f0.reg.txdr = cm_object_get_child_by_name(obj, "TXDR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.pe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "PE"); + state->u.f0.fld.cr1.txie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "TXIE"); + state->u.f0.fld.cr1.rxie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXIE"); + state->u.f0.fld.cr1.addrie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ADDRIE"); + state->u.f0.fld.cr1.nackie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "NACKIE"); + state->u.f0.fld.cr1.stopie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "STOPIE"); + state->u.f0.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "TCIE"); + state->u.f0.fld.cr1.errie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ERRIE"); + state->u.f0.fld.cr1.dnf = cm_object_get_child_by_name(state->u.f0.reg.cr1, "DNF"); + state->u.f0.fld.cr1.anfoff = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ANFOFF"); + state->u.f0.fld.cr1.swrst = cm_object_get_child_by_name(state->u.f0.reg.cr1, "SWRST"); + state->u.f0.fld.cr1.txdmaen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "TXDMAEN"); + state->u.f0.fld.cr1.rxdmaen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXDMAEN"); + state->u.f0.fld.cr1.sbc = cm_object_get_child_by_name(state->u.f0.reg.cr1, "SBC"); + state->u.f0.fld.cr1.nostretch = cm_object_get_child_by_name(state->u.f0.reg.cr1, "NOSTRETCH"); + state->u.f0.fld.cr1.wupen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "WUPEN"); + state->u.f0.fld.cr1.gcen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "GCEN"); + state->u.f0.fld.cr1.smbhen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "SMBHEN"); + state->u.f0.fld.cr1.smbden = cm_object_get_child_by_name(state->u.f0.reg.cr1, "SMBDEN"); + state->u.f0.fld.cr1.alerten = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ALERTEN"); + state->u.f0.fld.cr1.pecen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "PECEN"); + + // CR2 bitfields. + state->u.f0.fld.cr2.sadd0 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "SADD0"); + state->u.f0.fld.cr2.sadd1 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "SADD1"); + state->u.f0.fld.cr2.sadd8 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "SADD8"); + state->u.f0.fld.cr2.rd_wrn = cm_object_get_child_by_name(state->u.f0.reg.cr2, "RD_WRN"); + state->u.f0.fld.cr2.add10 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADD10"); + state->u.f0.fld.cr2.head10r = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HEAD10R"); + state->u.f0.fld.cr2.start = cm_object_get_child_by_name(state->u.f0.reg.cr2, "START"); + state->u.f0.fld.cr2.stop = cm_object_get_child_by_name(state->u.f0.reg.cr2, "STOP"); + state->u.f0.fld.cr2.nack = cm_object_get_child_by_name(state->u.f0.reg.cr2, "NACK"); + state->u.f0.fld.cr2.nbytes = cm_object_get_child_by_name(state->u.f0.reg.cr2, "NBYTES"); + state->u.f0.fld.cr2.reload = cm_object_get_child_by_name(state->u.f0.reg.cr2, "RELOAD"); + state->u.f0.fld.cr2.autoend = cm_object_get_child_by_name(state->u.f0.reg.cr2, "AUTOEND"); + state->u.f0.fld.cr2.pecbyte = cm_object_get_child_by_name(state->u.f0.reg.cr2, "PECBYTE"); + + // OAR1 bitfields. + state->u.f0.fld.oar1.oa1_0 = cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1_0"); + state->u.f0.fld.oar1.oa1_1 = cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1_1"); + state->u.f0.fld.oar1.oa1_8 = cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1_8"); + state->u.f0.fld.oar1.oa1mode = cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1MODE"); + state->u.f0.fld.oar1.oa1en = cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1EN"); + + // OAR2 bitfields. + state->u.f0.fld.oar2.oa2 = cm_object_get_child_by_name(state->u.f0.reg.oar2, "OA2"); + state->u.f0.fld.oar2.oa2msk = cm_object_get_child_by_name(state->u.f0.reg.oar2, "OA2MSK"); + state->u.f0.fld.oar2.oa2en = cm_object_get_child_by_name(state->u.f0.reg.oar2, "OA2EN"); + + // TIMINGR bitfields. + state->u.f0.fld.timingr.scll = cm_object_get_child_by_name(state->u.f0.reg.timingr, "SCLL"); + state->u.f0.fld.timingr.sclh = cm_object_get_child_by_name(state->u.f0.reg.timingr, "SCLH"); + state->u.f0.fld.timingr.sdadel = cm_object_get_child_by_name(state->u.f0.reg.timingr, "SDADEL"); + state->u.f0.fld.timingr.scldel = cm_object_get_child_by_name(state->u.f0.reg.timingr, "SCLDEL"); + state->u.f0.fld.timingr.presc = cm_object_get_child_by_name(state->u.f0.reg.timingr, "PRESC"); + + // TIMEOUTR bitfields. + state->u.f0.fld.timeoutr.timeouta = cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIMEOUTA"); + state->u.f0.fld.timeoutr.tidle = cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIDLE"); + state->u.f0.fld.timeoutr.timouten = cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIMOUTEN"); + state->u.f0.fld.timeoutr.timeoutb = cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIMEOUTB"); + state->u.f0.fld.timeoutr.texten = cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TEXTEN"); + + // ISR bitfields. + state->u.f0.fld.isr.txe = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXE"); + state->u.f0.fld.isr.txis = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXIS"); + state->u.f0.fld.isr.rxne = cm_object_get_child_by_name(state->u.f0.reg.isr, "RXNE"); + state->u.f0.fld.isr.addr = cm_object_get_child_by_name(state->u.f0.reg.isr, "ADDR"); + state->u.f0.fld.isr.nackf = cm_object_get_child_by_name(state->u.f0.reg.isr, "NACKF"); + state->u.f0.fld.isr.stopf = cm_object_get_child_by_name(state->u.f0.reg.isr, "STOPF"); + state->u.f0.fld.isr.tc = cm_object_get_child_by_name(state->u.f0.reg.isr, "TC"); + state->u.f0.fld.isr.tcr = cm_object_get_child_by_name(state->u.f0.reg.isr, "TCR"); + state->u.f0.fld.isr.berr = cm_object_get_child_by_name(state->u.f0.reg.isr, "BERR"); + state->u.f0.fld.isr.arlo = cm_object_get_child_by_name(state->u.f0.reg.isr, "ARLO"); + state->u.f0.fld.isr.ovr = cm_object_get_child_by_name(state->u.f0.reg.isr, "OVR"); + state->u.f0.fld.isr.pecerr = cm_object_get_child_by_name(state->u.f0.reg.isr, "PECERR"); + state->u.f0.fld.isr.timeout = cm_object_get_child_by_name(state->u.f0.reg.isr, "TIMEOUT"); + state->u.f0.fld.isr.alert = cm_object_get_child_by_name(state->u.f0.reg.isr, "ALERT"); + state->u.f0.fld.isr.busy = cm_object_get_child_by_name(state->u.f0.reg.isr, "BUSY"); + state->u.f0.fld.isr.dir = cm_object_get_child_by_name(state->u.f0.reg.isr, "DIR"); + state->u.f0.fld.isr.addcode = cm_object_get_child_by_name(state->u.f0.reg.isr, "ADDCODE"); + + // ICR bitfields. + state->u.f0.fld.icr.addrcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "ADDRCF"); + state->u.f0.fld.icr.nackcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "NACKCF"); + state->u.f0.fld.icr.stopcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "STOPCF"); + state->u.f0.fld.icr.berrcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "BERRCF"); + state->u.f0.fld.icr.arlocf = cm_object_get_child_by_name(state->u.f0.reg.icr, "ARLOCF"); + state->u.f0.fld.icr.ovrcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "OVRCF"); + state->u.f0.fld.icr.peccf = cm_object_get_child_by_name(state->u.f0.reg.icr, "PECCF"); + state->u.f0.fld.icr.timoutcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "TIMOUTCF"); + state->u.f0.fld.icr.alertcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "ALERTCF"); + + // PECR bitfields. + state->u.f0.fld.pecr.pec = cm_object_get_child_by_name(state->u.f0.reg.pecr, "PEC"); + + // RXDR bitfields. + state->u.f0.fld.rxdr.rxdata = cm_object_get_child_by_name(state->u.f0.reg.rxdr, "RXDATA"); + + // TXDR bitfields. + state->u.f0.fld.txdr.txdata = cm_object_get_child_by_name(state->u.f0.reg.txdr, "TXDATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2c_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2c_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2c_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2c_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2c_is_enabled(Object *obj) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2c_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2CState *state = STM32_I2C_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_I2C_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2c_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2C)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2CState *state = STM32_I2C_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2C"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_i2c_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_i2c_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_i2c_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_i2c_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_i2c_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2C%dEN", + 1 + state->port_index - STM32_PORT_I2C1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2c_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2C); +} + +static void stm32_i2c_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2c_reset_callback; + dc->realize = stm32_i2c_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2c_is_enabled; +} + +static const TypeInfo stm32_i2c_type_info = { + .name = TYPE_STM32_I2C, + .parent = TYPE_STM32_I2C_PARENT, + .instance_init = stm32_i2c_instance_init_callback, + .instance_size = sizeof(STM32I2CState), + .class_init = stm32_i2c_class_init_callback, + .class_size = sizeof(STM32I2CClass) }; + +static void stm32_i2c_register_types(void) +{ + type_register_static(&stm32_i2c_type_info); +} + +type_init(stm32_i2c_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/i2c1.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/i2c1.h new file mode 100644 index 0000000000..ef46fca0ef --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/i2c1.h @@ -0,0 +1,246 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2C_H_ +#define STM32_I2C_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2C DEVICE_PATH_STM32 "I2C" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_I2C1, + STM32_PORT_I2C2, + STM32_PORT_I2C_UNDEFINED = 0xFF, +} stm32_i2c_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2C TYPE_STM32_PREFIX "i2c" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2C_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2CParentClass; +typedef PeripheralState STM32I2CParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2CClass, (obj), TYPE_STM32_I2C) +#define STM32_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2CClass, (klass), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentClass parent_class; + // public: + + // None, so far. +} STM32I2CClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2C_STATE(obj) \ + OBJECT_CHECK(STM32I2CState, (obj), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_i2c_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 I2C (Inter-integrated circuit) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *oar1; // 0x8 (Own address register 1) + Object *oar2; // 0xC (Own address register 2) + Object *timingr; // 0x10 (Timing register) + Object *timeoutr; // 0x14 (Status register 1) + Object *isr; // 0x18 (Interrupt and Status register) + Object *icr; // 0x1C (Interrupt clear register) + Object *pecr; // 0x20 (PEC register) + Object *rxdr; // 0x24 (Receive data register) + Object *txdr; // 0x28 (Transmit data register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *pe; // [0:0] Peripheral enable + Object *txie; // [1:1] TX Interrupt enable + Object *rxie; // [2:2] RX Interrupt enable + Object *addrie; // [3:3] Address match interrupt enable (slave only) + Object *nackie; // [4:4] Not acknowledge received interrupt enable + Object *stopie; // [5:5] STOP detection Interrupt enable + Object *tcie; // [6:6] Transfer Complete interrupt enable + Object *errie; // [7:7] Error interrupts enable + Object *dnf; // [8:11] Digital noise filter + Object *anfoff; // [12:12] Analog noise filter OFF + Object *swrst; // [13:13] Software reset + Object *txdmaen; // [14:14] DMA transmission requests enable + Object *rxdmaen; // [15:15] DMA reception requests enable + Object *sbc; // [16:16] Slave byte control + Object *nostretch; // [17:17] Clock stretching disable + Object *wupen; // [18:18] Wakeup from STOP enable + Object *gcen; // [19:19] General call enable + Object *smbhen; // [20:20] SMBus Host address enable + Object *smbden; // [21:21] SMBus Device Default address enable + Object *alerten; // [22:22] SMBUS alert enable + Object *pecen; // [23:23] PEC enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *sadd0; // [0:0] Slave address bit 0 (master mode) + Object *sadd1; // [1:7] Slave address bit 7:1 (master mode) + Object *sadd8; // [8:9] Slave address bit 9:8 (master mode) + Object *rd_wrn; // [10:10] Transfer direction (master mode) + Object *add10; // [11:11] 10-bit addressing mode (master mode) + Object *head10r; // [12:12] 10-bit address header only read direction (master receiver mode) + Object *start; // [13:13] Start generation + Object *stop; // [14:14] Stop generation (master mode) + Object *nack; // [15:15] NACK generation (slave mode) + Object *nbytes; // [16:23] Number of bytes + Object *reload; // [24:24] NBYTES reload mode + Object *autoend; // [25:25] Automatic end mode (master mode) + Object *pecbyte; // [26:26] Packet error checking byte + } cr2; + + // OAR1 (Own address register 1) bitfields. + struct { + Object *oa1_0; // [0:0] Interface address + Object *oa1_1; // [1:7] Interface address + Object *oa1_8; // [8:9] Interface address + Object *oa1mode; // [10:10] Own Address 1 10-bit mode + Object *oa1en; // [15:15] Own Address 1 enable + } oar1; + + // OAR2 (Own address register 2) bitfields. + struct { + Object *oa2; // [1:7] Interface address + Object *oa2msk; // [8:10] Own Address 2 masks + Object *oa2en; // [15:15] Own Address 2 enable + } oar2; + + // TIMINGR (Timing register) bitfields. + struct { + Object *scll; // [0:7] SCL low period (master mode) + Object *sclh; // [8:15] SCL high period (master mode) + Object *sdadel; // [16:19] Data hold time + Object *scldel; // [20:23] Data setup time + Object *presc; // [28:31] Timing prescaler + } timingr; + + // TIMEOUTR (Status register 1) bitfields. + struct { + Object *timeouta; // [0:11] Bus timeout A + Object *tidle; // [12:12] Idle clock timeout detection + Object *timouten; // [15:15] Clock timeout enable + Object *timeoutb; // [16:27] Bus timeout B + Object *texten; // [31:31] Extended clock timeout enable + } timeoutr; + + // ISR (Interrupt and Status register) bitfields. + struct { + Object *txe; // [0:0] Transmit data register empty (transmitters) + Object *txis; // [1:1] Transmit interrupt status (transmitters) + Object *rxne; // [2:2] Receive data register not empty (receivers) + Object *addr; // [3:3] Address matched (slave mode) + Object *nackf; // [4:4] Not acknowledge received flag + Object *stopf; // [5:5] Stop detection flag + Object *tc; // [6:6] Transfer Complete (master mode) + Object *tcr; // [7:7] Transfer Complete Reload + Object *berr; // [8:8] Bus error + Object *arlo; // [9:9] Arbitration lost + Object *ovr; // [10:10] Overrun/Underrun (slave mode) + Object *pecerr; // [11:11] PEC Error in reception + Object *timeout; // [12:12] Timeout or t_low detection flag + Object *alert; // [13:13] SMBus alert + Object *busy; // [15:15] Bus busy + Object *dir; // [16:16] Transfer direction (Slave mode) + Object *addcode; // [17:23] Address match code (Slave mode) + } isr; + + // ICR (Interrupt clear register) bitfields. + struct { + Object *addrcf; // [3:3] Address Matched flag clear + Object *nackcf; // [4:4] Not Acknowledge flag clear + Object *stopcf; // [5:5] Stop detection flag clear + Object *berrcf; // [8:8] Bus error flag clear + Object *arlocf; // [9:9] Arbitration lost flag clear + Object *ovrcf; // [10:10] Overrun/Underrun flag clear + Object *peccf; // [11:11] PEC Error flag clear + Object *timoutcf; // [12:12] Timeout detection flag clear + Object *alertcf; // [13:13] Alert flag clear + } icr; + + // PECR (PEC register) bitfields. + struct { + Object *pec; // [0:7] Packet error checking register + } pecr; + + // RXDR (Receive data register) bitfields. + struct { + Object *rxdata; // [0:7] 8-bit receive data + } rxdr; + + // TXDR (Transmit data register) bitfields. + struct { + Object *txdata; // [0:7] 8-bit transmit data + } txdr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2CState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2C_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/iwdg.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/iwdg.c new file mode 100644 index 0000000000..c07f6ca2a3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/iwdg.c @@ -0,0 +1,256 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_iwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.kr = cm_object_get_child_by_name(obj, "KR"); + state->u.f0.reg.pr = cm_object_get_child_by_name(obj, "PR"); + state->u.f0.reg.rlr = cm_object_get_child_by_name(obj, "RLR"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.winr = cm_object_get_child_by_name(obj, "WINR"); + + + // KR bitfields. + state->u.f0.fld.kr.key = cm_object_get_child_by_name(state->u.f0.reg.kr, "KEY"); + + // PR bitfields. + state->u.f0.fld.pr.pr = cm_object_get_child_by_name(state->u.f0.reg.pr, "PR"); + + // RLR bitfields. + state->u.f0.fld.rlr.rl = cm_object_get_child_by_name(state->u.f0.reg.rlr, "RL"); + + // SR bitfields. + state->u.f0.fld.sr.pvu = cm_object_get_child_by_name(state->u.f0.reg.sr, "PVU"); + state->u.f0.fld.sr.rvu = cm_object_get_child_by_name(state->u.f0.reg.sr, "RVU"); + state->u.f0.fld.sr.wvu = cm_object_get_child_by_name(state->u.f0.reg.sr, "WVU"); + + // WINR bitfields. + state->u.f0.fld.winr.win = cm_object_get_child_by_name(state->u.f0.reg.winr, "WIN"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_iwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_iwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_iwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_iwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_iwdg_is_enabled(Object *obj) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_iwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_iwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_IWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32IWDGState *state = STM32_IWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "IWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_iwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_iwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_iwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_iwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_iwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/IWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_iwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_IWDG); +} + +static void stm32_iwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_iwdg_reset_callback; + dc->realize = stm32_iwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_iwdg_is_enabled; +} + +static const TypeInfo stm32_iwdg_type_info = { + .name = TYPE_STM32_IWDG, + .parent = TYPE_STM32_IWDG_PARENT, + .instance_init = stm32_iwdg_instance_init_callback, + .instance_size = sizeof(STM32IWDGState), + .class_init = stm32_iwdg_class_init_callback, + .class_size = sizeof(STM32IWDGClass) }; + +static void stm32_iwdg_register_types(void) +{ + type_register_static(&stm32_iwdg_type_info); +} + +type_init(stm32_iwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/iwdg.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/iwdg.h new file mode 100644 index 0000000000..5e6107e981 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/iwdg.h @@ -0,0 +1,131 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_IWDG_H_ +#define STM32_IWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_IWDG DEVICE_PATH_STM32 "IWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_IWDG TYPE_STM32_PREFIX "iwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_IWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32IWDGParentClass; +typedef PeripheralState STM32IWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_IWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32IWDGClass, (obj), TYPE_STM32_IWDG) +#define STM32_IWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32IWDGClass, (klass), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentClass parent_class; + // public: + + // None, so far. +} STM32IWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_IWDG_STATE(obj) \ + OBJECT_CHECK(STM32IWDGState, (obj), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 IWDG (Independent watchdog) registers. + struct { + Object *kr; // 0x0 (Key register) + Object *pr; // 0x4 (Prescaler register) + Object *rlr; // 0x8 (Reload register) + Object *sr; // 0xC (Status register) + Object *winr; // 0x10 (Window register) + } reg; + + struct { + + // KR (Key register) bitfields. + struct { + Object *key; // [0:15] Key value + } kr; + + // PR (Prescaler register) bitfields. + struct { + Object *pr; // [0:2] Prescaler divider + } pr; + + // RLR (Reload register) bitfields. + struct { + Object *rl; // [0:11] Watchdog counter reload value + } rlr; + + // SR (Status register) bitfields. + struct { + Object *pvu; // [0:0] Watchdog prescaler value update + Object *rvu; // [1:1] Watchdog counter reload value update + Object *wvu; // [2:2] Watchdog counter window value update + } sr; + + // WINR (Window register) bitfields. + struct { + Object *win; // [0:11] Watchdog counter window value + } winr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32IWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_IWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/pwr.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/pwr.c new file mode 100644 index 0000000000..fdfc43b543 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/pwr.c @@ -0,0 +1,259 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_pwr_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CR bitfields. + state->u.f0.fld.cr.lpds = cm_object_get_child_by_name(state->u.f0.reg.cr, "LPDS"); + state->u.f0.fld.cr.pdds = cm_object_get_child_by_name(state->u.f0.reg.cr, "PDDS"); + state->u.f0.fld.cr.cwuf = cm_object_get_child_by_name(state->u.f0.reg.cr, "CWUF"); + state->u.f0.fld.cr.csbf = cm_object_get_child_by_name(state->u.f0.reg.cr, "CSBF"); + state->u.f0.fld.cr.pvde = cm_object_get_child_by_name(state->u.f0.reg.cr, "PVDE"); + state->u.f0.fld.cr.pls = cm_object_get_child_by_name(state->u.f0.reg.cr, "PLS"); + state->u.f0.fld.cr.dbp = cm_object_get_child_by_name(state->u.f0.reg.cr, "DBP"); + + // CSR bitfields. + state->u.f0.fld.csr.wuf = cm_object_get_child_by_name(state->u.f0.reg.csr, "WUF"); + state->u.f0.fld.csr.sbf = cm_object_get_child_by_name(state->u.f0.reg.csr, "SBF"); + state->u.f0.fld.csr.pvdo = cm_object_get_child_by_name(state->u.f0.reg.csr, "PVDO"); + state->u.f0.fld.csr.vrefintrdy = cm_object_get_child_by_name(state->u.f0.reg.csr, "VREFINTRDY"); + state->u.f0.fld.csr.ewup1 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP1"); + state->u.f0.fld.csr.ewup2 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP2"); + state->u.f0.fld.csr.ewup3 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP3"); + state->u.f0.fld.csr.ewup4 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP4"); + state->u.f0.fld.csr.ewup5 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP5"); + state->u.f0.fld.csr.ewup6 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP6"); + state->u.f0.fld.csr.ewup7 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP7"); + state->u.f0.fld.csr.ewup8 = cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP8"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_pwr_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_pwr_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_pwr_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_pwr_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_pwr_is_enabled(Object *obj) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_pwr_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32PWRState *state = STM32_PWR_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_pwr_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_PWR)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32PWRState *state = STM32_PWR_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "PWR"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_pwr_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_pwr_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_pwr_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_pwr_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_pwr_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/PWREN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_pwr_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_PWR); +} + +static void stm32_pwr_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_pwr_reset_callback; + dc->realize = stm32_pwr_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_pwr_is_enabled; +} + +static const TypeInfo stm32_pwr_type_info = { + .name = TYPE_STM32_PWR, + .parent = TYPE_STM32_PWR_PARENT, + .instance_init = stm32_pwr_instance_init_callback, + .instance_size = sizeof(STM32PWRState), + .class_init = stm32_pwr_class_init_callback, + .class_size = sizeof(STM32PWRClass) }; + +static void stm32_pwr_register_types(void) +{ + type_register_static(&stm32_pwr_type_info); +} + +type_init(stm32_pwr_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/pwr.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/pwr.h new file mode 100644 index 0000000000..654aad52a6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/pwr.h @@ -0,0 +1,128 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_PWR_H_ +#define STM32_PWR_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_PWR DEVICE_PATH_STM32 "PWR" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_PWR TYPE_STM32_PREFIX "pwr" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_PWR_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32PWRParentClass; +typedef PeripheralState STM32PWRParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_PWR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32PWRClass, (obj), TYPE_STM32_PWR) +#define STM32_PWR_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32PWRClass, (klass), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentClass parent_class; + // public: + + // None, so far. +} STM32PWRClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_PWR_STATE(obj) \ + OBJECT_CHECK(STM32PWRState, (obj), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 PWR (Power control) registers. + struct { + Object *cr; // 0x0 (Power control register) + Object *csr; // 0x4 (Power control/status register) + } reg; + + struct { + + // CR (Power control register) bitfields. + struct { + Object *lpds; // [0:0] Low-power deep sleep + Object *pdds; // [1:1] Power down deepsleep + Object *cwuf; // [2:2] Clear wakeup flag + Object *csbf; // [3:3] Clear standby flag + Object *pvde; // [4:4] Power voltage detector enable + Object *pls; // [5:7] PVD level selection + Object *dbp; // [8:8] Disable backup domain write protection + } cr; + + // CSR (Power control/status register) bitfields. + struct { + Object *wuf; // [0:0] Wakeup flag + Object *sbf; // [1:1] Standby flag + Object *pvdo; // [2:2] PVD output + Object *vrefintrdy; // [3:3] VREFINT reference voltage ready + Object *ewup1; // [8:8] Enable WKUP pin 1 + Object *ewup2; // [9:9] Enable WKUP pin 2 + Object *ewup3; // [10:10] Enable WKUP pin 3 + Object *ewup4; // [11:11] Enable WKUP pin 4 + Object *ewup5; // [12:12] Enable WKUP pin 5 + Object *ewup6; // [13:13] Enable WKUP pin 6 + Object *ewup7; // [14:14] Enable WKUP pin 7 + Object *ewup8; // [15:15] Enable WKUP pin 8 + } csr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32PWRState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_PWR_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/rcc.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/rcc.c new file mode 100644 index 0000000000..cc597826dc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/rcc.c @@ -0,0 +1,425 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_rcc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f0.reg.cir = cm_object_get_child_by_name(obj, "CIR"); + state->u.f0.reg.apb2rstr = cm_object_get_child_by_name(obj, "APB2RSTR"); + state->u.f0.reg.apb1rstr = cm_object_get_child_by_name(obj, "APB1RSTR"); + state->u.f0.reg.ahbenr = cm_object_get_child_by_name(obj, "AHBENR"); + state->u.f0.reg.apb2enr = cm_object_get_child_by_name(obj, "APB2ENR"); + state->u.f0.reg.apb1enr = cm_object_get_child_by_name(obj, "APB1ENR"); + state->u.f0.reg.bdcr = cm_object_get_child_by_name(obj, "BDCR"); + state->u.f0.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f0.reg.ahbrstr = cm_object_get_child_by_name(obj, "AHBRSTR"); + state->u.f0.reg.cfgr2 = cm_object_get_child_by_name(obj, "CFGR2"); + state->u.f0.reg.cfgr3 = cm_object_get_child_by_name(obj, "CFGR3"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + + + // CR bitfields. + state->u.f0.fld.cr.hsion = cm_object_get_child_by_name(state->u.f0.reg.cr, "HSION"); + state->u.f0.fld.cr.hsirdy = cm_object_get_child_by_name(state->u.f0.reg.cr, "HSIRDY"); + state->u.f0.fld.cr.hsitrim = cm_object_get_child_by_name(state->u.f0.reg.cr, "HSITRIM"); + state->u.f0.fld.cr.hsical = cm_object_get_child_by_name(state->u.f0.reg.cr, "HSICAL"); + state->u.f0.fld.cr.hseon = cm_object_get_child_by_name(state->u.f0.reg.cr, "HSEON"); + state->u.f0.fld.cr.hserdy = cm_object_get_child_by_name(state->u.f0.reg.cr, "HSERDY"); + state->u.f0.fld.cr.hsebyp = cm_object_get_child_by_name(state->u.f0.reg.cr, "HSEBYP"); + state->u.f0.fld.cr.csson = cm_object_get_child_by_name(state->u.f0.reg.cr, "CSSON"); + state->u.f0.fld.cr.pllon = cm_object_get_child_by_name(state->u.f0.reg.cr, "PLLON"); + state->u.f0.fld.cr.pllrdy = cm_object_get_child_by_name(state->u.f0.reg.cr, "PLLRDY"); + + // CFGR bitfields. + state->u.f0.fld.cfgr.sw = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SW"); + state->u.f0.fld.cfgr.sws = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SWS"); + state->u.f0.fld.cfgr.hpre = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "HPRE"); + state->u.f0.fld.cfgr.ppre = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PPRE"); + state->u.f0.fld.cfgr.adcpre = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "ADCPRE"); + state->u.f0.fld.cfgr.pllsrc = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLSRC"); + state->u.f0.fld.cfgr.pllxtpre = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLXTPRE"); + state->u.f0.fld.cfgr.pllmul = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLMUL"); + state->u.f0.fld.cfgr.mco = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "MCO"); + state->u.f0.fld.cfgr.mcopre = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "MCOPRE"); + state->u.f0.fld.cfgr.pllnodiv = cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLNODIV"); + + // CIR bitfields. + state->u.f0.fld.cir.lsirdyf = cm_object_get_child_by_name(state->u.f0.reg.cir, "LSIRDYF"); + state->u.f0.fld.cir.lserdyf = cm_object_get_child_by_name(state->u.f0.reg.cir, "LSERDYF"); + state->u.f0.fld.cir.hsirdyf = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSIRDYF"); + state->u.f0.fld.cir.hserdyf = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSERDYF"); + state->u.f0.fld.cir.pllrdyf = cm_object_get_child_by_name(state->u.f0.reg.cir, "PLLRDYF"); + state->u.f0.fld.cir.hsi14rdyf = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI14RDYF"); + state->u.f0.fld.cir.hsi48rdyf = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI48RDYF"); + state->u.f0.fld.cir.cssf = cm_object_get_child_by_name(state->u.f0.reg.cir, "CSSF"); + state->u.f0.fld.cir.lsirdyie = cm_object_get_child_by_name(state->u.f0.reg.cir, "LSIRDYIE"); + state->u.f0.fld.cir.lserdyie = cm_object_get_child_by_name(state->u.f0.reg.cir, "LSERDYIE"); + state->u.f0.fld.cir.hsirdyie = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSIRDYIE"); + state->u.f0.fld.cir.hserdyie = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSERDYIE"); + state->u.f0.fld.cir.pllrdyie = cm_object_get_child_by_name(state->u.f0.reg.cir, "PLLRDYIE"); + state->u.f0.fld.cir.hsi14rdye = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI14RDYE"); + state->u.f0.fld.cir.hsi48rdyie = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI48RDYIE"); + state->u.f0.fld.cir.lsirdyc = cm_object_get_child_by_name(state->u.f0.reg.cir, "LSIRDYC"); + state->u.f0.fld.cir.lserdyc = cm_object_get_child_by_name(state->u.f0.reg.cir, "LSERDYC"); + state->u.f0.fld.cir.hsirdyc = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSIRDYC"); + state->u.f0.fld.cir.hserdyc = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSERDYC"); + state->u.f0.fld.cir.pllrdyc = cm_object_get_child_by_name(state->u.f0.reg.cir, "PLLRDYC"); + state->u.f0.fld.cir.hsi14rdyc = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI14RDYC"); + state->u.f0.fld.cir.hsi48rdyc = cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI48RDYC"); + state->u.f0.fld.cir.cssc = cm_object_get_child_by_name(state->u.f0.reg.cir, "CSSC"); + + // APB2RSTR bitfields. + state->u.f0.fld.apb2rstr.syscfgrst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "SYSCFGRST"); + state->u.f0.fld.apb2rstr.adcrst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "ADCRST"); + state->u.f0.fld.apb2rstr.tim1rst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM1RST"); + state->u.f0.fld.apb2rstr.spi1rst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "SPI1RST"); + state->u.f0.fld.apb2rstr.usart1rst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "USART1RST"); + state->u.f0.fld.apb2rstr.tim15rst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM15RST"); + state->u.f0.fld.apb2rstr.tim16rst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM16RST"); + state->u.f0.fld.apb2rstr.tim17rst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM17RST"); + state->u.f0.fld.apb2rstr.dbgmcurst = cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "DBGMCURST"); + + // APB1RSTR bitfields. + state->u.f0.fld.apb1rstr.tim2rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM2RST"); + state->u.f0.fld.apb1rstr.tim3rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM3RST"); + state->u.f0.fld.apb1rstr.tim6rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM6RST"); + state->u.f0.fld.apb1rstr.tim7rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM7RST"); + state->u.f0.fld.apb1rstr.tim14rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM14RST"); + state->u.f0.fld.apb1rstr.wwdgrst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "WWDGRST"); + state->u.f0.fld.apb1rstr.spi2rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "SPI2RST"); + state->u.f0.fld.apb1rstr.usart2rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USART2RST"); + state->u.f0.fld.apb1rstr.usart3rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USART3RST"); + state->u.f0.fld.apb1rstr.usart4rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USART4RST"); + state->u.f0.fld.apb1rstr.usart5rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USART5RST"); + state->u.f0.fld.apb1rstr.i2c1rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "I2C1RST"); + state->u.f0.fld.apb1rstr.i2c2rst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "I2C2RST"); + state->u.f0.fld.apb1rstr.usbrst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USBRST"); + state->u.f0.fld.apb1rstr.canrst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "CANRST"); + state->u.f0.fld.apb1rstr.crsrst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "CRSRST"); + state->u.f0.fld.apb1rstr.pwrrst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "PWRRST"); + state->u.f0.fld.apb1rstr.dacrst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "DACRST"); + state->u.f0.fld.apb1rstr.cecrst = cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "CECRST"); + + // AHBENR bitfields. + state->u.f0.fld.ahbenr.dma1en = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "DMA1EN"); + state->u.f0.fld.ahbenr.dma2en = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "DMA2EN"); + state->u.f0.fld.ahbenr.sramen = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "SRAMEN"); + state->u.f0.fld.ahbenr.flitfen = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "FLITFEN"); + state->u.f0.fld.ahbenr.crcen = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "CRCEN"); + state->u.f0.fld.ahbenr.iopaen = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPAEN"); + state->u.f0.fld.ahbenr.iopben = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPBEN"); + state->u.f0.fld.ahbenr.iopcen = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPCEN"); + state->u.f0.fld.ahbenr.iopden = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPDEN"); + state->u.f0.fld.ahbenr.iopfen = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPFEN"); + state->u.f0.fld.ahbenr.tscen = cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "TSCEN"); + + // APB2ENR bitfields. + state->u.f0.fld.apb2enr.syscfgen = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "SYSCFGEN"); + state->u.f0.fld.apb2enr.adcen = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "ADCEN"); + state->u.f0.fld.apb2enr.tim1en = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM1EN"); + state->u.f0.fld.apb2enr.spi1en = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "SPI1EN"); + state->u.f0.fld.apb2enr.usart1en = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "USART1EN"); + state->u.f0.fld.apb2enr.tim15en = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM15EN"); + state->u.f0.fld.apb2enr.tim16en = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM16EN"); + state->u.f0.fld.apb2enr.tim17en = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM17EN"); + state->u.f0.fld.apb2enr.dbgmcuen = cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "DBGMCUEN"); + + // APB1ENR bitfields. + state->u.f0.fld.apb1enr.tim2en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM2EN"); + state->u.f0.fld.apb1enr.tim3en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM3EN"); + state->u.f0.fld.apb1enr.tim6en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM6EN"); + state->u.f0.fld.apb1enr.tim7en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM7EN"); + state->u.f0.fld.apb1enr.tim14en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM14EN"); + state->u.f0.fld.apb1enr.wwdgen = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "WWDGEN"); + state->u.f0.fld.apb1enr.spi2en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "SPI2EN"); + state->u.f0.fld.apb1enr.usart2en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USART2EN"); + state->u.f0.fld.apb1enr.usart3en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USART3EN"); + state->u.f0.fld.apb1enr.usart4en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USART4EN"); + state->u.f0.fld.apb1enr.usart5en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USART5EN"); + state->u.f0.fld.apb1enr.i2c1en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "I2C1EN"); + state->u.f0.fld.apb1enr.i2c2en = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "I2C2EN"); + state->u.f0.fld.apb1enr.usbrst = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USBRST"); + state->u.f0.fld.apb1enr.canen = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "CANEN"); + state->u.f0.fld.apb1enr.crsen = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "CRSEN"); + state->u.f0.fld.apb1enr.pwren = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "PWREN"); + state->u.f0.fld.apb1enr.dacen = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "DACEN"); + state->u.f0.fld.apb1enr.cecen = cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "CECEN"); + + // BDCR bitfields. + state->u.f0.fld.bdcr.lseon = cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSEON"); + state->u.f0.fld.bdcr.lserdy = cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSERDY"); + state->u.f0.fld.bdcr.lsebyp = cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSEBYP"); + state->u.f0.fld.bdcr.lsedrv = cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSEDRV"); + state->u.f0.fld.bdcr.rtcsel = cm_object_get_child_by_name(state->u.f0.reg.bdcr, "RTCSEL"); + state->u.f0.fld.bdcr.rtcen = cm_object_get_child_by_name(state->u.f0.reg.bdcr, "RTCEN"); + state->u.f0.fld.bdcr.bdrst = cm_object_get_child_by_name(state->u.f0.reg.bdcr, "BDRST"); + + // CSR bitfields. + state->u.f0.fld.csr.lsion = cm_object_get_child_by_name(state->u.f0.reg.csr, "LSION"); + state->u.f0.fld.csr.lsirdy = cm_object_get_child_by_name(state->u.f0.reg.csr, "LSIRDY"); + state->u.f0.fld.csr.rmvf = cm_object_get_child_by_name(state->u.f0.reg.csr, "RMVF"); + state->u.f0.fld.csr.oblrstf = cm_object_get_child_by_name(state->u.f0.reg.csr, "OBLRSTF"); + state->u.f0.fld.csr.pinrstf = cm_object_get_child_by_name(state->u.f0.reg.csr, "PINRSTF"); + state->u.f0.fld.csr.porrstf = cm_object_get_child_by_name(state->u.f0.reg.csr, "PORRSTF"); + state->u.f0.fld.csr.sftrstf = cm_object_get_child_by_name(state->u.f0.reg.csr, "SFTRSTF"); + state->u.f0.fld.csr.iwdgrstf = cm_object_get_child_by_name(state->u.f0.reg.csr, "IWDGRSTF"); + state->u.f0.fld.csr.wwdgrstf = cm_object_get_child_by_name(state->u.f0.reg.csr, "WWDGRSTF"); + state->u.f0.fld.csr.lpwrrstf = cm_object_get_child_by_name(state->u.f0.reg.csr, "LPWRRSTF"); + + // AHBRSTR bitfields. + state->u.f0.fld.ahbrstr.ioparst = cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPARST"); + state->u.f0.fld.ahbrstr.iopbrst = cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPBRST"); + state->u.f0.fld.ahbrstr.iopcrst = cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPCRST"); + state->u.f0.fld.ahbrstr.iopdrst = cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPDRST"); + state->u.f0.fld.ahbrstr.iopfrst = cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPFRST"); + state->u.f0.fld.ahbrstr.tscrst = cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "TSCRST"); + + // CFGR2 bitfields. + state->u.f0.fld.cfgr2.prediv = cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "PREDIV"); + + // CFGR3 bitfields. + state->u.f0.fld.cfgr3.usart1sw = cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "USART1SW"); + state->u.f0.fld.cfgr3.i2c1sw = cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "I2C1SW"); + state->u.f0.fld.cfgr3.cecsw = cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "CECSW"); + state->u.f0.fld.cfgr3.usbsw = cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "USBSW"); + state->u.f0.fld.cfgr3.adcsw = cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "ADCSW"); + state->u.f0.fld.cfgr3.usart2sw = cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "USART2SW"); + + // CR2 bitfields. + state->u.f0.fld.cr2.hsi14on = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14ON"); + state->u.f0.fld.cr2.hsi14rdy = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14RDY"); + state->u.f0.fld.cr2.hsi14dis = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14DIS"); + state->u.f0.fld.cr2.hsi14trim = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14TRIM"); + state->u.f0.fld.cr2.hsi14cal = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14CAL"); + state->u.f0.fld.cr2.hsi48on = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI48ON"); + state->u.f0.fld.cr2.hsi48rdy = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI48RDY"); + state->u.f0.fld.cr2.hsi48cal = cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI48CAL"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rcc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rcc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rcc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rcc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rcc_is_enabled(Object *obj) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rcc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RCCState *state = STM32_RCC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rcc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RCC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RCCState *state = STM32_RCC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RCC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_rcc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rcc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_rcc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rcc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_rcc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RCCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rcc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RCC); +} + +static void stm32_rcc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rcc_reset_callback; + dc->realize = stm32_rcc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rcc_is_enabled; +} + +static const TypeInfo stm32_rcc_type_info = { + .name = TYPE_STM32_RCC, + .parent = TYPE_STM32_RCC_PARENT, + .instance_init = stm32_rcc_instance_init_callback, + .instance_size = sizeof(STM32RCCState), + .class_init = stm32_rcc_class_init_callback, + .class_size = sizeof(STM32RCCClass) }; + +static void stm32_rcc_register_types(void) +{ + type_register_static(&stm32_rcc_type_info); +} + +type_init(stm32_rcc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/rcc.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/rcc.h new file mode 100644 index 0000000000..cad46983d7 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/rcc.h @@ -0,0 +1,318 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RCC_H_ +#define STM32_RCC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RCC DEVICE_PATH_STM32 "RCC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RCC TYPE_STM32_PREFIX "rcc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RCC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RCCParentClass; +typedef PeripheralState STM32RCCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RCCClass, (obj), TYPE_STM32_RCC) +#define STM32_RCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RCCClass, (klass), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentClass parent_class; + // public: + + // None, so far. +} STM32RCCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RCC_STATE(obj) \ + OBJECT_CHECK(STM32RCCState, (obj), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 RCC (Reset and clock control) registers. + struct { + Object *cr; // 0x0 (Clock control register) + Object *cfgr; // 0x4 (Clock configuration register (RCC_CFGR)) + Object *cir; // 0x8 (Clock interrupt register (RCC_CIR)) + Object *apb2rstr; // 0xC (APB2 peripheral reset register (RCC_APB2RSTR)) + Object *apb1rstr; // 0x10 (APB1 peripheral reset register (RCC_APB1RSTR)) + Object *ahbenr; // 0x14 (AHB Peripheral Clock enable register (RCC_AHBENR)) + Object *apb2enr; // 0x18 (APB2 peripheral clock enable register (RCC_APB2ENR)) + Object *apb1enr; // 0x1C (APB1 peripheral clock enable register (RCC_APB1ENR)) + Object *bdcr; // 0x20 (Backup domain control register (RCC_BDCR)) + Object *csr; // 0x24 (Control/status register (RCC_CSR)) + Object *ahbrstr; // 0x28 (AHB peripheral reset register) + Object *cfgr2; // 0x2C (Clock configuration register 2) + Object *cfgr3; // 0x30 (Clock configuration register 3) + Object *cr2; // 0x34 (Clock control register 2) + } reg; + + struct { + + // CR (Clock control register) bitfields. + struct { + Object *hsion; // [0:0] Internal High Speed clock enable + Object *hsirdy; // [1:1] Internal High Speed clock ready flag + Object *hsitrim; // [3:7] Internal High Speed clock trimming + Object *hsical; // [8:15] Internal High Speed clock Calibration + Object *hseon; // [16:16] External High Speed clock enable + Object *hserdy; // [17:17] External High Speed clock ready flag + Object *hsebyp; // [18:18] External High Speed clock Bypass + Object *csson; // [19:19] Clock Security System enable + Object *pllon; // [24:24] PLL enable + Object *pllrdy; // [25:25] PLL clock ready flag + } cr; + + // CFGR (Clock configuration register (RCC_CFGR)) bitfields. + struct { + Object *sw; // [0:1] System clock Switch + Object *sws; // [2:3] System Clock Switch Status + Object *hpre; // [4:7] AHB prescaler + Object *ppre; // [8:10] APB Low speed prescaler (APB1) + Object *adcpre; // [14:14] ADC prescaler + Object *pllsrc; // [15:16] PLL input clock source + Object *pllxtpre; // [17:17] HSE divider for PLL entry + Object *pllmul; // [18:21] PLL Multiplication Factor + Object *mco; // [24:26] Microcontroller clock output + Object *mcopre; // [28:30] Microcontroller Clock Output Prescaler + Object *pllnodiv; // [31:31] PLL clock not divided for MCO + } cfgr; + + // CIR (Clock interrupt register (RCC_CIR)) bitfields. + struct { + Object *lsirdyf; // [0:0] LSI Ready Interrupt flag + Object *lserdyf; // [1:1] LSE Ready Interrupt flag + Object *hsirdyf; // [2:2] HSI Ready Interrupt flag + Object *hserdyf; // [3:3] HSE Ready Interrupt flag + Object *pllrdyf; // [4:4] PLL Ready Interrupt flag + Object *hsi14rdyf; // [5:5] HSI14 ready interrupt flag + Object *hsi48rdyf; // [6:6] HSI48 ready interrupt flag + Object *cssf; // [7:7] Clock Security System Interrupt flag + Object *lsirdyie; // [8:8] LSI Ready Interrupt Enable + Object *lserdyie; // [9:9] LSE Ready Interrupt Enable + Object *hsirdyie; // [10:10] HSI Ready Interrupt Enable + Object *hserdyie; // [11:11] HSE Ready Interrupt Enable + Object *pllrdyie; // [12:12] PLL Ready Interrupt Enable + Object *hsi14rdye; // [13:13] HSI14 ready interrupt enable + Object *hsi48rdyie; // [14:14] HSI48 ready interrupt enable + Object *lsirdyc; // [16:16] LSI Ready Interrupt Clear + Object *lserdyc; // [17:17] LSE Ready Interrupt Clear + Object *hsirdyc; // [18:18] HSI Ready Interrupt Clear + Object *hserdyc; // [19:19] HSE Ready Interrupt Clear + Object *pllrdyc; // [20:20] PLL Ready Interrupt Clear + Object *hsi14rdyc; // [21:21] HSI 14 MHz Ready Interrupt Clear + Object *hsi48rdyc; // [22:22] HSI48 Ready Interrupt Clear + Object *cssc; // [23:23] Clock security system interrupt clear + } cir; + + // APB2RSTR (APB2 peripheral reset register (RCC_APB2RSTR)) bitfields. + struct { + Object *syscfgrst; // [0:0] SYSCFG and COMP reset + Object *adcrst; // [9:9] ADC interface reset + Object *tim1rst; // [11:11] TIM1 timer reset + Object *spi1rst; // [12:12] SPI 1 reset + Object *usart1rst; // [14:14] USART1 reset + Object *tim15rst; // [16:16] TIM15 timer reset + Object *tim16rst; // [17:17] TIM16 timer reset + Object *tim17rst; // [18:18] TIM17 timer reset + Object *dbgmcurst; // [22:22] Debug MCU reset + } apb2rstr; + + // APB1RSTR (APB1 peripheral reset register (RCC_APB1RSTR)) bitfields. + struct { + Object *tim2rst; // [0:0] Timer 2 reset + Object *tim3rst; // [1:1] Timer 3 reset + Object *tim6rst; // [4:4] Timer 6 reset + Object *tim7rst; // [5:5] TIM7 timer reset + Object *tim14rst; // [8:8] Timer 14 reset + Object *wwdgrst; // [11:11] Window watchdog reset + Object *spi2rst; // [14:14] SPI2 reset + Object *usart2rst; // [17:17] USART 2 reset + Object *usart3rst; // [18:18] USART3 reset + Object *usart4rst; // [19:19] USART4 reset + Object *usart5rst; // [20:20] USART5 reset + Object *i2c1rst; // [21:21] I2C1 reset + Object *i2c2rst; // [22:22] I2C2 reset + Object *usbrst; // [23:23] USB interface reset + Object *canrst; // [25:25] CAN interface reset + Object *crsrst; // [27:27] Clock Recovery System interface reset + Object *pwrrst; // [28:28] Power interface reset + Object *dacrst; // [29:29] DAC interface reset + Object *cecrst; // [30:30] HDMI CEC reset + } apb1rstr; + + // AHBENR (AHB Peripheral Clock enable register (RCC_AHBENR)) bitfields. + struct { + Object *dma1en; // [0:0] DMA1 clock enable + Object *dma2en; // [1:1] DMA2 clock enable + Object *sramen; // [2:2] SRAM interface clock enable + Object *flitfen; // [4:4] FLITF clock enable + Object *crcen; // [6:6] CRC clock enable + Object *iopaen; // [17:17] I/O port A clock enable + Object *iopben; // [18:18] I/O port B clock enable + Object *iopcen; // [19:19] I/O port C clock enable + Object *iopden; // [20:20] I/O port D clock enable + Object *iopfen; // [22:22] I/O port F clock enable + Object *tscen; // [24:24] Touch sensing controller clock enable + } ahbenr; + + // APB2ENR (APB2 peripheral clock enable register (RCC_APB2ENR)) bitfields. + struct { + Object *syscfgen; // [0:0] SYSCFG clock enable + Object *adcen; // [9:9] ADC 1 interface clock enable + Object *tim1en; // [11:11] TIM1 Timer clock enable + Object *spi1en; // [12:12] SPI 1 clock enable + Object *usart1en; // [14:14] USART1 clock enable + Object *tim15en; // [16:16] TIM15 timer clock enable + Object *tim16en; // [17:17] TIM16 timer clock enable + Object *tim17en; // [18:18] TIM17 timer clock enable + Object *dbgmcuen; // [22:22] MCU debug module clock enable + } apb2enr; + + // APB1ENR (APB1 peripheral clock enable register (RCC_APB1ENR)) bitfields. + struct { + Object *tim2en; // [0:0] Timer 2 clock enable + Object *tim3en; // [1:1] Timer 3 clock enable + Object *tim6en; // [4:4] Timer 6 clock enable + Object *tim7en; // [5:5] TIM7 timer clock enable + Object *tim14en; // [8:8] Timer 14 clock enable + Object *wwdgen; // [11:11] Window watchdog clock enable + Object *spi2en; // [14:14] SPI 2 clock enable + Object *usart2en; // [17:17] USART 2 clock enable + Object *usart3en; // [18:18] USART3 clock enable + Object *usart4en; // [19:19] USART4 clock enable + Object *usart5en; // [20:20] USART5 clock enable + Object *i2c1en; // [21:21] I2C 1 clock enable + Object *i2c2en; // [22:22] I2C 2 clock enable + Object *usbrst; // [23:23] USB interface clock enable + Object *canen; // [25:25] CAN interface clock enable + Object *crsen; // [27:27] Clock Recovery System interface clock enable + Object *pwren; // [28:28] Power interface clock enable + Object *dacen; // [29:29] DAC interface clock enable + Object *cecen; // [30:30] HDMI CEC interface clock enable + } apb1enr; + + // BDCR (Backup domain control register (RCC_BDCR)) bitfields. + struct { + Object *lseon; // [0:0] External Low Speed oscillator enable + Object *lserdy; // [1:1] External Low Speed oscillator ready + Object *lsebyp; // [2:2] External Low Speed oscillator bypass + Object *lsedrv; // [3:4] LSE oscillator drive capability + Object *rtcsel; // [8:9] RTC clock source selection + Object *rtcen; // [15:15] RTC clock enable + Object *bdrst; // [16:16] Backup domain software reset + } bdcr; + + // CSR (Control/status register (RCC_CSR)) bitfields. + struct { + Object *lsion; // [0:0] Internal low speed oscillator enable + Object *lsirdy; // [1:1] Internal low speed oscillator ready + Object *rmvf; // [24:24] Remove reset flag + Object *oblrstf; // [25:25] Option byte loader reset flag + Object *pinrstf; // [26:26] PIN reset flag + Object *porrstf; // [27:27] POR/PDR reset flag + Object *sftrstf; // [28:28] Software reset flag + Object *iwdgrstf; // [29:29] Independent watchdog reset flag + Object *wwdgrstf; // [30:30] Window watchdog reset flag + Object *lpwrrstf; // [31:31] Low-power reset flag + } csr; + + // AHBRSTR (AHB peripheral reset register) bitfields. + struct { + Object *ioparst; // [17:17] I/O port A reset + Object *iopbrst; // [18:18] I/O port B reset + Object *iopcrst; // [19:19] I/O port C reset + Object *iopdrst; // [20:20] I/O port D reset + Object *iopfrst; // [22:22] I/O port F reset + Object *tscrst; // [24:24] Touch sensing controller reset + } ahbrstr; + + // CFGR2 (Clock configuration register 2) bitfields. + struct { + Object *prediv; // [0:3] PREDIV division factor + } cfgr2; + + // CFGR3 (Clock configuration register 3) bitfields. + struct { + Object *usart1sw; // [0:1] USART1 clock source selection + Object *i2c1sw; // [4:4] I2C1 clock source selection + Object *cecsw; // [6:6] HDMI CEC clock source selection + Object *usbsw; // [7:7] USB clock source selection + Object *adcsw; // [8:8] ADC clock source selection + Object *usart2sw; // [16:17] USART2 clock source selection + } cfgr3; + + // CR2 (Clock control register 2) bitfields. + struct { + Object *hsi14on; // [0:0] HSI14 clock enable + Object *hsi14rdy; // [1:1] HR14 clock ready flag + Object *hsi14dis; // [2:2] HSI14 clock request from ADC disable + Object *hsi14trim; // [3:7] HSI14 clock trimming + Object *hsi14cal; // [8:15] HSI14 clock calibration + Object *hsi48on; // [16:16] HSI48 clock enable + Object *hsi48rdy; // [17:17] HSI48 clock ready flag + Object *hsi48cal; // [24:24] HSI48 factory clock calibration + } cr2; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RCCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RCC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/rtc.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/rtc.c new file mode 100644 index 0000000000..dee101ed2b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/rtc.c @@ -0,0 +1,395 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_rtc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.tr = cm_object_get_child_by_name(obj, "TR"); + state->u.f0.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.prer = cm_object_get_child_by_name(obj, "PRER"); + state->u.f0.reg.alrmar = cm_object_get_child_by_name(obj, "ALRMAR"); + state->u.f0.reg.wpr = cm_object_get_child_by_name(obj, "WPR"); + state->u.f0.reg.ssr = cm_object_get_child_by_name(obj, "SSR"); + state->u.f0.reg.shiftr = cm_object_get_child_by_name(obj, "SHIFTR"); + state->u.f0.reg.tstr = cm_object_get_child_by_name(obj, "TSTR"); + state->u.f0.reg.tsdr = cm_object_get_child_by_name(obj, "TSDR"); + state->u.f0.reg.tsssr = cm_object_get_child_by_name(obj, "TSSSR"); + state->u.f0.reg.calr = cm_object_get_child_by_name(obj, "CALR"); + state->u.f0.reg.tafcr = cm_object_get_child_by_name(obj, "TAFCR"); + state->u.f0.reg.alrmassr = cm_object_get_child_by_name(obj, "ALRMASSR"); + state->u.f0.reg.bkp0r = cm_object_get_child_by_name(obj, "BKP0R"); + state->u.f0.reg.bkp1r = cm_object_get_child_by_name(obj, "BKP1R"); + state->u.f0.reg.bkp2r = cm_object_get_child_by_name(obj, "BKP2R"); + state->u.f0.reg.bkp3r = cm_object_get_child_by_name(obj, "BKP3R"); + state->u.f0.reg.bkp4r = cm_object_get_child_by_name(obj, "BKP4R"); + + + // TR bitfields. + state->u.f0.fld.tr.su = cm_object_get_child_by_name(state->u.f0.reg.tr, "SU"); + state->u.f0.fld.tr.st = cm_object_get_child_by_name(state->u.f0.reg.tr, "ST"); + state->u.f0.fld.tr.mnu = cm_object_get_child_by_name(state->u.f0.reg.tr, "MNU"); + state->u.f0.fld.tr.mnt = cm_object_get_child_by_name(state->u.f0.reg.tr, "MNT"); + state->u.f0.fld.tr.hu = cm_object_get_child_by_name(state->u.f0.reg.tr, "HU"); + state->u.f0.fld.tr.ht = cm_object_get_child_by_name(state->u.f0.reg.tr, "HT"); + state->u.f0.fld.tr.pm = cm_object_get_child_by_name(state->u.f0.reg.tr, "PM"); + + // DR bitfields. + state->u.f0.fld.dr.du = cm_object_get_child_by_name(state->u.f0.reg.dr, "DU"); + state->u.f0.fld.dr.dt = cm_object_get_child_by_name(state->u.f0.reg.dr, "DT"); + state->u.f0.fld.dr.mu = cm_object_get_child_by_name(state->u.f0.reg.dr, "MU"); + state->u.f0.fld.dr.mt = cm_object_get_child_by_name(state->u.f0.reg.dr, "MT"); + state->u.f0.fld.dr.wdu = cm_object_get_child_by_name(state->u.f0.reg.dr, "WDU"); + state->u.f0.fld.dr.yu = cm_object_get_child_by_name(state->u.f0.reg.dr, "YU"); + state->u.f0.fld.dr.yt = cm_object_get_child_by_name(state->u.f0.reg.dr, "YT"); + + // CR bitfields. + state->u.f0.fld.cr.tsedge = cm_object_get_child_by_name(state->u.f0.reg.cr, "TSEDGE"); + state->u.f0.fld.cr.refckon = cm_object_get_child_by_name(state->u.f0.reg.cr, "REFCKON"); + state->u.f0.fld.cr.bypshad = cm_object_get_child_by_name(state->u.f0.reg.cr, "BYPSHAD"); + state->u.f0.fld.cr.fmt = cm_object_get_child_by_name(state->u.f0.reg.cr, "FMT"); + state->u.f0.fld.cr.alrae = cm_object_get_child_by_name(state->u.f0.reg.cr, "ALRAE"); + state->u.f0.fld.cr.tse = cm_object_get_child_by_name(state->u.f0.reg.cr, "TSE"); + state->u.f0.fld.cr.alraie = cm_object_get_child_by_name(state->u.f0.reg.cr, "ALRAIE"); + state->u.f0.fld.cr.tsie = cm_object_get_child_by_name(state->u.f0.reg.cr, "TSIE"); + state->u.f0.fld.cr.add1h = cm_object_get_child_by_name(state->u.f0.reg.cr, "ADD1H"); + state->u.f0.fld.cr.sub1h = cm_object_get_child_by_name(state->u.f0.reg.cr, "SUB1H"); + state->u.f0.fld.cr.bkp = cm_object_get_child_by_name(state->u.f0.reg.cr, "BKP"); + state->u.f0.fld.cr.cosel = cm_object_get_child_by_name(state->u.f0.reg.cr, "COSEL"); + state->u.f0.fld.cr.pol = cm_object_get_child_by_name(state->u.f0.reg.cr, "POL"); + state->u.f0.fld.cr.osel = cm_object_get_child_by_name(state->u.f0.reg.cr, "OSEL"); + state->u.f0.fld.cr.coe = cm_object_get_child_by_name(state->u.f0.reg.cr, "COE"); + + // ISR bitfields. + state->u.f0.fld.isr.alrawf = cm_object_get_child_by_name(state->u.f0.reg.isr, "ALRAWF"); + state->u.f0.fld.isr.shpf = cm_object_get_child_by_name(state->u.f0.reg.isr, "SHPF"); + state->u.f0.fld.isr.inits = cm_object_get_child_by_name(state->u.f0.reg.isr, "INITS"); + state->u.f0.fld.isr.rsf = cm_object_get_child_by_name(state->u.f0.reg.isr, "RSF"); + state->u.f0.fld.isr.initf = cm_object_get_child_by_name(state->u.f0.reg.isr, "INITF"); + state->u.f0.fld.isr.init = cm_object_get_child_by_name(state->u.f0.reg.isr, "INIT"); + state->u.f0.fld.isr.alraf = cm_object_get_child_by_name(state->u.f0.reg.isr, "ALRAF"); + state->u.f0.fld.isr.tsf = cm_object_get_child_by_name(state->u.f0.reg.isr, "TSF"); + state->u.f0.fld.isr.tsovf = cm_object_get_child_by_name(state->u.f0.reg.isr, "TSOVF"); + state->u.f0.fld.isr.tamp1f = cm_object_get_child_by_name(state->u.f0.reg.isr, "TAMP1F"); + state->u.f0.fld.isr.tamp2f = cm_object_get_child_by_name(state->u.f0.reg.isr, "TAMP2F"); + state->u.f0.fld.isr.recalpf = cm_object_get_child_by_name(state->u.f0.reg.isr, "RECALPF"); + + // PRER bitfields. + state->u.f0.fld.prer.prediv_s = cm_object_get_child_by_name(state->u.f0.reg.prer, "PREDIV_S"); + state->u.f0.fld.prer.prediv_a = cm_object_get_child_by_name(state->u.f0.reg.prer, "PREDIV_A"); + + // ALRMAR bitfields. + state->u.f0.fld.alrmar.su = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "SU"); + state->u.f0.fld.alrmar.st = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "ST"); + state->u.f0.fld.alrmar.msk1 = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK1"); + state->u.f0.fld.alrmar.mnu = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MNU"); + state->u.f0.fld.alrmar.mnt = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MNT"); + state->u.f0.fld.alrmar.msk2 = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK2"); + state->u.f0.fld.alrmar.hu = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "HU"); + state->u.f0.fld.alrmar.ht = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "HT"); + state->u.f0.fld.alrmar.pm = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "PM"); + state->u.f0.fld.alrmar.msk3 = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK3"); + state->u.f0.fld.alrmar.du = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "DU"); + state->u.f0.fld.alrmar.dt = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "DT"); + state->u.f0.fld.alrmar.wdsel = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "WDSEL"); + state->u.f0.fld.alrmar.msk4 = cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK4"); + + // WPR bitfields. + state->u.f0.fld.wpr.key = cm_object_get_child_by_name(state->u.f0.reg.wpr, "KEY"); + + // SSR bitfields. + state->u.f0.fld.ssr.ss = cm_object_get_child_by_name(state->u.f0.reg.ssr, "SS"); + + // SHIFTR bitfields. + state->u.f0.fld.shiftr.subfs = cm_object_get_child_by_name(state->u.f0.reg.shiftr, "SUBFS"); + state->u.f0.fld.shiftr.add1s = cm_object_get_child_by_name(state->u.f0.reg.shiftr, "ADD1S"); + + // TSTR bitfields. + state->u.f0.fld.tstr.su = cm_object_get_child_by_name(state->u.f0.reg.tstr, "SU"); + state->u.f0.fld.tstr.st = cm_object_get_child_by_name(state->u.f0.reg.tstr, "ST"); + state->u.f0.fld.tstr.mnu = cm_object_get_child_by_name(state->u.f0.reg.tstr, "MNU"); + state->u.f0.fld.tstr.mnt = cm_object_get_child_by_name(state->u.f0.reg.tstr, "MNT"); + state->u.f0.fld.tstr.hu = cm_object_get_child_by_name(state->u.f0.reg.tstr, "HU"); + state->u.f0.fld.tstr.ht = cm_object_get_child_by_name(state->u.f0.reg.tstr, "HT"); + state->u.f0.fld.tstr.pm = cm_object_get_child_by_name(state->u.f0.reg.tstr, "PM"); + + // TSDR bitfields. + state->u.f0.fld.tsdr.du = cm_object_get_child_by_name(state->u.f0.reg.tsdr, "DU"); + state->u.f0.fld.tsdr.dt = cm_object_get_child_by_name(state->u.f0.reg.tsdr, "DT"); + state->u.f0.fld.tsdr.mu = cm_object_get_child_by_name(state->u.f0.reg.tsdr, "MU"); + state->u.f0.fld.tsdr.mt = cm_object_get_child_by_name(state->u.f0.reg.tsdr, "MT"); + state->u.f0.fld.tsdr.wdu = cm_object_get_child_by_name(state->u.f0.reg.tsdr, "WDU"); + + // TSSSR bitfields. + state->u.f0.fld.tsssr.ss = cm_object_get_child_by_name(state->u.f0.reg.tsssr, "SS"); + + // CALR bitfields. + state->u.f0.fld.calr.calm = cm_object_get_child_by_name(state->u.f0.reg.calr, "CALM"); + state->u.f0.fld.calr.calw16 = cm_object_get_child_by_name(state->u.f0.reg.calr, "CALW16"); + state->u.f0.fld.calr.calw8 = cm_object_get_child_by_name(state->u.f0.reg.calr, "CALW8"); + state->u.f0.fld.calr.calp = cm_object_get_child_by_name(state->u.f0.reg.calr, "CALP"); + + // TAFCR bitfields. + state->u.f0.fld.tafcr.tamp1e = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP1E"); + state->u.f0.fld.tafcr.tamp1trg = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP1TRG"); + state->u.f0.fld.tafcr.tampie = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPIE"); + state->u.f0.fld.tafcr.tamp2e = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP2E"); + state->u.f0.fld.tafcr.tamp2_trg = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP2_TRG"); + state->u.f0.fld.tafcr.tampts = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPTS"); + state->u.f0.fld.tafcr.tampfreq = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPFREQ"); + state->u.f0.fld.tafcr.tampflt = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPFLT"); + state->u.f0.fld.tafcr.tamp_prch = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP_PRCH"); + state->u.f0.fld.tafcr.tamp_pudis = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP_PUDIS"); + state->u.f0.fld.tafcr.pc13value = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC13VALUE"); + state->u.f0.fld.tafcr.pc13mode = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC13MODE"); + state->u.f0.fld.tafcr.pc14value = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC14VALUE"); + state->u.f0.fld.tafcr.pc14mode = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC14MODE"); + state->u.f0.fld.tafcr.pc15value = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC15VALUE"); + state->u.f0.fld.tafcr.pc15mode = cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC15MODE"); + + // ALRMASSR bitfields. + state->u.f0.fld.alrmassr.ss = cm_object_get_child_by_name(state->u.f0.reg.alrmassr, "SS"); + state->u.f0.fld.alrmassr.maskss = cm_object_get_child_by_name(state->u.f0.reg.alrmassr, "MASKSS"); + + // BKP0R bitfields. + state->u.f0.fld.bkp0r.bkp = cm_object_get_child_by_name(state->u.f0.reg.bkp0r, "BKP"); + + // BKP1R bitfields. + state->u.f0.fld.bkp1r.bkp = cm_object_get_child_by_name(state->u.f0.reg.bkp1r, "BKP"); + + // BKP2R bitfields. + state->u.f0.fld.bkp2r.bkp = cm_object_get_child_by_name(state->u.f0.reg.bkp2r, "BKP"); + + // BKP3R bitfields. + state->u.f0.fld.bkp3r.bkp = cm_object_get_child_by_name(state->u.f0.reg.bkp3r, "BKP"); + + // BKP4R bitfields. + state->u.f0.fld.bkp4r.bkp = cm_object_get_child_by_name(state->u.f0.reg.bkp4r, "BKP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rtc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rtc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rtc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rtc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rtc_is_enabled(Object *obj) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rtc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RTCState *state = STM32_RTC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rtc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RTC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RTCState *state = STM32_RTC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RTC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_rtc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rtc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_rtc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rtc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_rtc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RTCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rtc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RTC); +} + +static void stm32_rtc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rtc_reset_callback; + dc->realize = stm32_rtc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rtc_is_enabled; +} + +static const TypeInfo stm32_rtc_type_info = { + .name = TYPE_STM32_RTC, + .parent = TYPE_STM32_RTC_PARENT, + .instance_init = stm32_rtc_instance_init_callback, + .instance_size = sizeof(STM32RTCState), + .class_init = stm32_rtc_class_init_callback, + .class_size = sizeof(STM32RTCClass) }; + +static void stm32_rtc_register_types(void) +{ + type_register_static(&stm32_rtc_type_info); +} + +type_init(stm32_rtc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/rtc.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/rtc.h new file mode 100644 index 0000000000..78179abcda --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/rtc.h @@ -0,0 +1,300 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RTC_H_ +#define STM32_RTC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RTC DEVICE_PATH_STM32 "RTC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RTC TYPE_STM32_PREFIX "rtc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RTC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RTCParentClass; +typedef PeripheralState STM32RTCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RTCClass, (obj), TYPE_STM32_RTC) +#define STM32_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RTCClass, (klass), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentClass parent_class; + // public: + + // None, so far. +} STM32RTCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RTC_STATE(obj) \ + OBJECT_CHECK(STM32RTCState, (obj), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 RTC (Real-time clock) registers. + struct { + Object *tr; // 0x0 (Time register) + Object *dr; // 0x4 (Date register) + Object *cr; // 0x8 (Control register) + Object *isr; // 0xC (Initialization and status register) + Object *prer; // 0x10 (Prescaler register) + Object *alrmar; // 0x1C (Alarm A register) + Object *wpr; // 0x24 (Write protection register) + Object *ssr; // 0x28 (Sub second register) + Object *shiftr; // 0x2C (Shift control register) + Object *tstr; // 0x30 (Timestamp time register) + Object *tsdr; // 0x34 (Timestamp date register) + Object *tsssr; // 0x38 (Time-stamp sub second register) + Object *calr; // 0x3C (Calibration register) + Object *tafcr; // 0x40 (Tamper and alternate function configuration register) + Object *alrmassr; // 0x44 (Alarm A sub second register) + Object *bkp0r; // 0x50 (Backup register) + Object *bkp1r; // 0x54 (Backup register) + Object *bkp2r; // 0x58 (Backup register) + Object *bkp3r; // 0x5C (Backup register) + Object *bkp4r; // 0x60 (Backup register) + } reg; + + struct { + + // TR (Time register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + } tr; + + // DR (Date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + Object *yu; // [16:19] Year units in BCD format + Object *yt; // [20:23] Year tens in BCD format + } dr; + + // CR (Control register) bitfields. + struct { + Object *tsedge; // [3:3] Time-stamp event active edge + Object *refckon; // [4:4] RTC_REFIN reference clock detection enable (50 or 60 Hz) + Object *bypshad; // [5:5] Bypass the shadow registers + Object *fmt; // [6:6] Hour format + Object *alrae; // [8:8] Alarm A enable + Object *tse; // [11:11] Timestamp enable + Object *alraie; // [12:12] Alarm A interrupt enable + Object *tsie; // [15:15] Time-stamp interrupt enable + Object *add1h; // [16:16] Add 1 hour (summer time change) + Object *sub1h; // [17:17] Subtract 1 hour (winter time change) + Object *bkp; // [18:18] Backup + Object *cosel; // [19:19] Calibration output selection + Object *pol; // [20:20] Output polarity + Object *osel; // [21:22] Output selection + Object *coe; // [23:23] Calibration output enable + } cr; + + // ISR (Initialization and status register) bitfields. + struct { + Object *alrawf; // [0:0] Alarm A write flag + Object *shpf; // [3:3] Shift operation pending + Object *inits; // [4:4] Initialization status flag + Object *rsf; // [5:5] Registers synchronization flag + Object *initf; // [6:6] Initialization flag + Object *init; // [7:7] Initialization mode + Object *alraf; // [8:8] Alarm A flag + Object *tsf; // [11:11] Time-stamp flag + Object *tsovf; // [12:12] Time-stamp overflow flag + Object *tamp1f; // [13:13] RTC_TAMP1 detection flag + Object *tamp2f; // [14:14] RTC_TAMP2 detection flag + Object *recalpf; // [16:16] Recalibration pending Flag + } isr; + + // PRER (Prescaler register) bitfields. + struct { + Object *prediv_s; // [0:14] Synchronous prescaler factor + Object *prediv_a; // [16:22] Asynchronous prescaler factor + } prer; + + // ALRMAR (Alarm A register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format. + Object *st; // [4:6] Second tens in BCD format. + Object *msk1; // [7:7] Alarm A seconds mask + Object *mnu; // [8:11] Minute units in BCD format. + Object *mnt; // [12:14] Minute tens in BCD format. + Object *msk2; // [15:15] Alarm A minutes mask + Object *hu; // [16:19] Hour units in BCD format. + Object *ht; // [20:21] Hour tens in BCD format. + Object *pm; // [22:22] AM/PM notation + Object *msk3; // [23:23] Alarm A hours mask + Object *du; // [24:27] Date units or day in BCD format. + Object *dt; // [28:29] Date tens in BCD format. + Object *wdsel; // [30:30] Week day selection + Object *msk4; // [31:31] Alarm A date mask + } alrmar; + + // WPR (Write protection register) bitfields. + struct { + Object *key; // [0:7] Write protection key + } wpr; + + // SSR (Sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } ssr; + + // SHIFTR (Shift control register) bitfields. + struct { + Object *subfs; // [0:14] Subtract a fraction of a second + Object *add1s; // [31:31] Reserved + } shiftr; + + // TSTR (Timestamp time register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format. + Object *st; // [4:6] Second tens in BCD format. + Object *mnu; // [8:11] Minute units in BCD format. + Object *mnt; // [12:14] Minute tens in BCD format. + Object *hu; // [16:19] Hour units in BCD format. + Object *ht; // [20:21] Hour tens in BCD format. + Object *pm; // [22:22] AM/PM notation + } tstr; + + // TSDR (Timestamp date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + } tsdr; + + // TSSSR (Time-stamp sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } tsssr; + + // CALR (Calibration register) bitfields. + struct { + Object *calm; // [0:8] Calibration minus + Object *calw16; // [13:13] Reserved + Object *calw8; // [14:14] Use a 16-second calibration cycle period + Object *calp; // [15:15] Use an 8-second calibration cycle period + } calr; + + // TAFCR (Tamper and alternate function configuration register) bitfields. + struct { + Object *tamp1e; // [0:0] RTC_TAMP1 input detection enable + Object *tamp1trg; // [1:1] Active level for RTC_TAMP1 input + Object *tampie; // [2:2] Tamper interrupt enable + Object *tamp2e; // [3:3] RTC_TAMP2 input detection enable + Object *tamp2_trg; // [4:4] Active level for RTC_TAMP2 input + Object *tampts; // [7:7] Activate timestamp on tamper detection event + Object *tampfreq; // [8:10] Tamper sampling frequency + Object *tampflt; // [11:12] RTC_TAMPx filter count + Object *tamp_prch; // [13:14] RTC_TAMPx precharge duration + Object *tamp_pudis; // [15:15] RTC_TAMPx pull-up disable + Object *pc13value; // [18:18] RTC_ALARM output type/PC13 value + Object *pc13mode; // [19:19] PC13 mode + Object *pc14value; // [20:20] PC14 value + Object *pc14mode; // [21:21] PC14 mode + Object *pc15value; // [22:22] PC15 value + Object *pc15mode; // [23:23] PC15 mode + } tafcr; + + // ALRMASSR (Alarm A sub second register) bitfields. + struct { + Object *ss; // [0:14] Sub seconds value + Object *maskss; // [24:27] Mask the most-significant bits starting at this bit + } alrmassr; + + // BKP0R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp0r; + + // BKP1R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp1r; + + // BKP2R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp2r; + + // BKP3R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp3r; + + // BKP4R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp4r; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RTCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RTC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/spi1.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/spi1.c new file mode 100644 index 0000000000..d979885d68 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/spi1.c @@ -0,0 +1,318 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_spi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f0.reg.crcpr = cm_object_get_child_by_name(obj, "CRCPR"); + state->u.f0.reg.rxcrcr = cm_object_get_child_by_name(obj, "RXCRCR"); + state->u.f0.reg.txcrcr = cm_object_get_child_by_name(obj, "TXCRCR"); + state->u.f0.reg.i2scfgr = cm_object_get_child_by_name(obj, "I2SCFGR"); + state->u.f0.reg.i2spr = cm_object_get_child_by_name(obj, "I2SPR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.cpha = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CPHA"); + state->u.f0.fld.cr1.cpol = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CPOL"); + state->u.f0.fld.cr1.mstr = cm_object_get_child_by_name(state->u.f0.reg.cr1, "MSTR"); + state->u.f0.fld.cr1.br = cm_object_get_child_by_name(state->u.f0.reg.cr1, "BR"); + state->u.f0.fld.cr1.spe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "SPE"); + state->u.f0.fld.cr1.lsbfirst = cm_object_get_child_by_name(state->u.f0.reg.cr1, "LSBFIRST"); + state->u.f0.fld.cr1.ssi = cm_object_get_child_by_name(state->u.f0.reg.cr1, "SSI"); + state->u.f0.fld.cr1.ssm = cm_object_get_child_by_name(state->u.f0.reg.cr1, "SSM"); + state->u.f0.fld.cr1.rxonly = cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXONLY"); + state->u.f0.fld.cr1.dff = cm_object_get_child_by_name(state->u.f0.reg.cr1, "DFF"); + state->u.f0.fld.cr1.crcnext = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CRCNEXT"); + state->u.f0.fld.cr1.crcen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CRCEN"); + state->u.f0.fld.cr1.bidioe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "BIDIOE"); + state->u.f0.fld.cr1.bidimode = cm_object_get_child_by_name(state->u.f0.reg.cr1, "BIDIMODE"); + + // CR2 bitfields. + state->u.f0.fld.cr2.rxdmaen = cm_object_get_child_by_name(state->u.f0.reg.cr2, "RXDMAEN"); + state->u.f0.fld.cr2.txdmaen = cm_object_get_child_by_name(state->u.f0.reg.cr2, "TXDMAEN"); + state->u.f0.fld.cr2.ssoe = cm_object_get_child_by_name(state->u.f0.reg.cr2, "SSOE"); + state->u.f0.fld.cr2.nssp = cm_object_get_child_by_name(state->u.f0.reg.cr2, "NSSP"); + state->u.f0.fld.cr2.frf = cm_object_get_child_by_name(state->u.f0.reg.cr2, "FRF"); + state->u.f0.fld.cr2.errie = cm_object_get_child_by_name(state->u.f0.reg.cr2, "ERRIE"); + state->u.f0.fld.cr2.rxneie = cm_object_get_child_by_name(state->u.f0.reg.cr2, "RXNEIE"); + state->u.f0.fld.cr2.txeie = cm_object_get_child_by_name(state->u.f0.reg.cr2, "TXEIE"); + state->u.f0.fld.cr2.ds = cm_object_get_child_by_name(state->u.f0.reg.cr2, "DS"); + state->u.f0.fld.cr2.frxth = cm_object_get_child_by_name(state->u.f0.reg.cr2, "FRXTH"); + state->u.f0.fld.cr2.ldma_rx = cm_object_get_child_by_name(state->u.f0.reg.cr2, "LDMA_RX"); + state->u.f0.fld.cr2.ldma_tx = cm_object_get_child_by_name(state->u.f0.reg.cr2, "LDMA_TX"); + + // SR bitfields. + state->u.f0.fld.sr.rxne = cm_object_get_child_by_name(state->u.f0.reg.sr, "RXNE"); + state->u.f0.fld.sr.txe = cm_object_get_child_by_name(state->u.f0.reg.sr, "TXE"); + state->u.f0.fld.sr.chside = cm_object_get_child_by_name(state->u.f0.reg.sr, "CHSIDE"); + state->u.f0.fld.sr.udr = cm_object_get_child_by_name(state->u.f0.reg.sr, "UDR"); + state->u.f0.fld.sr.crcerr = cm_object_get_child_by_name(state->u.f0.reg.sr, "CRCERR"); + state->u.f0.fld.sr.modf = cm_object_get_child_by_name(state->u.f0.reg.sr, "MODF"); + state->u.f0.fld.sr.ovr = cm_object_get_child_by_name(state->u.f0.reg.sr, "OVR"); + state->u.f0.fld.sr.bsy = cm_object_get_child_by_name(state->u.f0.reg.sr, "BSY"); + state->u.f0.fld.sr.tifrfe = cm_object_get_child_by_name(state->u.f0.reg.sr, "TIFRFE"); + state->u.f0.fld.sr.frlvl = cm_object_get_child_by_name(state->u.f0.reg.sr, "FRLVL"); + state->u.f0.fld.sr.ftlvl = cm_object_get_child_by_name(state->u.f0.reg.sr, "FTLVL"); + + // DR bitfields. + state->u.f0.fld.dr.dr = cm_object_get_child_by_name(state->u.f0.reg.dr, "DR"); + + // CRCPR bitfields. + state->u.f0.fld.crcpr.crcpoly = cm_object_get_child_by_name(state->u.f0.reg.crcpr, "CRCPOLY"); + + // RXCRCR bitfields. + state->u.f0.fld.rxcrcr.rxcrc = cm_object_get_child_by_name(state->u.f0.reg.rxcrcr, "RxCRC"); + + // TXCRCR bitfields. + state->u.f0.fld.txcrcr.txcrc = cm_object_get_child_by_name(state->u.f0.reg.txcrcr, "TxCRC"); + + // I2SCFGR bitfields. + state->u.f0.fld.i2scfgr.chlen = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "CHLEN"); + state->u.f0.fld.i2scfgr.datlen = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "DATLEN"); + state->u.f0.fld.i2scfgr.ckpol = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "CKPOL"); + state->u.f0.fld.i2scfgr.i2sstd = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SSTD"); + state->u.f0.fld.i2scfgr.pcmsync = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "PCMSYNC"); + state->u.f0.fld.i2scfgr.i2scfg = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SCFG"); + state->u.f0.fld.i2scfgr.i2se = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SE"); + state->u.f0.fld.i2scfgr.i2smod = cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SMOD"); + + // I2SPR bitfields. + state->u.f0.fld.i2spr.i2sdiv = cm_object_get_child_by_name(state->u.f0.reg.i2spr, "I2SDIV"); + state->u.f0.fld.i2spr.odd = cm_object_get_child_by_name(state->u.f0.reg.i2spr, "ODD"); + state->u.f0.fld.i2spr.mckoe = cm_object_get_child_by_name(state->u.f0.reg.i2spr, "MCKOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_spi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_spi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_spi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_spi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_spi_is_enabled(Object *obj) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_spi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SPIState *state = STM32_SPI_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_SPI_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_spi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SPI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SPIState *state = STM32_SPI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SPI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_spi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_spi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_spi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_spi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_spi_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SPI%dEN", + 1 + state->port_index - STM32_PORT_SPI1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_spi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SPI); +} + +static void stm32_spi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_spi_reset_callback; + dc->realize = stm32_spi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_spi_is_enabled; +} + +static const TypeInfo stm32_spi_type_info = { + .name = TYPE_STM32_SPI, + .parent = TYPE_STM32_SPI_PARENT, + .instance_init = stm32_spi_instance_init_callback, + .instance_size = sizeof(STM32SPIState), + .class_init = stm32_spi_class_init_callback, + .class_size = sizeof(STM32SPIClass) }; + +static void stm32_spi_register_types(void) +{ + type_register_static(&stm32_spi_type_info); +} + +type_init(stm32_spi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/spi1.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/spi1.h new file mode 100644 index 0000000000..7dc7a5e202 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/spi1.h @@ -0,0 +1,207 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SPI_H_ +#define STM32_SPI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SPI DEVICE_PATH_STM32 "SPI" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_SPI1, + STM32_PORT_SPI2, + STM32_PORT_SPI_UNDEFINED = 0xFF, +} stm32_spi_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SPI TYPE_STM32_PREFIX "spi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SPI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SPIParentClass; +typedef PeripheralState STM32SPIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SPI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SPIClass, (obj), TYPE_STM32_SPI) +#define STM32_SPI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SPIClass, (klass), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentClass parent_class; + // public: + + // None, so far. +} STM32SPIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SPI_STATE(obj) \ + OBJECT_CHECK(STM32SPIState, (obj), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_spi_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 SPI (Serial peripheral interface) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *sr; // 0x8 (Status register) + Object *dr; // 0xC (Data register) + Object *crcpr; // 0x10 (CRC polynomial register) + Object *rxcrcr; // 0x14 (RX CRC register) + Object *txcrcr; // 0x18 (TX CRC register) + Object *i2scfgr; // 0x1C (I2S configuration register) + Object *i2spr; // 0x20 (I2S prescaler register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cpha; // [0:0] Clock phase + Object *cpol; // [1:1] Clock polarity + Object *mstr; // [2:2] Master selection + Object *br; // [3:5] Baud rate control + Object *spe; // [6:6] SPI enable + Object *lsbfirst; // [7:7] Frame format + Object *ssi; // [8:8] Internal slave select + Object *ssm; // [9:9] Software slave management + Object *rxonly; // [10:10] Receive only + Object *dff; // [11:11] Data frame format + Object *crcnext; // [12:12] CRC transfer next + Object *crcen; // [13:13] Hardware CRC calculation enable + Object *bidioe; // [14:14] Output enable in bidirectional mode + Object *bidimode; // [15:15] Bidirectional data mode enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *rxdmaen; // [0:0] Rx buffer DMA enable + Object *txdmaen; // [1:1] Tx buffer DMA enable + Object *ssoe; // [2:2] SS output enable + Object *nssp; // [3:3] NSS pulse management + Object *frf; // [4:4] Frame format + Object *errie; // [5:5] Error interrupt enable + Object *rxneie; // [6:6] RX buffer not empty interrupt enable + Object *txeie; // [7:7] Tx buffer empty interrupt enable + Object *ds; // [8:11] Data size + Object *frxth; // [12:12] FIFO reception threshold + Object *ldma_rx; // [13:13] Last DMA transfer for reception + Object *ldma_tx; // [14:14] Last DMA transfer for transmission + } cr2; + + // SR (Status register) bitfields. + struct { + Object *rxne; // [0:0] Receive buffer not empty + Object *txe; // [1:1] Transmit buffer empty + Object *chside; // [2:2] Channel side + Object *udr; // [3:3] Underrun flag + Object *crcerr; // [4:4] CRC error flag + Object *modf; // [5:5] Mode fault + Object *ovr; // [6:6] Overrun flag + Object *bsy; // [7:7] Busy flag + Object *tifrfe; // [8:8] TI frame format error + Object *frlvl; // [9:10] FIFO reception level + Object *ftlvl; // [11:12] FIFO transmission level + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:15] Data register + } dr; + + // CRCPR (CRC polynomial register) bitfields. + struct { + Object *crcpoly; // [0:15] CRC polynomial register + } crcpr; + + // RXCRCR (RX CRC register) bitfields. + struct { + Object *rxcrc; // [0:15] Rx CRC register + } rxcrcr; + + // TXCRCR (TX CRC register) bitfields. + struct { + Object *txcrc; // [0:15] Tx CRC register + } txcrcr; + + // I2SCFGR (I2S configuration register) bitfields. + struct { + Object *chlen; // [0:0] Channel length (number of bits per audio channel) + Object *datlen; // [1:2] Data length to be transferred + Object *ckpol; // [3:3] Steady state clock polarity + Object *i2sstd; // [4:5] I2S standard selection + Object *pcmsync; // [7:7] PCM frame synchronization + Object *i2scfg; // [8:9] I2S configuration mode + Object *i2se; // [10:10] I2S Enable + Object *i2smod; // [11:11] I2S mode selection + } i2scfgr; + + // I2SPR (I2S prescaler register) bitfields. + struct { + Object *i2sdiv; // [0:7] I2S Linear prescaler + Object *odd; // [8:8] Odd factor for the prescaler + Object *mckoe; // [9:9] Master clock output enable + } i2spr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SPIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SPI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/syscfg.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/syscfg.c new file mode 100644 index 0000000000..2b0a7ac37d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/syscfg.c @@ -0,0 +1,291 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_syscfg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cfgr1 = cm_object_get_child_by_name(obj, "CFGR1"); + state->u.f0.reg.exticr1 = cm_object_get_child_by_name(obj, "EXTICR1"); + state->u.f0.reg.exticr2 = cm_object_get_child_by_name(obj, "EXTICR2"); + state->u.f0.reg.exticr3 = cm_object_get_child_by_name(obj, "EXTICR3"); + state->u.f0.reg.exticr4 = cm_object_get_child_by_name(obj, "EXTICR4"); + state->u.f0.reg.cfgr2 = cm_object_get_child_by_name(obj, "CFGR2"); + + + // CFGR1 bitfields. + state->u.f0.fld.cfgr1.mem_mode = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "MEM_MODE"); + state->u.f0.fld.cfgr1.adc_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "ADC_DMA_RMP"); + state->u.f0.fld.cfgr1.usart1_tx_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART1_TX_DMA_RMP"); + state->u.f0.fld.cfgr1.usart1_rx_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART1_RX_DMA_RMP"); + state->u.f0.fld.cfgr1.tim16_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM16_DMA_RMP"); + state->u.f0.fld.cfgr1.tim17_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM17_DMA_RMP"); + state->u.f0.fld.cfgr1.i2c_pb6_fm = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB6_FM"); + state->u.f0.fld.cfgr1.i2c_pb7_fm = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB7_FM"); + state->u.f0.fld.cfgr1.i2c_pb8_fm = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB8_FM"); + state->u.f0.fld.cfgr1.i2c_pb9_fm = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB9_FM"); + state->u.f0.fld.cfgr1.i2c1_fm_plus = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C1_FM_plus"); + state->u.f0.fld.cfgr1.i2c2_fm_plus = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C2_FM_plus"); + state->u.f0.fld.cfgr1.spi2_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "SPI2_DMA_RMP"); + state->u.f0.fld.cfgr1.usart2_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART2_DMA_RMP"); + state->u.f0.fld.cfgr1.usart3_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART3_DMA_RMP"); + state->u.f0.fld.cfgr1.i2c1_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C1_DMA_RMP"); + state->u.f0.fld.cfgr1.tim1_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM1_DMA_RMP"); + state->u.f0.fld.cfgr1.tim2_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM2_DMA_RMP"); + state->u.f0.fld.cfgr1.tim3_dma_rmp = cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM3_DMA_RMP"); + + // EXTICR1 bitfields. + state->u.f0.fld.exticr1.exti0 = cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI0"); + state->u.f0.fld.exticr1.exti1 = cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI1"); + state->u.f0.fld.exticr1.exti2 = cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI2"); + state->u.f0.fld.exticr1.exti3 = cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI3"); + + // EXTICR2 bitfields. + state->u.f0.fld.exticr2.exti4 = cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI4"); + state->u.f0.fld.exticr2.exti5 = cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI5"); + state->u.f0.fld.exticr2.exti6 = cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI6"); + state->u.f0.fld.exticr2.exti7 = cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI7"); + + // EXTICR3 bitfields. + state->u.f0.fld.exticr3.exti8 = cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI8"); + state->u.f0.fld.exticr3.exti9 = cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI9"); + state->u.f0.fld.exticr3.exti10 = cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI10"); + state->u.f0.fld.exticr3.exti11 = cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI11"); + + // EXTICR4 bitfields. + state->u.f0.fld.exticr4.exti12 = cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI12"); + state->u.f0.fld.exticr4.exti13 = cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI13"); + state->u.f0.fld.exticr4.exti14 = cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI14"); + state->u.f0.fld.exticr4.exti15 = cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI15"); + + // CFGR2 bitfields. + state->u.f0.fld.cfgr2.locup_lock = cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "LOCUP_LOCK"); + state->u.f0.fld.cfgr2.sram_parity_lock = cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "SRAM_PARITY_LOCK"); + state->u.f0.fld.cfgr2.pvd_lock = cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "PVD_LOCK"); + state->u.f0.fld.cfgr2.sram_pef = cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "SRAM_PEF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_syscfg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_syscfg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_syscfg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_syscfg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_syscfg_is_enabled(Object *obj) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_syscfg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_syscfg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SYSCFG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SYSCFG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_syscfg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_syscfg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_syscfg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_syscfg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_syscfg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SYSCFGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_syscfg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SYSCFG); +} + +static void stm32_syscfg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_syscfg_reset_callback; + dc->realize = stm32_syscfg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_syscfg_is_enabled; +} + +static const TypeInfo stm32_syscfg_type_info = { + .name = TYPE_STM32_SYSCFG, + .parent = TYPE_STM32_SYSCFG_PARENT, + .instance_init = stm32_syscfg_instance_init_callback, + .instance_size = sizeof(STM32SYSCFGState), + .class_init = stm32_syscfg_class_init_callback, + .class_size = sizeof(STM32SYSCFGClass) }; + +static void stm32_syscfg_register_types(void) +{ + type_register_static(&stm32_syscfg_type_info); +} + +type_init(stm32_syscfg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/syscfg.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/syscfg.h new file mode 100644 index 0000000000..5c699c6131 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/syscfg.h @@ -0,0 +1,168 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SYSCFG_H_ +#define STM32_SYSCFG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SYSCFG DEVICE_PATH_STM32 "SYSCFG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SYSCFG TYPE_STM32_PREFIX "syscfg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SYSCFG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SYSCFGParentClass; +typedef PeripheralState STM32SYSCFGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SYSCFG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SYSCFGClass, (obj), TYPE_STM32_SYSCFG) +#define STM32_SYSCFG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SYSCFGClass, (klass), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentClass parent_class; + // public: + + // None, so far. +} STM32SYSCFGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SYSCFG_STATE(obj) \ + OBJECT_CHECK(STM32SYSCFGState, (obj), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 SYSCFG (System configuration controller) registers. + struct { + Object *cfgr1; // 0x0 (Configuration register 1) + Object *exticr1; // 0x8 (External interrupt configuration register 1) + Object *exticr2; // 0xC (External interrupt configuration register 2) + Object *exticr3; // 0x10 (External interrupt configuration register 3) + Object *exticr4; // 0x14 (External interrupt configuration register 4) + Object *cfgr2; // 0x18 (Configuration register 2) + } reg; + + struct { + + // CFGR1 (Configuration register 1) bitfields. + struct { + Object *mem_mode; // [0:1] Memory mapping selection bits + Object *adc_dma_rmp; // [8:8] ADC DMA remapping bit + Object *usart1_tx_dma_rmp; // [9:9] USART1_TX DMA remapping bit + Object *usart1_rx_dma_rmp; // [10:10] USART1_RX DMA request remapping bit + Object *tim16_dma_rmp; // [11:11] TIM16 DMA request remapping bit + Object *tim17_dma_rmp; // [12:12] TIM17 DMA request remapping bit + Object *i2c_pb6_fm; // [16:16] Fast Mode Plus (FM plus) driving capability activation bits. + Object *i2c_pb7_fm; // [17:17] Fast Mode Plus (FM+) driving capability activation bits. + Object *i2c_pb8_fm; // [18:18] Fast Mode Plus (FM+) driving capability activation bits. + Object *i2c_pb9_fm; // [19:19] Fast Mode Plus (FM+) driving capability activation bits. + Object *i2c1_fm_plus; // [20:20] FM+ driving capability activation for I2C1 + Object *i2c2_fm_plus; // [21:21] FM+ driving capability activation for I2C2 + Object *spi2_dma_rmp; // [24:24] SPI2 DMA request remapping bit + Object *usart2_dma_rmp; // [25:25] USART2 DMA request remapping bit + Object *usart3_dma_rmp; // [26:26] USART3 DMA request remapping bit + Object *i2c1_dma_rmp; // [27:27] I2C1 DMA request remapping bit + Object *tim1_dma_rmp; // [28:28] TIM1 DMA request remapping bit + Object *tim2_dma_rmp; // [29:29] TIM2 DMA request remapping bit + Object *tim3_dma_rmp; // [30:30] TIM3 DMA request remapping bit + } cfgr1; + + // EXTICR1 (External interrupt configuration register 1) bitfields. + struct { + Object *exti0; // [0:3] EXTI 0 configuration bits + Object *exti1; // [4:7] EXTI 1 configuration bits + Object *exti2; // [8:11] EXTI 2 configuration bits + Object *exti3; // [12:15] EXTI 3 configuration bits + } exticr1; + + // EXTICR2 (External interrupt configuration register 2) bitfields. + struct { + Object *exti4; // [0:3] EXTI 4 configuration bits + Object *exti5; // [4:7] EXTI 5 configuration bits + Object *exti6; // [8:11] EXTI 6 configuration bits + Object *exti7; // [12:15] EXTI 7 configuration bits + } exticr2; + + // EXTICR3 (External interrupt configuration register 3) bitfields. + struct { + Object *exti8; // [0:3] EXTI 8 configuration bits + Object *exti9; // [4:7] EXTI 9 configuration bits + Object *exti10; // [8:11] EXTI 10 configuration bits + Object *exti11; // [12:15] EXTI 11 configuration bits + } exticr3; + + // EXTICR4 (External interrupt configuration register 4) bitfields. + struct { + Object *exti12; // [0:3] EXTI 12 configuration bits + Object *exti13; // [4:7] EXTI 13 configuration bits + Object *exti14; // [8:11] EXTI 14 configuration bits + Object *exti15; // [12:15] EXTI 15 configuration bits + } exticr4; + + // CFGR2 (Configuration register 2) bitfields. + struct { + Object *locup_lock; // [0:0] Cortex-M0 LOCKUP bit enable bit + Object *sram_parity_lock; // [1:1] SRAM parity lock bit + Object *pvd_lock; // [2:2] PVD lock enable bit + Object *sram_pef; // [8:8] SRAM parity flag + } cfgr2; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SYSCFGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SYSCFG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim1.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim1.c new file mode 100644 index 0000000000..03d6b4e0c5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim1.c @@ -0,0 +1,427 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_tim1_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f0.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f0.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f0.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f0.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f0.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f0.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f0.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f0.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f0.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f0.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f0.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f0.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f0.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f0.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f0.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + state->u.f0.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f0.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.cen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); + state->u.f0.fld.cr1.udis = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); + state->u.f0.fld.cr1.urs = cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); + state->u.f0.fld.cr1.opm = cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); + state->u.f0.fld.cr1.dir = cm_object_get_child_by_name(state->u.f0.reg.cr1, "DIR"); + state->u.f0.fld.cr1.cms = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CMS"); + state->u.f0.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); + state->u.f0.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f0.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCPC"); + state->u.f0.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCUS"); + state->u.f0.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); + state->u.f0.fld.cr2.mms = cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); + state->u.f0.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f0.reg.cr2, "TI1S"); + state->u.f0.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1"); + state->u.f0.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1N"); + state->u.f0.fld.cr2.ois2 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS2"); + state->u.f0.fld.cr2.ois2n = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS2N"); + state->u.f0.fld.cr2.ois3 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS3"); + state->u.f0.fld.cr2.ois3n = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS3N"); + state->u.f0.fld.cr2.ois4 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS4"); + + // SMCR bitfields. + state->u.f0.fld.smcr.sms = cm_object_get_child_by_name(state->u.f0.reg.smcr, "SMS"); + state->u.f0.fld.smcr.ts = cm_object_get_child_by_name(state->u.f0.reg.smcr, "TS"); + state->u.f0.fld.smcr.msm = cm_object_get_child_by_name(state->u.f0.reg.smcr, "MSM"); + state->u.f0.fld.smcr.etf = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETF"); + state->u.f0.fld.smcr.etps = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETPS"); + state->u.f0.fld.smcr.ece = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ECE"); + state->u.f0.fld.smcr.etp = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f0.fld.dier.uie = cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); + state->u.f0.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); + state->u.f0.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2IE"); + state->u.f0.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3IE"); + state->u.f0.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4IE"); + state->u.f0.fld.dier.comie = cm_object_get_child_by_name(state->u.f0.reg.dier, "COMIE"); + state->u.f0.fld.dier.tie = cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); + state->u.f0.fld.dier.bie = cm_object_get_child_by_name(state->u.f0.reg.dier, "BIE"); + state->u.f0.fld.dier.ude = cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); + state->u.f0.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); + state->u.f0.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2DE"); + state->u.f0.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3DE"); + state->u.f0.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4DE"); + state->u.f0.fld.dier.comde = cm_object_get_child_by_name(state->u.f0.reg.dier, "COMDE"); + state->u.f0.fld.dier.tde = cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); + + // SR bitfields. + state->u.f0.fld.sr.uif = cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); + state->u.f0.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); + state->u.f0.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2IF"); + state->u.f0.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3IF"); + state->u.f0.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4IF"); + state->u.f0.fld.sr.comif = cm_object_get_child_by_name(state->u.f0.reg.sr, "COMIF"); + state->u.f0.fld.sr.tif = cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); + state->u.f0.fld.sr.bif = cm_object_get_child_by_name(state->u.f0.reg.sr, "BIF"); + state->u.f0.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); + state->u.f0.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2OF"); + state->u.f0.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3OF"); + state->u.f0.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f0.fld.egr.ug = cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); + state->u.f0.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); + state->u.f0.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC2G"); + state->u.f0.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC3G"); + state->u.f0.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC4G"); + state->u.f0.fld.egr.comg = cm_object_get_child_by_name(state->u.f0.reg.egr, "COMG"); + state->u.f0.fld.egr.tg = cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); + state->u.f0.fld.egr.bg = cm_object_get_child_by_name(state->u.f0.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f0.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); + state->u.f0.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); + state->u.f0.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); + state->u.f0.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); + state->u.f0.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1CE"); + state->u.f0.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC2S"); + state->u.f0.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2FE"); + state->u.f0.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2PE"); + state->u.f0.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2M"); + state->u.f0.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f0.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); + state->u.f0.fld.ccmr1_input.ic1pcs = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PCS"); + state->u.f0.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); + state->u.f0.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC2S"); + state->u.f0.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2PCS"); + state->u.f0.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f0.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC3S"); + state->u.f0.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3FE"); + state->u.f0.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3PE"); + state->u.f0.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3M"); + state->u.f0.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3CE"); + state->u.f0.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC4S"); + state->u.f0.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4FE"); + state->u.f0.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4PE"); + state->u.f0.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4M"); + state->u.f0.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f0.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC3S"); + state->u.f0.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3PSC"); + state->u.f0.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3F"); + state->u.f0.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC4S"); + state->u.f0.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4PSC"); + state->u.f0.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f0.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); + state->u.f0.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); + state->u.f0.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NE"); + state->u.f0.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); + state->u.f0.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2E"); + state->u.f0.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2P"); + state->u.f0.fld.ccer.cc2ne = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NE"); + state->u.f0.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NP"); + state->u.f0.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3E"); + state->u.f0.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3P"); + state->u.f0.fld.ccer.cc3ne = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3NE"); + state->u.f0.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3NP"); + state->u.f0.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4E"); + state->u.f0.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f0.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f0.fld.psc.psc = cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f0.fld.arr.arr = cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); + + // RCR bitfields. + state->u.f0.fld.rcr.rep = cm_object_get_child_by_name(state->u.f0.reg.rcr, "REP"); + + // CCR1 bitfields. + state->u.f0.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f0.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f0.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f0.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CCR4"); + + // BDTR bitfields. + state->u.f0.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "DTG"); + state->u.f0.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "LOCK"); + state->u.f0.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSI"); + state->u.f0.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSR"); + state->u.f0.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKE"); + state->u.f0.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKP"); + state->u.f0.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "AOE"); + state->u.f0.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "MOE"); + + // DCR bitfields. + state->u.f0.fld.dcr.dba = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); + state->u.f0.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f0.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim1_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim1_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim1_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim1_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim1_is_enabled(Object *obj) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim1_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim1_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM1)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM1State *state = STM32_TIM1_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM1"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_tim1_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim1_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim1_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim1_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim1_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM1EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim1_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM1); +} + +static void stm32_tim1_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim1_reset_callback; + dc->realize = stm32_tim1_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim1_is_enabled; +} + +static const TypeInfo stm32_tim1_type_info = { + .name = TYPE_STM32_TIM1, + .parent = TYPE_STM32_TIM1_PARENT, + .instance_init = stm32_tim1_instance_init_callback, + .instance_size = sizeof(STM32TIM1State), + .class_init = stm32_tim1_class_init_callback, + .class_size = sizeof(STM32TIM1Class) }; + +static void stm32_tim1_register_types(void) +{ + type_register_static(&stm32_tim1_type_info); +} + +type_init(stm32_tim1_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim1.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim1.h new file mode 100644 index 0000000000..42aadc5cdc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim1.h @@ -0,0 +1,336 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM1_H_ +#define STM32_TIM1_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM1 DEVICE_PATH_STM32 "TIM1" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM1 TYPE_STM32_PREFIX "tim1" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM1_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM1ParentClass; +typedef PeripheralState STM32TIM1ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM1_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM1Class, (obj), TYPE_STM32_TIM1) +#define STM32_TIM1_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM1Class, (klass), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM1Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM1_STATE(obj) \ + OBJECT_CHECK(STM32TIM1State, (obj), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 TIM1 (Advanced-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *rcr; // 0x30 (Repetition counter register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *bdtr; // 0x44 (Break and dead-time register) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + Object *ois2; // [10:10] Output Idle state 2 + Object *ois2n; // [11:11] Output Idle state 2 + Object *ois3; // [12:12] Output Idle state 3 + Object *ois3n; // [13:13] Output Idle state 3 + Object *ois4; // [14:14] Output Idle state 4 + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *comde; // [13:13] Reserved + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *oc1ce; // [7:7] Output Compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + Object *oc2ce; // [15:15] Output Compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1pcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2ne; // [6:6] Capture/Compare 2 complementary output enable + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3ne; // [10:10] Capture/Compare 3 complementary output enable + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare 3 value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare 3 value + } ccr4; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM1State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM1_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim14.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim14.c new file mode 100644 index 0000000000..9b60190237 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim14.c @@ -0,0 +1,297 @@ +/* + * STM32 - TIM14 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_tim14_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM14State *state = STM32_TIM14_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f0.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f0.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f0.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f0.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f0.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f0.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f0.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f0.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.cen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); + state->u.f0.fld.cr1.udis = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); + state->u.f0.fld.cr1.urs = cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); + state->u.f0.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); + state->u.f0.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); + + // DIER bitfields. + state->u.f0.fld.dier.uie = cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); + state->u.f0.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f0.fld.sr.uif = cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); + state->u.f0.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); + state->u.f0.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f0.fld.egr.ug = cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); + state->u.f0.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f0.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); + state->u.f0.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); + state->u.f0.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); + state->u.f0.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f0.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); + state->u.f0.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); + state->u.f0.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f0.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); + state->u.f0.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); + state->u.f0.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f0.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f0.fld.psc.psc = cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f0.fld.arr.arr = cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f0.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); + + // OR bitfields. + state->u.f0.fld.or_.rmp = cm_object_get_child_by_name(state->u.f0.reg.or_, "RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim14_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim14_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim14_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim14_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim14_is_enabled(Object *obj) +{ + STM32TIM14State *state = STM32_TIM14_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim14_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM14State *state = STM32_TIM14_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim14_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM14)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM14State *state = STM32_TIM14_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM14"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_tim14_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim14_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim14_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim14_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim14_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM14EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim14_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM14); +} + +static void stm32_tim14_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim14_reset_callback; + dc->realize = stm32_tim14_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim14_is_enabled; +} + +static const TypeInfo stm32_tim14_type_info = { + .name = TYPE_STM32_TIM14, + .parent = TYPE_STM32_TIM14_PARENT, + .instance_init = stm32_tim14_instance_init_callback, + .instance_size = sizeof(STM32TIM14State), + .class_init = stm32_tim14_class_init_callback, + .class_size = sizeof(STM32TIM14Class) }; + +static void stm32_tim14_register_types(void) +{ + type_register_static(&stm32_tim14_type_info); +} + +type_init(stm32_tim14_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim14.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim14.h new file mode 100644 index 0000000000..2395697adb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim14.h @@ -0,0 +1,186 @@ +/* + * STM32 - TIM14 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM14_H_ +#define STM32_TIM14_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM14 DEVICE_PATH_STM32 "TIM14" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM14 TYPE_STM32_PREFIX "tim14" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM14_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM14ParentClass; +typedef PeripheralState STM32TIM14ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM14_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM14Class, (obj), TYPE_STM32_TIM14) +#define STM32_TIM14_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM14Class, (klass), TYPE_STM32_TIM14) + +typedef struct { + // private: + STM32TIM14ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM14Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM14_STATE(obj) \ + OBJECT_CHECK(STM32TIM14State, (obj), TYPE_STM32_TIM14) + +typedef struct { + // private: + STM32TIM14ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 TIM14 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *or_; // 0x50 (Option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // OR (Option register) bitfields. + struct { + Object *rmp; // [0:1] Timer input 1 remap + } or_; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM14State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM14_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim15.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim15.c new file mode 100644 index 0000000000..bdeedecfb4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim15.c @@ -0,0 +1,366 @@ +/* + * STM32 - TIM15 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_tim15_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM15State *state = STM32_TIM15_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f0.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f0.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f0.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f0.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f0.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f0.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f0.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f0.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f0.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f0.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f0.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + state->u.f0.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f0.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.cen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); + state->u.f0.fld.cr1.udis = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); + state->u.f0.fld.cr1.urs = cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); + state->u.f0.fld.cr1.opm = cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); + state->u.f0.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); + state->u.f0.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f0.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCPC"); + state->u.f0.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCUS"); + state->u.f0.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); + state->u.f0.fld.cr2.mms = cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); + state->u.f0.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1"); + state->u.f0.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1N"); + state->u.f0.fld.cr2.ois2 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS2"); + + // SMCR bitfields. + state->u.f0.fld.smcr.sms = cm_object_get_child_by_name(state->u.f0.reg.smcr, "SMS"); + state->u.f0.fld.smcr.ts = cm_object_get_child_by_name(state->u.f0.reg.smcr, "TS"); + state->u.f0.fld.smcr.msm = cm_object_get_child_by_name(state->u.f0.reg.smcr, "MSM"); + + // DIER bitfields. + state->u.f0.fld.dier.uie = cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); + state->u.f0.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); + state->u.f0.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2IE"); + state->u.f0.fld.dier.comie = cm_object_get_child_by_name(state->u.f0.reg.dier, "COMIE"); + state->u.f0.fld.dier.tie = cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); + state->u.f0.fld.dier.bie = cm_object_get_child_by_name(state->u.f0.reg.dier, "BIE"); + state->u.f0.fld.dier.ude = cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); + state->u.f0.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); + state->u.f0.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2DE"); + state->u.f0.fld.dier.tde = cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); + + // SR bitfields. + state->u.f0.fld.sr.uif = cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); + state->u.f0.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); + state->u.f0.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2IF"); + state->u.f0.fld.sr.comif = cm_object_get_child_by_name(state->u.f0.reg.sr, "COMIF"); + state->u.f0.fld.sr.tif = cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); + state->u.f0.fld.sr.bif = cm_object_get_child_by_name(state->u.f0.reg.sr, "BIF"); + state->u.f0.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); + state->u.f0.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2OF"); + + // EGR bitfields. + state->u.f0.fld.egr.ug = cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); + state->u.f0.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); + state->u.f0.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC2G"); + state->u.f0.fld.egr.comg = cm_object_get_child_by_name(state->u.f0.reg.egr, "COMG"); + state->u.f0.fld.egr.tg = cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); + state->u.f0.fld.egr.bg = cm_object_get_child_by_name(state->u.f0.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f0.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); + state->u.f0.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); + state->u.f0.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); + state->u.f0.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); + state->u.f0.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC2S"); + state->u.f0.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2FE"); + state->u.f0.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2PE"); + state->u.f0.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2M"); + + // CCMR1_Input bitfields. + state->u.f0.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); + state->u.f0.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); + state->u.f0.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); + state->u.f0.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC2S"); + state->u.f0.fld.ccmr1_input.ic2psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2PSC"); + state->u.f0.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2F"); + + // CCER bitfields. + state->u.f0.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); + state->u.f0.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); + state->u.f0.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NE"); + state->u.f0.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); + state->u.f0.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2E"); + state->u.f0.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2P"); + state->u.f0.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NP"); + + // CNT bitfields. + state->u.f0.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f0.fld.psc.psc = cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f0.fld.arr.arr = cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); + + // RCR bitfields. + state->u.f0.fld.rcr.rep = cm_object_get_child_by_name(state->u.f0.reg.rcr, "REP"); + + // CCR1 bitfields. + state->u.f0.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f0.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2"); + + // BDTR bitfields. + state->u.f0.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "DTG"); + state->u.f0.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "LOCK"); + state->u.f0.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSI"); + state->u.f0.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSR"); + state->u.f0.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKE"); + state->u.f0.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKP"); + state->u.f0.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "AOE"); + state->u.f0.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "MOE"); + + // DCR bitfields. + state->u.f0.fld.dcr.dba = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); + state->u.f0.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f0.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim15_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim15_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim15_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim15_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim15_is_enabled(Object *obj) +{ + STM32TIM15State *state = STM32_TIM15_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim15_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM15State *state = STM32_TIM15_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim15_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM15)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM15State *state = STM32_TIM15_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM15"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_tim15_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim15_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim15_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim15_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim15_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM15EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim15_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM15); +} + +static void stm32_tim15_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim15_reset_callback; + dc->realize = stm32_tim15_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim15_is_enabled; +} + +static const TypeInfo stm32_tim15_type_info = { + .name = TYPE_STM32_TIM15, + .parent = TYPE_STM32_TIM15_PARENT, + .instance_init = stm32_tim15_instance_init_callback, + .instance_size = sizeof(STM32TIM15State), + .class_init = stm32_tim15_class_init_callback, + .class_size = sizeof(STM32TIM15Class) }; + +static void stm32_tim15_register_types(void) +{ + type_register_static(&stm32_tim15_type_info); +} + +type_init(stm32_tim15_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim15.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim15.h new file mode 100644 index 0000000000..b46b6b20e1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim15.h @@ -0,0 +1,267 @@ +/* + * STM32 - TIM15 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM15_H_ +#define STM32_TIM15_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM15 DEVICE_PATH_STM32 "TIM15" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM15 TYPE_STM32_PREFIX "tim15" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM15_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM15ParentClass; +typedef PeripheralState STM32TIM15ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM15_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM15Class, (obj), TYPE_STM32_TIM15) +#define STM32_TIM15_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM15Class, (klass), TYPE_STM32_TIM15) + +typedef struct { + // private: + STM32TIM15ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM15Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM15_STATE(obj) \ + OBJECT_CHECK(STM32TIM15State, (obj), TYPE_STM32_TIM15) + +typedef struct { + // private: + STM32TIM15ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 TIM15 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *rcr; // 0x30 (Repetition counter register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *bdtr; // 0x44 (Break and dead-time register) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + Object *ois2; // [10:10] Output Idle state 2 + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2psc; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM15State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM15_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim16.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim16.c new file mode 100644 index 0000000000..9b75d2c439 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim16.c @@ -0,0 +1,339 @@ +/* + * STM32 - TIM16 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_tim16_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM16State *state = STM32_TIM16_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f0.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f0.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f0.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f0.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f0.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f0.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f0.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f0.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f0.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + state->u.f0.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f0.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.cen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); + state->u.f0.fld.cr1.udis = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); + state->u.f0.fld.cr1.urs = cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); + state->u.f0.fld.cr1.opm = cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); + state->u.f0.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); + state->u.f0.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f0.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCPC"); + state->u.f0.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCUS"); + state->u.f0.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); + state->u.f0.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1"); + state->u.f0.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1N"); + + // DIER bitfields. + state->u.f0.fld.dier.uie = cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); + state->u.f0.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); + state->u.f0.fld.dier.comie = cm_object_get_child_by_name(state->u.f0.reg.dier, "COMIE"); + state->u.f0.fld.dier.tie = cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); + state->u.f0.fld.dier.bie = cm_object_get_child_by_name(state->u.f0.reg.dier, "BIE"); + state->u.f0.fld.dier.ude = cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); + state->u.f0.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); + state->u.f0.fld.dier.tde = cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); + + // SR bitfields. + state->u.f0.fld.sr.uif = cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); + state->u.f0.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); + state->u.f0.fld.sr.comif = cm_object_get_child_by_name(state->u.f0.reg.sr, "COMIF"); + state->u.f0.fld.sr.tif = cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); + state->u.f0.fld.sr.bif = cm_object_get_child_by_name(state->u.f0.reg.sr, "BIF"); + state->u.f0.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f0.fld.egr.ug = cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); + state->u.f0.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); + state->u.f0.fld.egr.comg = cm_object_get_child_by_name(state->u.f0.reg.egr, "COMG"); + state->u.f0.fld.egr.tg = cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); + state->u.f0.fld.egr.bg = cm_object_get_child_by_name(state->u.f0.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f0.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); + state->u.f0.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); + state->u.f0.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); + state->u.f0.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f0.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); + state->u.f0.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); + state->u.f0.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f0.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); + state->u.f0.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); + state->u.f0.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NE"); + state->u.f0.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f0.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f0.fld.psc.psc = cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f0.fld.arr.arr = cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); + + // RCR bitfields. + state->u.f0.fld.rcr.rep = cm_object_get_child_by_name(state->u.f0.reg.rcr, "REP"); + + // CCR1 bitfields. + state->u.f0.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); + + // BDTR bitfields. + state->u.f0.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "DTG"); + state->u.f0.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "LOCK"); + state->u.f0.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSI"); + state->u.f0.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSR"); + state->u.f0.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKE"); + state->u.f0.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKP"); + state->u.f0.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "AOE"); + state->u.f0.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f0.reg.bdtr, "MOE"); + + // DCR bitfields. + state->u.f0.fld.dcr.dba = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); + state->u.f0.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f0.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim16_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim16_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim16_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim16_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim16_is_enabled(Object *obj) +{ + STM32TIM16State *state = STM32_TIM16_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim16_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM16State *state = STM32_TIM16_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim16_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM16)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM16State *state = STM32_TIM16_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM16"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_tim16_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim16_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim16_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim16_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim16_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM16EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim16_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM16); +} + +static void stm32_tim16_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim16_reset_callback; + dc->realize = stm32_tim16_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim16_is_enabled; +} + +static const TypeInfo stm32_tim16_type_info = { + .name = TYPE_STM32_TIM16, + .parent = TYPE_STM32_TIM16_PARENT, + .instance_init = stm32_tim16_instance_init_callback, + .instance_size = sizeof(STM32TIM16State), + .class_init = stm32_tim16_class_init_callback, + .class_size = sizeof(STM32TIM16Class) }; + +static void stm32_tim16_register_types(void) +{ + type_register_static(&stm32_tim16_type_info); +} + +type_init(stm32_tim16_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim16.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim16.h new file mode 100644 index 0000000000..d605de6dd8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim16.h @@ -0,0 +1,236 @@ +/* + * STM32 - TIM16 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM16_H_ +#define STM32_TIM16_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM16 DEVICE_PATH_STM32 "TIM16" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM16 TYPE_STM32_PREFIX "tim16" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM16_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM16ParentClass; +typedef PeripheralState STM32TIM16ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM16_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM16Class, (obj), TYPE_STM32_TIM16) +#define STM32_TIM16_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM16Class, (klass), TYPE_STM32_TIM16) + +typedef struct { + // private: + STM32TIM16ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM16Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM16_STATE(obj) \ + OBJECT_CHECK(STM32TIM16State, (obj), TYPE_STM32_TIM16) + +typedef struct { + // private: + STM32TIM16ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 TIM16 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *rcr; // 0x30 (Repetition counter register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *bdtr; // 0x44 (Break and dead-time register) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + } cr2; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM16State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM16_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim2.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim2.c new file mode 100644 index 0000000000..656c3f5368 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim2.c @@ -0,0 +1,401 @@ +/* + * STM32 - TIM2 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_tim2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f0.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f0.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f0.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f0.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f0.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f0.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f0.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f0.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f0.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f0.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f0.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f0.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f0.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f0.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f0.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.cen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); + state->u.f0.fld.cr1.udis = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); + state->u.f0.fld.cr1.urs = cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); + state->u.f0.fld.cr1.opm = cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); + state->u.f0.fld.cr1.dir = cm_object_get_child_by_name(state->u.f0.reg.cr1, "DIR"); + state->u.f0.fld.cr1.cms = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CMS"); + state->u.f0.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); + state->u.f0.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f0.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); + state->u.f0.fld.cr2.mms = cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); + state->u.f0.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f0.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f0.fld.smcr.sms = cm_object_get_child_by_name(state->u.f0.reg.smcr, "SMS"); + state->u.f0.fld.smcr.ts = cm_object_get_child_by_name(state->u.f0.reg.smcr, "TS"); + state->u.f0.fld.smcr.msm = cm_object_get_child_by_name(state->u.f0.reg.smcr, "MSM"); + state->u.f0.fld.smcr.etf = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETF"); + state->u.f0.fld.smcr.etps = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETPS"); + state->u.f0.fld.smcr.ece = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ECE"); + state->u.f0.fld.smcr.etp = cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f0.fld.dier.uie = cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); + state->u.f0.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); + state->u.f0.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2IE"); + state->u.f0.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3IE"); + state->u.f0.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4IE"); + state->u.f0.fld.dier.tie = cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); + state->u.f0.fld.dier.ude = cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); + state->u.f0.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); + state->u.f0.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2DE"); + state->u.f0.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3DE"); + state->u.f0.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4DE"); + state->u.f0.fld.dier.comde = cm_object_get_child_by_name(state->u.f0.reg.dier, "COMDE"); + state->u.f0.fld.dier.tde = cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); + + // SR bitfields. + state->u.f0.fld.sr.uif = cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); + state->u.f0.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); + state->u.f0.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2IF"); + state->u.f0.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3IF"); + state->u.f0.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4IF"); + state->u.f0.fld.sr.tif = cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); + state->u.f0.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); + state->u.f0.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2OF"); + state->u.f0.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3OF"); + state->u.f0.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f0.fld.egr.ug = cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); + state->u.f0.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); + state->u.f0.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC2G"); + state->u.f0.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC3G"); + state->u.f0.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f0.reg.egr, "CC4G"); + state->u.f0.fld.egr.tg = cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f0.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); + state->u.f0.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); + state->u.f0.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); + state->u.f0.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); + state->u.f0.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1CE"); + state->u.f0.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC2S"); + state->u.f0.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2FE"); + state->u.f0.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2PE"); + state->u.f0.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2M"); + state->u.f0.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f0.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); + state->u.f0.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); + state->u.f0.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); + state->u.f0.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC2S"); + state->u.f0.fld.ccmr1_input.ic2psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2PSC"); + state->u.f0.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f0.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC3S"); + state->u.f0.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3FE"); + state->u.f0.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3PE"); + state->u.f0.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3M"); + state->u.f0.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3CE"); + state->u.f0.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC4S"); + state->u.f0.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4FE"); + state->u.f0.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4PE"); + state->u.f0.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4M"); + state->u.f0.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f0.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC3S"); + state->u.f0.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3PSC"); + state->u.f0.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3F"); + state->u.f0.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC4S"); + state->u.f0.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4PSC"); + state->u.f0.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f0.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); + state->u.f0.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); + state->u.f0.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); + state->u.f0.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2E"); + state->u.f0.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2P"); + state->u.f0.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NP"); + state->u.f0.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3E"); + state->u.f0.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3P"); + state->u.f0.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3NP"); + state->u.f0.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4E"); + state->u.f0.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4P"); + state->u.f0.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f0.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT_L"); + state->u.f0.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f0.fld.psc.psc = cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f0.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR_L"); + state->u.f0.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f0.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1_L"); + state->u.f0.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f0.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2_L"); + state->u.f0.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f0.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CCR3_L"); + state->u.f0.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f0.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CCR4_L"); + state->u.f0.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f0.fld.dcr.dba = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); + state->u.f0.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f0.fld.dmar.dmar = cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim2_is_enabled(Object *obj) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM2State *state = STM32_TIM2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_tim2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim2_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM2EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM2); +} + +static void stm32_tim2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim2_reset_callback; + dc->realize = stm32_tim2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim2_is_enabled; +} + +static const TypeInfo stm32_tim2_type_info = { + .name = TYPE_STM32_TIM2, + .parent = TYPE_STM32_TIM2_PARENT, + .instance_init = stm32_tim2_instance_init_callback, + .instance_size = sizeof(STM32TIM2State), + .class_init = stm32_tim2_class_init_callback, + .class_size = sizeof(STM32TIM2Class) }; + +static void stm32_tim2_register_types(void) +{ + type_register_static(&stm32_tim2_type_info); +} + +type_init(stm32_tim2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim2.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim2.h new file mode 100644 index 0000000000..65739cac37 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim2.h @@ -0,0 +1,306 @@ +/* + * STM32 - TIM2 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM2_H_ +#define STM32_TIM2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM2 DEVICE_PATH_STM32 "TIM2" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM2 TYPE_STM32_PREFIX "tim2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM2ParentClass; +typedef PeripheralState STM32TIM2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM2Class, (obj), TYPE_STM32_TIM2) +#define STM32_TIM2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM2Class, (klass), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM2_STATE(obj) \ + OBJECT_CHECK(STM32TIM2State, (obj), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 TIM2 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *comde; // [13:13] Reserved + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output compare 1 fast enable + Object *oc1pe; // [3:3] Output compare 1 preload enable + Object *oc1m; // [4:6] Output compare 1 mode + Object *oc1ce; // [7:7] Output compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output compare 2 fast enable + Object *oc2pe; // [11:11] Output compare 2 preload enable + Object *oc2m; // [12:14] Output compare 2 mode + Object *oc2ce; // [15:15] Output compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/compare 2 selection + Object *ic2psc; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value (TIM2 only) + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value (TIM2 only) + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value (TIM2 only) + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value (TIM2 only) + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value (TIM2 only) + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value (TIM2 only) + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmar; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim6.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim6.c new file mode 100644 index 0000000000..9d92c11c4c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim6.c @@ -0,0 +1,271 @@ +/* + * STM32 - TIM6 (Basic-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_tim6_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f0.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f0.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f0.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f0.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.cen = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); + state->u.f0.fld.cr1.udis = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); + state->u.f0.fld.cr1.urs = cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); + state->u.f0.fld.cr1.opm = cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); + state->u.f0.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); + + // CR2 bitfields. + state->u.f0.fld.cr2.mms = cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); + + // DIER bitfields. + state->u.f0.fld.dier.uie = cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); + state->u.f0.fld.dier.ude = cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); + + // SR bitfields. + state->u.f0.fld.sr.uif = cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); + + // EGR bitfields. + state->u.f0.fld.egr.ug = cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); + + // CNT bitfields. + state->u.f0.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f0.fld.psc.psc = cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f0.fld.arr.arr = cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim6_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim6_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim6_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim6_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim6_is_enabled(Object *obj) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim6_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim6_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM6)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM6State *state = STM32_TIM6_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM6"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_tim6_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim6_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim6_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim6_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim6_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM6EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim6_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM6); +} + +static void stm32_tim6_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim6_reset_callback; + dc->realize = stm32_tim6_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim6_is_enabled; +} + +static const TypeInfo stm32_tim6_type_info = { + .name = TYPE_STM32_TIM6, + .parent = TYPE_STM32_TIM6_PARENT, + .instance_init = stm32_tim6_instance_init_callback, + .instance_size = sizeof(STM32TIM6State), + .class_init = stm32_tim6_class_init_callback, + .class_size = sizeof(STM32TIM6Class) }; + +static void stm32_tim6_register_types(void) +{ + type_register_static(&stm32_tim6_type_info); +} + +type_init(stm32_tim6_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tim6.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim6.h new file mode 100644 index 0000000000..f241d24b5e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tim6.h @@ -0,0 +1,152 @@ +/* + * STM32 - TIM6 (Basic-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM6_H_ +#define STM32_TIM6_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM6 DEVICE_PATH_STM32 "TIM6" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM6 TYPE_STM32_PREFIX "tim6" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM6_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM6ParentClass; +typedef PeripheralState STM32TIM6ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM6_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM6Class, (obj), TYPE_STM32_TIM6) +#define STM32_TIM6_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM6Class, (klass), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM6Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM6_STATE(obj) \ + OBJECT_CHECK(STM32TIM6State, (obj), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 TIM6 (Basic-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *ude; // [8:8] Update DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + } egr; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Low counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Low Auto-reload value + } arr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM6State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM6_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tsc.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/tsc.c new file mode 100644 index 0000000000..a4faa50259 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tsc.c @@ -0,0 +1,415 @@ +/* + * STM32 - TSC (Touch sensing controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_tsc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TSCState *state = STM32_TSC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.ier = cm_object_get_child_by_name(obj, "IER"); + state->u.f0.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.iohcr = cm_object_get_child_by_name(obj, "IOHCR"); + state->u.f0.reg.ioascr = cm_object_get_child_by_name(obj, "IOASCR"); + state->u.f0.reg.ioscr = cm_object_get_child_by_name(obj, "IOSCR"); + state->u.f0.reg.ioccr = cm_object_get_child_by_name(obj, "IOCCR"); + state->u.f0.reg.iogcsr = cm_object_get_child_by_name(obj, "IOGCSR"); + state->u.f0.reg.iog1cr = cm_object_get_child_by_name(obj, "IOG1CR"); + state->u.f0.reg.iog2cr = cm_object_get_child_by_name(obj, "IOG2CR"); + state->u.f0.reg.iog3cr = cm_object_get_child_by_name(obj, "IOG3CR"); + state->u.f0.reg.iog4cr = cm_object_get_child_by_name(obj, "IOG4CR"); + state->u.f0.reg.iog5cr = cm_object_get_child_by_name(obj, "IOG5CR"); + state->u.f0.reg.iog6cr = cm_object_get_child_by_name(obj, "IOG6CR"); + + + // CR bitfields. + state->u.f0.fld.cr.tsce = cm_object_get_child_by_name(state->u.f0.reg.cr, "TSCE"); + state->u.f0.fld.cr.start = cm_object_get_child_by_name(state->u.f0.reg.cr, "START"); + state->u.f0.fld.cr.am = cm_object_get_child_by_name(state->u.f0.reg.cr, "AM"); + state->u.f0.fld.cr.syncpol = cm_object_get_child_by_name(state->u.f0.reg.cr, "SYNCPOL"); + state->u.f0.fld.cr.iodef = cm_object_get_child_by_name(state->u.f0.reg.cr, "IODEF"); + state->u.f0.fld.cr.mcv = cm_object_get_child_by_name(state->u.f0.reg.cr, "MCV"); + state->u.f0.fld.cr.pgpsc = cm_object_get_child_by_name(state->u.f0.reg.cr, "PGPSC"); + state->u.f0.fld.cr.sspsc = cm_object_get_child_by_name(state->u.f0.reg.cr, "SSPSC"); + state->u.f0.fld.cr.sse = cm_object_get_child_by_name(state->u.f0.reg.cr, "SSE"); + state->u.f0.fld.cr.ssd = cm_object_get_child_by_name(state->u.f0.reg.cr, "SSD"); + state->u.f0.fld.cr.ctpl = cm_object_get_child_by_name(state->u.f0.reg.cr, "CTPL"); + state->u.f0.fld.cr.ctph = cm_object_get_child_by_name(state->u.f0.reg.cr, "CTPH"); + + // IER bitfields. + state->u.f0.fld.ier.eoaie = cm_object_get_child_by_name(state->u.f0.reg.ier, "EOAIE"); + state->u.f0.fld.ier.mceie = cm_object_get_child_by_name(state->u.f0.reg.ier, "MCEIE"); + + // ICR bitfields. + state->u.f0.fld.icr.eoaic = cm_object_get_child_by_name(state->u.f0.reg.icr, "EOAIC"); + state->u.f0.fld.icr.mceic = cm_object_get_child_by_name(state->u.f0.reg.icr, "MCEIC"); + + // ISR bitfields. + state->u.f0.fld.isr.eoaf = cm_object_get_child_by_name(state->u.f0.reg.isr, "EOAF"); + state->u.f0.fld.isr.mcef = cm_object_get_child_by_name(state->u.f0.reg.isr, "MCEF"); + + // IOHCR bitfields. + state->u.f0.fld.iohcr.g1_io1 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO1"); + state->u.f0.fld.iohcr.g1_io2 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO2"); + state->u.f0.fld.iohcr.g1_io3 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO3"); + state->u.f0.fld.iohcr.g1_io4 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO4"); + state->u.f0.fld.iohcr.g2_io1 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO1"); + state->u.f0.fld.iohcr.g2_io2 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO2"); + state->u.f0.fld.iohcr.g2_io3 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO3"); + state->u.f0.fld.iohcr.g2_io4 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO4"); + state->u.f0.fld.iohcr.g3_io1 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO1"); + state->u.f0.fld.iohcr.g3_io2 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO2"); + state->u.f0.fld.iohcr.g3_io3 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO3"); + state->u.f0.fld.iohcr.g3_io4 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO4"); + state->u.f0.fld.iohcr.g4_io1 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO1"); + state->u.f0.fld.iohcr.g4_io2 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO2"); + state->u.f0.fld.iohcr.g4_io3 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO3"); + state->u.f0.fld.iohcr.g4_io4 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO4"); + state->u.f0.fld.iohcr.g5_io1 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO1"); + state->u.f0.fld.iohcr.g5_io2 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO2"); + state->u.f0.fld.iohcr.g5_io3 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO3"); + state->u.f0.fld.iohcr.g5_io4 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO4"); + state->u.f0.fld.iohcr.g6_io1 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO1"); + state->u.f0.fld.iohcr.g6_io2 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO2"); + state->u.f0.fld.iohcr.g6_io3 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO3"); + state->u.f0.fld.iohcr.g6_io4 = cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO4"); + + // IOASCR bitfields. + state->u.f0.fld.ioascr.g1_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO1"); + state->u.f0.fld.ioascr.g1_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO2"); + state->u.f0.fld.ioascr.g1_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO3"); + state->u.f0.fld.ioascr.g1_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO4"); + state->u.f0.fld.ioascr.g2_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO1"); + state->u.f0.fld.ioascr.g2_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO2"); + state->u.f0.fld.ioascr.g2_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO3"); + state->u.f0.fld.ioascr.g2_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO4"); + state->u.f0.fld.ioascr.g3_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO1"); + state->u.f0.fld.ioascr.g3_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO2"); + state->u.f0.fld.ioascr.g3_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO3"); + state->u.f0.fld.ioascr.g3_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO4"); + state->u.f0.fld.ioascr.g4_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO1"); + state->u.f0.fld.ioascr.g4_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO2"); + state->u.f0.fld.ioascr.g4_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO3"); + state->u.f0.fld.ioascr.g4_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO4"); + state->u.f0.fld.ioascr.g5_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO1"); + state->u.f0.fld.ioascr.g5_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO2"); + state->u.f0.fld.ioascr.g5_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO3"); + state->u.f0.fld.ioascr.g5_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO4"); + state->u.f0.fld.ioascr.g6_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO1"); + state->u.f0.fld.ioascr.g6_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO2"); + state->u.f0.fld.ioascr.g6_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO3"); + state->u.f0.fld.ioascr.g6_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO4"); + + // IOSCR bitfields. + state->u.f0.fld.ioscr.g1_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO1"); + state->u.f0.fld.ioscr.g1_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO2"); + state->u.f0.fld.ioscr.g1_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO3"); + state->u.f0.fld.ioscr.g1_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO4"); + state->u.f0.fld.ioscr.g2_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO1"); + state->u.f0.fld.ioscr.g2_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO2"); + state->u.f0.fld.ioscr.g2_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO3"); + state->u.f0.fld.ioscr.g2_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO4"); + state->u.f0.fld.ioscr.g3_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO1"); + state->u.f0.fld.ioscr.g3_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO2"); + state->u.f0.fld.ioscr.g3_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO3"); + state->u.f0.fld.ioscr.g3_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO4"); + state->u.f0.fld.ioscr.g4_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO1"); + state->u.f0.fld.ioscr.g4_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO2"); + state->u.f0.fld.ioscr.g4_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO3"); + state->u.f0.fld.ioscr.g4_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO4"); + state->u.f0.fld.ioscr.g5_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO1"); + state->u.f0.fld.ioscr.g5_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO2"); + state->u.f0.fld.ioscr.g5_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO3"); + state->u.f0.fld.ioscr.g5_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO4"); + state->u.f0.fld.ioscr.g6_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO1"); + state->u.f0.fld.ioscr.g6_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO2"); + state->u.f0.fld.ioscr.g6_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO3"); + state->u.f0.fld.ioscr.g6_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO4"); + + // IOCCR bitfields. + state->u.f0.fld.ioccr.g1_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO1"); + state->u.f0.fld.ioccr.g1_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO2"); + state->u.f0.fld.ioccr.g1_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO3"); + state->u.f0.fld.ioccr.g1_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO4"); + state->u.f0.fld.ioccr.g2_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO1"); + state->u.f0.fld.ioccr.g2_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO2"); + state->u.f0.fld.ioccr.g2_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO3"); + state->u.f0.fld.ioccr.g2_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO4"); + state->u.f0.fld.ioccr.g3_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO1"); + state->u.f0.fld.ioccr.g3_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO2"); + state->u.f0.fld.ioccr.g3_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO3"); + state->u.f0.fld.ioccr.g3_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO4"); + state->u.f0.fld.ioccr.g4_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO1"); + state->u.f0.fld.ioccr.g4_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO2"); + state->u.f0.fld.ioccr.g4_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO3"); + state->u.f0.fld.ioccr.g4_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO4"); + state->u.f0.fld.ioccr.g5_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO1"); + state->u.f0.fld.ioccr.g5_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO2"); + state->u.f0.fld.ioccr.g5_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO3"); + state->u.f0.fld.ioccr.g5_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO4"); + state->u.f0.fld.ioccr.g6_io1 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO1"); + state->u.f0.fld.ioccr.g6_io2 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO2"); + state->u.f0.fld.ioccr.g6_io3 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO3"); + state->u.f0.fld.ioccr.g6_io4 = cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO4"); + + // IOGCSR bitfields. + state->u.f0.fld.iogcsr.g1e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G1E"); + state->u.f0.fld.iogcsr.g2e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G2E"); + state->u.f0.fld.iogcsr.g3e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G3E"); + state->u.f0.fld.iogcsr.g4e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G4E"); + state->u.f0.fld.iogcsr.g5e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G5E"); + state->u.f0.fld.iogcsr.g6e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G6E"); + state->u.f0.fld.iogcsr.g7e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G7E"); + state->u.f0.fld.iogcsr.g8e = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G8E"); + state->u.f0.fld.iogcsr.g1s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G1S"); + state->u.f0.fld.iogcsr.g2s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G2S"); + state->u.f0.fld.iogcsr.g3s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G3S"); + state->u.f0.fld.iogcsr.g4s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G4S"); + state->u.f0.fld.iogcsr.g5s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G5S"); + state->u.f0.fld.iogcsr.g6s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G6S"); + state->u.f0.fld.iogcsr.g7s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G7S"); + state->u.f0.fld.iogcsr.g8s = cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G8S"); + + // IOG1CR bitfields. + state->u.f0.fld.iog1cr.cnt = cm_object_get_child_by_name(state->u.f0.reg.iog1cr, "CNT"); + + // IOG2CR bitfields. + state->u.f0.fld.iog2cr.cnt = cm_object_get_child_by_name(state->u.f0.reg.iog2cr, "CNT"); + + // IOG3CR bitfields. + state->u.f0.fld.iog3cr.cnt = cm_object_get_child_by_name(state->u.f0.reg.iog3cr, "CNT"); + + // IOG4CR bitfields. + state->u.f0.fld.iog4cr.cnt = cm_object_get_child_by_name(state->u.f0.reg.iog4cr, "CNT"); + + // IOG5CR bitfields. + state->u.f0.fld.iog5cr.cnt = cm_object_get_child_by_name(state->u.f0.reg.iog5cr, "CNT"); + + // IOG6CR bitfields. + state->u.f0.fld.iog6cr.cnt = cm_object_get_child_by_name(state->u.f0.reg.iog6cr, "CNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tsc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tsc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tsc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tsc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tsc_is_enabled(Object *obj) +{ + STM32TSCState *state = STM32_TSC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tsc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TSCState *state = STM32_TSC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tsc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TSC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TSCState *state = STM32_TSC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TSC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_tsc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tsc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tsc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tsc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tsc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TSCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tsc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TSC); +} + +static void stm32_tsc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tsc_reset_callback; + dc->realize = stm32_tsc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tsc_is_enabled; +} + +static const TypeInfo stm32_tsc_type_info = { + .name = TYPE_STM32_TSC, + .parent = TYPE_STM32_TSC_PARENT, + .instance_init = stm32_tsc_instance_init_callback, + .instance_size = sizeof(STM32TSCState), + .class_init = stm32_tsc_class_init_callback, + .class_size = sizeof(STM32TSCClass) }; + +static void stm32_tsc_register_types(void) +{ + type_register_static(&stm32_tsc_type_info); +} + +type_init(stm32_tsc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/tsc.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/tsc.h new file mode 100644 index 0000000000..03f1af76d8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/tsc.h @@ -0,0 +1,310 @@ +/* + * STM32 - TSC (Touch sensing controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TSC_H_ +#define STM32_TSC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TSC DEVICE_PATH_STM32 "TSC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TSC TYPE_STM32_PREFIX "tsc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TSC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TSCParentClass; +typedef PeripheralState STM32TSCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TSC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TSCClass, (obj), TYPE_STM32_TSC) +#define STM32_TSC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TSCClass, (klass), TYPE_STM32_TSC) + +typedef struct { + // private: + STM32TSCParentClass parent_class; + // public: + + // None, so far. +} STM32TSCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TSC_STATE(obj) \ + OBJECT_CHECK(STM32TSCState, (obj), TYPE_STM32_TSC) + +typedef struct { + // private: + STM32TSCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 TSC (Touch sensing controller) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *ier; // 0x4 (Interrupt enable register) + Object *icr; // 0x8 (Interrupt clear register) + Object *isr; // 0xC (Interrupt status register) + Object *iohcr; // 0x10 (I/O hysteresis control register) + Object *ioascr; // 0x18 (I/O analog switch control register) + Object *ioscr; // 0x20 (I/O sampling control register) + Object *ioccr; // 0x28 (I/O channel control register) + Object *iogcsr; // 0x30 (I/O group control status register) + Object *iog1cr; // 0x34 (I/O group x counter register) + Object *iog2cr; // 0x38 (I/O group x counter register) + Object *iog3cr; // 0x3C (I/O group x counter register) + Object *iog4cr; // 0x40 (I/O group x counter register) + Object *iog5cr; // 0x44 (I/O group x counter register) + Object *iog6cr; // 0x48 (I/O group x counter register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *tsce; // [0:0] Touch sensing controller enable + Object *start; // [1:1] Start a new acquisition + Object *am; // [2:2] Acquisition mode + Object *syncpol; // [3:3] Synchronization pin polarity + Object *iodef; // [4:4] I/O Default mode + Object *mcv; // [5:7] Max count value + Object *pgpsc; // [12:14] Pulse generator prescaler + Object *sspsc; // [15:15] Spread spectrum prescaler + Object *sse; // [16:16] Spread spectrum enable + Object *ssd; // [17:23] Spread spectrum deviation + Object *ctpl; // [24:27] Charge transfer pulse low + Object *ctph; // [28:31] Charge transfer pulse high + } cr; + + // IER (Interrupt enable register) bitfields. + struct { + Object *eoaie; // [0:0] End of acquisition interrupt enable + Object *mceie; // [1:1] Max count error interrupt enable + } ier; + + // ICR (Interrupt clear register) bitfields. + struct { + Object *eoaic; // [0:0] End of acquisition interrupt clear + Object *mceic; // [1:1] Max count error interrupt clear + } icr; + + // ISR (Interrupt status register) bitfields. + struct { + Object *eoaf; // [0:0] End of acquisition flag + Object *mcef; // [1:1] Max count error flag + } isr; + + // IOHCR (I/O hysteresis control register) bitfields. + struct { + Object *g1_io1; // [0:0] G1_IO1 Schmitt trigger hysteresis mode + Object *g1_io2; // [1:1] G1_IO2 Schmitt trigger hysteresis mode + Object *g1_io3; // [2:2] G1_IO3 Schmitt trigger hysteresis mode + Object *g1_io4; // [3:3] G1_IO4 Schmitt trigger hysteresis mode + Object *g2_io1; // [4:4] G2_IO1 Schmitt trigger hysteresis mode + Object *g2_io2; // [5:5] G2_IO2 Schmitt trigger hysteresis mode + Object *g2_io3; // [6:6] G2_IO3 Schmitt trigger hysteresis mode + Object *g2_io4; // [7:7] G2_IO4 Schmitt trigger hysteresis mode + Object *g3_io1; // [8:8] G3_IO1 Schmitt trigger hysteresis mode + Object *g3_io2; // [9:9] G3_IO2 Schmitt trigger hysteresis mode + Object *g3_io3; // [10:10] G3_IO3 Schmitt trigger hysteresis mode + Object *g3_io4; // [11:11] G3_IO4 Schmitt trigger hysteresis mode + Object *g4_io1; // [12:12] G4_IO1 Schmitt trigger hysteresis mode + Object *g4_io2; // [13:13] G4_IO2 Schmitt trigger hysteresis mode + Object *g4_io3; // [14:14] G4_IO3 Schmitt trigger hysteresis mode + Object *g4_io4; // [15:15] G4_IO4 Schmitt trigger hysteresis mode + Object *g5_io1; // [16:16] G5_IO1 Schmitt trigger hysteresis mode + Object *g5_io2; // [17:17] G5_IO2 Schmitt trigger hysteresis mode + Object *g5_io3; // [18:18] G5_IO3 Schmitt trigger hysteresis mode + Object *g5_io4; // [19:19] G5_IO4 Schmitt trigger hysteresis mode + Object *g6_io1; // [20:20] G6_IO1 Schmitt trigger hysteresis mode + Object *g6_io2; // [21:21] G6_IO2 Schmitt trigger hysteresis mode + Object *g6_io3; // [22:22] G6_IO3 Schmitt trigger hysteresis mode + Object *g6_io4; // [23:23] G6_IO4 Schmitt trigger hysteresis mode + } iohcr; + + // IOASCR (I/O analog switch control register) bitfields. + struct { + Object *g1_io1; // [0:0] G1_IO1 analog switch enable + Object *g1_io2; // [1:1] G1_IO2 analog switch enable + Object *g1_io3; // [2:2] G1_IO3 analog switch enable + Object *g1_io4; // [3:3] G1_IO4 analog switch enable + Object *g2_io1; // [4:4] G2_IO1 analog switch enable + Object *g2_io2; // [5:5] G2_IO2 analog switch enable + Object *g2_io3; // [6:6] G2_IO3 analog switch enable + Object *g2_io4; // [7:7] G2_IO4 analog switch enable + Object *g3_io1; // [8:8] G3_IO1 analog switch enable + Object *g3_io2; // [9:9] G3_IO2 analog switch enable + Object *g3_io3; // [10:10] G3_IO3 analog switch enable + Object *g3_io4; // [11:11] G3_IO4 analog switch enable + Object *g4_io1; // [12:12] G4_IO1 analog switch enable + Object *g4_io2; // [13:13] G4_IO2 analog switch enable + Object *g4_io3; // [14:14] G4_IO3 analog switch enable + Object *g4_io4; // [15:15] G4_IO4 analog switch enable + Object *g5_io1; // [16:16] G5_IO1 analog switch enable + Object *g5_io2; // [17:17] G5_IO2 analog switch enable + Object *g5_io3; // [18:18] G5_IO3 analog switch enable + Object *g5_io4; // [19:19] G5_IO4 analog switch enable + Object *g6_io1; // [20:20] G6_IO1 analog switch enable + Object *g6_io2; // [21:21] G6_IO2 analog switch enable + Object *g6_io3; // [22:22] G6_IO3 analog switch enable + Object *g6_io4; // [23:23] G6_IO4 analog switch enable + } ioascr; + + // IOSCR (I/O sampling control register) bitfields. + struct { + Object *g1_io1; // [0:0] G1_IO1 sampling mode + Object *g1_io2; // [1:1] G1_IO2 sampling mode + Object *g1_io3; // [2:2] G1_IO3 sampling mode + Object *g1_io4; // [3:3] G1_IO4 sampling mode + Object *g2_io1; // [4:4] G2_IO1 sampling mode + Object *g2_io2; // [5:5] G2_IO2 sampling mode + Object *g2_io3; // [6:6] G2_IO3 sampling mode + Object *g2_io4; // [7:7] G2_IO4 sampling mode + Object *g3_io1; // [8:8] G3_IO1 sampling mode + Object *g3_io2; // [9:9] G3_IO2 sampling mode + Object *g3_io3; // [10:10] G3_IO3 sampling mode + Object *g3_io4; // [11:11] G3_IO4 sampling mode + Object *g4_io1; // [12:12] G4_IO1 sampling mode + Object *g4_io2; // [13:13] G4_IO2 sampling mode + Object *g4_io3; // [14:14] G4_IO3 sampling mode + Object *g4_io4; // [15:15] G4_IO4 sampling mode + Object *g5_io1; // [16:16] G5_IO1 sampling mode + Object *g5_io2; // [17:17] G5_IO2 sampling mode + Object *g5_io3; // [18:18] G5_IO3 sampling mode + Object *g5_io4; // [19:19] G5_IO4 sampling mode + Object *g6_io1; // [20:20] G6_IO1 sampling mode + Object *g6_io2; // [21:21] G6_IO2 sampling mode + Object *g6_io3; // [22:22] G6_IO3 sampling mode + Object *g6_io4; // [23:23] G6_IO4 sampling mode + } ioscr; + + // IOCCR (I/O channel control register) bitfields. + struct { + Object *g1_io1; // [0:0] G1_IO1 channel mode + Object *g1_io2; // [1:1] G1_IO2 channel mode + Object *g1_io3; // [2:2] G1_IO3 channel mode + Object *g1_io4; // [3:3] G1_IO4 channel mode + Object *g2_io1; // [4:4] G2_IO1 channel mode + Object *g2_io2; // [5:5] G2_IO2 channel mode + Object *g2_io3; // [6:6] G2_IO3 channel mode + Object *g2_io4; // [7:7] G2_IO4 channel mode + Object *g3_io1; // [8:8] G3_IO1 channel mode + Object *g3_io2; // [9:9] G3_IO2 channel mode + Object *g3_io3; // [10:10] G3_IO3 channel mode + Object *g3_io4; // [11:11] G3_IO4 channel mode + Object *g4_io1; // [12:12] G4_IO1 channel mode + Object *g4_io2; // [13:13] G4_IO2 channel mode + Object *g4_io3; // [14:14] G4_IO3 channel mode + Object *g4_io4; // [15:15] G4_IO4 channel mode + Object *g5_io1; // [16:16] G5_IO1 channel mode + Object *g5_io2; // [17:17] G5_IO2 channel mode + Object *g5_io3; // [18:18] G5_IO3 channel mode + Object *g5_io4; // [19:19] G5_IO4 channel mode + Object *g6_io1; // [20:20] G6_IO1 channel mode + Object *g6_io2; // [21:21] G6_IO2 channel mode + Object *g6_io3; // [22:22] G6_IO3 channel mode + Object *g6_io4; // [23:23] G6_IO4 channel mode + } ioccr; + + // IOGCSR (I/O group control status register) bitfields. + struct { + Object *g1e; // [0:0] Analog I/O group x enable + Object *g2e; // [1:1] Analog I/O group x enable + Object *g3e; // [2:2] Analog I/O group x enable + Object *g4e; // [3:3] Analog I/O group x enable + Object *g5e; // [4:4] Analog I/O group x enable + Object *g6e; // [5:5] Analog I/O group x enable + Object *g7e; // [6:6] Analog I/O group x enable + Object *g8e; // [7:7] Analog I/O group x enable + Object *g1s; // [16:16] Analog I/O group x status + Object *g2s; // [17:17] Analog I/O group x status + Object *g3s; // [18:18] Analog I/O group x status + Object *g4s; // [19:19] Analog I/O group x status + Object *g5s; // [20:20] Analog I/O group x status + Object *g6s; // [21:21] Analog I/O group x status + Object *g7s; // [22:22] Analog I/O group x status + Object *g8s; // [23:23] Analog I/O group x status + } iogcsr; + + // IOG1CR (I/O group x counter register) bitfields. + struct { + Object *cnt; // [0:13] Counter value + } iog1cr; + + // IOG2CR (I/O group x counter register) bitfields. + struct { + Object *cnt; // [0:13] Counter value + } iog2cr; + + // IOG3CR (I/O group x counter register) bitfields. + struct { + Object *cnt; // [0:13] Counter value + } iog3cr; + + // IOG4CR (I/O group x counter register) bitfields. + struct { + Object *cnt; // [0:13] Counter value + } iog4cr; + + // IOG5CR (I/O group x counter register) bitfields. + struct { + Object *cnt; // [0:13] Counter value + } iog5cr; + + // IOG6CR (I/O group x counter register) bitfields. + struct { + Object *cnt; // [0:13] Counter value + } iog6cr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TSCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TSC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/usart1.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/usart1.c new file mode 100644 index 0000000000..916dec733f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/usart1.c @@ -0,0 +1,378 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_usart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f0.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f0.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + state->u.f0.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f0.reg.gtpr = cm_object_get_child_by_name(obj, "GTPR"); + state->u.f0.reg.rtor = cm_object_get_child_by_name(obj, "RTOR"); + state->u.f0.reg.rqr = cm_object_get_child_by_name(obj, "RQR"); + state->u.f0.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f0.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f0.reg.rdr = cm_object_get_child_by_name(obj, "RDR"); + state->u.f0.reg.tdr = cm_object_get_child_by_name(obj, "TDR"); + + + // CR1 bitfields. + state->u.f0.fld.cr1.ue = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UE"); + state->u.f0.fld.cr1.uesm = cm_object_get_child_by_name(state->u.f0.reg.cr1, "UESM"); + state->u.f0.fld.cr1.re = cm_object_get_child_by_name(state->u.f0.reg.cr1, "RE"); + state->u.f0.fld.cr1.te = cm_object_get_child_by_name(state->u.f0.reg.cr1, "TE"); + state->u.f0.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "IDLEIE"); + state->u.f0.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXNEIE"); + state->u.f0.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "TCIE"); + state->u.f0.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "TXEIE"); + state->u.f0.fld.cr1.peie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "PEIE"); + state->u.f0.fld.cr1.ps = cm_object_get_child_by_name(state->u.f0.reg.cr1, "PS"); + state->u.f0.fld.cr1.pce = cm_object_get_child_by_name(state->u.f0.reg.cr1, "PCE"); + state->u.f0.fld.cr1.wake = cm_object_get_child_by_name(state->u.f0.reg.cr1, "WAKE"); + state->u.f0.fld.cr1.m = cm_object_get_child_by_name(state->u.f0.reg.cr1, "M"); + state->u.f0.fld.cr1.mme = cm_object_get_child_by_name(state->u.f0.reg.cr1, "MME"); + state->u.f0.fld.cr1.cmie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "CMIE"); + state->u.f0.fld.cr1.over8 = cm_object_get_child_by_name(state->u.f0.reg.cr1, "OVER8"); + state->u.f0.fld.cr1.dedt = cm_object_get_child_by_name(state->u.f0.reg.cr1, "DEDT"); + state->u.f0.fld.cr1.deat = cm_object_get_child_by_name(state->u.f0.reg.cr1, "DEAT"); + state->u.f0.fld.cr1.rtoie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "RTOIE"); + state->u.f0.fld.cr1.eobie = cm_object_get_child_by_name(state->u.f0.reg.cr1, "EOBIE"); + state->u.f0.fld.cr1.m1 = cm_object_get_child_by_name(state->u.f0.reg.cr1, "M1"); + + // CR2 bitfields. + state->u.f0.fld.cr2.addm7 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADDM7"); + state->u.f0.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f0.reg.cr2, "LBDL"); + state->u.f0.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f0.reg.cr2, "LBDIE"); + state->u.f0.fld.cr2.lbcl = cm_object_get_child_by_name(state->u.f0.reg.cr2, "LBCL"); + state->u.f0.fld.cr2.cpha = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CPHA"); + state->u.f0.fld.cr2.cpol = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CPOL"); + state->u.f0.fld.cr2.clken = cm_object_get_child_by_name(state->u.f0.reg.cr2, "CLKEN"); + state->u.f0.fld.cr2.stop = cm_object_get_child_by_name(state->u.f0.reg.cr2, "STOP"); + state->u.f0.fld.cr2.linen = cm_object_get_child_by_name(state->u.f0.reg.cr2, "LINEN"); + state->u.f0.fld.cr2.swap = cm_object_get_child_by_name(state->u.f0.reg.cr2, "SWAP"); + state->u.f0.fld.cr2.rxinv = cm_object_get_child_by_name(state->u.f0.reg.cr2, "RXINV"); + state->u.f0.fld.cr2.txinv = cm_object_get_child_by_name(state->u.f0.reg.cr2, "TXINV"); + state->u.f0.fld.cr2.datainv = cm_object_get_child_by_name(state->u.f0.reg.cr2, "DATAINV"); + state->u.f0.fld.cr2.msbfirst = cm_object_get_child_by_name(state->u.f0.reg.cr2, "MSBFIRST"); + state->u.f0.fld.cr2.abren = cm_object_get_child_by_name(state->u.f0.reg.cr2, "ABREN"); + state->u.f0.fld.cr2.abrmod = cm_object_get_child_by_name(state->u.f0.reg.cr2, "ABRMOD"); + state->u.f0.fld.cr2.rtoen = cm_object_get_child_by_name(state->u.f0.reg.cr2, "RTOEN"); + state->u.f0.fld.cr2.add0 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADD0"); + state->u.f0.fld.cr2.add4 = cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADD4"); + + // CR3 bitfields. + state->u.f0.fld.cr3.eie = cm_object_get_child_by_name(state->u.f0.reg.cr3, "EIE"); + state->u.f0.fld.cr3.iren = cm_object_get_child_by_name(state->u.f0.reg.cr3, "IREN"); + state->u.f0.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f0.reg.cr3, "IRLP"); + state->u.f0.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f0.reg.cr3, "HDSEL"); + state->u.f0.fld.cr3.nack = cm_object_get_child_by_name(state->u.f0.reg.cr3, "NACK"); + state->u.f0.fld.cr3.scen = cm_object_get_child_by_name(state->u.f0.reg.cr3, "SCEN"); + state->u.f0.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f0.reg.cr3, "DMAR"); + state->u.f0.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f0.reg.cr3, "DMAT"); + state->u.f0.fld.cr3.rtse = cm_object_get_child_by_name(state->u.f0.reg.cr3, "RTSE"); + state->u.f0.fld.cr3.ctse = cm_object_get_child_by_name(state->u.f0.reg.cr3, "CTSE"); + state->u.f0.fld.cr3.ctsie = cm_object_get_child_by_name(state->u.f0.reg.cr3, "CTSIE"); + state->u.f0.fld.cr3.onebit = cm_object_get_child_by_name(state->u.f0.reg.cr3, "ONEBIT"); + state->u.f0.fld.cr3.ovrdis = cm_object_get_child_by_name(state->u.f0.reg.cr3, "OVRDIS"); + state->u.f0.fld.cr3.ddre = cm_object_get_child_by_name(state->u.f0.reg.cr3, "DDRE"); + state->u.f0.fld.cr3.dem = cm_object_get_child_by_name(state->u.f0.reg.cr3, "DEM"); + state->u.f0.fld.cr3.dep = cm_object_get_child_by_name(state->u.f0.reg.cr3, "DEP"); + state->u.f0.fld.cr3.scarcnt = cm_object_get_child_by_name(state->u.f0.reg.cr3, "SCARCNT"); + state->u.f0.fld.cr3.wus = cm_object_get_child_by_name(state->u.f0.reg.cr3, "WUS"); + state->u.f0.fld.cr3.wufie = cm_object_get_child_by_name(state->u.f0.reg.cr3, "WUFIE"); + + // BRR bitfields. + state->u.f0.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f0.reg.brr, "DIV_Fraction"); + state->u.f0.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f0.reg.brr, "DIV_Mantissa"); + + // GTPR bitfields. + state->u.f0.fld.gtpr.psc = cm_object_get_child_by_name(state->u.f0.reg.gtpr, "PSC"); + state->u.f0.fld.gtpr.gt = cm_object_get_child_by_name(state->u.f0.reg.gtpr, "GT"); + + // RTOR bitfields. + state->u.f0.fld.rtor.rto = cm_object_get_child_by_name(state->u.f0.reg.rtor, "RTO"); + state->u.f0.fld.rtor.blen = cm_object_get_child_by_name(state->u.f0.reg.rtor, "BLEN"); + + // RQR bitfields. + state->u.f0.fld.rqr.abrrq = cm_object_get_child_by_name(state->u.f0.reg.rqr, "ABRRQ"); + state->u.f0.fld.rqr.sbkrq = cm_object_get_child_by_name(state->u.f0.reg.rqr, "SBKRQ"); + state->u.f0.fld.rqr.mmrq = cm_object_get_child_by_name(state->u.f0.reg.rqr, "MMRQ"); + state->u.f0.fld.rqr.rxfrq = cm_object_get_child_by_name(state->u.f0.reg.rqr, "RXFRQ"); + state->u.f0.fld.rqr.txfrq = cm_object_get_child_by_name(state->u.f0.reg.rqr, "TXFRQ"); + + // ISR bitfields. + state->u.f0.fld.isr.pe = cm_object_get_child_by_name(state->u.f0.reg.isr, "PE"); + state->u.f0.fld.isr.fe = cm_object_get_child_by_name(state->u.f0.reg.isr, "FE"); + state->u.f0.fld.isr.nf = cm_object_get_child_by_name(state->u.f0.reg.isr, "NF"); + state->u.f0.fld.isr.ore = cm_object_get_child_by_name(state->u.f0.reg.isr, "ORE"); + state->u.f0.fld.isr.idle = cm_object_get_child_by_name(state->u.f0.reg.isr, "IDLE"); + state->u.f0.fld.isr.rxne = cm_object_get_child_by_name(state->u.f0.reg.isr, "RXNE"); + state->u.f0.fld.isr.tc = cm_object_get_child_by_name(state->u.f0.reg.isr, "TC"); + state->u.f0.fld.isr.txe = cm_object_get_child_by_name(state->u.f0.reg.isr, "TXE"); + state->u.f0.fld.isr.lbdf = cm_object_get_child_by_name(state->u.f0.reg.isr, "LBDF"); + state->u.f0.fld.isr.ctsif = cm_object_get_child_by_name(state->u.f0.reg.isr, "CTSIF"); + state->u.f0.fld.isr.cts = cm_object_get_child_by_name(state->u.f0.reg.isr, "CTS"); + state->u.f0.fld.isr.rtof = cm_object_get_child_by_name(state->u.f0.reg.isr, "RTOF"); + state->u.f0.fld.isr.eobf = cm_object_get_child_by_name(state->u.f0.reg.isr, "EOBF"); + state->u.f0.fld.isr.abre = cm_object_get_child_by_name(state->u.f0.reg.isr, "ABRE"); + state->u.f0.fld.isr.abrf = cm_object_get_child_by_name(state->u.f0.reg.isr, "ABRF"); + state->u.f0.fld.isr.busy = cm_object_get_child_by_name(state->u.f0.reg.isr, "BUSY"); + state->u.f0.fld.isr.cmf = cm_object_get_child_by_name(state->u.f0.reg.isr, "CMF"); + state->u.f0.fld.isr.sbkf = cm_object_get_child_by_name(state->u.f0.reg.isr, "SBKF"); + state->u.f0.fld.isr.rwu = cm_object_get_child_by_name(state->u.f0.reg.isr, "RWU"); + state->u.f0.fld.isr.wuf = cm_object_get_child_by_name(state->u.f0.reg.isr, "WUF"); + state->u.f0.fld.isr.teack = cm_object_get_child_by_name(state->u.f0.reg.isr, "TEACK"); + state->u.f0.fld.isr.reack = cm_object_get_child_by_name(state->u.f0.reg.isr, "REACK"); + + // ICR bitfields. + state->u.f0.fld.icr.pecf = cm_object_get_child_by_name(state->u.f0.reg.icr, "PECF"); + state->u.f0.fld.icr.fecf = cm_object_get_child_by_name(state->u.f0.reg.icr, "FECF"); + state->u.f0.fld.icr.ncf = cm_object_get_child_by_name(state->u.f0.reg.icr, "NCF"); + state->u.f0.fld.icr.orecf = cm_object_get_child_by_name(state->u.f0.reg.icr, "ORECF"); + state->u.f0.fld.icr.idlecf = cm_object_get_child_by_name(state->u.f0.reg.icr, "IDLECF"); + state->u.f0.fld.icr.tccf = cm_object_get_child_by_name(state->u.f0.reg.icr, "TCCF"); + state->u.f0.fld.icr.lbdcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "LBDCF"); + state->u.f0.fld.icr.ctscf = cm_object_get_child_by_name(state->u.f0.reg.icr, "CTSCF"); + state->u.f0.fld.icr.rtocf = cm_object_get_child_by_name(state->u.f0.reg.icr, "RTOCF"); + state->u.f0.fld.icr.eobcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "EOBCF"); + state->u.f0.fld.icr.cmcf = cm_object_get_child_by_name(state->u.f0.reg.icr, "CMCF"); + state->u.f0.fld.icr.wucf = cm_object_get_child_by_name(state->u.f0.reg.icr, "WUCF"); + + // RDR bitfields. + state->u.f0.fld.rdr.rdr = cm_object_get_child_by_name(state->u.f0.reg.rdr, "RDR"); + + // TDR bitfields. + state->u.f0.fld.tdr.tdr = cm_object_get_child_by_name(state->u.f0.reg.tdr, "TDR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usart_is_enabled(Object *obj) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USARTState *state = STM32_USART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_USART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USARTState *state = STM32_USART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_usart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_usart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_usart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USART%dEN", + 1 + state->port_index - STM32_PORT_USART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USART); +} + +static void stm32_usart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usart_reset_callback; + dc->realize = stm32_usart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usart_is_enabled; +} + +static const TypeInfo stm32_usart_type_info = { + .name = TYPE_STM32_USART, + .parent = TYPE_STM32_USART_PARENT, + .instance_init = stm32_usart_instance_init_callback, + .instance_size = sizeof(STM32USARTState), + .class_init = stm32_usart_class_init_callback, + .class_size = sizeof(STM32USARTClass) }; + +static void stm32_usart_register_types(void) +{ + type_register_static(&stm32_usart_type_info); +} + +type_init(stm32_usart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/usart1.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/usart1.h new file mode 100644 index 0000000000..ccbce5f49c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/usart1.h @@ -0,0 +1,277 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USART_H_ +#define STM32_USART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USART DEVICE_PATH_STM32 "USART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_USART1, + STM32_PORT_USART2, + STM32_PORT_USART3, + STM32_PORT_USART4, + STM32_PORT_USART5, + STM32_PORT_USART6, + STM32_PORT_USART7, + STM32_PORT_USART8, + STM32_PORT_USART_UNDEFINED = 0xFF, +} stm32_usart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USART TYPE_STM32_PREFIX "usart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USARTParentClass; +typedef PeripheralState STM32USARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USARTClass, (obj), TYPE_STM32_USART) +#define STM32_USART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USARTClass, (klass), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentClass parent_class; + // public: + + // None, so far. +} STM32USARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USART_STATE(obj) \ + OBJECT_CHECK(STM32USARTState, (obj), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_usart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 USART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *cr3; // 0x8 (Control register 3) + Object *brr; // 0xC (Baud rate register) + Object *gtpr; // 0x10 (Guard time and prescaler register) + Object *rtor; // 0x14 (Receiver timeout register) + Object *rqr; // 0x18 (Request register) + Object *isr; // 0x1C (Interrupt & status register) + Object *icr; // 0x20 (Interrupt flag clear register) + Object *rdr; // 0x24 (Receive data register) + Object *tdr; // 0x28 (Transmit data register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *ue; // [0:0] USART enable + Object *uesm; // [1:1] USART enable in Stop mode + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] Interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Receiver wakeup method + Object *m; // [12:12] Word length + Object *mme; // [13:13] Mute mode enable + Object *cmie; // [14:14] Character match interrupt enable + Object *over8; // [15:15] Oversampling mode + Object *dedt; // [16:20] Driver Enable deassertion time + Object *deat; // [21:25] Driver Enable assertion time + Object *rtoie; // [26:26] Receiver timeout interrupt enable + Object *eobie; // [27:27] End of Block interrupt enable + Object *m1; // [28:28] Word length + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *addm7; // [4:4] 7-bit Address Detection/4-bit Address Detection + Object *lbdl; // [5:5] LIN break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *lbcl; // [8:8] Last bit clock pulse + Object *cpha; // [9:9] Clock phase + Object *cpol; // [10:10] Clock polarity + Object *clken; // [11:11] Clock enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + Object *swap; // [15:15] Swap TX/RX pins + Object *rxinv; // [16:16] RX pin active level inversion + Object *txinv; // [17:17] TX pin active level inversion + Object *datainv; // [18:18] Binary data inversion + Object *msbfirst; // [19:19] Most significant bit first + Object *abren; // [20:20] Auto baud rate enable + Object *abrmod; // [21:22] Auto baud rate mode + Object *rtoen; // [23:23] Receiver timeout enable + Object *add0; // [24:27] Address of the USART node + Object *add4; // [28:31] Address of the USART node + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *nack; // [4:4] Smartcard NACK enable + Object *scen; // [5:5] Smartcard mode enable + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *rtse; // [8:8] RTS enable + Object *ctse; // [9:9] CTS enable + Object *ctsie; // [10:10] CTS interrupt enable + Object *onebit; // [11:11] One sample bit method enable + Object *ovrdis; // [12:12] Overrun Disable + Object *ddre; // [13:13] DMA Disable on Reception Error + Object *dem; // [14:14] Driver enable mode + Object *dep; // [15:15] Driver enable polarity selection + Object *scarcnt; // [17:19] Smartcard auto-retry count + Object *wus; // [20:21] Wakeup from Stop mode interrupt flag selection + Object *wufie; // [22:22] Wakeup from Stop mode interrupt enable + } cr3; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // GTPR (Guard time and prescaler register) bitfields. + struct { + Object *psc; // [0:7] Prescaler value + Object *gt; // [8:15] Guard time value + } gtpr; + + // RTOR (Receiver timeout register) bitfields. + struct { + Object *rto; // [0:23] Receiver timeout value + Object *blen; // [24:31] Block Length + } rtor; + + // RQR (Request register) bitfields. + struct { + Object *abrrq; // [0:0] Auto baud rate request + Object *sbkrq; // [1:1] Send break request + Object *mmrq; // [2:2] Mute mode request + Object *rxfrq; // [3:3] Receive data flush request + Object *txfrq; // [4:4] Transmit data flush request + } rqr; + + // ISR (Interrupt & status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *nf; // [2:2] Noise detected flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] Idle line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbdf; // [8:8] LIN break detection flag + Object *ctsif; // [9:9] CTS interrupt flag + Object *cts; // [10:10] CTS flag + Object *rtof; // [11:11] Receiver timeout + Object *eobf; // [12:12] End of block flag + Object *abre; // [14:14] Auto baud rate error + Object *abrf; // [15:15] Auto baud rate flag + Object *busy; // [16:16] Busy flag + Object *cmf; // [17:17] Character match flag + Object *sbkf; // [18:18] Send break flag + Object *rwu; // [19:19] Receiver wakeup from Mute mode + Object *wuf; // [20:20] Wakeup from Stop mode flag + Object *teack; // [21:21] Transmit enable acknowledge flag + Object *reack; // [22:22] Receive enable acknowledge flag + } isr; + + // ICR (Interrupt flag clear register) bitfields. + struct { + Object *pecf; // [0:0] Parity error clear flag + Object *fecf; // [1:1] Framing error clear flag + Object *ncf; // [2:2] Noise detected clear flag + Object *orecf; // [3:3] Overrun error clear flag + Object *idlecf; // [4:4] Idle line detected clear flag + Object *tccf; // [6:6] Transmission complete clear flag + Object *lbdcf; // [8:8] LIN break detection clear flag + Object *ctscf; // [9:9] CTS clear flag + Object *rtocf; // [11:11] Receiver timeout clear flag + Object *eobcf; // [12:12] End of timeout clear flag + Object *cmcf; // [17:17] Character match clear flag + Object *wucf; // [20:20] Wakeup from Stop mode clear flag + } icr; + + // RDR (Receive data register) bitfields. + struct { + Object *rdr; // [0:8] Receive data value + } rdr; + + // TDR (Transmit data register) bitfields. + struct { + Object *tdr; // [0:8] Transmit data value + } tdr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/usb.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/usb.c new file mode 100644 index 0000000000..17baa6415f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/usb.c @@ -0,0 +1,406 @@ +/* + * STM32 - USB (Universal serial bus full-speed device interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_usb_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USBState *state = STM32_USB_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.ep0r = cm_object_get_child_by_name(obj, "EP0R"); + state->u.f0.reg.ep1r = cm_object_get_child_by_name(obj, "EP1R"); + state->u.f0.reg.ep2r = cm_object_get_child_by_name(obj, "EP2R"); + state->u.f0.reg.ep3r = cm_object_get_child_by_name(obj, "EP3R"); + state->u.f0.reg.ep4r = cm_object_get_child_by_name(obj, "EP4R"); + state->u.f0.reg.ep5r = cm_object_get_child_by_name(obj, "EP5R"); + state->u.f0.reg.ep6r = cm_object_get_child_by_name(obj, "EP6R"); + state->u.f0.reg.ep7r = cm_object_get_child_by_name(obj, "EP7R"); + state->u.f0.reg.cntr = cm_object_get_child_by_name(obj, "CNTR"); + state->u.f0.reg.istr = cm_object_get_child_by_name(obj, "ISTR"); + state->u.f0.reg.fnr = cm_object_get_child_by_name(obj, "FNR"); + state->u.f0.reg.daddr = cm_object_get_child_by_name(obj, "DADDR"); + state->u.f0.reg.btable = cm_object_get_child_by_name(obj, "BTABLE"); + state->u.f0.reg.lpmcsr = cm_object_get_child_by_name(obj, "LPMCSR"); + state->u.f0.reg.bcdr = cm_object_get_child_by_name(obj, "BCDR"); + + + // EP0R bitfields. + state->u.f0.fld.ep0r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "EA"); + state->u.f0.fld.ep0r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "STAT_TX"); + state->u.f0.fld.ep0r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "DTOG_TX"); + state->u.f0.fld.ep0r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "CTR_TX"); + state->u.f0.fld.ep0r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "EP_KIND"); + state->u.f0.fld.ep0r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "EP_TYPE"); + state->u.f0.fld.ep0r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "SETUP"); + state->u.f0.fld.ep0r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "STAT_RX"); + state->u.f0.fld.ep0r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "DTOG_RX"); + state->u.f0.fld.ep0r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep0r, "CTR_RX"); + + // EP1R bitfields. + state->u.f0.fld.ep1r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "EA"); + state->u.f0.fld.ep1r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "STAT_TX"); + state->u.f0.fld.ep1r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "DTOG_TX"); + state->u.f0.fld.ep1r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "CTR_TX"); + state->u.f0.fld.ep1r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "EP_KIND"); + state->u.f0.fld.ep1r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "EP_TYPE"); + state->u.f0.fld.ep1r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "SETUP"); + state->u.f0.fld.ep1r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "STAT_RX"); + state->u.f0.fld.ep1r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "DTOG_RX"); + state->u.f0.fld.ep1r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep1r, "CTR_RX"); + + // EP2R bitfields. + state->u.f0.fld.ep2r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "EA"); + state->u.f0.fld.ep2r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "STAT_TX"); + state->u.f0.fld.ep2r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "DTOG_TX"); + state->u.f0.fld.ep2r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "CTR_TX"); + state->u.f0.fld.ep2r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "EP_KIND"); + state->u.f0.fld.ep2r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "EP_TYPE"); + state->u.f0.fld.ep2r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "SETUP"); + state->u.f0.fld.ep2r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "STAT_RX"); + state->u.f0.fld.ep2r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "DTOG_RX"); + state->u.f0.fld.ep2r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep2r, "CTR_RX"); + + // EP3R bitfields. + state->u.f0.fld.ep3r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "EA"); + state->u.f0.fld.ep3r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "STAT_TX"); + state->u.f0.fld.ep3r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "DTOG_TX"); + state->u.f0.fld.ep3r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "CTR_TX"); + state->u.f0.fld.ep3r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "EP_KIND"); + state->u.f0.fld.ep3r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "EP_TYPE"); + state->u.f0.fld.ep3r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "SETUP"); + state->u.f0.fld.ep3r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "STAT_RX"); + state->u.f0.fld.ep3r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "DTOG_RX"); + state->u.f0.fld.ep3r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep3r, "CTR_RX"); + + // EP4R bitfields. + state->u.f0.fld.ep4r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "EA"); + state->u.f0.fld.ep4r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "STAT_TX"); + state->u.f0.fld.ep4r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "DTOG_TX"); + state->u.f0.fld.ep4r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "CTR_TX"); + state->u.f0.fld.ep4r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "EP_KIND"); + state->u.f0.fld.ep4r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "EP_TYPE"); + state->u.f0.fld.ep4r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "SETUP"); + state->u.f0.fld.ep4r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "STAT_RX"); + state->u.f0.fld.ep4r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "DTOG_RX"); + state->u.f0.fld.ep4r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep4r, "CTR_RX"); + + // EP5R bitfields. + state->u.f0.fld.ep5r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "EA"); + state->u.f0.fld.ep5r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "STAT_TX"); + state->u.f0.fld.ep5r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "DTOG_TX"); + state->u.f0.fld.ep5r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "CTR_TX"); + state->u.f0.fld.ep5r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "EP_KIND"); + state->u.f0.fld.ep5r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "EP_TYPE"); + state->u.f0.fld.ep5r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "SETUP"); + state->u.f0.fld.ep5r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "STAT_RX"); + state->u.f0.fld.ep5r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "DTOG_RX"); + state->u.f0.fld.ep5r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep5r, "CTR_RX"); + + // EP6R bitfields. + state->u.f0.fld.ep6r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "EA"); + state->u.f0.fld.ep6r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "STAT_TX"); + state->u.f0.fld.ep6r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "DTOG_TX"); + state->u.f0.fld.ep6r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "CTR_TX"); + state->u.f0.fld.ep6r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "EP_KIND"); + state->u.f0.fld.ep6r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "EP_TYPE"); + state->u.f0.fld.ep6r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "SETUP"); + state->u.f0.fld.ep6r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "STAT_RX"); + state->u.f0.fld.ep6r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "DTOG_RX"); + state->u.f0.fld.ep6r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep6r, "CTR_RX"); + + // EP7R bitfields. + state->u.f0.fld.ep7r.ea = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "EA"); + state->u.f0.fld.ep7r.stat_tx = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "STAT_TX"); + state->u.f0.fld.ep7r.dtog_tx = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "DTOG_TX"); + state->u.f0.fld.ep7r.ctr_tx = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "CTR_TX"); + state->u.f0.fld.ep7r.ep_kind = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "EP_KIND"); + state->u.f0.fld.ep7r.ep_type = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "EP_TYPE"); + state->u.f0.fld.ep7r.setup = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "SETUP"); + state->u.f0.fld.ep7r.stat_rx = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "STAT_RX"); + state->u.f0.fld.ep7r.dtog_rx = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "DTOG_RX"); + state->u.f0.fld.ep7r.ctr_rx = cm_object_get_child_by_name(state->u.f0.reg.ep7r, "CTR_RX"); + + // CNTR bitfields. + state->u.f0.fld.cntr.fres = cm_object_get_child_by_name(state->u.f0.reg.cntr, "FRES"); + state->u.f0.fld.cntr.pdwn = cm_object_get_child_by_name(state->u.f0.reg.cntr, "PDWN"); + state->u.f0.fld.cntr.lpmode = cm_object_get_child_by_name(state->u.f0.reg.cntr, "LPMODE"); + state->u.f0.fld.cntr.fsusp = cm_object_get_child_by_name(state->u.f0.reg.cntr, "FSUSP"); + state->u.f0.fld.cntr.resume = cm_object_get_child_by_name(state->u.f0.reg.cntr, "RESUME"); + state->u.f0.fld.cntr.l1resume = cm_object_get_child_by_name(state->u.f0.reg.cntr, "L1RESUME"); + state->u.f0.fld.cntr.l1reqm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "L1REQM"); + state->u.f0.fld.cntr.esofm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "ESOFM"); + state->u.f0.fld.cntr.sofm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "SOFM"); + state->u.f0.fld.cntr.resetm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "RESETM"); + state->u.f0.fld.cntr.suspm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "SUSPM"); + state->u.f0.fld.cntr.wkupm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "WKUPM"); + state->u.f0.fld.cntr.errm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "ERRM"); + state->u.f0.fld.cntr.pmaovrm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "PMAOVRM"); + state->u.f0.fld.cntr.ctrm = cm_object_get_child_by_name(state->u.f0.reg.cntr, "CTRM"); + + // ISTR bitfields. + state->u.f0.fld.istr.ep_id = cm_object_get_child_by_name(state->u.f0.reg.istr, "EP_ID"); + state->u.f0.fld.istr.dir = cm_object_get_child_by_name(state->u.f0.reg.istr, "DIR"); + state->u.f0.fld.istr.l1req = cm_object_get_child_by_name(state->u.f0.reg.istr, "L1REQ"); + state->u.f0.fld.istr.esof = cm_object_get_child_by_name(state->u.f0.reg.istr, "ESOF"); + state->u.f0.fld.istr.sof = cm_object_get_child_by_name(state->u.f0.reg.istr, "SOF"); + state->u.f0.fld.istr.reset = cm_object_get_child_by_name(state->u.f0.reg.istr, "RESET"); + state->u.f0.fld.istr.susp = cm_object_get_child_by_name(state->u.f0.reg.istr, "SUSP"); + state->u.f0.fld.istr.wkup = cm_object_get_child_by_name(state->u.f0.reg.istr, "WKUP"); + state->u.f0.fld.istr.err = cm_object_get_child_by_name(state->u.f0.reg.istr, "ERR"); + state->u.f0.fld.istr.pmaovr = cm_object_get_child_by_name(state->u.f0.reg.istr, "PMAOVR"); + state->u.f0.fld.istr.ctr = cm_object_get_child_by_name(state->u.f0.reg.istr, "CTR"); + + // FNR bitfields. + state->u.f0.fld.fnr.fn = cm_object_get_child_by_name(state->u.f0.reg.fnr, "FN"); + state->u.f0.fld.fnr.lsof = cm_object_get_child_by_name(state->u.f0.reg.fnr, "LSOF"); + state->u.f0.fld.fnr.lck = cm_object_get_child_by_name(state->u.f0.reg.fnr, "LCK"); + state->u.f0.fld.fnr.rxdm = cm_object_get_child_by_name(state->u.f0.reg.fnr, "RXDM"); + state->u.f0.fld.fnr.rxdp = cm_object_get_child_by_name(state->u.f0.reg.fnr, "RXDP"); + + // DADDR bitfields. + state->u.f0.fld.daddr.add = cm_object_get_child_by_name(state->u.f0.reg.daddr, "ADD"); + state->u.f0.fld.daddr.ef = cm_object_get_child_by_name(state->u.f0.reg.daddr, "EF"); + + // BTABLE bitfields. + state->u.f0.fld.btable.btable = cm_object_get_child_by_name(state->u.f0.reg.btable, "BTABLE"); + + // LPMCSR bitfields. + state->u.f0.fld.lpmcsr.lpmen = cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "LPMEN"); + state->u.f0.fld.lpmcsr.lpmack = cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "LPMACK"); + state->u.f0.fld.lpmcsr.remwake = cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "REMWAKE"); + state->u.f0.fld.lpmcsr.besl = cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "BESL"); + + // BCDR bitfields. + state->u.f0.fld.bcdr.bcden = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "BCDEN"); + state->u.f0.fld.bcdr.dcden = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "DCDEN"); + state->u.f0.fld.bcdr.pden = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "PDEN"); + state->u.f0.fld.bcdr.sden = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "SDEN"); + state->u.f0.fld.bcdr.dcdet = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "DCDET"); + state->u.f0.fld.bcdr.pdet = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "PDET"); + state->u.f0.fld.bcdr.sdet = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "SDET"); + state->u.f0.fld.bcdr.ps2det = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "PS2DET"); + state->u.f0.fld.bcdr.dppu = cm_object_get_child_by_name(state->u.f0.reg.bcdr, "DPPU"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usb_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usb_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usb_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usb_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usb_is_enabled(Object *obj) +{ + STM32USBState *state = STM32_USB_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usb_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USBState *state = STM32_USB_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usb_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USB)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USBState *state = STM32_USB_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USB"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_usb_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usb_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_usb_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usb_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_usb_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USBEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usb_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USB); +} + +static void stm32_usb_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usb_reset_callback; + dc->realize = stm32_usb_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usb_is_enabled; +} + +static const TypeInfo stm32_usb_type_info = { + .name = TYPE_STM32_USB, + .parent = TYPE_STM32_USB_PARENT, + .instance_init = stm32_usb_instance_init_callback, + .instance_size = sizeof(STM32USBState), + .class_init = stm32_usb_class_init_callback, + .class_size = sizeof(STM32USBClass) }; + +static void stm32_usb_register_types(void) +{ + type_register_static(&stm32_usb_type_info); +} + +type_init(stm32_usb_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/usb.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/usb.h new file mode 100644 index 0000000000..bda9681a65 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/usb.h @@ -0,0 +1,301 @@ +/* + * STM32 - USB (Universal serial bus full-speed device interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USB_H_ +#define STM32_USB_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USB DEVICE_PATH_STM32 "USB" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USB TYPE_STM32_PREFIX "usb" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USB_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USBParentClass; +typedef PeripheralState STM32USBParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USB_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USBClass, (obj), TYPE_STM32_USB) +#define STM32_USB_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USBClass, (klass), TYPE_STM32_USB) + +typedef struct { + // private: + STM32USBParentClass parent_class; + // public: + + // None, so far. +} STM32USBClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USB_STATE(obj) \ + OBJECT_CHECK(STM32USBState, (obj), TYPE_STM32_USB) + +typedef struct { + // private: + STM32USBParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 USB (Universal serial bus full-speed device interface) registers. + struct { + Object *ep0r; // 0x0 (Endpoint 0 register) + Object *ep1r; // 0x4 (Endpoint 1 register) + Object *ep2r; // 0x8 (Endpoint 2 register) + Object *ep3r; // 0xC (Endpoint 3 register) + Object *ep4r; // 0x10 (Endpoint 4 register) + Object *ep5r; // 0x14 (Endpoint 5 register) + Object *ep6r; // 0x18 (Endpoint 6 register) + Object *ep7r; // 0x1C (Endpoint 7 register) + Object *cntr; // 0x40 (Control register) + Object *istr; // 0x44 (Interrupt status register) + Object *fnr; // 0x48 (Frame number register) + Object *daddr; // 0x4C (Device address) + Object *btable; // 0x50 (Buffer table address) + Object *lpmcsr; // 0x54 (LPM control and status register) + Object *bcdr; // 0x58 (Battery charging detector) + } reg; + + struct { + + // EP0R (Endpoint 0 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep0r; + + // EP1R (Endpoint 1 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep1r; + + // EP2R (Endpoint 2 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep2r; + + // EP3R (Endpoint 3 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep3r; + + // EP4R (Endpoint 4 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep4r; + + // EP5R (Endpoint 5 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep5r; + + // EP6R (Endpoint 6 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep6r; + + // EP7R (Endpoint 7 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep7r; + + // CNTR (Control register) bitfields. + struct { + Object *fres; // [0:0] Force USB Reset + Object *pdwn; // [1:1] Power down + Object *lpmode; // [2:2] Low-power mode + Object *fsusp; // [3:3] Force suspend + Object *resume; // [4:4] Resume request + Object *l1resume; // [5:5] LPM L1 Resume request + Object *l1reqm; // [7:7] LPM L1 state request interrupt mask + Object *esofm; // [8:8] Expected start of frame interrupt mask + Object *sofm; // [9:9] Start of frame interrupt mask + Object *resetm; // [10:10] USB reset interrupt mask + Object *suspm; // [11:11] Suspend mode interrupt mask + Object *wkupm; // [12:12] Wakeup interrupt mask + Object *errm; // [13:13] Error interrupt mask + Object *pmaovrm; // [14:14] Packet memory area over / underrun interrupt mask + Object *ctrm; // [15:15] Correct transfer interrupt mask + } cntr; + + // ISTR (Interrupt status register) bitfields. + struct { + Object *ep_id; // [0:3] Endpoint Identifier + Object *dir; // [4:4] Direction of transaction + Object *l1req; // [7:7] LPM L1 state request + Object *esof; // [8:8] Expected start frame + Object *sof; // [9:9] Start of frame + Object *reset; // [10:10] Reset request + Object *susp; // [11:11] Suspend mode request + Object *wkup; // [12:12] Wakeup + Object *err; // [13:13] Error + Object *pmaovr; // [14:14] Packet memory area over / underrun + Object *ctr; // [15:15] Correct transfer + } istr; + + // FNR (Frame number register) bitfields. + struct { + Object *fn; // [0:10] Frame number + Object *lsof; // [11:12] Lost SOF + Object *lck; // [13:13] Locked + Object *rxdm; // [14:14] Receive data - line status + Object *rxdp; // [15:15] Receive data + line status + } fnr; + + // DADDR (Device address) bitfields. + struct { + Object *add; // [0:6] Device address + Object *ef; // [7:7] Enable function + } daddr; + + // BTABLE (Buffer table address) bitfields. + struct { + Object *btable; // [3:15] Buffer table + } btable; + + // LPMCSR (LPM control and status register) bitfields. + struct { + Object *lpmen; // [0:0] LPM support enable + Object *lpmack; // [1:1] LPM Token acknowledge enable + Object *remwake; // [3:3] BRemoteWake value + Object *besl; // [4:7] BESL value + } lpmcsr; + + // BCDR (Battery charging detector) bitfields. + struct { + Object *bcden; // [0:0] Battery charging detector (BCD) enable + Object *dcden; // [1:1] Data contact detection (DCD) mode enable + Object *pden; // [2:2] Primary detection (PD) mode enable + Object *sden; // [3:3] Secondary detection (SD) mode enable + Object *dcdet; // [4:4] Data contact detection (DCD) status + Object *pdet; // [5:5] Primary detection (PD) status + Object *sdet; // [6:6] Secondary detection (SD) status + Object *ps2det; // [7:7] DM pull-up detection status + Object *dppu; // [15:15] DP pull-up control + } bcdr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USBState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USB_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/wwdg.c b/gnu-mcu-eclipse/devices/support/STM32F0x1/wwdg.c new file mode 100644 index 0000000000..4f5904b7a8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/wwdg.c @@ -0,0 +1,249 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x1_wwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f0.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f0.reg.cfr = cm_object_get_child_by_name(obj, "CFR"); + state->u.f0.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f0.fld.cr.t = cm_object_get_child_by_name(state->u.f0.reg.cr, "T"); + state->u.f0.fld.cr.wdga = cm_object_get_child_by_name(state->u.f0.reg.cr, "WDGA"); + + // CFR bitfields. + state->u.f0.fld.cfr.w = cm_object_get_child_by_name(state->u.f0.reg.cfr, "W"); + state->u.f0.fld.cfr.wdgtb = cm_object_get_child_by_name(state->u.f0.reg.cfr, "WDGTB"); + state->u.f0.fld.cfr.ewi = cm_object_get_child_by_name(state->u.f0.reg.cfr, "EWI"); + + // SR bitfields. + state->u.f0.fld.sr.ewif = cm_object_get_child_by_name(state->u.f0.reg.sr, "EWIF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_wwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_wwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_wwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_wwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_wwdg_is_enabled(Object *obj) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_wwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_wwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_WWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32WWDGState *state = STM32_WWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "WWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x1 ) { + + stm32f0x1_wwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_wwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_wwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_wwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_wwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/WWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_wwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_WWDG); +} + +static void stm32_wwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_wwdg_reset_callback; + dc->realize = stm32_wwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_wwdg_is_enabled; +} + +static const TypeInfo stm32_wwdg_type_info = { + .name = TYPE_STM32_WWDG, + .parent = TYPE_STM32_WWDG_PARENT, + .instance_init = stm32_wwdg_instance_init_callback, + .instance_size = sizeof(STM32WWDGState), + .class_init = stm32_wwdg_class_init_callback, + .class_size = sizeof(STM32WWDGClass) }; + +static void stm32_wwdg_register_types(void) +{ + type_register_static(&stm32_wwdg_type_info); +} + +type_init(stm32_wwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x1/wwdg.h b/gnu-mcu-eclipse/devices/support/STM32F0x1/wwdg.h new file mode 100644 index 0000000000..c7ba585cb3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x1/wwdg.h @@ -0,0 +1,120 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_WWDG_H_ +#define STM32_WWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_WWDG DEVICE_PATH_STM32 "WWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_WWDG TYPE_STM32_PREFIX "wwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_WWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32WWDGParentClass; +typedef PeripheralState STM32WWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_WWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32WWDGClass, (obj), TYPE_STM32_WWDG) +#define STM32_WWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32WWDGClass, (klass), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentClass parent_class; + // public: + + // None, so far. +} STM32WWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_WWDG_STATE(obj) \ + OBJECT_CHECK(STM32WWDGState, (obj), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0 WWDG (Window watchdog) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *cfr; // 0x4 (Configuration register) + Object *sr; // 0x8 (Status register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *t; // [0:6] 7-bit counter + Object *wdga; // [7:7] Activation bit + } cr; + + // CFR (Configuration register) bitfields. + struct { + Object *w; // [0:6] 7-bit window value + Object *wdgtb; // [7:8] Timer base + Object *ewi; // [9:9] Early wakeup interrupt + } cfr; + + // SR (Status register) bitfields. + struct { + Object *ewif; // [0:0] Early wakeup interrupt flag + } sr; + } fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32WWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_WWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2-patch.json b/gnu-mcu-eclipse/devices/support/STM32F0x2-patch.json new file mode 100644 index 0000000000..74635eef0f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2-patch.json @@ -0,0 +1,135 @@ +{ + "comment": "Patch for QEMU use.", + "device": { + "name": "STM32F0x2", + "cpu": { + "name": "CM0", + "revision": "r0p0", + "endian": "little", + "mpuPresent": "false", + "fpuPresent": "false", + "nvicPrioBits": "2", + "deviceNumInterrupts": "31", + "vendorSystickConfig": "false", + "qemuItmPresent": false + }, + "access": "read-write", + "qemuAlignment": "any", + "peripherals": [ + { + "name": "EXTI", + "qemuAlignment": "word" + }, + { + "name": "FLASH", + "qemuAlignment": "word" + }, + { + "name": "PWR", + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "qemuAlignment": "any" + }, + { + "name": "SYSCFG", + "qemuAlignment": "any" + }, + { + "name": "GPIOA", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "qemuAlignment": "any", + "qemuGroupName": "GPIO" + }, + { + "name": "USART1", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART2", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART3", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART4", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART5", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART6", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART7", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART8", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "SPI1", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "qemuGroupName": "SPI" + }, + { + "name": "I2C1", + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "qemuGroupName": "I2C" + }, + { + "name": "DMA1", + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "qemuGroupName": "DMA" + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2-xsvd.json b/gnu-mcu-eclipse/devices/support/STM32F0x2-xsvd.json new file mode 100644 index 0000000000..015dc44000 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2-xsvd.json @@ -0,0 +1,30633 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F0x2.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.11", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x2.svd", + "--output", + "STM32F0x2-xsvd.json" + ], + "date": "2017-01-30T20:41:59.999Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F0x2", + "version": "1.0", + "description": "STM32F0x2", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "CRC", + "description": "Cyclic redundancy check calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data register bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "General-purpose 8-bit data register bits", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "POLYSIZE", + "description": "Polynomial size", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "REV_IN", + "description": "Reverse input data", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "REV_OUT", + "description": "Reverse output data", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "INIT", + "displayName": "INIT", + "description": "Initial CRC value", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "INIT", + "description": "Programmable initial CRC value", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "GPIOF", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48001400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bit 0", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000C00" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000800" + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOF", + "baseAddress": "0x48000400" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOF", + "baseAddress": "0x48001000" + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x48000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x28000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Port x Reset bit y", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x Reset bit y", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x Reset bit y", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x Reset bit y", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x Reset bit y", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x Reset bit y", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x Reset bit y", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x Reset bit y", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x Reset bit y", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x Reset bit y", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x Reset bit y", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x Reset bit y", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x Reset bit y", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x Reset bit y", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x Reset bit y", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Port x Reset bit y", + "bitOffset": "15", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1_global_interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "NSSP", + "description": "NSS pulse management", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "FRXTH", + "description": "FIFO reception threshold", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LDMA_RX", + "description": "Last DMA transfer for reception", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LDMA_TX", + "description": "Last DMA transfer for transmission", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FRLVL", + "description": "FIFO reception level", + "bitOffset": "9", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "FTLVL", + "description": "FIFO transmission level", + "bitOffset": "11", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000010", + "fields": [ + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "26" + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt and DAC underrun interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "VREFINTRDY", + "description": "VREFINT reference voltage ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP1", + "description": "Enable WKUP pin 1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP2", + "description": "Enable WKUP pin 2", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP3", + "description": "Enable WKUP pin 3", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP4", + "description": "Enable WKUP pin 4", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP5", + "description": "Enable WKUP pin 5", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP6", + "description": "Enable WKUP pin 6", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP7", + "description": "Enable WKUP pin 7", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EWUP8", + "description": "Enable WKUP pin 8", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "I2C1", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1", + "description": "I2C1 global interrupt", + "value": "23" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXIE", + "description": "TX Interrupt enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXIE", + "description": "RX Interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADDRIE", + "description": "Address match interrupt enable (slave only)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NACKIE", + "description": "Not acknowledge received interrupt enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "STOPIE", + "description": "STOP detection Interrupt enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TCIE", + "description": "Transfer Complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRIE", + "description": "Error interrupts enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DNF", + "description": "Digital noise filter", + "bitOffset": "8", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "ANFOFF", + "description": "Analog noise filter OFF", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "13", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXDMAEN", + "description": "DMA transmission requests enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXDMAEN", + "description": "DMA reception requests enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SBC", + "description": "Slave byte control", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUPEN", + "description": "Wakeup from STOP enable", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GCEN", + "description": "General call enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBHEN", + "description": "SMBus Host address enable", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SMBDEN", + "description": "SMBus Device Default address enable", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALERTEN", + "description": "SMBUS alert enable", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECEN", + "description": "PEC enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PECBYTE", + "description": "Packet error checking byte", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "AUTOEND", + "description": "Automatic end mode (master mode)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "RELOAD", + "description": "NBYTES reload mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "NBYTES", + "description": "Number of bytes", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NACK", + "description": "NACK generation (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation (master mode)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HEAD10R", + "description": "10-bit address header only read direction (master receiver mode)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "10-bit addressing mode (master mode)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RD_WRN", + "description": "Transfer direction (master mode)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SADD8", + "description": "Slave address bit 9:8 (master mode)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "SADD1", + "description": "Slave address bit 7:1 (master mode)", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "SADD0", + "description": "Slave address bit 0 (master mode)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA1_0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OA1_1", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA1_8", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OA1MODE", + "description": "Own Address 1 10-bit mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OA1EN", + "description": "Own Address 1 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OA2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "OA2MSK", + "description": "Own Address 2 masks", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "OA2EN", + "description": "Own Address 2 enable", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "TIMINGR", + "displayName": "TIMINGR", + "description": "Timing register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SCLL", + "description": "SCL low period (master mode)", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "SCLH", + "description": "SCL high period (master mode)", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "SDADEL", + "description": "Data hold time", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "SCLDEL", + "description": "Data setup time", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "PRESC", + "description": "Timing prescaler", + "bitOffset": "28", + "bitWidth": "4" + } + ] + }, + { + "name": "TIMEOUTR", + "displayName": "TIMEOUTR", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIMEOUTA", + "description": "Bus timeout A", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "TIDLE", + "description": "Idle clock timeout detection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIMOUTEN", + "description": "Clock timeout enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIMEOUTB", + "description": "Bus timeout B", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "TEXTEN", + "description": "Extended clock timeout enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000001", + "fields": [ + { + "name": "ADDCODE", + "description": "Address match code (Slave mode)", + "bitOffset": "17", + "bitWidth": "7", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Transfer direction (Slave mode)", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIMEOUT", + "description": "Timeout or t_low detection flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun/Underrun (slave mode)", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ARLO", + "description": "Arbitration lost", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCR", + "description": "Transfer Complete Reload", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transfer Complete (master mode)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NACKF", + "description": "Not acknowledge received flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address matched (slave mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Receive data register not empty (receivers)", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXIS", + "description": "Transmit interrupt status (transmitters)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty (transmitters)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALERTCF", + "description": "Alert flag clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TIMOUTCF", + "description": "Timeout detection flag clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PECCF", + "description": "PEC Error flag clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OVRCF", + "description": "Overrun/Underrun flag clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ARLOCF", + "description": "Arbitration lost flag clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BERRCF", + "description": "Bus error flag clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STOPCF", + "description": "Stop detection flag clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACKCF", + "description": "Not Acknowledge flag clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ADDRCF", + "description": "Address Matched flag clear", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "PECR", + "displayName": "PECR", + "description": "PEC register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PEC", + "description": "Packet error checking register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDATA", + "description": "8-bit receive data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXDATA", + "description": "8-bit transmit data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2", + "description": "I2C2 global interrupt", + "value": "24" + } + ] + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WVU", + "description": "Watchdog counter window value update", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "WINR", + "displayName": "WINR", + "description": "Window register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "WIN", + "description": "Watchdog counter window value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "T", + "description": "7-bit counter", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WDGTB", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_UP_TRG_COM", + "description": "TIM1 break, update, trigger and commutation interrupt", + "value": "13" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "14" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare 3 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM2", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "15" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value (TIM2 only)", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAR", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "16" + } + ] + }, + { + "name": "TIM14", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40002000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM14", + "description": "TIM14 global interrupt", + "value": "19" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Timer input 1 remap", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM6", + "description": "Basic-timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "18" + } + ] + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD and VDDIO2 supply comparator interrupt", + "value": "1" + }, + { + "name": "EXTI0_1", + "description": "EXTI Line[1:0] interrupts", + "value": "5" + }, + { + "name": "EXTI2_3", + "description": "EXTI Line[3:2] interrupts", + "value": "6" + }, + { + "name": "EXTI4_15", + "description": "EXTI Line15 and EXTI4 interrupts", + "value": "7" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0F940000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Interrupt Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Interrupt Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Interrupt Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Interrupt Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Interrupt Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "MR23", + "description": "Event Mask on line 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "MR24", + "description": "Event Mask on line 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "MR25", + "description": "Event Mask on line 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MR26", + "description": "Event Mask on line 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "MR27", + "description": "Event Mask on line 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x33D", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ISER", + "displayName": "ISER", + "description": "Interrupt Set Enable Register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER", + "displayName": "ICER", + "description": "Interrupt Clear Enable Register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR", + "displayName": "ISPR", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR", + "displayName": "ICPR", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register 0", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_00", + "description": "PRI_00", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_01", + "description": "PRI_01", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_02", + "description": "PRI_02", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_03", + "description": "PRI_03", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register 1", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_40", + "description": "PRI_40", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_41", + "description": "PRI_41", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_42", + "description": "PRI_42", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_43", + "description": "PRI_43", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register 2", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_80", + "description": "PRI_80", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_81", + "description": "PRI_81", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_82", + "description": "PRI_82", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_83", + "description": "PRI_83", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register 3", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_120", + "description": "PRI_120", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_121", + "description": "PRI_121", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_122", + "description": "PRI_122", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_123", + "description": "PRI_123", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register 4", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_160", + "description": "PRI_160", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_161", + "description": "PRI_161", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_162", + "description": "PRI_162", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_163", + "description": "PRI_163", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register 5", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_200", + "description": "PRI_200", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_201", + "description": "PRI_201", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_202", + "description": "PRI_202", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_203", + "description": "PRI_203", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register 6", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_240", + "description": "PRI_240", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_241", + "description": "PRI_241", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_242", + "description": "PRI_242", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_243", + "description": "PRI_243", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register 7", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRI_280", + "description": "PRI_280", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PRI_281", + "description": "PRI_281", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PRI_282", + "description": "PRI_282", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PRI_283", + "description": "PRI_283", + "bitOffset": "30", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_CH1", + "description": "DMA1 channel 1 interrupt", + "value": "9" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL input clock source", + "bitOffset": "15", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCOPRE", + "description": "Microcontroller Clock Output Prescaler", + "bitOffset": "28", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PLLNODIV", + "description": "PLL clock not divided for MCO", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14RDYF", + "description": "HSI14 ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48RDYF", + "description": "HSI48 ready interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDYE", + "description": "HSI14 ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDYIE", + "description": "HSI48 ready interrupt enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI14RDYC", + "description": "HSI 14 MHz Ready Interrupt Clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSI48RDYC", + "description": "HSI48 Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGRST", + "description": "SYSCFG and COMP reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15RST", + "description": "TIM15 timer reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16RST", + "description": "TIM16 timer reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17RST", + "description": "TIM17 timer reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCURST", + "description": "Debug MCU reset", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 timer reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "Timer 14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4RST", + "description": "USART4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANRST", + "description": "CAN interface reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSRST", + "description": "Clock Recovery System interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECRST", + "description": "HDMI CEC reset", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFEN", + "description": "I/O port F clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCEN", + "description": "Touch sensing controller clock enable", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SYSCFGEN", + "description": "SYSCFG clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ADCEN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM15EN", + "description": "TIM15 timer clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM16EN", + "description": "TIM16 timer clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM17EN", + "description": "TIM17 timer clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBGMCUEN", + "description": "MCU debug module clock enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 timer clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "Timer 14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4EN", + "description": "USART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB interface clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANEN", + "description": "CAN interface clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CRSEN", + "description": "Clock Recovery System interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CECEN", + "description": "HDMI CEC interface clock enable", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSEDRV", + "description": "LSE oscillator drive capability", + "bitOffset": "3", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OBLRSTF", + "description": "Option byte loader reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "AHBRSTR", + "displayName": "AHBRSTR", + "description": "AHB peripheral reset register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IOPARST", + "description": "I/O port A reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "I/O port B reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "I/O port C reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "I/O port D reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "IOPFRST", + "description": "I/O port F reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TSCRST", + "description": "Touch sensing controller reset", + "bitOffset": "24", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Clock configuration register 2", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PREDIV", + "description": "PREDIV division factor", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR3", + "displayName": "CFGR3", + "description": "Clock configuration register 3", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "USART1SW", + "description": "USART1 clock source selection", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "I2C1SW", + "description": "I2C1 clock source selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CECSW", + "description": "HDMI CEC clock source selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "USBSW", + "description": "USB clock source selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ADCSW", + "description": "ADC clock source selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART2SW", + "description": "USART2 clock source selection", + "bitOffset": "16", + "bitWidth": "2" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Clock control register 2", + "addressOffset": "0x34", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "HSI14ON", + "description": "HSI14 clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14RDY", + "description": "HR14 clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI14DIS", + "description": "HSI14 clock request from ADC disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI14TRIM", + "description": "HSI14 clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSI14CAL", + "description": "HSI14 clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSI48ON", + "description": "HSI48 clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSI48RDY", + "description": "HSI48 clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSI48CAL", + "description": "HSI48 factory clock calibration", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ] + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1D", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "Memory mapping selection bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "ADC_DMA_RMP", + "description": "ADC DMA remapping bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART1_TX_DMA_RMP", + "description": "USART1_TX DMA remapping bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "USART1_RX_DMA_RMP", + "description": "USART1_RX DMA request remapping bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM16_DMA_RMP", + "description": "TIM16 DMA request remapping bit", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM17_DMA_RMP", + "description": "TIM17 DMA request remapping bit", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C_PB6_FM", + "description": "Fast Mode Plus (FM plus) driving capability activation bits.", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2C_PB7_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2C_PB8_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "I2C_PB9_FM", + "description": "Fast Mode Plus (FM+) driving capability activation bits.", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "I2C1_FM_plus", + "description": "FM+ driving capability activation for I2C1", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C2_FM_plus", + "description": "FM+ driving capability activation for I2C2", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SPI2_DMA_RMP", + "description": "SPI2 DMA request remapping bit", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "USART2_DMA_RMP", + "description": "USART2 DMA request remapping bit", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "USART3_DMA_RMP", + "description": "USART3 DMA request remapping bit", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "I2C1_DMA_RMP", + "description": "I2C1 DMA request remapping bit", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "TIM1_DMA_RMP", + "description": "TIM1 DMA request remapping bit", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "TIM2_DMA_RMP", + "description": "TIM2 DMA request remapping bit", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "TIM3_DMA_RMP", + "description": "TIM3 DMA request remapping bit", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI3", + "description": "EXTI 3 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI 2 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI 1 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI0", + "description": "EXTI 0 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI7", + "description": "EXTI 7 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI 6 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI 5 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI4", + "description": "EXTI 4 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI11", + "description": "EXTI 11 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI 10 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI 9 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI8", + "description": "EXTI 8 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI15", + "description": "EXTI 15 configuration bits", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI 14 configuration bits", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI 13 configuration bits", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI12", + "description": "EXTI 12 configuration bits", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SRAM_PEF", + "description": "SRAM parity flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PVD_LOCK", + "description": "PVD lock enable bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRAM_PARITY_LOCK", + "description": "SRAM parity lock bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LOCUP_LOCK", + "description": "Cortex-M0 LOCKUP bit enable bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "ADC", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OVR", + "description": "ADC overrun", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "EOS", + "description": "End of sequence flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "End of conversion flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOSMP", + "description": "End of sampling flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADRDY", + "description": "ADC ready", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "EOSIE", + "description": "End of conversion sequence interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "End of conversion interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOSMPIE", + "description": "End of sampling flag interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADRDYIE", + "description": "ADC ready interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADCAL", + "description": "ADC calibration", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "ADSTP", + "description": "ADC stop conversion command", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ADSTART", + "description": "ADC start conversion command", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ADDIS", + "description": "ADC disable command", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADEN", + "description": "ADC enable command", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR1", + "displayName": "CFGR1", + "description": "Configuration register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDCH", + "description": "Analog watchdog channel selection", + "bitOffset": "26", + "bitWidth": "5" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel or on all channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "AUTOFF", + "description": "Auto-off mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AUTDLY", + "description": "Auto-delayed conversion mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Single / continuous conversion mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVRMOD", + "description": "Overrun management mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "EXTEN", + "description": "External trigger enable and polarity selection", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "EXTSEL", + "description": "External trigger selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Data resolution", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "SCANDIR", + "description": "Scan sequence direction", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMACFG", + "description": "Direct memery access configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "Direct memory access enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Configuration register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00008000", + "fields": [ + { + "name": "JITOFF_D4", + "description": "JITOFF_D4", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "JITOFF_D2", + "description": "JITOFF_D2", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR", + "displayName": "SMPR", + "description": "Sampling time register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPR", + "description": "Sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "TR", + "displayName": "TR", + "description": "Watchdog threshold register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "CHSELR", + "displayName": "CHSELR", + "description": "Channel selection register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL18", + "description": "Channel-x selection", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CHSEL17", + "description": "Channel-x selection", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CHSEL16", + "description": "Channel-x selection", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CHSEL15", + "description": "Channel-x selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CHSEL14", + "description": "Channel-x selection", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CHSEL13", + "description": "Channel-x selection", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CHSEL12", + "description": "Channel-x selection", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CHSEL11", + "description": "Channel-x selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHSEL10", + "description": "Channel-x selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CHSEL9", + "description": "Channel-x selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CHSEL8", + "description": "Channel-x selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CHSEL7", + "description": "Channel-x selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CHSEL6", + "description": "Channel-x selection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CHSEL5", + "description": "Channel-x selection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHSEL4", + "description": "Channel-x selection", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CHSEL3", + "description": "Channel-x selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CHSEL2", + "description": "Channel-x selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CHSEL1", + "description": "Channel-x selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CHSEL0", + "description": "Channel-x selection", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Converted data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Common configuration register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VBATEN", + "description": "VBAT enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TSEN", + "description": "Temperature sensor enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "VREFEN", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UE", + "description": "USART enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "UESM", + "description": "USART enable in Stop mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "Interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Receiver wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MME", + "description": "Mute mode enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CMIE", + "description": "Character match interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DEDT", + "description": "Driver Enable deassertion time", + "bitOffset": "16", + "bitWidth": "5" + }, + { + "name": "DEAT", + "description": "Driver Enable assertion time", + "bitOffset": "21", + "bitWidth": "5" + }, + { + "name": "RTOIE", + "description": "Receiver timeout interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "EOBIE", + "description": "End of Block interrupt enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "M1", + "description": "Word length", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD4", + "description": "Address of the USART node", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "ADD0", + "description": "Address of the USART node", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "RTOEN", + "description": "Receiver timeout enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ABRMOD", + "description": "Auto baud rate mode", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ABREN", + "description": "Auto baud rate enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MSBFIRST", + "description": "Most significant bit first", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DATAINV", + "description": "Binary data inversion", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TXINV", + "description": "TX pin active level inversion", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "RXINV", + "description": "RX pin active level inversion", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWAP", + "description": "Swap TX/RX pins", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "LIN break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADDM7", + "description": "7-bit Address Detection/4-bit Address Detection", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "WUFIE", + "description": "Wakeup from Stop mode interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WUS", + "description": "Wakeup from Stop mode interrupt flag selection", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "SCARCNT", + "description": "Smartcard auto-retry count", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "DEP", + "description": "Driver enable polarity selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DEM", + "description": "Driver enable mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DDRE", + "description": "DMA Disable on Reception Error", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OVRDIS", + "description": "Overrun Disable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RTOR", + "displayName": "RTOR", + "description": "Receiver timeout register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BLEN", + "description": "Block Length", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "RTO", + "description": "Receiver timeout value", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "RQR", + "displayName": "RQR", + "description": "Request register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TXFRQ", + "description": "Transmit data flush request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXFRQ", + "description": "Receive data flush request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMRQ", + "description": "Mute mode request", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SBKRQ", + "description": "Send break request", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ABRRQ", + "description": "Auto baud rate request", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt & status register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00C0", + "fields": [ + { + "name": "REACK", + "description": "Receive enable acknowledge flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEACK", + "description": "Transmit enable acknowledge flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "WUF", + "description": "Wakeup from Stop mode flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup from Mute mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SBKF", + "description": "Send break flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CMF", + "description": "Character match flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Busy flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ABRF", + "description": "Auto baud rate flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ABRE", + "description": "Auto baud rate error", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "EOBF", + "description": "End of block flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RTOF", + "description": "Receiver timeout", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSIF", + "description": "CTS interrupt flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBDF", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLE", + "description": "Idle line detected", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "WUCF", + "description": "Wakeup from Stop mode clear flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CMCF", + "description": "Character match clear flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EOBCF", + "description": "End of timeout clear flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RTOCF", + "description": "Receiver timeout clear flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTSCF", + "description": "CTS clear flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBDCF", + "description": "LIN break detection clear flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCCF", + "description": "Transmission complete clear flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDLECF", + "description": "Idle line detected clear flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ORECF", + "description": "Overrun error clear flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NCF", + "description": "Noise detected clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FECF", + "description": "Framing error clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PECF", + "description": "Parity error clear flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "RDR", + "displayName": "RDR", + "description": "Receive data register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RDR", + "description": "Receive data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TDR", + "displayName": "TDR", + "description": "Transmit data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDR", + "description": "Transmit data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + } + ] + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "28" + } + ] + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3_4", + "description": "USART3 and USART4 global interrupt", + "value": "29" + } + ] + }, + { + "name": "USART4", + "derivedFrom": "USART1", + "baseAddress": "0x40004C00" + }, + { + "name": "COMP", + "description": "Comparator", + "groupName": "COMP", + "baseAddress": "0x4001001C", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x5", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC_COMP", + "description": "ADC and comparator interrupts", + "value": "12" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "Control and status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COMP1EN", + "description": "Comparator 1 enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1_INP_DAC", + "description": "COMP1_INP_DAC", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1MODE", + "description": "Comparator 1 mode", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1INSEL", + "description": "Comparator 1 inverting input selection", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1OUTSEL", + "description": "Comparator 1 output selection", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP1POL", + "description": "Comparator 1 output polarity", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP1HYST", + "description": "Comparator 1 hysteresis", + "bitOffset": "12", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP1OUT", + "description": "Comparator 1 output", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP1LOCK", + "description": "Comparator 1 lock", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2EN", + "description": "Comparator 2 enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2MODE", + "description": "Comparator 2 mode", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2INSEL", + "description": "Comparator 2 inverting input selection", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "WNDWEN", + "description": "Window mode enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2OUTSEL", + "description": "Comparator 2 output selection", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "COMP2POL", + "description": "Comparator 2 output polarity", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COMP2HYST", + "description": "Comparator 2 hysteresis", + "bitOffset": "28", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COMP2OUT", + "description": "Comparator 2 output", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "COMP2LOCK", + "description": "Comparator 2 lock", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC interrupts", + "value": "2" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REFCKON", + "description": "RTC_REFIN reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BYPSHAD", + "description": "Bypass the shadow registers", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSE", + "description": "Timestamp enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "COSEL", + "description": "Calibration output selection", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "RTC_TAMP1 detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "RTC_TAMP2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + }, + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format.", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format.", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADD1S", + "description": "Reserved", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Timestamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format.", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format.", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format.", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format.", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format.", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format.", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Timestamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Time-stamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALP", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALW16", + "description": "Reserved", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PC15MODE", + "description": "PC15 mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PC15VALUE", + "description": "PC15 value", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PC14MODE", + "description": "PC14 mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PC14VALUE", + "description": "PC14 value", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PC13MODE", + "description": "PC13 mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PC13VALUE", + "description": "RTC_ALARM output type/PC13 value", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TAMP_PUDIS", + "description": "RTC_TAMPx pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMP_PRCH", + "description": "RTC_TAMPx precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPFLT", + "description": "RTC_TAMPx filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMP2_TRG", + "description": "Active level for RTC_TAMP2 input", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "RTC_TAMP2 input detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for RTC_TAMP1 input", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMP1E", + "description": "RTC_TAMP1 input detection enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "TIM15", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM15", + "description": "TIM15 global interrupt", + "value": "20" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM16", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM16", + "description": "TIM16 global interrupt", + "value": "21" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM17", + "derivedFrom": "TIM16", + "baseAddress": "0x40014800", + "interrupts": [ + { + "name": "TIM17", + "description": "TIM17 global interrupt", + "value": "22" + } + ] + }, + { + "name": "TSC", + "description": "Touch sensing controller", + "groupName": "TSC", + "baseAddress": "0x40024000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TSC", + "description": "Touch sensing interrupt", + "value": "8" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTPH", + "description": "Charge transfer pulse high", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "CTPL", + "description": "Charge transfer pulse low", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SSD", + "description": "Spread spectrum deviation", + "bitOffset": "17", + "bitWidth": "7" + }, + { + "name": "SSE", + "description": "Spread spectrum enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SSPSC", + "description": "Spread spectrum prescaler", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PGPSC", + "description": "Pulse generator prescaler", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MCV", + "description": "Max count value", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "IODEF", + "description": "I/O Default mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SYNCPOL", + "description": "Synchronization pin polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "AM", + "description": "Acquisition mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start a new acquisition", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSCE", + "description": "Touch sensing controller enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCEIE", + "description": "Max count error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOAIE", + "description": "End of acquisition interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCEIC", + "description": "Max count error interrupt clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOAIC", + "description": "End of acquisition interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCEF", + "description": "Max count error flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EOAF", + "description": "End of acquisition flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOHCR", + "displayName": "IOHCR", + "description": "I/O hysteresis control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 Schmitt trigger hysteresis mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 Schmitt trigger hysteresis mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 Schmitt trigger hysteresis mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 Schmitt trigger hysteresis mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOASCR", + "displayName": "IOASCR", + "description": "I/O analog switch control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 analog switch enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 analog switch enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 analog switch enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 analog switch enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 analog switch enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 analog switch enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 analog switch enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 analog switch enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 analog switch enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 analog switch enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 analog switch enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 analog switch enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 analog switch enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 analog switch enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 analog switch enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 analog switch enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 analog switch enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 analog switch enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 analog switch enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 analog switch enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 analog switch enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 analog switch enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 analog switch enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 analog switch enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOSCR", + "displayName": "IOSCR", + "description": "I/O sampling control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 sampling mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 sampling mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 sampling mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 sampling mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 sampling mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 sampling mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 sampling mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 sampling mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 sampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 sampling mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 sampling mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 sampling mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 sampling mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 sampling mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 sampling mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 sampling mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 sampling mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 sampling mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 sampling mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 sampling mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 sampling mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 sampling mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 sampling mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 sampling mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOCCR", + "displayName": "IOCCR", + "description": "I/O channel control register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G6_IO4", + "description": "G6_IO4 channel mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "G6_IO3", + "description": "G6_IO3 channel mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "G6_IO2", + "description": "G6_IO2 channel mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "G6_IO1", + "description": "G6_IO1 channel mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "G5_IO4", + "description": "G5_IO4 channel mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "G5_IO3", + "description": "G5_IO3 channel mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "G5_IO2", + "description": "G5_IO2 channel mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "G5_IO1", + "description": "G5_IO1 channel mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "G4_IO4", + "description": "G4_IO4 channel mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "G4_IO3", + "description": "G4_IO3 channel mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "G4_IO2", + "description": "G4_IO2 channel mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "G4_IO1", + "description": "G4_IO1 channel mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "G3_IO4", + "description": "G3_IO4 channel mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "G3_IO3", + "description": "G3_IO3 channel mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "G3_IO2", + "description": "G3_IO2 channel mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "G3_IO1", + "description": "G3_IO1 channel mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "G2_IO4", + "description": "G2_IO4 channel mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "G2_IO3", + "description": "G2_IO3 channel mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "G2_IO2", + "description": "G2_IO2 channel mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "G2_IO1", + "description": "G2_IO1 channel mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "G1_IO4", + "description": "G1_IO4 channel mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "G1_IO3", + "description": "G1_IO3 channel mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "G1_IO2", + "description": "G1_IO2 channel mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "G1_IO1", + "description": "G1_IO1 channel mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IOGCSR", + "displayName": "IOGCSR", + "description": "I/O group control status register", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "G8S", + "description": "Analog I/O group x status", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G7S", + "description": "Analog I/O group x status", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G6S", + "description": "Analog I/O group x status", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G5S", + "description": "Analog I/O group x status", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G4S", + "description": "Analog I/O group x status", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G3S", + "description": "Analog I/O group x status", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G2S", + "description": "Analog I/O group x status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G1S", + "description": "Analog I/O group x status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "G8E", + "description": "Analog I/O group x enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G7E", + "description": "Analog I/O group x enable", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G6E", + "description": "Analog I/O group x enable", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G5E", + "description": "Analog I/O group x enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G4E", + "description": "Analog I/O group x enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G3E", + "description": "Analog I/O group x enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G2E", + "description": "Analog I/O group x enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "G1E", + "description": "Analog I/O group x enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "IOG1CR", + "displayName": "IOG1CR", + "description": "I/O group x counter register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG2CR", + "displayName": "IOG2CR", + "description": "I/O group x counter register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG3CR", + "displayName": "IOG3CR", + "description": "I/O group x counter register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG4CR", + "displayName": "IOG4CR", + "description": "I/O group x counter register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG5CR", + "displayName": "IOG5CR", + "description": "I/O group x counter register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "IOG6CR", + "displayName": "IOG6CR", + "description": "I/O group x counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "14" + } + ] + } + ] + }, + { + "name": "CEC", + "description": "HDMI-CEC controller", + "groupName": "CEC", + "baseAddress": "0x40007800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CEC_CAN", + "description": "CEC and CAN global interrupt", + "value": "30" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXEOM", + "description": "Tx End Of Message", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TXSOM", + "description": "Tx start of message", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CECEN", + "description": "CEC Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LBPEGEN", + "description": "Generate Error-Bit on Long Bit Period Error", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BREGEN", + "description": "Generate error-bit on bit rising error", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BRESTP", + "description": "Rx-stop on bit rising error", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RXTOL", + "description": "Rx-Tolerance", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SFT", + "description": "Signal Free Time", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "LSTN", + "description": "Listen mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OAR", + "description": "Own Address", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TXDR", + "displayName": "TXDR", + "description": "Tx data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXD", + "description": "Tx Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RXDR", + "displayName": "RXDR", + "description": "Rx Data Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDR", + "description": "CEC Rx Data Register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and Status Register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXACKE", + "description": "Tx-Missing acknowledge error", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Tx-Error", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXUDR", + "description": "Tx-Buffer Underrun", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXEND", + "description": "End of Transmission", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXBR", + "description": "Tx-Byte Request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ARBLST", + "description": "Arbitration Lost", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXACKE", + "description": "Rx-Missing Acknowledge", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBPE", + "description": "Rx-Long Bit Period Error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SBPE", + "description": "Rx-Short Bit period error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BRE", + "description": "Rx-Bit rising error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RXOVR", + "description": "Rx-Overrun", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RXEND", + "description": "End Of Reception", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXBR", + "description": "Rx-Byte Received", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TXACKIE", + "description": "Tx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TXERRIE", + "description": "Tx-Error Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXUDRIE", + "description": "Tx-Underrun interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TXENDIE", + "description": "Tx-End of message interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TXBRIE", + "description": "Tx-Byte Request Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ARBLSTIE", + "description": "Arbitration Lost Interrupt Enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXACKIE", + "description": "Rx-Missing Acknowledge Error Interrupt Enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBPEIE", + "description": "Long Bit Period Error Interrupt Enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SBPEIE", + "description": "Short Bit Period Error Interrupt Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BREIE", + "description": "Bit Rising Error Interrupt Enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RXOVRIE", + "description": "Rx-Buffer Overrun Interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RXENDIE", + "description": "End Of Reception Interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXBRIE", + "description": "Rx-Byte Received Interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "Flash", + "description": "Flash", + "groupName": "Flash", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "3" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "LATENCY", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "PRFTBE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "PRFTBS", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FKEYR", + "description": "Flash Key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEYR", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Flash status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRT", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Flash control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "FORCE_OPTLOAD", + "description": "Force option byte loading", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFF2", + "fields": [ + { + "name": "Data1", + "description": "Data1", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "VDDA_MONITOR", + "description": "VDDA_MONITOR", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BOOT1", + "description": "BOOT1", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LEVEL2_PROT", + "description": "Level 2 protection status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LEVEL1_PROT", + "description": "Level 1 protection status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DBGMCU", + "description": "Debug support", + "groupName": "DBGMCU", + "baseAddress": "0x40015800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "MCU Device ID Code Register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "Device Identifier", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DIV_ID", + "description": "Division Identifier", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "REV_ID", + "description": "Revision Identifier", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Debug MCU Configuration Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_STOP", + "description": "Debug Stop Mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "Debug Standby Mode", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "APBLFZ", + "displayName": "APBLFZ", + "description": "APB Low Freeze Register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER2_STOP", + "description": "Debug Timer 2 stopped when Core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER3_STOP", + "description": "Debug Timer 3 stopped when Core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER6_STOP", + "description": "Debug Timer 6 stopped when Core is halted", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER14_STOP", + "description": "Debug Timer 14 stopped when Core is halted", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_RTC_STOP", + "description": "Debug RTC stopped when Core is halted", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "Debug Window Wachdog stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDG_STOP", + "description": "Debug Independent Wachdog stopped when Core is halted", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "I2C1_SMBUS_TIMEOUT", + "description": "SMBUS timeout mode stopped when Core is halted", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APBHFZ", + "displayName": "APBHFZ", + "description": "APB High Freeze Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_TIMER1_STOP", + "description": "Debug Timer 1 stopped when Core is halted", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER15_STO", + "description": "Debug Timer 15 stopped when Core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER16_STO", + "description": "Debug Timer 16 stopped when Core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIMER17_STO", + "description": "Debug Timer 17 stopped when Core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "USB", + "description": "Universal serial bus full-speed device interface", + "groupName": "USB", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USB", + "description": "USB global interrupt", + "value": "31" + } + ], + "registers": [ + { + "name": "EP0R", + "displayName": "EP0R", + "description": "Endpoint 0 register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP1R", + "displayName": "EP1R", + "description": "Endpoint 1 register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP2R", + "displayName": "EP2R", + "description": "Endpoint 2 register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP3R", + "displayName": "EP3R", + "description": "Endpoint 3 register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP4R", + "displayName": "EP4R", + "description": "Endpoint 4 register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP5R", + "displayName": "EP5R", + "description": "Endpoint 5 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP6R", + "displayName": "EP6R", + "description": "Endpoint 6 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP7R", + "displayName": "EP7R", + "description": "Endpoint 7 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNTR", + "displayName": "CNTR", + "description": "Control register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000003", + "fields": [ + { + "name": "FRES", + "description": "Force USB Reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDWN", + "description": "Power down", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPMODE", + "description": "Low-power mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSUSP", + "description": "Force suspend", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RESUME", + "description": "Resume request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "L1RESUME", + "description": "LPM L1 Resume request", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "L1REQM", + "description": "LPM L1 state request interrupt mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ESOFM", + "description": "Expected start of frame interrupt mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOFM", + "description": "Start of frame interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESETM", + "description": "USB reset interrupt mask", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSPM", + "description": "Suspend mode interrupt mask", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUPM", + "description": "Wakeup interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRM", + "description": "Error interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVRM", + "description": "Packet memory area over / underrun interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTRM", + "description": "Correct transfer interrupt mask", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ISTR", + "displayName": "ISTR", + "description": "Interrupt status register", + "addressOffset": "0x44", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EP_ID", + "description": "Endpoint Identifier", + "bitOffset": "0", + "bitWidth": "4", + "access": "read-only" + }, + { + "name": "DIR", + "description": "Direction of transaction", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "L1REQ", + "description": "LPM L1 state request", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESOF", + "description": "Expected start frame", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RESET", + "description": "Reset request", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SUSP", + "description": "Suspend mode request", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUP", + "description": "Wakeup", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERR", + "description": "Error", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PMAOVR", + "description": "Packet memory area over / underrun", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTR", + "description": "Correct transfer", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FNR", + "displayName": "FNR", + "description": "Frame number register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FN", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "LSOF", + "description": "Lost SOF", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "LCK", + "description": "Locked", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "RXDM", + "description": "Receive data - line status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXDP", + "description": "Receive data + line status", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DADDR", + "displayName": "DADDR", + "description": "Device address", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Device address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "EF", + "description": "Enable function", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "BTABLE", + "displayName": "BTABLE", + "description": "Buffer table address", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BTABLE", + "description": "Buffer table", + "bitOffset": "3", + "bitWidth": "13" + } + ] + }, + { + "name": "LPMCSR", + "displayName": "LPMCSR", + "description": "LPM control and status register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "LPMEN", + "description": "LPM support enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPMACK", + "description": "LPM Token acknowledge enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "REMWAKE", + "description": "BRemoteWake value", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BESL", + "description": "BESL value", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-only" + } + ] + }, + { + "name": "BCDR", + "displayName": "BCDR", + "description": "Battery charging detector", + "addressOffset": "0x58", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "BCDEN", + "description": "Battery charging detector (BCD) enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDEN", + "description": "Data contact detection (DCD) mode enable", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PDEN", + "description": "Primary detection (PD) mode enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDEN", + "description": "Secondary detection (SD) mode enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCDET", + "description": "Data contact detection (DCD) status", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PDET", + "description": "Primary detection (PD) status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SDET", + "description": "Secondary detection (SD) status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PS2DET", + "description": "DM pull-up detection status", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DPPU", + "description": "DP pull-up control", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "CRS", + "description": "Clock recovery system", + "groupName": "CRS", + "baseAddress": "0x40006C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC_CRS", + "description": "RCC and CRS global interrupts", + "value": "4" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "TRIM", + "description": "HSI48 oscillator smooth trimming", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "SWSYNC", + "description": "Generate software SYNC event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AUTOTRIMEN", + "description": "Automatic trimming enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Frequency error counter enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ESYNCIE", + "description": "Expected SYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Synchronization or trimming error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCWARNIE", + "description": "SYNC warning interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SYNCOKIE", + "description": "SYNC event OK interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2022BB7F", + "fields": [ + { + "name": "SYNCPOL", + "description": "SYNC polarity selection", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SYNCSRC", + "description": "SYNC signal source selection", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "SYNCDIV", + "description": "SYNC divider", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "FELIM", + "description": "Frequency error limit", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "RELOAD", + "description": "Counter reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt and status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FECAP", + "description": "Frequency error capture", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FEDIR", + "description": "Frequency error direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TRIMOVF", + "description": "Trimming overflow or underflow", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SYNCMISS", + "description": "SYNC missed", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SYNCERR", + "description": "SYNC error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ESYNCF", + "description": "Expected SYNC flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERRF", + "description": "Error flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCWARNF", + "description": "SYNC warning flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SYNCOKF", + "description": "SYNC event OK flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ESYNCC", + "description": "Expected SYNC clear flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERRC", + "description": "Error clear flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SYNCWARNC", + "description": "SYNC warning clear flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SYNCOKC", + "description": "SYNC event OK clear flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": 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+ { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FS1R", + "displayName": "CAN_FS1R", + "description": "CAN_FS1R", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/adc.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/adc.c new file mode 100644 index 0000000000..602ba04467 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/adc.c @@ -0,0 +1,311 @@ +/* + * STM32- ADC(Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.ier= cm_object_get_child_by_name(obj, "IER"); +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.cfgr1= cm_object_get_child_by_name(obj, "CFGR1"); +state->u.f0.reg.cfgr2= cm_object_get_child_by_name(obj, "CFGR2"); +state->u.f0.reg.smpr= cm_object_get_child_by_name(obj, "SMPR"); +state->u.f0.reg.tr= cm_object_get_child_by_name(obj, "TR"); +state->u.f0.reg.chselr= cm_object_get_child_by_name(obj, "CHSELR"); +state->u.f0.reg.dr= cm_object_get_child_by_name(obj, "DR"); +state->u.f0.reg.ccr= cm_object_get_child_by_name(obj, "CCR"); +// ISRbitfields. +state->u.f0.fld.isr.adrdy= cm_object_get_child_by_name(state->u.f0.reg.isr, "ADRDY"); +state->u.f0.fld.isr.eosmp= cm_object_get_child_by_name(state->u.f0.reg.isr, "EOSMP"); +state->u.f0.fld.isr.eoc= cm_object_get_child_by_name(state->u.f0.reg.isr, "EOC"); +state->u.f0.fld.isr.eos= cm_object_get_child_by_name(state->u.f0.reg.isr, "EOS"); +state->u.f0.fld.isr.ovr= cm_object_get_child_by_name(state->u.f0.reg.isr, "OVR"); +state->u.f0.fld.isr.awd= cm_object_get_child_by_name(state->u.f0.reg.isr, "AWD"); +// IERbitfields. +state->u.f0.fld.ier.adrdyie= cm_object_get_child_by_name(state->u.f0.reg.ier, "ADRDYIE"); +state->u.f0.fld.ier.eosmpie= cm_object_get_child_by_name(state->u.f0.reg.ier, "EOSMPIE"); +state->u.f0.fld.ier.eocie= cm_object_get_child_by_name(state->u.f0.reg.ier, "EOCIE"); +state->u.f0.fld.ier.eosie= cm_object_get_child_by_name(state->u.f0.reg.ier, "EOSIE"); +state->u.f0.fld.ier.ovrie= cm_object_get_child_by_name(state->u.f0.reg.ier, "OVRIE"); +state->u.f0.fld.ier.awdie= cm_object_get_child_by_name(state->u.f0.reg.ier, "AWDIE"); +// CRbitfields. +state->u.f0.fld.cr.aden= cm_object_get_child_by_name(state->u.f0.reg.cr, "ADEN"); +state->u.f0.fld.cr.addis= cm_object_get_child_by_name(state->u.f0.reg.cr, "ADDIS"); +state->u.f0.fld.cr.adstart= cm_object_get_child_by_name(state->u.f0.reg.cr, "ADSTART"); +state->u.f0.fld.cr.adstp= cm_object_get_child_by_name(state->u.f0.reg.cr, "ADSTP"); +state->u.f0.fld.cr.adcal= cm_object_get_child_by_name(state->u.f0.reg.cr, "ADCAL"); +// CFGR1bitfields. +state->u.f0.fld.cfgr1.dmaen= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "DMAEN"); +state->u.f0.fld.cfgr1.dmacfg= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "DMACFG"); +state->u.f0.fld.cfgr1.scandir= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "SCANDIR"); +state->u.f0.fld.cfgr1.res= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "RES"); +state->u.f0.fld.cfgr1.align= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "ALIGN"); +state->u.f0.fld.cfgr1.extsel= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "EXTSEL"); +state->u.f0.fld.cfgr1.exten= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "EXTEN"); +state->u.f0.fld.cfgr1.ovrmod= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "OVRMOD"); +state->u.f0.fld.cfgr1.cont= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "CONT"); +state->u.f0.fld.cfgr1.autdly= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AUTDLY"); +state->u.f0.fld.cfgr1.autoff= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AUTOFF"); +state->u.f0.fld.cfgr1.discen= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "DISCEN"); +state->u.f0.fld.cfgr1.awdsgl= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AWDSGL"); +state->u.f0.fld.cfgr1.awden= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AWDEN"); +state->u.f0.fld.cfgr1.awdch= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "AWDCH"); +// CFGR2bitfields. +state->u.f0.fld.cfgr2.jitoff_d2= cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "JITOFF_D2"); +state->u.f0.fld.cfgr2.jitoff_d4= cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "JITOFF_D4"); +// SMPRbitfields. +state->u.f0.fld.smpr.smpr= cm_object_get_child_by_name(state->u.f0.reg.smpr, "SMPR"); +// TRbitfields. +state->u.f0.fld.tr.lt= cm_object_get_child_by_name(state->u.f0.reg.tr, "LT"); +state->u.f0.fld.tr.ht= cm_object_get_child_by_name(state->u.f0.reg.tr, "HT"); +// CHSELRbitfields. +state->u.f0.fld.chselr.chsel0= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL0"); +state->u.f0.fld.chselr.chsel1= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL1"); +state->u.f0.fld.chselr.chsel2= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL2"); +state->u.f0.fld.chselr.chsel3= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL3"); +state->u.f0.fld.chselr.chsel4= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL4"); +state->u.f0.fld.chselr.chsel5= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL5"); +state->u.f0.fld.chselr.chsel6= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL6"); +state->u.f0.fld.chselr.chsel7= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL7"); +state->u.f0.fld.chselr.chsel8= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL8"); +state->u.f0.fld.chselr.chsel9= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL9"); +state->u.f0.fld.chselr.chsel10= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL10"); +state->u.f0.fld.chselr.chsel11= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL11"); +state->u.f0.fld.chselr.chsel12= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL12"); +state->u.f0.fld.chselr.chsel13= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL13"); +state->u.f0.fld.chselr.chsel14= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL14"); +state->u.f0.fld.chselr.chsel15= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL15"); +state->u.f0.fld.chselr.chsel16= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL16"); +state->u.f0.fld.chselr.chsel17= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL17"); +state->u.f0.fld.chselr.chsel18= cm_object_get_child_by_name(state->u.f0.reg.chselr, "CHSEL18"); +// DRbitfields. +state->u.f0.fld.dr.data= cm_object_get_child_by_name(state->u.f0.reg.dr, "DATA"); +// CCRbitfields. +state->u.f0.fld.ccr.vrefen= cm_object_get_child_by_name(state->u.f0.reg.ccr, "VREFEN"); +state->u.f0.fld.ccr.tsen= cm_object_get_child_by_name(state->u.f0.reg.ccr, "TSEN"); +state->u.f0.fld.ccr.vbaten= cm_object_get_child_by_name(state->u.f0.reg.ccr, "VBATEN"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADCEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/adc.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/adc.h new file mode 100644 index 0000000000..e406979976 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/adc.h @@ -0,0 +1,137 @@ +/* + * STM32- ADC(Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADCDEVICE_PATH_STM32"ADC" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADCTYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0ADC(Analog-to-digital converter) registers. + struct { +Object *isr; // 0x0(Interrupt and status register) +Object *ier; // 0x4(Interrupt enable register) +Object *cr; // 0x8(Control register) +Object *cfgr1; // 0xC(Configuration register 1) +Object *cfgr2; // 0x10(Configuration register 2) +Object *smpr; // 0x14(Sampling time register) +Object *tr; // 0x20(Watchdog threshold register) +Object *chselr; // 0x28(Channel selection register) +Object *dr; // 0x40(Data register) +Object *ccr; // 0x308(Common configuration register) +} reg; + + struct { +// ISR(Interrupt and status register) bitfields. + struct { +Object *adrdy; // [0:0] ADC readyObject *eosmp; // [1:1] End of sampling flagObject *eoc; // [2:2] End of conversion flagObject *eos; // [3:3] End of sequence flagObject *ovr; // [4:4] ADC overrunObject *awd; // [7:7] Analog watchdog flag} isr; +// IER(Interrupt enable register) bitfields. + struct { +Object *adrdyie; // [0:0] ADC ready interrupt enableObject *eosmpie; // [1:1] End of sampling flag interrupt enableObject *eocie; // [2:2] End of conversion interrupt enableObject *eosie; // [3:3] End of conversion sequence interrupt enableObject *ovrie; // [4:4] Overrun interrupt enableObject *awdie; // [7:7] Analog watchdog interrupt enable} ier; +// CR(Control register) bitfields. + struct { +Object *aden; // [0:0] ADC enable commandObject *addis; // [1:1] ADC disable commandObject *adstart; // [2:2] ADC start conversion commandObject *adstp; // [4:4] ADC stop conversion commandObject *adcal; // [31:31] ADC calibration} cr; +// CFGR1(Configuration register 1) bitfields. + struct { +Object *dmaen; // [0:0] Direct memory access enableObject *dmacfg; // [1:1] Direct memery access configurationObject *scandir; // [2:2] Scan sequence directionObject *res; // [3:4] Data resolutionObject *align; // [5:5] Data alignmentObject *extsel; // [6:8] External trigger selectionObject *exten; // [10:11] External trigger enable and polarity selectionObject *ovrmod; // [12:12] Overrun management modeObject *cont; // [13:13] Single / continuous conversion modeObject *autdly; // [14:14] Auto-delayed conversion modeObject *autoff; // [15:15] Auto-off modeObject *discen; // [16:16] Discontinuous modeObject *awdsgl; // [22:22] Enable the watchdog on a single channel or on all channelsObject *awden; // [23:23] Analog watchdog enableObject *awdch; // [26:30] Analog watchdog channel selection} cfgr1; +// CFGR2(Configuration register 2) bitfields. + struct { +Object *jitoff_d2; // [30:30] JITOFF_D2Object *jitoff_d4; // [31:31] JITOFF_D4} cfgr2; +// SMPR(Sampling time register) bitfields. + struct { +Object *smpr; // [0:2] Sampling time selection} smpr; +// TR(Watchdog threshold register) bitfields. + struct { +Object *lt; // [0:11] Analog watchdog lower thresholdObject *ht; // [16:27] Analog watchdog higher threshold} tr; +// CHSELR(Channel selection register) bitfields. + struct { +Object *chsel0; // [0:0] Channel-x selectionObject *chsel1; // [1:1] Channel-x selectionObject *chsel2; // [2:2] Channel-x selectionObject *chsel3; // [3:3] Channel-x selectionObject *chsel4; // [4:4] Channel-x selectionObject *chsel5; // [5:5] Channel-x selectionObject *chsel6; // [6:6] Channel-x selectionObject *chsel7; // [7:7] Channel-x selectionObject *chsel8; // [8:8] Channel-x selectionObject *chsel9; // [9:9] Channel-x selectionObject *chsel10; // [10:10] Channel-x selectionObject *chsel11; // [11:11] Channel-x selectionObject *chsel12; // [12:12] Channel-x selectionObject *chsel13; // [13:13] Channel-x selectionObject *chsel14; // [14:14] Channel-x selectionObject *chsel15; // [15:15] Channel-x selectionObject *chsel16; // [16:16] Channel-x selectionObject *chsel17; // [17:17] Channel-x selectionObject *chsel18; // [18:18] Channel-x selection} chselr; +// DR(Data register) bitfields. + struct { +Object *data; // [0:15] Converted data} dr; +// CCR(Common configuration register) bitfields. + struct { +Object *vrefen; // [22:22] Temperature sensor and VREFINT enableObject *tsen; // [23:23] Temperature sensor enableObject *vbaten; // [24:24] VBAT enable} ccr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/can.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/can.c new file mode 100644 index 0000000000..bd7c0bfb7f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/can.c @@ -0,0 +1,2468 @@ +/* + * STM32- CAN(Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_can_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.can_mcr= cm_object_get_child_by_name(obj, "CAN_MCR"); +state->u.f0.reg.can_msr= cm_object_get_child_by_name(obj, "CAN_MSR"); +state->u.f0.reg.can_tsr= cm_object_get_child_by_name(obj, "CAN_TSR"); +state->u.f0.reg.can_rf0r= cm_object_get_child_by_name(obj, "CAN_RF0R"); +state->u.f0.reg.can_rf1r= cm_object_get_child_by_name(obj, "CAN_RF1R"); +state->u.f0.reg.can_ier= cm_object_get_child_by_name(obj, "CAN_IER"); +state->u.f0.reg.can_esr= cm_object_get_child_by_name(obj, "CAN_ESR"); +state->u.f0.reg.can_btr= cm_object_get_child_by_name(obj, "CAN_BTR"); +state->u.f0.reg.can_ti0r= cm_object_get_child_by_name(obj, "CAN_TI0R"); +state->u.f0.reg.can_tdt0r= cm_object_get_child_by_name(obj, "CAN_TDT0R"); +state->u.f0.reg.can_tdl0r= cm_object_get_child_by_name(obj, "CAN_TDL0R"); +state->u.f0.reg.can_tdh0r= cm_object_get_child_by_name(obj, "CAN_TDH0R"); +state->u.f0.reg.can_ti1r= cm_object_get_child_by_name(obj, "CAN_TI1R"); +state->u.f0.reg.can_tdt1r= cm_object_get_child_by_name(obj, "CAN_TDT1R"); +state->u.f0.reg.can_tdl1r= cm_object_get_child_by_name(obj, "CAN_TDL1R"); +state->u.f0.reg.can_tdh1r= cm_object_get_child_by_name(obj, "CAN_TDH1R"); +state->u.f0.reg.can_ti2r= cm_object_get_child_by_name(obj, "CAN_TI2R"); +state->u.f0.reg.can_tdt2r= cm_object_get_child_by_name(obj, "CAN_TDT2R"); +state->u.f0.reg.can_tdl2r= cm_object_get_child_by_name(obj, "CAN_TDL2R"); +state->u.f0.reg.can_tdh2r= cm_object_get_child_by_name(obj, "CAN_TDH2R"); +state->u.f0.reg.can_ri0r= cm_object_get_child_by_name(obj, "CAN_RI0R"); +state->u.f0.reg.can_rdt0r= cm_object_get_child_by_name(obj, "CAN_RDT0R"); +state->u.f0.reg.can_rdl0r= cm_object_get_child_by_name(obj, "CAN_RDL0R"); +state->u.f0.reg.can_rdh0r= cm_object_get_child_by_name(obj, "CAN_RDH0R"); +state->u.f0.reg.can_ri1r= cm_object_get_child_by_name(obj, "CAN_RI1R"); +state->u.f0.reg.can_rdt1r= cm_object_get_child_by_name(obj, "CAN_RDT1R"); +state->u.f0.reg.can_rdl1r= cm_object_get_child_by_name(obj, "CAN_RDL1R"); +state->u.f0.reg.can_rdh1r= cm_object_get_child_by_name(obj, "CAN_RDH1R"); +state->u.f0.reg.can_fmr= cm_object_get_child_by_name(obj, "CAN_FMR"); +state->u.f0.reg.can_fm1r= cm_object_get_child_by_name(obj, "CAN_FM1R"); +state->u.f0.reg.can_fs1r= cm_object_get_child_by_name(obj, "CAN_FS1R"); +state->u.f0.reg.can_ffa1r= cm_object_get_child_by_name(obj, "CAN_FFA1R"); +state->u.f0.reg.can_fa1r= cm_object_get_child_by_name(obj, "CAN_FA1R"); +state->u.f0.reg.f0r1= cm_object_get_child_by_name(obj, "F0R1"); +state->u.f0.reg.f0r2= cm_object_get_child_by_name(obj, "F0R2"); +state->u.f0.reg.f1r1= cm_object_get_child_by_name(obj, "F1R1"); +state->u.f0.reg.f1r2= cm_object_get_child_by_name(obj, "F1R2"); +state->u.f0.reg.f2r1= cm_object_get_child_by_name(obj, "F2R1"); +state->u.f0.reg.f2r2= cm_object_get_child_by_name(obj, "F2R2"); +state->u.f0.reg.f3r1= cm_object_get_child_by_name(obj, "F3R1"); +state->u.f0.reg.f3r2= cm_object_get_child_by_name(obj, "F3R2"); +state->u.f0.reg.f4r1= cm_object_get_child_by_name(obj, "F4R1"); +state->u.f0.reg.f4r2= cm_object_get_child_by_name(obj, "F4R2"); +state->u.f0.reg.f5r1= cm_object_get_child_by_name(obj, "F5R1"); +state->u.f0.reg.f5r2= cm_object_get_child_by_name(obj, "F5R2"); +state->u.f0.reg.f6r1= cm_object_get_child_by_name(obj, "F6R1"); +state->u.f0.reg.f6r2= cm_object_get_child_by_name(obj, "F6R2"); +state->u.f0.reg.f7r1= cm_object_get_child_by_name(obj, "F7R1"); +state->u.f0.reg.f7r2= cm_object_get_child_by_name(obj, "F7R2"); +state->u.f0.reg.f8r1= cm_object_get_child_by_name(obj, "F8R1"); +state->u.f0.reg.f8r2= cm_object_get_child_by_name(obj, "F8R2"); +state->u.f0.reg.f9r1= cm_object_get_child_by_name(obj, "F9R1"); +state->u.f0.reg.f9r2= cm_object_get_child_by_name(obj, "F9R2"); +state->u.f0.reg.f10r1= cm_object_get_child_by_name(obj, "F10R1"); +state->u.f0.reg.f10r2= cm_object_get_child_by_name(obj, "F10R2"); +state->u.f0.reg.f11r1= cm_object_get_child_by_name(obj, "F11R1"); +state->u.f0.reg.f11r2= cm_object_get_child_by_name(obj, "F11R2"); +state->u.f0.reg.f12r1= cm_object_get_child_by_name(obj, "F12R1"); +state->u.f0.reg.f12r2= cm_object_get_child_by_name(obj, "F12R2"); +state->u.f0.reg.f13r1= cm_object_get_child_by_name(obj, "F13R1"); +state->u.f0.reg.f13r2= cm_object_get_child_by_name(obj, "F13R2"); +state->u.f0.reg.f14r1= cm_object_get_child_by_name(obj, "F14R1"); +state->u.f0.reg.f14r2= cm_object_get_child_by_name(obj, "F14R2"); +state->u.f0.reg.f15r1= cm_object_get_child_by_name(obj, "F15R1"); +state->u.f0.reg.f15r2= cm_object_get_child_by_name(obj, "F15R2"); +state->u.f0.reg.f16r1= cm_object_get_child_by_name(obj, "F16R1"); +state->u.f0.reg.f16r2= cm_object_get_child_by_name(obj, "F16R2"); +state->u.f0.reg.f17r1= cm_object_get_child_by_name(obj, "F17R1"); +state->u.f0.reg.f17r2= cm_object_get_child_by_name(obj, "F17R2"); +state->u.f0.reg.f18r1= cm_object_get_child_by_name(obj, "F18R1"); +state->u.f0.reg.f18r2= cm_object_get_child_by_name(obj, "F18R2"); +state->u.f0.reg.f19r1= cm_object_get_child_by_name(obj, "F19R1"); +state->u.f0.reg.f19r2= cm_object_get_child_by_name(obj, "F19R2"); +state->u.f0.reg.f20r1= cm_object_get_child_by_name(obj, "F20R1"); +state->u.f0.reg.f20r2= cm_object_get_child_by_name(obj, "F20R2"); +state->u.f0.reg.f21r1= cm_object_get_child_by_name(obj, "F21R1"); +state->u.f0.reg.f21r2= cm_object_get_child_by_name(obj, "F21R2"); +state->u.f0.reg.f22r1= cm_object_get_child_by_name(obj, "F22R1"); +state->u.f0.reg.f22r2= cm_object_get_child_by_name(obj, "F22R2"); +state->u.f0.reg.f23r1= cm_object_get_child_by_name(obj, "F23R1"); +state->u.f0.reg.f23r2= cm_object_get_child_by_name(obj, "F23R2"); +state->u.f0.reg.f24r1= cm_object_get_child_by_name(obj, "F24R1"); +state->u.f0.reg.f24r2= cm_object_get_child_by_name(obj, "F24R2"); +state->u.f0.reg.f25r1= cm_object_get_child_by_name(obj, "F25R1"); +state->u.f0.reg.f25r2= cm_object_get_child_by_name(obj, "F25R2"); +state->u.f0.reg.f26r1= cm_object_get_child_by_name(obj, "F26R1"); +state->u.f0.reg.f26r2= cm_object_get_child_by_name(obj, "F26R2"); +state->u.f0.reg.f27r1= cm_object_get_child_by_name(obj, "F27R1"); +state->u.f0.reg.f27r2= cm_object_get_child_by_name(obj, "F27R2"); +// CAN_MCRbitfields. +state->u.f0.fld.can_mcr.inrq= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "INRQ"); +state->u.f0.fld.can_mcr.sleep= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "SLEEP"); +state->u.f0.fld.can_mcr.txfp= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "TXFP"); +state->u.f0.fld.can_mcr.rflm= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "RFLM"); +state->u.f0.fld.can_mcr.nart= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "NART"); +state->u.f0.fld.can_mcr.awum= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "AWUM"); +state->u.f0.fld.can_mcr.abom= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "ABOM"); +state->u.f0.fld.can_mcr.ttcm= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "TTCM"); +state->u.f0.fld.can_mcr.reset= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "RESET"); +state->u.f0.fld.can_mcr.dbf= cm_object_get_child_by_name(state->u.f0.reg.can_mcr, "DBF"); +// CAN_MSRbitfields. +state->u.f0.fld.can_msr.inak= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "INAK"); +state->u.f0.fld.can_msr.slak= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "SLAK"); +state->u.f0.fld.can_msr.erri= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "ERRI"); +state->u.f0.fld.can_msr.wkui= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "WKUI"); +state->u.f0.fld.can_msr.slaki= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "SLAKI"); +state->u.f0.fld.can_msr.txm= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "TXM"); +state->u.f0.fld.can_msr.rxm= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "RXM"); +state->u.f0.fld.can_msr.samp= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "SAMP"); +state->u.f0.fld.can_msr.rx= cm_object_get_child_by_name(state->u.f0.reg.can_msr, "RX"); +// CAN_TSRbitfields. +state->u.f0.fld.can_tsr.rqcp0= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "RQCP0"); +state->u.f0.fld.can_tsr.txok0= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TXOK0"); +state->u.f0.fld.can_tsr.alst0= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ALST0"); +state->u.f0.fld.can_tsr.terr0= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TERR0"); +state->u.f0.fld.can_tsr.abrq0= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ABRQ0"); +state->u.f0.fld.can_tsr.rqcp1= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "RQCP1"); +state->u.f0.fld.can_tsr.txok1= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TXOK1"); +state->u.f0.fld.can_tsr.alst1= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ALST1"); +state->u.f0.fld.can_tsr.terr1= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TERR1"); +state->u.f0.fld.can_tsr.abrq1= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ABRQ1"); +state->u.f0.fld.can_tsr.rqcp2= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "RQCP2"); +state->u.f0.fld.can_tsr.txok2= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TXOK2"); +state->u.f0.fld.can_tsr.alst2= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ALST2"); +state->u.f0.fld.can_tsr.terr2= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TERR2"); +state->u.f0.fld.can_tsr.abrq2= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "ABRQ2"); +state->u.f0.fld.can_tsr.code= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "CODE"); +state->u.f0.fld.can_tsr.tme0= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TME0"); +state->u.f0.fld.can_tsr.tme1= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TME1"); +state->u.f0.fld.can_tsr.tme2= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "TME2"); +state->u.f0.fld.can_tsr.low0= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "LOW0"); +state->u.f0.fld.can_tsr.low1= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "LOW1"); +state->u.f0.fld.can_tsr.low2= cm_object_get_child_by_name(state->u.f0.reg.can_tsr, "LOW2"); +// CAN_RF0Rbitfields. +state->u.f0.fld.can_rf0r.fmp0= cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "FMP0"); +state->u.f0.fld.can_rf0r.full0= cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "FULL0"); +state->u.f0.fld.can_rf0r.fovr0= cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "FOVR0"); +state->u.f0.fld.can_rf0r.rfom0= cm_object_get_child_by_name(state->u.f0.reg.can_rf0r, "RFOM0"); +// CAN_RF1Rbitfields. +state->u.f0.fld.can_rf1r.fmp1= cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "FMP1"); +state->u.f0.fld.can_rf1r.full1= cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "FULL1"); +state->u.f0.fld.can_rf1r.fovr1= cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "FOVR1"); +state->u.f0.fld.can_rf1r.rfom1= cm_object_get_child_by_name(state->u.f0.reg.can_rf1r, "RFOM1"); +// CAN_IERbitfields. +state->u.f0.fld.can_ier.tmeie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "TMEIE"); +state->u.f0.fld.can_ier.fmpie0= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FMPIE0"); +state->u.f0.fld.can_ier.ffie0= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FFIE0"); +state->u.f0.fld.can_ier.fovie0= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FOVIE0"); +state->u.f0.fld.can_ier.fmpie1= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FMPIE1"); +state->u.f0.fld.can_ier.ffie1= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FFIE1"); +state->u.f0.fld.can_ier.fovie1= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "FOVIE1"); +state->u.f0.fld.can_ier.ewgie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "EWGIE"); +state->u.f0.fld.can_ier.epvie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "EPVIE"); +state->u.f0.fld.can_ier.bofie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "BOFIE"); +state->u.f0.fld.can_ier.lecie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "LECIE"); +state->u.f0.fld.can_ier.errie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "ERRIE"); +state->u.f0.fld.can_ier.wkuie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "WKUIE"); +state->u.f0.fld.can_ier.slkie= cm_object_get_child_by_name(state->u.f0.reg.can_ier, "SLKIE"); +// CAN_ESRbitfields. +state->u.f0.fld.can_esr.ewgf= cm_object_get_child_by_name(state->u.f0.reg.can_esr, "EWGF"); +state->u.f0.fld.can_esr.epvf= cm_object_get_child_by_name(state->u.f0.reg.can_esr, "EPVF"); +state->u.f0.fld.can_esr.boff= cm_object_get_child_by_name(state->u.f0.reg.can_esr, "BOFF"); +state->u.f0.fld.can_esr.lec= cm_object_get_child_by_name(state->u.f0.reg.can_esr, "LEC"); +state->u.f0.fld.can_esr.tec= cm_object_get_child_by_name(state->u.f0.reg.can_esr, "TEC"); +state->u.f0.fld.can_esr.rec= cm_object_get_child_by_name(state->u.f0.reg.can_esr, "REC"); +// CAN_BTRbitfields. +state->u.f0.fld.can_btr.brp= cm_object_get_child_by_name(state->u.f0.reg.can_btr, "BRP"); +state->u.f0.fld.can_btr.ts1= cm_object_get_child_by_name(state->u.f0.reg.can_btr, "TS1"); +state->u.f0.fld.can_btr.ts2= cm_object_get_child_by_name(state->u.f0.reg.can_btr, "TS2"); +state->u.f0.fld.can_btr.sjw= cm_object_get_child_by_name(state->u.f0.reg.can_btr, "SJW"); +state->u.f0.fld.can_btr.lbkm= cm_object_get_child_by_name(state->u.f0.reg.can_btr, "LBKM"); +state->u.f0.fld.can_btr.silm= cm_object_get_child_by_name(state->u.f0.reg.can_btr, "SILM"); +// CAN_TI0Rbitfields. +state->u.f0.fld.can_ti0r.txrq= cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "TXRQ"); +state->u.f0.fld.can_ti0r.rtr= cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "RTR"); +state->u.f0.fld.can_ti0r.ide= cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "IDE"); +state->u.f0.fld.can_ti0r.exid= cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "EXID"); +state->u.f0.fld.can_ti0r.stid= cm_object_get_child_by_name(state->u.f0.reg.can_ti0r, "STID"); +// CAN_TDT0Rbitfields. +state->u.f0.fld.can_tdt0r.dlc= cm_object_get_child_by_name(state->u.f0.reg.can_tdt0r, "DLC"); +state->u.f0.fld.can_tdt0r.tgt= cm_object_get_child_by_name(state->u.f0.reg.can_tdt0r, "TGT"); +state->u.f0.fld.can_tdt0r.time= cm_object_get_child_by_name(state->u.f0.reg.can_tdt0r, "TIME"); +// CAN_TDL0Rbitfields. +state->u.f0.fld.can_tdl0r.data0= cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA0"); +state->u.f0.fld.can_tdl0r.data1= cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA1"); +state->u.f0.fld.can_tdl0r.data2= cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA2"); +state->u.f0.fld.can_tdl0r.data3= cm_object_get_child_by_name(state->u.f0.reg.can_tdl0r, "DATA3"); +// CAN_TDH0Rbitfields. +state->u.f0.fld.can_tdh0r.data4= cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA4"); +state->u.f0.fld.can_tdh0r.data5= cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA5"); +state->u.f0.fld.can_tdh0r.data6= cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA6"); +state->u.f0.fld.can_tdh0r.data7= cm_object_get_child_by_name(state->u.f0.reg.can_tdh0r, "DATA7"); +// CAN_TI1Rbitfields. +state->u.f0.fld.can_ti1r.txrq= cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "TXRQ"); +state->u.f0.fld.can_ti1r.rtr= cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "RTR"); +state->u.f0.fld.can_ti1r.ide= cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "IDE"); +state->u.f0.fld.can_ti1r.exid= cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "EXID"); +state->u.f0.fld.can_ti1r.stid= cm_object_get_child_by_name(state->u.f0.reg.can_ti1r, "STID"); +// CAN_TDT1Rbitfields. +state->u.f0.fld.can_tdt1r.dlc= cm_object_get_child_by_name(state->u.f0.reg.can_tdt1r, "DLC"); +state->u.f0.fld.can_tdt1r.tgt= cm_object_get_child_by_name(state->u.f0.reg.can_tdt1r, "TGT"); +state->u.f0.fld.can_tdt1r.time= cm_object_get_child_by_name(state->u.f0.reg.can_tdt1r, "TIME"); +// CAN_TDL1Rbitfields. +state->u.f0.fld.can_tdl1r.data0= cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA0"); +state->u.f0.fld.can_tdl1r.data1= cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA1"); +state->u.f0.fld.can_tdl1r.data2= cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA2"); +state->u.f0.fld.can_tdl1r.data3= cm_object_get_child_by_name(state->u.f0.reg.can_tdl1r, "DATA3"); +// CAN_TDH1Rbitfields. +state->u.f0.fld.can_tdh1r.data4= cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA4"); +state->u.f0.fld.can_tdh1r.data5= cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA5"); +state->u.f0.fld.can_tdh1r.data6= cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA6"); +state->u.f0.fld.can_tdh1r.data7= cm_object_get_child_by_name(state->u.f0.reg.can_tdh1r, "DATA7"); +// CAN_TI2Rbitfields. +state->u.f0.fld.can_ti2r.txrq= cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "TXRQ"); +state->u.f0.fld.can_ti2r.rtr= cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "RTR"); +state->u.f0.fld.can_ti2r.ide= cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "IDE"); +state->u.f0.fld.can_ti2r.exid= cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "EXID"); +state->u.f0.fld.can_ti2r.stid= cm_object_get_child_by_name(state->u.f0.reg.can_ti2r, "STID"); +// CAN_TDT2Rbitfields. +state->u.f0.fld.can_tdt2r.dlc= cm_object_get_child_by_name(state->u.f0.reg.can_tdt2r, "DLC"); +state->u.f0.fld.can_tdt2r.tgt= cm_object_get_child_by_name(state->u.f0.reg.can_tdt2r, "TGT"); +state->u.f0.fld.can_tdt2r.time= cm_object_get_child_by_name(state->u.f0.reg.can_tdt2r, "TIME"); +// CAN_TDL2Rbitfields. +state->u.f0.fld.can_tdl2r.data0= cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA0"); +state->u.f0.fld.can_tdl2r.data1= cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA1"); +state->u.f0.fld.can_tdl2r.data2= cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA2"); +state->u.f0.fld.can_tdl2r.data3= cm_object_get_child_by_name(state->u.f0.reg.can_tdl2r, "DATA3"); +// CAN_TDH2Rbitfields. +state->u.f0.fld.can_tdh2r.data4= cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA4"); +state->u.f0.fld.can_tdh2r.data5= cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA5"); +state->u.f0.fld.can_tdh2r.data6= cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA6"); +state->u.f0.fld.can_tdh2r.data7= cm_object_get_child_by_name(state->u.f0.reg.can_tdh2r, "DATA7"); +// CAN_RI0Rbitfields. +state->u.f0.fld.can_ri0r.rtr= cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "RTR"); +state->u.f0.fld.can_ri0r.ide= cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "IDE"); +state->u.f0.fld.can_ri0r.exid= cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "EXID"); +state->u.f0.fld.can_ri0r.stid= cm_object_get_child_by_name(state->u.f0.reg.can_ri0r, "STID"); +// CAN_RDT0Rbitfields. +state->u.f0.fld.can_rdt0r.dlc= cm_object_get_child_by_name(state->u.f0.reg.can_rdt0r, "DLC"); +state->u.f0.fld.can_rdt0r.fmi= cm_object_get_child_by_name(state->u.f0.reg.can_rdt0r, "FMI"); +state->u.f0.fld.can_rdt0r.time= cm_object_get_child_by_name(state->u.f0.reg.can_rdt0r, "TIME"); +// CAN_RDL0Rbitfields. +state->u.f0.fld.can_rdl0r.data0= cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA0"); +state->u.f0.fld.can_rdl0r.data1= cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA1"); +state->u.f0.fld.can_rdl0r.data2= cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA2"); +state->u.f0.fld.can_rdl0r.data3= cm_object_get_child_by_name(state->u.f0.reg.can_rdl0r, "DATA3"); +// CAN_RDH0Rbitfields. +state->u.f0.fld.can_rdh0r.data4= cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA4"); +state->u.f0.fld.can_rdh0r.data5= cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA5"); +state->u.f0.fld.can_rdh0r.data6= cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA6"); +state->u.f0.fld.can_rdh0r.data7= cm_object_get_child_by_name(state->u.f0.reg.can_rdh0r, "DATA7"); +// CAN_RI1Rbitfields. +state->u.f0.fld.can_ri1r.rtr= cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "RTR"); +state->u.f0.fld.can_ri1r.ide= cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "IDE"); +state->u.f0.fld.can_ri1r.exid= cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "EXID"); +state->u.f0.fld.can_ri1r.stid= cm_object_get_child_by_name(state->u.f0.reg.can_ri1r, "STID"); +// CAN_RDT1Rbitfields. +state->u.f0.fld.can_rdt1r.dlc= cm_object_get_child_by_name(state->u.f0.reg.can_rdt1r, "DLC"); +state->u.f0.fld.can_rdt1r.fmi= cm_object_get_child_by_name(state->u.f0.reg.can_rdt1r, "FMI"); +state->u.f0.fld.can_rdt1r.time= cm_object_get_child_by_name(state->u.f0.reg.can_rdt1r, "TIME"); +// CAN_RDL1Rbitfields. +state->u.f0.fld.can_rdl1r.data0= cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA0"); +state->u.f0.fld.can_rdl1r.data1= cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA1"); +state->u.f0.fld.can_rdl1r.data2= cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA2"); +state->u.f0.fld.can_rdl1r.data3= cm_object_get_child_by_name(state->u.f0.reg.can_rdl1r, "DATA3"); +// CAN_RDH1Rbitfields. +state->u.f0.fld.can_rdh1r.data4= cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA4"); +state->u.f0.fld.can_rdh1r.data5= cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA5"); +state->u.f0.fld.can_rdh1r.data6= cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA6"); +state->u.f0.fld.can_rdh1r.data7= cm_object_get_child_by_name(state->u.f0.reg.can_rdh1r, "DATA7"); +// CAN_FMRbitfields. +state->u.f0.fld.can_fmr.finit= cm_object_get_child_by_name(state->u.f0.reg.can_fmr, "FINIT"); +state->u.f0.fld.can_fmr.can2sb= cm_object_get_child_by_name(state->u.f0.reg.can_fmr, "CAN2SB"); +// CAN_FM1Rbitfields. +state->u.f0.fld.can_fm1r.fbm0= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM0"); +state->u.f0.fld.can_fm1r.fbm1= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM1"); +state->u.f0.fld.can_fm1r.fbm2= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM2"); +state->u.f0.fld.can_fm1r.fbm3= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM3"); +state->u.f0.fld.can_fm1r.fbm4= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM4"); +state->u.f0.fld.can_fm1r.fbm5= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM5"); +state->u.f0.fld.can_fm1r.fbm6= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM6"); +state->u.f0.fld.can_fm1r.fbm7= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM7"); +state->u.f0.fld.can_fm1r.fbm8= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM8"); +state->u.f0.fld.can_fm1r.fbm9= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM9"); +state->u.f0.fld.can_fm1r.fbm10= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM10"); +state->u.f0.fld.can_fm1r.fbm11= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM11"); +state->u.f0.fld.can_fm1r.fbm12= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM12"); +state->u.f0.fld.can_fm1r.fbm13= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM13"); +state->u.f0.fld.can_fm1r.fbm14= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM14"); +state->u.f0.fld.can_fm1r.fbm15= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM15"); +state->u.f0.fld.can_fm1r.fbm16= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM16"); +state->u.f0.fld.can_fm1r.fbm17= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM17"); +state->u.f0.fld.can_fm1r.fbm18= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM18"); +state->u.f0.fld.can_fm1r.fbm19= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM19"); +state->u.f0.fld.can_fm1r.fbm20= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM20"); +state->u.f0.fld.can_fm1r.fbm21= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM21"); +state->u.f0.fld.can_fm1r.fbm22= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM22"); +state->u.f0.fld.can_fm1r.fbm23= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM23"); +state->u.f0.fld.can_fm1r.fbm24= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM24"); +state->u.f0.fld.can_fm1r.fbm25= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM25"); +state->u.f0.fld.can_fm1r.fbm26= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM26"); +state->u.f0.fld.can_fm1r.fbm27= cm_object_get_child_by_name(state->u.f0.reg.can_fm1r, "FBM27"); +// CAN_FS1Rbitfields. +state->u.f0.fld.can_fs1r.fsc0= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC0"); +state->u.f0.fld.can_fs1r.fsc1= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC1"); +state->u.f0.fld.can_fs1r.fsc2= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC2"); +state->u.f0.fld.can_fs1r.fsc3= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC3"); +state->u.f0.fld.can_fs1r.fsc4= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC4"); +state->u.f0.fld.can_fs1r.fsc5= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC5"); +state->u.f0.fld.can_fs1r.fsc6= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC6"); +state->u.f0.fld.can_fs1r.fsc7= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC7"); +state->u.f0.fld.can_fs1r.fsc8= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC8"); +state->u.f0.fld.can_fs1r.fsc9= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC9"); +state->u.f0.fld.can_fs1r.fsc10= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC10"); +state->u.f0.fld.can_fs1r.fsc11= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC11"); +state->u.f0.fld.can_fs1r.fsc12= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC12"); +state->u.f0.fld.can_fs1r.fsc13= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC13"); +state->u.f0.fld.can_fs1r.fsc14= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC14"); +state->u.f0.fld.can_fs1r.fsc15= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC15"); +state->u.f0.fld.can_fs1r.fsc16= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC16"); +state->u.f0.fld.can_fs1r.fsc17= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC17"); +state->u.f0.fld.can_fs1r.fsc18= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC18"); +state->u.f0.fld.can_fs1r.fsc19= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC19"); +state->u.f0.fld.can_fs1r.fsc20= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC20"); +state->u.f0.fld.can_fs1r.fsc21= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC21"); +state->u.f0.fld.can_fs1r.fsc22= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC22"); +state->u.f0.fld.can_fs1r.fsc23= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC23"); +state->u.f0.fld.can_fs1r.fsc24= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC24"); +state->u.f0.fld.can_fs1r.fsc25= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC25"); +state->u.f0.fld.can_fs1r.fsc26= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC26"); +state->u.f0.fld.can_fs1r.fsc27= cm_object_get_child_by_name(state->u.f0.reg.can_fs1r, "FSC27"); +// CAN_FFA1Rbitfields. +state->u.f0.fld.can_ffa1r.ffa0= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA0"); +state->u.f0.fld.can_ffa1r.ffa1= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA1"); +state->u.f0.fld.can_ffa1r.ffa2= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA2"); +state->u.f0.fld.can_ffa1r.ffa3= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA3"); +state->u.f0.fld.can_ffa1r.ffa4= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA4"); +state->u.f0.fld.can_ffa1r.ffa5= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA5"); +state->u.f0.fld.can_ffa1r.ffa6= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA6"); +state->u.f0.fld.can_ffa1r.ffa7= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA7"); +state->u.f0.fld.can_ffa1r.ffa8= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA8"); +state->u.f0.fld.can_ffa1r.ffa9= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA9"); +state->u.f0.fld.can_ffa1r.ffa10= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA10"); +state->u.f0.fld.can_ffa1r.ffa11= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA11"); +state->u.f0.fld.can_ffa1r.ffa12= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA12"); +state->u.f0.fld.can_ffa1r.ffa13= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA13"); +state->u.f0.fld.can_ffa1r.ffa14= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA14"); +state->u.f0.fld.can_ffa1r.ffa15= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA15"); +state->u.f0.fld.can_ffa1r.ffa16= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA16"); +state->u.f0.fld.can_ffa1r.ffa17= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA17"); +state->u.f0.fld.can_ffa1r.ffa18= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA18"); +state->u.f0.fld.can_ffa1r.ffa19= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA19"); +state->u.f0.fld.can_ffa1r.ffa20= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA20"); +state->u.f0.fld.can_ffa1r.ffa21= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA21"); +state->u.f0.fld.can_ffa1r.ffa22= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA22"); +state->u.f0.fld.can_ffa1r.ffa23= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA23"); +state->u.f0.fld.can_ffa1r.ffa24= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA24"); +state->u.f0.fld.can_ffa1r.ffa25= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA25"); +state->u.f0.fld.can_ffa1r.ffa26= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA26"); +state->u.f0.fld.can_ffa1r.ffa27= cm_object_get_child_by_name(state->u.f0.reg.can_ffa1r, "FFA27"); +// CAN_FA1Rbitfields. +state->u.f0.fld.can_fa1r.fact0= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT0"); +state->u.f0.fld.can_fa1r.fact1= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT1"); +state->u.f0.fld.can_fa1r.fact2= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT2"); +state->u.f0.fld.can_fa1r.fact3= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT3"); +state->u.f0.fld.can_fa1r.fact4= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT4"); +state->u.f0.fld.can_fa1r.fact5= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT5"); +state->u.f0.fld.can_fa1r.fact6= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT6"); +state->u.f0.fld.can_fa1r.fact7= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT7"); +state->u.f0.fld.can_fa1r.fact8= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT8"); +state->u.f0.fld.can_fa1r.fact9= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT9"); +state->u.f0.fld.can_fa1r.fact10= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT10"); +state->u.f0.fld.can_fa1r.fact11= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT11"); +state->u.f0.fld.can_fa1r.fact12= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT12"); +state->u.f0.fld.can_fa1r.fact13= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT13"); +state->u.f0.fld.can_fa1r.fact14= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT14"); +state->u.f0.fld.can_fa1r.fact15= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT15"); +state->u.f0.fld.can_fa1r.fact16= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT16"); +state->u.f0.fld.can_fa1r.fact17= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT17"); +state->u.f0.fld.can_fa1r.fact18= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT18"); +state->u.f0.fld.can_fa1r.fact19= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT19"); +state->u.f0.fld.can_fa1r.fact20= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT20"); +state->u.f0.fld.can_fa1r.fact21= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT21"); +state->u.f0.fld.can_fa1r.fact22= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT22"); +state->u.f0.fld.can_fa1r.fact23= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT23"); +state->u.f0.fld.can_fa1r.fact24= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT24"); +state->u.f0.fld.can_fa1r.fact25= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT25"); +state->u.f0.fld.can_fa1r.fact26= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT26"); +state->u.f0.fld.can_fa1r.fact27= cm_object_get_child_by_name(state->u.f0.reg.can_fa1r, "FACT27"); +// F0R1bitfields. +state->u.f0.fld.f0r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB0"); +state->u.f0.fld.f0r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB1"); +state->u.f0.fld.f0r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB2"); +state->u.f0.fld.f0r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB3"); +state->u.f0.fld.f0r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB4"); +state->u.f0.fld.f0r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB5"); +state->u.f0.fld.f0r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB6"); +state->u.f0.fld.f0r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB7"); +state->u.f0.fld.f0r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB8"); +state->u.f0.fld.f0r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB9"); +state->u.f0.fld.f0r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB10"); +state->u.f0.fld.f0r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB11"); +state->u.f0.fld.f0r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB12"); +state->u.f0.fld.f0r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB13"); +state->u.f0.fld.f0r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB14"); +state->u.f0.fld.f0r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB15"); +state->u.f0.fld.f0r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB16"); +state->u.f0.fld.f0r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB17"); +state->u.f0.fld.f0r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB18"); +state->u.f0.fld.f0r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB19"); +state->u.f0.fld.f0r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB20"); +state->u.f0.fld.f0r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB21"); +state->u.f0.fld.f0r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB22"); +state->u.f0.fld.f0r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB23"); +state->u.f0.fld.f0r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB24"); +state->u.f0.fld.f0r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB25"); +state->u.f0.fld.f0r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB26"); +state->u.f0.fld.f0r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB27"); +state->u.f0.fld.f0r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB28"); +state->u.f0.fld.f0r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB29"); +state->u.f0.fld.f0r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB30"); +state->u.f0.fld.f0r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f0r1, "FB31"); +// F0R2bitfields. +state->u.f0.fld.f0r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB0"); +state->u.f0.fld.f0r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB1"); +state->u.f0.fld.f0r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB2"); +state->u.f0.fld.f0r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB3"); +state->u.f0.fld.f0r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB4"); +state->u.f0.fld.f0r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB5"); +state->u.f0.fld.f0r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB6"); +state->u.f0.fld.f0r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB7"); +state->u.f0.fld.f0r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB8"); +state->u.f0.fld.f0r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB9"); +state->u.f0.fld.f0r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB10"); +state->u.f0.fld.f0r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB11"); +state->u.f0.fld.f0r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB12"); +state->u.f0.fld.f0r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB13"); +state->u.f0.fld.f0r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB14"); +state->u.f0.fld.f0r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB15"); +state->u.f0.fld.f0r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB16"); +state->u.f0.fld.f0r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB17"); +state->u.f0.fld.f0r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB18"); +state->u.f0.fld.f0r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB19"); +state->u.f0.fld.f0r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB20"); +state->u.f0.fld.f0r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB21"); +state->u.f0.fld.f0r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB22"); +state->u.f0.fld.f0r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB23"); +state->u.f0.fld.f0r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB24"); +state->u.f0.fld.f0r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB25"); +state->u.f0.fld.f0r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB26"); +state->u.f0.fld.f0r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB27"); +state->u.f0.fld.f0r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB28"); +state->u.f0.fld.f0r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB29"); +state->u.f0.fld.f0r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB30"); +state->u.f0.fld.f0r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f0r2, "FB31"); +// F1R1bitfields. +state->u.f0.fld.f1r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB0"); +state->u.f0.fld.f1r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB1"); +state->u.f0.fld.f1r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB2"); +state->u.f0.fld.f1r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB3"); +state->u.f0.fld.f1r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB4"); +state->u.f0.fld.f1r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB5"); +state->u.f0.fld.f1r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB6"); +state->u.f0.fld.f1r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB7"); +state->u.f0.fld.f1r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB8"); +state->u.f0.fld.f1r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB9"); +state->u.f0.fld.f1r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB10"); +state->u.f0.fld.f1r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB11"); +state->u.f0.fld.f1r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB12"); +state->u.f0.fld.f1r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB13"); +state->u.f0.fld.f1r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB14"); +state->u.f0.fld.f1r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB15"); +state->u.f0.fld.f1r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB16"); +state->u.f0.fld.f1r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB17"); +state->u.f0.fld.f1r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB18"); +state->u.f0.fld.f1r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB19"); +state->u.f0.fld.f1r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB20"); +state->u.f0.fld.f1r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB21"); +state->u.f0.fld.f1r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB22"); +state->u.f0.fld.f1r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB23"); +state->u.f0.fld.f1r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB24"); +state->u.f0.fld.f1r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB25"); +state->u.f0.fld.f1r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB26"); +state->u.f0.fld.f1r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB27"); +state->u.f0.fld.f1r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB28"); +state->u.f0.fld.f1r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB29"); +state->u.f0.fld.f1r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB30"); +state->u.f0.fld.f1r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f1r1, "FB31"); +// F1R2bitfields. +state->u.f0.fld.f1r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB0"); +state->u.f0.fld.f1r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB1"); +state->u.f0.fld.f1r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB2"); +state->u.f0.fld.f1r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB3"); +state->u.f0.fld.f1r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB4"); +state->u.f0.fld.f1r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB5"); +state->u.f0.fld.f1r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB6"); +state->u.f0.fld.f1r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB7"); +state->u.f0.fld.f1r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB8"); +state->u.f0.fld.f1r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB9"); +state->u.f0.fld.f1r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB10"); +state->u.f0.fld.f1r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB11"); +state->u.f0.fld.f1r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB12"); +state->u.f0.fld.f1r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB13"); +state->u.f0.fld.f1r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB14"); +state->u.f0.fld.f1r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB15"); +state->u.f0.fld.f1r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB16"); +state->u.f0.fld.f1r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB17"); +state->u.f0.fld.f1r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB18"); +state->u.f0.fld.f1r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB19"); +state->u.f0.fld.f1r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB20"); +state->u.f0.fld.f1r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB21"); +state->u.f0.fld.f1r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB22"); +state->u.f0.fld.f1r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB23"); +state->u.f0.fld.f1r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB24"); +state->u.f0.fld.f1r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB25"); +state->u.f0.fld.f1r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB26"); +state->u.f0.fld.f1r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB27"); +state->u.f0.fld.f1r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB28"); +state->u.f0.fld.f1r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB29"); +state->u.f0.fld.f1r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB30"); +state->u.f0.fld.f1r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f1r2, "FB31"); +// F2R1bitfields. +state->u.f0.fld.f2r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB0"); +state->u.f0.fld.f2r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB1"); +state->u.f0.fld.f2r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB2"); +state->u.f0.fld.f2r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB3"); +state->u.f0.fld.f2r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB4"); +state->u.f0.fld.f2r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB5"); +state->u.f0.fld.f2r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB6"); +state->u.f0.fld.f2r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB7"); +state->u.f0.fld.f2r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB8"); +state->u.f0.fld.f2r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB9"); +state->u.f0.fld.f2r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB10"); +state->u.f0.fld.f2r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB11"); +state->u.f0.fld.f2r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB12"); +state->u.f0.fld.f2r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB13"); +state->u.f0.fld.f2r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB14"); +state->u.f0.fld.f2r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB15"); +state->u.f0.fld.f2r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB16"); +state->u.f0.fld.f2r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB17"); +state->u.f0.fld.f2r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB18"); +state->u.f0.fld.f2r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB19"); +state->u.f0.fld.f2r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB20"); +state->u.f0.fld.f2r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB21"); +state->u.f0.fld.f2r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB22"); +state->u.f0.fld.f2r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB23"); +state->u.f0.fld.f2r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB24"); +state->u.f0.fld.f2r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB25"); +state->u.f0.fld.f2r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB26"); +state->u.f0.fld.f2r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB27"); +state->u.f0.fld.f2r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB28"); +state->u.f0.fld.f2r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB29"); +state->u.f0.fld.f2r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB30"); +state->u.f0.fld.f2r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f2r1, "FB31"); +// F2R2bitfields. +state->u.f0.fld.f2r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB0"); +state->u.f0.fld.f2r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB1"); +state->u.f0.fld.f2r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB2"); +state->u.f0.fld.f2r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB3"); +state->u.f0.fld.f2r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB4"); +state->u.f0.fld.f2r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB5"); +state->u.f0.fld.f2r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB6"); +state->u.f0.fld.f2r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB7"); +state->u.f0.fld.f2r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB8"); +state->u.f0.fld.f2r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB9"); +state->u.f0.fld.f2r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB10"); +state->u.f0.fld.f2r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB11"); +state->u.f0.fld.f2r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB12"); +state->u.f0.fld.f2r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB13"); +state->u.f0.fld.f2r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB14"); +state->u.f0.fld.f2r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB15"); +state->u.f0.fld.f2r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB16"); +state->u.f0.fld.f2r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB17"); +state->u.f0.fld.f2r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB18"); +state->u.f0.fld.f2r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB19"); +state->u.f0.fld.f2r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB20"); +state->u.f0.fld.f2r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB21"); +state->u.f0.fld.f2r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB22"); +state->u.f0.fld.f2r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB23"); +state->u.f0.fld.f2r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB24"); +state->u.f0.fld.f2r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB25"); +state->u.f0.fld.f2r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB26"); +state->u.f0.fld.f2r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB27"); +state->u.f0.fld.f2r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB28"); +state->u.f0.fld.f2r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB29"); +state->u.f0.fld.f2r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB30"); +state->u.f0.fld.f2r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f2r2, "FB31"); +// F3R1bitfields. +state->u.f0.fld.f3r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB0"); +state->u.f0.fld.f3r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB1"); +state->u.f0.fld.f3r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB2"); +state->u.f0.fld.f3r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB3"); +state->u.f0.fld.f3r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB4"); +state->u.f0.fld.f3r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB5"); +state->u.f0.fld.f3r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB6"); +state->u.f0.fld.f3r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB7"); +state->u.f0.fld.f3r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB8"); +state->u.f0.fld.f3r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB9"); +state->u.f0.fld.f3r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB10"); +state->u.f0.fld.f3r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB11"); +state->u.f0.fld.f3r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB12"); +state->u.f0.fld.f3r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB13"); +state->u.f0.fld.f3r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB14"); +state->u.f0.fld.f3r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB15"); +state->u.f0.fld.f3r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB16"); +state->u.f0.fld.f3r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB17"); +state->u.f0.fld.f3r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB18"); +state->u.f0.fld.f3r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB19"); +state->u.f0.fld.f3r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB20"); +state->u.f0.fld.f3r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB21"); +state->u.f0.fld.f3r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB22"); +state->u.f0.fld.f3r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB23"); +state->u.f0.fld.f3r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB24"); +state->u.f0.fld.f3r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB25"); +state->u.f0.fld.f3r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB26"); +state->u.f0.fld.f3r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB27"); +state->u.f0.fld.f3r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB28"); +state->u.f0.fld.f3r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB29"); +state->u.f0.fld.f3r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB30"); +state->u.f0.fld.f3r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f3r1, "FB31"); +// F3R2bitfields. +state->u.f0.fld.f3r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB0"); +state->u.f0.fld.f3r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB1"); +state->u.f0.fld.f3r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB2"); +state->u.f0.fld.f3r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB3"); +state->u.f0.fld.f3r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB4"); +state->u.f0.fld.f3r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB5"); +state->u.f0.fld.f3r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB6"); +state->u.f0.fld.f3r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB7"); +state->u.f0.fld.f3r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB8"); +state->u.f0.fld.f3r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB9"); +state->u.f0.fld.f3r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB10"); +state->u.f0.fld.f3r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB11"); +state->u.f0.fld.f3r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB12"); +state->u.f0.fld.f3r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB13"); +state->u.f0.fld.f3r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB14"); +state->u.f0.fld.f3r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB15"); +state->u.f0.fld.f3r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB16"); +state->u.f0.fld.f3r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB17"); +state->u.f0.fld.f3r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB18"); +state->u.f0.fld.f3r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB19"); +state->u.f0.fld.f3r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB20"); +state->u.f0.fld.f3r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB21"); +state->u.f0.fld.f3r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB22"); +state->u.f0.fld.f3r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB23"); +state->u.f0.fld.f3r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB24"); +state->u.f0.fld.f3r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB25"); +state->u.f0.fld.f3r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB26"); +state->u.f0.fld.f3r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB27"); +state->u.f0.fld.f3r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB28"); +state->u.f0.fld.f3r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB29"); +state->u.f0.fld.f3r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB30"); +state->u.f0.fld.f3r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f3r2, "FB31"); +// F4R1bitfields. +state->u.f0.fld.f4r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB0"); +state->u.f0.fld.f4r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB1"); +state->u.f0.fld.f4r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB2"); +state->u.f0.fld.f4r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB3"); +state->u.f0.fld.f4r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB4"); +state->u.f0.fld.f4r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB5"); +state->u.f0.fld.f4r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB6"); +state->u.f0.fld.f4r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB7"); +state->u.f0.fld.f4r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB8"); +state->u.f0.fld.f4r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB9"); +state->u.f0.fld.f4r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB10"); +state->u.f0.fld.f4r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB11"); +state->u.f0.fld.f4r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB12"); +state->u.f0.fld.f4r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB13"); +state->u.f0.fld.f4r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB14"); +state->u.f0.fld.f4r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB15"); +state->u.f0.fld.f4r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB16"); +state->u.f0.fld.f4r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB17"); +state->u.f0.fld.f4r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB18"); +state->u.f0.fld.f4r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB19"); +state->u.f0.fld.f4r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB20"); +state->u.f0.fld.f4r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB21"); +state->u.f0.fld.f4r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB22"); +state->u.f0.fld.f4r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB23"); +state->u.f0.fld.f4r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB24"); +state->u.f0.fld.f4r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB25"); +state->u.f0.fld.f4r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB26"); +state->u.f0.fld.f4r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB27"); +state->u.f0.fld.f4r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB28"); +state->u.f0.fld.f4r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB29"); +state->u.f0.fld.f4r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB30"); +state->u.f0.fld.f4r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f4r1, "FB31"); +// F4R2bitfields. +state->u.f0.fld.f4r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB0"); +state->u.f0.fld.f4r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB1"); +state->u.f0.fld.f4r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB2"); +state->u.f0.fld.f4r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB3"); +state->u.f0.fld.f4r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB4"); +state->u.f0.fld.f4r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB5"); +state->u.f0.fld.f4r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB6"); +state->u.f0.fld.f4r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB7"); +state->u.f0.fld.f4r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB8"); +state->u.f0.fld.f4r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB9"); +state->u.f0.fld.f4r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB10"); +state->u.f0.fld.f4r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB11"); +state->u.f0.fld.f4r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB12"); +state->u.f0.fld.f4r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB13"); +state->u.f0.fld.f4r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB14"); +state->u.f0.fld.f4r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB15"); +state->u.f0.fld.f4r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB16"); +state->u.f0.fld.f4r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB17"); +state->u.f0.fld.f4r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB18"); +state->u.f0.fld.f4r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB19"); +state->u.f0.fld.f4r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB20"); +state->u.f0.fld.f4r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB21"); +state->u.f0.fld.f4r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB22"); +state->u.f0.fld.f4r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB23"); +state->u.f0.fld.f4r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB24"); +state->u.f0.fld.f4r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB25"); +state->u.f0.fld.f4r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB26"); +state->u.f0.fld.f4r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB27"); +state->u.f0.fld.f4r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB28"); +state->u.f0.fld.f4r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB29"); +state->u.f0.fld.f4r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB30"); +state->u.f0.fld.f4r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f4r2, "FB31"); +// F5R1bitfields. +state->u.f0.fld.f5r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB0"); +state->u.f0.fld.f5r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB1"); +state->u.f0.fld.f5r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB2"); +state->u.f0.fld.f5r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB3"); +state->u.f0.fld.f5r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB4"); +state->u.f0.fld.f5r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB5"); +state->u.f0.fld.f5r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB6"); +state->u.f0.fld.f5r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB7"); +state->u.f0.fld.f5r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB8"); +state->u.f0.fld.f5r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB9"); +state->u.f0.fld.f5r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB10"); +state->u.f0.fld.f5r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB11"); +state->u.f0.fld.f5r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB12"); +state->u.f0.fld.f5r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB13"); +state->u.f0.fld.f5r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB14"); +state->u.f0.fld.f5r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB15"); +state->u.f0.fld.f5r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB16"); +state->u.f0.fld.f5r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB17"); +state->u.f0.fld.f5r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB18"); +state->u.f0.fld.f5r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB19"); +state->u.f0.fld.f5r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB20"); +state->u.f0.fld.f5r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB21"); +state->u.f0.fld.f5r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB22"); +state->u.f0.fld.f5r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB23"); +state->u.f0.fld.f5r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB24"); +state->u.f0.fld.f5r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB25"); +state->u.f0.fld.f5r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB26"); +state->u.f0.fld.f5r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB27"); +state->u.f0.fld.f5r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB28"); +state->u.f0.fld.f5r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB29"); +state->u.f0.fld.f5r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB30"); +state->u.f0.fld.f5r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f5r1, "FB31"); +// F5R2bitfields. +state->u.f0.fld.f5r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB0"); +state->u.f0.fld.f5r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB1"); +state->u.f0.fld.f5r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB2"); +state->u.f0.fld.f5r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB3"); +state->u.f0.fld.f5r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB4"); +state->u.f0.fld.f5r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB5"); +state->u.f0.fld.f5r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB6"); +state->u.f0.fld.f5r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB7"); +state->u.f0.fld.f5r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB8"); +state->u.f0.fld.f5r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB9"); +state->u.f0.fld.f5r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB10"); +state->u.f0.fld.f5r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB11"); +state->u.f0.fld.f5r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB12"); +state->u.f0.fld.f5r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB13"); +state->u.f0.fld.f5r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB14"); +state->u.f0.fld.f5r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB15"); +state->u.f0.fld.f5r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB16"); +state->u.f0.fld.f5r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB17"); +state->u.f0.fld.f5r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB18"); +state->u.f0.fld.f5r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB19"); +state->u.f0.fld.f5r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB20"); +state->u.f0.fld.f5r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB21"); +state->u.f0.fld.f5r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB22"); +state->u.f0.fld.f5r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB23"); +state->u.f0.fld.f5r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB24"); +state->u.f0.fld.f5r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB25"); +state->u.f0.fld.f5r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB26"); +state->u.f0.fld.f5r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB27"); +state->u.f0.fld.f5r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB28"); +state->u.f0.fld.f5r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB29"); +state->u.f0.fld.f5r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB30"); +state->u.f0.fld.f5r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f5r2, "FB31"); +// F6R1bitfields. +state->u.f0.fld.f6r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB0"); +state->u.f0.fld.f6r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB1"); +state->u.f0.fld.f6r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB2"); +state->u.f0.fld.f6r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB3"); +state->u.f0.fld.f6r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB4"); +state->u.f0.fld.f6r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB5"); +state->u.f0.fld.f6r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB6"); +state->u.f0.fld.f6r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB7"); +state->u.f0.fld.f6r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB8"); +state->u.f0.fld.f6r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB9"); +state->u.f0.fld.f6r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB10"); +state->u.f0.fld.f6r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB11"); +state->u.f0.fld.f6r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB12"); +state->u.f0.fld.f6r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB13"); +state->u.f0.fld.f6r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB14"); +state->u.f0.fld.f6r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB15"); +state->u.f0.fld.f6r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB16"); +state->u.f0.fld.f6r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB17"); +state->u.f0.fld.f6r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB18"); +state->u.f0.fld.f6r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB19"); +state->u.f0.fld.f6r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB20"); +state->u.f0.fld.f6r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB21"); +state->u.f0.fld.f6r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB22"); +state->u.f0.fld.f6r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB23"); +state->u.f0.fld.f6r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB24"); +state->u.f0.fld.f6r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB25"); +state->u.f0.fld.f6r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB26"); +state->u.f0.fld.f6r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB27"); +state->u.f0.fld.f6r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB28"); +state->u.f0.fld.f6r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB29"); +state->u.f0.fld.f6r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB30"); +state->u.f0.fld.f6r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f6r1, "FB31"); +// F6R2bitfields. +state->u.f0.fld.f6r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB0"); +state->u.f0.fld.f6r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB1"); +state->u.f0.fld.f6r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB2"); +state->u.f0.fld.f6r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB3"); +state->u.f0.fld.f6r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB4"); +state->u.f0.fld.f6r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB5"); +state->u.f0.fld.f6r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB6"); +state->u.f0.fld.f6r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB7"); +state->u.f0.fld.f6r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB8"); +state->u.f0.fld.f6r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB9"); +state->u.f0.fld.f6r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB10"); +state->u.f0.fld.f6r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB11"); +state->u.f0.fld.f6r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB12"); +state->u.f0.fld.f6r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB13"); +state->u.f0.fld.f6r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB14"); +state->u.f0.fld.f6r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB15"); +state->u.f0.fld.f6r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB16"); +state->u.f0.fld.f6r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB17"); +state->u.f0.fld.f6r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB18"); +state->u.f0.fld.f6r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB19"); +state->u.f0.fld.f6r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB20"); +state->u.f0.fld.f6r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB21"); +state->u.f0.fld.f6r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB22"); +state->u.f0.fld.f6r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB23"); +state->u.f0.fld.f6r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB24"); +state->u.f0.fld.f6r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB25"); +state->u.f0.fld.f6r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB26"); +state->u.f0.fld.f6r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB27"); +state->u.f0.fld.f6r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB28"); +state->u.f0.fld.f6r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB29"); +state->u.f0.fld.f6r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB30"); +state->u.f0.fld.f6r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f6r2, "FB31"); +// F7R1bitfields. +state->u.f0.fld.f7r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB0"); +state->u.f0.fld.f7r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB1"); +state->u.f0.fld.f7r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB2"); +state->u.f0.fld.f7r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB3"); +state->u.f0.fld.f7r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB4"); +state->u.f0.fld.f7r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB5"); +state->u.f0.fld.f7r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB6"); +state->u.f0.fld.f7r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB7"); +state->u.f0.fld.f7r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB8"); +state->u.f0.fld.f7r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB9"); +state->u.f0.fld.f7r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB10"); +state->u.f0.fld.f7r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB11"); +state->u.f0.fld.f7r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB12"); +state->u.f0.fld.f7r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB13"); +state->u.f0.fld.f7r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB14"); +state->u.f0.fld.f7r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB15"); +state->u.f0.fld.f7r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB16"); +state->u.f0.fld.f7r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB17"); +state->u.f0.fld.f7r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB18"); +state->u.f0.fld.f7r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB19"); +state->u.f0.fld.f7r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB20"); +state->u.f0.fld.f7r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB21"); +state->u.f0.fld.f7r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB22"); +state->u.f0.fld.f7r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB23"); +state->u.f0.fld.f7r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB24"); +state->u.f0.fld.f7r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB25"); +state->u.f0.fld.f7r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB26"); +state->u.f0.fld.f7r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB27"); +state->u.f0.fld.f7r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB28"); +state->u.f0.fld.f7r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB29"); +state->u.f0.fld.f7r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB30"); +state->u.f0.fld.f7r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f7r1, "FB31"); +// F7R2bitfields. +state->u.f0.fld.f7r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB0"); +state->u.f0.fld.f7r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB1"); +state->u.f0.fld.f7r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB2"); +state->u.f0.fld.f7r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB3"); +state->u.f0.fld.f7r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB4"); +state->u.f0.fld.f7r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB5"); +state->u.f0.fld.f7r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB6"); +state->u.f0.fld.f7r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB7"); +state->u.f0.fld.f7r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB8"); +state->u.f0.fld.f7r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB9"); +state->u.f0.fld.f7r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB10"); +state->u.f0.fld.f7r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB11"); +state->u.f0.fld.f7r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB12"); +state->u.f0.fld.f7r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB13"); +state->u.f0.fld.f7r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB14"); +state->u.f0.fld.f7r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB15"); +state->u.f0.fld.f7r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB16"); +state->u.f0.fld.f7r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB17"); +state->u.f0.fld.f7r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB18"); +state->u.f0.fld.f7r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB19"); +state->u.f0.fld.f7r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB20"); +state->u.f0.fld.f7r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB21"); +state->u.f0.fld.f7r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB22"); +state->u.f0.fld.f7r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB23"); +state->u.f0.fld.f7r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB24"); +state->u.f0.fld.f7r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB25"); +state->u.f0.fld.f7r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB26"); +state->u.f0.fld.f7r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB27"); +state->u.f0.fld.f7r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB28"); +state->u.f0.fld.f7r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB29"); +state->u.f0.fld.f7r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB30"); +state->u.f0.fld.f7r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f7r2, "FB31"); +// F8R1bitfields. +state->u.f0.fld.f8r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB0"); +state->u.f0.fld.f8r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB1"); +state->u.f0.fld.f8r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB2"); +state->u.f0.fld.f8r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB3"); +state->u.f0.fld.f8r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB4"); +state->u.f0.fld.f8r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB5"); +state->u.f0.fld.f8r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB6"); +state->u.f0.fld.f8r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB7"); +state->u.f0.fld.f8r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB8"); +state->u.f0.fld.f8r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB9"); +state->u.f0.fld.f8r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB10"); +state->u.f0.fld.f8r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB11"); +state->u.f0.fld.f8r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB12"); +state->u.f0.fld.f8r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB13"); +state->u.f0.fld.f8r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB14"); +state->u.f0.fld.f8r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB15"); +state->u.f0.fld.f8r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB16"); +state->u.f0.fld.f8r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB17"); +state->u.f0.fld.f8r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB18"); +state->u.f0.fld.f8r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB19"); +state->u.f0.fld.f8r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB20"); +state->u.f0.fld.f8r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB21"); +state->u.f0.fld.f8r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB22"); +state->u.f0.fld.f8r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB23"); +state->u.f0.fld.f8r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB24"); +state->u.f0.fld.f8r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB25"); +state->u.f0.fld.f8r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB26"); +state->u.f0.fld.f8r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB27"); +state->u.f0.fld.f8r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB28"); +state->u.f0.fld.f8r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB29"); +state->u.f0.fld.f8r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB30"); +state->u.f0.fld.f8r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f8r1, "FB31"); +// F8R2bitfields. +state->u.f0.fld.f8r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB0"); +state->u.f0.fld.f8r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB1"); +state->u.f0.fld.f8r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB2"); +state->u.f0.fld.f8r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB3"); +state->u.f0.fld.f8r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB4"); +state->u.f0.fld.f8r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB5"); +state->u.f0.fld.f8r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB6"); +state->u.f0.fld.f8r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB7"); +state->u.f0.fld.f8r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB8"); +state->u.f0.fld.f8r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB9"); +state->u.f0.fld.f8r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB10"); +state->u.f0.fld.f8r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB11"); +state->u.f0.fld.f8r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB12"); +state->u.f0.fld.f8r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB13"); +state->u.f0.fld.f8r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB14"); +state->u.f0.fld.f8r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB15"); +state->u.f0.fld.f8r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB16"); +state->u.f0.fld.f8r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB17"); +state->u.f0.fld.f8r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB18"); +state->u.f0.fld.f8r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB19"); +state->u.f0.fld.f8r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB20"); +state->u.f0.fld.f8r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB21"); +state->u.f0.fld.f8r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB22"); +state->u.f0.fld.f8r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB23"); +state->u.f0.fld.f8r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB24"); +state->u.f0.fld.f8r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB25"); +state->u.f0.fld.f8r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB26"); +state->u.f0.fld.f8r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB27"); +state->u.f0.fld.f8r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB28"); +state->u.f0.fld.f8r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB29"); +state->u.f0.fld.f8r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB30"); +state->u.f0.fld.f8r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f8r2, "FB31"); +// F9R1bitfields. +state->u.f0.fld.f9r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB0"); +state->u.f0.fld.f9r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB1"); +state->u.f0.fld.f9r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB2"); +state->u.f0.fld.f9r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB3"); +state->u.f0.fld.f9r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB4"); +state->u.f0.fld.f9r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB5"); +state->u.f0.fld.f9r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB6"); +state->u.f0.fld.f9r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB7"); +state->u.f0.fld.f9r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB8"); +state->u.f0.fld.f9r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB9"); +state->u.f0.fld.f9r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB10"); +state->u.f0.fld.f9r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB11"); +state->u.f0.fld.f9r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB12"); +state->u.f0.fld.f9r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB13"); +state->u.f0.fld.f9r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB14"); +state->u.f0.fld.f9r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB15"); +state->u.f0.fld.f9r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB16"); +state->u.f0.fld.f9r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB17"); +state->u.f0.fld.f9r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB18"); +state->u.f0.fld.f9r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB19"); +state->u.f0.fld.f9r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB20"); +state->u.f0.fld.f9r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB21"); +state->u.f0.fld.f9r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB22"); +state->u.f0.fld.f9r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB23"); +state->u.f0.fld.f9r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB24"); +state->u.f0.fld.f9r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB25"); +state->u.f0.fld.f9r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB26"); +state->u.f0.fld.f9r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB27"); +state->u.f0.fld.f9r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB28"); +state->u.f0.fld.f9r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB29"); +state->u.f0.fld.f9r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB30"); +state->u.f0.fld.f9r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f9r1, "FB31"); +// F9R2bitfields. +state->u.f0.fld.f9r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB0"); +state->u.f0.fld.f9r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB1"); +state->u.f0.fld.f9r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB2"); +state->u.f0.fld.f9r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB3"); +state->u.f0.fld.f9r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB4"); +state->u.f0.fld.f9r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB5"); +state->u.f0.fld.f9r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB6"); +state->u.f0.fld.f9r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB7"); +state->u.f0.fld.f9r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB8"); +state->u.f0.fld.f9r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB9"); +state->u.f0.fld.f9r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB10"); +state->u.f0.fld.f9r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB11"); +state->u.f0.fld.f9r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB12"); +state->u.f0.fld.f9r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB13"); +state->u.f0.fld.f9r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB14"); +state->u.f0.fld.f9r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB15"); +state->u.f0.fld.f9r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB16"); +state->u.f0.fld.f9r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB17"); +state->u.f0.fld.f9r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB18"); +state->u.f0.fld.f9r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB19"); +state->u.f0.fld.f9r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB20"); +state->u.f0.fld.f9r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB21"); +state->u.f0.fld.f9r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB22"); +state->u.f0.fld.f9r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB23"); +state->u.f0.fld.f9r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB24"); +state->u.f0.fld.f9r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB25"); +state->u.f0.fld.f9r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB26"); +state->u.f0.fld.f9r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB27"); +state->u.f0.fld.f9r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB28"); +state->u.f0.fld.f9r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB29"); +state->u.f0.fld.f9r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB30"); +state->u.f0.fld.f9r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f9r2, "FB31"); +// F10R1bitfields. +state->u.f0.fld.f10r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB0"); +state->u.f0.fld.f10r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB1"); +state->u.f0.fld.f10r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB2"); +state->u.f0.fld.f10r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB3"); +state->u.f0.fld.f10r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB4"); +state->u.f0.fld.f10r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB5"); +state->u.f0.fld.f10r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB6"); +state->u.f0.fld.f10r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB7"); +state->u.f0.fld.f10r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB8"); +state->u.f0.fld.f10r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB9"); +state->u.f0.fld.f10r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB10"); +state->u.f0.fld.f10r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB11"); +state->u.f0.fld.f10r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB12"); +state->u.f0.fld.f10r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB13"); +state->u.f0.fld.f10r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB14"); +state->u.f0.fld.f10r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB15"); +state->u.f0.fld.f10r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB16"); +state->u.f0.fld.f10r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB17"); +state->u.f0.fld.f10r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB18"); +state->u.f0.fld.f10r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB19"); +state->u.f0.fld.f10r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB20"); +state->u.f0.fld.f10r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB21"); +state->u.f0.fld.f10r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB22"); +state->u.f0.fld.f10r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB23"); +state->u.f0.fld.f10r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB24"); +state->u.f0.fld.f10r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB25"); +state->u.f0.fld.f10r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB26"); +state->u.f0.fld.f10r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB27"); +state->u.f0.fld.f10r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB28"); +state->u.f0.fld.f10r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB29"); +state->u.f0.fld.f10r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB30"); +state->u.f0.fld.f10r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f10r1, "FB31"); +// F10R2bitfields. +state->u.f0.fld.f10r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB0"); +state->u.f0.fld.f10r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB1"); +state->u.f0.fld.f10r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB2"); +state->u.f0.fld.f10r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB3"); +state->u.f0.fld.f10r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB4"); +state->u.f0.fld.f10r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB5"); +state->u.f0.fld.f10r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB6"); +state->u.f0.fld.f10r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB7"); +state->u.f0.fld.f10r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB8"); +state->u.f0.fld.f10r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB9"); +state->u.f0.fld.f10r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB10"); +state->u.f0.fld.f10r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB11"); +state->u.f0.fld.f10r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB12"); +state->u.f0.fld.f10r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB13"); +state->u.f0.fld.f10r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB14"); +state->u.f0.fld.f10r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB15"); +state->u.f0.fld.f10r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB16"); +state->u.f0.fld.f10r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB17"); +state->u.f0.fld.f10r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB18"); +state->u.f0.fld.f10r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB19"); +state->u.f0.fld.f10r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB20"); +state->u.f0.fld.f10r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB21"); +state->u.f0.fld.f10r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB22"); +state->u.f0.fld.f10r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB23"); +state->u.f0.fld.f10r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB24"); +state->u.f0.fld.f10r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB25"); +state->u.f0.fld.f10r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB26"); +state->u.f0.fld.f10r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB27"); +state->u.f0.fld.f10r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB28"); +state->u.f0.fld.f10r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB29"); +state->u.f0.fld.f10r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB30"); +state->u.f0.fld.f10r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f10r2, "FB31"); +// F11R1bitfields. +state->u.f0.fld.f11r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB0"); +state->u.f0.fld.f11r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB1"); +state->u.f0.fld.f11r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB2"); +state->u.f0.fld.f11r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB3"); +state->u.f0.fld.f11r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB4"); +state->u.f0.fld.f11r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB5"); +state->u.f0.fld.f11r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB6"); +state->u.f0.fld.f11r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB7"); +state->u.f0.fld.f11r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB8"); +state->u.f0.fld.f11r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB9"); +state->u.f0.fld.f11r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB10"); +state->u.f0.fld.f11r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB11"); +state->u.f0.fld.f11r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB12"); +state->u.f0.fld.f11r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB13"); +state->u.f0.fld.f11r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB14"); +state->u.f0.fld.f11r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB15"); +state->u.f0.fld.f11r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB16"); +state->u.f0.fld.f11r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB17"); +state->u.f0.fld.f11r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB18"); +state->u.f0.fld.f11r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB19"); +state->u.f0.fld.f11r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB20"); +state->u.f0.fld.f11r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB21"); +state->u.f0.fld.f11r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB22"); +state->u.f0.fld.f11r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB23"); +state->u.f0.fld.f11r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB24"); +state->u.f0.fld.f11r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB25"); +state->u.f0.fld.f11r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB26"); +state->u.f0.fld.f11r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB27"); +state->u.f0.fld.f11r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB28"); +state->u.f0.fld.f11r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB29"); +state->u.f0.fld.f11r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB30"); +state->u.f0.fld.f11r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f11r1, "FB31"); +// F11R2bitfields. +state->u.f0.fld.f11r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB0"); +state->u.f0.fld.f11r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB1"); +state->u.f0.fld.f11r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB2"); +state->u.f0.fld.f11r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB3"); +state->u.f0.fld.f11r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB4"); +state->u.f0.fld.f11r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB5"); +state->u.f0.fld.f11r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB6"); +state->u.f0.fld.f11r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB7"); +state->u.f0.fld.f11r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB8"); +state->u.f0.fld.f11r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB9"); +state->u.f0.fld.f11r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB10"); +state->u.f0.fld.f11r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB11"); +state->u.f0.fld.f11r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB12"); +state->u.f0.fld.f11r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB13"); +state->u.f0.fld.f11r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB14"); +state->u.f0.fld.f11r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB15"); +state->u.f0.fld.f11r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB16"); +state->u.f0.fld.f11r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB17"); +state->u.f0.fld.f11r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB18"); +state->u.f0.fld.f11r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB19"); +state->u.f0.fld.f11r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB20"); +state->u.f0.fld.f11r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB21"); +state->u.f0.fld.f11r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB22"); +state->u.f0.fld.f11r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB23"); +state->u.f0.fld.f11r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB24"); +state->u.f0.fld.f11r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB25"); +state->u.f0.fld.f11r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB26"); +state->u.f0.fld.f11r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB27"); +state->u.f0.fld.f11r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB28"); +state->u.f0.fld.f11r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB29"); +state->u.f0.fld.f11r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB30"); +state->u.f0.fld.f11r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f11r2, "FB31"); +// F12R1bitfields. +state->u.f0.fld.f12r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB0"); +state->u.f0.fld.f12r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB1"); +state->u.f0.fld.f12r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB2"); +state->u.f0.fld.f12r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB3"); +state->u.f0.fld.f12r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB4"); +state->u.f0.fld.f12r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB5"); +state->u.f0.fld.f12r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB6"); +state->u.f0.fld.f12r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB7"); +state->u.f0.fld.f12r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB8"); +state->u.f0.fld.f12r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB9"); +state->u.f0.fld.f12r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB10"); +state->u.f0.fld.f12r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB11"); +state->u.f0.fld.f12r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB12"); +state->u.f0.fld.f12r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB13"); +state->u.f0.fld.f12r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB14"); +state->u.f0.fld.f12r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB15"); +state->u.f0.fld.f12r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB16"); +state->u.f0.fld.f12r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB17"); +state->u.f0.fld.f12r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB18"); +state->u.f0.fld.f12r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB19"); +state->u.f0.fld.f12r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB20"); +state->u.f0.fld.f12r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB21"); +state->u.f0.fld.f12r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB22"); +state->u.f0.fld.f12r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB23"); +state->u.f0.fld.f12r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB24"); +state->u.f0.fld.f12r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB25"); +state->u.f0.fld.f12r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB26"); +state->u.f0.fld.f12r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB27"); +state->u.f0.fld.f12r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB28"); +state->u.f0.fld.f12r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB29"); +state->u.f0.fld.f12r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB30"); +state->u.f0.fld.f12r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f12r1, "FB31"); +// F12R2bitfields. +state->u.f0.fld.f12r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB0"); +state->u.f0.fld.f12r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB1"); +state->u.f0.fld.f12r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB2"); +state->u.f0.fld.f12r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB3"); +state->u.f0.fld.f12r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB4"); +state->u.f0.fld.f12r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB5"); +state->u.f0.fld.f12r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB6"); +state->u.f0.fld.f12r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB7"); +state->u.f0.fld.f12r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB8"); +state->u.f0.fld.f12r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB9"); +state->u.f0.fld.f12r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB10"); +state->u.f0.fld.f12r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB11"); +state->u.f0.fld.f12r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB12"); +state->u.f0.fld.f12r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB13"); +state->u.f0.fld.f12r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB14"); +state->u.f0.fld.f12r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB15"); +state->u.f0.fld.f12r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB16"); +state->u.f0.fld.f12r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB17"); +state->u.f0.fld.f12r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB18"); +state->u.f0.fld.f12r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB19"); +state->u.f0.fld.f12r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB20"); +state->u.f0.fld.f12r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB21"); +state->u.f0.fld.f12r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB22"); +state->u.f0.fld.f12r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB23"); +state->u.f0.fld.f12r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB24"); +state->u.f0.fld.f12r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB25"); +state->u.f0.fld.f12r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB26"); +state->u.f0.fld.f12r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB27"); +state->u.f0.fld.f12r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB28"); +state->u.f0.fld.f12r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB29"); +state->u.f0.fld.f12r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB30"); +state->u.f0.fld.f12r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f12r2, "FB31"); +// F13R1bitfields. +state->u.f0.fld.f13r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB0"); +state->u.f0.fld.f13r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB1"); +state->u.f0.fld.f13r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB2"); +state->u.f0.fld.f13r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB3"); +state->u.f0.fld.f13r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB4"); +state->u.f0.fld.f13r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB5"); +state->u.f0.fld.f13r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB6"); +state->u.f0.fld.f13r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB7"); +state->u.f0.fld.f13r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB8"); +state->u.f0.fld.f13r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB9"); +state->u.f0.fld.f13r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB10"); +state->u.f0.fld.f13r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB11"); +state->u.f0.fld.f13r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB12"); +state->u.f0.fld.f13r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB13"); +state->u.f0.fld.f13r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB14"); +state->u.f0.fld.f13r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB15"); +state->u.f0.fld.f13r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB16"); +state->u.f0.fld.f13r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB17"); +state->u.f0.fld.f13r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB18"); +state->u.f0.fld.f13r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB19"); +state->u.f0.fld.f13r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB20"); +state->u.f0.fld.f13r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB21"); +state->u.f0.fld.f13r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB22"); +state->u.f0.fld.f13r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB23"); +state->u.f0.fld.f13r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB24"); +state->u.f0.fld.f13r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB25"); +state->u.f0.fld.f13r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB26"); +state->u.f0.fld.f13r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB27"); +state->u.f0.fld.f13r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB28"); +state->u.f0.fld.f13r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB29"); +state->u.f0.fld.f13r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB30"); +state->u.f0.fld.f13r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f13r1, "FB31"); +// F13R2bitfields. +state->u.f0.fld.f13r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB0"); +state->u.f0.fld.f13r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB1"); +state->u.f0.fld.f13r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB2"); +state->u.f0.fld.f13r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB3"); +state->u.f0.fld.f13r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB4"); +state->u.f0.fld.f13r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB5"); +state->u.f0.fld.f13r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB6"); +state->u.f0.fld.f13r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB7"); +state->u.f0.fld.f13r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB8"); +state->u.f0.fld.f13r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB9"); +state->u.f0.fld.f13r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB10"); +state->u.f0.fld.f13r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB11"); +state->u.f0.fld.f13r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB12"); +state->u.f0.fld.f13r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB13"); +state->u.f0.fld.f13r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB14"); +state->u.f0.fld.f13r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB15"); +state->u.f0.fld.f13r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB16"); +state->u.f0.fld.f13r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB17"); +state->u.f0.fld.f13r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB18"); +state->u.f0.fld.f13r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB19"); +state->u.f0.fld.f13r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB20"); +state->u.f0.fld.f13r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB21"); +state->u.f0.fld.f13r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB22"); +state->u.f0.fld.f13r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB23"); +state->u.f0.fld.f13r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB24"); +state->u.f0.fld.f13r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB25"); +state->u.f0.fld.f13r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB26"); +state->u.f0.fld.f13r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB27"); +state->u.f0.fld.f13r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB28"); +state->u.f0.fld.f13r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB29"); +state->u.f0.fld.f13r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB30"); +state->u.f0.fld.f13r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f13r2, "FB31"); +// F14R1bitfields. +state->u.f0.fld.f14r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB0"); +state->u.f0.fld.f14r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB1"); +state->u.f0.fld.f14r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB2"); +state->u.f0.fld.f14r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB3"); +state->u.f0.fld.f14r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB4"); +state->u.f0.fld.f14r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB5"); +state->u.f0.fld.f14r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB6"); +state->u.f0.fld.f14r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB7"); +state->u.f0.fld.f14r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB8"); +state->u.f0.fld.f14r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB9"); +state->u.f0.fld.f14r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB10"); +state->u.f0.fld.f14r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB11"); +state->u.f0.fld.f14r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB12"); +state->u.f0.fld.f14r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB13"); +state->u.f0.fld.f14r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB14"); +state->u.f0.fld.f14r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB15"); +state->u.f0.fld.f14r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB16"); +state->u.f0.fld.f14r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB17"); +state->u.f0.fld.f14r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB18"); +state->u.f0.fld.f14r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB19"); +state->u.f0.fld.f14r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB20"); +state->u.f0.fld.f14r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB21"); +state->u.f0.fld.f14r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB22"); +state->u.f0.fld.f14r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB23"); +state->u.f0.fld.f14r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB24"); +state->u.f0.fld.f14r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB25"); +state->u.f0.fld.f14r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB26"); +state->u.f0.fld.f14r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB27"); +state->u.f0.fld.f14r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB28"); +state->u.f0.fld.f14r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB29"); +state->u.f0.fld.f14r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB30"); +state->u.f0.fld.f14r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f14r1, "FB31"); +// F14R2bitfields. +state->u.f0.fld.f14r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB0"); +state->u.f0.fld.f14r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB1"); +state->u.f0.fld.f14r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB2"); +state->u.f0.fld.f14r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB3"); +state->u.f0.fld.f14r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB4"); +state->u.f0.fld.f14r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB5"); +state->u.f0.fld.f14r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB6"); +state->u.f0.fld.f14r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB7"); +state->u.f0.fld.f14r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB8"); +state->u.f0.fld.f14r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB9"); +state->u.f0.fld.f14r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB10"); +state->u.f0.fld.f14r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB11"); +state->u.f0.fld.f14r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB12"); +state->u.f0.fld.f14r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB13"); +state->u.f0.fld.f14r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB14"); +state->u.f0.fld.f14r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB15"); +state->u.f0.fld.f14r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB16"); +state->u.f0.fld.f14r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB17"); +state->u.f0.fld.f14r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB18"); +state->u.f0.fld.f14r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB19"); +state->u.f0.fld.f14r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB20"); +state->u.f0.fld.f14r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB21"); +state->u.f0.fld.f14r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB22"); +state->u.f0.fld.f14r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB23"); +state->u.f0.fld.f14r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB24"); +state->u.f0.fld.f14r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB25"); +state->u.f0.fld.f14r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB26"); +state->u.f0.fld.f14r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB27"); +state->u.f0.fld.f14r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB28"); +state->u.f0.fld.f14r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB29"); +state->u.f0.fld.f14r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB30"); +state->u.f0.fld.f14r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f14r2, "FB31"); +// F15R1bitfields. +state->u.f0.fld.f15r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB0"); +state->u.f0.fld.f15r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB1"); +state->u.f0.fld.f15r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB2"); +state->u.f0.fld.f15r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB3"); +state->u.f0.fld.f15r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB4"); +state->u.f0.fld.f15r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB5"); +state->u.f0.fld.f15r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB6"); +state->u.f0.fld.f15r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB7"); +state->u.f0.fld.f15r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB8"); +state->u.f0.fld.f15r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB9"); +state->u.f0.fld.f15r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB10"); +state->u.f0.fld.f15r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB11"); +state->u.f0.fld.f15r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB12"); +state->u.f0.fld.f15r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB13"); +state->u.f0.fld.f15r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB14"); +state->u.f0.fld.f15r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB15"); +state->u.f0.fld.f15r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB16"); +state->u.f0.fld.f15r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB17"); +state->u.f0.fld.f15r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB18"); +state->u.f0.fld.f15r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB19"); +state->u.f0.fld.f15r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB20"); +state->u.f0.fld.f15r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB21"); +state->u.f0.fld.f15r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB22"); +state->u.f0.fld.f15r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB23"); +state->u.f0.fld.f15r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB24"); +state->u.f0.fld.f15r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB25"); +state->u.f0.fld.f15r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB26"); +state->u.f0.fld.f15r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB27"); +state->u.f0.fld.f15r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB28"); +state->u.f0.fld.f15r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB29"); +state->u.f0.fld.f15r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB30"); +state->u.f0.fld.f15r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f15r1, "FB31"); +// F15R2bitfields. +state->u.f0.fld.f15r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB0"); +state->u.f0.fld.f15r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB1"); +state->u.f0.fld.f15r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB2"); +state->u.f0.fld.f15r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB3"); +state->u.f0.fld.f15r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB4"); +state->u.f0.fld.f15r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB5"); +state->u.f0.fld.f15r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB6"); +state->u.f0.fld.f15r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB7"); +state->u.f0.fld.f15r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB8"); +state->u.f0.fld.f15r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB9"); +state->u.f0.fld.f15r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB10"); +state->u.f0.fld.f15r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB11"); +state->u.f0.fld.f15r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB12"); +state->u.f0.fld.f15r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB13"); +state->u.f0.fld.f15r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB14"); +state->u.f0.fld.f15r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB15"); +state->u.f0.fld.f15r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB16"); +state->u.f0.fld.f15r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB17"); +state->u.f0.fld.f15r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB18"); +state->u.f0.fld.f15r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB19"); +state->u.f0.fld.f15r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB20"); +state->u.f0.fld.f15r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB21"); +state->u.f0.fld.f15r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB22"); +state->u.f0.fld.f15r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB23"); +state->u.f0.fld.f15r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB24"); +state->u.f0.fld.f15r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB25"); +state->u.f0.fld.f15r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB26"); +state->u.f0.fld.f15r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB27"); +state->u.f0.fld.f15r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB28"); +state->u.f0.fld.f15r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB29"); +state->u.f0.fld.f15r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB30"); +state->u.f0.fld.f15r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f15r2, "FB31"); +// F16R1bitfields. +state->u.f0.fld.f16r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB0"); +state->u.f0.fld.f16r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB1"); +state->u.f0.fld.f16r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB2"); +state->u.f0.fld.f16r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB3"); +state->u.f0.fld.f16r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB4"); +state->u.f0.fld.f16r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB5"); +state->u.f0.fld.f16r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB6"); +state->u.f0.fld.f16r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB7"); +state->u.f0.fld.f16r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB8"); +state->u.f0.fld.f16r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB9"); +state->u.f0.fld.f16r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB10"); +state->u.f0.fld.f16r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB11"); +state->u.f0.fld.f16r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB12"); +state->u.f0.fld.f16r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB13"); +state->u.f0.fld.f16r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB14"); +state->u.f0.fld.f16r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB15"); +state->u.f0.fld.f16r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB16"); +state->u.f0.fld.f16r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB17"); +state->u.f0.fld.f16r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB18"); +state->u.f0.fld.f16r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB19"); +state->u.f0.fld.f16r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB20"); +state->u.f0.fld.f16r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB21"); +state->u.f0.fld.f16r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB22"); +state->u.f0.fld.f16r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB23"); +state->u.f0.fld.f16r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB24"); +state->u.f0.fld.f16r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB25"); +state->u.f0.fld.f16r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB26"); +state->u.f0.fld.f16r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB27"); +state->u.f0.fld.f16r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB28"); +state->u.f0.fld.f16r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB29"); +state->u.f0.fld.f16r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB30"); +state->u.f0.fld.f16r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f16r1, "FB31"); +// F16R2bitfields. +state->u.f0.fld.f16r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB0"); +state->u.f0.fld.f16r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB1"); +state->u.f0.fld.f16r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB2"); +state->u.f0.fld.f16r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB3"); +state->u.f0.fld.f16r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB4"); +state->u.f0.fld.f16r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB5"); +state->u.f0.fld.f16r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB6"); +state->u.f0.fld.f16r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB7"); +state->u.f0.fld.f16r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB8"); +state->u.f0.fld.f16r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB9"); +state->u.f0.fld.f16r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB10"); +state->u.f0.fld.f16r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB11"); +state->u.f0.fld.f16r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB12"); +state->u.f0.fld.f16r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB13"); +state->u.f0.fld.f16r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB14"); +state->u.f0.fld.f16r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB15"); +state->u.f0.fld.f16r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB16"); +state->u.f0.fld.f16r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB17"); +state->u.f0.fld.f16r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB18"); +state->u.f0.fld.f16r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB19"); +state->u.f0.fld.f16r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB20"); +state->u.f0.fld.f16r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB21"); +state->u.f0.fld.f16r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB22"); +state->u.f0.fld.f16r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB23"); +state->u.f0.fld.f16r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB24"); +state->u.f0.fld.f16r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB25"); +state->u.f0.fld.f16r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB26"); +state->u.f0.fld.f16r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB27"); +state->u.f0.fld.f16r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB28"); +state->u.f0.fld.f16r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB29"); +state->u.f0.fld.f16r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB30"); +state->u.f0.fld.f16r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f16r2, "FB31"); +// F17R1bitfields. +state->u.f0.fld.f17r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB0"); +state->u.f0.fld.f17r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB1"); +state->u.f0.fld.f17r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB2"); +state->u.f0.fld.f17r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB3"); +state->u.f0.fld.f17r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB4"); +state->u.f0.fld.f17r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB5"); +state->u.f0.fld.f17r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB6"); +state->u.f0.fld.f17r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB7"); +state->u.f0.fld.f17r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB8"); +state->u.f0.fld.f17r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB9"); +state->u.f0.fld.f17r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB10"); +state->u.f0.fld.f17r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB11"); +state->u.f0.fld.f17r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB12"); +state->u.f0.fld.f17r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB13"); +state->u.f0.fld.f17r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB14"); +state->u.f0.fld.f17r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB15"); +state->u.f0.fld.f17r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB16"); +state->u.f0.fld.f17r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB17"); +state->u.f0.fld.f17r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB18"); +state->u.f0.fld.f17r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB19"); +state->u.f0.fld.f17r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB20"); +state->u.f0.fld.f17r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB21"); +state->u.f0.fld.f17r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB22"); +state->u.f0.fld.f17r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB23"); +state->u.f0.fld.f17r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB24"); +state->u.f0.fld.f17r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB25"); +state->u.f0.fld.f17r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB26"); +state->u.f0.fld.f17r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB27"); +state->u.f0.fld.f17r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB28"); +state->u.f0.fld.f17r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB29"); +state->u.f0.fld.f17r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB30"); +state->u.f0.fld.f17r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f17r1, "FB31"); +// F17R2bitfields. +state->u.f0.fld.f17r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB0"); +state->u.f0.fld.f17r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB1"); +state->u.f0.fld.f17r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB2"); +state->u.f0.fld.f17r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB3"); +state->u.f0.fld.f17r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB4"); +state->u.f0.fld.f17r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB5"); +state->u.f0.fld.f17r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB6"); +state->u.f0.fld.f17r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB7"); +state->u.f0.fld.f17r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB8"); +state->u.f0.fld.f17r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB9"); +state->u.f0.fld.f17r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB10"); +state->u.f0.fld.f17r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB11"); +state->u.f0.fld.f17r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB12"); +state->u.f0.fld.f17r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB13"); +state->u.f0.fld.f17r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB14"); +state->u.f0.fld.f17r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB15"); +state->u.f0.fld.f17r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB16"); +state->u.f0.fld.f17r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB17"); +state->u.f0.fld.f17r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB18"); +state->u.f0.fld.f17r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB19"); +state->u.f0.fld.f17r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB20"); +state->u.f0.fld.f17r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB21"); +state->u.f0.fld.f17r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB22"); +state->u.f0.fld.f17r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB23"); +state->u.f0.fld.f17r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB24"); +state->u.f0.fld.f17r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB25"); +state->u.f0.fld.f17r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB26"); +state->u.f0.fld.f17r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB27"); +state->u.f0.fld.f17r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB28"); +state->u.f0.fld.f17r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB29"); +state->u.f0.fld.f17r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB30"); +state->u.f0.fld.f17r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f17r2, "FB31"); +// F18R1bitfields. +state->u.f0.fld.f18r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB0"); +state->u.f0.fld.f18r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB1"); +state->u.f0.fld.f18r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB2"); +state->u.f0.fld.f18r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB3"); +state->u.f0.fld.f18r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB4"); +state->u.f0.fld.f18r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB5"); +state->u.f0.fld.f18r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB6"); +state->u.f0.fld.f18r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB7"); +state->u.f0.fld.f18r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB8"); +state->u.f0.fld.f18r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB9"); +state->u.f0.fld.f18r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB10"); +state->u.f0.fld.f18r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB11"); +state->u.f0.fld.f18r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB12"); +state->u.f0.fld.f18r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB13"); +state->u.f0.fld.f18r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB14"); +state->u.f0.fld.f18r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB15"); +state->u.f0.fld.f18r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB16"); +state->u.f0.fld.f18r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB17"); +state->u.f0.fld.f18r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB18"); +state->u.f0.fld.f18r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB19"); +state->u.f0.fld.f18r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB20"); +state->u.f0.fld.f18r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB21"); +state->u.f0.fld.f18r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB22"); +state->u.f0.fld.f18r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB23"); +state->u.f0.fld.f18r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB24"); +state->u.f0.fld.f18r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB25"); +state->u.f0.fld.f18r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB26"); +state->u.f0.fld.f18r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB27"); +state->u.f0.fld.f18r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB28"); +state->u.f0.fld.f18r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB29"); +state->u.f0.fld.f18r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB30"); +state->u.f0.fld.f18r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f18r1, "FB31"); +// F18R2bitfields. +state->u.f0.fld.f18r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB0"); +state->u.f0.fld.f18r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB1"); +state->u.f0.fld.f18r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB2"); +state->u.f0.fld.f18r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB3"); +state->u.f0.fld.f18r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB4"); +state->u.f0.fld.f18r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB5"); +state->u.f0.fld.f18r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB6"); +state->u.f0.fld.f18r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB7"); +state->u.f0.fld.f18r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB8"); +state->u.f0.fld.f18r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB9"); +state->u.f0.fld.f18r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB10"); +state->u.f0.fld.f18r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB11"); +state->u.f0.fld.f18r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB12"); +state->u.f0.fld.f18r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB13"); +state->u.f0.fld.f18r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB14"); +state->u.f0.fld.f18r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB15"); +state->u.f0.fld.f18r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB16"); +state->u.f0.fld.f18r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB17"); +state->u.f0.fld.f18r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB18"); +state->u.f0.fld.f18r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB19"); +state->u.f0.fld.f18r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB20"); +state->u.f0.fld.f18r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB21"); +state->u.f0.fld.f18r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB22"); +state->u.f0.fld.f18r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB23"); +state->u.f0.fld.f18r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB24"); +state->u.f0.fld.f18r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB25"); +state->u.f0.fld.f18r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB26"); +state->u.f0.fld.f18r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB27"); +state->u.f0.fld.f18r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB28"); +state->u.f0.fld.f18r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB29"); +state->u.f0.fld.f18r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB30"); +state->u.f0.fld.f18r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f18r2, "FB31"); +// F19R1bitfields. +state->u.f0.fld.f19r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB0"); +state->u.f0.fld.f19r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB1"); +state->u.f0.fld.f19r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB2"); +state->u.f0.fld.f19r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB3"); +state->u.f0.fld.f19r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB4"); +state->u.f0.fld.f19r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB5"); +state->u.f0.fld.f19r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB6"); +state->u.f0.fld.f19r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB7"); +state->u.f0.fld.f19r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB8"); +state->u.f0.fld.f19r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB9"); +state->u.f0.fld.f19r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB10"); +state->u.f0.fld.f19r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB11"); +state->u.f0.fld.f19r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB12"); +state->u.f0.fld.f19r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB13"); +state->u.f0.fld.f19r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB14"); +state->u.f0.fld.f19r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB15"); +state->u.f0.fld.f19r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB16"); +state->u.f0.fld.f19r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB17"); +state->u.f0.fld.f19r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB18"); +state->u.f0.fld.f19r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB19"); +state->u.f0.fld.f19r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB20"); +state->u.f0.fld.f19r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB21"); +state->u.f0.fld.f19r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB22"); +state->u.f0.fld.f19r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB23"); +state->u.f0.fld.f19r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB24"); +state->u.f0.fld.f19r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB25"); +state->u.f0.fld.f19r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB26"); +state->u.f0.fld.f19r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB27"); +state->u.f0.fld.f19r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB28"); +state->u.f0.fld.f19r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB29"); +state->u.f0.fld.f19r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB30"); +state->u.f0.fld.f19r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f19r1, "FB31"); +// F19R2bitfields. +state->u.f0.fld.f19r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB0"); +state->u.f0.fld.f19r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB1"); +state->u.f0.fld.f19r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB2"); +state->u.f0.fld.f19r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB3"); +state->u.f0.fld.f19r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB4"); +state->u.f0.fld.f19r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB5"); +state->u.f0.fld.f19r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB6"); +state->u.f0.fld.f19r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB7"); +state->u.f0.fld.f19r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB8"); +state->u.f0.fld.f19r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB9"); +state->u.f0.fld.f19r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB10"); +state->u.f0.fld.f19r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB11"); +state->u.f0.fld.f19r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB12"); +state->u.f0.fld.f19r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB13"); +state->u.f0.fld.f19r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB14"); +state->u.f0.fld.f19r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB15"); +state->u.f0.fld.f19r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB16"); +state->u.f0.fld.f19r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB17"); +state->u.f0.fld.f19r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB18"); +state->u.f0.fld.f19r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB19"); +state->u.f0.fld.f19r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB20"); +state->u.f0.fld.f19r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB21"); +state->u.f0.fld.f19r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB22"); +state->u.f0.fld.f19r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB23"); +state->u.f0.fld.f19r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB24"); +state->u.f0.fld.f19r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB25"); +state->u.f0.fld.f19r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB26"); +state->u.f0.fld.f19r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB27"); +state->u.f0.fld.f19r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB28"); +state->u.f0.fld.f19r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB29"); +state->u.f0.fld.f19r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB30"); +state->u.f0.fld.f19r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f19r2, "FB31"); +// F20R1bitfields. +state->u.f0.fld.f20r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB0"); +state->u.f0.fld.f20r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB1"); +state->u.f0.fld.f20r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB2"); +state->u.f0.fld.f20r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB3"); +state->u.f0.fld.f20r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB4"); +state->u.f0.fld.f20r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB5"); +state->u.f0.fld.f20r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB6"); +state->u.f0.fld.f20r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB7"); +state->u.f0.fld.f20r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB8"); +state->u.f0.fld.f20r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB9"); +state->u.f0.fld.f20r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB10"); +state->u.f0.fld.f20r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB11"); +state->u.f0.fld.f20r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB12"); +state->u.f0.fld.f20r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB13"); +state->u.f0.fld.f20r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB14"); +state->u.f0.fld.f20r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB15"); +state->u.f0.fld.f20r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB16"); +state->u.f0.fld.f20r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB17"); +state->u.f0.fld.f20r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB18"); +state->u.f0.fld.f20r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB19"); +state->u.f0.fld.f20r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB20"); +state->u.f0.fld.f20r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB21"); +state->u.f0.fld.f20r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB22"); +state->u.f0.fld.f20r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB23"); +state->u.f0.fld.f20r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB24"); +state->u.f0.fld.f20r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB25"); +state->u.f0.fld.f20r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB26"); +state->u.f0.fld.f20r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB27"); +state->u.f0.fld.f20r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB28"); +state->u.f0.fld.f20r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB29"); +state->u.f0.fld.f20r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB30"); +state->u.f0.fld.f20r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f20r1, "FB31"); +// F20R2bitfields. +state->u.f0.fld.f20r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB0"); +state->u.f0.fld.f20r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB1"); +state->u.f0.fld.f20r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB2"); +state->u.f0.fld.f20r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB3"); +state->u.f0.fld.f20r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB4"); +state->u.f0.fld.f20r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB5"); +state->u.f0.fld.f20r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB6"); +state->u.f0.fld.f20r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB7"); +state->u.f0.fld.f20r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB8"); +state->u.f0.fld.f20r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB9"); +state->u.f0.fld.f20r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB10"); +state->u.f0.fld.f20r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB11"); +state->u.f0.fld.f20r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB12"); +state->u.f0.fld.f20r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB13"); +state->u.f0.fld.f20r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB14"); +state->u.f0.fld.f20r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB15"); +state->u.f0.fld.f20r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB16"); +state->u.f0.fld.f20r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB17"); +state->u.f0.fld.f20r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB18"); +state->u.f0.fld.f20r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB19"); +state->u.f0.fld.f20r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB20"); +state->u.f0.fld.f20r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB21"); +state->u.f0.fld.f20r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB22"); +state->u.f0.fld.f20r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB23"); +state->u.f0.fld.f20r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB24"); +state->u.f0.fld.f20r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB25"); +state->u.f0.fld.f20r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB26"); +state->u.f0.fld.f20r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB27"); +state->u.f0.fld.f20r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB28"); +state->u.f0.fld.f20r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB29"); +state->u.f0.fld.f20r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB30"); +state->u.f0.fld.f20r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f20r2, "FB31"); +// F21R1bitfields. +state->u.f0.fld.f21r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB0"); +state->u.f0.fld.f21r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB1"); +state->u.f0.fld.f21r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB2"); +state->u.f0.fld.f21r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB3"); +state->u.f0.fld.f21r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB4"); +state->u.f0.fld.f21r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB5"); +state->u.f0.fld.f21r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB6"); +state->u.f0.fld.f21r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB7"); +state->u.f0.fld.f21r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB8"); +state->u.f0.fld.f21r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB9"); +state->u.f0.fld.f21r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB10"); +state->u.f0.fld.f21r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB11"); +state->u.f0.fld.f21r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB12"); +state->u.f0.fld.f21r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB13"); +state->u.f0.fld.f21r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB14"); +state->u.f0.fld.f21r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB15"); +state->u.f0.fld.f21r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB16"); +state->u.f0.fld.f21r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB17"); +state->u.f0.fld.f21r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB18"); +state->u.f0.fld.f21r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB19"); +state->u.f0.fld.f21r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB20"); +state->u.f0.fld.f21r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB21"); +state->u.f0.fld.f21r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB22"); +state->u.f0.fld.f21r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB23"); +state->u.f0.fld.f21r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB24"); +state->u.f0.fld.f21r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB25"); +state->u.f0.fld.f21r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB26"); +state->u.f0.fld.f21r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB27"); +state->u.f0.fld.f21r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB28"); +state->u.f0.fld.f21r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB29"); +state->u.f0.fld.f21r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB30"); +state->u.f0.fld.f21r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f21r1, "FB31"); +// F21R2bitfields. +state->u.f0.fld.f21r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB0"); +state->u.f0.fld.f21r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB1"); +state->u.f0.fld.f21r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB2"); +state->u.f0.fld.f21r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB3"); +state->u.f0.fld.f21r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB4"); +state->u.f0.fld.f21r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB5"); +state->u.f0.fld.f21r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB6"); +state->u.f0.fld.f21r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB7"); +state->u.f0.fld.f21r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB8"); +state->u.f0.fld.f21r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB9"); +state->u.f0.fld.f21r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB10"); +state->u.f0.fld.f21r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB11"); +state->u.f0.fld.f21r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB12"); +state->u.f0.fld.f21r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB13"); +state->u.f0.fld.f21r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB14"); +state->u.f0.fld.f21r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB15"); +state->u.f0.fld.f21r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB16"); +state->u.f0.fld.f21r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB17"); +state->u.f0.fld.f21r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB18"); +state->u.f0.fld.f21r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB19"); +state->u.f0.fld.f21r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB20"); +state->u.f0.fld.f21r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB21"); +state->u.f0.fld.f21r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB22"); +state->u.f0.fld.f21r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB23"); +state->u.f0.fld.f21r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB24"); +state->u.f0.fld.f21r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB25"); +state->u.f0.fld.f21r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB26"); +state->u.f0.fld.f21r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB27"); +state->u.f0.fld.f21r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB28"); +state->u.f0.fld.f21r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB29"); +state->u.f0.fld.f21r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB30"); +state->u.f0.fld.f21r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f21r2, "FB31"); +// F22R1bitfields. +state->u.f0.fld.f22r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB0"); +state->u.f0.fld.f22r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB1"); +state->u.f0.fld.f22r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB2"); +state->u.f0.fld.f22r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB3"); +state->u.f0.fld.f22r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB4"); +state->u.f0.fld.f22r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB5"); +state->u.f0.fld.f22r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB6"); +state->u.f0.fld.f22r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB7"); +state->u.f0.fld.f22r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB8"); +state->u.f0.fld.f22r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB9"); +state->u.f0.fld.f22r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB10"); +state->u.f0.fld.f22r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB11"); +state->u.f0.fld.f22r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB12"); +state->u.f0.fld.f22r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB13"); +state->u.f0.fld.f22r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB14"); +state->u.f0.fld.f22r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB15"); +state->u.f0.fld.f22r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB16"); +state->u.f0.fld.f22r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB17"); +state->u.f0.fld.f22r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB18"); +state->u.f0.fld.f22r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB19"); +state->u.f0.fld.f22r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB20"); +state->u.f0.fld.f22r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB21"); +state->u.f0.fld.f22r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB22"); +state->u.f0.fld.f22r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB23"); +state->u.f0.fld.f22r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB24"); +state->u.f0.fld.f22r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB25"); +state->u.f0.fld.f22r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB26"); +state->u.f0.fld.f22r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB27"); +state->u.f0.fld.f22r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB28"); +state->u.f0.fld.f22r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB29"); +state->u.f0.fld.f22r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB30"); +state->u.f0.fld.f22r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f22r1, "FB31"); +// F22R2bitfields. +state->u.f0.fld.f22r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB0"); +state->u.f0.fld.f22r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB1"); +state->u.f0.fld.f22r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB2"); +state->u.f0.fld.f22r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB3"); +state->u.f0.fld.f22r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB4"); +state->u.f0.fld.f22r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB5"); +state->u.f0.fld.f22r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB6"); +state->u.f0.fld.f22r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB7"); +state->u.f0.fld.f22r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB8"); +state->u.f0.fld.f22r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB9"); +state->u.f0.fld.f22r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB10"); +state->u.f0.fld.f22r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB11"); +state->u.f0.fld.f22r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB12"); +state->u.f0.fld.f22r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB13"); +state->u.f0.fld.f22r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB14"); +state->u.f0.fld.f22r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB15"); +state->u.f0.fld.f22r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB16"); +state->u.f0.fld.f22r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB17"); +state->u.f0.fld.f22r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB18"); +state->u.f0.fld.f22r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB19"); +state->u.f0.fld.f22r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB20"); +state->u.f0.fld.f22r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB21"); +state->u.f0.fld.f22r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB22"); +state->u.f0.fld.f22r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB23"); +state->u.f0.fld.f22r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB24"); +state->u.f0.fld.f22r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB25"); +state->u.f0.fld.f22r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB26"); +state->u.f0.fld.f22r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB27"); +state->u.f0.fld.f22r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB28"); +state->u.f0.fld.f22r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB29"); +state->u.f0.fld.f22r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB30"); +state->u.f0.fld.f22r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f22r2, "FB31"); +// F23R1bitfields. +state->u.f0.fld.f23r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB0"); +state->u.f0.fld.f23r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB1"); +state->u.f0.fld.f23r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB2"); +state->u.f0.fld.f23r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB3"); +state->u.f0.fld.f23r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB4"); +state->u.f0.fld.f23r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB5"); +state->u.f0.fld.f23r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB6"); +state->u.f0.fld.f23r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB7"); +state->u.f0.fld.f23r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB8"); +state->u.f0.fld.f23r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB9"); +state->u.f0.fld.f23r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB10"); +state->u.f0.fld.f23r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB11"); +state->u.f0.fld.f23r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB12"); +state->u.f0.fld.f23r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB13"); +state->u.f0.fld.f23r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB14"); +state->u.f0.fld.f23r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB15"); +state->u.f0.fld.f23r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB16"); +state->u.f0.fld.f23r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB17"); +state->u.f0.fld.f23r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB18"); +state->u.f0.fld.f23r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB19"); +state->u.f0.fld.f23r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB20"); +state->u.f0.fld.f23r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB21"); +state->u.f0.fld.f23r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB22"); +state->u.f0.fld.f23r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB23"); +state->u.f0.fld.f23r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB24"); +state->u.f0.fld.f23r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB25"); +state->u.f0.fld.f23r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB26"); +state->u.f0.fld.f23r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB27"); +state->u.f0.fld.f23r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB28"); +state->u.f0.fld.f23r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB29"); +state->u.f0.fld.f23r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB30"); +state->u.f0.fld.f23r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f23r1, "FB31"); +// F23R2bitfields. +state->u.f0.fld.f23r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB0"); +state->u.f0.fld.f23r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB1"); +state->u.f0.fld.f23r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB2"); +state->u.f0.fld.f23r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB3"); +state->u.f0.fld.f23r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB4"); +state->u.f0.fld.f23r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB5"); +state->u.f0.fld.f23r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB6"); +state->u.f0.fld.f23r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB7"); +state->u.f0.fld.f23r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB8"); +state->u.f0.fld.f23r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB9"); +state->u.f0.fld.f23r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB10"); +state->u.f0.fld.f23r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB11"); +state->u.f0.fld.f23r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB12"); +state->u.f0.fld.f23r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB13"); +state->u.f0.fld.f23r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB14"); +state->u.f0.fld.f23r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB15"); +state->u.f0.fld.f23r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB16"); +state->u.f0.fld.f23r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB17"); +state->u.f0.fld.f23r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB18"); +state->u.f0.fld.f23r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB19"); +state->u.f0.fld.f23r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB20"); +state->u.f0.fld.f23r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB21"); +state->u.f0.fld.f23r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB22"); +state->u.f0.fld.f23r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB23"); +state->u.f0.fld.f23r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB24"); +state->u.f0.fld.f23r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB25"); +state->u.f0.fld.f23r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB26"); +state->u.f0.fld.f23r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB27"); +state->u.f0.fld.f23r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB28"); +state->u.f0.fld.f23r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB29"); +state->u.f0.fld.f23r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB30"); +state->u.f0.fld.f23r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f23r2, "FB31"); +// F24R1bitfields. +state->u.f0.fld.f24r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB0"); +state->u.f0.fld.f24r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB1"); +state->u.f0.fld.f24r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB2"); +state->u.f0.fld.f24r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB3"); +state->u.f0.fld.f24r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB4"); +state->u.f0.fld.f24r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB5"); +state->u.f0.fld.f24r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB6"); +state->u.f0.fld.f24r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB7"); +state->u.f0.fld.f24r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB8"); +state->u.f0.fld.f24r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB9"); +state->u.f0.fld.f24r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB10"); +state->u.f0.fld.f24r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB11"); +state->u.f0.fld.f24r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB12"); +state->u.f0.fld.f24r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB13"); +state->u.f0.fld.f24r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB14"); +state->u.f0.fld.f24r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB15"); +state->u.f0.fld.f24r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB16"); +state->u.f0.fld.f24r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB17"); +state->u.f0.fld.f24r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB18"); +state->u.f0.fld.f24r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB19"); +state->u.f0.fld.f24r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB20"); +state->u.f0.fld.f24r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB21"); +state->u.f0.fld.f24r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB22"); +state->u.f0.fld.f24r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB23"); +state->u.f0.fld.f24r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB24"); +state->u.f0.fld.f24r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB25"); +state->u.f0.fld.f24r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB26"); +state->u.f0.fld.f24r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB27"); +state->u.f0.fld.f24r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB28"); +state->u.f0.fld.f24r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB29"); +state->u.f0.fld.f24r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB30"); +state->u.f0.fld.f24r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f24r1, "FB31"); +// F24R2bitfields. +state->u.f0.fld.f24r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB0"); +state->u.f0.fld.f24r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB1"); +state->u.f0.fld.f24r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB2"); +state->u.f0.fld.f24r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB3"); +state->u.f0.fld.f24r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB4"); +state->u.f0.fld.f24r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB5"); +state->u.f0.fld.f24r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB6"); +state->u.f0.fld.f24r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB7"); +state->u.f0.fld.f24r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB8"); +state->u.f0.fld.f24r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB9"); +state->u.f0.fld.f24r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB10"); +state->u.f0.fld.f24r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB11"); +state->u.f0.fld.f24r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB12"); +state->u.f0.fld.f24r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB13"); +state->u.f0.fld.f24r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB14"); +state->u.f0.fld.f24r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB15"); +state->u.f0.fld.f24r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB16"); +state->u.f0.fld.f24r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB17"); +state->u.f0.fld.f24r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB18"); +state->u.f0.fld.f24r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB19"); +state->u.f0.fld.f24r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB20"); +state->u.f0.fld.f24r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB21"); +state->u.f0.fld.f24r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB22"); +state->u.f0.fld.f24r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB23"); +state->u.f0.fld.f24r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB24"); +state->u.f0.fld.f24r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB25"); +state->u.f0.fld.f24r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB26"); +state->u.f0.fld.f24r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB27"); +state->u.f0.fld.f24r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB28"); +state->u.f0.fld.f24r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB29"); +state->u.f0.fld.f24r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB30"); +state->u.f0.fld.f24r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f24r2, "FB31"); +// F25R1bitfields. +state->u.f0.fld.f25r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB0"); +state->u.f0.fld.f25r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB1"); +state->u.f0.fld.f25r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB2"); +state->u.f0.fld.f25r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB3"); +state->u.f0.fld.f25r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB4"); +state->u.f0.fld.f25r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB5"); +state->u.f0.fld.f25r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB6"); +state->u.f0.fld.f25r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB7"); +state->u.f0.fld.f25r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB8"); +state->u.f0.fld.f25r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB9"); +state->u.f0.fld.f25r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB10"); +state->u.f0.fld.f25r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB11"); +state->u.f0.fld.f25r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB12"); +state->u.f0.fld.f25r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB13"); +state->u.f0.fld.f25r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB14"); +state->u.f0.fld.f25r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB15"); +state->u.f0.fld.f25r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB16"); +state->u.f0.fld.f25r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB17"); +state->u.f0.fld.f25r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB18"); +state->u.f0.fld.f25r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB19"); +state->u.f0.fld.f25r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB20"); +state->u.f0.fld.f25r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB21"); +state->u.f0.fld.f25r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB22"); +state->u.f0.fld.f25r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB23"); +state->u.f0.fld.f25r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB24"); +state->u.f0.fld.f25r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB25"); +state->u.f0.fld.f25r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB26"); +state->u.f0.fld.f25r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB27"); +state->u.f0.fld.f25r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB28"); +state->u.f0.fld.f25r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB29"); +state->u.f0.fld.f25r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB30"); +state->u.f0.fld.f25r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f25r1, "FB31"); +// F25R2bitfields. +state->u.f0.fld.f25r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB0"); +state->u.f0.fld.f25r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB1"); +state->u.f0.fld.f25r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB2"); +state->u.f0.fld.f25r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB3"); +state->u.f0.fld.f25r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB4"); +state->u.f0.fld.f25r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB5"); +state->u.f0.fld.f25r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB6"); +state->u.f0.fld.f25r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB7"); +state->u.f0.fld.f25r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB8"); +state->u.f0.fld.f25r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB9"); +state->u.f0.fld.f25r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB10"); +state->u.f0.fld.f25r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB11"); +state->u.f0.fld.f25r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB12"); +state->u.f0.fld.f25r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB13"); +state->u.f0.fld.f25r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB14"); +state->u.f0.fld.f25r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB15"); +state->u.f0.fld.f25r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB16"); +state->u.f0.fld.f25r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB17"); +state->u.f0.fld.f25r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB18"); +state->u.f0.fld.f25r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB19"); +state->u.f0.fld.f25r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB20"); +state->u.f0.fld.f25r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB21"); +state->u.f0.fld.f25r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB22"); +state->u.f0.fld.f25r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB23"); +state->u.f0.fld.f25r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB24"); +state->u.f0.fld.f25r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB25"); +state->u.f0.fld.f25r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB26"); +state->u.f0.fld.f25r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB27"); +state->u.f0.fld.f25r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB28"); +state->u.f0.fld.f25r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB29"); +state->u.f0.fld.f25r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB30"); +state->u.f0.fld.f25r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f25r2, "FB31"); +// F26R1bitfields. +state->u.f0.fld.f26r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB0"); +state->u.f0.fld.f26r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB1"); +state->u.f0.fld.f26r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB2"); +state->u.f0.fld.f26r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB3"); +state->u.f0.fld.f26r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB4"); +state->u.f0.fld.f26r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB5"); +state->u.f0.fld.f26r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB6"); +state->u.f0.fld.f26r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB7"); +state->u.f0.fld.f26r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB8"); +state->u.f0.fld.f26r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB9"); +state->u.f0.fld.f26r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB10"); +state->u.f0.fld.f26r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB11"); +state->u.f0.fld.f26r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB12"); +state->u.f0.fld.f26r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB13"); +state->u.f0.fld.f26r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB14"); +state->u.f0.fld.f26r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB15"); +state->u.f0.fld.f26r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB16"); +state->u.f0.fld.f26r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB17"); +state->u.f0.fld.f26r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB18"); +state->u.f0.fld.f26r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB19"); +state->u.f0.fld.f26r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB20"); +state->u.f0.fld.f26r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB21"); +state->u.f0.fld.f26r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB22"); +state->u.f0.fld.f26r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB23"); +state->u.f0.fld.f26r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB24"); +state->u.f0.fld.f26r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB25"); +state->u.f0.fld.f26r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB26"); +state->u.f0.fld.f26r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB27"); +state->u.f0.fld.f26r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB28"); +state->u.f0.fld.f26r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB29"); +state->u.f0.fld.f26r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB30"); +state->u.f0.fld.f26r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f26r1, "FB31"); +// F26R2bitfields. +state->u.f0.fld.f26r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB0"); +state->u.f0.fld.f26r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB1"); +state->u.f0.fld.f26r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB2"); +state->u.f0.fld.f26r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB3"); +state->u.f0.fld.f26r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB4"); +state->u.f0.fld.f26r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB5"); +state->u.f0.fld.f26r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB6"); +state->u.f0.fld.f26r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB7"); +state->u.f0.fld.f26r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB8"); +state->u.f0.fld.f26r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB9"); +state->u.f0.fld.f26r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB10"); +state->u.f0.fld.f26r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB11"); +state->u.f0.fld.f26r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB12"); +state->u.f0.fld.f26r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB13"); +state->u.f0.fld.f26r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB14"); +state->u.f0.fld.f26r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB15"); +state->u.f0.fld.f26r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB16"); +state->u.f0.fld.f26r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB17"); +state->u.f0.fld.f26r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB18"); +state->u.f0.fld.f26r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB19"); +state->u.f0.fld.f26r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB20"); +state->u.f0.fld.f26r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB21"); +state->u.f0.fld.f26r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB22"); +state->u.f0.fld.f26r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB23"); +state->u.f0.fld.f26r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB24"); +state->u.f0.fld.f26r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB25"); +state->u.f0.fld.f26r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB26"); +state->u.f0.fld.f26r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB27"); +state->u.f0.fld.f26r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB28"); +state->u.f0.fld.f26r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB29"); +state->u.f0.fld.f26r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB30"); +state->u.f0.fld.f26r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f26r2, "FB31"); +// F27R1bitfields. +state->u.f0.fld.f27r1.fb0= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB0"); +state->u.f0.fld.f27r1.fb1= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB1"); +state->u.f0.fld.f27r1.fb2= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB2"); +state->u.f0.fld.f27r1.fb3= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB3"); +state->u.f0.fld.f27r1.fb4= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB4"); +state->u.f0.fld.f27r1.fb5= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB5"); +state->u.f0.fld.f27r1.fb6= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB6"); +state->u.f0.fld.f27r1.fb7= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB7"); +state->u.f0.fld.f27r1.fb8= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB8"); +state->u.f0.fld.f27r1.fb9= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB9"); +state->u.f0.fld.f27r1.fb10= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB10"); +state->u.f0.fld.f27r1.fb11= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB11"); +state->u.f0.fld.f27r1.fb12= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB12"); +state->u.f0.fld.f27r1.fb13= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB13"); +state->u.f0.fld.f27r1.fb14= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB14"); +state->u.f0.fld.f27r1.fb15= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB15"); +state->u.f0.fld.f27r1.fb16= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB16"); +state->u.f0.fld.f27r1.fb17= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB17"); +state->u.f0.fld.f27r1.fb18= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB18"); +state->u.f0.fld.f27r1.fb19= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB19"); +state->u.f0.fld.f27r1.fb20= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB20"); +state->u.f0.fld.f27r1.fb21= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB21"); +state->u.f0.fld.f27r1.fb22= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB22"); +state->u.f0.fld.f27r1.fb23= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB23"); +state->u.f0.fld.f27r1.fb24= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB24"); +state->u.f0.fld.f27r1.fb25= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB25"); +state->u.f0.fld.f27r1.fb26= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB26"); +state->u.f0.fld.f27r1.fb27= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB27"); +state->u.f0.fld.f27r1.fb28= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB28"); +state->u.f0.fld.f27r1.fb29= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB29"); +state->u.f0.fld.f27r1.fb30= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB30"); +state->u.f0.fld.f27r1.fb31= cm_object_get_child_by_name(state->u.f0.reg.f27r1, "FB31"); +// F27R2bitfields. +state->u.f0.fld.f27r2.fb0= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB0"); +state->u.f0.fld.f27r2.fb1= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB1"); +state->u.f0.fld.f27r2.fb2= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB2"); +state->u.f0.fld.f27r2.fb3= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB3"); +state->u.f0.fld.f27r2.fb4= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB4"); +state->u.f0.fld.f27r2.fb5= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB5"); +state->u.f0.fld.f27r2.fb6= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB6"); +state->u.f0.fld.f27r2.fb7= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB7"); +state->u.f0.fld.f27r2.fb8= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB8"); +state->u.f0.fld.f27r2.fb9= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB9"); +state->u.f0.fld.f27r2.fb10= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB10"); +state->u.f0.fld.f27r2.fb11= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB11"); +state->u.f0.fld.f27r2.fb12= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB12"); +state->u.f0.fld.f27r2.fb13= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB13"); +state->u.f0.fld.f27r2.fb14= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB14"); +state->u.f0.fld.f27r2.fb15= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB15"); +state->u.f0.fld.f27r2.fb16= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB16"); +state->u.f0.fld.f27r2.fb17= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB17"); +state->u.f0.fld.f27r2.fb18= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB18"); +state->u.f0.fld.f27r2.fb19= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB19"); +state->u.f0.fld.f27r2.fb20= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB20"); +state->u.f0.fld.f27r2.fb21= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB21"); +state->u.f0.fld.f27r2.fb22= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB22"); +state->u.f0.fld.f27r2.fb23= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB23"); +state->u.f0.fld.f27r2.fb24= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB24"); +state->u.f0.fld.f27r2.fb25= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB25"); +state->u.f0.fld.f27r2.fb26= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB26"); +state->u.f0.fld.f27r2.fb27= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB27"); +state->u.f0.fld.f27r2.fb28= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB28"); +state->u.f0.fld.f27r2.fb29= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB29"); +state->u.f0.fld.f27r2.fb30= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB30"); +state->u.f0.fld.f27r2.fb31= cm_object_get_child_by_name(state->u.f0.reg.f27r2, "FB31"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_can_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_can_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_can_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_can_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_can_is_enabled(Object *obj) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_can_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CANState *state = STM32_CAN_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_can_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CAN)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CANState *state = STM32_CAN_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CAN"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_can_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_can_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_can_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_can_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_can_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CANEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_can_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CAN); +} + +static void stm32_can_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_can_reset_callback; + dc->realize = stm32_can_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_can_is_enabled; +} + +static const TypeInfo stm32_can_type_info = { + .name = TYPE_STM32_CAN, + .parent = TYPE_STM32_CAN_PARENT, + .instance_init = stm32_can_instance_init_callback, + .instance_size = sizeof(STM32CANState), + .class_init = stm32_can_class_init_callback, + .class_size = sizeof(STM32CANClass) }; + +static void stm32_can_register_types(void) +{ + type_register_static(&stm32_can_type_info); +} + +type_init(stm32_can_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/can.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/can.h new file mode 100644 index 0000000000..2ae3cc3179 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/can.h @@ -0,0 +1,453 @@ +/* + * STM32- CAN(Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CAN_H_ +#define STM32_CAN_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CANDEVICE_PATH_STM32"CAN" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CANTYPE_STM32_PREFIX "can" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CAN_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CANParentClass; +typedef PeripheralState STM32CANParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CAN_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CANClass, (obj), TYPE_STM32_CAN) +#define STM32_CAN_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CANClass, (klass), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentClass parent_class; + // public: + + // None, so far. +} STM32CANClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CAN_STATE(obj) \ + OBJECT_CHECK(STM32CANState, (obj), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0CAN(Controller area network) registers. + struct { +Object *can_mcr; // 0x0(CAN_MCR) +Object *can_msr; // 0x4(CAN_MSR) +Object *can_tsr; // 0x8(CAN_TSR) +Object *can_rf0r; // 0xC(CAN_RF0R) +Object *can_rf1r; // 0x10(CAN_RF1R) +Object *can_ier; // 0x14(CAN_IER) +Object *can_esr; // 0x18(CAN_ESR) +Object *can_btr; // 0x1C(CAN BTR) +Object *can_ti0r; // 0x180(CAN_TI0R) +Object *can_tdt0r; // 0x184(CAN_TDT0R) +Object *can_tdl0r; // 0x188(CAN_TDL0R) +Object *can_tdh0r; // 0x18C(CAN_TDH0R) +Object *can_ti1r; // 0x190(CAN_TI1R) +Object *can_tdt1r; // 0x194(CAN_TDT1R) +Object *can_tdl1r; // 0x198(CAN_TDL1R) +Object *can_tdh1r; // 0x19C(CAN_TDH1R) +Object *can_ti2r; // 0x1A0(CAN_TI2R) +Object *can_tdt2r; // 0x1A4(CAN_TDT2R) +Object *can_tdl2r; // 0x1A8(CAN_TDL2R) +Object *can_tdh2r; // 0x1AC(CAN_TDH2R) +Object *can_ri0r; // 0x1B0(CAN_RI0R) +Object *can_rdt0r; // 0x1B4(CAN_RDT0R) +Object *can_rdl0r; // 0x1B8(CAN_RDL0R) +Object *can_rdh0r; // 0x1BC(CAN_RDH0R) +Object *can_ri1r; // 0x1C0(CAN_RI1R) +Object *can_rdt1r; // 0x1C4(CAN_RDT1R) +Object *can_rdl1r; // 0x1C8(CAN_RDL1R) +Object *can_rdh1r; // 0x1CC(CAN_RDH1R) +Object *can_fmr; // 0x200(CAN_FMR) +Object *can_fm1r; // 0x204(CAN_FM1R) +Object *can_fs1r; // 0x20C(CAN_FS1R) +Object *can_ffa1r; // 0x214(CAN_FFA1R) +Object *can_fa1r; // 0x21C(CAN_FA1R) +Object *f0r1; // 0x240(Filter bank 0 register 1) +Object *f0r2; // 0x244(Filter bank 0 register 2) +Object *f1r1; // 0x248(Filter bank 1 register 1) +Object *f1r2; // 0x24C(Filter bank 1 register 2) +Object *f2r1; // 0x250(Filter bank 2 register 1) +Object *f2r2; // 0x254(Filter bank 2 register 2) +Object *f3r1; // 0x258(Filter bank 3 register 1) +Object *f3r2; // 0x25C(Filter bank 3 register 2) +Object *f4r1; // 0x260(Filter bank 4 register 1) +Object *f4r2; // 0x264(Filter bank 4 register 2) +Object *f5r1; // 0x268(Filter bank 5 register 1) +Object *f5r2; // 0x26C(Filter bank 5 register 2) +Object *f6r1; // 0x270(Filter bank 6 register 1) +Object *f6r2; // 0x274(Filter bank 6 register 2) +Object *f7r1; // 0x278(Filter bank 7 register 1) +Object *f7r2; // 0x27C(Filter bank 7 register 2) +Object *f8r1; // 0x280(Filter bank 8 register 1) +Object *f8r2; // 0x284(Filter bank 8 register 2) +Object *f9r1; // 0x288(Filter bank 9 register 1) +Object *f9r2; // 0x28C(Filter bank 9 register 2) +Object *f10r1; // 0x290(Filter bank 10 register 1) +Object *f10r2; // 0x294(Filter bank 10 register 2) +Object *f11r1; // 0x298(Filter bank 11 register 1) +Object *f11r2; // 0x29C(Filter bank 11 register 2) +Object *f12r1; // 0x2A0(Filter bank 4 register 1) +Object *f12r2; // 0x2A4(Filter bank 12 register 2) +Object *f13r1; // 0x2A8(Filter bank 13 register 1) +Object *f13r2; // 0x2AC(Filter bank 13 register 2) +Object *f14r1; // 0x2B0(Filter bank 14 register 1) +Object *f14r2; // 0x2B4(Filter bank 14 register 2) +Object *f15r1; // 0x2B8(Filter bank 15 register 1) +Object *f15r2; // 0x2BC(Filter bank 15 register 2) +Object *f16r1; // 0x2C0(Filter bank 16 register 1) +Object *f16r2; // 0x2C4(Filter bank 16 register 2) +Object *f17r1; // 0x2C8(Filter bank 17 register 1) +Object *f17r2; // 0x2CC(Filter bank 17 register 2) +Object *f18r1; // 0x2D0(Filter bank 18 register 1) +Object *f18r2; // 0x2D4(Filter bank 18 register 2) +Object *f19r1; // 0x2D8(Filter bank 19 register 1) +Object *f19r2; // 0x2DC(Filter bank 19 register 2) +Object *f20r1; // 0x2E0(Filter bank 20 register 1) +Object *f20r2; // 0x2E4(Filter bank 20 register 2) +Object *f21r1; // 0x2E8(Filter bank 21 register 1) +Object *f21r2; // 0x2EC(Filter bank 21 register 2) +Object *f22r1; // 0x2F0(Filter bank 22 register 1) +Object *f22r2; // 0x2F4(Filter bank 22 register 2) +Object *f23r1; // 0x2F8(Filter bank 23 register 1) +Object *f23r2; // 0x2FC(Filter bank 23 register 2) +Object *f24r1; // 0x300(Filter bank 24 register 1) +Object *f24r2; // 0x304(Filter bank 24 register 2) +Object *f25r1; // 0x308(Filter bank 25 register 1) +Object *f25r2; // 0x30C(Filter bank 25 register 2) +Object *f26r1; // 0x310(Filter bank 26 register 1) +Object *f26r2; // 0x314(Filter bank 26 register 2) +Object *f27r1; // 0x318(Filter bank 27 register 1) +Object *f27r2; // 0x31C(Filter bank 27 register 2) +} reg; + + struct { +// CAN_MCR(CAN_MCR) bitfields. + struct { +Object *inrq; // [0:0] INRQObject *sleep; // [1:1] SLEEPObject *txfp; // [2:2] TXFPObject *rflm; // [3:3] RFLMObject *nart; // [4:4] NARTObject *awum; // [5:5] AWUMObject *abom; // [6:6] ABOMObject *ttcm; // [7:7] TTCMObject *reset; // [15:15] RESETObject *dbf; // [16:16] DBF} can_mcr; +// CAN_MSR(CAN_MSR) bitfields. + struct { +Object *inak; // [0:0] INAKObject *slak; // [1:1] SLAKObject *erri; // [2:2] ERRIObject *wkui; // [3:3] WKUIObject *slaki; // [4:4] SLAKIObject *txm; // [8:8] TXMObject *rxm; // [9:9] RXMObject *samp; // [10:10] SAMPObject *rx; // [11:11] RX} can_msr; +// CAN_TSR(CAN_TSR) bitfields. + struct { +Object *rqcp0; // [0:0] RQCP0Object *txok0; // [1:1] TXOK0Object *alst0; // [2:2] ALST0Object *terr0; // [3:3] TERR0Object *abrq0; // [7:7] ABRQ0Object *rqcp1; // [8:8] RQCP1Object *txok1; // [9:9] TXOK1Object *alst1; // [10:10] ALST1Object *terr1; // [11:11] TERR1Object *abrq1; // [15:15] ABRQ1Object *rqcp2; // [16:16] RQCP2Object *txok2; // [17:17] TXOK2Object *alst2; // [18:18] ALST2Object *terr2; // [19:19] TERR2Object *abrq2; // [23:23] ABRQ2Object *code; // [24:25] CODEObject *tme0; // [26:26] Lowest priority flag for mailbox 0Object *tme1; // [27:27] Lowest priority flag for mailbox 1Object *tme2; // [28:28] Lowest priority flag for mailbox 2Object *low0; // [29:29] Lowest priority flag for mailbox 0Object *low1; // [30:30] Lowest priority flag for mailbox 1Object *low2; // [31:31] Lowest priority flag for mailbox 2} can_tsr; +// CAN_RF0R(CAN_RF0R) bitfields. + struct { +Object *fmp0; // [0:1] FMP0Object *full0; // [3:3] FULL0Object *fovr0; // [4:4] FOVR0Object *rfom0; // [5:5] RFOM0} can_rf0r; +// CAN_RF1R(CAN_RF1R) bitfields. + struct { +Object *fmp1; // [0:1] FMP1Object *full1; // [3:3] FULL1Object *fovr1; // [4:4] FOVR1Object *rfom1; // [5:5] RFOM1} can_rf1r; +// CAN_IER(CAN_IER) bitfields. + struct { +Object *tmeie; // [0:0] TMEIEObject *fmpie0; // [1:1] FMPIE0Object *ffie0; // [2:2] FFIE0Object *fovie0; // [3:3] FOVIE0Object *fmpie1; // [4:4] FMPIE1Object *ffie1; // [5:5] FFIE1Object *fovie1; // [6:6] FOVIE1Object *ewgie; // [8:8] EWGIEObject *epvie; // [9:9] EPVIEObject *bofie; // [10:10] BOFIEObject *lecie; // [11:11] LECIEObject *errie; // [15:15] ERRIEObject *wkuie; // [16:16] WKUIEObject *slkie; // [17:17] SLKIE} can_ier; +// CAN_ESR(CAN_ESR) bitfields. + struct { +Object *ewgf; // [0:0] EWGFObject *epvf; // [1:1] EPVFObject *boff; // [2:2] BOFFObject *lec; // [4:6] LECObject *tec; // [16:23] TECObject *rec; // [24:31] REC} can_esr; +// CAN_BTR(CAN BTR) bitfields. + struct { +Object *brp; // [0:9] BRPObject *ts1; // [16:19] TS1Object *ts2; // [20:22] TS2Object *sjw; // [24:25] SJWObject *lbkm; // [30:30] LBKMObject *silm; // [31:31] SILM} can_btr; +// CAN_TI0R(CAN_TI0R) bitfields. + struct { +Object *txrq; // [0:0] TXRQObject *rtr; // [1:1] RTRObject *ide; // [2:2] IDEObject *exid; // [3:20] EXIDObject *stid; // [21:31] STID} can_ti0r; +// CAN_TDT0R(CAN_TDT0R) bitfields. + struct { +Object *dlc; // [0:3] DLCObject *tgt; // [8:8] TGTObject *time; // [16:31] TIME} can_tdt0r; +// CAN_TDL0R(CAN_TDL0R) bitfields. + struct { +Object *data0; // [0:7] DATA0Object *data1; // [8:15] DATA1Object *data2; // [16:23] DATA2Object *data3; // [24:31] DATA3} can_tdl0r; +// CAN_TDH0R(CAN_TDH0R) bitfields. + struct { +Object *data4; // [0:7] DATA4Object *data5; // [8:15] DATA5Object *data6; // [16:23] DATA6Object *data7; // [24:31] DATA7} can_tdh0r; +// CAN_TI1R(CAN_TI1R) bitfields. + struct { +Object *txrq; // [0:0] TXRQObject *rtr; // [1:1] RTRObject *ide; // [2:2] IDEObject *exid; // [3:20] EXIDObject *stid; // [21:31] STID} can_ti1r; +// CAN_TDT1R(CAN_TDT1R) bitfields. + struct { +Object *dlc; // [0:3] DLCObject *tgt; // [8:8] TGTObject *time; // [16:31] TIME} can_tdt1r; +// CAN_TDL1R(CAN_TDL1R) bitfields. + struct { +Object *data0; // [0:7] DATA0Object *data1; // [8:15] DATA1Object *data2; // [16:23] DATA2Object *data3; // [24:31] DATA3} can_tdl1r; +// CAN_TDH1R(CAN_TDH1R) bitfields. + struct { +Object *data4; // [0:7] DATA4Object *data5; // [8:15] DATA5Object *data6; // [16:23] DATA6Object *data7; // [24:31] DATA7} can_tdh1r; +// CAN_TI2R(CAN_TI2R) bitfields. + struct { +Object *txrq; // [0:0] TXRQObject *rtr; // [1:1] RTRObject *ide; // [2:2] IDEObject *exid; // [3:20] EXIDObject *stid; // [21:31] STID} can_ti2r; +// CAN_TDT2R(CAN_TDT2R) bitfields. + struct { +Object *dlc; // [0:3] DLCObject *tgt; // [8:8] TGTObject *time; // [16:31] TIME} can_tdt2r; +// CAN_TDL2R(CAN_TDL2R) bitfields. + struct { +Object *data0; // [0:7] DATA0Object *data1; // [8:15] DATA1Object *data2; // [16:23] DATA2Object *data3; // [24:31] DATA3} can_tdl2r; +// CAN_TDH2R(CAN_TDH2R) bitfields. + struct { +Object *data4; // [0:7] DATA4Object *data5; // [8:15] DATA5Object *data6; // [16:23] DATA6Object *data7; // [24:31] DATA7} can_tdh2r; +// CAN_RI0R(CAN_RI0R) bitfields. + struct { +Object *rtr; // [1:1] RTRObject *ide; // [2:2] IDEObject *exid; // [3:20] EXIDObject *stid; // [21:31] STID} can_ri0r; +// CAN_RDT0R(CAN_RDT0R) bitfields. + struct { +Object *dlc; // [0:3] DLCObject *fmi; // [8:15] FMIObject *time; // [16:31] TIME} can_rdt0r; +// CAN_RDL0R(CAN_RDL0R) bitfields. + struct { +Object *data0; // [0:7] DATA0Object *data1; // [8:15] DATA1Object *data2; // [16:23] DATA2Object *data3; // [24:31] DATA3} can_rdl0r; +// CAN_RDH0R(CAN_RDH0R) bitfields. + struct { +Object *data4; // [0:7] DATA4Object *data5; // [8:15] DATA5Object *data6; // [16:23] DATA6Object *data7; // [24:31] DATA7} can_rdh0r; +// CAN_RI1R(CAN_RI1R) bitfields. + struct { +Object *rtr; // [1:1] RTRObject *ide; // [2:2] IDEObject *exid; // [3:20] EXIDObject *stid; // [21:31] STID} can_ri1r; +// CAN_RDT1R(CAN_RDT1R) bitfields. + struct { +Object *dlc; // [0:3] DLCObject *fmi; // [8:15] FMIObject *time; // [16:31] TIME} can_rdt1r; +// CAN_RDL1R(CAN_RDL1R) bitfields. + struct { +Object *data0; // [0:7] DATA0Object *data1; // [8:15] DATA1Object *data2; // [16:23] DATA2Object *data3; // [24:31] DATA3} can_rdl1r; +// CAN_RDH1R(CAN_RDH1R) bitfields. + struct { +Object *data4; // [0:7] DATA4Object *data5; // [8:15] DATA5Object *data6; // [16:23] DATA6Object *data7; // [24:31] DATA7} can_rdh1r; +// CAN_FMR(CAN_FMR) bitfields. + struct { +Object *finit; // [0:0] FINITObject *can2sb; // [8:13] CAN2SB} can_fmr; +// CAN_FM1R(CAN_FM1R) bitfields. + struct { +Object *fbm0; // [0:0] Filter modeObject *fbm1; // [1:1] Filter modeObject *fbm2; // [2:2] Filter modeObject *fbm3; // [3:3] Filter modeObject *fbm4; // [4:4] Filter modeObject *fbm5; // [5:5] Filter modeObject *fbm6; // [6:6] Filter modeObject *fbm7; // [7:7] Filter modeObject *fbm8; // [8:8] Filter modeObject *fbm9; // [9:9] Filter modeObject *fbm10; // [10:10] Filter modeObject *fbm11; // [11:11] Filter modeObject *fbm12; // [12:12] Filter modeObject *fbm13; // [13:13] Filter modeObject *fbm14; // [14:14] Filter modeObject *fbm15; // [15:15] Filter modeObject *fbm16; // [16:16] Filter modeObject *fbm17; // [17:17] Filter modeObject *fbm18; // [18:18] Filter modeObject *fbm19; // [19:19] Filter modeObject *fbm20; // [20:20] Filter modeObject *fbm21; // [21:21] Filter modeObject *fbm22; // [22:22] Filter modeObject *fbm23; // [23:23] Filter modeObject *fbm24; // [24:24] Filter modeObject *fbm25; // [25:25] Filter modeObject *fbm26; // [26:26] Filter modeObject *fbm27; // [27:27] Filter mode} can_fm1r; +// CAN_FS1R(CAN_FS1R) bitfields. + struct { +Object *fsc0; // [0:0] Filter scale configurationObject *fsc1; // [1:1] Filter scale configurationObject *fsc2; // [2:2] Filter scale configurationObject *fsc3; // [3:3] Filter scale configurationObject *fsc4; // [4:4] Filter scale configurationObject *fsc5; // [5:5] Filter scale configurationObject *fsc6; // [6:6] Filter scale configurationObject *fsc7; // [7:7] Filter scale configurationObject *fsc8; // [8:8] Filter scale configurationObject *fsc9; // [9:9] Filter scale configurationObject *fsc10; // [10:10] Filter scale configurationObject *fsc11; // [11:11] Filter scale configurationObject *fsc12; // [12:12] Filter scale configurationObject *fsc13; // [13:13] Filter scale configurationObject *fsc14; // [14:14] Filter scale configurationObject *fsc15; // [15:15] Filter scale configurationObject *fsc16; // [16:16] Filter scale configurationObject *fsc17; // [17:17] Filter scale configurationObject *fsc18; // [18:18] Filter scale configurationObject *fsc19; // [19:19] Filter scale configurationObject *fsc20; // [20:20] Filter scale configurationObject *fsc21; // [21:21] Filter scale configurationObject *fsc22; // [22:22] Filter scale configurationObject *fsc23; // [23:23] Filter scale configurationObject *fsc24; // [24:24] Filter scale configurationObject *fsc25; // [25:25] Filter scale configurationObject *fsc26; // [26:26] Filter scale configurationObject *fsc27; // [27:27] Filter scale configuration} can_fs1r; +// CAN_FFA1R(CAN_FFA1R) bitfields. + struct { +Object *ffa0; // [0:0] Filter FIFO assignment for filter 0Object *ffa1; // [1:1] Filter FIFO assignment for filter 1Object *ffa2; // [2:2] Filter FIFO assignment for filter 2Object *ffa3; // [3:3] Filter FIFO assignment for filter 3Object *ffa4; // [4:4] Filter FIFO assignment for filter 4Object *ffa5; // [5:5] Filter FIFO assignment for filter 5Object *ffa6; // [6:6] Filter FIFO assignment for filter 6Object *ffa7; // [7:7] Filter FIFO assignment for filter 7Object *ffa8; // [8:8] Filter FIFO assignment for filter 8Object *ffa9; // [9:9] Filter FIFO assignment for filter 9Object *ffa10; // [10:10] Filter FIFO assignment for filter 10Object *ffa11; // [11:11] Filter FIFO assignment for filter 11Object *ffa12; // [12:12] Filter FIFO assignment for filter 12Object *ffa13; // [13:13] Filter FIFO assignment for filter 13Object *ffa14; // [14:14] Filter FIFO assignment for filter 14Object *ffa15; // [15:15] Filter FIFO assignment for filter 15Object *ffa16; // [16:16] Filter FIFO assignment for filter 16Object *ffa17; // [17:17] Filter FIFO assignment for filter 17Object *ffa18; // [18:18] Filter FIFO assignment for filter 18Object *ffa19; // [19:19] Filter FIFO assignment for filter 19Object *ffa20; // [20:20] Filter FIFO assignment for filter 20Object *ffa21; // [21:21] Filter FIFO assignment for filter 21Object *ffa22; // [22:22] Filter FIFO assignment for filter 22Object *ffa23; // [23:23] Filter FIFO assignment for filter 23Object *ffa24; // [24:24] Filter FIFO assignment for filter 24Object *ffa25; // [25:25] Filter FIFO assignment for filter 25Object *ffa26; // [26:26] Filter FIFO assignment for filter 26Object *ffa27; // [27:27] Filter FIFO assignment for filter 27} can_ffa1r; +// CAN_FA1R(CAN_FA1R) bitfields. + struct { +Object *fact0; // [0:0] Filter activeObject *fact1; // [1:1] Filter activeObject *fact2; // [2:2] Filter activeObject *fact3; // [3:3] Filter activeObject *fact4; // [4:4] Filter activeObject *fact5; // [5:5] Filter activeObject *fact6; // [6:6] Filter activeObject *fact7; // [7:7] Filter activeObject *fact8; // [8:8] Filter activeObject *fact9; // [9:9] Filter activeObject *fact10; // [10:10] Filter activeObject *fact11; // [11:11] Filter activeObject *fact12; // [12:12] Filter activeObject *fact13; // [13:13] Filter activeObject *fact14; // [14:14] Filter activeObject *fact15; // [15:15] Filter activeObject *fact16; // [16:16] Filter activeObject *fact17; // [17:17] Filter activeObject *fact18; // [18:18] Filter activeObject *fact19; // [19:19] Filter activeObject *fact20; // [20:20] Filter activeObject *fact21; // [21:21] Filter activeObject *fact22; // [22:22] Filter activeObject *fact23; // [23:23] Filter activeObject *fact24; // [24:24] Filter activeObject *fact25; // [25:25] Filter activeObject *fact26; // [26:26] Filter activeObject *fact27; // [27:27] Filter active} can_fa1r; +// F0R1(Filter bank 0 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f0r1; +// F0R2(Filter bank 0 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f0r2; +// F1R1(Filter bank 1 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f1r1; +// F1R2(Filter bank 1 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f1r2; +// F2R1(Filter bank 2 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f2r1; +// F2R2(Filter bank 2 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f2r2; +// F3R1(Filter bank 3 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f3r1; +// F3R2(Filter bank 3 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f3r2; +// F4R1(Filter bank 4 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f4r1; +// F4R2(Filter bank 4 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f4r2; +// F5R1(Filter bank 5 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f5r1; +// F5R2(Filter bank 5 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f5r2; +// F6R1(Filter bank 6 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f6r1; +// F6R2(Filter bank 6 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f6r2; +// F7R1(Filter bank 7 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f7r1; +// F7R2(Filter bank 7 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f7r2; +// F8R1(Filter bank 8 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f8r1; +// F8R2(Filter bank 8 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f8r2; +// F9R1(Filter bank 9 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f9r1; +// F9R2(Filter bank 9 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f9r2; +// F10R1(Filter bank 10 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f10r1; +// F10R2(Filter bank 10 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f10r2; +// F11R1(Filter bank 11 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f11r1; +// F11R2(Filter bank 11 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f11r2; +// F12R1(Filter bank 4 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f12r1; +// F12R2(Filter bank 12 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f12r2; +// F13R1(Filter bank 13 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f13r1; +// F13R2(Filter bank 13 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f13r2; +// F14R1(Filter bank 14 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f14r1; +// F14R2(Filter bank 14 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f14r2; +// F15R1(Filter bank 15 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f15r1; +// F15R2(Filter bank 15 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f15r2; +// F16R1(Filter bank 16 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f16r1; +// F16R2(Filter bank 16 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f16r2; +// F17R1(Filter bank 17 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f17r1; +// F17R2(Filter bank 17 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f17r2; +// F18R1(Filter bank 18 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f18r1; +// F18R2(Filter bank 18 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f18r2; +// F19R1(Filter bank 19 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f19r1; +// F19R2(Filter bank 19 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f19r2; +// F20R1(Filter bank 20 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f20r1; +// F20R2(Filter bank 20 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f20r2; +// F21R1(Filter bank 21 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f21r1; +// F21R2(Filter bank 21 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f21r2; +// F22R1(Filter bank 22 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f22r1; +// F22R2(Filter bank 22 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f22r2; +// F23R1(Filter bank 23 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f23r1; +// F23R2(Filter bank 23 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f23r2; +// F24R1(Filter bank 24 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f24r1; +// F24R2(Filter bank 24 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f24r2; +// F25R1(Filter bank 25 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f25r1; +// F25R2(Filter bank 25 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f25r2; +// F26R1(Filter bank 26 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f26r1; +// F26R2(Filter bank 26 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f26r2; +// F27R1(Filter bank 27 register 1) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f27r1; +// F27R2(Filter bank 27 register 2) bitfields. + struct { +Object *fb0; // [0:0] Filter bitsObject *fb1; // [1:1] Filter bitsObject *fb2; // [2:2] Filter bitsObject *fb3; // [3:3] Filter bitsObject *fb4; // [4:4] Filter bitsObject *fb5; // [5:5] Filter bitsObject *fb6; // [6:6] Filter bitsObject *fb7; // [7:7] Filter bitsObject *fb8; // [8:8] Filter bitsObject *fb9; // [9:9] Filter bitsObject *fb10; // [10:10] Filter bitsObject *fb11; // [11:11] Filter bitsObject *fb12; // [12:12] Filter bitsObject *fb13; // [13:13] Filter bitsObject *fb14; // [14:14] Filter bitsObject *fb15; // [15:15] Filter bitsObject *fb16; // [16:16] Filter bitsObject *fb17; // [17:17] Filter bitsObject *fb18; // [18:18] Filter bitsObject *fb19; // [19:19] Filter bitsObject *fb20; // [20:20] Filter bitsObject *fb21; // [21:21] Filter bitsObject *fb22; // [22:22] Filter bitsObject *fb23; // [23:23] Filter bitsObject *fb24; // [24:24] Filter bitsObject *fb25; // [25:25] Filter bitsObject *fb26; // [26:26] Filter bitsObject *fb27; // [27:27] Filter bitsObject *fb28; // [28:28] Filter bitsObject *fb29; // [29:29] Filter bitsObject *fb30; // [30:30] Filter bitsObject *fb31; // [31:31] Filter bits} f27r2; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CANState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CAN_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/cec.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/cec.c new file mode 100644 index 0000000000..ff089477ce --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/cec.c @@ -0,0 +1,281 @@ +/* + * STM32- CEC(HDMI-CEC controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_cec_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CECState *state = STM32_CEC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.cfgr= cm_object_get_child_by_name(obj, "CFGR"); +state->u.f0.reg.txdr= cm_object_get_child_by_name(obj, "TXDR"); +state->u.f0.reg.rxdr= cm_object_get_child_by_name(obj, "RXDR"); +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.ier= cm_object_get_child_by_name(obj, "IER"); +// CRbitfields. +state->u.f0.fld.cr.cecen= cm_object_get_child_by_name(state->u.f0.reg.cr, "CECEN"); +state->u.f0.fld.cr.txsom= cm_object_get_child_by_name(state->u.f0.reg.cr, "TXSOM"); +state->u.f0.fld.cr.txeom= cm_object_get_child_by_name(state->u.f0.reg.cr, "TXEOM"); +// CFGRbitfields. +state->u.f0.fld.cfgr.oar= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "OAR"); +state->u.f0.fld.cfgr.lstn= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "LSTN"); +state->u.f0.fld.cfgr.sft= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SFT"); +state->u.f0.fld.cfgr.rxtol= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "RXTOL"); +state->u.f0.fld.cfgr.brestp= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "BRESTP"); +state->u.f0.fld.cfgr.bregen= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "BREGEN"); +state->u.f0.fld.cfgr.lbpegen= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "LBPEGEN"); +// TXDRbitfields. +state->u.f0.fld.txdr.txd= cm_object_get_child_by_name(state->u.f0.reg.txdr, "TXD"); +// RXDRbitfields. +state->u.f0.fld.rxdr.rxdr= cm_object_get_child_by_name(state->u.f0.reg.rxdr, "RXDR"); +// ISRbitfields. +state->u.f0.fld.isr.rxbr= cm_object_get_child_by_name(state->u.f0.reg.isr, "RXBR"); +state->u.f0.fld.isr.rxend= cm_object_get_child_by_name(state->u.f0.reg.isr, "RXEND"); +state->u.f0.fld.isr.rxovr= cm_object_get_child_by_name(state->u.f0.reg.isr, "RXOVR"); +state->u.f0.fld.isr.bre= cm_object_get_child_by_name(state->u.f0.reg.isr, "BRE"); +state->u.f0.fld.isr.sbpe= cm_object_get_child_by_name(state->u.f0.reg.isr, "SBPE"); +state->u.f0.fld.isr.lbpe= cm_object_get_child_by_name(state->u.f0.reg.isr, "LBPE"); +state->u.f0.fld.isr.rxacke= cm_object_get_child_by_name(state->u.f0.reg.isr, "RXACKE"); +state->u.f0.fld.isr.arblst= cm_object_get_child_by_name(state->u.f0.reg.isr, "ARBLST"); +state->u.f0.fld.isr.txbr= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXBR"); +state->u.f0.fld.isr.txend= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXEND"); +state->u.f0.fld.isr.txudr= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXUDR"); +state->u.f0.fld.isr.txerr= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXERR"); +state->u.f0.fld.isr.txacke= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXACKE"); +// IERbitfields. +state->u.f0.fld.ier.rxbrie= cm_object_get_child_by_name(state->u.f0.reg.ier, "RXBRIE"); +state->u.f0.fld.ier.rxendie= cm_object_get_child_by_name(state->u.f0.reg.ier, "RXENDIE"); +state->u.f0.fld.ier.rxovrie= cm_object_get_child_by_name(state->u.f0.reg.ier, "RXOVRIE"); +state->u.f0.fld.ier.breie= cm_object_get_child_by_name(state->u.f0.reg.ier, "BREIE"); +state->u.f0.fld.ier.sbpeie= cm_object_get_child_by_name(state->u.f0.reg.ier, "SBPEIE"); +state->u.f0.fld.ier.lbpeie= cm_object_get_child_by_name(state->u.f0.reg.ier, "LBPEIE"); +state->u.f0.fld.ier.rxackie= cm_object_get_child_by_name(state->u.f0.reg.ier, "RXACKIE"); +state->u.f0.fld.ier.arblstie= cm_object_get_child_by_name(state->u.f0.reg.ier, "ARBLSTIE"); +state->u.f0.fld.ier.txbrie= cm_object_get_child_by_name(state->u.f0.reg.ier, "TXBRIE"); +state->u.f0.fld.ier.txendie= cm_object_get_child_by_name(state->u.f0.reg.ier, "TXENDIE"); +state->u.f0.fld.ier.txudrie= cm_object_get_child_by_name(state->u.f0.reg.ier, "TXUDRIE"); +state->u.f0.fld.ier.txerrie= cm_object_get_child_by_name(state->u.f0.reg.ier, "TXERRIE"); +state->u.f0.fld.ier.txackie= cm_object_get_child_by_name(state->u.f0.reg.ier, "TXACKIE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_cec_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_cec_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_cec_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_cec_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CECState *state = STM32_CEC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_cec_is_enabled(Object *obj) +{ + STM32CECState *state = STM32_CEC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_cec_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CECState *state = STM32_CEC_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_cec_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CEC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CECState *state = STM32_CEC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CEC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_cec_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_cec_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_cec_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_cec_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_cec_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CECEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_cec_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CEC); +} + +static void stm32_cec_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_cec_reset_callback; + dc->realize = stm32_cec_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_cec_is_enabled; +} + +static const TypeInfo stm32_cec_type_info = { + .name = TYPE_STM32_CEC, + .parent = TYPE_STM32_CEC_PARENT, + .instance_init = stm32_cec_instance_init_callback, + .instance_size = sizeof(STM32CECState), + .class_init = stm32_cec_class_init_callback, + .class_size = sizeof(STM32CECClass) }; + +static void stm32_cec_register_types(void) +{ + type_register_static(&stm32_cec_type_info); +} + +type_init(stm32_cec_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/cec.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/cec.h new file mode 100644 index 0000000000..81a896d1b5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/cec.h @@ -0,0 +1,121 @@ +/* + * STM32- CEC(HDMI-CEC controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CEC_H_ +#define STM32_CEC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CECDEVICE_PATH_STM32"CEC" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CECTYPE_STM32_PREFIX "cec" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CEC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CECParentClass; +typedef PeripheralState STM32CECParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CEC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CECClass, (obj), TYPE_STM32_CEC) +#define STM32_CEC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CECClass, (klass), TYPE_STM32_CEC) + +typedef struct { + // private: + STM32CECParentClass parent_class; + // public: + + // None, so far. +} STM32CECClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CEC_STATE(obj) \ + OBJECT_CHECK(STM32CECState, (obj), TYPE_STM32_CEC) + +typedef struct { + // private: + STM32CECParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0CEC(HDMI-CEC controller) registers. + struct { +Object *cr; // 0x0(Control register) +Object *cfgr; // 0x4(Configuration register) +Object *txdr; // 0x8(Tx data register) +Object *rxdr; // 0xC(Rx Data Register) +Object *isr; // 0x10(Interrupt and Status Register) +Object *ier; // 0x14(Interrupt enable register) +} reg; + + struct { +// CR(Control register) bitfields. + struct { +Object *cecen; // [0:0] CEC EnableObject *txsom; // [1:1] Tx start of messageObject *txeom; // [2:2] Tx End Of Message} cr; +// CFGR(Configuration register) bitfields. + struct { +Object *oar; // [0:3] Own AddressObject *lstn; // [4:4] Listen modeObject *sft; // [5:7] Signal Free TimeObject *rxtol; // [8:8] Rx-ToleranceObject *brestp; // [9:9] Rx-stop on bit rising errorObject *bregen; // [10:10] Generate error-bit on bit rising errorObject *lbpegen; // [11:11] Generate Error-Bit on Long Bit Period Error} cfgr; +// TXDR(Tx data register) bitfields. + struct { +Object *txd; // [0:7] Tx Data register} txdr; +// RXDR(Rx Data Register) bitfields. + struct { +Object *rxdr; // [0:7] CEC Rx Data Register} rxdr; +// ISR(Interrupt and Status Register) bitfields. + struct { +Object *rxbr; // [0:0] Rx-Byte ReceivedObject *rxend; // [1:1] End Of ReceptionObject *rxovr; // [2:2] Rx-OverrunObject *bre; // [3:3] Rx-Bit rising errorObject *sbpe; // [4:4] Rx-Short Bit period errorObject *lbpe; // [5:5] Rx-Long Bit Period ErrorObject *rxacke; // [6:6] Rx-Missing AcknowledgeObject *arblst; // [7:7] Arbitration LostObject *txbr; // [8:8] Tx-Byte RequestObject *txend; // [9:9] End of TransmissionObject *txudr; // [10:10] Tx-Buffer UnderrunObject *txerr; // [11:11] Tx-ErrorObject *txacke; // [12:12] Tx-Missing acknowledge error} isr; +// IER(Interrupt enable register) bitfields. + struct { +Object *rxbrie; // [0:0] Rx-Byte Received Interrupt EnableObject *rxendie; // [1:1] End Of Reception Interrupt EnableObject *rxovrie; // [2:2] Rx-Buffer Overrun Interrupt EnableObject *breie; // [3:3] Bit Rising Error Interrupt EnableObject *sbpeie; // [4:4] Short Bit Period Error Interrupt EnableObject *lbpeie; // [5:5] Long Bit Period Error Interrupt EnableObject *rxackie; // [6:6] Rx-Missing Acknowledge Error Interrupt EnableObject *arblstie; // [7:7] Arbitration Lost Interrupt EnableObject *txbrie; // [8:8] Tx-Byte Request Interrupt EnableObject *txendie; // [9:9] Tx-End of message interrupt enableObject *txudrie; // [10:10] Tx-Underrun interrupt enableObject *txerrie; // [11:11] Tx-Error Interrupt EnableObject *txackie; // [12:12] Tx-Missing Acknowledge Error Interrupt Enable} ier; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CECState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CEC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/comp.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/comp.c new file mode 100644 index 0000000000..df0f3b6815 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/comp.c @@ -0,0 +1,251 @@ +/* + * STM32- COMP(Comparator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_comp_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32COMPState *state = STM32_COMP_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.csr= cm_object_get_child_by_name(obj, "CSR"); +// CSRbitfields. +state->u.f0.fld.csr.comp1en= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1EN"); +state->u.f0.fld.csr.comp1_inp_dac= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1_INP_DAC"); +state->u.f0.fld.csr.comp1mode= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1MODE"); +state->u.f0.fld.csr.comp1insel= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1INSEL"); +state->u.f0.fld.csr.comp1outsel= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1OUTSEL"); +state->u.f0.fld.csr.comp1pol= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1POL"); +state->u.f0.fld.csr.comp1hyst= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1HYST"); +state->u.f0.fld.csr.comp1out= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1OUT"); +state->u.f0.fld.csr.comp1lock= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP1LOCK"); +state->u.f0.fld.csr.comp2en= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2EN"); +state->u.f0.fld.csr.comp2mode= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2MODE"); +state->u.f0.fld.csr.comp2insel= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2INSEL"); +state->u.f0.fld.csr.wndwen= cm_object_get_child_by_name(state->u.f0.reg.csr, "WNDWEN"); +state->u.f0.fld.csr.comp2outsel= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2OUTSEL"); +state->u.f0.fld.csr.comp2pol= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2POL"); +state->u.f0.fld.csr.comp2hyst= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2HYST"); +state->u.f0.fld.csr.comp2out= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2OUT"); +state->u.f0.fld.csr.comp2lock= cm_object_get_child_by_name(state->u.f0.reg.csr, "COMP2LOCK"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_comp_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_comp_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_comp_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_comp_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32COMPState *state = STM32_COMP_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_comp_is_enabled(Object *obj) +{ + STM32COMPState *state = STM32_COMP_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_comp_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32COMPState *state = STM32_COMP_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_comp_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_COMP)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32COMPState *state = STM32_COMP_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "COMP"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_comp_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_comp_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_comp_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_comp_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_comp_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/COMPEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_comp_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_COMP); +} + +static void stm32_comp_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_comp_reset_callback; + dc->realize = stm32_comp_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_comp_is_enabled; +} + +static const TypeInfo stm32_comp_type_info = { + .name = TYPE_STM32_COMP, + .parent = TYPE_STM32_COMP_PARENT, + .instance_init = stm32_comp_instance_init_callback, + .instance_size = sizeof(STM32COMPState), + .class_init = stm32_comp_class_init_callback, + .class_size = sizeof(STM32COMPClass) }; + +static void stm32_comp_register_types(void) +{ + type_register_static(&stm32_comp_type_info); +} + +type_init(stm32_comp_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/comp.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/comp.h new file mode 100644 index 0000000000..544b266aca --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/comp.h @@ -0,0 +1,101 @@ +/* + * STM32- COMP(Comparator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_COMP_H_ +#define STM32_COMP_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_COMPDEVICE_PATH_STM32"COMP" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_COMPTYPE_STM32_PREFIX "comp" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_COMP_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32COMPParentClass; +typedef PeripheralState STM32COMPParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_COMP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32COMPClass, (obj), TYPE_STM32_COMP) +#define STM32_COMP_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32COMPClass, (klass), TYPE_STM32_COMP) + +typedef struct { + // private: + STM32COMPParentClass parent_class; + // public: + + // None, so far. +} STM32COMPClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_COMP_STATE(obj) \ + OBJECT_CHECK(STM32COMPState, (obj), TYPE_STM32_COMP) + +typedef struct { + // private: + STM32COMPParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0COMP(Comparator) registers. + struct { +Object *csr; // 0x0(Control and status register) +} reg; + + struct { +// CSR(Control and status register) bitfields. + struct { +Object *comp1en; // [0:0] Comparator 1 enableObject *comp1_inp_dac; // [1:1] COMP1_INP_DACObject *comp1mode; // [2:3] Comparator 1 modeObject *comp1insel; // [4:6] Comparator 1 inverting input selectionObject *comp1outsel; // [8:10] Comparator 1 output selectionObject *comp1pol; // [11:11] Comparator 1 output polarityObject *comp1hyst; // [12:13] Comparator 1 hysteresisObject *comp1out; // [14:14] Comparator 1 outputObject *comp1lock; // [15:15] Comparator 1 lockObject *comp2en; // [16:16] Comparator 2 enableObject *comp2mode; // [18:19] Comparator 2 modeObject *comp2insel; // [20:22] Comparator 2 inverting input selectionObject *wndwen; // [23:23] Window mode enableObject *comp2outsel; // [24:26] Comparator 2 output selectionObject *comp2pol; // [27:27] Comparator 2 output polarityObject *comp2hyst; // [28:29] Comparator 2 hysteresisObject *comp2out; // [30:30] Comparator 2 outputObject *comp2lock; // [31:31] Comparator 2 lock} csr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32COMPState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_COMP_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/crc.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/crc.c new file mode 100644 index 0000000000..43c6cea63b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/crc.c @@ -0,0 +1,246 @@ +/* + * STM32- CRC(Cyclic redundancy check calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_crc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.dr= cm_object_get_child_by_name(obj, "DR"); +state->u.f0.reg.idr= cm_object_get_child_by_name(obj, "IDR"); +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.init= cm_object_get_child_by_name(obj, "INIT"); +// DRbitfields. +state->u.f0.fld.dr.dr= cm_object_get_child_by_name(state->u.f0.reg.dr, "DR"); +// IDRbitfields. +state->u.f0.fld.idr.idr= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR"); +// CRbitfields. +state->u.f0.fld.cr.reset= cm_object_get_child_by_name(state->u.f0.reg.cr, "RESET"); +state->u.f0.fld.cr.polysize= cm_object_get_child_by_name(state->u.f0.reg.cr, "POLYSIZE"); +state->u.f0.fld.cr.rev_in= cm_object_get_child_by_name(state->u.f0.reg.cr, "REV_IN"); +state->u.f0.fld.cr.rev_out= cm_object_get_child_by_name(state->u.f0.reg.cr, "REV_OUT"); +// INITbitfields. +state->u.f0.fld.init.init= cm_object_get_child_by_name(state->u.f0.reg.init, "INIT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crc_is_enabled(Object *obj) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRCState *state = STM32_CRC_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRCState *state = STM32_CRC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_crc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_crc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_crc_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRCEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRC); +} + +static void stm32_crc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crc_reset_callback; + dc->realize = stm32_crc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crc_is_enabled; +} + +static const TypeInfo stm32_crc_type_info = { + .name = TYPE_STM32_CRC, + .parent = TYPE_STM32_CRC_PARENT, + .instance_init = stm32_crc_instance_init_callback, + .instance_size = sizeof(STM32CRCState), + .class_init = stm32_crc_class_init_callback, + .class_size = sizeof(STM32CRCClass) }; + +static void stm32_crc_register_types(void) +{ + type_register_static(&stm32_crc_type_info); +} + +type_init(stm32_crc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/crc.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/crc.h new file mode 100644 index 0000000000..af41794597 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/crc.h @@ -0,0 +1,113 @@ +/* + * STM32- CRC(Cyclic redundancy check calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRC_H_ +#define STM32_CRC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRCDEVICE_PATH_STM32"CRC" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRCTYPE_STM32_PREFIX "crc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRCParentClass; +typedef PeripheralState STM32CRCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRCClass, (obj), TYPE_STM32_CRC) +#define STM32_CRC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRCClass, (klass), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentClass parent_class; + // public: + + // None, so far. +} STM32CRCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRC_STATE(obj) \ + OBJECT_CHECK(STM32CRCState, (obj), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0CRC(Cyclic redundancy check calculation unit) registers. + struct { +Object *dr; // 0x0(Data register) +Object *idr; // 0x4(Independent data register) +Object *cr; // 0x8(Control register) +Object *init; // 0xC(Initial CRC value) +} reg; + + struct { +// DR(Data register) bitfields. + struct { +Object *dr; // [0:31] Data register bits} dr; +// IDR(Independent data register) bitfields. + struct { +Object *idr; // [0:7] General-purpose 8-bit data register bits} idr; +// CR(Control register) bitfields. + struct { +Object *reset; // [0:0] Reset bitObject *polysize; // [3:4] Polynomial sizeObject *rev_in; // [5:6] Reverse input dataObject *rev_out; // [7:7] Reverse output data} cr; +// INIT(Initial CRC value) bitfields. + struct { +Object *init; // [0:31] Programmable initial CRC value} init; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/crs.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/crs.c new file mode 100644 index 0000000000..00d7b8d912 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/crs.c @@ -0,0 +1,265 @@ +/* + * STM32- CRS(Clock recovery system) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_crs_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRSState *state = STM32_CRS_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.cfgr= cm_object_get_child_by_name(obj, "CFGR"); +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.icr= cm_object_get_child_by_name(obj, "ICR"); +// CRbitfields. +state->u.f0.fld.cr.syncokie= cm_object_get_child_by_name(state->u.f0.reg.cr, "SYNCOKIE"); +state->u.f0.fld.cr.syncwarnie= cm_object_get_child_by_name(state->u.f0.reg.cr, "SYNCWARNIE"); +state->u.f0.fld.cr.errie= cm_object_get_child_by_name(state->u.f0.reg.cr, "ERRIE"); +state->u.f0.fld.cr.esyncie= cm_object_get_child_by_name(state->u.f0.reg.cr, "ESYNCIE"); +state->u.f0.fld.cr.cen= cm_object_get_child_by_name(state->u.f0.reg.cr, "CEN"); +state->u.f0.fld.cr.autotrimen= cm_object_get_child_by_name(state->u.f0.reg.cr, "AUTOTRIMEN"); +state->u.f0.fld.cr.swsync= cm_object_get_child_by_name(state->u.f0.reg.cr, "SWSYNC"); +state->u.f0.fld.cr.trim= cm_object_get_child_by_name(state->u.f0.reg.cr, "TRIM"); +// CFGRbitfields. +state->u.f0.fld.cfgr.reload= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "RELOAD"); +state->u.f0.fld.cfgr.felim= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "FELIM"); +state->u.f0.fld.cfgr.syncdiv= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SYNCDIV"); +state->u.f0.fld.cfgr.syncsrc= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SYNCSRC"); +state->u.f0.fld.cfgr.syncpol= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SYNCPOL"); +// ISRbitfields. +state->u.f0.fld.isr.syncokf= cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCOKF"); +state->u.f0.fld.isr.syncwarnf= cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCWARNF"); +state->u.f0.fld.isr.errf= cm_object_get_child_by_name(state->u.f0.reg.isr, "ERRF"); +state->u.f0.fld.isr.esyncf= cm_object_get_child_by_name(state->u.f0.reg.isr, "ESYNCF"); +state->u.f0.fld.isr.syncerr= cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCERR"); +state->u.f0.fld.isr.syncmiss= cm_object_get_child_by_name(state->u.f0.reg.isr, "SYNCMISS"); +state->u.f0.fld.isr.trimovf= cm_object_get_child_by_name(state->u.f0.reg.isr, "TRIMOVF"); +state->u.f0.fld.isr.fedir= cm_object_get_child_by_name(state->u.f0.reg.isr, "FEDIR"); +state->u.f0.fld.isr.fecap= cm_object_get_child_by_name(state->u.f0.reg.isr, "FECAP"); +// ICRbitfields. +state->u.f0.fld.icr.syncokc= cm_object_get_child_by_name(state->u.f0.reg.icr, "SYNCOKC"); +state->u.f0.fld.icr.syncwarnc= cm_object_get_child_by_name(state->u.f0.reg.icr, "SYNCWARNC"); +state->u.f0.fld.icr.errc= cm_object_get_child_by_name(state->u.f0.reg.icr, "ERRC"); +state->u.f0.fld.icr.esyncc= cm_object_get_child_by_name(state->u.f0.reg.icr, "ESYNCC"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crs_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crs_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crs_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crs_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRSState *state = STM32_CRS_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crs_is_enabled(Object *obj) +{ + STM32CRSState *state = STM32_CRS_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crs_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRSState *state = STM32_CRS_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crs_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRS)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRSState *state = STM32_CRS_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRS"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_crs_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crs_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_crs_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_crs_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_crs_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRSEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crs_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRS); +} + +static void stm32_crs_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crs_reset_callback; + dc->realize = stm32_crs_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crs_is_enabled; +} + +static const TypeInfo stm32_crs_type_info = { + .name = TYPE_STM32_CRS, + .parent = TYPE_STM32_CRS_PARENT, + .instance_init = stm32_crs_instance_init_callback, + .instance_size = sizeof(STM32CRSState), + .class_init = stm32_crs_class_init_callback, + .class_size = sizeof(STM32CRSClass) }; + +static void stm32_crs_register_types(void) +{ + type_register_static(&stm32_crs_type_info); +} + +type_init(stm32_crs_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/crs.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/crs.h new file mode 100644 index 0000000000..e00b10074f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/crs.h @@ -0,0 +1,113 @@ +/* + * STM32- CRS(Clock recovery system) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRS_H_ +#define STM32_CRS_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRSDEVICE_PATH_STM32"CRS" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRSTYPE_STM32_PREFIX "crs" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRS_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRSParentClass; +typedef PeripheralState STM32CRSParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRSClass, (obj), TYPE_STM32_CRS) +#define STM32_CRS_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRSClass, (klass), TYPE_STM32_CRS) + +typedef struct { + // private: + STM32CRSParentClass parent_class; + // public: + + // None, so far. +} STM32CRSClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRS_STATE(obj) \ + OBJECT_CHECK(STM32CRSState, (obj), TYPE_STM32_CRS) + +typedef struct { + // private: + STM32CRSParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0CRS(Clock recovery system) registers. + struct { +Object *cr; // 0x0(Control register) +Object *cfgr; // 0x4(Configuration register) +Object *isr; // 0x8(Interrupt and status register) +Object *icr; // 0xC(Interrupt flag clear register) +} reg; + + struct { +// CR(Control register) bitfields. + struct { +Object *syncokie; // [0:0] SYNC event OK interrupt enableObject *syncwarnie; // [1:1] SYNC warning interrupt enableObject *errie; // [2:2] Synchronization or trimming error interrupt enableObject *esyncie; // [3:3] Expected SYNC interrupt enableObject *cen; // [5:5] Frequency error counter enableObject *autotrimen; // [6:6] Automatic trimming enableObject *swsync; // [7:7] Generate software SYNC eventObject *trim; // [8:13] HSI48 oscillator smooth trimming} cr; +// CFGR(Configuration register) bitfields. + struct { +Object *reload; // [0:15] Counter reload valueObject *felim; // [16:23] Frequency error limitObject *syncdiv; // [24:26] SYNC dividerObject *syncsrc; // [28:29] SYNC signal source selectionObject *syncpol; // [31:31] SYNC polarity selection} cfgr; +// ISR(Interrupt and status register) bitfields. + struct { +Object *syncokf; // [0:0] SYNC event OK flagObject *syncwarnf; // [1:1] SYNC warning flagObject *errf; // [2:2] Error flagObject *esyncf; // [3:3] Expected SYNC flagObject *syncerr; // [8:8] SYNC errorObject *syncmiss; // [9:9] SYNC missedObject *trimovf; // [10:10] Trimming overflow or underflowObject *fedir; // [15:15] Frequency error directionObject *fecap; // [16:31] Frequency error capture} isr; +// ICR(Interrupt flag clear register) bitfields. + struct { +Object *syncokc; // [0:0] SYNC event OK clear flagObject *syncwarnc; // [1:1] SYNC warning clear flagObject *errc; // [2:2] Error clear flagObject *esyncc; // [3:3] Expected SYNC clear flag} icr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRSState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRS_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/dac.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/dac.c new file mode 100644 index 0000000000..6dd0e7e283 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/dac.c @@ -0,0 +1,259 @@ +/* + * STM32- DAC(Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_dac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.swtrigr= cm_object_get_child_by_name(obj, "SWTRIGR"); +state->u.f0.reg.dhr12r1= cm_object_get_child_by_name(obj, "DHR12R1"); +state->u.f0.reg.dhr12l1= cm_object_get_child_by_name(obj, "DHR12L1"); +state->u.f0.reg.dhr8r1= cm_object_get_child_by_name(obj, "DHR8R1"); +state->u.f0.reg.dor1= cm_object_get_child_by_name(obj, "DOR1"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +// CRbitfields. +state->u.f0.fld.cr.lpds= cm_object_get_child_by_name(state->u.f0.reg.cr, "LPDS"); +state->u.f0.fld.cr.pdds= cm_object_get_child_by_name(state->u.f0.reg.cr, "PDDS"); +state->u.f0.fld.cr.cwuf= cm_object_get_child_by_name(state->u.f0.reg.cr, "CWUF"); +state->u.f0.fld.cr.csbf= cm_object_get_child_by_name(state->u.f0.reg.cr, "CSBF"); +state->u.f0.fld.cr.pvde= cm_object_get_child_by_name(state->u.f0.reg.cr, "PVDE"); +state->u.f0.fld.cr.pls= cm_object_get_child_by_name(state->u.f0.reg.cr, "PLS"); +state->u.f0.fld.cr.dbp= cm_object_get_child_by_name(state->u.f0.reg.cr, "DBP"); +// SWTRIGRbitfields. +state->u.f0.fld.swtrigr.swtrig1= cm_object_get_child_by_name(state->u.f0.reg.swtrigr, "SWTRIG1"); +// DHR12R1bitfields. +state->u.f0.fld.dhr12r1.dacc1dhr= cm_object_get_child_by_name(state->u.f0.reg.dhr12r1, "DACC1DHR"); +// DHR12L1bitfields. +state->u.f0.fld.dhr12l1.dacc1dhr= cm_object_get_child_by_name(state->u.f0.reg.dhr12l1, "DACC1DHR"); +// DHR8R1bitfields. +state->u.f0.fld.dhr8r1.dacc1dhr= cm_object_get_child_by_name(state->u.f0.reg.dhr8r1, "DACC1DHR"); +// DOR1bitfields. +state->u.f0.fld.dor1.dacc1dor= cm_object_get_child_by_name(state->u.f0.reg.dor1, "DACC1DOR"); +// SRbitfields. +state->u.f0.fld.sr.dmaudr1= cm_object_get_child_by_name(state->u.f0.reg.sr, "DMAUDR1"); +state->u.f0.fld.sr.dmaudr2= cm_object_get_child_by_name(state->u.f0.reg.sr, "DMAUDR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dac_is_enabled(Object *obj) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DACState *state = STM32_DAC_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DACState *state = STM32_DAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_dac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_dac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_dac_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DACEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DAC); +} + +static void stm32_dac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dac_reset_callback; + dc->realize = stm32_dac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dac_is_enabled; +} + +static const TypeInfo stm32_dac_type_info = { + .name = TYPE_STM32_DAC, + .parent = TYPE_STM32_DAC_PARENT, + .instance_init = stm32_dac_instance_init_callback, + .instance_size = sizeof(STM32DACState), + .class_init = stm32_dac_class_init_callback, + .class_size = sizeof(STM32DACClass) }; + +static void stm32_dac_register_types(void) +{ + type_register_static(&stm32_dac_type_info); +} + +type_init(stm32_dac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/dac.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/dac.h new file mode 100644 index 0000000000..13587ea293 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/dac.h @@ -0,0 +1,125 @@ +/* + * STM32- DAC(Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DAC_H_ +#define STM32_DAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DACDEVICE_PATH_STM32"DAC" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DACTYPE_STM32_PREFIX "dac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DACParentClass; +typedef PeripheralState STM32DACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DACClass, (obj), TYPE_STM32_DAC) +#define STM32_DAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DACClass, (klass), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentClass parent_class; + // public: + + // None, so far. +} STM32DACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DAC_STATE(obj) \ + OBJECT_CHECK(STM32DACState, (obj), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0DAC(Digital-to-analog converter) registers. + struct { +Object *cr; // 0x0(Control register) +Object *swtrigr; // 0x4(Software trigger register) +Object *dhr12r1; // 0x8(Channel1 12-bit right-aligned data holding register) +Object *dhr12l1; // 0xC(Channel1 12-bit left aligned data holding register) +Object *dhr8r1; // 0x10(Channel1 8-bit right aligned data holding register) +Object *dor1; // 0x2C(Channel1 data output register) +Object *sr; // 0x34(Status register) +} reg; + + struct { +// CR(Control register) bitfields. + struct { +Object *lpds; // [0:0] Low-power deep sleepObject *pdds; // [1:1] Power down deepsleepObject *cwuf; // [2:2] Clear wakeup flagObject *csbf; // [3:3] Clear standby flagObject *pvde; // [4:4] Power voltage detector enableObject *pls; // [5:7] PVD level selectionObject *dbp; // [8:8] Disable backup domain write protection} cr; +// SWTRIGR(Software trigger register) bitfields. + struct { +Object *swtrig1; // [0:0] DAC channel1 software trigger} swtrigr; +// DHR12R1(Channel1 12-bit right-aligned data holding register) bitfields. + struct { +Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data} dhr12r1; +// DHR12L1(Channel1 12-bit left aligned data holding register) bitfields. + struct { +Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data} dhr12l1; +// DHR8R1(Channel1 8-bit right aligned data holding register) bitfields. + struct { +Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data} dhr8r1; +// DOR1(Channel1 data output register) bitfields. + struct { +Object *dacc1dor; // [0:11] DAC channel1 data output} dor1; +// SR(Status register) bitfields. + struct { +Object *dmaudr1; // [13:13] DAC channel1 DMA underrun flagObject *dmaudr2; // [29:29] DAC channel2 DMA underrun flag} sr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/dbgmcu.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/dbgmcu.c new file mode 100644 index 0000000000..01e465ac11 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/dbgmcu.c @@ -0,0 +1,256 @@ +/* + * STM32- DBGMCU(Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_dbgmcu_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.idcode= cm_object_get_child_by_name(obj, "IDCODE"); +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.apblfz= cm_object_get_child_by_name(obj, "APBLFZ"); +state->u.f0.reg.apbhfz= cm_object_get_child_by_name(obj, "APBHFZ"); +// IDCODEbitfields. +state->u.f0.fld.idcode.dev_id= cm_object_get_child_by_name(state->u.f0.reg.idcode, "DEV_ID"); +state->u.f0.fld.idcode.div_id= cm_object_get_child_by_name(state->u.f0.reg.idcode, "DIV_ID"); +state->u.f0.fld.idcode.rev_id= cm_object_get_child_by_name(state->u.f0.reg.idcode, "REV_ID"); +// CRbitfields. +state->u.f0.fld.cr.dbg_stop= cm_object_get_child_by_name(state->u.f0.reg.cr, "DBG_STOP"); +state->u.f0.fld.cr.dbg_standby= cm_object_get_child_by_name(state->u.f0.reg.cr, "DBG_STANDBY"); +// APBLFZbitfields. +state->u.f0.fld.apblfz.dbg_timer2_stop= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER2_STOP"); +state->u.f0.fld.apblfz.dbg_timer3_stop= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER3_STOP"); +state->u.f0.fld.apblfz.dbg_timer6_stop= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER6_STOP"); +state->u.f0.fld.apblfz.dbg_timer14_stop= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_TIMER14_STOP"); +state->u.f0.fld.apblfz.dbg_rtc_stop= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_RTC_STOP"); +state->u.f0.fld.apblfz.dbg_wwdg_stop= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_WWDG_STOP"); +state->u.f0.fld.apblfz.dbg_iwdg_stop= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "DBG_IWDG_STOP"); +state->u.f0.fld.apblfz.i2c1_smbus_timeout= cm_object_get_child_by_name(state->u.f0.reg.apblfz, "I2C1_SMBUS_TIMEOUT"); +// APBHFZbitfields. +state->u.f0.fld.apbhfz.dbg_timer1_stop= cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER1_STOP"); +state->u.f0.fld.apbhfz.dbg_timer15_sto= cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER15_STO"); +state->u.f0.fld.apbhfz.dbg_timer16_sto= cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER16_STO"); +state->u.f0.fld.apbhfz.dbg_timer17_sto= cm_object_get_child_by_name(state->u.f0.reg.apbhfz, "DBG_TIMER17_STO"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dbgmcu_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dbgmcu_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dbgmcu_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dbgmcu_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dbgmcu_is_enabled(Object *obj) +{ + STM32DBGMCUState *state = STM32_DBGMCU_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dbgmcu_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DBGMCUState *state = STM32_DBGMCU_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dbgmcu_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DBGMCU)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DBGMCUState *state = STM32_DBGMCU_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DBGMCU"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_dbgmcu_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dbgmcu_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_dbgmcu_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dbgmcu_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_dbgmcu_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DBGMCUEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dbgmcu_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DBGMCU); +} + +static void stm32_dbgmcu_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dbgmcu_reset_callback; + dc->realize = stm32_dbgmcu_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dbgmcu_is_enabled; +} + +static const TypeInfo stm32_dbgmcu_type_info = { + .name = TYPE_STM32_DBGMCU, + .parent = TYPE_STM32_DBGMCU_PARENT, + .instance_init = stm32_dbgmcu_instance_init_callback, + .instance_size = sizeof(STM32DBGMCUState), + .class_init = stm32_dbgmcu_class_init_callback, + .class_size = sizeof(STM32DBGMCUClass) }; + +static void stm32_dbgmcu_register_types(void) +{ + type_register_static(&stm32_dbgmcu_type_info); +} + +type_init(stm32_dbgmcu_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/dbgmcu.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/dbgmcu.h new file mode 100644 index 0000000000..707257f9e7 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/dbgmcu.h @@ -0,0 +1,113 @@ +/* + * STM32- DBGMCU(Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DBGMCU_H_ +#define STM32_DBGMCU_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DBGMCUDEVICE_PATH_STM32"DBGMCU" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DBGMCUTYPE_STM32_PREFIX "dbgmcu" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DBGMCU_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DBGMCUParentClass; +typedef PeripheralState STM32DBGMCUParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DBGMCU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DBGMCUClass, (obj), TYPE_STM32_DBGMCU) +#define STM32_DBGMCU_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DBGMCUClass, (klass), TYPE_STM32_DBGMCU) + +typedef struct { + // private: + STM32DBGMCUParentClass parent_class; + // public: + + // None, so far. +} STM32DBGMCUClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DBGMCU_STATE(obj) \ + OBJECT_CHECK(STM32DBGMCUState, (obj), TYPE_STM32_DBGMCU) + +typedef struct { + // private: + STM32DBGMCUParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0DBGMCU(Debug support) registers. + struct { +Object *idcode; // 0x0(MCU Device ID Code Register) +Object *cr; // 0x4(Debug MCU Configuration Register) +Object *apblfz; // 0x8(APB Low Freeze Register) +Object *apbhfz; // 0xC(APB High Freeze Register) +} reg; + + struct { +// IDCODE(MCU Device ID Code Register) bitfields. + struct { +Object *dev_id; // [0:11] Device IdentifierObject *div_id; // [12:15] Division IdentifierObject *rev_id; // [16:31] Revision Identifier} idcode; +// CR(Debug MCU Configuration Register) bitfields. + struct { +Object *dbg_stop; // [1:1] Debug Stop ModeObject *dbg_standby; // [2:2] Debug Standby Mode} cr; +// APBLFZ(APB Low Freeze Register) bitfields. + struct { +Object *dbg_timer2_stop; // [0:0] Debug Timer 2 stopped when Core is haltedObject *dbg_timer3_stop; // [1:1] Debug Timer 3 stopped when Core is haltedObject *dbg_timer6_stop; // [4:4] Debug Timer 6 stopped when Core is haltedObject *dbg_timer14_stop; // [8:8] Debug Timer 14 stopped when Core is haltedObject *dbg_rtc_stop; // [10:10] Debug RTC stopped when Core is haltedObject *dbg_wwdg_stop; // [11:11] Debug Window Wachdog stopped when Core is haltedObject *dbg_iwdg_stop; // [12:12] Debug Independent Wachdog stopped when Core is haltedObject *i2c1_smbus_timeout; // [21:21] SMBUS timeout mode stopped when Core is halted} apblfz; +// APBHFZ(APB High Freeze Register) bitfields. + struct { +Object *dbg_timer1_stop; // [11:11] Debug Timer 1 stopped when Core is haltedObject *dbg_timer15_sto; // [16:16] Debug Timer 15 stopped when Core is haltedObject *dbg_timer16_sto; // [17:17] Debug Timer 16 stopped when Core is haltedObject *dbg_timer17_sto; // [18:18] Debug Timer 17 stopped when Core is halted} apbhfz; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DBGMCUState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DBGMCU_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/dma1.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/dma1.c new file mode 100644 index 0000000000..dc032575f2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/dma1.c @@ -0,0 +1,456 @@ +/* + * STM32- DMA(DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.ifcr= cm_object_get_child_by_name(obj, "IFCR"); +state->u.f0.reg.ccr1= cm_object_get_child_by_name(obj, "CCR1"); +state->u.f0.reg.cndtr1= cm_object_get_child_by_name(obj, "CNDTR1"); +state->u.f0.reg.cpar1= cm_object_get_child_by_name(obj, "CPAR1"); +state->u.f0.reg.cmar1= cm_object_get_child_by_name(obj, "CMAR1"); +state->u.f0.reg.ccr2= cm_object_get_child_by_name(obj, "CCR2"); +state->u.f0.reg.cndtr2= cm_object_get_child_by_name(obj, "CNDTR2"); +state->u.f0.reg.cpar2= cm_object_get_child_by_name(obj, "CPAR2"); +state->u.f0.reg.cmar2= cm_object_get_child_by_name(obj, "CMAR2"); +state->u.f0.reg.ccr3= cm_object_get_child_by_name(obj, "CCR3"); +state->u.f0.reg.cndtr3= cm_object_get_child_by_name(obj, "CNDTR3"); +state->u.f0.reg.cpar3= cm_object_get_child_by_name(obj, "CPAR3"); +state->u.f0.reg.cmar3= cm_object_get_child_by_name(obj, "CMAR3"); +state->u.f0.reg.ccr4= cm_object_get_child_by_name(obj, "CCR4"); +state->u.f0.reg.cndtr4= cm_object_get_child_by_name(obj, "CNDTR4"); +state->u.f0.reg.cpar4= cm_object_get_child_by_name(obj, "CPAR4"); +state->u.f0.reg.cmar4= cm_object_get_child_by_name(obj, "CMAR4"); +state->u.f0.reg.ccr5= cm_object_get_child_by_name(obj, "CCR5"); +state->u.f0.reg.cndtr5= cm_object_get_child_by_name(obj, "CNDTR5"); +state->u.f0.reg.cpar5= cm_object_get_child_by_name(obj, "CPAR5"); +state->u.f0.reg.cmar5= cm_object_get_child_by_name(obj, "CMAR5"); +state->u.f0.reg.ccr6= cm_object_get_child_by_name(obj, "CCR6"); +state->u.f0.reg.cndtr6= cm_object_get_child_by_name(obj, "CNDTR6"); +state->u.f0.reg.cpar6= cm_object_get_child_by_name(obj, "CPAR6"); +state->u.f0.reg.cmar6= cm_object_get_child_by_name(obj, "CMAR6"); +state->u.f0.reg.ccr7= cm_object_get_child_by_name(obj, "CCR7"); +state->u.f0.reg.cndtr7= cm_object_get_child_by_name(obj, "CNDTR7"); +state->u.f0.reg.cpar7= cm_object_get_child_by_name(obj, "CPAR7"); +state->u.f0.reg.cmar7= cm_object_get_child_by_name(obj, "CMAR7"); +// ISRbitfields. +state->u.f0.fld.isr.gif1= cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF1"); +state->u.f0.fld.isr.tcif1= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF1"); +state->u.f0.fld.isr.htif1= cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF1"); +state->u.f0.fld.isr.teif1= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF1"); +state->u.f0.fld.isr.gif2= cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF2"); +state->u.f0.fld.isr.tcif2= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF2"); +state->u.f0.fld.isr.htif2= cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF2"); +state->u.f0.fld.isr.teif2= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF2"); +state->u.f0.fld.isr.gif3= cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF3"); +state->u.f0.fld.isr.tcif3= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF3"); +state->u.f0.fld.isr.htif3= cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF3"); +state->u.f0.fld.isr.teif3= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF3"); +state->u.f0.fld.isr.gif4= cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF4"); +state->u.f0.fld.isr.tcif4= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF4"); +state->u.f0.fld.isr.htif4= cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF4"); +state->u.f0.fld.isr.teif4= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF4"); +state->u.f0.fld.isr.gif5= cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF5"); +state->u.f0.fld.isr.tcif5= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF5"); +state->u.f0.fld.isr.htif5= cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF5"); +state->u.f0.fld.isr.teif5= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF5"); +state->u.f0.fld.isr.gif6= cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF6"); +state->u.f0.fld.isr.tcif6= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF6"); +state->u.f0.fld.isr.htif6= cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF6"); +state->u.f0.fld.isr.teif6= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF6"); +state->u.f0.fld.isr.gif7= cm_object_get_child_by_name(state->u.f0.reg.isr, "GIF7"); +state->u.f0.fld.isr.tcif7= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCIF7"); +state->u.f0.fld.isr.htif7= cm_object_get_child_by_name(state->u.f0.reg.isr, "HTIF7"); +state->u.f0.fld.isr.teif7= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEIF7"); +// IFCRbitfields. +state->u.f0.fld.ifcr.cgif1= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF1"); +state->u.f0.fld.ifcr.ctcif1= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF1"); +state->u.f0.fld.ifcr.chtif1= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF1"); +state->u.f0.fld.ifcr.cteif1= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF1"); +state->u.f0.fld.ifcr.cgif2= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF2"); +state->u.f0.fld.ifcr.ctcif2= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF2"); +state->u.f0.fld.ifcr.chtif2= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF2"); +state->u.f0.fld.ifcr.cteif2= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF2"); +state->u.f0.fld.ifcr.cgif3= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF3"); +state->u.f0.fld.ifcr.ctcif3= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF3"); +state->u.f0.fld.ifcr.chtif3= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF3"); +state->u.f0.fld.ifcr.cteif3= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF3"); +state->u.f0.fld.ifcr.cgif4= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF4"); +state->u.f0.fld.ifcr.ctcif4= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF4"); +state->u.f0.fld.ifcr.chtif4= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF4"); +state->u.f0.fld.ifcr.cteif4= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF4"); +state->u.f0.fld.ifcr.cgif5= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF5"); +state->u.f0.fld.ifcr.ctcif5= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF5"); +state->u.f0.fld.ifcr.chtif5= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF5"); +state->u.f0.fld.ifcr.cteif5= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF5"); +state->u.f0.fld.ifcr.cgif6= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF6"); +state->u.f0.fld.ifcr.ctcif6= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF6"); +state->u.f0.fld.ifcr.chtif6= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF6"); +state->u.f0.fld.ifcr.cteif6= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF6"); +state->u.f0.fld.ifcr.cgif7= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CGIF7"); +state->u.f0.fld.ifcr.ctcif7= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTCIF7"); +state->u.f0.fld.ifcr.chtif7= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CHTIF7"); +state->u.f0.fld.ifcr.cteif7= cm_object_get_child_by_name(state->u.f0.reg.ifcr, "CTEIF7"); +// CCR1bitfields. +state->u.f0.fld.ccr1.en= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "EN"); +state->u.f0.fld.ccr1.tcie= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "TCIE"); +state->u.f0.fld.ccr1.htie= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "HTIE"); +state->u.f0.fld.ccr1.teie= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "TEIE"); +state->u.f0.fld.ccr1.dir= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "DIR"); +state->u.f0.fld.ccr1.circ= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CIRC"); +state->u.f0.fld.ccr1.pinc= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "PINC"); +state->u.f0.fld.ccr1.minc= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "MINC"); +state->u.f0.fld.ccr1.psize= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "PSIZE"); +state->u.f0.fld.ccr1.msize= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "MSIZE"); +state->u.f0.fld.ccr1.pl= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "PL"); +state->u.f0.fld.ccr1.mem2mem= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "MEM2MEM"); +// CNDTR1bitfields. +state->u.f0.fld.cndtr1.ndt= cm_object_get_child_by_name(state->u.f0.reg.cndtr1, "NDT"); +// CPAR1bitfields. +state->u.f0.fld.cpar1.pa= cm_object_get_child_by_name(state->u.f0.reg.cpar1, "PA"); +// CMAR1bitfields. +state->u.f0.fld.cmar1.ma= cm_object_get_child_by_name(state->u.f0.reg.cmar1, "MA"); +// CCR2bitfields. +state->u.f0.fld.ccr2.en= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "EN"); +state->u.f0.fld.ccr2.tcie= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "TCIE"); +state->u.f0.fld.ccr2.htie= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "HTIE"); +state->u.f0.fld.ccr2.teie= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "TEIE"); +state->u.f0.fld.ccr2.dir= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "DIR"); +state->u.f0.fld.ccr2.circ= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CIRC"); +state->u.f0.fld.ccr2.pinc= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "PINC"); +state->u.f0.fld.ccr2.minc= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "MINC"); +state->u.f0.fld.ccr2.psize= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "PSIZE"); +state->u.f0.fld.ccr2.msize= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "MSIZE"); +state->u.f0.fld.ccr2.pl= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "PL"); +state->u.f0.fld.ccr2.mem2mem= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "MEM2MEM"); +// CNDTR2bitfields. +state->u.f0.fld.cndtr2.ndt= cm_object_get_child_by_name(state->u.f0.reg.cndtr2, "NDT"); +// CPAR2bitfields. +state->u.f0.fld.cpar2.pa= cm_object_get_child_by_name(state->u.f0.reg.cpar2, "PA"); +// CMAR2bitfields. +state->u.f0.fld.cmar2.ma= cm_object_get_child_by_name(state->u.f0.reg.cmar2, "MA"); +// CCR3bitfields. +state->u.f0.fld.ccr3.en= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "EN"); +state->u.f0.fld.ccr3.tcie= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "TCIE"); +state->u.f0.fld.ccr3.htie= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "HTIE"); +state->u.f0.fld.ccr3.teie= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "TEIE"); +state->u.f0.fld.ccr3.dir= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "DIR"); +state->u.f0.fld.ccr3.circ= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CIRC"); +state->u.f0.fld.ccr3.pinc= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "PINC"); +state->u.f0.fld.ccr3.minc= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "MINC"); +state->u.f0.fld.ccr3.psize= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "PSIZE"); +state->u.f0.fld.ccr3.msize= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "MSIZE"); +state->u.f0.fld.ccr3.pl= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "PL"); +state->u.f0.fld.ccr3.mem2mem= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "MEM2MEM"); +// CNDTR3bitfields. +state->u.f0.fld.cndtr3.ndt= cm_object_get_child_by_name(state->u.f0.reg.cndtr3, "NDT"); +// CPAR3bitfields. +state->u.f0.fld.cpar3.pa= cm_object_get_child_by_name(state->u.f0.reg.cpar3, "PA"); +// CMAR3bitfields. +state->u.f0.fld.cmar3.ma= cm_object_get_child_by_name(state->u.f0.reg.cmar3, "MA"); +// CCR4bitfields. +state->u.f0.fld.ccr4.en= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "EN"); +state->u.f0.fld.ccr4.tcie= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "TCIE"); +state->u.f0.fld.ccr4.htie= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "HTIE"); +state->u.f0.fld.ccr4.teie= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "TEIE"); +state->u.f0.fld.ccr4.dir= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "DIR"); +state->u.f0.fld.ccr4.circ= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CIRC"); +state->u.f0.fld.ccr4.pinc= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "PINC"); +state->u.f0.fld.ccr4.minc= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "MINC"); +state->u.f0.fld.ccr4.psize= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "PSIZE"); +state->u.f0.fld.ccr4.msize= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "MSIZE"); +state->u.f0.fld.ccr4.pl= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "PL"); +state->u.f0.fld.ccr4.mem2mem= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "MEM2MEM"); +// CNDTR4bitfields. +state->u.f0.fld.cndtr4.ndt= cm_object_get_child_by_name(state->u.f0.reg.cndtr4, "NDT"); +// CPAR4bitfields. +state->u.f0.fld.cpar4.pa= cm_object_get_child_by_name(state->u.f0.reg.cpar4, "PA"); +// CMAR4bitfields. +state->u.f0.fld.cmar4.ma= cm_object_get_child_by_name(state->u.f0.reg.cmar4, "MA"); +// CCR5bitfields. +state->u.f0.fld.ccr5.en= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "EN"); +state->u.f0.fld.ccr5.tcie= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "TCIE"); +state->u.f0.fld.ccr5.htie= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "HTIE"); +state->u.f0.fld.ccr5.teie= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "TEIE"); +state->u.f0.fld.ccr5.dir= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "DIR"); +state->u.f0.fld.ccr5.circ= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "CIRC"); +state->u.f0.fld.ccr5.pinc= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "PINC"); +state->u.f0.fld.ccr5.minc= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "MINC"); +state->u.f0.fld.ccr5.psize= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "PSIZE"); +state->u.f0.fld.ccr5.msize= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "MSIZE"); +state->u.f0.fld.ccr5.pl= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "PL"); +state->u.f0.fld.ccr5.mem2mem= cm_object_get_child_by_name(state->u.f0.reg.ccr5, "MEM2MEM"); +// CNDTR5bitfields. +state->u.f0.fld.cndtr5.ndt= cm_object_get_child_by_name(state->u.f0.reg.cndtr5, "NDT"); +// CPAR5bitfields. +state->u.f0.fld.cpar5.pa= cm_object_get_child_by_name(state->u.f0.reg.cpar5, "PA"); +// CMAR5bitfields. +state->u.f0.fld.cmar5.ma= cm_object_get_child_by_name(state->u.f0.reg.cmar5, "MA"); +// CCR6bitfields. +state->u.f0.fld.ccr6.en= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "EN"); +state->u.f0.fld.ccr6.tcie= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "TCIE"); +state->u.f0.fld.ccr6.htie= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "HTIE"); +state->u.f0.fld.ccr6.teie= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "TEIE"); +state->u.f0.fld.ccr6.dir= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "DIR"); +state->u.f0.fld.ccr6.circ= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "CIRC"); +state->u.f0.fld.ccr6.pinc= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "PINC"); +state->u.f0.fld.ccr6.minc= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "MINC"); +state->u.f0.fld.ccr6.psize= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "PSIZE"); +state->u.f0.fld.ccr6.msize= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "MSIZE"); +state->u.f0.fld.ccr6.pl= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "PL"); +state->u.f0.fld.ccr6.mem2mem= cm_object_get_child_by_name(state->u.f0.reg.ccr6, "MEM2MEM"); +// CNDTR6bitfields. +state->u.f0.fld.cndtr6.ndt= cm_object_get_child_by_name(state->u.f0.reg.cndtr6, "NDT"); +// CPAR6bitfields. +state->u.f0.fld.cpar6.pa= cm_object_get_child_by_name(state->u.f0.reg.cpar6, "PA"); +// CMAR6bitfields. +state->u.f0.fld.cmar6.ma= cm_object_get_child_by_name(state->u.f0.reg.cmar6, "MA"); +// CCR7bitfields. +state->u.f0.fld.ccr7.en= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "EN"); +state->u.f0.fld.ccr7.tcie= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "TCIE"); +state->u.f0.fld.ccr7.htie= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "HTIE"); +state->u.f0.fld.ccr7.teie= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "TEIE"); +state->u.f0.fld.ccr7.dir= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "DIR"); +state->u.f0.fld.ccr7.circ= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "CIRC"); +state->u.f0.fld.ccr7.pinc= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "PINC"); +state->u.f0.fld.ccr7.minc= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "MINC"); +state->u.f0.fld.ccr7.psize= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "PSIZE"); +state->u.f0.fld.ccr7.msize= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "MSIZE"); +state->u.f0.fld.ccr7.pl= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "PL"); +state->u.f0.fld.ccr7.mem2mem= cm_object_get_child_by_name(state->u.f0.reg.ccr7, "MEM2MEM"); +// CNDTR7bitfields. +state->u.f0.fld.cndtr7.ndt= cm_object_get_child_by_name(state->u.f0.reg.cndtr7, "NDT"); +// CPAR7bitfields. +state->u.f0.fld.cpar7.pa= cm_object_get_child_by_name(state->u.f0.reg.cpar7, "PA"); +// CMAR7bitfields. +state->u.f0.fld.cmar7.ma= cm_object_get_child_by_name(state->u.f0.reg.cmar7, "MA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma_is_enabled(Object *obj) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMAState *state = STM32_DMA_STATE(obj); + + // Capabilities are not yet available. + +cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_DMA_UNDEFINED; +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMAState *state = STM32_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_dma_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA%dEN", + 1 + state->port_index - STM32_PORT_DMA1); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA); +} + +static void stm32_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma_reset_callback; + dc->realize = stm32_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma_is_enabled; +} + +static const TypeInfo stm32_dma_type_info = { + .name = TYPE_STM32_DMA, + .parent = TYPE_STM32_DMA_PARENT, + .instance_init = stm32_dma_instance_init_callback, + .instance_size = sizeof(STM32DMAState), + .class_init = stm32_dma_class_init_callback, + .class_size = sizeof(STM32DMAClass) }; + +static void stm32_dma_register_types(void) +{ + type_register_static(&stm32_dma_type_info); +} + +type_init(stm32_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/dma1.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/dma1.h new file mode 100644 index 0000000000..20ff83b5b4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/dma1.h @@ -0,0 +1,227 @@ +/* + * STM32- DMA(DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA_H_ +#define STM32_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMADEVICE_PATH_STM32"DMA" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. +STM32_PORT_DMA1, +STM32_PORT_DMA_UNDEFINED = 0xFF, +} stm32_dma_index_t; +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMATYPE_STM32_PREFIX "dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMAParentClass; +typedef PeripheralState STM32DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMAClass, (obj), TYPE_STM32_DMA) +#define STM32_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMAClass, (klass), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentClass parent_class; + // public: + + // None, so far. +} STM32DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA_STATE(obj) \ + OBJECT_CHECK(STM32DMAState, (obj), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +// Remove it if there is only one port + stm32_dma_index_t port_index; +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0DMA(DMA controller) registers. + struct { +Object *isr; // 0x0(DMA interrupt status register (DMA_ISR)) +Object *ifcr; // 0x4(DMA interrupt flag clear register (DMA_IFCR)) +Object *ccr1; // 0x8(DMA channel configuration register (DMA_CCR)) +Object *cndtr1; // 0xC(DMA channel 1 number of data register) +Object *cpar1; // 0x10(DMA channel 1 peripheral address register) +Object *cmar1; // 0x14(DMA channel 1 memory address register) +Object *ccr2; // 0x1C(DMA channel configuration register (DMA_CCR)) +Object *cndtr2; // 0x20(DMA channel 2 number of data register) +Object *cpar2; // 0x24(DMA channel 2 peripheral address register) +Object *cmar2; // 0x28(DMA channel 2 memory address register) +Object *ccr3; // 0x30(DMA channel configuration register (DMA_CCR)) +Object *cndtr3; // 0x34(DMA channel 3 number of data register) +Object *cpar3; // 0x38(DMA channel 3 peripheral address register) +Object *cmar3; // 0x3C(DMA channel 3 memory address register) +Object *ccr4; // 0x44(DMA channel configuration register (DMA_CCR)) +Object *cndtr4; // 0x48(DMA channel 4 number of data register) +Object *cpar4; // 0x4C(DMA channel 4 peripheral address register) +Object *cmar4; // 0x50(DMA channel 4 memory address register) +Object *ccr5; // 0x58(DMA channel configuration register (DMA_CCR)) +Object *cndtr5; // 0x5C(DMA channel 5 number of data register) +Object *cpar5; // 0x60(DMA channel 5 peripheral address register) +Object *cmar5; // 0x64(DMA channel 5 memory address register) +Object *ccr6; // 0x6C(DMA channel configuration register (DMA_CCR)) +Object *cndtr6; // 0x70(DMA channel 6 number of data register) +Object *cpar6; // 0x74(DMA channel 6 peripheral address register) +Object *cmar6; // 0x78(DMA channel 6 memory address register) +Object *ccr7; // 0x80(DMA channel configuration register (DMA_CCR)) +Object *cndtr7; // 0x84(DMA channel 7 number of data register) +Object *cpar7; // 0x88(DMA channel 7 peripheral address register) +Object *cmar7; // 0x8C(DMA channel 7 memory address register) +} reg; + + struct { +// ISR(DMA interrupt status register (DMA_ISR)) bitfields. + struct { +Object *gif1; // [0:0] Channel 1 Global interrupt flagObject *tcif1; // [1:1] Channel 1 Transfer Complete flagObject *htif1; // [2:2] Channel 1 Half Transfer Complete flagObject *teif1; // [3:3] Channel 1 Transfer Error flagObject *gif2; // [4:4] Channel 2 Global interrupt flagObject *tcif2; // [5:5] Channel 2 Transfer Complete flagObject *htif2; // [6:6] Channel 2 Half Transfer Complete flagObject *teif2; // [7:7] Channel 2 Transfer Error flagObject *gif3; // [8:8] Channel 3 Global interrupt flagObject *tcif3; // [9:9] Channel 3 Transfer Complete flagObject *htif3; // [10:10] Channel 3 Half Transfer Complete flagObject *teif3; // [11:11] Channel 3 Transfer Error flagObject *gif4; // [12:12] Channel 4 Global interrupt flagObject *tcif4; // [13:13] Channel 4 Transfer Complete flagObject *htif4; // [14:14] Channel 4 Half Transfer Complete flagObject *teif4; // [15:15] Channel 4 Transfer Error flagObject *gif5; // [16:16] Channel 5 Global interrupt flagObject *tcif5; // [17:17] Channel 5 Transfer Complete flagObject *htif5; // [18:18] Channel 5 Half Transfer Complete flagObject *teif5; // [19:19] Channel 5 Transfer Error flagObject *gif6; // [20:20] Channel 6 Global interrupt flagObject *tcif6; // [21:21] Channel 6 Transfer Complete flagObject *htif6; // [22:22] Channel 6 Half Transfer Complete flagObject *teif6; // [23:23] Channel 6 Transfer Error flagObject *gif7; // [24:24] Channel 7 Global interrupt flagObject *tcif7; // [25:25] Channel 7 Transfer Complete flagObject *htif7; // [26:26] Channel 7 Half Transfer Complete flagObject *teif7; // [27:27] Channel 7 Transfer Error flag} isr; +// IFCR(DMA interrupt flag clear register (DMA_IFCR)) bitfields. + struct { +Object *cgif1; // [0:0] Channel 1 Global interrupt clearObject *ctcif1; // [1:1] Channel 1 Transfer Complete clearObject *chtif1; // [2:2] Channel 1 Half Transfer clearObject *cteif1; // [3:3] Channel 1 Transfer Error clearObject *cgif2; // [4:4] Channel 2 Global interrupt clearObject *ctcif2; // [5:5] Channel 2 Transfer Complete clearObject *chtif2; // [6:6] Channel 2 Half Transfer clearObject *cteif2; // [7:7] Channel 2 Transfer Error clearObject *cgif3; // [8:8] Channel 3 Global interrupt clearObject *ctcif3; // [9:9] Channel 3 Transfer Complete clearObject *chtif3; // [10:10] Channel 3 Half Transfer clearObject *cteif3; // [11:11] Channel 3 Transfer Error clearObject *cgif4; // [12:12] Channel 4 Global interrupt clearObject *ctcif4; // [13:13] Channel 4 Transfer Complete clearObject *chtif4; // [14:14] Channel 4 Half Transfer clearObject *cteif4; // [15:15] Channel 4 Transfer Error clearObject *cgif5; // [16:16] Channel 5 Global interrupt clearObject *ctcif5; // [17:17] Channel 5 Transfer Complete clearObject *chtif5; // [18:18] Channel 5 Half Transfer clearObject *cteif5; // [19:19] Channel 5 Transfer Error clearObject *cgif6; // [20:20] Channel 6 Global interrupt clearObject *ctcif6; // [21:21] Channel 6 Transfer Complete clearObject *chtif6; // [22:22] Channel 6 Half Transfer clearObject *cteif6; // [23:23] Channel 6 Transfer Error clearObject *cgif7; // [24:24] Channel 7 Global interrupt clearObject *ctcif7; // [25:25] Channel 7 Transfer Complete clearObject *chtif7; // [26:26] Channel 7 Half Transfer clearObject *cteif7; // [27:27] Channel 7 Transfer Error clear} ifcr; +// CCR1(DMA channel configuration register (DMA_CCR)) bitfields. + struct { +Object *en; // [0:0] Channel enableObject *tcie; // [1:1] Transfer complete interrupt enableObject *htie; // [2:2] Half Transfer interrupt enableObject *teie; // [3:3] Transfer error interrupt enableObject *dir; // [4:4] Data transfer directionObject *circ; // [5:5] Circular modeObject *pinc; // [6:6] Peripheral increment modeObject *minc; // [7:7] Memory increment modeObject *psize; // [8:9] Peripheral sizeObject *msize; // [10:11] Memory sizeObject *pl; // [12:13] Channel Priority levelObject *mem2mem; // [14:14] Memory to memory mode} ccr1; +// CNDTR1(DMA channel 1 number of data register) bitfields. + struct { +Object *ndt; // [0:15] Number of data to transfer} cndtr1; +// CPAR1(DMA channel 1 peripheral address register) bitfields. + struct { +Object *pa; // [0:31] Peripheral address} cpar1; +// CMAR1(DMA channel 1 memory address register) bitfields. + struct { +Object *ma; // [0:31] Memory address} cmar1; +// CCR2(DMA channel configuration register (DMA_CCR)) bitfields. + struct { +Object *en; // [0:0] Channel enableObject *tcie; // [1:1] Transfer complete interrupt enableObject *htie; // [2:2] Half Transfer interrupt enableObject *teie; // [3:3] Transfer error interrupt enableObject *dir; // [4:4] Data transfer directionObject *circ; // [5:5] Circular modeObject *pinc; // [6:6] Peripheral increment modeObject *minc; // [7:7] Memory increment modeObject *psize; // [8:9] Peripheral sizeObject *msize; // [10:11] Memory sizeObject *pl; // [12:13] Channel Priority levelObject *mem2mem; // [14:14] Memory to memory mode} ccr2; +// CNDTR2(DMA channel 2 number of data register) bitfields. + struct { +Object *ndt; // [0:15] Number of data to transfer} cndtr2; +// CPAR2(DMA channel 2 peripheral address register) bitfields. + struct { +Object *pa; // [0:31] Peripheral address} cpar2; +// CMAR2(DMA channel 2 memory address register) bitfields. + struct { +Object *ma; // [0:31] Memory address} cmar2; +// CCR3(DMA channel configuration register (DMA_CCR)) bitfields. + struct { +Object *en; // [0:0] Channel enableObject *tcie; // [1:1] Transfer complete interrupt enableObject *htie; // [2:2] Half Transfer interrupt enableObject *teie; // [3:3] Transfer error interrupt enableObject *dir; // [4:4] Data transfer directionObject *circ; // [5:5] Circular modeObject *pinc; // [6:6] Peripheral increment modeObject *minc; // [7:7] Memory increment modeObject *psize; // [8:9] Peripheral sizeObject *msize; // [10:11] Memory sizeObject *pl; // [12:13] Channel Priority levelObject *mem2mem; // [14:14] Memory to memory mode} ccr3; +// CNDTR3(DMA channel 3 number of data register) bitfields. + struct { +Object *ndt; // [0:15] Number of data to transfer} cndtr3; +// CPAR3(DMA channel 3 peripheral address register) bitfields. + struct { +Object *pa; // [0:31] Peripheral address} cpar3; +// CMAR3(DMA channel 3 memory address register) bitfields. + struct { +Object *ma; // [0:31] Memory address} cmar3; +// CCR4(DMA channel configuration register (DMA_CCR)) bitfields. + struct { +Object *en; // [0:0] Channel enableObject *tcie; // [1:1] Transfer complete interrupt enableObject *htie; // [2:2] Half Transfer interrupt enableObject *teie; // [3:3] Transfer error interrupt enableObject *dir; // [4:4] Data transfer directionObject *circ; // [5:5] Circular modeObject *pinc; // [6:6] Peripheral increment modeObject *minc; // [7:7] Memory increment modeObject *psize; // [8:9] Peripheral sizeObject *msize; // [10:11] Memory sizeObject *pl; // [12:13] Channel Priority levelObject *mem2mem; // [14:14] Memory to memory mode} ccr4; +// CNDTR4(DMA channel 4 number of data register) bitfields. + struct { +Object *ndt; // [0:15] Number of data to transfer} cndtr4; +// CPAR4(DMA channel 4 peripheral address register) bitfields. + struct { +Object *pa; // [0:31] Peripheral address} cpar4; +// CMAR4(DMA channel 4 memory address register) bitfields. + struct { +Object *ma; // [0:31] Memory address} cmar4; +// CCR5(DMA channel configuration register (DMA_CCR)) bitfields. + struct { +Object *en; // [0:0] Channel enableObject *tcie; // [1:1] Transfer complete interrupt enableObject *htie; // [2:2] Half Transfer interrupt enableObject *teie; // [3:3] Transfer error interrupt enableObject *dir; // [4:4] Data transfer directionObject *circ; // [5:5] Circular modeObject *pinc; // [6:6] Peripheral increment modeObject *minc; // [7:7] Memory increment modeObject *psize; // [8:9] Peripheral sizeObject *msize; // [10:11] Memory sizeObject *pl; // [12:13] Channel Priority levelObject *mem2mem; // [14:14] Memory to memory mode} ccr5; +// CNDTR5(DMA channel 5 number of data register) bitfields. + struct { +Object *ndt; // [0:15] Number of data to transfer} cndtr5; +// CPAR5(DMA channel 5 peripheral address register) bitfields. + struct { +Object *pa; // [0:31] Peripheral address} cpar5; +// CMAR5(DMA channel 5 memory address register) bitfields. + struct { +Object *ma; // [0:31] Memory address} cmar5; +// CCR6(DMA channel configuration register (DMA_CCR)) bitfields. + struct { +Object *en; // [0:0] Channel enableObject *tcie; // [1:1] Transfer complete interrupt enableObject *htie; // [2:2] Half Transfer interrupt enableObject *teie; // [3:3] Transfer error interrupt enableObject *dir; // [4:4] Data transfer directionObject *circ; // [5:5] Circular modeObject *pinc; // [6:6] Peripheral increment modeObject *minc; // [7:7] Memory increment modeObject *psize; // [8:9] Peripheral sizeObject *msize; // [10:11] Memory sizeObject *pl; // [12:13] Channel Priority levelObject *mem2mem; // [14:14] Memory to memory mode} ccr6; +// CNDTR6(DMA channel 6 number of data register) bitfields. + struct { +Object *ndt; // [0:15] Number of data to transfer} cndtr6; +// CPAR6(DMA channel 6 peripheral address register) bitfields. + struct { +Object *pa; // [0:31] Peripheral address} cpar6; +// CMAR6(DMA channel 6 memory address register) bitfields. + struct { +Object *ma; // [0:31] Memory address} cmar6; +// CCR7(DMA channel configuration register (DMA_CCR)) bitfields. + struct { +Object *en; // [0:0] Channel enableObject *tcie; // [1:1] Transfer complete interrupt enableObject *htie; // [2:2] Half Transfer interrupt enableObject *teie; // [3:3] Transfer error interrupt enableObject *dir; // [4:4] Data transfer directionObject *circ; // [5:5] Circular modeObject *pinc; // [6:6] Peripheral increment modeObject *minc; // [7:7] Memory increment modeObject *psize; // [8:9] Peripheral sizeObject *msize; // [10:11] Memory sizeObject *pl; // [12:13] Channel Priority levelObject *mem2mem; // [14:14] Memory to memory mode} ccr7; +// CNDTR7(DMA channel 7 number of data register) bitfields. + struct { +Object *ndt; // [0:15] Number of data to transfer} cndtr7; +// CPAR7(DMA channel 7 peripheral address register) bitfields. + struct { +Object *pa; // [0:31] Peripheral address} cpar7; +// CMAR7(DMA channel 7 memory address register) bitfields. + struct { +Object *ma; // [0:31] Memory address} cmar7; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/exti.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/exti.c new file mode 100644 index 0000000000..e5f43ff419 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/exti.c @@ -0,0 +1,375 @@ +/* + * STM32- EXTI(External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_exti_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.imr= cm_object_get_child_by_name(obj, "IMR"); +state->u.f0.reg.emr= cm_object_get_child_by_name(obj, "EMR"); +state->u.f0.reg.rtsr= cm_object_get_child_by_name(obj, "RTSR"); +state->u.f0.reg.ftsr= cm_object_get_child_by_name(obj, "FTSR"); +state->u.f0.reg.swier= cm_object_get_child_by_name(obj, "SWIER"); +state->u.f0.reg.pr= cm_object_get_child_by_name(obj, "PR"); +// IMRbitfields. +state->u.f0.fld.imr.mr0= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR0"); +state->u.f0.fld.imr.mr1= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR1"); +state->u.f0.fld.imr.mr2= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR2"); +state->u.f0.fld.imr.mr3= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR3"); +state->u.f0.fld.imr.mr4= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR4"); +state->u.f0.fld.imr.mr5= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR5"); +state->u.f0.fld.imr.mr6= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR6"); +state->u.f0.fld.imr.mr7= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR7"); +state->u.f0.fld.imr.mr8= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR8"); +state->u.f0.fld.imr.mr9= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR9"); +state->u.f0.fld.imr.mr10= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR10"); +state->u.f0.fld.imr.mr11= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR11"); +state->u.f0.fld.imr.mr12= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR12"); +state->u.f0.fld.imr.mr13= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR13"); +state->u.f0.fld.imr.mr14= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR14"); +state->u.f0.fld.imr.mr15= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR15"); +state->u.f0.fld.imr.mr16= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR16"); +state->u.f0.fld.imr.mr17= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR17"); +state->u.f0.fld.imr.mr18= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR18"); +state->u.f0.fld.imr.mr19= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR19"); +state->u.f0.fld.imr.mr20= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR20"); +state->u.f0.fld.imr.mr21= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR21"); +state->u.f0.fld.imr.mr22= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR22"); +state->u.f0.fld.imr.mr23= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR23"); +state->u.f0.fld.imr.mr24= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR24"); +state->u.f0.fld.imr.mr25= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR25"); +state->u.f0.fld.imr.mr26= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR26"); +state->u.f0.fld.imr.mr27= cm_object_get_child_by_name(state->u.f0.reg.imr, "MR27"); +// EMRbitfields. +state->u.f0.fld.emr.mr0= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR0"); +state->u.f0.fld.emr.mr1= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR1"); +state->u.f0.fld.emr.mr2= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR2"); +state->u.f0.fld.emr.mr3= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR3"); +state->u.f0.fld.emr.mr4= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR4"); +state->u.f0.fld.emr.mr5= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR5"); +state->u.f0.fld.emr.mr6= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR6"); +state->u.f0.fld.emr.mr7= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR7"); +state->u.f0.fld.emr.mr8= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR8"); +state->u.f0.fld.emr.mr9= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR9"); +state->u.f0.fld.emr.mr10= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR10"); +state->u.f0.fld.emr.mr11= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR11"); +state->u.f0.fld.emr.mr12= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR12"); +state->u.f0.fld.emr.mr13= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR13"); +state->u.f0.fld.emr.mr14= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR14"); +state->u.f0.fld.emr.mr15= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR15"); +state->u.f0.fld.emr.mr16= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR16"); +state->u.f0.fld.emr.mr17= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR17"); +state->u.f0.fld.emr.mr18= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR18"); +state->u.f0.fld.emr.mr19= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR19"); +state->u.f0.fld.emr.mr20= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR20"); +state->u.f0.fld.emr.mr21= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR21"); +state->u.f0.fld.emr.mr22= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR22"); +state->u.f0.fld.emr.mr23= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR23"); +state->u.f0.fld.emr.mr24= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR24"); +state->u.f0.fld.emr.mr25= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR25"); +state->u.f0.fld.emr.mr26= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR26"); +state->u.f0.fld.emr.mr27= cm_object_get_child_by_name(state->u.f0.reg.emr, "MR27"); +// RTSRbitfields. +state->u.f0.fld.rtsr.tr0= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR0"); +state->u.f0.fld.rtsr.tr1= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR1"); +state->u.f0.fld.rtsr.tr2= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR2"); +state->u.f0.fld.rtsr.tr3= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR3"); +state->u.f0.fld.rtsr.tr4= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR4"); +state->u.f0.fld.rtsr.tr5= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR5"); +state->u.f0.fld.rtsr.tr6= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR6"); +state->u.f0.fld.rtsr.tr7= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR7"); +state->u.f0.fld.rtsr.tr8= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR8"); +state->u.f0.fld.rtsr.tr9= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR9"); +state->u.f0.fld.rtsr.tr10= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR10"); +state->u.f0.fld.rtsr.tr11= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR11"); +state->u.f0.fld.rtsr.tr12= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR12"); +state->u.f0.fld.rtsr.tr13= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR13"); +state->u.f0.fld.rtsr.tr14= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR14"); +state->u.f0.fld.rtsr.tr15= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR15"); +state->u.f0.fld.rtsr.tr16= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR16"); +state->u.f0.fld.rtsr.tr17= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR17"); +state->u.f0.fld.rtsr.tr19= cm_object_get_child_by_name(state->u.f0.reg.rtsr, "TR19"); +// FTSRbitfields. +state->u.f0.fld.ftsr.tr0= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR0"); +state->u.f0.fld.ftsr.tr1= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR1"); +state->u.f0.fld.ftsr.tr2= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR2"); +state->u.f0.fld.ftsr.tr3= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR3"); +state->u.f0.fld.ftsr.tr4= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR4"); +state->u.f0.fld.ftsr.tr5= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR5"); +state->u.f0.fld.ftsr.tr6= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR6"); +state->u.f0.fld.ftsr.tr7= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR7"); +state->u.f0.fld.ftsr.tr8= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR8"); +state->u.f0.fld.ftsr.tr9= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR9"); +state->u.f0.fld.ftsr.tr10= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR10"); +state->u.f0.fld.ftsr.tr11= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR11"); +state->u.f0.fld.ftsr.tr12= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR12"); +state->u.f0.fld.ftsr.tr13= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR13"); +state->u.f0.fld.ftsr.tr14= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR14"); +state->u.f0.fld.ftsr.tr15= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR15"); +state->u.f0.fld.ftsr.tr16= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR16"); +state->u.f0.fld.ftsr.tr17= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR17"); +state->u.f0.fld.ftsr.tr19= cm_object_get_child_by_name(state->u.f0.reg.ftsr, "TR19"); +// SWIERbitfields. +state->u.f0.fld.swier.swier0= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER0"); +state->u.f0.fld.swier.swier1= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER1"); +state->u.f0.fld.swier.swier2= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER2"); +state->u.f0.fld.swier.swier3= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER3"); +state->u.f0.fld.swier.swier4= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER4"); +state->u.f0.fld.swier.swier5= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER5"); +state->u.f0.fld.swier.swier6= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER6"); +state->u.f0.fld.swier.swier7= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER7"); +state->u.f0.fld.swier.swier8= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER8"); +state->u.f0.fld.swier.swier9= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER9"); +state->u.f0.fld.swier.swier10= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER10"); +state->u.f0.fld.swier.swier11= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER11"); +state->u.f0.fld.swier.swier12= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER12"); +state->u.f0.fld.swier.swier13= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER13"); +state->u.f0.fld.swier.swier14= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER14"); +state->u.f0.fld.swier.swier15= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER15"); +state->u.f0.fld.swier.swier16= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER16"); +state->u.f0.fld.swier.swier17= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER17"); +state->u.f0.fld.swier.swier19= cm_object_get_child_by_name(state->u.f0.reg.swier, "SWIER19"); +// PRbitfields. +state->u.f0.fld.pr.pr0= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR0"); +state->u.f0.fld.pr.pr1= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR1"); +state->u.f0.fld.pr.pr2= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR2"); +state->u.f0.fld.pr.pr3= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR3"); +state->u.f0.fld.pr.pr4= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR4"); +state->u.f0.fld.pr.pr5= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR5"); +state->u.f0.fld.pr.pr6= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR6"); +state->u.f0.fld.pr.pr7= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR7"); +state->u.f0.fld.pr.pr8= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR8"); +state->u.f0.fld.pr.pr9= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR9"); +state->u.f0.fld.pr.pr10= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR10"); +state->u.f0.fld.pr.pr11= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR11"); +state->u.f0.fld.pr.pr12= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR12"); +state->u.f0.fld.pr.pr13= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR13"); +state->u.f0.fld.pr.pr14= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR14"); +state->u.f0.fld.pr.pr15= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR15"); +state->u.f0.fld.pr.pr16= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR16"); +state->u.f0.fld.pr.pr17= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR17"); +state->u.f0.fld.pr.pr19= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR19"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_exti_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_exti_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_exti_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_exti_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_exti_is_enabled(Object *obj) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_exti_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_exti_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_EXTI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32EXTIState *state = STM32_EXTI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "EXTI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_exti_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_exti_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_exti_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_exti_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_exti_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/EXTIEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_exti_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_EXTI); +} + +static void stm32_exti_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_exti_reset_callback; + dc->realize = stm32_exti_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_exti_is_enabled; +} + +static const TypeInfo stm32_exti_type_info = { + .name = TYPE_STM32_EXTI, + .parent = TYPE_STM32_EXTI_PARENT, + .instance_init = stm32_exti_instance_init_callback, + .instance_size = sizeof(STM32EXTIState), + .class_init = stm32_exti_class_init_callback, + .class_size = sizeof(STM32EXTIClass) }; + +static void stm32_exti_register_types(void) +{ + type_register_static(&stm32_exti_type_info); +} + +type_init(stm32_exti_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/exti.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/exti.h new file mode 100644 index 0000000000..aa623be591 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/exti.h @@ -0,0 +1,121 @@ +/* + * STM32- EXTI(External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_EXTI_H_ +#define STM32_EXTI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_EXTIDEVICE_PATH_STM32"EXTI" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_EXTITYPE_STM32_PREFIX "exti" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_EXTI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32EXTIParentClass; +typedef PeripheralState STM32EXTIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_EXTI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32EXTIClass, (obj), TYPE_STM32_EXTI) +#define STM32_EXTI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32EXTIClass, (klass), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentClass parent_class; + // public: + + // None, so far. +} STM32EXTIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_EXTI_STATE(obj) \ + OBJECT_CHECK(STM32EXTIState, (obj), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0EXTI(External interrupt/event controller) registers. + struct { +Object *imr; // 0x0(Interrupt mask register (EXTI_IMR)) +Object *emr; // 0x4(Event mask register (EXTI_EMR)) +Object *rtsr; // 0x8(Rising Trigger selection register (EXTI_RTSR)) +Object *ftsr; // 0xC(Falling Trigger selection register (EXTI_FTSR)) +Object *swier; // 0x10(Software interrupt event register (EXTI_SWIER)) +Object *pr; // 0x14(Pending register (EXTI_PR)) +} reg; + + struct { +// IMR(Interrupt mask register (EXTI_IMR)) bitfields. + struct { +Object *mr0; // [0:0] Interrupt Mask on line 0Object *mr1; // [1:1] Interrupt Mask on line 1Object *mr2; // [2:2] Interrupt Mask on line 2Object *mr3; // [3:3] Interrupt Mask on line 3Object *mr4; // [4:4] Interrupt Mask on line 4Object *mr5; // [5:5] Interrupt Mask on line 5Object *mr6; // [6:6] Interrupt Mask on line 6Object *mr7; // [7:7] Interrupt Mask on line 7Object *mr8; // [8:8] Interrupt Mask on line 8Object *mr9; // [9:9] Interrupt Mask on line 9Object *mr10; // [10:10] Interrupt Mask on line 10Object *mr11; // [11:11] Interrupt Mask on line 11Object *mr12; // [12:12] Interrupt Mask on line 12Object *mr13; // [13:13] Interrupt Mask on line 13Object *mr14; // [14:14] Interrupt Mask on line 14Object *mr15; // [15:15] Interrupt Mask on line 15Object *mr16; // [16:16] Interrupt Mask on line 16Object *mr17; // [17:17] Interrupt Mask on line 17Object *mr18; // [18:18] Interrupt Mask on line 18Object *mr19; // [19:19] Interrupt Mask on line 19Object *mr20; // [20:20] Interrupt Mask on line 20Object *mr21; // [21:21] Interrupt Mask on line 21Object *mr22; // [22:22] Interrupt Mask on line 22Object *mr23; // [23:23] Interrupt Mask on line 23Object *mr24; // [24:24] Interrupt Mask on line 24Object *mr25; // [25:25] Interrupt Mask on line 25Object *mr26; // [26:26] Interrupt Mask on line 26Object *mr27; // [27:27] Interrupt Mask on line 27} imr; +// EMR(Event mask register (EXTI_EMR)) bitfields. + struct { +Object *mr0; // [0:0] Event Mask on line 0Object *mr1; // [1:1] Event Mask on line 1Object *mr2; // [2:2] Event Mask on line 2Object *mr3; // [3:3] Event Mask on line 3Object *mr4; // [4:4] Event Mask on line 4Object *mr5; // [5:5] Event Mask on line 5Object *mr6; // [6:6] Event Mask on line 6Object *mr7; // [7:7] Event Mask on line 7Object *mr8; // [8:8] Event Mask on line 8Object *mr9; // [9:9] Event Mask on line 9Object *mr10; // [10:10] Event Mask on line 10Object *mr11; // [11:11] Event Mask on line 11Object *mr12; // [12:12] Event Mask on line 12Object *mr13; // [13:13] Event Mask on line 13Object *mr14; // [14:14] Event Mask on line 14Object *mr15; // [15:15] Event Mask on line 15Object *mr16; // [16:16] Event Mask on line 16Object *mr17; // [17:17] Event Mask on line 17Object *mr18; // [18:18] Event Mask on line 18Object *mr19; // [19:19] Event Mask on line 19Object *mr20; // [20:20] Event Mask on line 20Object *mr21; // [21:21] Event Mask on line 21Object *mr22; // [22:22] Event Mask on line 22Object *mr23; // [23:23] Event Mask on line 23Object *mr24; // [24:24] Event Mask on line 24Object *mr25; // [25:25] Event Mask on line 25Object *mr26; // [26:26] Event Mask on line 26Object *mr27; // [27:27] Event Mask on line 27} emr; +// RTSR(Rising Trigger selection register (EXTI_RTSR)) bitfields. + struct { +Object *tr0; // [0:0] Rising trigger event configuration of line 0Object *tr1; // [1:1] Rising trigger event configuration of line 1Object *tr2; // [2:2] Rising trigger event configuration of line 2Object *tr3; // [3:3] Rising trigger event configuration of line 3Object *tr4; // [4:4] Rising trigger event configuration of line 4Object *tr5; // [5:5] Rising trigger event configuration of line 5Object *tr6; // [6:6] Rising trigger event configuration of line 6Object *tr7; // [7:7] Rising trigger event configuration of line 7Object *tr8; // [8:8] Rising trigger event configuration of line 8Object *tr9; // [9:9] Rising trigger event configuration of line 9Object *tr10; // [10:10] Rising trigger event configuration of line 10Object *tr11; // [11:11] Rising trigger event configuration of line 11Object *tr12; // [12:12] Rising trigger event configuration of line 12Object *tr13; // [13:13] Rising trigger event configuration of line 13Object *tr14; // [14:14] Rising trigger event configuration of line 14Object *tr15; // [15:15] Rising trigger event configuration of line 15Object *tr16; // [16:16] Rising trigger event configuration of line 16Object *tr17; // [17:17] Rising trigger event configuration of line 17Object *tr19; // [19:19] Rising trigger event configuration of line 19} rtsr; +// FTSR(Falling Trigger selection register (EXTI_FTSR)) bitfields. + struct { +Object *tr0; // [0:0] Falling trigger event configuration of line 0Object *tr1; // [1:1] Falling trigger event configuration of line 1Object *tr2; // [2:2] Falling trigger event configuration of line 2Object *tr3; // [3:3] Falling trigger event configuration of line 3Object *tr4; // [4:4] Falling trigger event configuration of line 4Object *tr5; // [5:5] Falling trigger event configuration of line 5Object *tr6; // [6:6] Falling trigger event configuration of line 6Object *tr7; // [7:7] Falling trigger event configuration of line 7Object *tr8; // [8:8] Falling trigger event configuration of line 8Object *tr9; // [9:9] Falling trigger event configuration of line 9Object *tr10; // [10:10] Falling trigger event configuration of line 10Object *tr11; // [11:11] Falling trigger event configuration of line 11Object *tr12; // [12:12] Falling trigger event configuration of line 12Object *tr13; // [13:13] Falling trigger event configuration of line 13Object *tr14; // [14:14] Falling trigger event configuration of line 14Object *tr15; // [15:15] Falling trigger event configuration of line 15Object *tr16; // [16:16] Falling trigger event configuration of line 16Object *tr17; // [17:17] Falling trigger event configuration of line 17Object *tr19; // [19:19] Falling trigger event configuration of line 19} ftsr; +// SWIER(Software interrupt event register (EXTI_SWIER)) bitfields. + struct { +Object *swier0; // [0:0] Software Interrupt on line 0Object *swier1; // [1:1] Software Interrupt on line 1Object *swier2; // [2:2] Software Interrupt on line 2Object *swier3; // [3:3] Software Interrupt on line 3Object *swier4; // [4:4] Software Interrupt on line 4Object *swier5; // [5:5] Software Interrupt on line 5Object *swier6; // [6:6] Software Interrupt on line 6Object *swier7; // [7:7] Software Interrupt on line 7Object *swier8; // [8:8] Software Interrupt on line 8Object *swier9; // [9:9] Software Interrupt on line 9Object *swier10; // [10:10] Software Interrupt on line 10Object *swier11; // [11:11] Software Interrupt on line 11Object *swier12; // [12:12] Software Interrupt on line 12Object *swier13; // [13:13] Software Interrupt on line 13Object *swier14; // [14:14] Software Interrupt on line 14Object *swier15; // [15:15] Software Interrupt on line 15Object *swier16; // [16:16] Software Interrupt on line 16Object *swier17; // [17:17] Software Interrupt on line 17Object *swier19; // [19:19] Software Interrupt on line 19} swier; +// PR(Pending register (EXTI_PR)) bitfields. + struct { +Object *pr0; // [0:0] Pending bit 0Object *pr1; // [1:1] Pending bit 1Object *pr2; // [2:2] Pending bit 2Object *pr3; // [3:3] Pending bit 3Object *pr4; // [4:4] Pending bit 4Object *pr5; // [5:5] Pending bit 5Object *pr6; // [6:6] Pending bit 6Object *pr7; // [7:7] Pending bit 7Object *pr8; // [8:8] Pending bit 8Object *pr9; // [9:9] Pending bit 9Object *pr10; // [10:10] Pending bit 10Object *pr11; // [11:11] Pending bit 11Object *pr12; // [12:12] Pending bit 12Object *pr13; // [13:13] Pending bit 13Object *pr14; // [14:14] Pending bit 14Object *pr15; // [15:15] Pending bit 15Object *pr16; // [16:16] Pending bit 16Object *pr17; // [17:17] Pending bit 17Object *pr19; // [19:19] Pending bit 19} pr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32EXTIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_EXTI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/flash.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/flash.c new file mode 100644 index 0000000000..ffa7eaab7e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/flash.c @@ -0,0 +1,279 @@ +/* + * STM32- Flash(Flash) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_flash_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FlashState *state = STM32_Flash_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.acr= cm_object_get_child_by_name(obj, "ACR"); +state->u.f0.reg.keyr= cm_object_get_child_by_name(obj, "KEYR"); +state->u.f0.reg.optkeyr= cm_object_get_child_by_name(obj, "OPTKEYR"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.ar= cm_object_get_child_by_name(obj, "AR"); +state->u.f0.reg.obr= cm_object_get_child_by_name(obj, "OBR"); +state->u.f0.reg.wrpr= cm_object_get_child_by_name(obj, "WRPR"); +// ACRbitfields. +state->u.f0.fld.acr.latency= cm_object_get_child_by_name(state->u.f0.reg.acr, "LATENCY"); +state->u.f0.fld.acr.prftbe= cm_object_get_child_by_name(state->u.f0.reg.acr, "PRFTBE"); +state->u.f0.fld.acr.prftbs= cm_object_get_child_by_name(state->u.f0.reg.acr, "PRFTBS"); +// KEYRbitfields. +state->u.f0.fld.keyr.fkeyr= cm_object_get_child_by_name(state->u.f0.reg.keyr, "FKEYR"); +// OPTKEYRbitfields. +state->u.f0.fld.optkeyr.optkeyr= cm_object_get_child_by_name(state->u.f0.reg.optkeyr, "OPTKEYR"); +// SRbitfields. +state->u.f0.fld.sr.bsy= cm_object_get_child_by_name(state->u.f0.reg.sr, "BSY"); +state->u.f0.fld.sr.pgerr= cm_object_get_child_by_name(state->u.f0.reg.sr, "PGERR"); +state->u.f0.fld.sr.wrprt= cm_object_get_child_by_name(state->u.f0.reg.sr, "WRPRT"); +state->u.f0.fld.sr.eop= cm_object_get_child_by_name(state->u.f0.reg.sr, "EOP"); +// CRbitfields. +state->u.f0.fld.cr.pg= cm_object_get_child_by_name(state->u.f0.reg.cr, "PG"); +state->u.f0.fld.cr.per= cm_object_get_child_by_name(state->u.f0.reg.cr, "PER"); +state->u.f0.fld.cr.mer= cm_object_get_child_by_name(state->u.f0.reg.cr, "MER"); +state->u.f0.fld.cr.optpg= cm_object_get_child_by_name(state->u.f0.reg.cr, "OPTPG"); +state->u.f0.fld.cr.opter= cm_object_get_child_by_name(state->u.f0.reg.cr, "OPTER"); +state->u.f0.fld.cr.strt= cm_object_get_child_by_name(state->u.f0.reg.cr, "STRT"); +state->u.f0.fld.cr.lock= cm_object_get_child_by_name(state->u.f0.reg.cr, "LOCK"); +state->u.f0.fld.cr.optwre= cm_object_get_child_by_name(state->u.f0.reg.cr, "OPTWRE"); +state->u.f0.fld.cr.errie= cm_object_get_child_by_name(state->u.f0.reg.cr, "ERRIE"); +state->u.f0.fld.cr.eopie= cm_object_get_child_by_name(state->u.f0.reg.cr, "EOPIE"); +state->u.f0.fld.cr.force_optload= cm_object_get_child_by_name(state->u.f0.reg.cr, "FORCE_OPTLOAD"); +// ARbitfields. +state->u.f0.fld.ar.far_= cm_object_get_child_by_name(state->u.f0.reg.ar, "FAR"); +// OBRbitfields. +state->u.f0.fld.obr.opterr= cm_object_get_child_by_name(state->u.f0.reg.obr, "OPTERR"); +state->u.f0.fld.obr.level1_prot= cm_object_get_child_by_name(state->u.f0.reg.obr, "LEVEL1_PROT"); +state->u.f0.fld.obr.level2_prot= cm_object_get_child_by_name(state->u.f0.reg.obr, "LEVEL2_PROT"); +state->u.f0.fld.obr.wdg_sw= cm_object_get_child_by_name(state->u.f0.reg.obr, "WDG_SW"); +state->u.f0.fld.obr.nrst_stop= cm_object_get_child_by_name(state->u.f0.reg.obr, "nRST_STOP"); +state->u.f0.fld.obr.nrst_stdby= cm_object_get_child_by_name(state->u.f0.reg.obr, "nRST_STDBY"); +state->u.f0.fld.obr.boot1= cm_object_get_child_by_name(state->u.f0.reg.obr, "BOOT1"); +state->u.f0.fld.obr.vdda_monitor= cm_object_get_child_by_name(state->u.f0.reg.obr, "VDDA_MONITOR"); +state->u.f0.fld.obr.data0= cm_object_get_child_by_name(state->u.f0.reg.obr, "Data0"); +state->u.f0.fld.obr.data1= cm_object_get_child_by_name(state->u.f0.reg.obr, "Data1"); +// WRPRbitfields. +state->u.f0.fld.wrpr.wrp= cm_object_get_child_by_name(state->u.f0.reg.wrpr, "WRP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_flash_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_flash_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_flash_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_flash_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FlashState *state = STM32_Flash_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_flash_is_enabled(Object *obj) +{ + STM32FlashState *state = STM32_Flash_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_flash_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FlashState *state = STM32_Flash_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_flash_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Flash)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FlashState *state = STM32_Flash_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Flash"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_flash_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_flash_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_flash_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_flash_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_flash_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FlashEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_flash_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Flash); +} + +static void stm32_flash_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_flash_reset_callback; + dc->realize = stm32_flash_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_flash_is_enabled; +} + +static const TypeInfo stm32_flash_type_info = { + .name = TYPE_STM32_Flash, + .parent = TYPE_STM32_Flash_PARENT, + .instance_init = stm32_flash_instance_init_callback, + .instance_size = sizeof(STM32FlashState), + .class_init = stm32_flash_class_init_callback, + .class_size = sizeof(STM32FlashClass) }; + +static void stm32_flash_register_types(void) +{ + type_register_static(&stm32_flash_type_info); +} + +type_init(stm32_flash_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/flash.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/flash.h new file mode 100644 index 0000000000..672450cdc1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/flash.h @@ -0,0 +1,129 @@ +/* + * STM32- Flash(Flash) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Flash_H_ +#define STM32_Flash_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FlashDEVICE_PATH_STM32"Flash" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FlashTYPE_STM32_PREFIX "flash" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Flash_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FlashParentClass; +typedef PeripheralState STM32FlashParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Flash_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FlashClass, (obj), TYPE_STM32_Flash) +#define STM32_Flash_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FlashClass, (klass), TYPE_STM32_Flash) + +typedef struct { + // private: + STM32FlashParentClass parent_class; + // public: + + // None, so far. +} STM32FlashClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Flash_STATE(obj) \ + OBJECT_CHECK(STM32FlashState, (obj), TYPE_STM32_Flash) + +typedef struct { + // private: + STM32FlashParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0Flash(Flash) registers. + struct { +Object *acr; // 0x0(Flash access control register) +Object *keyr; // 0x4(Flash key register) +Object *optkeyr; // 0x8(Flash option key register) +Object *sr; // 0xC(Flash status register) +Object *cr; // 0x10(Flash control register) +Object *ar; // 0x14(Flash address register) +Object *obr; // 0x1C(Option byte register) +Object *wrpr; // 0x20(Write protection register) +} reg; + + struct { +// ACR(Flash access control register) bitfields. + struct { +Object *latency; // [0:2] LATENCYObject *prftbe; // [4:4] PRFTBEObject *prftbs; // [5:5] PRFTBS} acr; +// KEYR(Flash key register) bitfields. + struct { +Object *fkeyr; // [0:31] Flash Key} keyr; +// OPTKEYR(Flash option key register) bitfields. + struct { +Object *optkeyr; // [0:31] Option byte key} optkeyr; +// SR(Flash status register) bitfields. + struct { +Object *bsy; // [0:0] BusyObject *pgerr; // [2:2] Programming errorObject *wrprt; // [4:4] Write protection errorObject *eop; // [5:5] End of operation} sr; +// CR(Flash control register) bitfields. + struct { +Object *pg; // [0:0] ProgrammingObject *per; // [1:1] Page eraseObject *mer; // [2:2] Mass eraseObject *optpg; // [4:4] Option byte programmingObject *opter; // [5:5] Option byte eraseObject *strt; // [6:6] StartObject *lock; // [7:7] LockObject *optwre; // [9:9] Option bytes write enableObject *errie; // [10:10] Error interrupt enableObject *eopie; // [12:12] End of operation interrupt enableObject *force_optload; // [13:13] Force option byte loading} cr; +// AR(Flash address register) bitfields. + struct { +Object *far_; // [0:31] Flash address} ar; +// OBR(Option byte register) bitfields. + struct { +Object *opterr; // [0:0] Option byte errorObject *level1_prot; // [1:1] Level 1 protection statusObject *level2_prot; // [2:2] Level 2 protection statusObject *wdg_sw; // [8:8] WDG_SWObject *nrst_stop; // [9:9] NRST_STOPObject *nrst_stdby; // [10:10] NRST_STDBYObject *boot1; // [12:12] BOOT1Object *vdda_monitor; // [13:13] VDDA_MONITORObject *data0; // [16:23] Data0Object *data1; // [24:31] Data1} obr; +// WRPR(Write protection register) bitfields. + struct { +Object *wrp; // [0:31] Write protect} wrpr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FlashState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Flash_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/gpioa.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpioa.c new file mode 100644 index 0000000000..b5e95269d2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpioa.c @@ -0,0 +1,434 @@ +/* + * STM32- GPIO(General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.moder= cm_object_get_child_by_name(obj, "MODER"); +state->u.f0.reg.otyper= cm_object_get_child_by_name(obj, "OTYPER"); +state->u.f0.reg.ospeedr= cm_object_get_child_by_name(obj, "OSPEEDR"); +state->u.f0.reg.pupdr= cm_object_get_child_by_name(obj, "PUPDR"); +state->u.f0.reg.idr= cm_object_get_child_by_name(obj, "IDR"); +state->u.f0.reg.odr= cm_object_get_child_by_name(obj, "ODR"); +state->u.f0.reg.bsrr= cm_object_get_child_by_name(obj, "BSRR"); +state->u.f0.reg.lckr= cm_object_get_child_by_name(obj, "LCKR"); +state->u.f0.reg.afrl= cm_object_get_child_by_name(obj, "AFRL"); +state->u.f0.reg.afrh= cm_object_get_child_by_name(obj, "AFRH"); +state->u.f0.reg.brr= cm_object_get_child_by_name(obj, "BRR"); +// MODERbitfields. +state->u.f0.fld.moder.moder0= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER0"); +state->u.f0.fld.moder.moder1= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER1"); +state->u.f0.fld.moder.moder2= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER2"); +state->u.f0.fld.moder.moder3= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER3"); +state->u.f0.fld.moder.moder4= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER4"); +state->u.f0.fld.moder.moder5= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER5"); +state->u.f0.fld.moder.moder6= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER6"); +state->u.f0.fld.moder.moder7= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER7"); +state->u.f0.fld.moder.moder8= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER8"); +state->u.f0.fld.moder.moder9= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER9"); +state->u.f0.fld.moder.moder10= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER10"); +state->u.f0.fld.moder.moder11= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER11"); +state->u.f0.fld.moder.moder12= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER12"); +state->u.f0.fld.moder.moder13= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER13"); +state->u.f0.fld.moder.moder14= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER14"); +state->u.f0.fld.moder.moder15= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER15"); +// OTYPERbitfields. +state->u.f0.fld.otyper.ot0= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT0"); +state->u.f0.fld.otyper.ot1= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT1"); +state->u.f0.fld.otyper.ot2= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT2"); +state->u.f0.fld.otyper.ot3= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT3"); +state->u.f0.fld.otyper.ot4= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT4"); +state->u.f0.fld.otyper.ot5= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT5"); +state->u.f0.fld.otyper.ot6= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT6"); +state->u.f0.fld.otyper.ot7= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT7"); +state->u.f0.fld.otyper.ot8= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT8"); +state->u.f0.fld.otyper.ot9= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT9"); +state->u.f0.fld.otyper.ot10= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT10"); +state->u.f0.fld.otyper.ot11= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT11"); +state->u.f0.fld.otyper.ot12= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT12"); +state->u.f0.fld.otyper.ot13= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT13"); +state->u.f0.fld.otyper.ot14= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT14"); +state->u.f0.fld.otyper.ot15= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT15"); +// OSPEEDRbitfields. +state->u.f0.fld.ospeedr.ospeedr0= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR0"); +state->u.f0.fld.ospeedr.ospeedr1= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR1"); +state->u.f0.fld.ospeedr.ospeedr2= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR2"); +state->u.f0.fld.ospeedr.ospeedr3= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR3"); +state->u.f0.fld.ospeedr.ospeedr4= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR4"); +state->u.f0.fld.ospeedr.ospeedr5= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR5"); +state->u.f0.fld.ospeedr.ospeedr6= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR6"); +state->u.f0.fld.ospeedr.ospeedr7= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR7"); +state->u.f0.fld.ospeedr.ospeedr8= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR8"); +state->u.f0.fld.ospeedr.ospeedr9= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR9"); +state->u.f0.fld.ospeedr.ospeedr10= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR10"); +state->u.f0.fld.ospeedr.ospeedr11= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR11"); +state->u.f0.fld.ospeedr.ospeedr12= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR12"); +state->u.f0.fld.ospeedr.ospeedr13= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR13"); +state->u.f0.fld.ospeedr.ospeedr14= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR14"); +state->u.f0.fld.ospeedr.ospeedr15= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR15"); +// PUPDRbitfields. +state->u.f0.fld.pupdr.pupdr0= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR0"); +state->u.f0.fld.pupdr.pupdr1= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR1"); +state->u.f0.fld.pupdr.pupdr2= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR2"); +state->u.f0.fld.pupdr.pupdr3= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR3"); +state->u.f0.fld.pupdr.pupdr4= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR4"); +state->u.f0.fld.pupdr.pupdr5= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR5"); +state->u.f0.fld.pupdr.pupdr6= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR6"); +state->u.f0.fld.pupdr.pupdr7= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR7"); +state->u.f0.fld.pupdr.pupdr8= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR8"); +state->u.f0.fld.pupdr.pupdr9= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR9"); +state->u.f0.fld.pupdr.pupdr10= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR10"); +state->u.f0.fld.pupdr.pupdr11= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR11"); +state->u.f0.fld.pupdr.pupdr12= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR12"); +state->u.f0.fld.pupdr.pupdr13= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR13"); +state->u.f0.fld.pupdr.pupdr14= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR14"); +state->u.f0.fld.pupdr.pupdr15= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR15"); +// IDRbitfields. +state->u.f0.fld.idr.idr0= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR0"); +state->u.f0.fld.idr.idr1= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR1"); +state->u.f0.fld.idr.idr2= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR2"); +state->u.f0.fld.idr.idr3= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR3"); +state->u.f0.fld.idr.idr4= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR4"); +state->u.f0.fld.idr.idr5= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR5"); +state->u.f0.fld.idr.idr6= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR6"); +state->u.f0.fld.idr.idr7= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR7"); +state->u.f0.fld.idr.idr8= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR8"); +state->u.f0.fld.idr.idr9= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR9"); +state->u.f0.fld.idr.idr10= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR10"); +state->u.f0.fld.idr.idr11= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR11"); +state->u.f0.fld.idr.idr12= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR12"); +state->u.f0.fld.idr.idr13= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR13"); +state->u.f0.fld.idr.idr14= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR14"); +state->u.f0.fld.idr.idr15= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR15"); +// ODRbitfields. +state->u.f0.fld.odr.odr0= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR0"); +state->u.f0.fld.odr.odr1= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR1"); +state->u.f0.fld.odr.odr2= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR2"); +state->u.f0.fld.odr.odr3= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR3"); +state->u.f0.fld.odr.odr4= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR4"); +state->u.f0.fld.odr.odr5= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR5"); +state->u.f0.fld.odr.odr6= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR6"); +state->u.f0.fld.odr.odr7= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR7"); +state->u.f0.fld.odr.odr8= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR8"); +state->u.f0.fld.odr.odr9= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR9"); +state->u.f0.fld.odr.odr10= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR10"); +state->u.f0.fld.odr.odr11= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR11"); +state->u.f0.fld.odr.odr12= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR12"); +state->u.f0.fld.odr.odr13= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR13"); +state->u.f0.fld.odr.odr14= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR14"); +state->u.f0.fld.odr.odr15= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR15"); +// BSRRbitfields. +state->u.f0.fld.bsrr.bs0= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS0"); +state->u.f0.fld.bsrr.bs1= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS1"); +state->u.f0.fld.bsrr.bs2= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS2"); +state->u.f0.fld.bsrr.bs3= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS3"); +state->u.f0.fld.bsrr.bs4= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS4"); +state->u.f0.fld.bsrr.bs5= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS5"); +state->u.f0.fld.bsrr.bs6= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS6"); +state->u.f0.fld.bsrr.bs7= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS7"); +state->u.f0.fld.bsrr.bs8= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS8"); +state->u.f0.fld.bsrr.bs9= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS9"); +state->u.f0.fld.bsrr.bs10= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS10"); +state->u.f0.fld.bsrr.bs11= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS11"); +state->u.f0.fld.bsrr.bs12= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS12"); +state->u.f0.fld.bsrr.bs13= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS13"); +state->u.f0.fld.bsrr.bs14= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS14"); +state->u.f0.fld.bsrr.bs15= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS15"); +state->u.f0.fld.bsrr.br0= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR0"); +state->u.f0.fld.bsrr.br1= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR1"); +state->u.f0.fld.bsrr.br2= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR2"); +state->u.f0.fld.bsrr.br3= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR3"); +state->u.f0.fld.bsrr.br4= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR4"); +state->u.f0.fld.bsrr.br5= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR5"); +state->u.f0.fld.bsrr.br6= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR6"); +state->u.f0.fld.bsrr.br7= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR7"); +state->u.f0.fld.bsrr.br8= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR8"); +state->u.f0.fld.bsrr.br9= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR9"); +state->u.f0.fld.bsrr.br10= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR10"); +state->u.f0.fld.bsrr.br11= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR11"); +state->u.f0.fld.bsrr.br12= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR12"); +state->u.f0.fld.bsrr.br13= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR13"); +state->u.f0.fld.bsrr.br14= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR14"); +state->u.f0.fld.bsrr.br15= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR15"); +// LCKRbitfields. +state->u.f0.fld.lckr.lck0= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK0"); +state->u.f0.fld.lckr.lck1= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK1"); +state->u.f0.fld.lckr.lck2= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK2"); +state->u.f0.fld.lckr.lck3= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK3"); +state->u.f0.fld.lckr.lck4= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK4"); +state->u.f0.fld.lckr.lck5= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK5"); +state->u.f0.fld.lckr.lck6= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK6"); +state->u.f0.fld.lckr.lck7= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK7"); +state->u.f0.fld.lckr.lck8= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK8"); +state->u.f0.fld.lckr.lck9= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK9"); +state->u.f0.fld.lckr.lck10= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK10"); +state->u.f0.fld.lckr.lck11= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK11"); +state->u.f0.fld.lckr.lck12= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK12"); +state->u.f0.fld.lckr.lck13= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK13"); +state->u.f0.fld.lckr.lck14= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK14"); +state->u.f0.fld.lckr.lck15= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK15"); +state->u.f0.fld.lckr.lckk= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCKK"); +// AFRLbitfields. +state->u.f0.fld.afrl.afrl0= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL0"); +state->u.f0.fld.afrl.afrl1= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL1"); +state->u.f0.fld.afrl.afrl2= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL2"); +state->u.f0.fld.afrl.afrl3= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL3"); +state->u.f0.fld.afrl.afrl4= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL4"); +state->u.f0.fld.afrl.afrl5= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL5"); +state->u.f0.fld.afrl.afrl6= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL6"); +state->u.f0.fld.afrl.afrl7= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL7"); +// AFRHbitfields. +state->u.f0.fld.afrh.afrh8= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH8"); +state->u.f0.fld.afrh.afrh9= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH9"); +state->u.f0.fld.afrh.afrh10= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH10"); +state->u.f0.fld.afrh.afrh11= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH11"); +state->u.f0.fld.afrh.afrh12= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH12"); +state->u.f0.fld.afrh.afrh13= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH13"); +state->u.f0.fld.afrh.afrh14= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH14"); +state->u.f0.fld.afrh.afrh15= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH15"); +// BRRbitfields. +state->u.f0.fld.brr.br0= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR0"); +state->u.f0.fld.brr.br1= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR1"); +state->u.f0.fld.brr.br2= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR2"); +state->u.f0.fld.brr.br3= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR3"); +state->u.f0.fld.brr.br4= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR4"); +state->u.f0.fld.brr.br5= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR5"); +state->u.f0.fld.brr.br6= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR6"); +state->u.f0.fld.brr.br7= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR7"); +state->u.f0.fld.brr.br8= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR8"); +state->u.f0.fld.brr.br9= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR9"); +state->u.f0.fld.brr.br10= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR10"); +state->u.f0.fld.brr.br11= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR11"); +state->u.f0.fld.brr.br12= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR12"); +state->u.f0.fld.brr.br13= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR13"); +state->u.f0.fld.brr.br14= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR14"); +state->u.f0.fld.brr.br15= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + +cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/gpioa.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpioa.h new file mode 100644 index 0000000000..6a4f23d14c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpioa.h @@ -0,0 +1,156 @@ +/* + * STM32- GPIO(General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIODEVICE_PATH_STM32"GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. +STM32_PORT_GPIOA, +STM32_PORT_GPIOB, +STM32_PORT_GPIOC, +STM32_PORT_GPIOD, +STM32_PORT_GPIOE, +STM32_PORT_GPIOF, +STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIOTYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +// Remove it if there is only one port + stm32_gpio_index_t port_index; +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0GPIO(General-purpose I/Os) registers. + struct { +Object *moder; // 0x0(GPIO port mode register) +Object *otyper; // 0x4(GPIO port output type register) +Object *ospeedr; // 0x8(GPIO port output speed register) +Object *pupdr; // 0xC(GPIO port pull-up/pull-down register) +Object *idr; // 0x10(GPIO port input data register) +Object *odr; // 0x14(GPIO port output data register) +Object *bsrr; // 0x18(GPIO port bit set/reset register) +Object *lckr; // 0x1C(GPIO port configuration lock register) +Object *afrl; // 0x20(GPIO alternate function low register) +Object *afrh; // 0x24(GPIO alternate function high register) +Object *brr; // 0x28(Port bit reset register) +} reg; + + struct { +// MODER(GPIO port mode register) bitfields. + struct { +Object *moder0; // [0:1] Port x configuration bits (y = 0..15)Object *moder1; // [2:3] Port x configuration bits (y = 0..15)Object *moder2; // [4:5] Port x configuration bits (y = 0..15)Object *moder3; // [6:7] Port x configuration bits (y = 0..15)Object *moder4; // [8:9] Port x configuration bits (y = 0..15)Object *moder5; // [10:11] Port x configuration bits (y = 0..15)Object *moder6; // [12:13] Port x configuration bits (y = 0..15)Object *moder7; // [14:15] Port x configuration bits (y = 0..15)Object *moder8; // [16:17] Port x configuration bits (y = 0..15)Object *moder9; // [18:19] Port x configuration bits (y = 0..15)Object *moder10; // [20:21] Port x configuration bits (y = 0..15)Object *moder11; // [22:23] Port x configuration bits (y = 0..15)Object *moder12; // [24:25] Port x configuration bits (y = 0..15)Object *moder13; // [26:27] Port x configuration bits (y = 0..15)Object *moder14; // [28:29] Port x configuration bits (y = 0..15)Object *moder15; // [30:31] Port x configuration bits (y = 0..15)} moder; +// OTYPER(GPIO port output type register) bitfields. + struct { +Object *ot0; // [0:0] Port x configuration bits (y = 0..15)Object *ot1; // [1:1] Port x configuration bits (y = 0..15)Object *ot2; // [2:2] Port x configuration bits (y = 0..15)Object *ot3; // [3:3] Port x configuration bits (y = 0..15)Object *ot4; // [4:4] Port x configuration bits (y = 0..15)Object *ot5; // [5:5] Port x configuration bits (y = 0..15)Object *ot6; // [6:6] Port x configuration bits (y = 0..15)Object *ot7; // [7:7] Port x configuration bits (y = 0..15)Object *ot8; // [8:8] Port x configuration bits (y = 0..15)Object *ot9; // [9:9] Port x configuration bits (y = 0..15)Object *ot10; // [10:10] Port x configuration bits (y = 0..15)Object *ot11; // [11:11] Port x configuration bits (y = 0..15)Object *ot12; // [12:12] Port x configuration bits (y = 0..15)Object *ot13; // [13:13] Port x configuration bits (y = 0..15)Object *ot14; // [14:14] Port x configuration bits (y = 0..15)Object *ot15; // [15:15] Port x configuration bits (y = 0..15)} otyper; +// OSPEEDR(GPIO port output speed register) bitfields. + struct { +Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15)Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15)Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15)Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15)Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15)Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15)Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15)Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15)Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15)Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15)Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15)Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15)Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15)Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15)Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15)Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15)} ospeedr; +// PUPDR(GPIO port pull-up/pull-down register) bitfields. + struct { +Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15)Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15)Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15)Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15)Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15)Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15)Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15)Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15)Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15)Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15)Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15)Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15)Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15)Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15)Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15)Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15)} pupdr; +// IDR(GPIO port input data register) bitfields. + struct { +Object *idr0; // [0:0] Port input data (y = 0..15)Object *idr1; // [1:1] Port input data (y = 0..15)Object *idr2; // [2:2] Port input data (y = 0..15)Object *idr3; // [3:3] Port input data (y = 0..15)Object *idr4; // [4:4] Port input data (y = 0..15)Object *idr5; // [5:5] Port input data (y = 0..15)Object *idr6; // [6:6] Port input data (y = 0..15)Object *idr7; // [7:7] Port input data (y = 0..15)Object *idr8; // [8:8] Port input data (y = 0..15)Object *idr9; // [9:9] Port input data (y = 0..15)Object *idr10; // [10:10] Port input data (y = 0..15)Object *idr11; // [11:11] Port input data (y = 0..15)Object *idr12; // [12:12] Port input data (y = 0..15)Object *idr13; // [13:13] Port input data (y = 0..15)Object *idr14; // [14:14] Port input data (y = 0..15)Object *idr15; // [15:15] Port input data (y = 0..15)} idr; +// ODR(GPIO port output data register) bitfields. + struct { +Object *odr0; // [0:0] Port output data (y = 0..15)Object *odr1; // [1:1] Port output data (y = 0..15)Object *odr2; // [2:2] Port output data (y = 0..15)Object *odr3; // [3:3] Port output data (y = 0..15)Object *odr4; // [4:4] Port output data (y = 0..15)Object *odr5; // [5:5] Port output data (y = 0..15)Object *odr6; // [6:6] Port output data (y = 0..15)Object *odr7; // [7:7] Port output data (y = 0..15)Object *odr8; // [8:8] Port output data (y = 0..15)Object *odr9; // [9:9] Port output data (y = 0..15)Object *odr10; // [10:10] Port output data (y = 0..15)Object *odr11; // [11:11] Port output data (y = 0..15)Object *odr12; // [12:12] Port output data (y = 0..15)Object *odr13; // [13:13] Port output data (y = 0..15)Object *odr14; // [14:14] Port output data (y = 0..15)Object *odr15; // [15:15] Port output data (y = 0..15)} odr; +// BSRR(GPIO port bit set/reset register) bitfields. + struct { +Object *bs0; // [0:0] Port x set bit y (y= 0..15)Object *bs1; // [1:1] Port x set bit y (y= 0..15)Object *bs2; // [2:2] Port x set bit y (y= 0..15)Object *bs3; // [3:3] Port x set bit y (y= 0..15)Object *bs4; // [4:4] Port x set bit y (y= 0..15)Object *bs5; // [5:5] Port x set bit y (y= 0..15)Object *bs6; // [6:6] Port x set bit y (y= 0..15)Object *bs7; // [7:7] Port x set bit y (y= 0..15)Object *bs8; // [8:8] Port x set bit y (y= 0..15)Object *bs9; // [9:9] Port x set bit y (y= 0..15)Object *bs10; // [10:10] Port x set bit y (y= 0..15)Object *bs11; // [11:11] Port x set bit y (y= 0..15)Object *bs12; // [12:12] Port x set bit y (y= 0..15)Object *bs13; // [13:13] Port x set bit y (y= 0..15)Object *bs14; // [14:14] Port x set bit y (y= 0..15)Object *bs15; // [15:15] Port x set bit y (y= 0..15)Object *br0; // [16:16] Port x set bit y (y= 0..15)Object *br1; // [17:17] Port x reset bit y (y = 0..15)Object *br2; // [18:18] Port x reset bit y (y = 0..15)Object *br3; // [19:19] Port x reset bit y (y = 0..15)Object *br4; // [20:20] Port x reset bit y (y = 0..15)Object *br5; // [21:21] Port x reset bit y (y = 0..15)Object *br6; // [22:22] Port x reset bit y (y = 0..15)Object *br7; // [23:23] Port x reset bit y (y = 0..15)Object *br8; // [24:24] Port x reset bit y (y = 0..15)Object *br9; // [25:25] Port x reset bit y (y = 0..15)Object *br10; // [26:26] Port x reset bit y (y = 0..15)Object *br11; // [27:27] Port x reset bit y (y = 0..15)Object *br12; // [28:28] Port x reset bit y (y = 0..15)Object *br13; // [29:29] Port x reset bit y (y = 0..15)Object *br14; // [30:30] Port x reset bit y (y = 0..15)Object *br15; // [31:31] Port x reset bit y (y = 0..15)} bsrr; +// LCKR(GPIO port configuration lock register) bitfields. + struct { +Object *lck0; // [0:0] Port x lock bit y (y= 0..15)Object *lck1; // [1:1] Port x lock bit y (y= 0..15)Object *lck2; // [2:2] Port x lock bit y (y= 0..15)Object *lck3; // [3:3] Port x lock bit y (y= 0..15)Object *lck4; // [4:4] Port x lock bit y (y= 0..15)Object *lck5; // [5:5] Port x lock bit y (y= 0..15)Object *lck6; // [6:6] Port x lock bit y (y= 0..15)Object *lck7; // [7:7] Port x lock bit y (y= 0..15)Object *lck8; // [8:8] Port x lock bit y (y= 0..15)Object *lck9; // [9:9] Port x lock bit y (y= 0..15)Object *lck10; // [10:10] Port x lock bit y (y= 0..15)Object *lck11; // [11:11] Port x lock bit y (y= 0..15)Object *lck12; // [12:12] Port x lock bit y (y= 0..15)Object *lck13; // [13:13] Port x lock bit y (y= 0..15)Object *lck14; // [14:14] Port x lock bit y (y= 0..15)Object *lck15; // [15:15] Port x lock bit y (y= 0..15)Object *lckk; // [16:16] Port x lock bit y (y= 0..15)} lckr; +// AFRL(GPIO alternate function low register) bitfields. + struct { +Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7)Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7)Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7)Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7)Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7)Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7)Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7)Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7)} afrl; +// AFRH(GPIO alternate function high register) bitfields. + struct { +Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15)Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15)Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15)Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15)Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15)Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15)Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15)Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15)} afrh; +// BRR(Port bit reset register) bitfields. + struct { +Object *br0; // [0:0] Port x Reset bit yObject *br1; // [1:1] Port x Reset bit yObject *br2; // [2:2] Port x Reset bit yObject *br3; // [3:3] Port x Reset bit yObject *br4; // [4:4] Port x Reset bit yObject *br5; // [5:5] Port x Reset bit yObject *br6; // [6:6] Port x Reset bit yObject *br7; // [7:7] Port x Reset bit yObject *br8; // [8:8] Port x Reset bit yObject *br9; // [9:9] Port x Reset bit yObject *br10; // [10:10] Port x Reset bit yObject *br11; // [11:11] Port x Reset bit yObject *br12; // [12:12] Port x Reset bit yObject *br13; // [13:13] Port x Reset bit yObject *br14; // [14:14] Port x Reset bit yObject *br15; // [15:15] Port x Reset bit y} brr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/gpiof.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpiof.c new file mode 100644 index 0000000000..b5e95269d2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpiof.c @@ -0,0 +1,434 @@ +/* + * STM32- GPIO(General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.moder= cm_object_get_child_by_name(obj, "MODER"); +state->u.f0.reg.otyper= cm_object_get_child_by_name(obj, "OTYPER"); +state->u.f0.reg.ospeedr= cm_object_get_child_by_name(obj, "OSPEEDR"); +state->u.f0.reg.pupdr= cm_object_get_child_by_name(obj, "PUPDR"); +state->u.f0.reg.idr= cm_object_get_child_by_name(obj, "IDR"); +state->u.f0.reg.odr= cm_object_get_child_by_name(obj, "ODR"); +state->u.f0.reg.bsrr= cm_object_get_child_by_name(obj, "BSRR"); +state->u.f0.reg.lckr= cm_object_get_child_by_name(obj, "LCKR"); +state->u.f0.reg.afrl= cm_object_get_child_by_name(obj, "AFRL"); +state->u.f0.reg.afrh= cm_object_get_child_by_name(obj, "AFRH"); +state->u.f0.reg.brr= cm_object_get_child_by_name(obj, "BRR"); +// MODERbitfields. +state->u.f0.fld.moder.moder0= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER0"); +state->u.f0.fld.moder.moder1= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER1"); +state->u.f0.fld.moder.moder2= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER2"); +state->u.f0.fld.moder.moder3= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER3"); +state->u.f0.fld.moder.moder4= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER4"); +state->u.f0.fld.moder.moder5= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER5"); +state->u.f0.fld.moder.moder6= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER6"); +state->u.f0.fld.moder.moder7= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER7"); +state->u.f0.fld.moder.moder8= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER8"); +state->u.f0.fld.moder.moder9= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER9"); +state->u.f0.fld.moder.moder10= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER10"); +state->u.f0.fld.moder.moder11= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER11"); +state->u.f0.fld.moder.moder12= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER12"); +state->u.f0.fld.moder.moder13= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER13"); +state->u.f0.fld.moder.moder14= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER14"); +state->u.f0.fld.moder.moder15= cm_object_get_child_by_name(state->u.f0.reg.moder, "MODER15"); +// OTYPERbitfields. +state->u.f0.fld.otyper.ot0= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT0"); +state->u.f0.fld.otyper.ot1= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT1"); +state->u.f0.fld.otyper.ot2= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT2"); +state->u.f0.fld.otyper.ot3= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT3"); +state->u.f0.fld.otyper.ot4= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT4"); +state->u.f0.fld.otyper.ot5= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT5"); +state->u.f0.fld.otyper.ot6= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT6"); +state->u.f0.fld.otyper.ot7= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT7"); +state->u.f0.fld.otyper.ot8= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT8"); +state->u.f0.fld.otyper.ot9= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT9"); +state->u.f0.fld.otyper.ot10= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT10"); +state->u.f0.fld.otyper.ot11= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT11"); +state->u.f0.fld.otyper.ot12= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT12"); +state->u.f0.fld.otyper.ot13= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT13"); +state->u.f0.fld.otyper.ot14= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT14"); +state->u.f0.fld.otyper.ot15= cm_object_get_child_by_name(state->u.f0.reg.otyper, "OT15"); +// OSPEEDRbitfields. +state->u.f0.fld.ospeedr.ospeedr0= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR0"); +state->u.f0.fld.ospeedr.ospeedr1= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR1"); +state->u.f0.fld.ospeedr.ospeedr2= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR2"); +state->u.f0.fld.ospeedr.ospeedr3= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR3"); +state->u.f0.fld.ospeedr.ospeedr4= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR4"); +state->u.f0.fld.ospeedr.ospeedr5= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR5"); +state->u.f0.fld.ospeedr.ospeedr6= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR6"); +state->u.f0.fld.ospeedr.ospeedr7= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR7"); +state->u.f0.fld.ospeedr.ospeedr8= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR8"); +state->u.f0.fld.ospeedr.ospeedr9= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR9"); +state->u.f0.fld.ospeedr.ospeedr10= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR10"); +state->u.f0.fld.ospeedr.ospeedr11= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR11"); +state->u.f0.fld.ospeedr.ospeedr12= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR12"); +state->u.f0.fld.ospeedr.ospeedr13= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR13"); +state->u.f0.fld.ospeedr.ospeedr14= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR14"); +state->u.f0.fld.ospeedr.ospeedr15= cm_object_get_child_by_name(state->u.f0.reg.ospeedr, "OSPEEDR15"); +// PUPDRbitfields. +state->u.f0.fld.pupdr.pupdr0= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR0"); +state->u.f0.fld.pupdr.pupdr1= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR1"); +state->u.f0.fld.pupdr.pupdr2= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR2"); +state->u.f0.fld.pupdr.pupdr3= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR3"); +state->u.f0.fld.pupdr.pupdr4= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR4"); +state->u.f0.fld.pupdr.pupdr5= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR5"); +state->u.f0.fld.pupdr.pupdr6= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR6"); +state->u.f0.fld.pupdr.pupdr7= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR7"); +state->u.f0.fld.pupdr.pupdr8= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR8"); +state->u.f0.fld.pupdr.pupdr9= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR9"); +state->u.f0.fld.pupdr.pupdr10= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR10"); +state->u.f0.fld.pupdr.pupdr11= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR11"); +state->u.f0.fld.pupdr.pupdr12= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR12"); +state->u.f0.fld.pupdr.pupdr13= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR13"); +state->u.f0.fld.pupdr.pupdr14= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR14"); +state->u.f0.fld.pupdr.pupdr15= cm_object_get_child_by_name(state->u.f0.reg.pupdr, "PUPDR15"); +// IDRbitfields. +state->u.f0.fld.idr.idr0= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR0"); +state->u.f0.fld.idr.idr1= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR1"); +state->u.f0.fld.idr.idr2= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR2"); +state->u.f0.fld.idr.idr3= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR3"); +state->u.f0.fld.idr.idr4= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR4"); +state->u.f0.fld.idr.idr5= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR5"); +state->u.f0.fld.idr.idr6= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR6"); +state->u.f0.fld.idr.idr7= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR7"); +state->u.f0.fld.idr.idr8= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR8"); +state->u.f0.fld.idr.idr9= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR9"); +state->u.f0.fld.idr.idr10= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR10"); +state->u.f0.fld.idr.idr11= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR11"); +state->u.f0.fld.idr.idr12= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR12"); +state->u.f0.fld.idr.idr13= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR13"); +state->u.f0.fld.idr.idr14= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR14"); +state->u.f0.fld.idr.idr15= cm_object_get_child_by_name(state->u.f0.reg.idr, "IDR15"); +// ODRbitfields. +state->u.f0.fld.odr.odr0= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR0"); +state->u.f0.fld.odr.odr1= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR1"); +state->u.f0.fld.odr.odr2= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR2"); +state->u.f0.fld.odr.odr3= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR3"); +state->u.f0.fld.odr.odr4= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR4"); +state->u.f0.fld.odr.odr5= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR5"); +state->u.f0.fld.odr.odr6= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR6"); +state->u.f0.fld.odr.odr7= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR7"); +state->u.f0.fld.odr.odr8= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR8"); +state->u.f0.fld.odr.odr9= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR9"); +state->u.f0.fld.odr.odr10= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR10"); +state->u.f0.fld.odr.odr11= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR11"); +state->u.f0.fld.odr.odr12= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR12"); +state->u.f0.fld.odr.odr13= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR13"); +state->u.f0.fld.odr.odr14= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR14"); +state->u.f0.fld.odr.odr15= cm_object_get_child_by_name(state->u.f0.reg.odr, "ODR15"); +// BSRRbitfields. +state->u.f0.fld.bsrr.bs0= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS0"); +state->u.f0.fld.bsrr.bs1= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS1"); +state->u.f0.fld.bsrr.bs2= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS2"); +state->u.f0.fld.bsrr.bs3= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS3"); +state->u.f0.fld.bsrr.bs4= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS4"); +state->u.f0.fld.bsrr.bs5= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS5"); +state->u.f0.fld.bsrr.bs6= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS6"); +state->u.f0.fld.bsrr.bs7= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS7"); +state->u.f0.fld.bsrr.bs8= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS8"); +state->u.f0.fld.bsrr.bs9= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS9"); +state->u.f0.fld.bsrr.bs10= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS10"); +state->u.f0.fld.bsrr.bs11= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS11"); +state->u.f0.fld.bsrr.bs12= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS12"); +state->u.f0.fld.bsrr.bs13= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS13"); +state->u.f0.fld.bsrr.bs14= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS14"); +state->u.f0.fld.bsrr.bs15= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BS15"); +state->u.f0.fld.bsrr.br0= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR0"); +state->u.f0.fld.bsrr.br1= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR1"); +state->u.f0.fld.bsrr.br2= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR2"); +state->u.f0.fld.bsrr.br3= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR3"); +state->u.f0.fld.bsrr.br4= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR4"); +state->u.f0.fld.bsrr.br5= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR5"); +state->u.f0.fld.bsrr.br6= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR6"); +state->u.f0.fld.bsrr.br7= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR7"); +state->u.f0.fld.bsrr.br8= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR8"); +state->u.f0.fld.bsrr.br9= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR9"); +state->u.f0.fld.bsrr.br10= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR10"); +state->u.f0.fld.bsrr.br11= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR11"); +state->u.f0.fld.bsrr.br12= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR12"); +state->u.f0.fld.bsrr.br13= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR13"); +state->u.f0.fld.bsrr.br14= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR14"); +state->u.f0.fld.bsrr.br15= cm_object_get_child_by_name(state->u.f0.reg.bsrr, "BR15"); +// LCKRbitfields. +state->u.f0.fld.lckr.lck0= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK0"); +state->u.f0.fld.lckr.lck1= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK1"); +state->u.f0.fld.lckr.lck2= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK2"); +state->u.f0.fld.lckr.lck3= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK3"); +state->u.f0.fld.lckr.lck4= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK4"); +state->u.f0.fld.lckr.lck5= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK5"); +state->u.f0.fld.lckr.lck6= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK6"); +state->u.f0.fld.lckr.lck7= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK7"); +state->u.f0.fld.lckr.lck8= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK8"); +state->u.f0.fld.lckr.lck9= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK9"); +state->u.f0.fld.lckr.lck10= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK10"); +state->u.f0.fld.lckr.lck11= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK11"); +state->u.f0.fld.lckr.lck12= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK12"); +state->u.f0.fld.lckr.lck13= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK13"); +state->u.f0.fld.lckr.lck14= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK14"); +state->u.f0.fld.lckr.lck15= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCK15"); +state->u.f0.fld.lckr.lckk= cm_object_get_child_by_name(state->u.f0.reg.lckr, "LCKK"); +// AFRLbitfields. +state->u.f0.fld.afrl.afrl0= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL0"); +state->u.f0.fld.afrl.afrl1= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL1"); +state->u.f0.fld.afrl.afrl2= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL2"); +state->u.f0.fld.afrl.afrl3= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL3"); +state->u.f0.fld.afrl.afrl4= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL4"); +state->u.f0.fld.afrl.afrl5= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL5"); +state->u.f0.fld.afrl.afrl6= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL6"); +state->u.f0.fld.afrl.afrl7= cm_object_get_child_by_name(state->u.f0.reg.afrl, "AFRL7"); +// AFRHbitfields. +state->u.f0.fld.afrh.afrh8= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH8"); +state->u.f0.fld.afrh.afrh9= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH9"); +state->u.f0.fld.afrh.afrh10= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH10"); +state->u.f0.fld.afrh.afrh11= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH11"); +state->u.f0.fld.afrh.afrh12= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH12"); +state->u.f0.fld.afrh.afrh13= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH13"); +state->u.f0.fld.afrh.afrh14= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH14"); +state->u.f0.fld.afrh.afrh15= cm_object_get_child_by_name(state->u.f0.reg.afrh, "AFRH15"); +// BRRbitfields. +state->u.f0.fld.brr.br0= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR0"); +state->u.f0.fld.brr.br1= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR1"); +state->u.f0.fld.brr.br2= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR2"); +state->u.f0.fld.brr.br3= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR3"); +state->u.f0.fld.brr.br4= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR4"); +state->u.f0.fld.brr.br5= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR5"); +state->u.f0.fld.brr.br6= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR6"); +state->u.f0.fld.brr.br7= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR7"); +state->u.f0.fld.brr.br8= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR8"); +state->u.f0.fld.brr.br9= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR9"); +state->u.f0.fld.brr.br10= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR10"); +state->u.f0.fld.brr.br11= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR11"); +state->u.f0.fld.brr.br12= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR12"); +state->u.f0.fld.brr.br13= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR13"); +state->u.f0.fld.brr.br14= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR14"); +state->u.f0.fld.brr.br15= cm_object_get_child_by_name(state->u.f0.reg.brr, "BR15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + +cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/gpiof.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpiof.h new file mode 100644 index 0000000000..3d514cf945 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/gpiof.h @@ -0,0 +1,156 @@ +/* + * STM32- GPIO(General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIODEVICE_PATH_STM32"GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. +STM32_PORT_GPIOA, +STM32_PORT_GPIOB, +STM32_PORT_GPIOC, +STM32_PORT_GPIOD, +STM32_PORT_GPIOE, +STM32_PORT_GPIOF, +STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIOTYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +// Remove it if there is only one port + stm32_gpio_index_t port_index; +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0GPIO(General-purpose I/Os) registers. + struct { +Object *moder; // 0x0(GPIO port mode register) +Object *otyper; // 0x4(GPIO port output type register) +Object *ospeedr; // 0x8(GPIO port output speed register) +Object *pupdr; // 0xC(GPIO port pull-up/pull-down register) +Object *idr; // 0x10(GPIO port input data register) +Object *odr; // 0x14(GPIO port output data register) +Object *bsrr; // 0x18(GPIO port bit set/reset register) +Object *lckr; // 0x1C(GPIO port configuration lock register) +Object *afrl; // 0x20(GPIO alternate function low register) +Object *afrh; // 0x24(GPIO alternate function high register) +Object *brr; // 0x28(Port bit reset register) +} reg; + + struct { +// MODER(GPIO port mode register) bitfields. + struct { +Object *moder0; // [0:1] Port x configuration bits (y = 0..15)Object *moder1; // [2:3] Port x configuration bits (y = 0..15)Object *moder2; // [4:5] Port x configuration bits (y = 0..15)Object *moder3; // [6:7] Port x configuration bits (y = 0..15)Object *moder4; // [8:9] Port x configuration bits (y = 0..15)Object *moder5; // [10:11] Port x configuration bits (y = 0..15)Object *moder6; // [12:13] Port x configuration bits (y = 0..15)Object *moder7; // [14:15] Port x configuration bits (y = 0..15)Object *moder8; // [16:17] Port x configuration bits (y = 0..15)Object *moder9; // [18:19] Port x configuration bits (y = 0..15)Object *moder10; // [20:21] Port x configuration bits (y = 0..15)Object *moder11; // [22:23] Port x configuration bits (y = 0..15)Object *moder12; // [24:25] Port x configuration bits (y = 0..15)Object *moder13; // [26:27] Port x configuration bits (y = 0..15)Object *moder14; // [28:29] Port x configuration bits (y = 0..15)Object *moder15; // [30:31] Port x configuration bits (y = 0..15)} moder; +// OTYPER(GPIO port output type register) bitfields. + struct { +Object *ot0; // [0:0] Port x configuration bit 0Object *ot1; // [1:1] Port x configuration bit 1Object *ot2; // [2:2] Port x configuration bit 2Object *ot3; // [3:3] Port x configuration bit 3Object *ot4; // [4:4] Port x configuration bit 4Object *ot5; // [5:5] Port x configuration bit 5Object *ot6; // [6:6] Port x configuration bit 6Object *ot7; // [7:7] Port x configuration bit 7Object *ot8; // [8:8] Port x configuration bit 8Object *ot9; // [9:9] Port x configuration bit 9Object *ot10; // [10:10] Port x configuration bit 10Object *ot11; // [11:11] Port x configuration bit 11Object *ot12; // [12:12] Port x configuration bit 12Object *ot13; // [13:13] Port x configuration bit 13Object *ot14; // [14:14] Port x configuration bit 14Object *ot15; // [15:15] Port x configuration bit 15} otyper; +// OSPEEDR(GPIO port output speed register) bitfields. + struct { +Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15)Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15)Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15)Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15)Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15)Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15)Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15)Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15)Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15)Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15)Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15)Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15)Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15)Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15)Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15)Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15)} ospeedr; +// PUPDR(GPIO port pull-up/pull-down register) bitfields. + struct { +Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15)Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15)Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15)Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15)Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15)Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15)Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15)Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15)Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15)Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15)Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15)Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15)Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15)Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15)Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15)Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15)} pupdr; +// IDR(GPIO port input data register) bitfields. + struct { +Object *idr0; // [0:0] Port input data (y = 0..15)Object *idr1; // [1:1] Port input data (y = 0..15)Object *idr2; // [2:2] Port input data (y = 0..15)Object *idr3; // [3:3] Port input data (y = 0..15)Object *idr4; // [4:4] Port input data (y = 0..15)Object *idr5; // [5:5] Port input data (y = 0..15)Object *idr6; // [6:6] Port input data (y = 0..15)Object *idr7; // [7:7] Port input data (y = 0..15)Object *idr8; // [8:8] Port input data (y = 0..15)Object *idr9; // [9:9] Port input data (y = 0..15)Object *idr10; // [10:10] Port input data (y = 0..15)Object *idr11; // [11:11] Port input data (y = 0..15)Object *idr12; // [12:12] Port input data (y = 0..15)Object *idr13; // [13:13] Port input data (y = 0..15)Object *idr14; // [14:14] Port input data (y = 0..15)Object *idr15; // [15:15] Port input data (y = 0..15)} idr; +// ODR(GPIO port output data register) bitfields. + struct { +Object *odr0; // [0:0] Port output data (y = 0..15)Object *odr1; // [1:1] Port output data (y = 0..15)Object *odr2; // [2:2] Port output data (y = 0..15)Object *odr3; // [3:3] Port output data (y = 0..15)Object *odr4; // [4:4] Port output data (y = 0..15)Object *odr5; // [5:5] Port output data (y = 0..15)Object *odr6; // [6:6] Port output data (y = 0..15)Object *odr7; // [7:7] Port output data (y = 0..15)Object *odr8; // [8:8] Port output data (y = 0..15)Object *odr9; // [9:9] Port output data (y = 0..15)Object *odr10; // [10:10] Port output data (y = 0..15)Object *odr11; // [11:11] Port output data (y = 0..15)Object *odr12; // [12:12] Port output data (y = 0..15)Object *odr13; // [13:13] Port output data (y = 0..15)Object *odr14; // [14:14] Port output data (y = 0..15)Object *odr15; // [15:15] Port output data (y = 0..15)} odr; +// BSRR(GPIO port bit set/reset register) bitfields. + struct { +Object *bs0; // [0:0] Port x set bit y (y= 0..15)Object *bs1; // [1:1] Port x set bit y (y= 0..15)Object *bs2; // [2:2] Port x set bit y (y= 0..15)Object *bs3; // [3:3] Port x set bit y (y= 0..15)Object *bs4; // [4:4] Port x set bit y (y= 0..15)Object *bs5; // [5:5] Port x set bit y (y= 0..15)Object *bs6; // [6:6] Port x set bit y (y= 0..15)Object *bs7; // [7:7] Port x set bit y (y= 0..15)Object *bs8; // [8:8] Port x set bit y (y= 0..15)Object *bs9; // [9:9] Port x set bit y (y= 0..15)Object *bs10; // [10:10] Port x set bit y (y= 0..15)Object *bs11; // [11:11] Port x set bit y (y= 0..15)Object *bs12; // [12:12] Port x set bit y (y= 0..15)Object *bs13; // [13:13] Port x set bit y (y= 0..15)Object *bs14; // [14:14] Port x set bit y (y= 0..15)Object *bs15; // [15:15] Port x set bit y (y= 0..15)Object *br0; // [16:16] Port x set bit y (y= 0..15)Object *br1; // [17:17] Port x reset bit y (y = 0..15)Object *br2; // [18:18] Port x reset bit y (y = 0..15)Object *br3; // [19:19] Port x reset bit y (y = 0..15)Object *br4; // [20:20] Port x reset bit y (y = 0..15)Object *br5; // [21:21] Port x reset bit y (y = 0..15)Object *br6; // [22:22] Port x reset bit y (y = 0..15)Object *br7; // [23:23] Port x reset bit y (y = 0..15)Object *br8; // [24:24] Port x reset bit y (y = 0..15)Object *br9; // [25:25] Port x reset bit y (y = 0..15)Object *br10; // [26:26] Port x reset bit y (y = 0..15)Object *br11; // [27:27] Port x reset bit y (y = 0..15)Object *br12; // [28:28] Port x reset bit y (y = 0..15)Object *br13; // [29:29] Port x reset bit y (y = 0..15)Object *br14; // [30:30] Port x reset bit y (y = 0..15)Object *br15; // [31:31] Port x reset bit y (y = 0..15)} bsrr; +// LCKR(GPIO port configuration lock register) bitfields. + struct { +Object *lck0; // [0:0] Port x lock bit y (y= 0..15)Object *lck1; // [1:1] Port x lock bit y (y= 0..15)Object *lck2; // [2:2] Port x lock bit y (y= 0..15)Object *lck3; // [3:3] Port x lock bit y (y= 0..15)Object *lck4; // [4:4] Port x lock bit y (y= 0..15)Object *lck5; // [5:5] Port x lock bit y (y= 0..15)Object *lck6; // [6:6] Port x lock bit y (y= 0..15)Object *lck7; // [7:7] Port x lock bit y (y= 0..15)Object *lck8; // [8:8] Port x lock bit y (y= 0..15)Object *lck9; // [9:9] Port x lock bit y (y= 0..15)Object *lck10; // [10:10] Port x lock bit y (y= 0..15)Object *lck11; // [11:11] Port x lock bit y (y= 0..15)Object *lck12; // [12:12] Port x lock bit y (y= 0..15)Object *lck13; // [13:13] Port x lock bit y (y= 0..15)Object *lck14; // [14:14] Port x lock bit y (y= 0..15)Object *lck15; // [15:15] Port x lock bit y (y= 0..15)Object *lckk; // [16:16] Port x lock bit y} lckr; +// AFRL(GPIO alternate function low register) bitfields. + struct { +Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7)Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7)Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7)Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7)Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7)Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7)Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7)Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7)} afrl; +// AFRH(GPIO alternate function high register) bitfields. + struct { +Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15)Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15)Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15)Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15)Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15)Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15)Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15)Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15)} afrh; +// BRR(Port bit reset register) bitfields. + struct { +Object *br0; // [0:0] Port x Reset bit yObject *br1; // [1:1] Port x Reset bit yObject *br2; // [2:2] Port x Reset bit yObject *br3; // [3:3] Port x Reset bit yObject *br4; // [4:4] Port x Reset bit yObject *br5; // [5:5] Port x Reset bit yObject *br6; // [6:6] Port x Reset bit yObject *br7; // [7:7] Port x Reset bit yObject *br8; // [8:8] Port x Reset bit yObject *br9; // [9:9] Port x Reset bit yObject *br10; // [10:10] Port x Reset bit yObject *br11; // [11:11] Port x Reset bit yObject *br12; // [12:12] Port x Reset bit yObject *br13; // [13:13] Port x Reset bit yObject *br14; // [14:14] Port x Reset bit yObject *br15; // [15:15] Port x Reset bit y} brr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/i2c1.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/i2c1.c new file mode 100644 index 0000000000..105af9b5ee --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/i2c1.c @@ -0,0 +1,338 @@ +/* + * STM32- I2C(Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_i2c_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.oar1= cm_object_get_child_by_name(obj, "OAR1"); +state->u.f0.reg.oar2= cm_object_get_child_by_name(obj, "OAR2"); +state->u.f0.reg.timingr= cm_object_get_child_by_name(obj, "TIMINGR"); +state->u.f0.reg.timeoutr= cm_object_get_child_by_name(obj, "TIMEOUTR"); +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.icr= cm_object_get_child_by_name(obj, "ICR"); +state->u.f0.reg.pecr= cm_object_get_child_by_name(obj, "PECR"); +state->u.f0.reg.rxdr= cm_object_get_child_by_name(obj, "RXDR"); +state->u.f0.reg.txdr= cm_object_get_child_by_name(obj, "TXDR"); +// CR1bitfields. +state->u.f0.fld.cr1.pe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "PE"); +state->u.f0.fld.cr1.txie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "TXIE"); +state->u.f0.fld.cr1.rxie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXIE"); +state->u.f0.fld.cr1.addrie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ADDRIE"); +state->u.f0.fld.cr1.nackie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "NACKIE"); +state->u.f0.fld.cr1.stopie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "STOPIE"); +state->u.f0.fld.cr1.tcie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "TCIE"); +state->u.f0.fld.cr1.errie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ERRIE"); +state->u.f0.fld.cr1.dnf= cm_object_get_child_by_name(state->u.f0.reg.cr1, "DNF"); +state->u.f0.fld.cr1.anfoff= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ANFOFF"); +state->u.f0.fld.cr1.swrst= cm_object_get_child_by_name(state->u.f0.reg.cr1, "SWRST"); +state->u.f0.fld.cr1.txdmaen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "TXDMAEN"); +state->u.f0.fld.cr1.rxdmaen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXDMAEN"); +state->u.f0.fld.cr1.sbc= cm_object_get_child_by_name(state->u.f0.reg.cr1, "SBC"); +state->u.f0.fld.cr1.nostretch= cm_object_get_child_by_name(state->u.f0.reg.cr1, "NOSTRETCH"); +state->u.f0.fld.cr1.wupen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "WUPEN"); +state->u.f0.fld.cr1.gcen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "GCEN"); +state->u.f0.fld.cr1.smbhen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "SMBHEN"); +state->u.f0.fld.cr1.smbden= cm_object_get_child_by_name(state->u.f0.reg.cr1, "SMBDEN"); +state->u.f0.fld.cr1.alerten= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ALERTEN"); +state->u.f0.fld.cr1.pecen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "PECEN"); +// CR2bitfields. +state->u.f0.fld.cr2.sadd0= cm_object_get_child_by_name(state->u.f0.reg.cr2, "SADD0"); +state->u.f0.fld.cr2.sadd1= cm_object_get_child_by_name(state->u.f0.reg.cr2, "SADD1"); +state->u.f0.fld.cr2.sadd8= cm_object_get_child_by_name(state->u.f0.reg.cr2, "SADD8"); +state->u.f0.fld.cr2.rd_wrn= cm_object_get_child_by_name(state->u.f0.reg.cr2, "RD_WRN"); +state->u.f0.fld.cr2.add10= cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADD10"); +state->u.f0.fld.cr2.head10r= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HEAD10R"); +state->u.f0.fld.cr2.start= cm_object_get_child_by_name(state->u.f0.reg.cr2, "START"); +state->u.f0.fld.cr2.stop= cm_object_get_child_by_name(state->u.f0.reg.cr2, "STOP"); +state->u.f0.fld.cr2.nack= cm_object_get_child_by_name(state->u.f0.reg.cr2, "NACK"); +state->u.f0.fld.cr2.nbytes= cm_object_get_child_by_name(state->u.f0.reg.cr2, "NBYTES"); +state->u.f0.fld.cr2.reload= cm_object_get_child_by_name(state->u.f0.reg.cr2, "RELOAD"); +state->u.f0.fld.cr2.autoend= cm_object_get_child_by_name(state->u.f0.reg.cr2, "AUTOEND"); +state->u.f0.fld.cr2.pecbyte= cm_object_get_child_by_name(state->u.f0.reg.cr2, "PECBYTE"); +// OAR1bitfields. +state->u.f0.fld.oar1.oa1_0= cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1_0"); +state->u.f0.fld.oar1.oa1_1= cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1_1"); +state->u.f0.fld.oar1.oa1_8= cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1_8"); +state->u.f0.fld.oar1.oa1mode= cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1MODE"); +state->u.f0.fld.oar1.oa1en= cm_object_get_child_by_name(state->u.f0.reg.oar1, "OA1EN"); +// OAR2bitfields. +state->u.f0.fld.oar2.oa2= cm_object_get_child_by_name(state->u.f0.reg.oar2, "OA2"); +state->u.f0.fld.oar2.oa2msk= cm_object_get_child_by_name(state->u.f0.reg.oar2, "OA2MSK"); +state->u.f0.fld.oar2.oa2en= cm_object_get_child_by_name(state->u.f0.reg.oar2, "OA2EN"); +// TIMINGRbitfields. +state->u.f0.fld.timingr.scll= cm_object_get_child_by_name(state->u.f0.reg.timingr, "SCLL"); +state->u.f0.fld.timingr.sclh= cm_object_get_child_by_name(state->u.f0.reg.timingr, "SCLH"); +state->u.f0.fld.timingr.sdadel= cm_object_get_child_by_name(state->u.f0.reg.timingr, "SDADEL"); +state->u.f0.fld.timingr.scldel= cm_object_get_child_by_name(state->u.f0.reg.timingr, "SCLDEL"); +state->u.f0.fld.timingr.presc= cm_object_get_child_by_name(state->u.f0.reg.timingr, "PRESC"); +// TIMEOUTRbitfields. +state->u.f0.fld.timeoutr.timeouta= cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIMEOUTA"); +state->u.f0.fld.timeoutr.tidle= cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIDLE"); +state->u.f0.fld.timeoutr.timouten= cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIMOUTEN"); +state->u.f0.fld.timeoutr.timeoutb= cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TIMEOUTB"); +state->u.f0.fld.timeoutr.texten= cm_object_get_child_by_name(state->u.f0.reg.timeoutr, "TEXTEN"); +// ISRbitfields. +state->u.f0.fld.isr.txe= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXE"); +state->u.f0.fld.isr.txis= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXIS"); +state->u.f0.fld.isr.rxne= cm_object_get_child_by_name(state->u.f0.reg.isr, "RXNE"); +state->u.f0.fld.isr.addr= cm_object_get_child_by_name(state->u.f0.reg.isr, "ADDR"); +state->u.f0.fld.isr.nackf= cm_object_get_child_by_name(state->u.f0.reg.isr, "NACKF"); +state->u.f0.fld.isr.stopf= cm_object_get_child_by_name(state->u.f0.reg.isr, "STOPF"); +state->u.f0.fld.isr.tc= cm_object_get_child_by_name(state->u.f0.reg.isr, "TC"); +state->u.f0.fld.isr.tcr= cm_object_get_child_by_name(state->u.f0.reg.isr, "TCR"); +state->u.f0.fld.isr.berr= cm_object_get_child_by_name(state->u.f0.reg.isr, "BERR"); +state->u.f0.fld.isr.arlo= cm_object_get_child_by_name(state->u.f0.reg.isr, "ARLO"); +state->u.f0.fld.isr.ovr= cm_object_get_child_by_name(state->u.f0.reg.isr, "OVR"); +state->u.f0.fld.isr.pecerr= cm_object_get_child_by_name(state->u.f0.reg.isr, "PECERR"); +state->u.f0.fld.isr.timeout= cm_object_get_child_by_name(state->u.f0.reg.isr, "TIMEOUT"); +state->u.f0.fld.isr.alert= cm_object_get_child_by_name(state->u.f0.reg.isr, "ALERT"); +state->u.f0.fld.isr.busy= cm_object_get_child_by_name(state->u.f0.reg.isr, "BUSY"); +state->u.f0.fld.isr.dir= cm_object_get_child_by_name(state->u.f0.reg.isr, "DIR"); +state->u.f0.fld.isr.addcode= cm_object_get_child_by_name(state->u.f0.reg.isr, "ADDCODE"); +// ICRbitfields. +state->u.f0.fld.icr.addrcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "ADDRCF"); +state->u.f0.fld.icr.nackcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "NACKCF"); +state->u.f0.fld.icr.stopcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "STOPCF"); +state->u.f0.fld.icr.berrcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "BERRCF"); +state->u.f0.fld.icr.arlocf= cm_object_get_child_by_name(state->u.f0.reg.icr, "ARLOCF"); +state->u.f0.fld.icr.ovrcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "OVRCF"); +state->u.f0.fld.icr.peccf= cm_object_get_child_by_name(state->u.f0.reg.icr, "PECCF"); +state->u.f0.fld.icr.timoutcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "TIMOUTCF"); +state->u.f0.fld.icr.alertcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "ALERTCF"); +// PECRbitfields. +state->u.f0.fld.pecr.pec= cm_object_get_child_by_name(state->u.f0.reg.pecr, "PEC"); +// RXDRbitfields. +state->u.f0.fld.rxdr.rxdata= cm_object_get_child_by_name(state->u.f0.reg.rxdr, "RXDATA"); +// TXDRbitfields. +state->u.f0.fld.txdr.txdata= cm_object_get_child_by_name(state->u.f0.reg.txdr, "TXDATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2c_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2c_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2c_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2c_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2c_is_enabled(Object *obj) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2c_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2CState *state = STM32_I2C_STATE(obj); + + // Capabilities are not yet available. + +cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_I2C_UNDEFINED; +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2c_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2C)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2CState *state = STM32_I2C_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2C"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_i2c_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_i2c_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_i2c_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_i2c_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_i2c_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2C%dEN", + 1 + state->port_index - STM32_PORT_I2C1); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2c_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2C); +} + +static void stm32_i2c_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2c_reset_callback; + dc->realize = stm32_i2c_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2c_is_enabled; +} + +static const TypeInfo stm32_i2c_type_info = { + .name = TYPE_STM32_I2C, + .parent = TYPE_STM32_I2C_PARENT, + .instance_init = stm32_i2c_instance_init_callback, + .instance_size = sizeof(STM32I2CState), + .class_init = stm32_i2c_class_init_callback, + .class_size = sizeof(STM32I2CClass) }; + +static void stm32_i2c_register_types(void) +{ + type_register_static(&stm32_i2c_type_info); +} + +type_init(stm32_i2c_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/i2c1.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/i2c1.h new file mode 100644 index 0000000000..2d55efda6a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/i2c1.h @@ -0,0 +1,152 @@ +/* + * STM32- I2C(Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2C_H_ +#define STM32_I2C_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2CDEVICE_PATH_STM32"I2C" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. +STM32_PORT_I2C1, +STM32_PORT_I2C2, +STM32_PORT_I2C_UNDEFINED = 0xFF, +} stm32_i2c_index_t; +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2CTYPE_STM32_PREFIX "i2c" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2C_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2CParentClass; +typedef PeripheralState STM32I2CParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2CClass, (obj), TYPE_STM32_I2C) +#define STM32_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2CClass, (klass), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentClass parent_class; + // public: + + // None, so far. +} STM32I2CClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2C_STATE(obj) \ + OBJECT_CHECK(STM32I2CState, (obj), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +// Remove it if there is only one port + stm32_i2c_index_t port_index; +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0I2C(Inter-integrated circuit) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *oar1; // 0x8(Own address register 1) +Object *oar2; // 0xC(Own address register 2) +Object *timingr; // 0x10(Timing register) +Object *timeoutr; // 0x14(Status register 1) +Object *isr; // 0x18(Interrupt and Status register) +Object *icr; // 0x1C(Interrupt clear register) +Object *pecr; // 0x20(PEC register) +Object *rxdr; // 0x24(Receive data register) +Object *txdr; // 0x28(Transmit data register) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *pe; // [0:0] Peripheral enableObject *txie; // [1:1] TX Interrupt enableObject *rxie; // [2:2] RX Interrupt enableObject *addrie; // [3:3] Address match interrupt enable (slave only)Object *nackie; // [4:4] Not acknowledge received interrupt enableObject *stopie; // [5:5] STOP detection Interrupt enableObject *tcie; // [6:6] Transfer Complete interrupt enableObject *errie; // [7:7] Error interrupts enableObject *dnf; // [8:11] Digital noise filterObject *anfoff; // [12:12] Analog noise filter OFFObject *swrst; // [13:13] Software resetObject *txdmaen; // [14:14] DMA transmission requests enableObject *rxdmaen; // [15:15] DMA reception requests enableObject *sbc; // [16:16] Slave byte controlObject *nostretch; // [17:17] Clock stretching disableObject *wupen; // [18:18] Wakeup from STOP enableObject *gcen; // [19:19] General call enableObject *smbhen; // [20:20] SMBus Host address enableObject *smbden; // [21:21] SMBus Device Default address enableObject *alerten; // [22:22] SMBUS alert enableObject *pecen; // [23:23] PEC enable} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *sadd0; // [0:0] Slave address bit 0 (master mode)Object *sadd1; // [1:7] Slave address bit 7:1 (master mode)Object *sadd8; // [8:9] Slave address bit 9:8 (master mode)Object *rd_wrn; // [10:10] Transfer direction (master mode)Object *add10; // [11:11] 10-bit addressing mode (master mode)Object *head10r; // [12:12] 10-bit address header only read direction (master receiver mode)Object *start; // [13:13] Start generationObject *stop; // [14:14] Stop generation (master mode)Object *nack; // [15:15] NACK generation (slave mode)Object *nbytes; // [16:23] Number of bytesObject *reload; // [24:24] NBYTES reload modeObject *autoend; // [25:25] Automatic end mode (master mode)Object *pecbyte; // [26:26] Packet error checking byte} cr2; +// OAR1(Own address register 1) bitfields. + struct { +Object *oa1_0; // [0:0] Interface addressObject *oa1_1; // [1:7] Interface addressObject *oa1_8; // [8:9] Interface addressObject *oa1mode; // [10:10] Own Address 1 10-bit modeObject *oa1en; // [15:15] Own Address 1 enable} oar1; +// OAR2(Own address register 2) bitfields. + struct { +Object *oa2; // [1:7] Interface addressObject *oa2msk; // [8:10] Own Address 2 masksObject *oa2en; // [15:15] Own Address 2 enable} oar2; +// TIMINGR(Timing register) bitfields. + struct { +Object *scll; // [0:7] SCL low period (master mode)Object *sclh; // [8:15] SCL high period (master mode)Object *sdadel; // [16:19] Data hold timeObject *scldel; // [20:23] Data setup timeObject *presc; // [28:31] Timing prescaler} timingr; +// TIMEOUTR(Status register 1) bitfields. + struct { +Object *timeouta; // [0:11] Bus timeout AObject *tidle; // [12:12] Idle clock timeout detectionObject *timouten; // [15:15] Clock timeout enableObject *timeoutb; // [16:27] Bus timeout BObject *texten; // [31:31] Extended clock timeout enable} timeoutr; +// ISR(Interrupt and Status register) bitfields. + struct { +Object *txe; // [0:0] Transmit data register empty (transmitters)Object *txis; // [1:1] Transmit interrupt status (transmitters)Object *rxne; // [2:2] Receive data register not empty (receivers)Object *addr; // [3:3] Address matched (slave mode)Object *nackf; // [4:4] Not acknowledge received flagObject *stopf; // [5:5] Stop detection flagObject *tc; // [6:6] Transfer Complete (master mode)Object *tcr; // [7:7] Transfer Complete ReloadObject *berr; // [8:8] Bus errorObject *arlo; // [9:9] Arbitration lostObject *ovr; // [10:10] Overrun/Underrun (slave mode)Object *pecerr; // [11:11] PEC Error in receptionObject *timeout; // [12:12] Timeout or t_low detection flagObject *alert; // [13:13] SMBus alertObject *busy; // [15:15] Bus busyObject *dir; // [16:16] Transfer direction (Slave mode)Object *addcode; // [17:23] Address match code (Slave mode)} isr; +// ICR(Interrupt clear register) bitfields. + struct { +Object *addrcf; // [3:3] Address Matched flag clearObject *nackcf; // [4:4] Not Acknowledge flag clearObject *stopcf; // [5:5] Stop detection flag clearObject *berrcf; // [8:8] Bus error flag clearObject *arlocf; // [9:9] Arbitration lost flag clearObject *ovrcf; // [10:10] Overrun/Underrun flag clearObject *peccf; // [11:11] PEC Error flag clearObject *timoutcf; // [12:12] Timeout detection flag clearObject *alertcf; // [13:13] Alert flag clear} icr; +// PECR(PEC register) bitfields. + struct { +Object *pec; // [0:7] Packet error checking register} pecr; +// RXDR(Receive data register) bitfields. + struct { +Object *rxdata; // [0:7] 8-bit receive data} rxdr; +// TXDR(Transmit data register) bitfields. + struct { +Object *txdata; // [0:7] 8-bit transmit data} txdr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2CState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2C_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/iwdg.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/iwdg.c new file mode 100644 index 0000000000..3255b03ac2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/iwdg.c @@ -0,0 +1,248 @@ +/* + * STM32- IWDG(Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_iwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.kr= cm_object_get_child_by_name(obj, "KR"); +state->u.f0.reg.pr= cm_object_get_child_by_name(obj, "PR"); +state->u.f0.reg.rlr= cm_object_get_child_by_name(obj, "RLR"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.winr= cm_object_get_child_by_name(obj, "WINR"); +// KRbitfields. +state->u.f0.fld.kr.key= cm_object_get_child_by_name(state->u.f0.reg.kr, "KEY"); +// PRbitfields. +state->u.f0.fld.pr.pr= cm_object_get_child_by_name(state->u.f0.reg.pr, "PR"); +// RLRbitfields. +state->u.f0.fld.rlr.rl= cm_object_get_child_by_name(state->u.f0.reg.rlr, "RL"); +// SRbitfields. +state->u.f0.fld.sr.pvu= cm_object_get_child_by_name(state->u.f0.reg.sr, "PVU"); +state->u.f0.fld.sr.rvu= cm_object_get_child_by_name(state->u.f0.reg.sr, "RVU"); +state->u.f0.fld.sr.wvu= cm_object_get_child_by_name(state->u.f0.reg.sr, "WVU"); +// WINRbitfields. +state->u.f0.fld.winr.win= cm_object_get_child_by_name(state->u.f0.reg.winr, "WIN"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_iwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_iwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_iwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_iwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_iwdg_is_enabled(Object *obj) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_iwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_iwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_IWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32IWDGState *state = STM32_IWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "IWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_iwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_iwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_iwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_iwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_iwdg_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/IWDGEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_iwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_IWDG); +} + +static void stm32_iwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_iwdg_reset_callback; + dc->realize = stm32_iwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_iwdg_is_enabled; +} + +static const TypeInfo stm32_iwdg_type_info = { + .name = TYPE_STM32_IWDG, + .parent = TYPE_STM32_IWDG_PARENT, + .instance_init = stm32_iwdg_instance_init_callback, + .instance_size = sizeof(STM32IWDGState), + .class_init = stm32_iwdg_class_init_callback, + .class_size = sizeof(STM32IWDGClass) }; + +static void stm32_iwdg_register_types(void) +{ + type_register_static(&stm32_iwdg_type_info); +} + +type_init(stm32_iwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/iwdg.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/iwdg.h new file mode 100644 index 0000000000..5ebbee1cb1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/iwdg.h @@ -0,0 +1,117 @@ +/* + * STM32- IWDG(Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_IWDG_H_ +#define STM32_IWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_IWDGDEVICE_PATH_STM32"IWDG" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_IWDGTYPE_STM32_PREFIX "iwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_IWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32IWDGParentClass; +typedef PeripheralState STM32IWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_IWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32IWDGClass, (obj), TYPE_STM32_IWDG) +#define STM32_IWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32IWDGClass, (klass), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentClass parent_class; + // public: + + // None, so far. +} STM32IWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_IWDG_STATE(obj) \ + OBJECT_CHECK(STM32IWDGState, (obj), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0IWDG(Independent watchdog) registers. + struct { +Object *kr; // 0x0(Key register) +Object *pr; // 0x4(Prescaler register) +Object *rlr; // 0x8(Reload register) +Object *sr; // 0xC(Status register) +Object *winr; // 0x10(Window register) +} reg; + + struct { +// KR(Key register) bitfields. + struct { +Object *key; // [0:15] Key value} kr; +// PR(Prescaler register) bitfields. + struct { +Object *pr; // [0:2] Prescaler divider} pr; +// RLR(Reload register) bitfields. + struct { +Object *rl; // [0:11] Watchdog counter reload value} rlr; +// SR(Status register) bitfields. + struct { +Object *pvu; // [0:0] Watchdog prescaler value updateObject *rvu; // [1:1] Watchdog counter reload value updateObject *wvu; // [2:2] Watchdog counter window value update} sr; +// WINR(Window register) bitfields. + struct { +Object *win; // [0:11] Watchdog counter window value} winr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32IWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_IWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/pwr.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/pwr.c new file mode 100644 index 0000000000..db9bfce694 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/pwr.c @@ -0,0 +1,254 @@ +/* + * STM32- PWR(Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_pwr_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.csr= cm_object_get_child_by_name(obj, "CSR"); +// CRbitfields. +state->u.f0.fld.cr.lpds= cm_object_get_child_by_name(state->u.f0.reg.cr, "LPDS"); +state->u.f0.fld.cr.pdds= cm_object_get_child_by_name(state->u.f0.reg.cr, "PDDS"); +state->u.f0.fld.cr.cwuf= cm_object_get_child_by_name(state->u.f0.reg.cr, "CWUF"); +state->u.f0.fld.cr.csbf= cm_object_get_child_by_name(state->u.f0.reg.cr, "CSBF"); +state->u.f0.fld.cr.pvde= cm_object_get_child_by_name(state->u.f0.reg.cr, "PVDE"); +state->u.f0.fld.cr.pls= cm_object_get_child_by_name(state->u.f0.reg.cr, "PLS"); +state->u.f0.fld.cr.dbp= cm_object_get_child_by_name(state->u.f0.reg.cr, "DBP"); +// CSRbitfields. +state->u.f0.fld.csr.wuf= cm_object_get_child_by_name(state->u.f0.reg.csr, "WUF"); +state->u.f0.fld.csr.sbf= cm_object_get_child_by_name(state->u.f0.reg.csr, "SBF"); +state->u.f0.fld.csr.pvdo= cm_object_get_child_by_name(state->u.f0.reg.csr, "PVDO"); +state->u.f0.fld.csr.vrefintrdy= cm_object_get_child_by_name(state->u.f0.reg.csr, "VREFINTRDY"); +state->u.f0.fld.csr.ewup1= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP1"); +state->u.f0.fld.csr.ewup2= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP2"); +state->u.f0.fld.csr.ewup3= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP3"); +state->u.f0.fld.csr.ewup4= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP4"); +state->u.f0.fld.csr.ewup5= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP5"); +state->u.f0.fld.csr.ewup6= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP6"); +state->u.f0.fld.csr.ewup7= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP7"); +state->u.f0.fld.csr.ewup8= cm_object_get_child_by_name(state->u.f0.reg.csr, "EWUP8"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_pwr_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_pwr_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_pwr_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_pwr_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_pwr_is_enabled(Object *obj) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_pwr_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32PWRState *state = STM32_PWR_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_pwr_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_PWR)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32PWRState *state = STM32_PWR_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "PWR"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_pwr_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_pwr_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_pwr_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_pwr_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_pwr_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/PWREN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_pwr_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_PWR); +} + +static void stm32_pwr_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_pwr_reset_callback; + dc->realize = stm32_pwr_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_pwr_is_enabled; +} + +static const TypeInfo stm32_pwr_type_info = { + .name = TYPE_STM32_PWR, + .parent = TYPE_STM32_PWR_PARENT, + .instance_init = stm32_pwr_instance_init_callback, + .instance_size = sizeof(STM32PWRState), + .class_init = stm32_pwr_class_init_callback, + .class_size = sizeof(STM32PWRClass) }; + +static void stm32_pwr_register_types(void) +{ + type_register_static(&stm32_pwr_type_info); +} + +type_init(stm32_pwr_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/pwr.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/pwr.h new file mode 100644 index 0000000000..74f52e3b55 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/pwr.h @@ -0,0 +1,105 @@ +/* + * STM32- PWR(Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_PWR_H_ +#define STM32_PWR_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_PWRDEVICE_PATH_STM32"PWR" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_PWRTYPE_STM32_PREFIX "pwr" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_PWR_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32PWRParentClass; +typedef PeripheralState STM32PWRParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_PWR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32PWRClass, (obj), TYPE_STM32_PWR) +#define STM32_PWR_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32PWRClass, (klass), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentClass parent_class; + // public: + + // None, so far. +} STM32PWRClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_PWR_STATE(obj) \ + OBJECT_CHECK(STM32PWRState, (obj), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0PWR(Power control) registers. + struct { +Object *cr; // 0x0(Power control register) +Object *csr; // 0x4(Power control/status register) +} reg; + + struct { +// CR(Power control register) bitfields. + struct { +Object *lpds; // [0:0] Low-power deep sleepObject *pdds; // [1:1] Power down deepsleepObject *cwuf; // [2:2] Clear wakeup flagObject *csbf; // [3:3] Clear standby flagObject *pvde; // [4:4] Power voltage detector enableObject *pls; // [5:7] PVD level selectionObject *dbp; // [8:8] Disable backup domain write protection} cr; +// CSR(Power control/status register) bitfields. + struct { +Object *wuf; // [0:0] Wakeup flagObject *sbf; // [1:1] Standby flagObject *pvdo; // [2:2] PVD outputObject *vrefintrdy; // [3:3] VREFINT reference voltage readyObject *ewup1; // [8:8] Enable WKUP pin 1Object *ewup2; // [9:9] Enable WKUP pin 2Object *ewup3; // [10:10] Enable WKUP pin 3Object *ewup4; // [11:11] Enable WKUP pin 4Object *ewup5; // [12:12] Enable WKUP pin 5Object *ewup6; // [13:13] Enable WKUP pin 6Object *ewup7; // [14:14] Enable WKUP pin 7Object *ewup8; // [15:15] Enable WKUP pin 8} csr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32PWRState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_PWR_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/rcc.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/rcc.c new file mode 100644 index 0000000000..5ad27f2793 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/rcc.c @@ -0,0 +1,405 @@ +/* + * STM32- RCC(Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_rcc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.cfgr= cm_object_get_child_by_name(obj, "CFGR"); +state->u.f0.reg.cir= cm_object_get_child_by_name(obj, "CIR"); +state->u.f0.reg.apb2rstr= cm_object_get_child_by_name(obj, "APB2RSTR"); +state->u.f0.reg.apb1rstr= cm_object_get_child_by_name(obj, "APB1RSTR"); +state->u.f0.reg.ahbenr= cm_object_get_child_by_name(obj, "AHBENR"); +state->u.f0.reg.apb2enr= cm_object_get_child_by_name(obj, "APB2ENR"); +state->u.f0.reg.apb1enr= cm_object_get_child_by_name(obj, "APB1ENR"); +state->u.f0.reg.bdcr= cm_object_get_child_by_name(obj, "BDCR"); +state->u.f0.reg.csr= cm_object_get_child_by_name(obj, "CSR"); +state->u.f0.reg.ahbrstr= cm_object_get_child_by_name(obj, "AHBRSTR"); +state->u.f0.reg.cfgr2= cm_object_get_child_by_name(obj, "CFGR2"); +state->u.f0.reg.cfgr3= cm_object_get_child_by_name(obj, "CFGR3"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +// CRbitfields. +state->u.f0.fld.cr.hsion= cm_object_get_child_by_name(state->u.f0.reg.cr, "HSION"); +state->u.f0.fld.cr.hsirdy= cm_object_get_child_by_name(state->u.f0.reg.cr, "HSIRDY"); +state->u.f0.fld.cr.hsitrim= cm_object_get_child_by_name(state->u.f0.reg.cr, "HSITRIM"); +state->u.f0.fld.cr.hsical= cm_object_get_child_by_name(state->u.f0.reg.cr, "HSICAL"); +state->u.f0.fld.cr.hseon= cm_object_get_child_by_name(state->u.f0.reg.cr, "HSEON"); +state->u.f0.fld.cr.hserdy= cm_object_get_child_by_name(state->u.f0.reg.cr, "HSERDY"); +state->u.f0.fld.cr.hsebyp= cm_object_get_child_by_name(state->u.f0.reg.cr, "HSEBYP"); +state->u.f0.fld.cr.csson= cm_object_get_child_by_name(state->u.f0.reg.cr, "CSSON"); +state->u.f0.fld.cr.pllon= cm_object_get_child_by_name(state->u.f0.reg.cr, "PLLON"); +state->u.f0.fld.cr.pllrdy= cm_object_get_child_by_name(state->u.f0.reg.cr, "PLLRDY"); +// CFGRbitfields. +state->u.f0.fld.cfgr.sw= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SW"); +state->u.f0.fld.cfgr.sws= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "SWS"); +state->u.f0.fld.cfgr.hpre= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "HPRE"); +state->u.f0.fld.cfgr.ppre= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PPRE"); +state->u.f0.fld.cfgr.adcpre= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "ADCPRE"); +state->u.f0.fld.cfgr.pllsrc= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLSRC"); +state->u.f0.fld.cfgr.pllxtpre= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLXTPRE"); +state->u.f0.fld.cfgr.pllmul= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLMUL"); +state->u.f0.fld.cfgr.mco= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "MCO"); +state->u.f0.fld.cfgr.mcopre= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "MCOPRE"); +state->u.f0.fld.cfgr.pllnodiv= cm_object_get_child_by_name(state->u.f0.reg.cfgr, "PLLNODIV"); +// CIRbitfields. +state->u.f0.fld.cir.lsirdyf= cm_object_get_child_by_name(state->u.f0.reg.cir, "LSIRDYF"); +state->u.f0.fld.cir.lserdyf= cm_object_get_child_by_name(state->u.f0.reg.cir, "LSERDYF"); +state->u.f0.fld.cir.hsirdyf= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSIRDYF"); +state->u.f0.fld.cir.hserdyf= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSERDYF"); +state->u.f0.fld.cir.pllrdyf= cm_object_get_child_by_name(state->u.f0.reg.cir, "PLLRDYF"); +state->u.f0.fld.cir.hsi14rdyf= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI14RDYF"); +state->u.f0.fld.cir.hsi48rdyf= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI48RDYF"); +state->u.f0.fld.cir.cssf= cm_object_get_child_by_name(state->u.f0.reg.cir, "CSSF"); +state->u.f0.fld.cir.lsirdyie= cm_object_get_child_by_name(state->u.f0.reg.cir, "LSIRDYIE"); +state->u.f0.fld.cir.lserdyie= cm_object_get_child_by_name(state->u.f0.reg.cir, "LSERDYIE"); +state->u.f0.fld.cir.hsirdyie= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSIRDYIE"); +state->u.f0.fld.cir.hserdyie= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSERDYIE"); +state->u.f0.fld.cir.pllrdyie= cm_object_get_child_by_name(state->u.f0.reg.cir, "PLLRDYIE"); +state->u.f0.fld.cir.hsi14rdye= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI14RDYE"); +state->u.f0.fld.cir.hsi48rdyie= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI48RDYIE"); +state->u.f0.fld.cir.lsirdyc= cm_object_get_child_by_name(state->u.f0.reg.cir, "LSIRDYC"); +state->u.f0.fld.cir.lserdyc= cm_object_get_child_by_name(state->u.f0.reg.cir, "LSERDYC"); +state->u.f0.fld.cir.hsirdyc= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSIRDYC"); +state->u.f0.fld.cir.hserdyc= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSERDYC"); +state->u.f0.fld.cir.pllrdyc= cm_object_get_child_by_name(state->u.f0.reg.cir, "PLLRDYC"); +state->u.f0.fld.cir.hsi14rdyc= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI14RDYC"); +state->u.f0.fld.cir.hsi48rdyc= cm_object_get_child_by_name(state->u.f0.reg.cir, "HSI48RDYC"); +state->u.f0.fld.cir.cssc= cm_object_get_child_by_name(state->u.f0.reg.cir, "CSSC"); +// APB2RSTRbitfields. +state->u.f0.fld.apb2rstr.syscfgrst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "SYSCFGRST"); +state->u.f0.fld.apb2rstr.adcrst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "ADCRST"); +state->u.f0.fld.apb2rstr.tim1rst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM1RST"); +state->u.f0.fld.apb2rstr.spi1rst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "SPI1RST"); +state->u.f0.fld.apb2rstr.usart1rst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "USART1RST"); +state->u.f0.fld.apb2rstr.tim15rst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM15RST"); +state->u.f0.fld.apb2rstr.tim16rst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM16RST"); +state->u.f0.fld.apb2rstr.tim17rst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "TIM17RST"); +state->u.f0.fld.apb2rstr.dbgmcurst= cm_object_get_child_by_name(state->u.f0.reg.apb2rstr, "DBGMCURST"); +// APB1RSTRbitfields. +state->u.f0.fld.apb1rstr.tim2rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM2RST"); +state->u.f0.fld.apb1rstr.tim3rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM3RST"); +state->u.f0.fld.apb1rstr.tim6rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM6RST"); +state->u.f0.fld.apb1rstr.tim7rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM7RST"); +state->u.f0.fld.apb1rstr.tim14rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "TIM14RST"); +state->u.f0.fld.apb1rstr.wwdgrst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "WWDGRST"); +state->u.f0.fld.apb1rstr.spi2rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "SPI2RST"); +state->u.f0.fld.apb1rstr.usart2rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USART2RST"); +state->u.f0.fld.apb1rstr.usart3rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USART3RST"); +state->u.f0.fld.apb1rstr.usart4rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USART4RST"); +state->u.f0.fld.apb1rstr.i2c1rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "I2C1RST"); +state->u.f0.fld.apb1rstr.i2c2rst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "I2C2RST"); +state->u.f0.fld.apb1rstr.usbrst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "USBRST"); +state->u.f0.fld.apb1rstr.canrst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "CANRST"); +state->u.f0.fld.apb1rstr.crsrst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "CRSRST"); +state->u.f0.fld.apb1rstr.pwrrst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "PWRRST"); +state->u.f0.fld.apb1rstr.dacrst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "DACRST"); +state->u.f0.fld.apb1rstr.cecrst= cm_object_get_child_by_name(state->u.f0.reg.apb1rstr, "CECRST"); +// AHBENRbitfields. +state->u.f0.fld.ahbenr.dma1en= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "DMA1EN"); +state->u.f0.fld.ahbenr.sramen= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "SRAMEN"); +state->u.f0.fld.ahbenr.flitfen= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "FLITFEN"); +state->u.f0.fld.ahbenr.crcen= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "CRCEN"); +state->u.f0.fld.ahbenr.iopaen= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPAEN"); +state->u.f0.fld.ahbenr.iopben= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPBEN"); +state->u.f0.fld.ahbenr.iopcen= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPCEN"); +state->u.f0.fld.ahbenr.iopden= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPDEN"); +state->u.f0.fld.ahbenr.iopfen= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "IOPFEN"); +state->u.f0.fld.ahbenr.tscen= cm_object_get_child_by_name(state->u.f0.reg.ahbenr, "TSCEN"); +// APB2ENRbitfields. +state->u.f0.fld.apb2enr.syscfgen= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "SYSCFGEN"); +state->u.f0.fld.apb2enr.adcen= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "ADCEN"); +state->u.f0.fld.apb2enr.tim1en= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM1EN"); +state->u.f0.fld.apb2enr.spi1en= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "SPI1EN"); +state->u.f0.fld.apb2enr.usart1en= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "USART1EN"); +state->u.f0.fld.apb2enr.tim15en= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM15EN"); +state->u.f0.fld.apb2enr.tim16en= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM16EN"); +state->u.f0.fld.apb2enr.tim17en= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "TIM17EN"); +state->u.f0.fld.apb2enr.dbgmcuen= cm_object_get_child_by_name(state->u.f0.reg.apb2enr, "DBGMCUEN"); +// APB1ENRbitfields. +state->u.f0.fld.apb1enr.tim2en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM2EN"); +state->u.f0.fld.apb1enr.tim3en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM3EN"); +state->u.f0.fld.apb1enr.tim6en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM6EN"); +state->u.f0.fld.apb1enr.tim7en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM7EN"); +state->u.f0.fld.apb1enr.tim14en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "TIM14EN"); +state->u.f0.fld.apb1enr.wwdgen= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "WWDGEN"); +state->u.f0.fld.apb1enr.spi2en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "SPI2EN"); +state->u.f0.fld.apb1enr.usart2en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USART2EN"); +state->u.f0.fld.apb1enr.usart3en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USART3EN"); +state->u.f0.fld.apb1enr.usart4en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USART4EN"); +state->u.f0.fld.apb1enr.i2c1en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "I2C1EN"); +state->u.f0.fld.apb1enr.i2c2en= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "I2C2EN"); +state->u.f0.fld.apb1enr.usbrst= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "USBRST"); +state->u.f0.fld.apb1enr.canen= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "CANEN"); +state->u.f0.fld.apb1enr.crsen= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "CRSEN"); +state->u.f0.fld.apb1enr.pwren= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "PWREN"); +state->u.f0.fld.apb1enr.dacen= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "DACEN"); +state->u.f0.fld.apb1enr.cecen= cm_object_get_child_by_name(state->u.f0.reg.apb1enr, "CECEN"); +// BDCRbitfields. +state->u.f0.fld.bdcr.lseon= cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSEON"); +state->u.f0.fld.bdcr.lserdy= cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSERDY"); +state->u.f0.fld.bdcr.lsebyp= cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSEBYP"); +state->u.f0.fld.bdcr.lsedrv= cm_object_get_child_by_name(state->u.f0.reg.bdcr, "LSEDRV"); +state->u.f0.fld.bdcr.rtcsel= cm_object_get_child_by_name(state->u.f0.reg.bdcr, "RTCSEL"); +state->u.f0.fld.bdcr.rtcen= cm_object_get_child_by_name(state->u.f0.reg.bdcr, "RTCEN"); +state->u.f0.fld.bdcr.bdrst= cm_object_get_child_by_name(state->u.f0.reg.bdcr, "BDRST"); +// CSRbitfields. +state->u.f0.fld.csr.lsion= cm_object_get_child_by_name(state->u.f0.reg.csr, "LSION"); +state->u.f0.fld.csr.lsirdy= cm_object_get_child_by_name(state->u.f0.reg.csr, "LSIRDY"); +state->u.f0.fld.csr.rmvf= cm_object_get_child_by_name(state->u.f0.reg.csr, "RMVF"); +state->u.f0.fld.csr.oblrstf= cm_object_get_child_by_name(state->u.f0.reg.csr, "OBLRSTF"); +state->u.f0.fld.csr.pinrstf= cm_object_get_child_by_name(state->u.f0.reg.csr, "PINRSTF"); +state->u.f0.fld.csr.porrstf= cm_object_get_child_by_name(state->u.f0.reg.csr, "PORRSTF"); +state->u.f0.fld.csr.sftrstf= cm_object_get_child_by_name(state->u.f0.reg.csr, "SFTRSTF"); +state->u.f0.fld.csr.iwdgrstf= cm_object_get_child_by_name(state->u.f0.reg.csr, "IWDGRSTF"); +state->u.f0.fld.csr.wwdgrstf= cm_object_get_child_by_name(state->u.f0.reg.csr, "WWDGRSTF"); +state->u.f0.fld.csr.lpwrrstf= cm_object_get_child_by_name(state->u.f0.reg.csr, "LPWRRSTF"); +// AHBRSTRbitfields. +state->u.f0.fld.ahbrstr.ioparst= cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPARST"); +state->u.f0.fld.ahbrstr.iopbrst= cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPBRST"); +state->u.f0.fld.ahbrstr.iopcrst= cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPCRST"); +state->u.f0.fld.ahbrstr.iopdrst= cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPDRST"); +state->u.f0.fld.ahbrstr.iopfrst= cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "IOPFRST"); +state->u.f0.fld.ahbrstr.tscrst= cm_object_get_child_by_name(state->u.f0.reg.ahbrstr, "TSCRST"); +// CFGR2bitfields. +state->u.f0.fld.cfgr2.prediv= cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "PREDIV"); +// CFGR3bitfields. +state->u.f0.fld.cfgr3.usart1sw= cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "USART1SW"); +state->u.f0.fld.cfgr3.i2c1sw= cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "I2C1SW"); +state->u.f0.fld.cfgr3.cecsw= cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "CECSW"); +state->u.f0.fld.cfgr3.usbsw= cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "USBSW"); +state->u.f0.fld.cfgr3.adcsw= cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "ADCSW"); +state->u.f0.fld.cfgr3.usart2sw= cm_object_get_child_by_name(state->u.f0.reg.cfgr3, "USART2SW"); +// CR2bitfields. +state->u.f0.fld.cr2.hsi14on= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14ON"); +state->u.f0.fld.cr2.hsi14rdy= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14RDY"); +state->u.f0.fld.cr2.hsi14dis= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14DIS"); +state->u.f0.fld.cr2.hsi14trim= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14TRIM"); +state->u.f0.fld.cr2.hsi14cal= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI14CAL"); +state->u.f0.fld.cr2.hsi48on= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI48ON"); +state->u.f0.fld.cr2.hsi48rdy= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI48RDY"); +state->u.f0.fld.cr2.hsi48cal= cm_object_get_child_by_name(state->u.f0.reg.cr2, "HSI48CAL"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rcc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rcc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rcc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rcc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rcc_is_enabled(Object *obj) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rcc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RCCState *state = STM32_RCC_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rcc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RCC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RCCState *state = STM32_RCC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RCC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_rcc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rcc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_rcc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rcc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_rcc_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RCCEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rcc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RCC); +} + +static void stm32_rcc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rcc_reset_callback; + dc->realize = stm32_rcc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rcc_is_enabled; +} + +static const TypeInfo stm32_rcc_type_info = { + .name = TYPE_STM32_RCC, + .parent = TYPE_STM32_RCC_PARENT, + .instance_init = stm32_rcc_instance_init_callback, + .instance_size = sizeof(STM32RCCState), + .class_init = stm32_rcc_class_init_callback, + .class_size = sizeof(STM32RCCClass) }; + +static void stm32_rcc_register_types(void) +{ + type_register_static(&stm32_rcc_type_info); +} + +type_init(stm32_rcc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/rcc.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/rcc.h new file mode 100644 index 0000000000..1d033f394b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/rcc.h @@ -0,0 +1,153 @@ +/* + * STM32- RCC(Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RCC_H_ +#define STM32_RCC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RCCDEVICE_PATH_STM32"RCC" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RCCTYPE_STM32_PREFIX "rcc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RCC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RCCParentClass; +typedef PeripheralState STM32RCCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RCCClass, (obj), TYPE_STM32_RCC) +#define STM32_RCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RCCClass, (klass), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentClass parent_class; + // public: + + // None, so far. +} STM32RCCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RCC_STATE(obj) \ + OBJECT_CHECK(STM32RCCState, (obj), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0RCC(Reset and clock control) registers. + struct { +Object *cr; // 0x0(Clock control register) +Object *cfgr; // 0x4(Clock configuration register (RCC_CFGR)) +Object *cir; // 0x8(Clock interrupt register (RCC_CIR)) +Object *apb2rstr; // 0xC(APB2 peripheral reset register (RCC_APB2RSTR)) +Object *apb1rstr; // 0x10(APB1 peripheral reset register (RCC_APB1RSTR)) +Object *ahbenr; // 0x14(AHB Peripheral Clock enable register (RCC_AHBENR)) +Object *apb2enr; // 0x18(APB2 peripheral clock enable register (RCC_APB2ENR)) +Object *apb1enr; // 0x1C(APB1 peripheral clock enable register (RCC_APB1ENR)) +Object *bdcr; // 0x20(Backup domain control register (RCC_BDCR)) +Object *csr; // 0x24(Control/status register (RCC_CSR)) +Object *ahbrstr; // 0x28(AHB peripheral reset register) +Object *cfgr2; // 0x2C(Clock configuration register 2) +Object *cfgr3; // 0x30(Clock configuration register 3) +Object *cr2; // 0x34(Clock control register 2) +} reg; + + struct { +// CR(Clock control register) bitfields. + struct { +Object *hsion; // [0:0] Internal High Speed clock enableObject *hsirdy; // [1:1] Internal High Speed clock ready flagObject *hsitrim; // [3:7] Internal High Speed clock trimmingObject *hsical; // [8:15] Internal High Speed clock CalibrationObject *hseon; // [16:16] External High Speed clock enableObject *hserdy; // [17:17] External High Speed clock ready flagObject *hsebyp; // [18:18] External High Speed clock BypassObject *csson; // [19:19] Clock Security System enableObject *pllon; // [24:24] PLL enableObject *pllrdy; // [25:25] PLL clock ready flag} cr; +// CFGR(Clock configuration register (RCC_CFGR)) bitfields. + struct { +Object *sw; // [0:1] System clock SwitchObject *sws; // [2:3] System Clock Switch StatusObject *hpre; // [4:7] AHB prescalerObject *ppre; // [8:10] APB Low speed prescaler (APB1)Object *adcpre; // [14:14] ADC prescalerObject *pllsrc; // [15:16] PLL input clock sourceObject *pllxtpre; // [17:17] HSE divider for PLL entryObject *pllmul; // [18:21] PLL Multiplication FactorObject *mco; // [24:26] Microcontroller clock outputObject *mcopre; // [28:30] Microcontroller Clock Output PrescalerObject *pllnodiv; // [31:31] PLL clock not divided for MCO} cfgr; +// CIR(Clock interrupt register (RCC_CIR)) bitfields. + struct { +Object *lsirdyf; // [0:0] LSI Ready Interrupt flagObject *lserdyf; // [1:1] LSE Ready Interrupt flagObject *hsirdyf; // [2:2] HSI Ready Interrupt flagObject *hserdyf; // [3:3] HSE Ready Interrupt flagObject *pllrdyf; // [4:4] PLL Ready Interrupt flagObject *hsi14rdyf; // [5:5] HSI14 ready interrupt flagObject *hsi48rdyf; // [6:6] HSI48 ready interrupt flagObject *cssf; // [7:7] Clock Security System Interrupt flagObject *lsirdyie; // [8:8] LSI Ready Interrupt EnableObject *lserdyie; // [9:9] LSE Ready Interrupt EnableObject *hsirdyie; // [10:10] HSI Ready Interrupt EnableObject *hserdyie; // [11:11] HSE Ready Interrupt EnableObject *pllrdyie; // [12:12] PLL Ready Interrupt EnableObject *hsi14rdye; // [13:13] HSI14 ready interrupt enableObject *hsi48rdyie; // [14:14] HSI48 ready interrupt enableObject *lsirdyc; // [16:16] LSI Ready Interrupt ClearObject *lserdyc; // [17:17] LSE Ready Interrupt ClearObject *hsirdyc; // [18:18] HSI Ready Interrupt ClearObject *hserdyc; // [19:19] HSE Ready Interrupt ClearObject *pllrdyc; // [20:20] PLL Ready Interrupt ClearObject *hsi14rdyc; // [21:21] HSI 14 MHz Ready Interrupt ClearObject *hsi48rdyc; // [22:22] HSI48 Ready Interrupt ClearObject *cssc; // [23:23] Clock security system interrupt clear} cir; +// APB2RSTR(APB2 peripheral reset register (RCC_APB2RSTR)) bitfields. + struct { +Object *syscfgrst; // [0:0] SYSCFG and COMP resetObject *adcrst; // [9:9] ADC interface resetObject *tim1rst; // [11:11] TIM1 timer resetObject *spi1rst; // [12:12] SPI 1 resetObject *usart1rst; // [14:14] USART1 resetObject *tim15rst; // [16:16] TIM15 timer resetObject *tim16rst; // [17:17] TIM16 timer resetObject *tim17rst; // [18:18] TIM17 timer resetObject *dbgmcurst; // [22:22] Debug MCU reset} apb2rstr; +// APB1RSTR(APB1 peripheral reset register (RCC_APB1RSTR)) bitfields. + struct { +Object *tim2rst; // [0:0] Timer 2 resetObject *tim3rst; // [1:1] Timer 3 resetObject *tim6rst; // [4:4] Timer 6 resetObject *tim7rst; // [5:5] TIM7 timer resetObject *tim14rst; // [8:8] Timer 14 resetObject *wwdgrst; // [11:11] Window watchdog resetObject *spi2rst; // [14:14] SPI2 resetObject *usart2rst; // [17:17] USART 2 resetObject *usart3rst; // [18:18] USART3 resetObject *usart4rst; // [19:19] USART4 resetObject *i2c1rst; // [21:21] I2C1 resetObject *i2c2rst; // [22:22] I2C2 resetObject *usbrst; // [23:23] USB interface resetObject *canrst; // [25:25] CAN interface resetObject *crsrst; // [27:27] Clock Recovery System interface resetObject *pwrrst; // [28:28] Power interface resetObject *dacrst; // [29:29] DAC interface resetObject *cecrst; // [30:30] HDMI CEC reset} apb1rstr; +// AHBENR(AHB Peripheral Clock enable register (RCC_AHBENR)) bitfields. + struct { +Object *dma1en; // [0:0] DMA1 clock enableObject *sramen; // [2:2] SRAM interface clock enableObject *flitfen; // [4:4] FLITF clock enableObject *crcen; // [6:6] CRC clock enableObject *iopaen; // [17:17] I/O port A clock enableObject *iopben; // [18:18] I/O port B clock enableObject *iopcen; // [19:19] I/O port C clock enableObject *iopden; // [20:20] I/O port D clock enableObject *iopfen; // [22:22] I/O port F clock enableObject *tscen; // [24:24] Touch sensing controller clock enable} ahbenr; +// APB2ENR(APB2 peripheral clock enable register (RCC_APB2ENR)) bitfields. + struct { +Object *syscfgen; // [0:0] SYSCFG clock enableObject *adcen; // [9:9] ADC 1 interface clock enableObject *tim1en; // [11:11] TIM1 Timer clock enableObject *spi1en; // [12:12] SPI 1 clock enableObject *usart1en; // [14:14] USART1 clock enableObject *tim15en; // [16:16] TIM15 timer clock enableObject *tim16en; // [17:17] TIM16 timer clock enableObject *tim17en; // [18:18] TIM17 timer clock enableObject *dbgmcuen; // [22:22] MCU debug module clock enable} apb2enr; +// APB1ENR(APB1 peripheral clock enable register (RCC_APB1ENR)) bitfields. + struct { +Object *tim2en; // [0:0] Timer 2 clock enableObject *tim3en; // [1:1] Timer 3 clock enableObject *tim6en; // [4:4] Timer 6 clock enableObject *tim7en; // [5:5] TIM7 timer clock enableObject *tim14en; // [8:8] Timer 14 clock enableObject *wwdgen; // [11:11] Window watchdog clock enableObject *spi2en; // [14:14] SPI 2 clock enableObject *usart2en; // [17:17] USART 2 clock enableObject *usart3en; // [18:18] USART3 clock enableObject *usart4en; // [19:19] USART4 clock enableObject *i2c1en; // [21:21] I2C 1 clock enableObject *i2c2en; // [22:22] I2C 2 clock enableObject *usbrst; // [23:23] USB interface clock enableObject *canen; // [25:25] CAN interface clock enableObject *crsen; // [27:27] Clock Recovery System interface clock enableObject *pwren; // [28:28] Power interface clock enableObject *dacen; // [29:29] DAC interface clock enableObject *cecen; // [30:30] HDMI CEC interface clock enable} apb1enr; +// BDCR(Backup domain control register (RCC_BDCR)) bitfields. + struct { +Object *lseon; // [0:0] External Low Speed oscillator enableObject *lserdy; // [1:1] External Low Speed oscillator readyObject *lsebyp; // [2:2] External Low Speed oscillator bypassObject *lsedrv; // [3:4] LSE oscillator drive capabilityObject *rtcsel; // [8:9] RTC clock source selectionObject *rtcen; // [15:15] RTC clock enableObject *bdrst; // [16:16] Backup domain software reset} bdcr; +// CSR(Control/status register (RCC_CSR)) bitfields. + struct { +Object *lsion; // [0:0] Internal low speed oscillator enableObject *lsirdy; // [1:1] Internal low speed oscillator readyObject *rmvf; // [24:24] Remove reset flagObject *oblrstf; // [25:25] Option byte loader reset flagObject *pinrstf; // [26:26] PIN reset flagObject *porrstf; // [27:27] POR/PDR reset flagObject *sftrstf; // [28:28] Software reset flagObject *iwdgrstf; // [29:29] Independent watchdog reset flagObject *wwdgrstf; // [30:30] Window watchdog reset flagObject *lpwrrstf; // [31:31] Low-power reset flag} csr; +// AHBRSTR(AHB peripheral reset register) bitfields. + struct { +Object *ioparst; // [17:17] I/O port A resetObject *iopbrst; // [18:18] I/O port B resetObject *iopcrst; // [19:19] I/O port C resetObject *iopdrst; // [20:20] I/O port D resetObject *iopfrst; // [22:22] I/O port F resetObject *tscrst; // [24:24] Touch sensing controller reset} ahbrstr; +// CFGR2(Clock configuration register 2) bitfields. + struct { +Object *prediv; // [0:3] PREDIV division factor} cfgr2; +// CFGR3(Clock configuration register 3) bitfields. + struct { +Object *usart1sw; // [0:1] USART1 clock source selectionObject *i2c1sw; // [4:4] I2C1 clock source selectionObject *cecsw; // [6:6] HDMI CEC clock source selectionObject *usbsw; // [7:7] USB clock source selectionObject *adcsw; // [8:8] ADC clock source selectionObject *usart2sw; // [16:17] USART2 clock source selection} cfgr3; +// CR2(Clock control register 2) bitfields. + struct { +Object *hsi14on; // [0:0] HSI14 clock enableObject *hsi14rdy; // [1:1] HR14 clock ready flagObject *hsi14dis; // [2:2] HSI14 clock request from ADC disableObject *hsi14trim; // [3:7] HSI14 clock trimmingObject *hsi14cal; // [8:15] HSI14 clock calibrationObject *hsi48on; // [16:16] HSI48 clock enableObject *hsi48rdy; // [17:17] HSI48 clock ready flagObject *hsi48cal; // [24:24] HSI48 factory clock calibration} cr2; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RCCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RCC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/rtc.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/rtc.c new file mode 100644 index 0000000000..1059b7bd43 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/rtc.c @@ -0,0 +1,372 @@ +/* + * STM32- RTC(Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_rtc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.tr= cm_object_get_child_by_name(obj, "TR"); +state->u.f0.reg.dr= cm_object_get_child_by_name(obj, "DR"); +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.prer= cm_object_get_child_by_name(obj, "PRER"); +state->u.f0.reg.alrmar= cm_object_get_child_by_name(obj, "ALRMAR"); +state->u.f0.reg.wpr= cm_object_get_child_by_name(obj, "WPR"); +state->u.f0.reg.ssr= cm_object_get_child_by_name(obj, "SSR"); +state->u.f0.reg.shiftr= cm_object_get_child_by_name(obj, "SHIFTR"); +state->u.f0.reg.tstr= cm_object_get_child_by_name(obj, "TSTR"); +state->u.f0.reg.tsdr= cm_object_get_child_by_name(obj, "TSDR"); +state->u.f0.reg.tsssr= cm_object_get_child_by_name(obj, "TSSSR"); +state->u.f0.reg.calr= cm_object_get_child_by_name(obj, "CALR"); +state->u.f0.reg.tafcr= cm_object_get_child_by_name(obj, "TAFCR"); +state->u.f0.reg.alrmassr= cm_object_get_child_by_name(obj, "ALRMASSR"); +state->u.f0.reg.bkp0r= cm_object_get_child_by_name(obj, "BKP0R"); +state->u.f0.reg.bkp1r= cm_object_get_child_by_name(obj, "BKP1R"); +state->u.f0.reg.bkp2r= cm_object_get_child_by_name(obj, "BKP2R"); +state->u.f0.reg.bkp3r= cm_object_get_child_by_name(obj, "BKP3R"); +state->u.f0.reg.bkp4r= cm_object_get_child_by_name(obj, "BKP4R"); +// TRbitfields. +state->u.f0.fld.tr.su= cm_object_get_child_by_name(state->u.f0.reg.tr, "SU"); +state->u.f0.fld.tr.st= cm_object_get_child_by_name(state->u.f0.reg.tr, "ST"); +state->u.f0.fld.tr.mnu= cm_object_get_child_by_name(state->u.f0.reg.tr, "MNU"); +state->u.f0.fld.tr.mnt= cm_object_get_child_by_name(state->u.f0.reg.tr, "MNT"); +state->u.f0.fld.tr.hu= cm_object_get_child_by_name(state->u.f0.reg.tr, "HU"); +state->u.f0.fld.tr.ht= cm_object_get_child_by_name(state->u.f0.reg.tr, "HT"); +state->u.f0.fld.tr.pm= cm_object_get_child_by_name(state->u.f0.reg.tr, "PM"); +// DRbitfields. +state->u.f0.fld.dr.du= cm_object_get_child_by_name(state->u.f0.reg.dr, "DU"); +state->u.f0.fld.dr.dt= cm_object_get_child_by_name(state->u.f0.reg.dr, "DT"); +state->u.f0.fld.dr.mu= cm_object_get_child_by_name(state->u.f0.reg.dr, "MU"); +state->u.f0.fld.dr.mt= cm_object_get_child_by_name(state->u.f0.reg.dr, "MT"); +state->u.f0.fld.dr.wdu= cm_object_get_child_by_name(state->u.f0.reg.dr, "WDU"); +state->u.f0.fld.dr.yu= cm_object_get_child_by_name(state->u.f0.reg.dr, "YU"); +state->u.f0.fld.dr.yt= cm_object_get_child_by_name(state->u.f0.reg.dr, "YT"); +// CRbitfields. +state->u.f0.fld.cr.tsedge= cm_object_get_child_by_name(state->u.f0.reg.cr, "TSEDGE"); +state->u.f0.fld.cr.refckon= cm_object_get_child_by_name(state->u.f0.reg.cr, "REFCKON"); +state->u.f0.fld.cr.bypshad= cm_object_get_child_by_name(state->u.f0.reg.cr, "BYPSHAD"); +state->u.f0.fld.cr.fmt= cm_object_get_child_by_name(state->u.f0.reg.cr, "FMT"); +state->u.f0.fld.cr.alrae= cm_object_get_child_by_name(state->u.f0.reg.cr, "ALRAE"); +state->u.f0.fld.cr.tse= cm_object_get_child_by_name(state->u.f0.reg.cr, "TSE"); +state->u.f0.fld.cr.alraie= cm_object_get_child_by_name(state->u.f0.reg.cr, "ALRAIE"); +state->u.f0.fld.cr.tsie= cm_object_get_child_by_name(state->u.f0.reg.cr, "TSIE"); +state->u.f0.fld.cr.add1h= cm_object_get_child_by_name(state->u.f0.reg.cr, "ADD1H"); +state->u.f0.fld.cr.sub1h= cm_object_get_child_by_name(state->u.f0.reg.cr, "SUB1H"); +state->u.f0.fld.cr.bkp= cm_object_get_child_by_name(state->u.f0.reg.cr, "BKP"); +state->u.f0.fld.cr.cosel= cm_object_get_child_by_name(state->u.f0.reg.cr, "COSEL"); +state->u.f0.fld.cr.pol= cm_object_get_child_by_name(state->u.f0.reg.cr, "POL"); +state->u.f0.fld.cr.osel= cm_object_get_child_by_name(state->u.f0.reg.cr, "OSEL"); +state->u.f0.fld.cr.coe= cm_object_get_child_by_name(state->u.f0.reg.cr, "COE"); +// ISRbitfields. +state->u.f0.fld.isr.alrawf= cm_object_get_child_by_name(state->u.f0.reg.isr, "ALRAWF"); +state->u.f0.fld.isr.shpf= cm_object_get_child_by_name(state->u.f0.reg.isr, "SHPF"); +state->u.f0.fld.isr.inits= cm_object_get_child_by_name(state->u.f0.reg.isr, "INITS"); +state->u.f0.fld.isr.rsf= cm_object_get_child_by_name(state->u.f0.reg.isr, "RSF"); +state->u.f0.fld.isr.initf= cm_object_get_child_by_name(state->u.f0.reg.isr, "INITF"); +state->u.f0.fld.isr.init= cm_object_get_child_by_name(state->u.f0.reg.isr, "INIT"); +state->u.f0.fld.isr.alraf= cm_object_get_child_by_name(state->u.f0.reg.isr, "ALRAF"); +state->u.f0.fld.isr.tsf= cm_object_get_child_by_name(state->u.f0.reg.isr, "TSF"); +state->u.f0.fld.isr.tsovf= cm_object_get_child_by_name(state->u.f0.reg.isr, "TSOVF"); +state->u.f0.fld.isr.tamp1f= cm_object_get_child_by_name(state->u.f0.reg.isr, "TAMP1F"); +state->u.f0.fld.isr.tamp2f= cm_object_get_child_by_name(state->u.f0.reg.isr, "TAMP2F"); +state->u.f0.fld.isr.recalpf= cm_object_get_child_by_name(state->u.f0.reg.isr, "RECALPF"); +// PRERbitfields. +state->u.f0.fld.prer.prediv_s= cm_object_get_child_by_name(state->u.f0.reg.prer, "PREDIV_S"); +state->u.f0.fld.prer.prediv_a= cm_object_get_child_by_name(state->u.f0.reg.prer, "PREDIV_A"); +// ALRMARbitfields. +state->u.f0.fld.alrmar.su= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "SU"); +state->u.f0.fld.alrmar.st= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "ST"); +state->u.f0.fld.alrmar.msk1= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK1"); +state->u.f0.fld.alrmar.mnu= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MNU"); +state->u.f0.fld.alrmar.mnt= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MNT"); +state->u.f0.fld.alrmar.msk2= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK2"); +state->u.f0.fld.alrmar.hu= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "HU"); +state->u.f0.fld.alrmar.ht= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "HT"); +state->u.f0.fld.alrmar.pm= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "PM"); +state->u.f0.fld.alrmar.msk3= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK3"); +state->u.f0.fld.alrmar.du= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "DU"); +state->u.f0.fld.alrmar.dt= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "DT"); +state->u.f0.fld.alrmar.wdsel= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "WDSEL"); +state->u.f0.fld.alrmar.msk4= cm_object_get_child_by_name(state->u.f0.reg.alrmar, "MSK4"); +// WPRbitfields. +state->u.f0.fld.wpr.key= cm_object_get_child_by_name(state->u.f0.reg.wpr, "KEY"); +// SSRbitfields. +state->u.f0.fld.ssr.ss= cm_object_get_child_by_name(state->u.f0.reg.ssr, "SS"); +// SHIFTRbitfields. +state->u.f0.fld.shiftr.subfs= cm_object_get_child_by_name(state->u.f0.reg.shiftr, "SUBFS"); +state->u.f0.fld.shiftr.add1s= cm_object_get_child_by_name(state->u.f0.reg.shiftr, "ADD1S"); +// TSTRbitfields. +state->u.f0.fld.tstr.su= cm_object_get_child_by_name(state->u.f0.reg.tstr, "SU"); +state->u.f0.fld.tstr.st= cm_object_get_child_by_name(state->u.f0.reg.tstr, "ST"); +state->u.f0.fld.tstr.mnu= cm_object_get_child_by_name(state->u.f0.reg.tstr, "MNU"); +state->u.f0.fld.tstr.mnt= cm_object_get_child_by_name(state->u.f0.reg.tstr, "MNT"); +state->u.f0.fld.tstr.hu= cm_object_get_child_by_name(state->u.f0.reg.tstr, "HU"); +state->u.f0.fld.tstr.ht= cm_object_get_child_by_name(state->u.f0.reg.tstr, "HT"); +state->u.f0.fld.tstr.pm= cm_object_get_child_by_name(state->u.f0.reg.tstr, "PM"); +// TSDRbitfields. +state->u.f0.fld.tsdr.du= cm_object_get_child_by_name(state->u.f0.reg.tsdr, "DU"); +state->u.f0.fld.tsdr.dt= cm_object_get_child_by_name(state->u.f0.reg.tsdr, "DT"); +state->u.f0.fld.tsdr.mu= cm_object_get_child_by_name(state->u.f0.reg.tsdr, "MU"); +state->u.f0.fld.tsdr.mt= cm_object_get_child_by_name(state->u.f0.reg.tsdr, "MT"); +state->u.f0.fld.tsdr.wdu= cm_object_get_child_by_name(state->u.f0.reg.tsdr, "WDU"); +// TSSSRbitfields. +state->u.f0.fld.tsssr.ss= cm_object_get_child_by_name(state->u.f0.reg.tsssr, "SS"); +// CALRbitfields. +state->u.f0.fld.calr.calm= cm_object_get_child_by_name(state->u.f0.reg.calr, "CALM"); +state->u.f0.fld.calr.calw16= cm_object_get_child_by_name(state->u.f0.reg.calr, "CALW16"); +state->u.f0.fld.calr.calw8= cm_object_get_child_by_name(state->u.f0.reg.calr, "CALW8"); +state->u.f0.fld.calr.calp= cm_object_get_child_by_name(state->u.f0.reg.calr, "CALP"); +// TAFCRbitfields. +state->u.f0.fld.tafcr.tamp1e= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP1E"); +state->u.f0.fld.tafcr.tamp1trg= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP1TRG"); +state->u.f0.fld.tafcr.tampie= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPIE"); +state->u.f0.fld.tafcr.tamp2e= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP2E"); +state->u.f0.fld.tafcr.tamp2_trg= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP2_TRG"); +state->u.f0.fld.tafcr.tampts= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPTS"); +state->u.f0.fld.tafcr.tampfreq= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPFREQ"); +state->u.f0.fld.tafcr.tampflt= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMPFLT"); +state->u.f0.fld.tafcr.tamp_prch= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP_PRCH"); +state->u.f0.fld.tafcr.tamp_pudis= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "TAMP_PUDIS"); +state->u.f0.fld.tafcr.pc13value= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC13VALUE"); +state->u.f0.fld.tafcr.pc13mode= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC13MODE"); +state->u.f0.fld.tafcr.pc14value= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC14VALUE"); +state->u.f0.fld.tafcr.pc14mode= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC14MODE"); +state->u.f0.fld.tafcr.pc15value= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC15VALUE"); +state->u.f0.fld.tafcr.pc15mode= cm_object_get_child_by_name(state->u.f0.reg.tafcr, "PC15MODE"); +// ALRMASSRbitfields. +state->u.f0.fld.alrmassr.ss= cm_object_get_child_by_name(state->u.f0.reg.alrmassr, "SS"); +state->u.f0.fld.alrmassr.maskss= cm_object_get_child_by_name(state->u.f0.reg.alrmassr, "MASKSS"); +// BKP0Rbitfields. +state->u.f0.fld.bkp0r.bkp= cm_object_get_child_by_name(state->u.f0.reg.bkp0r, "BKP"); +// BKP1Rbitfields. +state->u.f0.fld.bkp1r.bkp= cm_object_get_child_by_name(state->u.f0.reg.bkp1r, "BKP"); +// BKP2Rbitfields. +state->u.f0.fld.bkp2r.bkp= cm_object_get_child_by_name(state->u.f0.reg.bkp2r, "BKP"); +// BKP3Rbitfields. +state->u.f0.fld.bkp3r.bkp= cm_object_get_child_by_name(state->u.f0.reg.bkp3r, "BKP"); +// BKP4Rbitfields. +state->u.f0.fld.bkp4r.bkp= cm_object_get_child_by_name(state->u.f0.reg.bkp4r, "BKP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rtc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rtc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rtc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rtc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rtc_is_enabled(Object *obj) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rtc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RTCState *state = STM32_RTC_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rtc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RTC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RTCState *state = STM32_RTC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RTC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_rtc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rtc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_rtc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_rtc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_rtc_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RTCEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rtc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RTC); +} + +static void stm32_rtc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rtc_reset_callback; + dc->realize = stm32_rtc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rtc_is_enabled; +} + +static const TypeInfo stm32_rtc_type_info = { + .name = TYPE_STM32_RTC, + .parent = TYPE_STM32_RTC_PARENT, + .instance_init = stm32_rtc_instance_init_callback, + .instance_size = sizeof(STM32RTCState), + .class_init = stm32_rtc_class_init_callback, + .class_size = sizeof(STM32RTCClass) }; + +static void stm32_rtc_register_types(void) +{ + type_register_static(&stm32_rtc_type_info); +} + +type_init(stm32_rtc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/rtc.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/rtc.h new file mode 100644 index 0000000000..1b7991081a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/rtc.h @@ -0,0 +1,177 @@ +/* + * STM32- RTC(Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RTC_H_ +#define STM32_RTC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RTCDEVICE_PATH_STM32"RTC" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RTCTYPE_STM32_PREFIX "rtc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RTC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RTCParentClass; +typedef PeripheralState STM32RTCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RTCClass, (obj), TYPE_STM32_RTC) +#define STM32_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RTCClass, (klass), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentClass parent_class; + // public: + + // None, so far. +} STM32RTCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RTC_STATE(obj) \ + OBJECT_CHECK(STM32RTCState, (obj), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0RTC(Real-time clock) registers. + struct { +Object *tr; // 0x0(Time register) +Object *dr; // 0x4(Date register) +Object *cr; // 0x8(Control register) +Object *isr; // 0xC(Initialization and status register) +Object *prer; // 0x10(Prescaler register) +Object *alrmar; // 0x1C(Alarm A register) +Object *wpr; // 0x24(Write protection register) +Object *ssr; // 0x28(Sub second register) +Object *shiftr; // 0x2C(Shift control register) +Object *tstr; // 0x30(Timestamp time register) +Object *tsdr; // 0x34(Timestamp date register) +Object *tsssr; // 0x38(Time-stamp sub second register) +Object *calr; // 0x3C(Calibration register) +Object *tafcr; // 0x40(Tamper and alternate function configuration register) +Object *alrmassr; // 0x44(Alarm A sub second register) +Object *bkp0r; // 0x50(Backup register) +Object *bkp1r; // 0x54(Backup register) +Object *bkp2r; // 0x58(Backup register) +Object *bkp3r; // 0x5C(Backup register) +Object *bkp4r; // 0x60(Backup register) +} reg; + + struct { +// TR(Time register) bitfields. + struct { +Object *su; // [0:3] Second units in BCD formatObject *st; // [4:6] Second tens in BCD formatObject *mnu; // [8:11] Minute units in BCD formatObject *mnt; // [12:14] Minute tens in BCD formatObject *hu; // [16:19] Hour units in BCD formatObject *ht; // [20:21] Hour tens in BCD formatObject *pm; // [22:22] AM/PM notation} tr; +// DR(Date register) bitfields. + struct { +Object *du; // [0:3] Date units in BCD formatObject *dt; // [4:5] Date tens in BCD formatObject *mu; // [8:11] Month units in BCD formatObject *mt; // [12:12] Month tens in BCD formatObject *wdu; // [13:15] Week day unitsObject *yu; // [16:19] Year units in BCD formatObject *yt; // [20:23] Year tens in BCD format} dr; +// CR(Control register) bitfields. + struct { +Object *tsedge; // [3:3] Time-stamp event active edgeObject *refckon; // [4:4] RTC_REFIN reference clock detection enable (50 or 60 Hz)Object *bypshad; // [5:5] Bypass the shadow registersObject *fmt; // [6:6] Hour formatObject *alrae; // [8:8] Alarm A enableObject *tse; // [11:11] Timestamp enableObject *alraie; // [12:12] Alarm A interrupt enableObject *tsie; // [15:15] Time-stamp interrupt enableObject *add1h; // [16:16] Add 1 hour (summer time change)Object *sub1h; // [17:17] Subtract 1 hour (winter time change)Object *bkp; // [18:18] BackupObject *cosel; // [19:19] Calibration output selectionObject *pol; // [20:20] Output polarityObject *osel; // [21:22] Output selectionObject *coe; // [23:23] Calibration output enable} cr; +// ISR(Initialization and status register) bitfields. + struct { +Object *alrawf; // [0:0] Alarm A write flagObject *shpf; // [3:3] Shift operation pendingObject *inits; // [4:4] Initialization status flagObject *rsf; // [5:5] Registers synchronization flagObject *initf; // [6:6] Initialization flagObject *init; // [7:7] Initialization modeObject *alraf; // [8:8] Alarm A flagObject *tsf; // [11:11] Time-stamp flagObject *tsovf; // [12:12] Time-stamp overflow flagObject *tamp1f; // [13:13] RTC_TAMP1 detection flagObject *tamp2f; // [14:14] RTC_TAMP2 detection flagObject *recalpf; // [16:16] Recalibration pending Flag} isr; +// PRER(Prescaler register) bitfields. + struct { +Object *prediv_s; // [0:14] Synchronous prescaler factorObject *prediv_a; // [16:22] Asynchronous prescaler factor} prer; +// ALRMAR(Alarm A register) bitfields. + struct { +Object *su; // [0:3] Second units in BCD format.Object *st; // [4:6] Second tens in BCD format.Object *msk1; // [7:7] Alarm A seconds maskObject *mnu; // [8:11] Minute units in BCD format.Object *mnt; // [12:14] Minute tens in BCD format.Object *msk2; // [15:15] Alarm A minutes maskObject *hu; // [16:19] Hour units in BCD format.Object *ht; // [20:21] Hour tens in BCD format.Object *pm; // [22:22] AM/PM notationObject *msk3; // [23:23] Alarm A hours maskObject *du; // [24:27] Date units or day in BCD format.Object *dt; // [28:29] Date tens in BCD format.Object *wdsel; // [30:30] Week day selectionObject *msk4; // [31:31] Alarm A date mask} alrmar; +// WPR(Write protection register) bitfields. + struct { +Object *key; // [0:7] Write protection key} wpr; +// SSR(Sub second register) bitfields. + struct { +Object *ss; // [0:15] Sub second value} ssr; +// SHIFTR(Shift control register) bitfields. + struct { +Object *subfs; // [0:14] Subtract a fraction of a secondObject *add1s; // [31:31] Reserved} shiftr; +// TSTR(Timestamp time register) bitfields. + struct { +Object *su; // [0:3] Second units in BCD format.Object *st; // [4:6] Second tens in BCD format.Object *mnu; // [8:11] Minute units in BCD format.Object *mnt; // [12:14] Minute tens in BCD format.Object *hu; // [16:19] Hour units in BCD format.Object *ht; // [20:21] Hour tens in BCD format.Object *pm; // [22:22] AM/PM notation} tstr; +// TSDR(Timestamp date register) bitfields. + struct { +Object *du; // [0:3] Date units in BCD formatObject *dt; // [4:5] Date tens in BCD formatObject *mu; // [8:11] Month units in BCD formatObject *mt; // [12:12] Month tens in BCD formatObject *wdu; // [13:15] Week day units} tsdr; +// TSSSR(Time-stamp sub second register) bitfields. + struct { +Object *ss; // [0:15] Sub second value} tsssr; +// CALR(Calibration register) bitfields. + struct { +Object *calm; // [0:8] Calibration minusObject *calw16; // [13:13] ReservedObject *calw8; // [14:14] Use a 16-second calibration cycle periodObject *calp; // [15:15] Use an 8-second calibration cycle period} calr; +// TAFCR(Tamper and alternate function configuration register) bitfields. + struct { +Object *tamp1e; // [0:0] RTC_TAMP1 input detection enableObject *tamp1trg; // [1:1] Active level for RTC_TAMP1 inputObject *tampie; // [2:2] Tamper interrupt enableObject *tamp2e; // [3:3] RTC_TAMP2 input detection enableObject *tamp2_trg; // [4:4] Active level for RTC_TAMP2 inputObject *tampts; // [7:7] Activate timestamp on tamper detection eventObject *tampfreq; // [8:10] Tamper sampling frequencyObject *tampflt; // [11:12] RTC_TAMPx filter countObject *tamp_prch; // [13:14] RTC_TAMPx precharge durationObject *tamp_pudis; // [15:15] RTC_TAMPx pull-up disableObject *pc13value; // [18:18] RTC_ALARM output type/PC13 valueObject *pc13mode; // [19:19] PC13 modeObject *pc14value; // [20:20] PC14 valueObject *pc14mode; // [21:21] PC14 modeObject *pc15value; // [22:22] PC15 valueObject *pc15mode; // [23:23] PC15 mode} tafcr; +// ALRMASSR(Alarm A sub second register) bitfields. + struct { +Object *ss; // [0:14] Sub seconds valueObject *maskss; // [24:27] Mask the most-significant bits starting at this bit} alrmassr; +// BKP0R(Backup register) bitfields. + struct { +Object *bkp; // [0:31] BKP} bkp0r; +// BKP1R(Backup register) bitfields. + struct { +Object *bkp; // [0:31] BKP} bkp1r; +// BKP2R(Backup register) bitfields. + struct { +Object *bkp; // [0:31] BKP} bkp2r; +// BKP3R(Backup register) bitfields. + struct { +Object *bkp; // [0:31] BKP} bkp3r; +// BKP4R(Backup register) bitfields. + struct { +Object *bkp; // [0:31] BKP} bkp4r; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RTCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RTC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/spi1.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/spi1.c new file mode 100644 index 0000000000..46b918e101 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/spi1.c @@ -0,0 +1,305 @@ +/* + * STM32- SPI(Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_spi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.dr= cm_object_get_child_by_name(obj, "DR"); +state->u.f0.reg.crcpr= cm_object_get_child_by_name(obj, "CRCPR"); +state->u.f0.reg.rxcrcr= cm_object_get_child_by_name(obj, "RXCRCR"); +state->u.f0.reg.txcrcr= cm_object_get_child_by_name(obj, "TXCRCR"); +state->u.f0.reg.i2scfgr= cm_object_get_child_by_name(obj, "I2SCFGR"); +state->u.f0.reg.i2spr= cm_object_get_child_by_name(obj, "I2SPR"); +// CR1bitfields. +state->u.f0.fld.cr1.cpha= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CPHA"); +state->u.f0.fld.cr1.cpol= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CPOL"); +state->u.f0.fld.cr1.mstr= cm_object_get_child_by_name(state->u.f0.reg.cr1, "MSTR"); +state->u.f0.fld.cr1.br= cm_object_get_child_by_name(state->u.f0.reg.cr1, "BR"); +state->u.f0.fld.cr1.spe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "SPE"); +state->u.f0.fld.cr1.lsbfirst= cm_object_get_child_by_name(state->u.f0.reg.cr1, "LSBFIRST"); +state->u.f0.fld.cr1.ssi= cm_object_get_child_by_name(state->u.f0.reg.cr1, "SSI"); +state->u.f0.fld.cr1.ssm= cm_object_get_child_by_name(state->u.f0.reg.cr1, "SSM"); +state->u.f0.fld.cr1.rxonly= cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXONLY"); +state->u.f0.fld.cr1.dff= cm_object_get_child_by_name(state->u.f0.reg.cr1, "DFF"); +state->u.f0.fld.cr1.crcnext= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CRCNEXT"); +state->u.f0.fld.cr1.crcen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CRCEN"); +state->u.f0.fld.cr1.bidioe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "BIDIOE"); +state->u.f0.fld.cr1.bidimode= cm_object_get_child_by_name(state->u.f0.reg.cr1, "BIDIMODE"); +// CR2bitfields. +state->u.f0.fld.cr2.rxdmaen= cm_object_get_child_by_name(state->u.f0.reg.cr2, "RXDMAEN"); +state->u.f0.fld.cr2.txdmaen= cm_object_get_child_by_name(state->u.f0.reg.cr2, "TXDMAEN"); +state->u.f0.fld.cr2.ssoe= cm_object_get_child_by_name(state->u.f0.reg.cr2, "SSOE"); +state->u.f0.fld.cr2.nssp= cm_object_get_child_by_name(state->u.f0.reg.cr2, "NSSP"); +state->u.f0.fld.cr2.frf= cm_object_get_child_by_name(state->u.f0.reg.cr2, "FRF"); +state->u.f0.fld.cr2.errie= cm_object_get_child_by_name(state->u.f0.reg.cr2, "ERRIE"); +state->u.f0.fld.cr2.rxneie= cm_object_get_child_by_name(state->u.f0.reg.cr2, "RXNEIE"); +state->u.f0.fld.cr2.txeie= cm_object_get_child_by_name(state->u.f0.reg.cr2, "TXEIE"); +state->u.f0.fld.cr2.ds= cm_object_get_child_by_name(state->u.f0.reg.cr2, "DS"); +state->u.f0.fld.cr2.frxth= cm_object_get_child_by_name(state->u.f0.reg.cr2, "FRXTH"); +state->u.f0.fld.cr2.ldma_rx= cm_object_get_child_by_name(state->u.f0.reg.cr2, "LDMA_RX"); +state->u.f0.fld.cr2.ldma_tx= cm_object_get_child_by_name(state->u.f0.reg.cr2, "LDMA_TX"); +// SRbitfields. +state->u.f0.fld.sr.rxne= cm_object_get_child_by_name(state->u.f0.reg.sr, "RXNE"); +state->u.f0.fld.sr.txe= cm_object_get_child_by_name(state->u.f0.reg.sr, "TXE"); +state->u.f0.fld.sr.chside= cm_object_get_child_by_name(state->u.f0.reg.sr, "CHSIDE"); +state->u.f0.fld.sr.udr= cm_object_get_child_by_name(state->u.f0.reg.sr, "UDR"); +state->u.f0.fld.sr.crcerr= cm_object_get_child_by_name(state->u.f0.reg.sr, "CRCERR"); +state->u.f0.fld.sr.modf= cm_object_get_child_by_name(state->u.f0.reg.sr, "MODF"); +state->u.f0.fld.sr.ovr= cm_object_get_child_by_name(state->u.f0.reg.sr, "OVR"); +state->u.f0.fld.sr.bsy= cm_object_get_child_by_name(state->u.f0.reg.sr, "BSY"); +state->u.f0.fld.sr.tifrfe= cm_object_get_child_by_name(state->u.f0.reg.sr, "TIFRFE"); +state->u.f0.fld.sr.frlvl= cm_object_get_child_by_name(state->u.f0.reg.sr, "FRLVL"); +state->u.f0.fld.sr.ftlvl= cm_object_get_child_by_name(state->u.f0.reg.sr, "FTLVL"); +// DRbitfields. +state->u.f0.fld.dr.dr= cm_object_get_child_by_name(state->u.f0.reg.dr, "DR"); +// CRCPRbitfields. +state->u.f0.fld.crcpr.crcpoly= cm_object_get_child_by_name(state->u.f0.reg.crcpr, "CRCPOLY"); +// RXCRCRbitfields. +state->u.f0.fld.rxcrcr.rxcrc= cm_object_get_child_by_name(state->u.f0.reg.rxcrcr, "RxCRC"); +// TXCRCRbitfields. +state->u.f0.fld.txcrcr.txcrc= cm_object_get_child_by_name(state->u.f0.reg.txcrcr, "TxCRC"); +// I2SCFGRbitfields. +state->u.f0.fld.i2scfgr.chlen= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "CHLEN"); +state->u.f0.fld.i2scfgr.datlen= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "DATLEN"); +state->u.f0.fld.i2scfgr.ckpol= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "CKPOL"); +state->u.f0.fld.i2scfgr.i2sstd= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SSTD"); +state->u.f0.fld.i2scfgr.pcmsync= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "PCMSYNC"); +state->u.f0.fld.i2scfgr.i2scfg= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SCFG"); +state->u.f0.fld.i2scfgr.i2se= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SE"); +state->u.f0.fld.i2scfgr.i2smod= cm_object_get_child_by_name(state->u.f0.reg.i2scfgr, "I2SMOD"); +// I2SPRbitfields. +state->u.f0.fld.i2spr.i2sdiv= cm_object_get_child_by_name(state->u.f0.reg.i2spr, "I2SDIV"); +state->u.f0.fld.i2spr.odd= cm_object_get_child_by_name(state->u.f0.reg.i2spr, "ODD"); +state->u.f0.fld.i2spr.mckoe= cm_object_get_child_by_name(state->u.f0.reg.i2spr, "MCKOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_spi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_spi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_spi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_spi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_spi_is_enabled(Object *obj) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_spi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SPIState *state = STM32_SPI_STATE(obj); + + // Capabilities are not yet available. + +cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_SPI_UNDEFINED; +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_spi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SPI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SPIState *state = STM32_SPI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SPI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_spi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_spi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_spi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_spi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_spi_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SPI%dEN", + 1 + state->port_index - STM32_PORT_SPI1); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_spi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SPI); +} + +static void stm32_spi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_spi_reset_callback; + dc->realize = stm32_spi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_spi_is_enabled; +} + +static const TypeInfo stm32_spi_type_info = { + .name = TYPE_STM32_SPI, + .parent = TYPE_STM32_SPI_PARENT, + .instance_init = stm32_spi_instance_init_callback, + .instance_size = sizeof(STM32SPIState), + .class_init = stm32_spi_class_init_callback, + .class_size = sizeof(STM32SPIClass) }; + +static void stm32_spi_register_types(void) +{ + type_register_static(&stm32_spi_type_info); +} + +type_init(stm32_spi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/spi1.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/spi1.h new file mode 100644 index 0000000000..b0f40dab03 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/spi1.h @@ -0,0 +1,144 @@ +/* + * STM32- SPI(Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SPI_H_ +#define STM32_SPI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SPIDEVICE_PATH_STM32"SPI" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. +STM32_PORT_SPI1, +STM32_PORT_SPI2, +STM32_PORT_SPI_UNDEFINED = 0xFF, +} stm32_spi_index_t; +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SPITYPE_STM32_PREFIX "spi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SPI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SPIParentClass; +typedef PeripheralState STM32SPIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SPI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SPIClass, (obj), TYPE_STM32_SPI) +#define STM32_SPI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SPIClass, (klass), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentClass parent_class; + // public: + + // None, so far. +} STM32SPIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SPI_STATE(obj) \ + OBJECT_CHECK(STM32SPIState, (obj), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +// Remove it if there is only one port + stm32_spi_index_t port_index; +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0SPI(Serial peripheral interface) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *sr; // 0x8(Status register) +Object *dr; // 0xC(Data register) +Object *crcpr; // 0x10(CRC polynomial register) +Object *rxcrcr; // 0x14(RX CRC register) +Object *txcrcr; // 0x18(TX CRC register) +Object *i2scfgr; // 0x1C(I2S configuration register) +Object *i2spr; // 0x20(I2S prescaler register) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *cpha; // [0:0] Clock phaseObject *cpol; // [1:1] Clock polarityObject *mstr; // [2:2] Master selectionObject *br; // [3:5] Baud rate controlObject *spe; // [6:6] SPI enableObject *lsbfirst; // [7:7] Frame formatObject *ssi; // [8:8] Internal slave selectObject *ssm; // [9:9] Software slave managementObject *rxonly; // [10:10] Receive onlyObject *dff; // [11:11] Data frame formatObject *crcnext; // [12:12] CRC transfer nextObject *crcen; // [13:13] Hardware CRC calculation enableObject *bidioe; // [14:14] Output enable in bidirectional modeObject *bidimode; // [15:15] Bidirectional data mode enable} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *rxdmaen; // [0:0] Rx buffer DMA enableObject *txdmaen; // [1:1] Tx buffer DMA enableObject *ssoe; // [2:2] SS output enableObject *nssp; // [3:3] NSS pulse managementObject *frf; // [4:4] Frame formatObject *errie; // [5:5] Error interrupt enableObject *rxneie; // [6:6] RX buffer not empty interrupt enableObject *txeie; // [7:7] Tx buffer empty interrupt enableObject *ds; // [8:11] Data sizeObject *frxth; // [12:12] FIFO reception thresholdObject *ldma_rx; // [13:13] Last DMA transfer for receptionObject *ldma_tx; // [14:14] Last DMA transfer for transmission} cr2; +// SR(Status register) bitfields. + struct { +Object *rxne; // [0:0] Receive buffer not emptyObject *txe; // [1:1] Transmit buffer emptyObject *chside; // [2:2] Channel sideObject *udr; // [3:3] Underrun flagObject *crcerr; // [4:4] CRC error flagObject *modf; // [5:5] Mode faultObject *ovr; // [6:6] Overrun flagObject *bsy; // [7:7] Busy flagObject *tifrfe; // [8:8] TI frame format errorObject *frlvl; // [9:10] FIFO reception levelObject *ftlvl; // [11:12] FIFO transmission level} sr; +// DR(Data register) bitfields. + struct { +Object *dr; // [0:15] Data register} dr; +// CRCPR(CRC polynomial register) bitfields. + struct { +Object *crcpoly; // [0:15] CRC polynomial register} crcpr; +// RXCRCR(RX CRC register) bitfields. + struct { +Object *rxcrc; // [0:15] Rx CRC register} rxcrcr; +// TXCRCR(TX CRC register) bitfields. + struct { +Object *txcrc; // [0:15] Tx CRC register} txcrcr; +// I2SCFGR(I2S configuration register) bitfields. + struct { +Object *chlen; // [0:0] Channel length (number of bits per audio channel)Object *datlen; // [1:2] Data length to be transferredObject *ckpol; // [3:3] Steady state clock polarityObject *i2sstd; // [4:5] I2S standard selectionObject *pcmsync; // [7:7] PCM frame synchronizationObject *i2scfg; // [8:9] I2S configuration modeObject *i2se; // [10:10] I2S EnableObject *i2smod; // [11:11] I2S mode selection} i2scfgr; +// I2SPR(I2S prescaler register) bitfields. + struct { +Object *i2sdiv; // [0:7] I2S Linear prescalerObject *odd; // [8:8] Odd factor for the prescalerObject *mckoe; // [9:9] Master clock output enable} i2spr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SPIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SPI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/syscfg.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/syscfg.c new file mode 100644 index 0000000000..fe07282134 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/syscfg.c @@ -0,0 +1,282 @@ +/* + * STM32- SYSCFG(System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_syscfg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cfgr1= cm_object_get_child_by_name(obj, "CFGR1"); +state->u.f0.reg.exticr1= cm_object_get_child_by_name(obj, "EXTICR1"); +state->u.f0.reg.exticr2= cm_object_get_child_by_name(obj, "EXTICR2"); +state->u.f0.reg.exticr3= cm_object_get_child_by_name(obj, "EXTICR3"); +state->u.f0.reg.exticr4= cm_object_get_child_by_name(obj, "EXTICR4"); +state->u.f0.reg.cfgr2= cm_object_get_child_by_name(obj, "CFGR2"); +// CFGR1bitfields. +state->u.f0.fld.cfgr1.mem_mode= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "MEM_MODE"); +state->u.f0.fld.cfgr1.adc_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "ADC_DMA_RMP"); +state->u.f0.fld.cfgr1.usart1_tx_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART1_TX_DMA_RMP"); +state->u.f0.fld.cfgr1.usart1_rx_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART1_RX_DMA_RMP"); +state->u.f0.fld.cfgr1.tim16_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM16_DMA_RMP"); +state->u.f0.fld.cfgr1.tim17_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM17_DMA_RMP"); +state->u.f0.fld.cfgr1.i2c_pb6_fm= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB6_FM"); +state->u.f0.fld.cfgr1.i2c_pb7_fm= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB7_FM"); +state->u.f0.fld.cfgr1.i2c_pb8_fm= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB8_FM"); +state->u.f0.fld.cfgr1.i2c_pb9_fm= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C_PB9_FM"); +state->u.f0.fld.cfgr1.i2c1_fm_plus= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C1_FM_plus"); +state->u.f0.fld.cfgr1.i2c2_fm_plus= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C2_FM_plus"); +state->u.f0.fld.cfgr1.spi2_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "SPI2_DMA_RMP"); +state->u.f0.fld.cfgr1.usart2_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART2_DMA_RMP"); +state->u.f0.fld.cfgr1.usart3_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "USART3_DMA_RMP"); +state->u.f0.fld.cfgr1.i2c1_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "I2C1_DMA_RMP"); +state->u.f0.fld.cfgr1.tim1_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM1_DMA_RMP"); +state->u.f0.fld.cfgr1.tim2_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM2_DMA_RMP"); +state->u.f0.fld.cfgr1.tim3_dma_rmp= cm_object_get_child_by_name(state->u.f0.reg.cfgr1, "TIM3_DMA_RMP"); +// EXTICR1bitfields. +state->u.f0.fld.exticr1.exti0= cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI0"); +state->u.f0.fld.exticr1.exti1= cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI1"); +state->u.f0.fld.exticr1.exti2= cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI2"); +state->u.f0.fld.exticr1.exti3= cm_object_get_child_by_name(state->u.f0.reg.exticr1, "EXTI3"); +// EXTICR2bitfields. +state->u.f0.fld.exticr2.exti4= cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI4"); +state->u.f0.fld.exticr2.exti5= cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI5"); +state->u.f0.fld.exticr2.exti6= cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI6"); +state->u.f0.fld.exticr2.exti7= cm_object_get_child_by_name(state->u.f0.reg.exticr2, "EXTI7"); +// EXTICR3bitfields. +state->u.f0.fld.exticr3.exti8= cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI8"); +state->u.f0.fld.exticr3.exti9= cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI9"); +state->u.f0.fld.exticr3.exti10= cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI10"); +state->u.f0.fld.exticr3.exti11= cm_object_get_child_by_name(state->u.f0.reg.exticr3, "EXTI11"); +// EXTICR4bitfields. +state->u.f0.fld.exticr4.exti12= cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI12"); +state->u.f0.fld.exticr4.exti13= cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI13"); +state->u.f0.fld.exticr4.exti14= cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI14"); +state->u.f0.fld.exticr4.exti15= cm_object_get_child_by_name(state->u.f0.reg.exticr4, "EXTI15"); +// CFGR2bitfields. +state->u.f0.fld.cfgr2.locup_lock= cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "LOCUP_LOCK"); +state->u.f0.fld.cfgr2.sram_parity_lock= cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "SRAM_PARITY_LOCK"); +state->u.f0.fld.cfgr2.pvd_lock= cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "PVD_LOCK"); +state->u.f0.fld.cfgr2.sram_pef= cm_object_get_child_by_name(state->u.f0.reg.cfgr2, "SRAM_PEF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_syscfg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_syscfg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_syscfg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_syscfg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_syscfg_is_enabled(Object *obj) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_syscfg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_syscfg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SYSCFG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SYSCFG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_syscfg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_syscfg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_syscfg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_syscfg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_syscfg_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SYSCFGEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_syscfg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SYSCFG); +} + +static void stm32_syscfg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_syscfg_reset_callback; + dc->realize = stm32_syscfg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_syscfg_is_enabled; +} + +static const TypeInfo stm32_syscfg_type_info = { + .name = TYPE_STM32_SYSCFG, + .parent = TYPE_STM32_SYSCFG_PARENT, + .instance_init = stm32_syscfg_instance_init_callback, + .instance_size = sizeof(STM32SYSCFGState), + .class_init = stm32_syscfg_class_init_callback, + .class_size = sizeof(STM32SYSCFGClass) }; + +static void stm32_syscfg_register_types(void) +{ + type_register_static(&stm32_syscfg_type_info); +} + +type_init(stm32_syscfg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/syscfg.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/syscfg.h new file mode 100644 index 0000000000..235b01d245 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/syscfg.h @@ -0,0 +1,121 @@ +/* + * STM32- SYSCFG(System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SYSCFG_H_ +#define STM32_SYSCFG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SYSCFGDEVICE_PATH_STM32"SYSCFG" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SYSCFGTYPE_STM32_PREFIX "syscfg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SYSCFG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SYSCFGParentClass; +typedef PeripheralState STM32SYSCFGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SYSCFG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SYSCFGClass, (obj), TYPE_STM32_SYSCFG) +#define STM32_SYSCFG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SYSCFGClass, (klass), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentClass parent_class; + // public: + + // None, so far. +} STM32SYSCFGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SYSCFG_STATE(obj) \ + OBJECT_CHECK(STM32SYSCFGState, (obj), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0SYSCFG(System configuration controller) registers. + struct { +Object *cfgr1; // 0x0(Configuration register 1) +Object *exticr1; // 0x8(External interrupt configuration register 1) +Object *exticr2; // 0xC(External interrupt configuration register 2) +Object *exticr3; // 0x10(External interrupt configuration register 3) +Object *exticr4; // 0x14(External interrupt configuration register 4) +Object *cfgr2; // 0x18(Configuration register 2) +} reg; + + struct { +// CFGR1(Configuration register 1) bitfields. + struct { +Object *mem_mode; // [0:1] Memory mapping selection bitsObject *adc_dma_rmp; // [8:8] ADC DMA remapping bitObject *usart1_tx_dma_rmp; // [9:9] USART1_TX DMA remapping bitObject *usart1_rx_dma_rmp; // [10:10] USART1_RX DMA request remapping bitObject *tim16_dma_rmp; // [11:11] TIM16 DMA request remapping bitObject *tim17_dma_rmp; // [12:12] TIM17 DMA request remapping bitObject *i2c_pb6_fm; // [16:16] Fast Mode Plus (FM plus) driving capability activation bits.Object *i2c_pb7_fm; // [17:17] Fast Mode Plus (FM+) driving capability activation bits.Object *i2c_pb8_fm; // [18:18] Fast Mode Plus (FM+) driving capability activation bits.Object *i2c_pb9_fm; // [19:19] Fast Mode Plus (FM+) driving capability activation bits.Object *i2c1_fm_plus; // [20:20] FM+ driving capability activation for I2C1Object *i2c2_fm_plus; // [21:21] FM+ driving capability activation for I2C2Object *spi2_dma_rmp; // [24:24] SPI2 DMA request remapping bitObject *usart2_dma_rmp; // [25:25] USART2 DMA request remapping bitObject *usart3_dma_rmp; // [26:26] USART3 DMA request remapping bitObject *i2c1_dma_rmp; // [27:27] I2C1 DMA request remapping bitObject *tim1_dma_rmp; // [28:28] TIM1 DMA request remapping bitObject *tim2_dma_rmp; // [29:29] TIM2 DMA request remapping bitObject *tim3_dma_rmp; // [30:30] TIM3 DMA request remapping bit} cfgr1; +// EXTICR1(External interrupt configuration register 1) bitfields. + struct { +Object *exti0; // [0:3] EXTI 0 configuration bitsObject *exti1; // [4:7] EXTI 1 configuration bitsObject *exti2; // [8:11] EXTI 2 configuration bitsObject *exti3; // [12:15] EXTI 3 configuration bits} exticr1; +// EXTICR2(External interrupt configuration register 2) bitfields. + struct { +Object *exti4; // [0:3] EXTI 4 configuration bitsObject *exti5; // [4:7] EXTI 5 configuration bitsObject *exti6; // [8:11] EXTI 6 configuration bitsObject *exti7; // [12:15] EXTI 7 configuration bits} exticr2; +// EXTICR3(External interrupt configuration register 3) bitfields. + struct { +Object *exti8; // [0:3] EXTI 8 configuration bitsObject *exti9; // [4:7] EXTI 9 configuration bitsObject *exti10; // [8:11] EXTI 10 configuration bitsObject *exti11; // [12:15] EXTI 11 configuration bits} exticr3; +// EXTICR4(External interrupt configuration register 4) bitfields. + struct { +Object *exti12; // [0:3] EXTI 12 configuration bitsObject *exti13; // [4:7] EXTI 13 configuration bitsObject *exti14; // [8:11] EXTI 14 configuration bitsObject *exti15; // [12:15] EXTI 15 configuration bits} exticr4; +// CFGR2(Configuration register 2) bitfields. + struct { +Object *locup_lock; // [0:0] Cortex-M0 LOCKUP bit enable bitObject *sram_parity_lock; // [1:1] SRAM parity lock bitObject *pvd_lock; // [2:2] PVD lock enable bitObject *sram_pef; // [8:8] SRAM parity flag} cfgr2; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SYSCFGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SYSCFG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim1.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim1.c new file mode 100644 index 0000000000..03de2d739b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim1.c @@ -0,0 +1,402 @@ +/* + * STM32- TIM1(Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_tim1_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.smcr= cm_object_get_child_by_name(obj, "SMCR"); +state->u.f0.reg.dier= cm_object_get_child_by_name(obj, "DIER"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.egr= cm_object_get_child_by_name(obj, "EGR"); +state->u.f0.reg.ccmr1_output= cm_object_get_child_by_name(obj, "CCMR1_Output"); +state->u.f0.reg.ccmr1_input= cm_object_get_child_by_name(obj, "CCMR1_Input"); +state->u.f0.reg.ccmr2_output= cm_object_get_child_by_name(obj, "CCMR2_Output"); +state->u.f0.reg.ccmr2_input= cm_object_get_child_by_name(obj, "CCMR2_Input"); +state->u.f0.reg.ccer= cm_object_get_child_by_name(obj, "CCER"); +state->u.f0.reg.cnt= cm_object_get_child_by_name(obj, "CNT"); +state->u.f0.reg.psc= cm_object_get_child_by_name(obj, "PSC"); +state->u.f0.reg.arr= cm_object_get_child_by_name(obj, "ARR"); +state->u.f0.reg.rcr= cm_object_get_child_by_name(obj, "RCR"); +state->u.f0.reg.ccr1= cm_object_get_child_by_name(obj, "CCR1"); +state->u.f0.reg.ccr2= cm_object_get_child_by_name(obj, "CCR2"); +state->u.f0.reg.ccr3= cm_object_get_child_by_name(obj, "CCR3"); +state->u.f0.reg.ccr4= cm_object_get_child_by_name(obj, "CCR4"); +state->u.f0.reg.bdtr= cm_object_get_child_by_name(obj, "BDTR"); +state->u.f0.reg.dcr= cm_object_get_child_by_name(obj, "DCR"); +state->u.f0.reg.dmar= cm_object_get_child_by_name(obj, "DMAR"); +// CR1bitfields. +state->u.f0.fld.cr1.cen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); +state->u.f0.fld.cr1.udis= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); +state->u.f0.fld.cr1.urs= cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); +state->u.f0.fld.cr1.opm= cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); +state->u.f0.fld.cr1.dir= cm_object_get_child_by_name(state->u.f0.reg.cr1, "DIR"); +state->u.f0.fld.cr1.cms= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CMS"); +state->u.f0.fld.cr1.arpe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); +state->u.f0.fld.cr1.ckd= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); +// CR2bitfields. +state->u.f0.fld.cr2.ccpc= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCPC"); +state->u.f0.fld.cr2.ccus= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCUS"); +state->u.f0.fld.cr2.ccds= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); +state->u.f0.fld.cr2.mms= cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); +state->u.f0.fld.cr2.ti1s= cm_object_get_child_by_name(state->u.f0.reg.cr2, "TI1S"); +state->u.f0.fld.cr2.ois1= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1"); +state->u.f0.fld.cr2.ois1n= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1N"); +state->u.f0.fld.cr2.ois2= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS2"); +state->u.f0.fld.cr2.ois2n= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS2N"); +state->u.f0.fld.cr2.ois3= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS3"); +state->u.f0.fld.cr2.ois3n= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS3N"); +state->u.f0.fld.cr2.ois4= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS4"); +// SMCRbitfields. +state->u.f0.fld.smcr.sms= cm_object_get_child_by_name(state->u.f0.reg.smcr, "SMS"); +state->u.f0.fld.smcr.ts= cm_object_get_child_by_name(state->u.f0.reg.smcr, "TS"); +state->u.f0.fld.smcr.msm= cm_object_get_child_by_name(state->u.f0.reg.smcr, "MSM"); +state->u.f0.fld.smcr.etf= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETF"); +state->u.f0.fld.smcr.etps= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETPS"); +state->u.f0.fld.smcr.ece= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ECE"); +state->u.f0.fld.smcr.etp= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETP"); +// DIERbitfields. +state->u.f0.fld.dier.uie= cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); +state->u.f0.fld.dier.cc1ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); +state->u.f0.fld.dier.cc2ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2IE"); +state->u.f0.fld.dier.cc3ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3IE"); +state->u.f0.fld.dier.cc4ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4IE"); +state->u.f0.fld.dier.comie= cm_object_get_child_by_name(state->u.f0.reg.dier, "COMIE"); +state->u.f0.fld.dier.tie= cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); +state->u.f0.fld.dier.bie= cm_object_get_child_by_name(state->u.f0.reg.dier, "BIE"); +state->u.f0.fld.dier.ude= cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); +state->u.f0.fld.dier.cc1de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); +state->u.f0.fld.dier.cc2de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2DE"); +state->u.f0.fld.dier.cc3de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3DE"); +state->u.f0.fld.dier.cc4de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4DE"); +state->u.f0.fld.dier.comde= cm_object_get_child_by_name(state->u.f0.reg.dier, "COMDE"); +state->u.f0.fld.dier.tde= cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); +// SRbitfields. +state->u.f0.fld.sr.uif= cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); +state->u.f0.fld.sr.cc1if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); +state->u.f0.fld.sr.cc2if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2IF"); +state->u.f0.fld.sr.cc3if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3IF"); +state->u.f0.fld.sr.cc4if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4IF"); +state->u.f0.fld.sr.comif= cm_object_get_child_by_name(state->u.f0.reg.sr, "COMIF"); +state->u.f0.fld.sr.tif= cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); +state->u.f0.fld.sr.bif= cm_object_get_child_by_name(state->u.f0.reg.sr, "BIF"); +state->u.f0.fld.sr.cc1of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); +state->u.f0.fld.sr.cc2of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2OF"); +state->u.f0.fld.sr.cc3of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3OF"); +state->u.f0.fld.sr.cc4of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4OF"); +// EGRbitfields. +state->u.f0.fld.egr.ug= cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); +state->u.f0.fld.egr.cc1g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); +state->u.f0.fld.egr.cc2g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC2G"); +state->u.f0.fld.egr.cc3g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC3G"); +state->u.f0.fld.egr.cc4g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC4G"); +state->u.f0.fld.egr.comg= cm_object_get_child_by_name(state->u.f0.reg.egr, "COMG"); +state->u.f0.fld.egr.tg= cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); +state->u.f0.fld.egr.bg= cm_object_get_child_by_name(state->u.f0.reg.egr, "BG"); +// CCMR1_Outputbitfields. +state->u.f0.fld.ccmr1_output.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); +state->u.f0.fld.ccmr1_output.oc1fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); +state->u.f0.fld.ccmr1_output.oc1pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); +state->u.f0.fld.ccmr1_output.oc1m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); +state->u.f0.fld.ccmr1_output.oc1ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1CE"); +state->u.f0.fld.ccmr1_output.cc2s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC2S"); +state->u.f0.fld.ccmr1_output.oc2fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2FE"); +state->u.f0.fld.ccmr1_output.oc2pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2PE"); +state->u.f0.fld.ccmr1_output.oc2m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2M"); +state->u.f0.fld.ccmr1_output.oc2ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2CE"); +// CCMR1_Inputbitfields. +state->u.f0.fld.ccmr1_input.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); +state->u.f0.fld.ccmr1_input.ic1pcs= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PCS"); +state->u.f0.fld.ccmr1_input.ic1f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); +state->u.f0.fld.ccmr1_input.cc2s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC2S"); +state->u.f0.fld.ccmr1_input.ic2pcs= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2PCS"); +state->u.f0.fld.ccmr1_input.ic2f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2F"); +// CCMR2_Outputbitfields. +state->u.f0.fld.ccmr2_output.cc3s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC3S"); +state->u.f0.fld.ccmr2_output.oc3fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3FE"); +state->u.f0.fld.ccmr2_output.oc3pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3PE"); +state->u.f0.fld.ccmr2_output.oc3m= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3M"); +state->u.f0.fld.ccmr2_output.oc3ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3CE"); +state->u.f0.fld.ccmr2_output.cc4s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC4S"); +state->u.f0.fld.ccmr2_output.oc4fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4FE"); +state->u.f0.fld.ccmr2_output.oc4pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4PE"); +state->u.f0.fld.ccmr2_output.oc4m= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4M"); +state->u.f0.fld.ccmr2_output.oc4ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4CE"); +// CCMR2_Inputbitfields. +state->u.f0.fld.ccmr2_input.cc3s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC3S"); +state->u.f0.fld.ccmr2_input.ic3psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3PSC"); +state->u.f0.fld.ccmr2_input.ic3f= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3F"); +state->u.f0.fld.ccmr2_input.cc4s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC4S"); +state->u.f0.fld.ccmr2_input.ic4psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4PSC"); +state->u.f0.fld.ccmr2_input.ic4f= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4F"); +// CCERbitfields. +state->u.f0.fld.ccer.cc1e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); +state->u.f0.fld.ccer.cc1p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); +state->u.f0.fld.ccer.cc1ne= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NE"); +state->u.f0.fld.ccer.cc1np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); +state->u.f0.fld.ccer.cc2e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2E"); +state->u.f0.fld.ccer.cc2p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2P"); +state->u.f0.fld.ccer.cc2ne= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NE"); +state->u.f0.fld.ccer.cc2np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NP"); +state->u.f0.fld.ccer.cc3e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3E"); +state->u.f0.fld.ccer.cc3p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3P"); +state->u.f0.fld.ccer.cc3ne= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3NE"); +state->u.f0.fld.ccer.cc3np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3NP"); +state->u.f0.fld.ccer.cc4e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4E"); +state->u.f0.fld.ccer.cc4p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4P"); +// CNTbitfields. +state->u.f0.fld.cnt.cnt= cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); +// PSCbitfields. +state->u.f0.fld.psc.psc= cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); +// ARRbitfields. +state->u.f0.fld.arr.arr= cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); +// RCRbitfields. +state->u.f0.fld.rcr.rep= cm_object_get_child_by_name(state->u.f0.reg.rcr, "REP"); +// CCR1bitfields. +state->u.f0.fld.ccr1.ccr1= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); +// CCR2bitfields. +state->u.f0.fld.ccr2.ccr2= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2"); +// CCR3bitfields. +state->u.f0.fld.ccr3.ccr3= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CCR3"); +// CCR4bitfields. +state->u.f0.fld.ccr4.ccr4= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CCR4"); +// BDTRbitfields. +state->u.f0.fld.bdtr.dtg= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "DTG"); +state->u.f0.fld.bdtr.lock= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "LOCK"); +state->u.f0.fld.bdtr.ossi= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSI"); +state->u.f0.fld.bdtr.ossr= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSR"); +state->u.f0.fld.bdtr.bke= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKE"); +state->u.f0.fld.bdtr.bkp= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKP"); +state->u.f0.fld.bdtr.aoe= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "AOE"); +state->u.f0.fld.bdtr.moe= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "MOE"); +// DCRbitfields. +state->u.f0.fld.dcr.dba= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); +state->u.f0.fld.dcr.dbl= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); +// DMARbitfields. +state->u.f0.fld.dmar.dmab= cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim1_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim1_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim1_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim1_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim1_is_enabled(Object *obj) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim1_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim1_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM1)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM1State *state = STM32_TIM1_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM1"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_tim1_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim1_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim1_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim1_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim1_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM1EN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim1_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM1); +} + +static void stm32_tim1_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim1_reset_callback; + dc->realize = stm32_tim1_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim1_is_enabled; +} + +static const TypeInfo stm32_tim1_type_info = { + .name = TYPE_STM32_TIM1, + .parent = TYPE_STM32_TIM1_PARENT, + .instance_init = stm32_tim1_instance_init_callback, + .instance_size = sizeof(STM32TIM1State), + .class_init = stm32_tim1_class_init_callback, + .class_size = sizeof(STM32TIM1Class) }; + +static void stm32_tim1_register_types(void) +{ + type_register_static(&stm32_tim1_type_info); +} + +type_init(stm32_tim1_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim1.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim1.h new file mode 100644 index 0000000000..230ee896b9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim1.h @@ -0,0 +1,185 @@ +/* + * STM32- TIM1(Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM1_H_ +#define STM32_TIM1_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM1DEVICE_PATH_STM32"TIM1" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM1TYPE_STM32_PREFIX "tim1" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM1_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM1ParentClass; +typedef PeripheralState STM32TIM1ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM1_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM1Class, (obj), TYPE_STM32_TIM1) +#define STM32_TIM1_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM1Class, (klass), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM1Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM1_STATE(obj) \ + OBJECT_CHECK(STM32TIM1State, (obj), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0TIM1(Advanced-timers) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *smcr; // 0x8(Slave mode control register) +Object *dier; // 0xC(DMA/Interrupt enable register) +Object *sr; // 0x10(Status register) +Object *egr; // 0x14(Event generation register) +Object *ccmr1_output; // 0x18(Capture/compare mode register (output mode)) +Object *ccmr1_input; // 0x18(Capture/compare mode register 1 (input mode)) +Object *ccmr2_output; // 0x1C(Capture/compare mode register (output mode)) +Object *ccmr2_input; // 0x1C(Capture/compare mode register 2 (input mode)) +Object *ccer; // 0x20(Capture/compare enable register) +Object *cnt; // 0x24(Counter) +Object *psc; // 0x28(Prescaler) +Object *arr; // 0x2C(Auto-reload register) +Object *rcr; // 0x30(Repetition counter register) +Object *ccr1; // 0x34(Capture/compare register 1) +Object *ccr2; // 0x38(Capture/compare register 2) +Object *ccr3; // 0x3C(Capture/compare register 3) +Object *ccr4; // 0x40(Capture/compare register 4) +Object *bdtr; // 0x44(Break and dead-time register) +Object *dcr; // 0x48(DMA control register) +Object *dmar; // 0x4C(DMA address for full transfer) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *cen; // [0:0] Counter enableObject *udis; // [1:1] Update disableObject *urs; // [2:2] Update request sourceObject *opm; // [3:3] One-pulse modeObject *dir; // [4:4] DirectionObject *cms; // [5:6] Center-aligned mode selectionObject *arpe; // [7:7] Auto-reload preload enableObject *ckd; // [8:9] Clock division} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *ccpc; // [0:0] Capture/compare preloaded controlObject *ccus; // [2:2] Capture/compare control update selectionObject *ccds; // [3:3] Capture/compare DMA selectionObject *mms; // [4:6] Master mode selectionObject *ti1s; // [7:7] TI1 selectionObject *ois1; // [8:8] Output Idle state 1Object *ois1n; // [9:9] Output Idle state 1Object *ois2; // [10:10] Output Idle state 2Object *ois2n; // [11:11] Output Idle state 2Object *ois3; // [12:12] Output Idle state 3Object *ois3n; // [13:13] Output Idle state 3Object *ois4; // [14:14] Output Idle state 4} cr2; +// SMCR(Slave mode control register) bitfields. + struct { +Object *sms; // [0:2] Slave mode selectionObject *ts; // [4:6] Trigger selectionObject *msm; // [7:7] Master/Slave modeObject *etf; // [8:11] External trigger filterObject *etps; // [12:13] External trigger prescalerObject *ece; // [14:14] External clock enableObject *etp; // [15:15] External trigger polarity} smcr; +// DIER(DMA/Interrupt enable register) bitfields. + struct { +Object *uie; // [0:0] Update interrupt enableObject *cc1ie; // [1:1] Capture/Compare 1 interrupt enableObject *cc2ie; // [2:2] Capture/Compare 2 interrupt enableObject *cc3ie; // [3:3] Capture/Compare 3 interrupt enableObject *cc4ie; // [4:4] Capture/Compare 4 interrupt enableObject *comie; // [5:5] COM interrupt enableObject *tie; // [6:6] Trigger interrupt enableObject *bie; // [7:7] Break interrupt enableObject *ude; // [8:8] Update DMA request enableObject *cc1de; // [9:9] Capture/Compare 1 DMA request enableObject *cc2de; // [10:10] Capture/Compare 2 DMA request enableObject *cc3de; // [11:11] Capture/Compare 3 DMA request enableObject *cc4de; // [12:12] Capture/Compare 4 DMA request enableObject *comde; // [13:13] ReservedObject *tde; // [14:14] Trigger DMA request enable} dier; +// SR(Status register) bitfields. + struct { +Object *uif; // [0:0] Update interrupt flagObject *cc1if; // [1:1] Capture/compare 1 interrupt flagObject *cc2if; // [2:2] Capture/Compare 2 interrupt flagObject *cc3if; // [3:3] Capture/Compare 3 interrupt flagObject *cc4if; // [4:4] Capture/Compare 4 interrupt flagObject *comif; // [5:5] COM interrupt flagObject *tif; // [6:6] Trigger interrupt flagObject *bif; // [7:7] Break interrupt flagObject *cc1of; // [9:9] Capture/Compare 1 overcapture flagObject *cc2of; // [10:10] Capture/compare 2 overcapture flagObject *cc3of; // [11:11] Capture/Compare 3 overcapture flagObject *cc4of; // [12:12] Capture/Compare 4 overcapture flag} sr; +// EGR(Event generation register) bitfields. + struct { +Object *ug; // [0:0] Update generationObject *cc1g; // [1:1] Capture/compare 1 generationObject *cc2g; // [2:2] Capture/compare 2 generationObject *cc3g; // [3:3] Capture/compare 3 generationObject *cc4g; // [4:4] Capture/compare 4 generationObject *comg; // [5:5] Capture/Compare control update generationObject *tg; // [6:6] Trigger generationObject *bg; // [7:7] Break generation} egr; +// CCMR1_Output(Capture/compare mode register (output mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *oc1fe; // [2:2] Output Compare 1 fast enableObject *oc1pe; // [3:3] Output Compare 1 preload enableObject *oc1m; // [4:6] Output Compare 1 modeObject *oc1ce; // [7:7] Output Compare 1 clear enableObject *cc2s; // [8:9] Capture/Compare 2 selectionObject *oc2fe; // [10:10] Output Compare 2 fast enableObject *oc2pe; // [11:11] Output Compare 2 preload enableObject *oc2m; // [12:14] Output Compare 2 modeObject *oc2ce; // [15:15] Output Compare 2 clear enable} ccmr1_output; +// CCMR1_Input(Capture/compare mode register 1 (input mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *ic1pcs; // [2:3] Input capture 1 prescalerObject *ic1f; // [4:7] Input capture 1 filterObject *cc2s; // [8:9] Capture/Compare 2 selectionObject *ic2pcs; // [10:11] Input capture 2 prescalerObject *ic2f; // [12:15] Input capture 2 filter} ccmr1_input; +// CCMR2_Output(Capture/compare mode register (output mode)) bitfields. + struct { +Object *cc3s; // [0:1] Capture/Compare 3 selectionObject *oc3fe; // [2:2] Output compare 3 fast enableObject *oc3pe; // [3:3] Output compare 3 preload enableObject *oc3m; // [4:6] Output compare 3 modeObject *oc3ce; // [7:7] Output compare 3 clear enableObject *cc4s; // [8:9] Capture/Compare 4 selectionObject *oc4fe; // [10:10] Output compare 4 fast enableObject *oc4pe; // [11:11] Output compare 4 preload enableObject *oc4m; // [12:14] Output compare 4 modeObject *oc4ce; // [15:15] Output compare 4 clear enable} ccmr2_output; +// CCMR2_Input(Capture/compare mode register 2 (input mode)) bitfields. + struct { +Object *cc3s; // [0:1] Capture/compare 3 selectionObject *ic3psc; // [2:3] Input capture 3 prescalerObject *ic3f; // [4:7] Input capture 3 filterObject *cc4s; // [8:9] Capture/Compare 4 selectionObject *ic4psc; // [10:11] Input capture 4 prescalerObject *ic4f; // [12:15] Input capture 4 filter} ccmr2_input; +// CCER(Capture/compare enable register) bitfields. + struct { +Object *cc1e; // [0:0] Capture/Compare 1 output enableObject *cc1p; // [1:1] Capture/Compare 1 output PolarityObject *cc1ne; // [2:2] Capture/Compare 1 complementary output enableObject *cc1np; // [3:3] Capture/Compare 1 output PolarityObject *cc2e; // [4:4] Capture/Compare 2 output enableObject *cc2p; // [5:5] Capture/Compare 2 output PolarityObject *cc2ne; // [6:6] Capture/Compare 2 complementary output enableObject *cc2np; // [7:7] Capture/Compare 2 output PolarityObject *cc3e; // [8:8] Capture/Compare 3 output enableObject *cc3p; // [9:9] Capture/Compare 3 output PolarityObject *cc3ne; // [10:10] Capture/Compare 3 complementary output enableObject *cc3np; // [11:11] Capture/Compare 3 output PolarityObject *cc4e; // [12:12] Capture/Compare 4 output enableObject *cc4p; // [13:13] Capture/Compare 3 output Polarity} ccer; +// CNT(Counter) bitfields. + struct { +Object *cnt; // [0:15] Counter value} cnt; +// PSC(Prescaler) bitfields. + struct { +Object *psc; // [0:15] Prescaler value} psc; +// ARR(Auto-reload register) bitfields. + struct { +Object *arr; // [0:15] Auto-reload value} arr; +// RCR(Repetition counter register) bitfields. + struct { +Object *rep; // [0:7] Repetition counter value} rcr; +// CCR1(Capture/compare register 1) bitfields. + struct { +Object *ccr1; // [0:15] Capture/Compare 1 value} ccr1; +// CCR2(Capture/compare register 2) bitfields. + struct { +Object *ccr2; // [0:15] Capture/Compare 2 value} ccr2; +// CCR3(Capture/compare register 3) bitfields. + struct { +Object *ccr3; // [0:15] Capture/Compare 3 value} ccr3; +// CCR4(Capture/compare register 4) bitfields. + struct { +Object *ccr4; // [0:15] Capture/Compare 3 value} ccr4; +// BDTR(Break and dead-time register) bitfields. + struct { +Object *dtg; // [0:7] Dead-time generator setupObject *lock; // [8:9] Lock configurationObject *ossi; // [10:10] Off-state selection for Idle modeObject *ossr; // [11:11] Off-state selection for Run modeObject *bke; // [12:12] Break enableObject *bkp; // [13:13] Break polarityObject *aoe; // [14:14] Automatic output enableObject *moe; // [15:15] Main output enable} bdtr; +// DCR(DMA control register) bitfields. + struct { +Object *dba; // [0:4] DMA base addressObject *dbl; // [8:12] DMA burst length} dcr; +// DMAR(DMA address for full transfer) bitfields. + struct { +Object *dmab; // [0:15] DMA register for burst accesses} dmar; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM1State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM1_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim14.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim14.c new file mode 100644 index 0000000000..edcc0d38f1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim14.c @@ -0,0 +1,282 @@ +/* + * STM32- TIM14(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_tim14_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM14State *state = STM32_TIM14_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.dier= cm_object_get_child_by_name(obj, "DIER"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.egr= cm_object_get_child_by_name(obj, "EGR"); +state->u.f0.reg.ccmr1_output= cm_object_get_child_by_name(obj, "CCMR1_Output"); +state->u.f0.reg.ccmr1_input= cm_object_get_child_by_name(obj, "CCMR1_Input"); +state->u.f0.reg.ccer= cm_object_get_child_by_name(obj, "CCER"); +state->u.f0.reg.cnt= cm_object_get_child_by_name(obj, "CNT"); +state->u.f0.reg.psc= cm_object_get_child_by_name(obj, "PSC"); +state->u.f0.reg.arr= cm_object_get_child_by_name(obj, "ARR"); +state->u.f0.reg.ccr1= cm_object_get_child_by_name(obj, "CCR1"); +state->u.f0.reg.or_= cm_object_get_child_by_name(obj, "OR"); +// CR1bitfields. +state->u.f0.fld.cr1.cen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); +state->u.f0.fld.cr1.udis= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); +state->u.f0.fld.cr1.urs= cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); +state->u.f0.fld.cr1.arpe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); +state->u.f0.fld.cr1.ckd= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); +// DIERbitfields. +state->u.f0.fld.dier.uie= cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); +state->u.f0.fld.dier.cc1ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); +// SRbitfields. +state->u.f0.fld.sr.uif= cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); +state->u.f0.fld.sr.cc1if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); +state->u.f0.fld.sr.cc1of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); +// EGRbitfields. +state->u.f0.fld.egr.ug= cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); +state->u.f0.fld.egr.cc1g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); +// CCMR1_Outputbitfields. +state->u.f0.fld.ccmr1_output.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); +state->u.f0.fld.ccmr1_output.oc1fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); +state->u.f0.fld.ccmr1_output.oc1pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); +state->u.f0.fld.ccmr1_output.oc1m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); +// CCMR1_Inputbitfields. +state->u.f0.fld.ccmr1_input.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); +state->u.f0.fld.ccmr1_input.ic1psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); +state->u.f0.fld.ccmr1_input.ic1f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); +// CCERbitfields. +state->u.f0.fld.ccer.cc1e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); +state->u.f0.fld.ccer.cc1p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); +state->u.f0.fld.ccer.cc1np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); +// CNTbitfields. +state->u.f0.fld.cnt.cnt= cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); +// PSCbitfields. +state->u.f0.fld.psc.psc= cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); +// ARRbitfields. +state->u.f0.fld.arr.arr= cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); +// CCR1bitfields. +state->u.f0.fld.ccr1.ccr1= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); +// ORbitfields. +state->u.f0.fld.or_.rmp= cm_object_get_child_by_name(state->u.f0.reg.or_, "RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim14_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim14_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim14_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim14_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM14State *state = STM32_TIM14_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim14_is_enabled(Object *obj) +{ + STM32TIM14State *state = STM32_TIM14_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim14_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM14State *state = STM32_TIM14_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim14_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM14)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM14State *state = STM32_TIM14_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM14"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_tim14_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim14_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim14_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim14_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim14_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM14EN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim14_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM14); +} + +static void stm32_tim14_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim14_reset_callback; + dc->realize = stm32_tim14_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim14_is_enabled; +} + +static const TypeInfo stm32_tim14_type_info = { + .name = TYPE_STM32_TIM14, + .parent = TYPE_STM32_TIM14_PARENT, + .instance_init = stm32_tim14_instance_init_callback, + .instance_size = sizeof(STM32TIM14State), + .class_init = stm32_tim14_class_init_callback, + .class_size = sizeof(STM32TIM14Class) }; + +static void stm32_tim14_register_types(void) +{ + type_register_static(&stm32_tim14_type_info); +} + +type_init(stm32_tim14_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim14.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim14.h new file mode 100644 index 0000000000..a3e781d071 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim14.h @@ -0,0 +1,145 @@ +/* + * STM32- TIM14(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM14_H_ +#define STM32_TIM14_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM14DEVICE_PATH_STM32"TIM14" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM14TYPE_STM32_PREFIX "tim14" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM14_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM14ParentClass; +typedef PeripheralState STM32TIM14ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM14_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM14Class, (obj), TYPE_STM32_TIM14) +#define STM32_TIM14_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM14Class, (klass), TYPE_STM32_TIM14) + +typedef struct { + // private: + STM32TIM14ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM14Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM14_STATE(obj) \ + OBJECT_CHECK(STM32TIM14State, (obj), TYPE_STM32_TIM14) + +typedef struct { + // private: + STM32TIM14ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0TIM14(General-purpose-timers) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *dier; // 0xC(DMA/Interrupt enable register) +Object *sr; // 0x10(Status register) +Object *egr; // 0x14(Event generation register) +Object *ccmr1_output; // 0x18(Capture/compare mode register (output mode)) +Object *ccmr1_input; // 0x18(Capture/compare mode register (input mode)) +Object *ccer; // 0x20(Capture/compare enable register) +Object *cnt; // 0x24(Counter) +Object *psc; // 0x28(Prescaler) +Object *arr; // 0x2C(Auto-reload register) +Object *ccr1; // 0x34(Capture/compare register 1) +Object *or_; // 0x50(Option register) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *cen; // [0:0] Counter enableObject *udis; // [1:1] Update disableObject *urs; // [2:2] Update request sourceObject *arpe; // [7:7] Auto-reload preload enableObject *ckd; // [8:9] Clock division} cr1; +// DIER(DMA/Interrupt enable register) bitfields. + struct { +Object *uie; // [0:0] Update interrupt enableObject *cc1ie; // [1:1] Capture/Compare 1 interrupt enable} dier; +// SR(Status register) bitfields. + struct { +Object *uif; // [0:0] Update interrupt flagObject *cc1if; // [1:1] Capture/compare 1 interrupt flagObject *cc1of; // [9:9] Capture/Compare 1 overcapture flag} sr; +// EGR(Event generation register) bitfields. + struct { +Object *ug; // [0:0] Update generationObject *cc1g; // [1:1] Capture/compare 1 generation} egr; +// CCMR1_Output(Capture/compare mode register (output mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *oc1fe; // [2:2] Output compare 1 fast enableObject *oc1pe; // [3:3] Output Compare 1 preload enableObject *oc1m; // [4:6] Output Compare 1 mode} ccmr1_output; +// CCMR1_Input(Capture/compare mode register (input mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *ic1psc; // [2:3] Input capture 1 prescalerObject *ic1f; // [4:7] Input capture 1 filter} ccmr1_input; +// CCER(Capture/compare enable register) bitfields. + struct { +Object *cc1e; // [0:0] Capture/Compare 1 output enableObject *cc1p; // [1:1] Capture/Compare 1 output PolarityObject *cc1np; // [3:3] Capture/Compare 1 output Polarity} ccer; +// CNT(Counter) bitfields. + struct { +Object *cnt; // [0:15] Counter value} cnt; +// PSC(Prescaler) bitfields. + struct { +Object *psc; // [0:15] Prescaler value} psc; +// ARR(Auto-reload register) bitfields. + struct { +Object *arr; // [0:15] Auto-reload value} arr; +// CCR1(Capture/compare register 1) bitfields. + struct { +Object *ccr1; // [0:15] Capture/Compare 1 value} ccr1; +// OR(Option register) bitfields. + struct { +Object *rmp; // [0:1] Timer input 1 remap} or_; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM14State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM14_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim15.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim15.c new file mode 100644 index 0000000000..18b95a90d0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim15.c @@ -0,0 +1,345 @@ +/* + * STM32- TIM15(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_tim15_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM15State *state = STM32_TIM15_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.smcr= cm_object_get_child_by_name(obj, "SMCR"); +state->u.f0.reg.dier= cm_object_get_child_by_name(obj, "DIER"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.egr= cm_object_get_child_by_name(obj, "EGR"); +state->u.f0.reg.ccmr1_output= cm_object_get_child_by_name(obj, "CCMR1_Output"); +state->u.f0.reg.ccmr1_input= cm_object_get_child_by_name(obj, "CCMR1_Input"); +state->u.f0.reg.ccer= cm_object_get_child_by_name(obj, "CCER"); +state->u.f0.reg.cnt= cm_object_get_child_by_name(obj, "CNT"); +state->u.f0.reg.psc= cm_object_get_child_by_name(obj, "PSC"); +state->u.f0.reg.arr= cm_object_get_child_by_name(obj, "ARR"); +state->u.f0.reg.rcr= cm_object_get_child_by_name(obj, "RCR"); +state->u.f0.reg.ccr1= cm_object_get_child_by_name(obj, "CCR1"); +state->u.f0.reg.ccr2= cm_object_get_child_by_name(obj, "CCR2"); +state->u.f0.reg.bdtr= cm_object_get_child_by_name(obj, "BDTR"); +state->u.f0.reg.dcr= cm_object_get_child_by_name(obj, "DCR"); +state->u.f0.reg.dmar= cm_object_get_child_by_name(obj, "DMAR"); +// CR1bitfields. +state->u.f0.fld.cr1.cen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); +state->u.f0.fld.cr1.udis= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); +state->u.f0.fld.cr1.urs= cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); +state->u.f0.fld.cr1.opm= cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); +state->u.f0.fld.cr1.arpe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); +state->u.f0.fld.cr1.ckd= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); +// CR2bitfields. +state->u.f0.fld.cr2.ccpc= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCPC"); +state->u.f0.fld.cr2.ccus= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCUS"); +state->u.f0.fld.cr2.ccds= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); +state->u.f0.fld.cr2.mms= cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); +state->u.f0.fld.cr2.ois1= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1"); +state->u.f0.fld.cr2.ois1n= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1N"); +state->u.f0.fld.cr2.ois2= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS2"); +// SMCRbitfields. +state->u.f0.fld.smcr.sms= cm_object_get_child_by_name(state->u.f0.reg.smcr, "SMS"); +state->u.f0.fld.smcr.ts= cm_object_get_child_by_name(state->u.f0.reg.smcr, "TS"); +state->u.f0.fld.smcr.msm= cm_object_get_child_by_name(state->u.f0.reg.smcr, "MSM"); +// DIERbitfields. +state->u.f0.fld.dier.uie= cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); +state->u.f0.fld.dier.cc1ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); +state->u.f0.fld.dier.cc2ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2IE"); +state->u.f0.fld.dier.comie= cm_object_get_child_by_name(state->u.f0.reg.dier, "COMIE"); +state->u.f0.fld.dier.tie= cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); +state->u.f0.fld.dier.bie= cm_object_get_child_by_name(state->u.f0.reg.dier, "BIE"); +state->u.f0.fld.dier.ude= cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); +state->u.f0.fld.dier.cc1de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); +state->u.f0.fld.dier.cc2de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2DE"); +state->u.f0.fld.dier.tde= cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); +// SRbitfields. +state->u.f0.fld.sr.uif= cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); +state->u.f0.fld.sr.cc1if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); +state->u.f0.fld.sr.cc2if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2IF"); +state->u.f0.fld.sr.comif= cm_object_get_child_by_name(state->u.f0.reg.sr, "COMIF"); +state->u.f0.fld.sr.tif= cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); +state->u.f0.fld.sr.bif= cm_object_get_child_by_name(state->u.f0.reg.sr, "BIF"); +state->u.f0.fld.sr.cc1of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); +state->u.f0.fld.sr.cc2of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2OF"); +// EGRbitfields. +state->u.f0.fld.egr.ug= cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); +state->u.f0.fld.egr.cc1g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); +state->u.f0.fld.egr.cc2g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC2G"); +state->u.f0.fld.egr.comg= cm_object_get_child_by_name(state->u.f0.reg.egr, "COMG"); +state->u.f0.fld.egr.tg= cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); +state->u.f0.fld.egr.bg= cm_object_get_child_by_name(state->u.f0.reg.egr, "BG"); +// CCMR1_Outputbitfields. +state->u.f0.fld.ccmr1_output.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); +state->u.f0.fld.ccmr1_output.oc1fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); +state->u.f0.fld.ccmr1_output.oc1pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); +state->u.f0.fld.ccmr1_output.oc1m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); +state->u.f0.fld.ccmr1_output.cc2s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC2S"); +state->u.f0.fld.ccmr1_output.oc2fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2FE"); +state->u.f0.fld.ccmr1_output.oc2pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2PE"); +state->u.f0.fld.ccmr1_output.oc2m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2M"); +// CCMR1_Inputbitfields. +state->u.f0.fld.ccmr1_input.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); +state->u.f0.fld.ccmr1_input.ic1psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); +state->u.f0.fld.ccmr1_input.ic1f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); +state->u.f0.fld.ccmr1_input.cc2s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC2S"); +state->u.f0.fld.ccmr1_input.ic2psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2PSC"); +state->u.f0.fld.ccmr1_input.ic2f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2F"); +// CCERbitfields. +state->u.f0.fld.ccer.cc1e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); +state->u.f0.fld.ccer.cc1p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); +state->u.f0.fld.ccer.cc1ne= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NE"); +state->u.f0.fld.ccer.cc1np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); +state->u.f0.fld.ccer.cc2e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2E"); +state->u.f0.fld.ccer.cc2p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2P"); +state->u.f0.fld.ccer.cc2np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NP"); +// CNTbitfields. +state->u.f0.fld.cnt.cnt= cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); +// PSCbitfields. +state->u.f0.fld.psc.psc= cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); +// ARRbitfields. +state->u.f0.fld.arr.arr= cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); +// RCRbitfields. +state->u.f0.fld.rcr.rep= cm_object_get_child_by_name(state->u.f0.reg.rcr, "REP"); +// CCR1bitfields. +state->u.f0.fld.ccr1.ccr1= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); +// CCR2bitfields. +state->u.f0.fld.ccr2.ccr2= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2"); +// BDTRbitfields. +state->u.f0.fld.bdtr.dtg= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "DTG"); +state->u.f0.fld.bdtr.lock= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "LOCK"); +state->u.f0.fld.bdtr.ossi= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSI"); +state->u.f0.fld.bdtr.ossr= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSR"); +state->u.f0.fld.bdtr.bke= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKE"); +state->u.f0.fld.bdtr.bkp= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKP"); +state->u.f0.fld.bdtr.aoe= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "AOE"); +state->u.f0.fld.bdtr.moe= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "MOE"); +// DCRbitfields. +state->u.f0.fld.dcr.dba= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); +state->u.f0.fld.dcr.dbl= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); +// DMARbitfields. +state->u.f0.fld.dmar.dmab= cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim15_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim15_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim15_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim15_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM15State *state = STM32_TIM15_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim15_is_enabled(Object *obj) +{ + STM32TIM15State *state = STM32_TIM15_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim15_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM15State *state = STM32_TIM15_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim15_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM15)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM15State *state = STM32_TIM15_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM15"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_tim15_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim15_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim15_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim15_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim15_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM15EN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim15_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM15); +} + +static void stm32_tim15_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim15_reset_callback; + dc->realize = stm32_tim15_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim15_is_enabled; +} + +static const TypeInfo stm32_tim15_type_info = { + .name = TYPE_STM32_TIM15, + .parent = TYPE_STM32_TIM15_PARENT, + .instance_init = stm32_tim15_instance_init_callback, + .instance_size = sizeof(STM32TIM15State), + .class_init = stm32_tim15_class_init_callback, + .class_size = sizeof(STM32TIM15Class) }; + +static void stm32_tim15_register_types(void) +{ + type_register_static(&stm32_tim15_type_info); +} + +type_init(stm32_tim15_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim15.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim15.h new file mode 100644 index 0000000000..da8b160d17 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim15.h @@ -0,0 +1,169 @@ +/* + * STM32- TIM15(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM15_H_ +#define STM32_TIM15_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM15DEVICE_PATH_STM32"TIM15" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM15TYPE_STM32_PREFIX "tim15" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM15_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM15ParentClass; +typedef PeripheralState STM32TIM15ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM15_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM15Class, (obj), TYPE_STM32_TIM15) +#define STM32_TIM15_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM15Class, (klass), TYPE_STM32_TIM15) + +typedef struct { + // private: + STM32TIM15ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM15Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM15_STATE(obj) \ + OBJECT_CHECK(STM32TIM15State, (obj), TYPE_STM32_TIM15) + +typedef struct { + // private: + STM32TIM15ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0TIM15(General-purpose-timers) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *smcr; // 0x8(Slave mode control register) +Object *dier; // 0xC(DMA/Interrupt enable register) +Object *sr; // 0x10(Status register) +Object *egr; // 0x14(Event generation register) +Object *ccmr1_output; // 0x18(Capture/compare mode register (output mode)) +Object *ccmr1_input; // 0x18(Capture/compare mode register 1 (input mode)) +Object *ccer; // 0x20(Capture/compare enable register) +Object *cnt; // 0x24(Counter) +Object *psc; // 0x28(Prescaler) +Object *arr; // 0x2C(Auto-reload register) +Object *rcr; // 0x30(Repetition counter register) +Object *ccr1; // 0x34(Capture/compare register 1) +Object *ccr2; // 0x38(Capture/compare register 2) +Object *bdtr; // 0x44(Break and dead-time register) +Object *dcr; // 0x48(DMA control register) +Object *dmar; // 0x4C(DMA address for full transfer) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *cen; // [0:0] Counter enableObject *udis; // [1:1] Update disableObject *urs; // [2:2] Update request sourceObject *opm; // [3:3] One-pulse modeObject *arpe; // [7:7] Auto-reload preload enableObject *ckd; // [8:9] Clock division} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *ccpc; // [0:0] Capture/compare preloaded controlObject *ccus; // [2:2] Capture/compare control update selectionObject *ccds; // [3:3] Capture/compare DMA selectionObject *mms; // [4:6] Master mode selectionObject *ois1; // [8:8] Output Idle state 1Object *ois1n; // [9:9] Output Idle state 1Object *ois2; // [10:10] Output Idle state 2} cr2; +// SMCR(Slave mode control register) bitfields. + struct { +Object *sms; // [0:2] Slave mode selectionObject *ts; // [4:6] Trigger selectionObject *msm; // [7:7] Master/Slave mode} smcr; +// DIER(DMA/Interrupt enable register) bitfields. + struct { +Object *uie; // [0:0] Update interrupt enableObject *cc1ie; // [1:1] Capture/Compare 1 interrupt enableObject *cc2ie; // [2:2] Capture/Compare 2 interrupt enableObject *comie; // [5:5] COM interrupt enableObject *tie; // [6:6] Trigger interrupt enableObject *bie; // [7:7] Break interrupt enableObject *ude; // [8:8] Update DMA request enableObject *cc1de; // [9:9] Capture/Compare 1 DMA request enableObject *cc2de; // [10:10] Capture/Compare 2 DMA request enableObject *tde; // [14:14] Trigger DMA request enable} dier; +// SR(Status register) bitfields. + struct { +Object *uif; // [0:0] Update interrupt flagObject *cc1if; // [1:1] Capture/compare 1 interrupt flagObject *cc2if; // [2:2] Capture/Compare 2 interrupt flagObject *comif; // [5:5] COM interrupt flagObject *tif; // [6:6] Trigger interrupt flagObject *bif; // [7:7] Break interrupt flagObject *cc1of; // [9:9] Capture/Compare 1 overcapture flagObject *cc2of; // [10:10] Capture/compare 2 overcapture flag} sr; +// EGR(Event generation register) bitfields. + struct { +Object *ug; // [0:0] Update generationObject *cc1g; // [1:1] Capture/compare 1 generationObject *cc2g; // [2:2] Capture/compare 2 generationObject *comg; // [5:5] Capture/Compare control update generationObject *tg; // [6:6] Trigger generationObject *bg; // [7:7] Break generation} egr; +// CCMR1_Output(Capture/compare mode register (output mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *oc1fe; // [2:2] Output Compare 1 fast enableObject *oc1pe; // [3:3] Output Compare 1 preload enableObject *oc1m; // [4:6] Output Compare 1 modeObject *cc2s; // [8:9] Capture/Compare 2 selectionObject *oc2fe; // [10:10] Output Compare 2 fast enableObject *oc2pe; // [11:11] Output Compare 2 preload enableObject *oc2m; // [12:14] Output Compare 2 mode} ccmr1_output; +// CCMR1_Input(Capture/compare mode register 1 (input mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *ic1psc; // [2:3] Input capture 1 prescalerObject *ic1f; // [4:7] Input capture 1 filterObject *cc2s; // [8:9] Capture/Compare 2 selectionObject *ic2psc; // [10:11] Input capture 2 prescalerObject *ic2f; // [12:15] Input capture 2 filter} ccmr1_input; +// CCER(Capture/compare enable register) bitfields. + struct { +Object *cc1e; // [0:0] Capture/Compare 1 output enableObject *cc1p; // [1:1] Capture/Compare 1 output PolarityObject *cc1ne; // [2:2] Capture/Compare 1 complementary output enableObject *cc1np; // [3:3] Capture/Compare 1 output PolarityObject *cc2e; // [4:4] Capture/Compare 2 output enableObject *cc2p; // [5:5] Capture/Compare 2 output PolarityObject *cc2np; // [7:7] Capture/Compare 2 output Polarity} ccer; +// CNT(Counter) bitfields. + struct { +Object *cnt; // [0:15] Counter value} cnt; +// PSC(Prescaler) bitfields. + struct { +Object *psc; // [0:15] Prescaler value} psc; +// ARR(Auto-reload register) bitfields. + struct { +Object *arr; // [0:15] Auto-reload value} arr; +// RCR(Repetition counter register) bitfields. + struct { +Object *rep; // [0:7] Repetition counter value} rcr; +// CCR1(Capture/compare register 1) bitfields. + struct { +Object *ccr1; // [0:15] Capture/Compare 1 value} ccr1; +// CCR2(Capture/compare register 2) bitfields. + struct { +Object *ccr2; // [0:15] Capture/Compare 2 value} ccr2; +// BDTR(Break and dead-time register) bitfields. + struct { +Object *dtg; // [0:7] Dead-time generator setupObject *lock; // [8:9] Lock configurationObject *ossi; // [10:10] Off-state selection for Idle modeObject *ossr; // [11:11] Off-state selection for Run modeObject *bke; // [12:12] Break enableObject *bkp; // [13:13] Break polarityObject *aoe; // [14:14] Automatic output enableObject *moe; // [15:15] Main output enable} bdtr; +// DCR(DMA control register) bitfields. + struct { +Object *dba; // [0:4] DMA base addressObject *dbl; // [8:12] DMA burst length} dcr; +// DMAR(DMA address for full transfer) bitfields. + struct { +Object *dmab; // [0:15] DMA register for burst accesses} dmar; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM15State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM15_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim16.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim16.c new file mode 100644 index 0000000000..5ac371fb19 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim16.c @@ -0,0 +1,320 @@ +/* + * STM32- TIM16(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_tim16_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM16State *state = STM32_TIM16_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.dier= cm_object_get_child_by_name(obj, "DIER"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.egr= cm_object_get_child_by_name(obj, "EGR"); +state->u.f0.reg.ccmr1_output= cm_object_get_child_by_name(obj, "CCMR1_Output"); +state->u.f0.reg.ccmr1_input= cm_object_get_child_by_name(obj, "CCMR1_Input"); +state->u.f0.reg.ccer= cm_object_get_child_by_name(obj, "CCER"); +state->u.f0.reg.cnt= cm_object_get_child_by_name(obj, "CNT"); +state->u.f0.reg.psc= cm_object_get_child_by_name(obj, "PSC"); +state->u.f0.reg.arr= cm_object_get_child_by_name(obj, "ARR"); +state->u.f0.reg.rcr= cm_object_get_child_by_name(obj, "RCR"); +state->u.f0.reg.ccr1= cm_object_get_child_by_name(obj, "CCR1"); +state->u.f0.reg.bdtr= cm_object_get_child_by_name(obj, "BDTR"); +state->u.f0.reg.dcr= cm_object_get_child_by_name(obj, "DCR"); +state->u.f0.reg.dmar= cm_object_get_child_by_name(obj, "DMAR"); +// CR1bitfields. +state->u.f0.fld.cr1.cen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); +state->u.f0.fld.cr1.udis= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); +state->u.f0.fld.cr1.urs= cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); +state->u.f0.fld.cr1.opm= cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); +state->u.f0.fld.cr1.arpe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); +state->u.f0.fld.cr1.ckd= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); +// CR2bitfields. +state->u.f0.fld.cr2.ccpc= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCPC"); +state->u.f0.fld.cr2.ccus= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCUS"); +state->u.f0.fld.cr2.ccds= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); +state->u.f0.fld.cr2.ois1= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1"); +state->u.f0.fld.cr2.ois1n= cm_object_get_child_by_name(state->u.f0.reg.cr2, "OIS1N"); +// DIERbitfields. +state->u.f0.fld.dier.uie= cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); +state->u.f0.fld.dier.cc1ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); +state->u.f0.fld.dier.comie= cm_object_get_child_by_name(state->u.f0.reg.dier, "COMIE"); +state->u.f0.fld.dier.tie= cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); +state->u.f0.fld.dier.bie= cm_object_get_child_by_name(state->u.f0.reg.dier, "BIE"); +state->u.f0.fld.dier.ude= cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); +state->u.f0.fld.dier.cc1de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); +state->u.f0.fld.dier.tde= cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); +// SRbitfields. +state->u.f0.fld.sr.uif= cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); +state->u.f0.fld.sr.cc1if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); +state->u.f0.fld.sr.comif= cm_object_get_child_by_name(state->u.f0.reg.sr, "COMIF"); +state->u.f0.fld.sr.tif= cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); +state->u.f0.fld.sr.bif= cm_object_get_child_by_name(state->u.f0.reg.sr, "BIF"); +state->u.f0.fld.sr.cc1of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); +// EGRbitfields. +state->u.f0.fld.egr.ug= cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); +state->u.f0.fld.egr.cc1g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); +state->u.f0.fld.egr.comg= cm_object_get_child_by_name(state->u.f0.reg.egr, "COMG"); +state->u.f0.fld.egr.tg= cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); +state->u.f0.fld.egr.bg= cm_object_get_child_by_name(state->u.f0.reg.egr, "BG"); +// CCMR1_Outputbitfields. +state->u.f0.fld.ccmr1_output.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); +state->u.f0.fld.ccmr1_output.oc1fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); +state->u.f0.fld.ccmr1_output.oc1pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); +state->u.f0.fld.ccmr1_output.oc1m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); +// CCMR1_Inputbitfields. +state->u.f0.fld.ccmr1_input.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); +state->u.f0.fld.ccmr1_input.ic1psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); +state->u.f0.fld.ccmr1_input.ic1f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); +// CCERbitfields. +state->u.f0.fld.ccer.cc1e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); +state->u.f0.fld.ccer.cc1p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); +state->u.f0.fld.ccer.cc1ne= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NE"); +state->u.f0.fld.ccer.cc1np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); +// CNTbitfields. +state->u.f0.fld.cnt.cnt= cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); +// PSCbitfields. +state->u.f0.fld.psc.psc= cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); +// ARRbitfields. +state->u.f0.fld.arr.arr= cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); +// RCRbitfields. +state->u.f0.fld.rcr.rep= cm_object_get_child_by_name(state->u.f0.reg.rcr, "REP"); +// CCR1bitfields. +state->u.f0.fld.ccr1.ccr1= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1"); +// BDTRbitfields. +state->u.f0.fld.bdtr.dtg= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "DTG"); +state->u.f0.fld.bdtr.lock= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "LOCK"); +state->u.f0.fld.bdtr.ossi= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSI"); +state->u.f0.fld.bdtr.ossr= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "OSSR"); +state->u.f0.fld.bdtr.bke= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKE"); +state->u.f0.fld.bdtr.bkp= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "BKP"); +state->u.f0.fld.bdtr.aoe= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "AOE"); +state->u.f0.fld.bdtr.moe= cm_object_get_child_by_name(state->u.f0.reg.bdtr, "MOE"); +// DCRbitfields. +state->u.f0.fld.dcr.dba= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); +state->u.f0.fld.dcr.dbl= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); +// DMARbitfields. +state->u.f0.fld.dmar.dmab= cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim16_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim16_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim16_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim16_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM16State *state = STM32_TIM16_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim16_is_enabled(Object *obj) +{ + STM32TIM16State *state = STM32_TIM16_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim16_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM16State *state = STM32_TIM16_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim16_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM16)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM16State *state = STM32_TIM16_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM16"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_tim16_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim16_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim16_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim16_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim16_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM16EN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim16_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM16); +} + +static void stm32_tim16_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim16_reset_callback; + dc->realize = stm32_tim16_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim16_is_enabled; +} + +static const TypeInfo stm32_tim16_type_info = { + .name = TYPE_STM32_TIM16, + .parent = TYPE_STM32_TIM16_PARENT, + .instance_init = stm32_tim16_instance_init_callback, + .instance_size = sizeof(STM32TIM16State), + .class_init = stm32_tim16_class_init_callback, + .class_size = sizeof(STM32TIM16Class) }; + +static void stm32_tim16_register_types(void) +{ + type_register_static(&stm32_tim16_type_info); +} + +type_init(stm32_tim16_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim16.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim16.h new file mode 100644 index 0000000000..08f5bb1379 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim16.h @@ -0,0 +1,161 @@ +/* + * STM32- TIM16(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM16_H_ +#define STM32_TIM16_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM16DEVICE_PATH_STM32"TIM16" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM16TYPE_STM32_PREFIX "tim16" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM16_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM16ParentClass; +typedef PeripheralState STM32TIM16ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM16_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM16Class, (obj), TYPE_STM32_TIM16) +#define STM32_TIM16_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM16Class, (klass), TYPE_STM32_TIM16) + +typedef struct { + // private: + STM32TIM16ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM16Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM16_STATE(obj) \ + OBJECT_CHECK(STM32TIM16State, (obj), TYPE_STM32_TIM16) + +typedef struct { + // private: + STM32TIM16ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0TIM16(General-purpose-timers) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *dier; // 0xC(DMA/Interrupt enable register) +Object *sr; // 0x10(Status register) +Object *egr; // 0x14(Event generation register) +Object *ccmr1_output; // 0x18(Capture/compare mode register (output mode)) +Object *ccmr1_input; // 0x18(Capture/compare mode register 1 (input mode)) +Object *ccer; // 0x20(Capture/compare enable register) +Object *cnt; // 0x24(Counter) +Object *psc; // 0x28(Prescaler) +Object *arr; // 0x2C(Auto-reload register) +Object *rcr; // 0x30(Repetition counter register) +Object *ccr1; // 0x34(Capture/compare register 1) +Object *bdtr; // 0x44(Break and dead-time register) +Object *dcr; // 0x48(DMA control register) +Object *dmar; // 0x4C(DMA address for full transfer) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *cen; // [0:0] Counter enableObject *udis; // [1:1] Update disableObject *urs; // [2:2] Update request sourceObject *opm; // [3:3] One-pulse modeObject *arpe; // [7:7] Auto-reload preload enableObject *ckd; // [8:9] Clock division} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *ccpc; // [0:0] Capture/compare preloaded controlObject *ccus; // [2:2] Capture/compare control update selectionObject *ccds; // [3:3] Capture/compare DMA selectionObject *ois1; // [8:8] Output Idle state 1Object *ois1n; // [9:9] Output Idle state 1} cr2; +// DIER(DMA/Interrupt enable register) bitfields. + struct { +Object *uie; // [0:0] Update interrupt enableObject *cc1ie; // [1:1] Capture/Compare 1 interrupt enableObject *comie; // [5:5] COM interrupt enableObject *tie; // [6:6] Trigger interrupt enableObject *bie; // [7:7] Break interrupt enableObject *ude; // [8:8] Update DMA request enableObject *cc1de; // [9:9] Capture/Compare 1 DMA request enableObject *tde; // [14:14] Trigger DMA request enable} dier; +// SR(Status register) bitfields. + struct { +Object *uif; // [0:0] Update interrupt flagObject *cc1if; // [1:1] Capture/compare 1 interrupt flagObject *comif; // [5:5] COM interrupt flagObject *tif; // [6:6] Trigger interrupt flagObject *bif; // [7:7] Break interrupt flagObject *cc1of; // [9:9] Capture/Compare 1 overcapture flag} sr; +// EGR(Event generation register) bitfields. + struct { +Object *ug; // [0:0] Update generationObject *cc1g; // [1:1] Capture/compare 1 generationObject *comg; // [5:5] Capture/Compare control update generationObject *tg; // [6:6] Trigger generationObject *bg; // [7:7] Break generation} egr; +// CCMR1_Output(Capture/compare mode register (output mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *oc1fe; // [2:2] Output Compare 1 fast enableObject *oc1pe; // [3:3] Output Compare 1 preload enableObject *oc1m; // [4:6] Output Compare 1 mode} ccmr1_output; +// CCMR1_Input(Capture/compare mode register 1 (input mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *ic1psc; // [2:3] Input capture 1 prescalerObject *ic1f; // [4:7] Input capture 1 filter} ccmr1_input; +// CCER(Capture/compare enable register) bitfields. + struct { +Object *cc1e; // [0:0] Capture/Compare 1 output enableObject *cc1p; // [1:1] Capture/Compare 1 output PolarityObject *cc1ne; // [2:2] Capture/Compare 1 complementary output enableObject *cc1np; // [3:3] Capture/Compare 1 output Polarity} ccer; +// CNT(Counter) bitfields. + struct { +Object *cnt; // [0:15] Counter value} cnt; +// PSC(Prescaler) bitfields. + struct { +Object *psc; // [0:15] Prescaler value} psc; +// ARR(Auto-reload register) bitfields. + struct { +Object *arr; // [0:15] Auto-reload value} arr; +// RCR(Repetition counter register) bitfields. + struct { +Object *rep; // [0:7] Repetition counter value} rcr; +// CCR1(Capture/compare register 1) bitfields. + struct { +Object *ccr1; // [0:15] Capture/Compare 1 value} ccr1; +// BDTR(Break and dead-time register) bitfields. + struct { +Object *dtg; // [0:7] Dead-time generator setupObject *lock; // [8:9] Lock configurationObject *ossi; // [10:10] Off-state selection for Idle modeObject *ossr; // [11:11] Off-state selection for Run modeObject *bke; // [12:12] Break enableObject *bkp; // [13:13] Break polarityObject *aoe; // [14:14] Automatic output enableObject *moe; // [15:15] Main output enable} bdtr; +// DCR(DMA control register) bitfields. + struct { +Object *dba; // [0:4] DMA base addressObject *dbl; // [8:12] DMA burst length} dcr; +// DMAR(DMA address for full transfer) bitfields. + struct { +Object *dmab; // [0:15] DMA register for burst accesses} dmar; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM16State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM16_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim2.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim2.c new file mode 100644 index 0000000000..ccc86bddb3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim2.c @@ -0,0 +1,378 @@ +/* + * STM32- TIM2(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_tim2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.smcr= cm_object_get_child_by_name(obj, "SMCR"); +state->u.f0.reg.dier= cm_object_get_child_by_name(obj, "DIER"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.egr= cm_object_get_child_by_name(obj, "EGR"); +state->u.f0.reg.ccmr1_output= cm_object_get_child_by_name(obj, "CCMR1_Output"); +state->u.f0.reg.ccmr1_input= cm_object_get_child_by_name(obj, "CCMR1_Input"); +state->u.f0.reg.ccmr2_output= cm_object_get_child_by_name(obj, "CCMR2_Output"); +state->u.f0.reg.ccmr2_input= cm_object_get_child_by_name(obj, "CCMR2_Input"); +state->u.f0.reg.ccer= cm_object_get_child_by_name(obj, "CCER"); +state->u.f0.reg.cnt= cm_object_get_child_by_name(obj, "CNT"); +state->u.f0.reg.psc= cm_object_get_child_by_name(obj, "PSC"); +state->u.f0.reg.arr= cm_object_get_child_by_name(obj, "ARR"); +state->u.f0.reg.ccr1= cm_object_get_child_by_name(obj, "CCR1"); +state->u.f0.reg.ccr2= cm_object_get_child_by_name(obj, "CCR2"); +state->u.f0.reg.ccr3= cm_object_get_child_by_name(obj, "CCR3"); +state->u.f0.reg.ccr4= cm_object_get_child_by_name(obj, "CCR4"); +state->u.f0.reg.dcr= cm_object_get_child_by_name(obj, "DCR"); +state->u.f0.reg.dmar= cm_object_get_child_by_name(obj, "DMAR"); +// CR1bitfields. +state->u.f0.fld.cr1.cen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); +state->u.f0.fld.cr1.udis= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); +state->u.f0.fld.cr1.urs= cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); +state->u.f0.fld.cr1.opm= cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); +state->u.f0.fld.cr1.dir= cm_object_get_child_by_name(state->u.f0.reg.cr1, "DIR"); +state->u.f0.fld.cr1.cms= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CMS"); +state->u.f0.fld.cr1.arpe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); +state->u.f0.fld.cr1.ckd= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CKD"); +// CR2bitfields. +state->u.f0.fld.cr2.ccds= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CCDS"); +state->u.f0.fld.cr2.mms= cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); +state->u.f0.fld.cr2.ti1s= cm_object_get_child_by_name(state->u.f0.reg.cr2, "TI1S"); +// SMCRbitfields. +state->u.f0.fld.smcr.sms= cm_object_get_child_by_name(state->u.f0.reg.smcr, "SMS"); +state->u.f0.fld.smcr.ts= cm_object_get_child_by_name(state->u.f0.reg.smcr, "TS"); +state->u.f0.fld.smcr.msm= cm_object_get_child_by_name(state->u.f0.reg.smcr, "MSM"); +state->u.f0.fld.smcr.etf= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETF"); +state->u.f0.fld.smcr.etps= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETPS"); +state->u.f0.fld.smcr.ece= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ECE"); +state->u.f0.fld.smcr.etp= cm_object_get_child_by_name(state->u.f0.reg.smcr, "ETP"); +// DIERbitfields. +state->u.f0.fld.dier.uie= cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); +state->u.f0.fld.dier.cc1ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1IE"); +state->u.f0.fld.dier.cc2ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2IE"); +state->u.f0.fld.dier.cc3ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3IE"); +state->u.f0.fld.dier.cc4ie= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4IE"); +state->u.f0.fld.dier.tie= cm_object_get_child_by_name(state->u.f0.reg.dier, "TIE"); +state->u.f0.fld.dier.ude= cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); +state->u.f0.fld.dier.cc1de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC1DE"); +state->u.f0.fld.dier.cc2de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC2DE"); +state->u.f0.fld.dier.cc3de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC3DE"); +state->u.f0.fld.dier.cc4de= cm_object_get_child_by_name(state->u.f0.reg.dier, "CC4DE"); +state->u.f0.fld.dier.comde= cm_object_get_child_by_name(state->u.f0.reg.dier, "COMDE"); +state->u.f0.fld.dier.tde= cm_object_get_child_by_name(state->u.f0.reg.dier, "TDE"); +// SRbitfields. +state->u.f0.fld.sr.uif= cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); +state->u.f0.fld.sr.cc1if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1IF"); +state->u.f0.fld.sr.cc2if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2IF"); +state->u.f0.fld.sr.cc3if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3IF"); +state->u.f0.fld.sr.cc4if= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4IF"); +state->u.f0.fld.sr.tif= cm_object_get_child_by_name(state->u.f0.reg.sr, "TIF"); +state->u.f0.fld.sr.cc1of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC1OF"); +state->u.f0.fld.sr.cc2of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC2OF"); +state->u.f0.fld.sr.cc3of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC3OF"); +state->u.f0.fld.sr.cc4of= cm_object_get_child_by_name(state->u.f0.reg.sr, "CC4OF"); +// EGRbitfields. +state->u.f0.fld.egr.ug= cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); +state->u.f0.fld.egr.cc1g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC1G"); +state->u.f0.fld.egr.cc2g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC2G"); +state->u.f0.fld.egr.cc3g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC3G"); +state->u.f0.fld.egr.cc4g= cm_object_get_child_by_name(state->u.f0.reg.egr, "CC4G"); +state->u.f0.fld.egr.tg= cm_object_get_child_by_name(state->u.f0.reg.egr, "TG"); +// CCMR1_Outputbitfields. +state->u.f0.fld.ccmr1_output.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC1S"); +state->u.f0.fld.ccmr1_output.oc1fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1FE"); +state->u.f0.fld.ccmr1_output.oc1pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1PE"); +state->u.f0.fld.ccmr1_output.oc1m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1M"); +state->u.f0.fld.ccmr1_output.oc1ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC1CE"); +state->u.f0.fld.ccmr1_output.cc2s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "CC2S"); +state->u.f0.fld.ccmr1_output.oc2fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2FE"); +state->u.f0.fld.ccmr1_output.oc2pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2PE"); +state->u.f0.fld.ccmr1_output.oc2m= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2M"); +state->u.f0.fld.ccmr1_output.oc2ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_output, "OC2CE"); +// CCMR1_Inputbitfields. +state->u.f0.fld.ccmr1_input.cc1s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC1S"); +state->u.f0.fld.ccmr1_input.ic1psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1PSC"); +state->u.f0.fld.ccmr1_input.ic1f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC1F"); +state->u.f0.fld.ccmr1_input.cc2s= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "CC2S"); +state->u.f0.fld.ccmr1_input.ic2psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2PSC"); +state->u.f0.fld.ccmr1_input.ic2f= cm_object_get_child_by_name(state->u.f0.reg.ccmr1_input, "IC2F"); +// CCMR2_Outputbitfields. +state->u.f0.fld.ccmr2_output.cc3s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC3S"); +state->u.f0.fld.ccmr2_output.oc3fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3FE"); +state->u.f0.fld.ccmr2_output.oc3pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3PE"); +state->u.f0.fld.ccmr2_output.oc3m= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3M"); +state->u.f0.fld.ccmr2_output.oc3ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC3CE"); +state->u.f0.fld.ccmr2_output.cc4s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "CC4S"); +state->u.f0.fld.ccmr2_output.oc4fe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4FE"); +state->u.f0.fld.ccmr2_output.oc4pe= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4PE"); +state->u.f0.fld.ccmr2_output.oc4m= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4M"); +state->u.f0.fld.ccmr2_output.oc4ce= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_output, "OC4CE"); +// CCMR2_Inputbitfields. +state->u.f0.fld.ccmr2_input.cc3s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC3S"); +state->u.f0.fld.ccmr2_input.ic3psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3PSC"); +state->u.f0.fld.ccmr2_input.ic3f= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC3F"); +state->u.f0.fld.ccmr2_input.cc4s= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "CC4S"); +state->u.f0.fld.ccmr2_input.ic4psc= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4PSC"); +state->u.f0.fld.ccmr2_input.ic4f= cm_object_get_child_by_name(state->u.f0.reg.ccmr2_input, "IC4F"); +// CCERbitfields. +state->u.f0.fld.ccer.cc1e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1E"); +state->u.f0.fld.ccer.cc1p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1P"); +state->u.f0.fld.ccer.cc1np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC1NP"); +state->u.f0.fld.ccer.cc2e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2E"); +state->u.f0.fld.ccer.cc2p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2P"); +state->u.f0.fld.ccer.cc2np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC2NP"); +state->u.f0.fld.ccer.cc3e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3E"); +state->u.f0.fld.ccer.cc3p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3P"); +state->u.f0.fld.ccer.cc3np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC3NP"); +state->u.f0.fld.ccer.cc4e= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4E"); +state->u.f0.fld.ccer.cc4p= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4P"); +state->u.f0.fld.ccer.cc4np= cm_object_get_child_by_name(state->u.f0.reg.ccer, "CC4NP"); +// CNTbitfields. +state->u.f0.fld.cnt.cnt_l= cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT_L"); +state->u.f0.fld.cnt.cnt_h= cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT_H"); +// PSCbitfields. +state->u.f0.fld.psc.psc= cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); +// ARRbitfields. +state->u.f0.fld.arr.arr_l= cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR_L"); +state->u.f0.fld.arr.arr_h= cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR_H"); +// CCR1bitfields. +state->u.f0.fld.ccr1.ccr1_l= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1_L"); +state->u.f0.fld.ccr1.ccr1_h= cm_object_get_child_by_name(state->u.f0.reg.ccr1, "CCR1_H"); +// CCR2bitfields. +state->u.f0.fld.ccr2.ccr2_l= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2_L"); +state->u.f0.fld.ccr2.ccr2_h= cm_object_get_child_by_name(state->u.f0.reg.ccr2, "CCR2_H"); +// CCR3bitfields. +state->u.f0.fld.ccr3.ccr3_l= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CCR3_L"); +state->u.f0.fld.ccr3.ccr3_h= cm_object_get_child_by_name(state->u.f0.reg.ccr3, "CCR3_H"); +// CCR4bitfields. +state->u.f0.fld.ccr4.ccr4_l= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CCR4_L"); +state->u.f0.fld.ccr4.ccr4_h= cm_object_get_child_by_name(state->u.f0.reg.ccr4, "CCR4_H"); +// DCRbitfields. +state->u.f0.fld.dcr.dba= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBA"); +state->u.f0.fld.dcr.dbl= cm_object_get_child_by_name(state->u.f0.reg.dcr, "DBL"); +// DMARbitfields. +state->u.f0.fld.dmar.dmar= cm_object_get_child_by_name(state->u.f0.reg.dmar, "DMAR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim2_is_enabled(Object *obj) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM2State *state = STM32_TIM2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_tim2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim2_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM2EN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM2); +} + +static void stm32_tim2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim2_reset_callback; + dc->realize = stm32_tim2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim2_is_enabled; +} + +static const TypeInfo stm32_tim2_type_info = { + .name = TYPE_STM32_TIM2, + .parent = TYPE_STM32_TIM2_PARENT, + .instance_init = stm32_tim2_instance_init_callback, + .instance_size = sizeof(STM32TIM2State), + .class_init = stm32_tim2_class_init_callback, + .class_size = sizeof(STM32TIM2Class) }; + +static void stm32_tim2_register_types(void) +{ + type_register_static(&stm32_tim2_type_info); +} + +type_init(stm32_tim2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim2.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim2.h new file mode 100644 index 0000000000..bace94d0ae --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim2.h @@ -0,0 +1,177 @@ +/* + * STM32- TIM2(General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM2_H_ +#define STM32_TIM2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM2DEVICE_PATH_STM32"TIM2" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM2TYPE_STM32_PREFIX "tim2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM2ParentClass; +typedef PeripheralState STM32TIM2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM2Class, (obj), TYPE_STM32_TIM2) +#define STM32_TIM2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM2Class, (klass), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM2_STATE(obj) \ + OBJECT_CHECK(STM32TIM2State, (obj), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0TIM2(General-purpose-timers) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *smcr; // 0x8(Slave mode control register) +Object *dier; // 0xC(DMA/Interrupt enable register) +Object *sr; // 0x10(Status register) +Object *egr; // 0x14(Event generation register) +Object *ccmr1_output; // 0x18(Capture/compare mode register 1 (output mode)) +Object *ccmr1_input; // 0x18(Capture/compare mode register 1 (input mode)) +Object *ccmr2_output; // 0x1C(Capture/compare mode register 2 (output mode)) +Object *ccmr2_input; // 0x1C(Capture/compare mode register 2 (input mode)) +Object *ccer; // 0x20(Capture/compare enable register) +Object *cnt; // 0x24(Counter) +Object *psc; // 0x28(Prescaler) +Object *arr; // 0x2C(Auto-reload register) +Object *ccr1; // 0x34(Capture/compare register 1) +Object *ccr2; // 0x38(Capture/compare register 2) +Object *ccr3; // 0x3C(Capture/compare register 3) +Object *ccr4; // 0x40(Capture/compare register 4) +Object *dcr; // 0x48(DMA control register) +Object *dmar; // 0x4C(DMA address for full transfer) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *cen; // [0:0] Counter enableObject *udis; // [1:1] Update disableObject *urs; // [2:2] Update request sourceObject *opm; // [3:3] One-pulse modeObject *dir; // [4:4] DirectionObject *cms; // [5:6] Center-aligned mode selectionObject *arpe; // [7:7] Auto-reload preload enableObject *ckd; // [8:9] Clock division} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *ccds; // [3:3] Capture/compare DMA selectionObject *mms; // [4:6] Master mode selectionObject *ti1s; // [7:7] TI1 selection} cr2; +// SMCR(Slave mode control register) bitfields. + struct { +Object *sms; // [0:2] Slave mode selectionObject *ts; // [4:6] Trigger selectionObject *msm; // [7:7] Master/Slave modeObject *etf; // [8:11] External trigger filterObject *etps; // [12:13] External trigger prescalerObject *ece; // [14:14] External clock enableObject *etp; // [15:15] External trigger polarity} smcr; +// DIER(DMA/Interrupt enable register) bitfields. + struct { +Object *uie; // [0:0] Update interrupt enableObject *cc1ie; // [1:1] Capture/Compare 1 interrupt enableObject *cc2ie; // [2:2] Capture/Compare 2 interrupt enableObject *cc3ie; // [3:3] Capture/Compare 3 interrupt enableObject *cc4ie; // [4:4] Capture/Compare 4 interrupt enableObject *tie; // [6:6] Trigger interrupt enableObject *ude; // [8:8] Update DMA request enableObject *cc1de; // [9:9] Capture/Compare 1 DMA request enableObject *cc2de; // [10:10] Capture/Compare 2 DMA request enableObject *cc3de; // [11:11] Capture/Compare 3 DMA request enableObject *cc4de; // [12:12] Capture/Compare 4 DMA request enableObject *comde; // [13:13] ReservedObject *tde; // [14:14] Trigger DMA request enable} dier; +// SR(Status register) bitfields. + struct { +Object *uif; // [0:0] Update interrupt flagObject *cc1if; // [1:1] Capture/compare 1 interrupt flagObject *cc2if; // [2:2] Capture/Compare 2 interrupt flagObject *cc3if; // [3:3] Capture/Compare 3 interrupt flagObject *cc4if; // [4:4] Capture/Compare 4 interrupt flagObject *tif; // [6:6] Trigger interrupt flagObject *cc1of; // [9:9] Capture/Compare 1 overcapture flagObject *cc2of; // [10:10] Capture/compare 2 overcapture flagObject *cc3of; // [11:11] Capture/Compare 3 overcapture flagObject *cc4of; // [12:12] Capture/Compare 4 overcapture flag} sr; +// EGR(Event generation register) bitfields. + struct { +Object *ug; // [0:0] Update generationObject *cc1g; // [1:1] Capture/compare 1 generationObject *cc2g; // [2:2] Capture/compare 2 generationObject *cc3g; // [3:3] Capture/compare 3 generationObject *cc4g; // [4:4] Capture/compare 4 generationObject *tg; // [6:6] Trigger generation} egr; +// CCMR1_Output(Capture/compare mode register 1 (output mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *oc1fe; // [2:2] Output compare 1 fast enableObject *oc1pe; // [3:3] Output compare 1 preload enableObject *oc1m; // [4:6] Output compare 1 modeObject *oc1ce; // [7:7] Output compare 1 clear enableObject *cc2s; // [8:9] Capture/Compare 2 selectionObject *oc2fe; // [10:10] Output compare 2 fast enableObject *oc2pe; // [11:11] Output compare 2 preload enableObject *oc2m; // [12:14] Output compare 2 modeObject *oc2ce; // [15:15] Output compare 2 clear enable} ccmr1_output; +// CCMR1_Input(Capture/compare mode register 1 (input mode)) bitfields. + struct { +Object *cc1s; // [0:1] Capture/Compare 1 selectionObject *ic1psc; // [2:3] Input capture 1 prescalerObject *ic1f; // [4:7] Input capture 1 filterObject *cc2s; // [8:9] Capture/compare 2 selectionObject *ic2psc; // [10:11] Input capture 2 prescalerObject *ic2f; // [12:15] Input capture 2 filter} ccmr1_input; +// CCMR2_Output(Capture/compare mode register 2 (output mode)) bitfields. + struct { +Object *cc3s; // [0:1] Capture/Compare 3 selectionObject *oc3fe; // [2:2] Output compare 3 fast enableObject *oc3pe; // [3:3] Output compare 3 preload enableObject *oc3m; // [4:6] Output compare 3 modeObject *oc3ce; // [7:7] Output compare 3 clear enableObject *cc4s; // [8:9] Capture/Compare 4 selectionObject *oc4fe; // [10:10] Output compare 4 fast enableObject *oc4pe; // [11:11] Output compare 4 preload enableObject *oc4m; // [12:14] Output compare 4 modeObject *oc4ce; // [15:15] Output compare 4 clear enable} ccmr2_output; +// CCMR2_Input(Capture/compare mode register 2 (input mode)) bitfields. + struct { +Object *cc3s; // [0:1] Capture/Compare 3 selectionObject *ic3psc; // [2:3] Input capture 3 prescalerObject *ic3f; // [4:7] Input capture 3 filterObject *cc4s; // [8:9] Capture/Compare 4 selectionObject *ic4psc; // [10:11] Input capture 4 prescalerObject *ic4f; // [12:15] Input capture 4 filter} ccmr2_input; +// CCER(Capture/compare enable register) bitfields. + struct { +Object *cc1e; // [0:0] Capture/Compare 1 output enableObject *cc1p; // [1:1] Capture/Compare 1 output PolarityObject *cc1np; // [3:3] Capture/Compare 1 output PolarityObject *cc2e; // [4:4] Capture/Compare 2 output enableObject *cc2p; // [5:5] Capture/Compare 2 output PolarityObject *cc2np; // [7:7] Capture/Compare 2 output PolarityObject *cc3e; // [8:8] Capture/Compare 3 output enableObject *cc3p; // [9:9] Capture/Compare 3 output PolarityObject *cc3np; // [11:11] Capture/Compare 3 output PolarityObject *cc4e; // [12:12] Capture/Compare 4 output enableObject *cc4p; // [13:13] Capture/Compare 3 output PolarityObject *cc4np; // [15:15] Capture/Compare 4 output Polarity} ccer; +// CNT(Counter) bitfields. + struct { +Object *cnt_l; // [0:15] Low counter valueObject *cnt_h; // [16:31] High counter value (TIM2 only)} cnt; +// PSC(Prescaler) bitfields. + struct { +Object *psc; // [0:15] Prescaler value} psc; +// ARR(Auto-reload register) bitfields. + struct { +Object *arr_l; // [0:15] Low Auto-reload valueObject *arr_h; // [16:31] High Auto-reload value (TIM2 only)} arr; +// CCR1(Capture/compare register 1) bitfields. + struct { +Object *ccr1_l; // [0:15] Low Capture/Compare 1 valueObject *ccr1_h; // [16:31] High Capture/Compare 1 value (TIM2 only)} ccr1; +// CCR2(Capture/compare register 2) bitfields. + struct { +Object *ccr2_l; // [0:15] Low Capture/Compare 2 valueObject *ccr2_h; // [16:31] High Capture/Compare 2 value (TIM2 only)} ccr2; +// CCR3(Capture/compare register 3) bitfields. + struct { +Object *ccr3_l; // [0:15] Low Capture/Compare valueObject *ccr3_h; // [16:31] High Capture/Compare value (TIM2 only)} ccr3; +// CCR4(Capture/compare register 4) bitfields. + struct { +Object *ccr4_l; // [0:15] Low Capture/Compare valueObject *ccr4_h; // [16:31] High Capture/Compare value (TIM2 only)} ccr4; +// DCR(DMA control register) bitfields. + struct { +Object *dba; // [0:4] DMA base addressObject *dbl; // [8:12] DMA burst length} dcr; +// DMAR(DMA address for full transfer) bitfields. + struct { +Object *dmar; // [0:15] DMA register for burst accesses} dmar; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim6.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim6.c new file mode 100644 index 0000000000..8d415882ef --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim6.c @@ -0,0 +1,260 @@ +/* + * STM32- TIM6(Basic-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_tim6_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.dier= cm_object_get_child_by_name(obj, "DIER"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +state->u.f0.reg.egr= cm_object_get_child_by_name(obj, "EGR"); +state->u.f0.reg.cnt= cm_object_get_child_by_name(obj, "CNT"); +state->u.f0.reg.psc= cm_object_get_child_by_name(obj, "PSC"); +state->u.f0.reg.arr= cm_object_get_child_by_name(obj, "ARR"); +// CR1bitfields. +state->u.f0.fld.cr1.cen= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CEN"); +state->u.f0.fld.cr1.udis= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UDIS"); +state->u.f0.fld.cr1.urs= cm_object_get_child_by_name(state->u.f0.reg.cr1, "URS"); +state->u.f0.fld.cr1.opm= cm_object_get_child_by_name(state->u.f0.reg.cr1, "OPM"); +state->u.f0.fld.cr1.arpe= cm_object_get_child_by_name(state->u.f0.reg.cr1, "ARPE"); +// CR2bitfields. +state->u.f0.fld.cr2.mms= cm_object_get_child_by_name(state->u.f0.reg.cr2, "MMS"); +// DIERbitfields. +state->u.f0.fld.dier.uie= cm_object_get_child_by_name(state->u.f0.reg.dier, "UIE"); +state->u.f0.fld.dier.ude= cm_object_get_child_by_name(state->u.f0.reg.dier, "UDE"); +// SRbitfields. +state->u.f0.fld.sr.uif= cm_object_get_child_by_name(state->u.f0.reg.sr, "UIF"); +// EGRbitfields. +state->u.f0.fld.egr.ug= cm_object_get_child_by_name(state->u.f0.reg.egr, "UG"); +// CNTbitfields. +state->u.f0.fld.cnt.cnt= cm_object_get_child_by_name(state->u.f0.reg.cnt, "CNT"); +// PSCbitfields. +state->u.f0.fld.psc.psc= cm_object_get_child_by_name(state->u.f0.reg.psc, "PSC"); +// ARRbitfields. +state->u.f0.fld.arr.arr= cm_object_get_child_by_name(state->u.f0.reg.arr, "ARR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim6_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim6_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim6_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim6_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim6_is_enabled(Object *obj) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim6_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim6_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM6)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM6State *state = STM32_TIM6_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM6"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_tim6_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim6_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tim6_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tim6_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tim6_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM6EN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim6_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM6); +} + +static void stm32_tim6_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim6_reset_callback; + dc->realize = stm32_tim6_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim6_is_enabled; +} + +static const TypeInfo stm32_tim6_type_info = { + .name = TYPE_STM32_TIM6, + .parent = TYPE_STM32_TIM6_PARENT, + .instance_init = stm32_tim6_instance_init_callback, + .instance_size = sizeof(STM32TIM6State), + .class_init = stm32_tim6_class_init_callback, + .class_size = sizeof(STM32TIM6Class) }; + +static void stm32_tim6_register_types(void) +{ + type_register_static(&stm32_tim6_type_info); +} + +type_init(stm32_tim6_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tim6.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim6.h new file mode 100644 index 0000000000..93dfa3083e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tim6.h @@ -0,0 +1,129 @@ +/* + * STM32- TIM6(Basic-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM6_H_ +#define STM32_TIM6_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM6DEVICE_PATH_STM32"TIM6" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM6TYPE_STM32_PREFIX "tim6" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM6_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM6ParentClass; +typedef PeripheralState STM32TIM6ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM6_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM6Class, (obj), TYPE_STM32_TIM6) +#define STM32_TIM6_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM6Class, (klass), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM6Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM6_STATE(obj) \ + OBJECT_CHECK(STM32TIM6State, (obj), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0TIM6(Basic-timers) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *dier; // 0xC(DMA/Interrupt enable register) +Object *sr; // 0x10(Status register) +Object *egr; // 0x14(Event generation register) +Object *cnt; // 0x24(Counter) +Object *psc; // 0x28(Prescaler) +Object *arr; // 0x2C(Auto-reload register) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *cen; // [0:0] Counter enableObject *udis; // [1:1] Update disableObject *urs; // [2:2] Update request sourceObject *opm; // [3:3] One-pulse modeObject *arpe; // [7:7] Auto-reload preload enable} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *mms; // [4:6] Master mode selection} cr2; +// DIER(DMA/Interrupt enable register) bitfields. + struct { +Object *uie; // [0:0] Update interrupt enableObject *ude; // [8:8] Update DMA request enable} dier; +// SR(Status register) bitfields. + struct { +Object *uif; // [0:0] Update interrupt flag} sr; +// EGR(Event generation register) bitfields. + struct { +Object *ug; // [0:0] Update generation} egr; +// CNT(Counter) bitfields. + struct { +Object *cnt; // [0:15] Low counter value} cnt; +// PSC(Prescaler) bitfields. + struct { +Object *psc; // [0:15] Prescaler value} psc; +// ARR(Auto-reload register) bitfields. + struct { +Object *arr; // [0:15] Low Auto-reload value} arr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM6State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM6_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tsc.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/tsc.c new file mode 100644 index 0000000000..4d30b286e7 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tsc.c @@ -0,0 +1,397 @@ +/* + * STM32- TSC(Touch sensing controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_tsc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TSCState *state = STM32_TSC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.ier= cm_object_get_child_by_name(obj, "IER"); +state->u.f0.reg.icr= cm_object_get_child_by_name(obj, "ICR"); +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.iohcr= cm_object_get_child_by_name(obj, "IOHCR"); +state->u.f0.reg.ioascr= cm_object_get_child_by_name(obj, "IOASCR"); +state->u.f0.reg.ioscr= cm_object_get_child_by_name(obj, "IOSCR"); +state->u.f0.reg.ioccr= cm_object_get_child_by_name(obj, "IOCCR"); +state->u.f0.reg.iogcsr= cm_object_get_child_by_name(obj, "IOGCSR"); +state->u.f0.reg.iog1cr= cm_object_get_child_by_name(obj, "IOG1CR"); +state->u.f0.reg.iog2cr= cm_object_get_child_by_name(obj, "IOG2CR"); +state->u.f0.reg.iog3cr= cm_object_get_child_by_name(obj, "IOG3CR"); +state->u.f0.reg.iog4cr= cm_object_get_child_by_name(obj, "IOG4CR"); +state->u.f0.reg.iog5cr= cm_object_get_child_by_name(obj, "IOG5CR"); +state->u.f0.reg.iog6cr= cm_object_get_child_by_name(obj, "IOG6CR"); +// CRbitfields. +state->u.f0.fld.cr.tsce= cm_object_get_child_by_name(state->u.f0.reg.cr, "TSCE"); +state->u.f0.fld.cr.start= cm_object_get_child_by_name(state->u.f0.reg.cr, "START"); +state->u.f0.fld.cr.am= cm_object_get_child_by_name(state->u.f0.reg.cr, "AM"); +state->u.f0.fld.cr.syncpol= cm_object_get_child_by_name(state->u.f0.reg.cr, "SYNCPOL"); +state->u.f0.fld.cr.iodef= cm_object_get_child_by_name(state->u.f0.reg.cr, "IODEF"); +state->u.f0.fld.cr.mcv= cm_object_get_child_by_name(state->u.f0.reg.cr, "MCV"); +state->u.f0.fld.cr.pgpsc= cm_object_get_child_by_name(state->u.f0.reg.cr, "PGPSC"); +state->u.f0.fld.cr.sspsc= cm_object_get_child_by_name(state->u.f0.reg.cr, "SSPSC"); +state->u.f0.fld.cr.sse= cm_object_get_child_by_name(state->u.f0.reg.cr, "SSE"); +state->u.f0.fld.cr.ssd= cm_object_get_child_by_name(state->u.f0.reg.cr, "SSD"); +state->u.f0.fld.cr.ctpl= cm_object_get_child_by_name(state->u.f0.reg.cr, "CTPL"); +state->u.f0.fld.cr.ctph= cm_object_get_child_by_name(state->u.f0.reg.cr, "CTPH"); +// IERbitfields. +state->u.f0.fld.ier.eoaie= cm_object_get_child_by_name(state->u.f0.reg.ier, "EOAIE"); +state->u.f0.fld.ier.mceie= cm_object_get_child_by_name(state->u.f0.reg.ier, "MCEIE"); +// ICRbitfields. +state->u.f0.fld.icr.eoaic= cm_object_get_child_by_name(state->u.f0.reg.icr, "EOAIC"); +state->u.f0.fld.icr.mceic= cm_object_get_child_by_name(state->u.f0.reg.icr, "MCEIC"); +// ISRbitfields. +state->u.f0.fld.isr.eoaf= cm_object_get_child_by_name(state->u.f0.reg.isr, "EOAF"); +state->u.f0.fld.isr.mcef= cm_object_get_child_by_name(state->u.f0.reg.isr, "MCEF"); +// IOHCRbitfields. +state->u.f0.fld.iohcr.g1_io1= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO1"); +state->u.f0.fld.iohcr.g1_io2= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO2"); +state->u.f0.fld.iohcr.g1_io3= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO3"); +state->u.f0.fld.iohcr.g1_io4= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G1_IO4"); +state->u.f0.fld.iohcr.g2_io1= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO1"); +state->u.f0.fld.iohcr.g2_io2= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO2"); +state->u.f0.fld.iohcr.g2_io3= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO3"); +state->u.f0.fld.iohcr.g2_io4= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G2_IO4"); +state->u.f0.fld.iohcr.g3_io1= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO1"); +state->u.f0.fld.iohcr.g3_io2= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO2"); +state->u.f0.fld.iohcr.g3_io3= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO3"); +state->u.f0.fld.iohcr.g3_io4= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G3_IO4"); +state->u.f0.fld.iohcr.g4_io1= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO1"); +state->u.f0.fld.iohcr.g4_io2= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO2"); +state->u.f0.fld.iohcr.g4_io3= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO3"); +state->u.f0.fld.iohcr.g4_io4= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G4_IO4"); +state->u.f0.fld.iohcr.g5_io1= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO1"); +state->u.f0.fld.iohcr.g5_io2= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO2"); +state->u.f0.fld.iohcr.g5_io3= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO3"); +state->u.f0.fld.iohcr.g5_io4= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G5_IO4"); +state->u.f0.fld.iohcr.g6_io1= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO1"); +state->u.f0.fld.iohcr.g6_io2= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO2"); +state->u.f0.fld.iohcr.g6_io3= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO3"); +state->u.f0.fld.iohcr.g6_io4= cm_object_get_child_by_name(state->u.f0.reg.iohcr, "G6_IO4"); +// IOASCRbitfields. +state->u.f0.fld.ioascr.g1_io1= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO1"); +state->u.f0.fld.ioascr.g1_io2= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO2"); +state->u.f0.fld.ioascr.g1_io3= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO3"); +state->u.f0.fld.ioascr.g1_io4= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G1_IO4"); +state->u.f0.fld.ioascr.g2_io1= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO1"); +state->u.f0.fld.ioascr.g2_io2= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO2"); +state->u.f0.fld.ioascr.g2_io3= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO3"); +state->u.f0.fld.ioascr.g2_io4= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G2_IO4"); +state->u.f0.fld.ioascr.g3_io1= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO1"); +state->u.f0.fld.ioascr.g3_io2= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO2"); +state->u.f0.fld.ioascr.g3_io3= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO3"); +state->u.f0.fld.ioascr.g3_io4= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G3_IO4"); +state->u.f0.fld.ioascr.g4_io1= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO1"); +state->u.f0.fld.ioascr.g4_io2= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO2"); +state->u.f0.fld.ioascr.g4_io3= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO3"); +state->u.f0.fld.ioascr.g4_io4= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G4_IO4"); +state->u.f0.fld.ioascr.g5_io1= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO1"); +state->u.f0.fld.ioascr.g5_io2= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO2"); +state->u.f0.fld.ioascr.g5_io3= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO3"); +state->u.f0.fld.ioascr.g5_io4= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G5_IO4"); +state->u.f0.fld.ioascr.g6_io1= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO1"); +state->u.f0.fld.ioascr.g6_io2= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO2"); +state->u.f0.fld.ioascr.g6_io3= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO3"); +state->u.f0.fld.ioascr.g6_io4= cm_object_get_child_by_name(state->u.f0.reg.ioascr, "G6_IO4"); +// IOSCRbitfields. +state->u.f0.fld.ioscr.g1_io1= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO1"); +state->u.f0.fld.ioscr.g1_io2= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO2"); +state->u.f0.fld.ioscr.g1_io3= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO3"); +state->u.f0.fld.ioscr.g1_io4= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G1_IO4"); +state->u.f0.fld.ioscr.g2_io1= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO1"); +state->u.f0.fld.ioscr.g2_io2= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO2"); +state->u.f0.fld.ioscr.g2_io3= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO3"); +state->u.f0.fld.ioscr.g2_io4= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G2_IO4"); +state->u.f0.fld.ioscr.g3_io1= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO1"); +state->u.f0.fld.ioscr.g3_io2= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO2"); +state->u.f0.fld.ioscr.g3_io3= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO3"); +state->u.f0.fld.ioscr.g3_io4= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G3_IO4"); +state->u.f0.fld.ioscr.g4_io1= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO1"); +state->u.f0.fld.ioscr.g4_io2= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO2"); +state->u.f0.fld.ioscr.g4_io3= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO3"); +state->u.f0.fld.ioscr.g4_io4= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G4_IO4"); +state->u.f0.fld.ioscr.g5_io1= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO1"); +state->u.f0.fld.ioscr.g5_io2= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO2"); +state->u.f0.fld.ioscr.g5_io3= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO3"); +state->u.f0.fld.ioscr.g5_io4= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G5_IO4"); +state->u.f0.fld.ioscr.g6_io1= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO1"); +state->u.f0.fld.ioscr.g6_io2= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO2"); +state->u.f0.fld.ioscr.g6_io3= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO3"); +state->u.f0.fld.ioscr.g6_io4= cm_object_get_child_by_name(state->u.f0.reg.ioscr, "G6_IO4"); +// IOCCRbitfields. +state->u.f0.fld.ioccr.g1_io1= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO1"); +state->u.f0.fld.ioccr.g1_io2= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO2"); +state->u.f0.fld.ioccr.g1_io3= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO3"); +state->u.f0.fld.ioccr.g1_io4= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G1_IO4"); +state->u.f0.fld.ioccr.g2_io1= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO1"); +state->u.f0.fld.ioccr.g2_io2= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO2"); +state->u.f0.fld.ioccr.g2_io3= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO3"); +state->u.f0.fld.ioccr.g2_io4= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G2_IO4"); +state->u.f0.fld.ioccr.g3_io1= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO1"); +state->u.f0.fld.ioccr.g3_io2= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO2"); +state->u.f0.fld.ioccr.g3_io3= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO3"); +state->u.f0.fld.ioccr.g3_io4= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G3_IO4"); +state->u.f0.fld.ioccr.g4_io1= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO1"); +state->u.f0.fld.ioccr.g4_io2= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO2"); +state->u.f0.fld.ioccr.g4_io3= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO3"); +state->u.f0.fld.ioccr.g4_io4= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G4_IO4"); +state->u.f0.fld.ioccr.g5_io1= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO1"); +state->u.f0.fld.ioccr.g5_io2= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO2"); +state->u.f0.fld.ioccr.g5_io3= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO3"); +state->u.f0.fld.ioccr.g5_io4= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G5_IO4"); +state->u.f0.fld.ioccr.g6_io1= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO1"); +state->u.f0.fld.ioccr.g6_io2= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO2"); +state->u.f0.fld.ioccr.g6_io3= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO3"); +state->u.f0.fld.ioccr.g6_io4= cm_object_get_child_by_name(state->u.f0.reg.ioccr, "G6_IO4"); +// IOGCSRbitfields. +state->u.f0.fld.iogcsr.g1e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G1E"); +state->u.f0.fld.iogcsr.g2e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G2E"); +state->u.f0.fld.iogcsr.g3e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G3E"); +state->u.f0.fld.iogcsr.g4e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G4E"); +state->u.f0.fld.iogcsr.g5e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G5E"); +state->u.f0.fld.iogcsr.g6e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G6E"); +state->u.f0.fld.iogcsr.g7e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G7E"); +state->u.f0.fld.iogcsr.g8e= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G8E"); +state->u.f0.fld.iogcsr.g1s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G1S"); +state->u.f0.fld.iogcsr.g2s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G2S"); +state->u.f0.fld.iogcsr.g3s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G3S"); +state->u.f0.fld.iogcsr.g4s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G4S"); +state->u.f0.fld.iogcsr.g5s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G5S"); +state->u.f0.fld.iogcsr.g6s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G6S"); +state->u.f0.fld.iogcsr.g7s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G7S"); +state->u.f0.fld.iogcsr.g8s= cm_object_get_child_by_name(state->u.f0.reg.iogcsr, "G8S"); +// IOG1CRbitfields. +state->u.f0.fld.iog1cr.cnt= cm_object_get_child_by_name(state->u.f0.reg.iog1cr, "CNT"); +// IOG2CRbitfields. +state->u.f0.fld.iog2cr.cnt= cm_object_get_child_by_name(state->u.f0.reg.iog2cr, "CNT"); +// IOG3CRbitfields. +state->u.f0.fld.iog3cr.cnt= cm_object_get_child_by_name(state->u.f0.reg.iog3cr, "CNT"); +// IOG4CRbitfields. +state->u.f0.fld.iog4cr.cnt= cm_object_get_child_by_name(state->u.f0.reg.iog4cr, "CNT"); +// IOG5CRbitfields. +state->u.f0.fld.iog5cr.cnt= cm_object_get_child_by_name(state->u.f0.reg.iog5cr, "CNT"); +// IOG6CRbitfields. +state->u.f0.fld.iog6cr.cnt= cm_object_get_child_by_name(state->u.f0.reg.iog6cr, "CNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tsc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tsc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tsc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tsc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TSCState *state = STM32_TSC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tsc_is_enabled(Object *obj) +{ + STM32TSCState *state = STM32_TSC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tsc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TSCState *state = STM32_TSC_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tsc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TSC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TSCState *state = STM32_TSC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TSC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_tsc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tsc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_tsc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_tsc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_tsc_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TSCEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tsc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TSC); +} + +static void stm32_tsc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tsc_reset_callback; + dc->realize = stm32_tsc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tsc_is_enabled; +} + +static const TypeInfo stm32_tsc_type_info = { + .name = TYPE_STM32_TSC, + .parent = TYPE_STM32_TSC_PARENT, + .instance_init = stm32_tsc_instance_init_callback, + .instance_size = sizeof(STM32TSCState), + .class_init = stm32_tsc_class_init_callback, + .class_size = sizeof(STM32TSCClass) }; + +static void stm32_tsc_register_types(void) +{ + type_register_static(&stm32_tsc_type_info); +} + +type_init(stm32_tsc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/tsc.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/tsc.h new file mode 100644 index 0000000000..b373886d30 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/tsc.h @@ -0,0 +1,157 @@ +/* + * STM32- TSC(Touch sensing controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TSC_H_ +#define STM32_TSC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TSCDEVICE_PATH_STM32"TSC" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TSCTYPE_STM32_PREFIX "tsc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TSC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TSCParentClass; +typedef PeripheralState STM32TSCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TSC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TSCClass, (obj), TYPE_STM32_TSC) +#define STM32_TSC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TSCClass, (klass), TYPE_STM32_TSC) + +typedef struct { + // private: + STM32TSCParentClass parent_class; + // public: + + // None, so far. +} STM32TSCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TSC_STATE(obj) \ + OBJECT_CHECK(STM32TSCState, (obj), TYPE_STM32_TSC) + +typedef struct { + // private: + STM32TSCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0TSC(Touch sensing controller) registers. + struct { +Object *cr; // 0x0(Control register) +Object *ier; // 0x4(Interrupt enable register) +Object *icr; // 0x8(Interrupt clear register) +Object *isr; // 0xC(Interrupt status register) +Object *iohcr; // 0x10(I/O hysteresis control register) +Object *ioascr; // 0x18(I/O analog switch control register) +Object *ioscr; // 0x20(I/O sampling control register) +Object *ioccr; // 0x28(I/O channel control register) +Object *iogcsr; // 0x30(I/O group control status register) +Object *iog1cr; // 0x34(I/O group x counter register) +Object *iog2cr; // 0x38(I/O group x counter register) +Object *iog3cr; // 0x3C(I/O group x counter register) +Object *iog4cr; // 0x40(I/O group x counter register) +Object *iog5cr; // 0x44(I/O group x counter register) +Object *iog6cr; // 0x48(I/O group x counter register) +} reg; + + struct { +// CR(Control register) bitfields. + struct { +Object *tsce; // [0:0] Touch sensing controller enableObject *start; // [1:1] Start a new acquisitionObject *am; // [2:2] Acquisition modeObject *syncpol; // [3:3] Synchronization pin polarityObject *iodef; // [4:4] I/O Default modeObject *mcv; // [5:7] Max count valueObject *pgpsc; // [12:14] Pulse generator prescalerObject *sspsc; // [15:15] Spread spectrum prescalerObject *sse; // [16:16] Spread spectrum enableObject *ssd; // [17:23] Spread spectrum deviationObject *ctpl; // [24:27] Charge transfer pulse lowObject *ctph; // [28:31] Charge transfer pulse high} cr; +// IER(Interrupt enable register) bitfields. + struct { +Object *eoaie; // [0:0] End of acquisition interrupt enableObject *mceie; // [1:1] Max count error interrupt enable} ier; +// ICR(Interrupt clear register) bitfields. + struct { +Object *eoaic; // [0:0] End of acquisition interrupt clearObject *mceic; // [1:1] Max count error interrupt clear} icr; +// ISR(Interrupt status register) bitfields. + struct { +Object *eoaf; // [0:0] End of acquisition flagObject *mcef; // [1:1] Max count error flag} isr; +// IOHCR(I/O hysteresis control register) bitfields. + struct { +Object *g1_io1; // [0:0] G1_IO1 Schmitt trigger hysteresis modeObject *g1_io2; // [1:1] G1_IO2 Schmitt trigger hysteresis modeObject *g1_io3; // [2:2] G1_IO3 Schmitt trigger hysteresis modeObject *g1_io4; // [3:3] G1_IO4 Schmitt trigger hysteresis modeObject *g2_io1; // [4:4] G2_IO1 Schmitt trigger hysteresis modeObject *g2_io2; // [5:5] G2_IO2 Schmitt trigger hysteresis modeObject *g2_io3; // [6:6] G2_IO3 Schmitt trigger hysteresis modeObject *g2_io4; // [7:7] G2_IO4 Schmitt trigger hysteresis modeObject *g3_io1; // [8:8] G3_IO1 Schmitt trigger hysteresis modeObject *g3_io2; // [9:9] G3_IO2 Schmitt trigger hysteresis modeObject *g3_io3; // [10:10] G3_IO3 Schmitt trigger hysteresis modeObject *g3_io4; // [11:11] G3_IO4 Schmitt trigger hysteresis modeObject *g4_io1; // [12:12] G4_IO1 Schmitt trigger hysteresis modeObject *g4_io2; // [13:13] G4_IO2 Schmitt trigger hysteresis modeObject *g4_io3; // [14:14] G4_IO3 Schmitt trigger hysteresis modeObject *g4_io4; // [15:15] G4_IO4 Schmitt trigger hysteresis modeObject *g5_io1; // [16:16] G5_IO1 Schmitt trigger hysteresis modeObject *g5_io2; // [17:17] G5_IO2 Schmitt trigger hysteresis modeObject *g5_io3; // [18:18] G5_IO3 Schmitt trigger hysteresis modeObject *g5_io4; // [19:19] G5_IO4 Schmitt trigger hysteresis modeObject *g6_io1; // [20:20] G6_IO1 Schmitt trigger hysteresis modeObject *g6_io2; // [21:21] G6_IO2 Schmitt trigger hysteresis modeObject *g6_io3; // [22:22] G6_IO3 Schmitt trigger hysteresis modeObject *g6_io4; // [23:23] G6_IO4 Schmitt trigger hysteresis mode} iohcr; +// IOASCR(I/O analog switch control register) bitfields. + struct { +Object *g1_io1; // [0:0] G1_IO1 analog switch enableObject *g1_io2; // [1:1] G1_IO2 analog switch enableObject *g1_io3; // [2:2] G1_IO3 analog switch enableObject *g1_io4; // [3:3] G1_IO4 analog switch enableObject *g2_io1; // [4:4] G2_IO1 analog switch enableObject *g2_io2; // [5:5] G2_IO2 analog switch enableObject *g2_io3; // [6:6] G2_IO3 analog switch enableObject *g2_io4; // [7:7] G2_IO4 analog switch enableObject *g3_io1; // [8:8] G3_IO1 analog switch enableObject *g3_io2; // [9:9] G3_IO2 analog switch enableObject *g3_io3; // [10:10] G3_IO3 analog switch enableObject *g3_io4; // [11:11] G3_IO4 analog switch enableObject *g4_io1; // [12:12] G4_IO1 analog switch enableObject *g4_io2; // [13:13] G4_IO2 analog switch enableObject *g4_io3; // [14:14] G4_IO3 analog switch enableObject *g4_io4; // [15:15] G4_IO4 analog switch enableObject *g5_io1; // [16:16] G5_IO1 analog switch enableObject *g5_io2; // [17:17] G5_IO2 analog switch enableObject *g5_io3; // [18:18] G5_IO3 analog switch enableObject *g5_io4; // [19:19] G5_IO4 analog switch enableObject *g6_io1; // [20:20] G6_IO1 analog switch enableObject *g6_io2; // [21:21] G6_IO2 analog switch enableObject *g6_io3; // [22:22] G6_IO3 analog switch enableObject *g6_io4; // [23:23] G6_IO4 analog switch enable} ioascr; +// IOSCR(I/O sampling control register) bitfields. + struct { +Object *g1_io1; // [0:0] G1_IO1 sampling modeObject *g1_io2; // [1:1] G1_IO2 sampling modeObject *g1_io3; // [2:2] G1_IO3 sampling modeObject *g1_io4; // [3:3] G1_IO4 sampling modeObject *g2_io1; // [4:4] G2_IO1 sampling modeObject *g2_io2; // [5:5] G2_IO2 sampling modeObject *g2_io3; // [6:6] G2_IO3 sampling modeObject *g2_io4; // [7:7] G2_IO4 sampling modeObject *g3_io1; // [8:8] G3_IO1 sampling modeObject *g3_io2; // [9:9] G3_IO2 sampling modeObject *g3_io3; // [10:10] G3_IO3 sampling modeObject *g3_io4; // [11:11] G3_IO4 sampling modeObject *g4_io1; // [12:12] G4_IO1 sampling modeObject *g4_io2; // [13:13] G4_IO2 sampling modeObject *g4_io3; // [14:14] G4_IO3 sampling modeObject *g4_io4; // [15:15] G4_IO4 sampling modeObject *g5_io1; // [16:16] G5_IO1 sampling modeObject *g5_io2; // [17:17] G5_IO2 sampling modeObject *g5_io3; // [18:18] G5_IO3 sampling modeObject *g5_io4; // [19:19] G5_IO4 sampling modeObject *g6_io1; // [20:20] G6_IO1 sampling modeObject *g6_io2; // [21:21] G6_IO2 sampling modeObject *g6_io3; // [22:22] G6_IO3 sampling modeObject *g6_io4; // [23:23] G6_IO4 sampling mode} ioscr; +// IOCCR(I/O channel control register) bitfields. + struct { +Object *g1_io1; // [0:0] G1_IO1 channel modeObject *g1_io2; // [1:1] G1_IO2 channel modeObject *g1_io3; // [2:2] G1_IO3 channel modeObject *g1_io4; // [3:3] G1_IO4 channel modeObject *g2_io1; // [4:4] G2_IO1 channel modeObject *g2_io2; // [5:5] G2_IO2 channel modeObject *g2_io3; // [6:6] G2_IO3 channel modeObject *g2_io4; // [7:7] G2_IO4 channel modeObject *g3_io1; // [8:8] G3_IO1 channel modeObject *g3_io2; // [9:9] G3_IO2 channel modeObject *g3_io3; // [10:10] G3_IO3 channel modeObject *g3_io4; // [11:11] G3_IO4 channel modeObject *g4_io1; // [12:12] G4_IO1 channel modeObject *g4_io2; // [13:13] G4_IO2 channel modeObject *g4_io3; // [14:14] G4_IO3 channel modeObject *g4_io4; // [15:15] G4_IO4 channel modeObject *g5_io1; // [16:16] G5_IO1 channel modeObject *g5_io2; // [17:17] G5_IO2 channel modeObject *g5_io3; // [18:18] G5_IO3 channel modeObject *g5_io4; // [19:19] G5_IO4 channel modeObject *g6_io1; // [20:20] G6_IO1 channel modeObject *g6_io2; // [21:21] G6_IO2 channel modeObject *g6_io3; // [22:22] G6_IO3 channel modeObject *g6_io4; // [23:23] G6_IO4 channel mode} ioccr; +// IOGCSR(I/O group control status register) bitfields. + struct { +Object *g1e; // [0:0] Analog I/O group x enableObject *g2e; // [1:1] Analog I/O group x enableObject *g3e; // [2:2] Analog I/O group x enableObject *g4e; // [3:3] Analog I/O group x enableObject *g5e; // [4:4] Analog I/O group x enableObject *g6e; // [5:5] Analog I/O group x enableObject *g7e; // [6:6] Analog I/O group x enableObject *g8e; // [7:7] Analog I/O group x enableObject *g1s; // [16:16] Analog I/O group x statusObject *g2s; // [17:17] Analog I/O group x statusObject *g3s; // [18:18] Analog I/O group x statusObject *g4s; // [19:19] Analog I/O group x statusObject *g5s; // [20:20] Analog I/O group x statusObject *g6s; // [21:21] Analog I/O group x statusObject *g7s; // [22:22] Analog I/O group x statusObject *g8s; // [23:23] Analog I/O group x status} iogcsr; +// IOG1CR(I/O group x counter register) bitfields. + struct { +Object *cnt; // [0:13] Counter value} iog1cr; +// IOG2CR(I/O group x counter register) bitfields. + struct { +Object *cnt; // [0:13] Counter value} iog2cr; +// IOG3CR(I/O group x counter register) bitfields. + struct { +Object *cnt; // [0:13] Counter value} iog3cr; +// IOG4CR(I/O group x counter register) bitfields. + struct { +Object *cnt; // [0:13] Counter value} iog4cr; +// IOG5CR(I/O group x counter register) bitfields. + struct { +Object *cnt; // [0:13] Counter value} iog5cr; +// IOG6CR(I/O group x counter register) bitfields. + struct { +Object *cnt; // [0:13] Counter value} iog6cr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TSCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TSC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/usart1.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/usart1.c new file mode 100644 index 0000000000..6229069a42 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/usart1.c @@ -0,0 +1,363 @@ +/* + * STM32- USART(Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_usart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr1= cm_object_get_child_by_name(obj, "CR1"); +state->u.f0.reg.cr2= cm_object_get_child_by_name(obj, "CR2"); +state->u.f0.reg.cr3= cm_object_get_child_by_name(obj, "CR3"); +state->u.f0.reg.brr= cm_object_get_child_by_name(obj, "BRR"); +state->u.f0.reg.gtpr= cm_object_get_child_by_name(obj, "GTPR"); +state->u.f0.reg.rtor= cm_object_get_child_by_name(obj, "RTOR"); +state->u.f0.reg.rqr= cm_object_get_child_by_name(obj, "RQR"); +state->u.f0.reg.isr= cm_object_get_child_by_name(obj, "ISR"); +state->u.f0.reg.icr= cm_object_get_child_by_name(obj, "ICR"); +state->u.f0.reg.rdr= cm_object_get_child_by_name(obj, "RDR"); +state->u.f0.reg.tdr= cm_object_get_child_by_name(obj, "TDR"); +// CR1bitfields. +state->u.f0.fld.cr1.ue= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UE"); +state->u.f0.fld.cr1.uesm= cm_object_get_child_by_name(state->u.f0.reg.cr1, "UESM"); +state->u.f0.fld.cr1.re= cm_object_get_child_by_name(state->u.f0.reg.cr1, "RE"); +state->u.f0.fld.cr1.te= cm_object_get_child_by_name(state->u.f0.reg.cr1, "TE"); +state->u.f0.fld.cr1.idleie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "IDLEIE"); +state->u.f0.fld.cr1.rxneie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "RXNEIE"); +state->u.f0.fld.cr1.tcie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "TCIE"); +state->u.f0.fld.cr1.txeie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "TXEIE"); +state->u.f0.fld.cr1.peie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "PEIE"); +state->u.f0.fld.cr1.ps= cm_object_get_child_by_name(state->u.f0.reg.cr1, "PS"); +state->u.f0.fld.cr1.pce= cm_object_get_child_by_name(state->u.f0.reg.cr1, "PCE"); +state->u.f0.fld.cr1.wake= cm_object_get_child_by_name(state->u.f0.reg.cr1, "WAKE"); +state->u.f0.fld.cr1.m= cm_object_get_child_by_name(state->u.f0.reg.cr1, "M"); +state->u.f0.fld.cr1.mme= cm_object_get_child_by_name(state->u.f0.reg.cr1, "MME"); +state->u.f0.fld.cr1.cmie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "CMIE"); +state->u.f0.fld.cr1.over8= cm_object_get_child_by_name(state->u.f0.reg.cr1, "OVER8"); +state->u.f0.fld.cr1.dedt= cm_object_get_child_by_name(state->u.f0.reg.cr1, "DEDT"); +state->u.f0.fld.cr1.deat= cm_object_get_child_by_name(state->u.f0.reg.cr1, "DEAT"); +state->u.f0.fld.cr1.rtoie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "RTOIE"); +state->u.f0.fld.cr1.eobie= cm_object_get_child_by_name(state->u.f0.reg.cr1, "EOBIE"); +state->u.f0.fld.cr1.m1= cm_object_get_child_by_name(state->u.f0.reg.cr1, "M1"); +// CR2bitfields. +state->u.f0.fld.cr2.addm7= cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADDM7"); +state->u.f0.fld.cr2.lbdl= cm_object_get_child_by_name(state->u.f0.reg.cr2, "LBDL"); +state->u.f0.fld.cr2.lbdie= cm_object_get_child_by_name(state->u.f0.reg.cr2, "LBDIE"); +state->u.f0.fld.cr2.lbcl= cm_object_get_child_by_name(state->u.f0.reg.cr2, "LBCL"); +state->u.f0.fld.cr2.cpha= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CPHA"); +state->u.f0.fld.cr2.cpol= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CPOL"); +state->u.f0.fld.cr2.clken= cm_object_get_child_by_name(state->u.f0.reg.cr2, "CLKEN"); +state->u.f0.fld.cr2.stop= cm_object_get_child_by_name(state->u.f0.reg.cr2, "STOP"); +state->u.f0.fld.cr2.linen= cm_object_get_child_by_name(state->u.f0.reg.cr2, "LINEN"); +state->u.f0.fld.cr2.swap= cm_object_get_child_by_name(state->u.f0.reg.cr2, "SWAP"); +state->u.f0.fld.cr2.rxinv= cm_object_get_child_by_name(state->u.f0.reg.cr2, "RXINV"); +state->u.f0.fld.cr2.txinv= cm_object_get_child_by_name(state->u.f0.reg.cr2, "TXINV"); +state->u.f0.fld.cr2.datainv= cm_object_get_child_by_name(state->u.f0.reg.cr2, "DATAINV"); +state->u.f0.fld.cr2.msbfirst= cm_object_get_child_by_name(state->u.f0.reg.cr2, "MSBFIRST"); +state->u.f0.fld.cr2.abren= cm_object_get_child_by_name(state->u.f0.reg.cr2, "ABREN"); +state->u.f0.fld.cr2.abrmod= cm_object_get_child_by_name(state->u.f0.reg.cr2, "ABRMOD"); +state->u.f0.fld.cr2.rtoen= cm_object_get_child_by_name(state->u.f0.reg.cr2, "RTOEN"); +state->u.f0.fld.cr2.add0= cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADD0"); +state->u.f0.fld.cr2.add4= cm_object_get_child_by_name(state->u.f0.reg.cr2, "ADD4"); +// CR3bitfields. +state->u.f0.fld.cr3.eie= cm_object_get_child_by_name(state->u.f0.reg.cr3, "EIE"); +state->u.f0.fld.cr3.iren= cm_object_get_child_by_name(state->u.f0.reg.cr3, "IREN"); +state->u.f0.fld.cr3.irlp= cm_object_get_child_by_name(state->u.f0.reg.cr3, "IRLP"); +state->u.f0.fld.cr3.hdsel= cm_object_get_child_by_name(state->u.f0.reg.cr3, "HDSEL"); +state->u.f0.fld.cr3.nack= cm_object_get_child_by_name(state->u.f0.reg.cr3, "NACK"); +state->u.f0.fld.cr3.scen= cm_object_get_child_by_name(state->u.f0.reg.cr3, "SCEN"); +state->u.f0.fld.cr3.dmar= cm_object_get_child_by_name(state->u.f0.reg.cr3, "DMAR"); +state->u.f0.fld.cr3.dmat= cm_object_get_child_by_name(state->u.f0.reg.cr3, "DMAT"); +state->u.f0.fld.cr3.rtse= cm_object_get_child_by_name(state->u.f0.reg.cr3, "RTSE"); +state->u.f0.fld.cr3.ctse= cm_object_get_child_by_name(state->u.f0.reg.cr3, "CTSE"); +state->u.f0.fld.cr3.ctsie= cm_object_get_child_by_name(state->u.f0.reg.cr3, "CTSIE"); +state->u.f0.fld.cr3.onebit= cm_object_get_child_by_name(state->u.f0.reg.cr3, "ONEBIT"); +state->u.f0.fld.cr3.ovrdis= cm_object_get_child_by_name(state->u.f0.reg.cr3, "OVRDIS"); +state->u.f0.fld.cr3.ddre= cm_object_get_child_by_name(state->u.f0.reg.cr3, "DDRE"); +state->u.f0.fld.cr3.dem= cm_object_get_child_by_name(state->u.f0.reg.cr3, "DEM"); +state->u.f0.fld.cr3.dep= cm_object_get_child_by_name(state->u.f0.reg.cr3, "DEP"); +state->u.f0.fld.cr3.scarcnt= cm_object_get_child_by_name(state->u.f0.reg.cr3, "SCARCNT"); +state->u.f0.fld.cr3.wus= cm_object_get_child_by_name(state->u.f0.reg.cr3, "WUS"); +state->u.f0.fld.cr3.wufie= cm_object_get_child_by_name(state->u.f0.reg.cr3, "WUFIE"); +// BRRbitfields. +state->u.f0.fld.brr.div_fraction= cm_object_get_child_by_name(state->u.f0.reg.brr, "DIV_Fraction"); +state->u.f0.fld.brr.div_mantissa= cm_object_get_child_by_name(state->u.f0.reg.brr, "DIV_Mantissa"); +// GTPRbitfields. +state->u.f0.fld.gtpr.psc= cm_object_get_child_by_name(state->u.f0.reg.gtpr, "PSC"); +state->u.f0.fld.gtpr.gt= cm_object_get_child_by_name(state->u.f0.reg.gtpr, "GT"); +// RTORbitfields. +state->u.f0.fld.rtor.rto= cm_object_get_child_by_name(state->u.f0.reg.rtor, "RTO"); +state->u.f0.fld.rtor.blen= cm_object_get_child_by_name(state->u.f0.reg.rtor, "BLEN"); +// RQRbitfields. +state->u.f0.fld.rqr.abrrq= cm_object_get_child_by_name(state->u.f0.reg.rqr, "ABRRQ"); +state->u.f0.fld.rqr.sbkrq= cm_object_get_child_by_name(state->u.f0.reg.rqr, "SBKRQ"); +state->u.f0.fld.rqr.mmrq= cm_object_get_child_by_name(state->u.f0.reg.rqr, "MMRQ"); +state->u.f0.fld.rqr.rxfrq= cm_object_get_child_by_name(state->u.f0.reg.rqr, "RXFRQ"); +state->u.f0.fld.rqr.txfrq= cm_object_get_child_by_name(state->u.f0.reg.rqr, "TXFRQ"); +// ISRbitfields. +state->u.f0.fld.isr.pe= cm_object_get_child_by_name(state->u.f0.reg.isr, "PE"); +state->u.f0.fld.isr.fe= cm_object_get_child_by_name(state->u.f0.reg.isr, "FE"); +state->u.f0.fld.isr.nf= cm_object_get_child_by_name(state->u.f0.reg.isr, "NF"); +state->u.f0.fld.isr.ore= cm_object_get_child_by_name(state->u.f0.reg.isr, "ORE"); +state->u.f0.fld.isr.idle= cm_object_get_child_by_name(state->u.f0.reg.isr, "IDLE"); +state->u.f0.fld.isr.rxne= cm_object_get_child_by_name(state->u.f0.reg.isr, "RXNE"); +state->u.f0.fld.isr.tc= cm_object_get_child_by_name(state->u.f0.reg.isr, "TC"); +state->u.f0.fld.isr.txe= cm_object_get_child_by_name(state->u.f0.reg.isr, "TXE"); +state->u.f0.fld.isr.lbdf= cm_object_get_child_by_name(state->u.f0.reg.isr, "LBDF"); +state->u.f0.fld.isr.ctsif= cm_object_get_child_by_name(state->u.f0.reg.isr, "CTSIF"); +state->u.f0.fld.isr.cts= cm_object_get_child_by_name(state->u.f0.reg.isr, "CTS"); +state->u.f0.fld.isr.rtof= cm_object_get_child_by_name(state->u.f0.reg.isr, "RTOF"); +state->u.f0.fld.isr.eobf= cm_object_get_child_by_name(state->u.f0.reg.isr, "EOBF"); +state->u.f0.fld.isr.abre= cm_object_get_child_by_name(state->u.f0.reg.isr, "ABRE"); +state->u.f0.fld.isr.abrf= cm_object_get_child_by_name(state->u.f0.reg.isr, "ABRF"); +state->u.f0.fld.isr.busy= cm_object_get_child_by_name(state->u.f0.reg.isr, "BUSY"); +state->u.f0.fld.isr.cmf= cm_object_get_child_by_name(state->u.f0.reg.isr, "CMF"); +state->u.f0.fld.isr.sbkf= cm_object_get_child_by_name(state->u.f0.reg.isr, "SBKF"); +state->u.f0.fld.isr.rwu= cm_object_get_child_by_name(state->u.f0.reg.isr, "RWU"); +state->u.f0.fld.isr.wuf= cm_object_get_child_by_name(state->u.f0.reg.isr, "WUF"); +state->u.f0.fld.isr.teack= cm_object_get_child_by_name(state->u.f0.reg.isr, "TEACK"); +state->u.f0.fld.isr.reack= cm_object_get_child_by_name(state->u.f0.reg.isr, "REACK"); +// ICRbitfields. +state->u.f0.fld.icr.pecf= cm_object_get_child_by_name(state->u.f0.reg.icr, "PECF"); +state->u.f0.fld.icr.fecf= cm_object_get_child_by_name(state->u.f0.reg.icr, "FECF"); +state->u.f0.fld.icr.ncf= cm_object_get_child_by_name(state->u.f0.reg.icr, "NCF"); +state->u.f0.fld.icr.orecf= cm_object_get_child_by_name(state->u.f0.reg.icr, "ORECF"); +state->u.f0.fld.icr.idlecf= cm_object_get_child_by_name(state->u.f0.reg.icr, "IDLECF"); +state->u.f0.fld.icr.tccf= cm_object_get_child_by_name(state->u.f0.reg.icr, "TCCF"); +state->u.f0.fld.icr.lbdcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "LBDCF"); +state->u.f0.fld.icr.ctscf= cm_object_get_child_by_name(state->u.f0.reg.icr, "CTSCF"); +state->u.f0.fld.icr.rtocf= cm_object_get_child_by_name(state->u.f0.reg.icr, "RTOCF"); +state->u.f0.fld.icr.eobcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "EOBCF"); +state->u.f0.fld.icr.cmcf= cm_object_get_child_by_name(state->u.f0.reg.icr, "CMCF"); +state->u.f0.fld.icr.wucf= cm_object_get_child_by_name(state->u.f0.reg.icr, "WUCF"); +// RDRbitfields. +state->u.f0.fld.rdr.rdr= cm_object_get_child_by_name(state->u.f0.reg.rdr, "RDR"); +// TDRbitfields. +state->u.f0.fld.tdr.tdr= cm_object_get_child_by_name(state->u.f0.reg.tdr, "TDR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usart_is_enabled(Object *obj) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USARTState *state = STM32_USART_STATE(obj); + + // Capabilities are not yet available. + +cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_USART_UNDEFINED; +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USARTState *state = STM32_USART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_usart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_usart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_usart_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USART%dEN", + 1 + state->port_index - STM32_PORT_USART1); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USART); +} + +static void stm32_usart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usart_reset_callback; + dc->realize = stm32_usart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usart_is_enabled; +} + +static const TypeInfo stm32_usart_type_info = { + .name = TYPE_STM32_USART, + .parent = TYPE_STM32_USART_PARENT, + .instance_init = stm32_usart_instance_init_callback, + .instance_size = sizeof(STM32USARTState), + .class_init = stm32_usart_class_init_callback, + .class_size = sizeof(STM32USARTClass) }; + +static void stm32_usart_register_types(void) +{ + type_register_static(&stm32_usart_type_info); +} + +type_init(stm32_usart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/usart1.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/usart1.h new file mode 100644 index 0000000000..541f081dd0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/usart1.h @@ -0,0 +1,154 @@ +/* + * STM32- USART(Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USART_H_ +#define STM32_USART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USARTDEVICE_PATH_STM32"USART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. +STM32_PORT_USART1, +STM32_PORT_USART2, +STM32_PORT_USART3, +STM32_PORT_USART4, +STM32_PORT_USART_UNDEFINED = 0xFF, +} stm32_usart_index_t; +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USARTTYPE_STM32_PREFIX "usart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USARTParentClass; +typedef PeripheralState STM32USARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USARTClass, (obj), TYPE_STM32_USART) +#define STM32_USART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USARTClass, (klass), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentClass parent_class; + // public: + + // None, so far. +} STM32USARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USART_STATE(obj) \ + OBJECT_CHECK(STM32USARTState, (obj), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +// Remove it if there is only one port + stm32_usart_index_t port_index; +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0USART(Universal synchronous asynchronous receiver transmitter) registers. + struct { +Object *cr1; // 0x0(Control register 1) +Object *cr2; // 0x4(Control register 2) +Object *cr3; // 0x8(Control register 3) +Object *brr; // 0xC(Baud rate register) +Object *gtpr; // 0x10(Guard time and prescaler register) +Object *rtor; // 0x14(Receiver timeout register) +Object *rqr; // 0x18(Request register) +Object *isr; // 0x1C(Interrupt & status register) +Object *icr; // 0x20(Interrupt flag clear register) +Object *rdr; // 0x24(Receive data register) +Object *tdr; // 0x28(Transmit data register) +} reg; + + struct { +// CR1(Control register 1) bitfields. + struct { +Object *ue; // [0:0] USART enableObject *uesm; // [1:1] USART enable in Stop modeObject *re; // [2:2] Receiver enableObject *te; // [3:3] Transmitter enableObject *idleie; // [4:4] IDLE interrupt enableObject *rxneie; // [5:5] RXNE interrupt enableObject *tcie; // [6:6] Transmission complete interrupt enableObject *txeie; // [7:7] Interrupt enableObject *peie; // [8:8] PE interrupt enableObject *ps; // [9:9] Parity selectionObject *pce; // [10:10] Parity control enableObject *wake; // [11:11] Receiver wakeup methodObject *m; // [12:12] Word lengthObject *mme; // [13:13] Mute mode enableObject *cmie; // [14:14] Character match interrupt enableObject *over8; // [15:15] Oversampling modeObject *dedt; // [16:20] Driver Enable deassertion timeObject *deat; // [21:25] Driver Enable assertion timeObject *rtoie; // [26:26] Receiver timeout interrupt enableObject *eobie; // [27:27] End of Block interrupt enableObject *m1; // [28:28] Word length} cr1; +// CR2(Control register 2) bitfields. + struct { +Object *addm7; // [4:4] 7-bit Address Detection/4-bit Address DetectionObject *lbdl; // [5:5] LIN break detection lengthObject *lbdie; // [6:6] LIN break detection interrupt enableObject *lbcl; // [8:8] Last bit clock pulseObject *cpha; // [9:9] Clock phaseObject *cpol; // [10:10] Clock polarityObject *clken; // [11:11] Clock enableObject *stop; // [12:13] STOP bitsObject *linen; // [14:14] LIN mode enableObject *swap; // [15:15] Swap TX/RX pinsObject *rxinv; // [16:16] RX pin active level inversionObject *txinv; // [17:17] TX pin active level inversionObject *datainv; // [18:18] Binary data inversionObject *msbfirst; // [19:19] Most significant bit firstObject *abren; // [20:20] Auto baud rate enableObject *abrmod; // [21:22] Auto baud rate modeObject *rtoen; // [23:23] Receiver timeout enableObject *add0; // [24:27] Address of the USART nodeObject *add4; // [28:31] Address of the USART node} cr2; +// CR3(Control register 3) bitfields. + struct { +Object *eie; // [0:0] Error interrupt enableObject *iren; // [1:1] IrDA mode enableObject *irlp; // [2:2] IrDA low-powerObject *hdsel; // [3:3] Half-duplex selectionObject *nack; // [4:4] Smartcard NACK enableObject *scen; // [5:5] Smartcard mode enableObject *dmar; // [6:6] DMA enable receiverObject *dmat; // [7:7] DMA enable transmitterObject *rtse; // [8:8] RTS enableObject *ctse; // [9:9] CTS enableObject *ctsie; // [10:10] CTS interrupt enableObject *onebit; // [11:11] One sample bit method enableObject *ovrdis; // [12:12] Overrun DisableObject *ddre; // [13:13] DMA Disable on Reception ErrorObject *dem; // [14:14] Driver enable modeObject *dep; // [15:15] Driver enable polarity selectionObject *scarcnt; // [17:19] Smartcard auto-retry countObject *wus; // [20:21] Wakeup from Stop mode interrupt flag selectionObject *wufie; // [22:22] Wakeup from Stop mode interrupt enable} cr3; +// BRR(Baud rate register) bitfields. + struct { +Object *div_fraction; // [0:3] Fraction of USARTDIVObject *div_mantissa; // [4:15] Mantissa of USARTDIV} brr; +// GTPR(Guard time and prescaler register) bitfields. + struct { +Object *psc; // [0:7] Prescaler valueObject *gt; // [8:15] Guard time value} gtpr; +// RTOR(Receiver timeout register) bitfields. + struct { +Object *rto; // [0:23] Receiver timeout valueObject *blen; // [24:31] Block Length} rtor; +// RQR(Request register) bitfields. + struct { +Object *abrrq; // [0:0] Auto baud rate requestObject *sbkrq; // [1:1] Send break requestObject *mmrq; // [2:2] Mute mode requestObject *rxfrq; // [3:3] Receive data flush requestObject *txfrq; // [4:4] Transmit data flush request} rqr; +// ISR(Interrupt & status register) bitfields. + struct { +Object *pe; // [0:0] Parity errorObject *fe; // [1:1] Framing errorObject *nf; // [2:2] Noise detected flagObject *ore; // [3:3] Overrun errorObject *idle; // [4:4] Idle line detectedObject *rxne; // [5:5] Read data register not emptyObject *tc; // [6:6] Transmission completeObject *txe; // [7:7] Transmit data register emptyObject *lbdf; // [8:8] LIN break detection flagObject *ctsif; // [9:9] CTS interrupt flagObject *cts; // [10:10] CTS flagObject *rtof; // [11:11] Receiver timeoutObject *eobf; // [12:12] End of block flagObject *abre; // [14:14] Auto baud rate errorObject *abrf; // [15:15] Auto baud rate flagObject *busy; // [16:16] Busy flagObject *cmf; // [17:17] Character match flagObject *sbkf; // [18:18] Send break flagObject *rwu; // [19:19] Receiver wakeup from Mute modeObject *wuf; // [20:20] Wakeup from Stop mode flagObject *teack; // [21:21] Transmit enable acknowledge flagObject *reack; // [22:22] Receive enable acknowledge flag} isr; +// ICR(Interrupt flag clear register) bitfields. + struct { +Object *pecf; // [0:0] Parity error clear flagObject *fecf; // [1:1] Framing error clear flagObject *ncf; // [2:2] Noise detected clear flagObject *orecf; // [3:3] Overrun error clear flagObject *idlecf; // [4:4] Idle line detected clear flagObject *tccf; // [6:6] Transmission complete clear flagObject *lbdcf; // [8:8] LIN break detection clear flagObject *ctscf; // [9:9] CTS clear flagObject *rtocf; // [11:11] Receiver timeout clear flagObject *eobcf; // [12:12] End of timeout clear flagObject *cmcf; // [17:17] Character match clear flagObject *wucf; // [20:20] Wakeup from Stop mode clear flag} icr; +// RDR(Receive data register) bitfields. + struct { +Object *rdr; // [0:8] Receive data value} rdr; +// TDR(Transmit data register) bitfields. + struct { +Object *tdr; // [0:8] Transmit data value} tdr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/usb.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/usb.c new file mode 100644 index 0000000000..23ff6b25e2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/usb.c @@ -0,0 +1,388 @@ +/* + * STM32- USB(Universal serial bus full-speed device interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_usb_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USBState *state = STM32_USB_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.ep0r= cm_object_get_child_by_name(obj, "EP0R"); +state->u.f0.reg.ep1r= cm_object_get_child_by_name(obj, "EP1R"); +state->u.f0.reg.ep2r= cm_object_get_child_by_name(obj, "EP2R"); +state->u.f0.reg.ep3r= cm_object_get_child_by_name(obj, "EP3R"); +state->u.f0.reg.ep4r= cm_object_get_child_by_name(obj, "EP4R"); +state->u.f0.reg.ep5r= cm_object_get_child_by_name(obj, "EP5R"); +state->u.f0.reg.ep6r= cm_object_get_child_by_name(obj, "EP6R"); +state->u.f0.reg.ep7r= cm_object_get_child_by_name(obj, "EP7R"); +state->u.f0.reg.cntr= cm_object_get_child_by_name(obj, "CNTR"); +state->u.f0.reg.istr= cm_object_get_child_by_name(obj, "ISTR"); +state->u.f0.reg.fnr= cm_object_get_child_by_name(obj, "FNR"); +state->u.f0.reg.daddr= cm_object_get_child_by_name(obj, "DADDR"); +state->u.f0.reg.btable= cm_object_get_child_by_name(obj, "BTABLE"); +state->u.f0.reg.lpmcsr= cm_object_get_child_by_name(obj, "LPMCSR"); +state->u.f0.reg.bcdr= cm_object_get_child_by_name(obj, "BCDR"); +// EP0Rbitfields. +state->u.f0.fld.ep0r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "EA"); +state->u.f0.fld.ep0r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "STAT_TX"); +state->u.f0.fld.ep0r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "DTOG_TX"); +state->u.f0.fld.ep0r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "CTR_TX"); +state->u.f0.fld.ep0r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "EP_KIND"); +state->u.f0.fld.ep0r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "EP_TYPE"); +state->u.f0.fld.ep0r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "SETUP"); +state->u.f0.fld.ep0r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "STAT_RX"); +state->u.f0.fld.ep0r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "DTOG_RX"); +state->u.f0.fld.ep0r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep0r, "CTR_RX"); +// EP1Rbitfields. +state->u.f0.fld.ep1r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "EA"); +state->u.f0.fld.ep1r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "STAT_TX"); +state->u.f0.fld.ep1r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "DTOG_TX"); +state->u.f0.fld.ep1r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "CTR_TX"); +state->u.f0.fld.ep1r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "EP_KIND"); +state->u.f0.fld.ep1r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "EP_TYPE"); +state->u.f0.fld.ep1r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "SETUP"); +state->u.f0.fld.ep1r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "STAT_RX"); +state->u.f0.fld.ep1r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "DTOG_RX"); +state->u.f0.fld.ep1r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep1r, "CTR_RX"); +// EP2Rbitfields. +state->u.f0.fld.ep2r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "EA"); +state->u.f0.fld.ep2r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "STAT_TX"); +state->u.f0.fld.ep2r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "DTOG_TX"); +state->u.f0.fld.ep2r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "CTR_TX"); +state->u.f0.fld.ep2r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "EP_KIND"); +state->u.f0.fld.ep2r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "EP_TYPE"); +state->u.f0.fld.ep2r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "SETUP"); +state->u.f0.fld.ep2r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "STAT_RX"); +state->u.f0.fld.ep2r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "DTOG_RX"); +state->u.f0.fld.ep2r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep2r, "CTR_RX"); +// EP3Rbitfields. +state->u.f0.fld.ep3r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "EA"); +state->u.f0.fld.ep3r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "STAT_TX"); +state->u.f0.fld.ep3r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "DTOG_TX"); +state->u.f0.fld.ep3r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "CTR_TX"); +state->u.f0.fld.ep3r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "EP_KIND"); +state->u.f0.fld.ep3r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "EP_TYPE"); +state->u.f0.fld.ep3r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "SETUP"); +state->u.f0.fld.ep3r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "STAT_RX"); +state->u.f0.fld.ep3r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "DTOG_RX"); +state->u.f0.fld.ep3r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep3r, "CTR_RX"); +// EP4Rbitfields. +state->u.f0.fld.ep4r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "EA"); +state->u.f0.fld.ep4r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "STAT_TX"); +state->u.f0.fld.ep4r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "DTOG_TX"); +state->u.f0.fld.ep4r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "CTR_TX"); +state->u.f0.fld.ep4r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "EP_KIND"); +state->u.f0.fld.ep4r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "EP_TYPE"); +state->u.f0.fld.ep4r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "SETUP"); +state->u.f0.fld.ep4r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "STAT_RX"); +state->u.f0.fld.ep4r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "DTOG_RX"); +state->u.f0.fld.ep4r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep4r, "CTR_RX"); +// EP5Rbitfields. +state->u.f0.fld.ep5r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "EA"); +state->u.f0.fld.ep5r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "STAT_TX"); +state->u.f0.fld.ep5r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "DTOG_TX"); +state->u.f0.fld.ep5r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "CTR_TX"); +state->u.f0.fld.ep5r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "EP_KIND"); +state->u.f0.fld.ep5r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "EP_TYPE"); +state->u.f0.fld.ep5r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "SETUP"); +state->u.f0.fld.ep5r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "STAT_RX"); +state->u.f0.fld.ep5r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "DTOG_RX"); +state->u.f0.fld.ep5r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep5r, "CTR_RX"); +// EP6Rbitfields. +state->u.f0.fld.ep6r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "EA"); +state->u.f0.fld.ep6r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "STAT_TX"); +state->u.f0.fld.ep6r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "DTOG_TX"); +state->u.f0.fld.ep6r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "CTR_TX"); +state->u.f0.fld.ep6r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "EP_KIND"); +state->u.f0.fld.ep6r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "EP_TYPE"); +state->u.f0.fld.ep6r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "SETUP"); +state->u.f0.fld.ep6r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "STAT_RX"); +state->u.f0.fld.ep6r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "DTOG_RX"); +state->u.f0.fld.ep6r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep6r, "CTR_RX"); +// EP7Rbitfields. +state->u.f0.fld.ep7r.ea= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "EA"); +state->u.f0.fld.ep7r.stat_tx= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "STAT_TX"); +state->u.f0.fld.ep7r.dtog_tx= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "DTOG_TX"); +state->u.f0.fld.ep7r.ctr_tx= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "CTR_TX"); +state->u.f0.fld.ep7r.ep_kind= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "EP_KIND"); +state->u.f0.fld.ep7r.ep_type= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "EP_TYPE"); +state->u.f0.fld.ep7r.setup= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "SETUP"); +state->u.f0.fld.ep7r.stat_rx= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "STAT_RX"); +state->u.f0.fld.ep7r.dtog_rx= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "DTOG_RX"); +state->u.f0.fld.ep7r.ctr_rx= cm_object_get_child_by_name(state->u.f0.reg.ep7r, "CTR_RX"); +// CNTRbitfields. +state->u.f0.fld.cntr.fres= cm_object_get_child_by_name(state->u.f0.reg.cntr, "FRES"); +state->u.f0.fld.cntr.pdwn= cm_object_get_child_by_name(state->u.f0.reg.cntr, "PDWN"); +state->u.f0.fld.cntr.lpmode= cm_object_get_child_by_name(state->u.f0.reg.cntr, "LPMODE"); +state->u.f0.fld.cntr.fsusp= cm_object_get_child_by_name(state->u.f0.reg.cntr, "FSUSP"); +state->u.f0.fld.cntr.resume= cm_object_get_child_by_name(state->u.f0.reg.cntr, "RESUME"); +state->u.f0.fld.cntr.l1resume= cm_object_get_child_by_name(state->u.f0.reg.cntr, "L1RESUME"); +state->u.f0.fld.cntr.l1reqm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "L1REQM"); +state->u.f0.fld.cntr.esofm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "ESOFM"); +state->u.f0.fld.cntr.sofm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "SOFM"); +state->u.f0.fld.cntr.resetm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "RESETM"); +state->u.f0.fld.cntr.suspm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "SUSPM"); +state->u.f0.fld.cntr.wkupm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "WKUPM"); +state->u.f0.fld.cntr.errm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "ERRM"); +state->u.f0.fld.cntr.pmaovrm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "PMAOVRM"); +state->u.f0.fld.cntr.ctrm= cm_object_get_child_by_name(state->u.f0.reg.cntr, "CTRM"); +// ISTRbitfields. +state->u.f0.fld.istr.ep_id= cm_object_get_child_by_name(state->u.f0.reg.istr, "EP_ID"); +state->u.f0.fld.istr.dir= cm_object_get_child_by_name(state->u.f0.reg.istr, "DIR"); +state->u.f0.fld.istr.l1req= cm_object_get_child_by_name(state->u.f0.reg.istr, "L1REQ"); +state->u.f0.fld.istr.esof= cm_object_get_child_by_name(state->u.f0.reg.istr, "ESOF"); +state->u.f0.fld.istr.sof= cm_object_get_child_by_name(state->u.f0.reg.istr, "SOF"); +state->u.f0.fld.istr.reset= cm_object_get_child_by_name(state->u.f0.reg.istr, "RESET"); +state->u.f0.fld.istr.susp= cm_object_get_child_by_name(state->u.f0.reg.istr, "SUSP"); +state->u.f0.fld.istr.wkup= cm_object_get_child_by_name(state->u.f0.reg.istr, "WKUP"); +state->u.f0.fld.istr.err= cm_object_get_child_by_name(state->u.f0.reg.istr, "ERR"); +state->u.f0.fld.istr.pmaovr= cm_object_get_child_by_name(state->u.f0.reg.istr, "PMAOVR"); +state->u.f0.fld.istr.ctr= cm_object_get_child_by_name(state->u.f0.reg.istr, "CTR"); +// FNRbitfields. +state->u.f0.fld.fnr.fn= cm_object_get_child_by_name(state->u.f0.reg.fnr, "FN"); +state->u.f0.fld.fnr.lsof= cm_object_get_child_by_name(state->u.f0.reg.fnr, "LSOF"); +state->u.f0.fld.fnr.lck= cm_object_get_child_by_name(state->u.f0.reg.fnr, "LCK"); +state->u.f0.fld.fnr.rxdm= cm_object_get_child_by_name(state->u.f0.reg.fnr, "RXDM"); +state->u.f0.fld.fnr.rxdp= cm_object_get_child_by_name(state->u.f0.reg.fnr, "RXDP"); +// DADDRbitfields. +state->u.f0.fld.daddr.add= cm_object_get_child_by_name(state->u.f0.reg.daddr, "ADD"); +state->u.f0.fld.daddr.ef= cm_object_get_child_by_name(state->u.f0.reg.daddr, "EF"); +// BTABLEbitfields. +state->u.f0.fld.btable.btable= cm_object_get_child_by_name(state->u.f0.reg.btable, "BTABLE"); +// LPMCSRbitfields. +state->u.f0.fld.lpmcsr.lpmen= cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "LPMEN"); +state->u.f0.fld.lpmcsr.lpmack= cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "LPMACK"); +state->u.f0.fld.lpmcsr.remwake= cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "REMWAKE"); +state->u.f0.fld.lpmcsr.besl= cm_object_get_child_by_name(state->u.f0.reg.lpmcsr, "BESL"); +// BCDRbitfields. +state->u.f0.fld.bcdr.bcden= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "BCDEN"); +state->u.f0.fld.bcdr.dcden= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "DCDEN"); +state->u.f0.fld.bcdr.pden= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "PDEN"); +state->u.f0.fld.bcdr.sden= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "SDEN"); +state->u.f0.fld.bcdr.dcdet= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "DCDET"); +state->u.f0.fld.bcdr.pdet= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "PDET"); +state->u.f0.fld.bcdr.sdet= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "SDET"); +state->u.f0.fld.bcdr.ps2det= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "PS2DET"); +state->u.f0.fld.bcdr.dppu= cm_object_get_child_by_name(state->u.f0.reg.bcdr, "DPPU"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usb_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usb_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usb_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usb_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usb_is_enabled(Object *obj) +{ + STM32USBState *state = STM32_USB_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usb_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USBState *state = STM32_USB_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usb_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USB)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USBState *state = STM32_USB_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USB"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_usb_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usb_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_usb_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_usb_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_usb_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USBEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usb_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USB); +} + +static void stm32_usb_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usb_reset_callback; + dc->realize = stm32_usb_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usb_is_enabled; +} + +static const TypeInfo stm32_usb_type_info = { + .name = TYPE_STM32_USB, + .parent = TYPE_STM32_USB_PARENT, + .instance_init = stm32_usb_instance_init_callback, + .instance_size = sizeof(STM32USBState), + .class_init = stm32_usb_class_init_callback, + .class_size = sizeof(STM32USBClass) }; + +static void stm32_usb_register_types(void) +{ + type_register_static(&stm32_usb_type_info); +} + +type_init(stm32_usb_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/usb.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/usb.h new file mode 100644 index 0000000000..1ebaf93b11 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/usb.h @@ -0,0 +1,157 @@ +/* + * STM32- USB(Universal serial bus full-speed device interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USB_H_ +#define STM32_USB_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USBDEVICE_PATH_STM32"USB" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USBTYPE_STM32_PREFIX "usb" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USB_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USBParentClass; +typedef PeripheralState STM32USBParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USB_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USBClass, (obj), TYPE_STM32_USB) +#define STM32_USB_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USBClass, (klass), TYPE_STM32_USB) + +typedef struct { + // private: + STM32USBParentClass parent_class; + // public: + + // None, so far. +} STM32USBClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USB_STATE(obj) \ + OBJECT_CHECK(STM32USBState, (obj), TYPE_STM32_USB) + +typedef struct { + // private: + STM32USBParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0USB(Universal serial bus full-speed device interface) registers. + struct { +Object *ep0r; // 0x0(Endpoint 0 register) +Object *ep1r; // 0x4(Endpoint 1 register) +Object *ep2r; // 0x8(Endpoint 2 register) +Object *ep3r; // 0xC(Endpoint 3 register) +Object *ep4r; // 0x10(Endpoint 4 register) +Object *ep5r; // 0x14(Endpoint 5 register) +Object *ep6r; // 0x18(Endpoint 6 register) +Object *ep7r; // 0x1C(Endpoint 7 register) +Object *cntr; // 0x40(Control register) +Object *istr; // 0x44(Interrupt status register) +Object *fnr; // 0x48(Frame number register) +Object *daddr; // 0x4C(Device address) +Object *btable; // 0x50(Buffer table address) +Object *lpmcsr; // 0x54(LPM control and status register) +Object *bcdr; // 0x58(Battery charging detector) +} reg; + + struct { +// EP0R(Endpoint 0 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep0r; +// EP1R(Endpoint 1 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep1r; +// EP2R(Endpoint 2 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep2r; +// EP3R(Endpoint 3 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep3r; +// EP4R(Endpoint 4 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep4r; +// EP5R(Endpoint 5 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep5r; +// EP6R(Endpoint 6 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep6r; +// EP7R(Endpoint 7 register) bitfields. + struct { +Object *ea; // [0:3] Endpoint addressObject *stat_tx; // [4:5] Status bits, for transmission transfersObject *dtog_tx; // [6:6] Data Toggle, for transmission transfersObject *ctr_tx; // [7:7] Correct Transfer for transmissionObject *ep_kind; // [8:8] Endpoint kindObject *ep_type; // [9:10] Endpoint typeObject *setup; // [11:11] Setup transaction completedObject *stat_rx; // [12:13] Status bits, for reception transfersObject *dtog_rx; // [14:14] Data Toggle, for reception transfersObject *ctr_rx; // [15:15] Correct transfer for reception} ep7r; +// CNTR(Control register) bitfields. + struct { +Object *fres; // [0:0] Force USB ResetObject *pdwn; // [1:1] Power downObject *lpmode; // [2:2] Low-power modeObject *fsusp; // [3:3] Force suspendObject *resume; // [4:4] Resume requestObject *l1resume; // [5:5] LPM L1 Resume requestObject *l1reqm; // [7:7] LPM L1 state request interrupt maskObject *esofm; // [8:8] Expected start of frame interrupt maskObject *sofm; // [9:9] Start of frame interrupt maskObject *resetm; // [10:10] USB reset interrupt maskObject *suspm; // [11:11] Suspend mode interrupt maskObject *wkupm; // [12:12] Wakeup interrupt maskObject *errm; // [13:13] Error interrupt maskObject *pmaovrm; // [14:14] Packet memory area over / underrun interrupt maskObject *ctrm; // [15:15] Correct transfer interrupt mask} cntr; +// ISTR(Interrupt status register) bitfields. + struct { +Object *ep_id; // [0:3] Endpoint IdentifierObject *dir; // [4:4] Direction of transactionObject *l1req; // [7:7] LPM L1 state requestObject *esof; // [8:8] Expected start frameObject *sof; // [9:9] Start of frameObject *reset; // [10:10] Reset requestObject *susp; // [11:11] Suspend mode requestObject *wkup; // [12:12] WakeupObject *err; // [13:13] ErrorObject *pmaovr; // [14:14] Packet memory area over / underrunObject *ctr; // [15:15] Correct transfer} istr; +// FNR(Frame number register) bitfields. + struct { +Object *fn; // [0:10] Frame numberObject *lsof; // [11:12] Lost SOFObject *lck; // [13:13] LockedObject *rxdm; // [14:14] Receive data - line statusObject *rxdp; // [15:15] Receive data + line status} fnr; +// DADDR(Device address) bitfields. + struct { +Object *add; // [0:6] Device addressObject *ef; // [7:7] Enable function} daddr; +// BTABLE(Buffer table address) bitfields. + struct { +Object *btable; // [3:15] Buffer table} btable; +// LPMCSR(LPM control and status register) bitfields. + struct { +Object *lpmen; // [0:0] LPM support enableObject *lpmack; // [1:1] LPM Token acknowledge enableObject *remwake; // [3:3] BRemoteWake valueObject *besl; // [4:7] BESL value} lpmcsr; +// BCDR(Battery charging detector) bitfields. + struct { +Object *bcden; // [0:0] Battery charging detector (BCD) enableObject *dcden; // [1:1] Data contact detection (DCD) mode enableObject *pden; // [2:2] Primary detection (PD) mode enableObject *sden; // [3:3] Secondary detection (SD) mode enableObject *dcdet; // [4:4] Data contact detection (DCD) statusObject *pdet; // [5:5] Primary detection (PD) statusObject *sdet; // [6:6] Secondary detection (SD) statusObject *ps2det; // [7:7] DM pull-up detection statusObject *dppu; // [15:15] DP pull-up control} bcdr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USBState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USB_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/wwdg.c b/gnu-mcu-eclipse/devices/support/STM32F0x2/wwdg.c new file mode 100644 index 0000000000..2b5e72c7d0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/wwdg.c @@ -0,0 +1,243 @@ +/* + * STM32- WWDG(Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f0x2_wwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. +state->u.f0.reg.cr= cm_object_get_child_by_name(obj, "CR"); +state->u.f0.reg.cfr= cm_object_get_child_by_name(obj, "CFR"); +state->u.f0.reg.sr= cm_object_get_child_by_name(obj, "SR"); +// CRbitfields. +state->u.f0.fld.cr.t= cm_object_get_child_by_name(state->u.f0.reg.cr, "T"); +state->u.f0.fld.cr.wdga= cm_object_get_child_by_name(state->u.f0.reg.cr, "WDGA"); +// CFRbitfields. +state->u.f0.fld.cfr.w= cm_object_get_child_by_name(state->u.f0.reg.cfr, "W"); +state->u.f0.fld.cfr.wdgtb= cm_object_get_child_by_name(state->u.f0.reg.cfr, "WDGTB"); +state->u.f0.fld.cfr.ewi= cm_object_get_child_by_name(state->u.f0.reg.cfr, "EWI"); +// SRbitfields. +state->u.f0.fld.sr.ewif= cm_object_get_child_by_name(state->u.f0.reg.sr, "EWIF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_wwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_wwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_wwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_wwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_wwdg_is_enabled(Object *obj) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_wwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + // Capabilities are not yet available. + +// TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_wwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_WWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32WWDGState *state = STM32_WWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "WWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F0: + + if (capabilities->f0.is_0x2) { + + stm32f0x2_wwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f0.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_wwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f0.reg.xxx, &stm32_wwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f0.reg.xxx, &stm32_wwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f0.reg.xxx, &stm32_wwdg_xxx_post_write_callback); + + // TODO: add interrupts. + +// TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/WWDGEN"); +} else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_wwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_WWDG); +} + +static void stm32_wwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_wwdg_reset_callback; + dc->realize = stm32_wwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_wwdg_is_enabled; +} + +static const TypeInfo stm32_wwdg_type_info = { + .name = TYPE_STM32_WWDG, + .parent = TYPE_STM32_WWDG_PARENT, + .instance_init = stm32_wwdg_instance_init_callback, + .instance_size = sizeof(STM32WWDGState), + .class_init = stm32_wwdg_class_init_callback, + .class_size = sizeof(STM32WWDGClass) }; + +static void stm32_wwdg_register_types(void) +{ + type_register_static(&stm32_wwdg_type_info); +} + +type_init(stm32_wwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F0x2/wwdg.h b/gnu-mcu-eclipse/devices/support/STM32F0x2/wwdg.h new file mode 100644 index 0000000000..464732e81e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F0x2/wwdg.h @@ -0,0 +1,109 @@ +/* + * STM32- WWDG(Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_WWDG_H_ +#define STM32_WWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_WWDGDEVICE_PATH_STM32"WWDG" + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_WWDGTYPE_STM32_PREFIX "wwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_WWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32WWDGParentClass; +typedef PeripheralState STM32WWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_WWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32WWDGClass, (obj), TYPE_STM32_WWDG) +#define STM32_WWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32WWDGClass, (klass), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentClass parent_class; + // public: + + // None, so far. +} STM32WWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_WWDG_STATE(obj) \ + OBJECT_CHECK(STM32WWDGState, (obj), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + +union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F0WWDG(Window watchdog) registers. + struct { +Object *cr; // 0x0(Control register) +Object *cfr; // 0x4(Configuration register) +Object *sr; // 0x8(Status register) +} reg; + + struct { +// CR(Control register) bitfields. + struct { +Object *t; // [0:6] 7-bit counterObject *wdga; // [7:7] Activation bit} cr; +// CFR(Configuration register) bitfields. + struct { +Object *w; // [0:6] 7-bit window valueObject *wdgtb; // [7:8] Timer baseObject *ewi; // [9:9] Early wakeup interrupt} cfr; +// SR(Status register) bitfields. + struct { +Object *ewif; // [0:0] Early wakeup interrupt flag} sr; +} fld; + } f0; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32WWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_WWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx-patch.json b/gnu-mcu-eclipse/devices/support/STM32F103xx-patch.json new file mode 100644 index 0000000000..24ee2d5a5b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx-patch.json @@ -0,0 +1,151 @@ +{ + "comment": "Patch for QEMU use.", + "device": { + "name": "STM32F103xx", + "cpu": { + "name": "CM3", + "revision": "r1p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "false", + "nvicPrioBits": "4", + "deviceNumInterrupts": "43", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "access": "read-write", + "qemuAlignment": "any", + "peripherals": [ + { + "name": "EXTI", + "qemuAlignment": "word" + }, + { + "name": "FLASH", + "qemuAlignment": "any" + }, + { + "name": "PWR", + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "qemuAlignment": "any" + }, + { + "name": "SYSCFG", + "qemuAlignment": "any" + }, + { + "name": "GPIOA", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "USART1", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART2", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART3", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART4", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART5", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART6", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART7", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART8", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "DMA1", + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "qemuGroupName": "DMA" + }, + { + "name": "I2C1", + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "qemuGroupName": "I2C" + }, + { + "name": "SPI1", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "qemuGroupName": "SPI" + }, + { + "name": "ADC1", + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "qemuGroupName": "ADC" + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx-xsvd.json b/gnu-mcu-eclipse/devices/support/STM32F103xx-xsvd.json new file mode 100644 index 0000000000..5fc23fc218 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx-xsvd.json @@ -0,0 +1,24302 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F103xx.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.2", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F103xx.svd", + "--output", + "STM32F103xx-xsvd.json" + ], + "date": "2016-12-14T22:50:50.255Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F103xx", + "version": "1.3", + "description": "STM32F103xx", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "FSMC", + "description": "Flexible static memory controller", + "groupName": "FSMC", + "baseAddress": "0xA0000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1000", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FSMC", + "description": "FSMC global interrupt", + "value": "48" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "SRAM/NOR-Flash chip-select control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR1", + "displayName": "BTR1", + "description": "SRAM/NOR-Flash chip-select timing register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "SRAM/NOR-Flash chip-select control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR2", + "displayName": "BTR2", + "description": "SRAM/NOR-Flash chip-select timing register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR3", + "displayName": "BCR3", + "description": "SRAM/NOR-Flash chip-select control register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR3", + "displayName": "BTR3", + "description": "SRAM/NOR-Flash chip-select timing register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR4", + "displayName": "BCR4", + "description": "SRAM/NOR-Flash chip-select control register 4", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR4", + "displayName": "BTR4", + "description": "SRAM/NOR-Flash chip-select timing register 4", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "PCR2", + "displayName": "PCR2", + "description": "PC Card/NAND Flash control register 2", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "FIFO status and interrupt register 2", + "addressOffset": "0x64", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM2", + "displayName": "PMEM2", + "description": "Common memory space timing register 2", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT2", + "displayName": "PATT2", + "description": "Attribute memory space timing register 2", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "Attribute memory x databus HiZ time", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "Attribute memory x hold time", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "Attribute memory x wait time", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "Attribute memory x setup time", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR2", + "displayName": "ECCR2", + "description": "ECC result register 2", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECC result", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR3", + "displayName": "PCR3", + "description": "PC Card/NAND Flash control register 3", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR3", + "displayName": "SR3", + "description": "FIFO status and interrupt register 3", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM3", + "displayName": "PMEM3", + "description": "Common memory space timing register 3", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT3", + "displayName": "PATT3", + "description": "Attribute memory space timing register 3", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR3", + "displayName": "ECCR3", + "description": "ECC result register 3", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR4", + "displayName": "PCR4", + "description": "PC Card/NAND Flash control register 4", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR4", + "displayName": "SR4", + "description": "FIFO status and interrupt register 4", + "addressOffset": "0xA4", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM4", + "displayName": "PMEM4", + "description": "Common memory space timing register 4", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT4", + "displayName": "PATT4", + "description": "Attribute memory space timing register 4", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PIO4", + "displayName": "PIO4", + "description": "I/O space timing register 4", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "IOHIZx", + "description": "IOHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "IOHOLDx", + "description": "IOHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IOWAITx", + "description": "IOWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IOSETx", + "description": "IOSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BWTR1", + "displayName": "BWTR1", + "description": "SRAM/NOR-Flash write timing registers 1", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR2", + "displayName": "BWTR2", + "description": "SRAM/NOR-Flash write timing registers 2", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR3", + "displayName": "BWTR3", + "description": "SRAM/NOR-Flash write timing registers 3", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR4", + "displayName": "BWTR4", + "description": "SRAM/NOR-Flash write timing registers 4", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low Power Deep Sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power Down Deep Sleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear Wake-up Flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear STANDBY Flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power Voltage Detector Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD Level Selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable Backup Domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wake-Up Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "STANDBY Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD Output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB High speed prescaler (APB2)", + "bitOffset": "11", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL entry clock source", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "OTGFSPRE", + "description": "USB OTG FS prescaler", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000000", + "fields": [ + { + "name": "AFIORST", + "description": "Alternate function I/O reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPARST", + "description": "IO port A reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "IO port B reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "IO port C reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "IO port D reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPERST", + "description": "IO port E reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPFRST", + "description": "IO port F reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IOPGRST", + "description": "IO port G reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC1RST", + "description": "ADC 1 interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2RST", + "description": "ADC 2 interface reset", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIM8RST", + "description": "TIM8 timer reset", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ADC3RST", + "description": "ADC 3 interface reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 timer reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 timer reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TIM11RST", + "description": "TIM11 timer reset", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "Timer 4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "Timer 5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "Timer 7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12RST", + "description": "Timer 12 reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13RST", + "description": "Timer 13 reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "Timer 14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4RST", + "description": "UART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5RST", + "description": "UART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANRST", + "description": "CAN reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BKPRST", + "description": "Backup interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSMCEN", + "description": "FSMC clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFIOEN", + "description": "Alternate function I/O clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPEEN", + "description": "I/O port E clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IOPFEN", + "description": "I/O port F clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IOPGEN", + "description": "I/O port G clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC 2 interface clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TIM8EN", + "description": "TIM8 Timer clock enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ADC3EN", + "description": "ADC3 interface clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 Timer clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 Timer clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TIM11EN", + "description": "TIM11 Timer clock enable", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "Timer 4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "Timer 5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "Timer 7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12EN", + "description": "Timer 12 clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13EN", + "description": "Timer 13 clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "Timer 14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI 3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART 3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART 4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART 5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "USBEN", + "description": "USB clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CANEN", + "description": "CAN clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BKPEN", + "description": "Backup interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General purpose I/O", + "groupName": "GPIO", + "baseAddress": "0x40010800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CRL", + "displayName": "CRL", + "description": "Port configuration register low (GPIOn_CRL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE0", + "description": "Port n.0 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF0", + "description": "Port n.0 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE1", + "description": "Port n.1 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF1", + "description": "Port n.1 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE2", + "description": "Port n.2 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF2", + "description": "Port n.2 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE3", + "description": "Port n.3 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF3", + "description": "Port n.3 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE4", + "description": "Port n.4 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF4", + "description": "Port n.4 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE5", + "description": "Port n.5 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF5", + "description": "Port n.5 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE6", + "description": "Port n.6 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF6", + "description": "Port n.6 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE7", + "description": "Port n.7 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF7", + "description": "Port n.7 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "CRH", + "displayName": "CRH", + "description": "Port configuration register high (GPIOn_CRL)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE8", + "description": "Port n.8 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF8", + "description": "Port n.8 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE9", + "description": "Port n.9 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF9", + "description": "Port n.9 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE10", + "description": "Port n.10 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF10", + "description": "Port n.10 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE11", + "description": "Port n.11 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF11", + "description": "Port n.11 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE12", + "description": "Port n.12 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF12", + "description": "Port n.12 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE13", + "description": "Port n.13 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF13", + "description": "Port n.13 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE14", + "description": "Port n.14 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF14", + "description": "Port n.14 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE15", + "description": "Port n.15 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF15", + "description": "Port n.15 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Port input data register (GPIOn_IDR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "Port output data register (GPIOn_ODR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "Port bit set/reset register (GPIOn_BSRR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Set bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Set bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Set bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Set bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Set bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Set bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Set bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Set bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Set bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Set bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Set bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Set bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Set bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Set bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Set bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Set bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 2", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register (GPIOn_BRR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "Port configuration lock register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port A Lock bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port A Lock bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port A Lock bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port A Lock bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port A Lock bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port A Lock bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port A Lock bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port A Lock bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port A Lock bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port A Lock bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port A Lock bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port A Lock bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port A Lock bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port A Lock bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port A Lock bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port A Lock bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Lock key", + "bitOffset": "16", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOA", + "baseAddress": "0x40010C00" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011000" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011400" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011800" + }, + { + "name": "GPIOF", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011C00" + }, + { + "name": "GPIOG", + "derivedFrom": "GPIOA", + "baseAddress": "0x40012000" + }, + { + "name": "AFIO", + "description": "Alternate function I/O", + "groupName": "AFIO", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "EVCR", + "displayName": "EVCR", + "description": "Event Control Register (AFIO_EVCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PIN", + "description": "Pin selection", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "PORT", + "description": "Port selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "EVOE", + "description": "Event Output Enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "MAPR", + "displayName": "MAPR", + "description": "AF remap and debug I/O configuration register (AFIO_MAPR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SPI1_REMAP", + "description": "SPI1 remapping", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "I2C1_REMAP", + "description": "I2C1 remapping", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART1_REMAP", + "description": "USART1 remapping", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART2_REMAP", + "description": "USART2 remapping", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART3_REMAP", + "description": "USART3 remapping", + "bitOffset": "4", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM1_REMAP", + "description": "TIM1 remapping", + "bitOffset": "6", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM2_REMAP", + "description": "TIM2 remapping", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM3_REMAP", + "description": "TIM3 remapping", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM4_REMAP", + "description": "TIM4 remapping", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CAN_REMAP", + "description": "CAN1 remapping", + "bitOffset": "13", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PD01_REMAP", + "description": "Port D0/Port D1 mapping on OSCIN/OSCOUT", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIM5CH4_IREMAP", + "description": "Set and cleared by software", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC1_ETRGINJ_REMAP", + "description": "ADC 1 External trigger injected conversion remapping", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC1_ETRGREG_REMAP", + "description": "ADC 1 external trigger regular conversion remapping", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC2_ETRGINJ_REMAP", + "description": "ADC 2 external trigger injected conversion remapping", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ADC2_ETRGREG_REMAP", + "description": "ADC 2 external trigger regular conversion remapping", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWJ_CFG", + "description": "Serial wire JTAG configuration", + "bitOffset": "24", + "bitWidth": "3", + "access": "write-only" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1 (AFIO_EXTICR1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI0 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI1 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI2 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI3 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2 (AFIO_EXTICR2)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI4 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI5 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI6 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI7 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3 (AFIO_EXTICR3)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI8 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI9 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI11 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4 (AFIO_EXTICR4)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI12 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI13 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI14 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI15 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "MAPR2", + "displayName": "MAPR2", + "description": "AF remap and debug I/O configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM9_REMAP", + "description": "TIM9 remapping", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM10_REMAP", + "description": "TIM10 remapping", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM11_REMAP", + "description": "TIM11 remapping", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM13_REMAP", + "description": "TIM13 remapping", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIM14_REMAP", + "description": "TIM14 remapping", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSMC_NADV", + "description": "NADV connect/disconnect", + "bitOffset": "10", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "EXTI", + "description": "EXTI", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMPER", + "description": "Tamper interrupt", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_Channel1", + "description": "DMA1 Channel1 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Channel2", + "description": "DMA1 Channel2 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Channel3", + "description": "DMA1 Channel3 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Channel4", + "description": "DMA1 Channel4 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Channel5", + "description": "DMA1 Channel5 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Channel6", + "description": "DMA1 Channel6 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Channel7", + "description": "DMA1 Channel7 global interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DMA2", + "derivedFrom": "DMA1", + "baseAddress": "0x40020400", + "interrupts": [ + { + "name": "DMA2_Channel1", + "description": "DMA2 Channel1 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Channel2", + "description": "DMA2 Channel2 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Channel3", + "description": "DMA2 Channel3 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Channel4_5", + "description": "DMA2 Channel4 and DMA2 Channel5 global interrupt", + "value": "59" + } + ] + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40018000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Bits 1:0 = PWRCTRL: Power supply control bits", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register (SDIO_CLKCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Bits 31:0 = : Command argument", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "SDIO command register (SDIO_CMD)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDINDEX", + "description": "CMDINDEX", + "bitOffset": "0", + "bitWidth": "6" + }, + { + "name": "WAITRESP", + "description": "WAITRESP", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "WAITINT", + "description": "WAITINT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "WAITPEND", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "CPSMEN", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SDIOSuspend", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "ENCMDcompl", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "NIEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CE_ATACMD", + "description": "CE_ATACMD", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "SDIO command register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "RESPCMD", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESPI1", + "displayName": "RESPI1", + "description": "Bits 31:0 = CARDSTATUS1", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "CARDSTATUS1", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Bits 31:0 = CARDSTATUS2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "CARDSTATUS2", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Bits 31:0 = CARDSTATUS3", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "CARDSTATUS3", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Bits 31:0 = CARDSTATUS4", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "CARDSTATUS4", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Bits 31:0 = DATATIME: Data timeout period", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Bits 24:0 = DATALENGTH: Data length value", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "SDIO data control register (SDIO_DCTRL)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "DTDIR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "DTMODE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMAEN", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "DBLOCKSIZE", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "PWSTART", + "description": "PWSTART", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PWSTOP", + "description": "PWSTOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "RWMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIOEN", + "bitOffset": "11", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Bits 24:0 = DATACOUNT: Data count value", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "SDIO status register (SDIO_STA)", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAIL", + "description": "CCRCFAIL", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "DCRCFAIL", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "CTIMEOUT", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "DTIMEOUT", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "TXUNDERR", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "RXOVERR", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "CMDREND", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "CMDSENT", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "DATAEND", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "STBITERR", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "DBCKEND", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "CMDACT", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "TXACT", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "RXACT", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "TXFIFOHE", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "RXFIFOHF", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "TXFIFOF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "RXFIFOF", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "TXFIFOE", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "RXFIFOE", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "TXDAVL", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "RXDAVL", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIOIT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAEND", + "description": "CEATAEND", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "SDIO interrupt clear register (SDIO_ICR)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILC", + "description": "CCRCFAILC", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAILC", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUTC", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUTC", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERRC", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERRC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDRENDC", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENTC", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAENDC", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERRC", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKENDC", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOITC", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATAENDC", + "description": "CEATAENDC", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "SDIO mask register (SDIO_MASK)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCRCFAILIE", + "description": "CCRCFAILIE", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "DCRCFAILIE", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "CTIMEOUTIE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "DTIMEOUTIE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "TXUNDERRIE", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "RXOVERRIE", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "CMDRENDIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "CMDSENTIE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "DATAENDIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "STBITERRIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBACKENDIE", + "description": "DBACKENDIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "CMDACTIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "TXACTIE", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "RXACTIE", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "TXFIFOHEIE", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "RXFIFOHFIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "TXFIFOFIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "RXFIFOFIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "TXFIFOEIE", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "RXFIFOEIE", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "TXDAVLIE", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "RXDAVLIE", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIOITIE", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CEATENDIE", + "description": "CEATENDIE", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIF0COUNT", + "description": "FIF0COUNT", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Bits 31:0 = FIFOData: Receive and transmit FIFO data", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "FIFOData", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC global interrupt", + "value": "3" + }, + { + "name": "RTCAlarm", + "description": "RTC Alarms through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "CRH", + "displayName": "CRH", + "description": "RTC Control Register High", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SECIE", + "description": "Second interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ALRIE", + "description": "Alarm interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OWIE", + "description": "Overflow interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "CRL", + "displayName": "CRL", + "description": "RTC Control Register Low", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000020", + "fields": [ + { + "name": "SECF", + "description": "Second Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRF", + "description": "Alarm Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OWF", + "description": "Overflow Flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RSF", + "description": "Registers Synchronized Flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNF", + "description": "Configuration Flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTOFF", + "description": "RTC operation OFF", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRLH", + "displayName": "PRLH", + "description": "RTC Prescaler Load Register High", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRLH", + "description": "RTC Prescaler Load Register High", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "PRLL", + "displayName": "PRLL", + "description": "RTC Prescaler Load Register Low", + "addressOffset": "0xC", + "size": "0x20", + "access": "write-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "PRLL", + "description": "RTC Prescaler Divider Register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DIVH", + "displayName": "DIVH", + "description": "RTC Prescaler Divider Register High", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DIVH", + "description": "RTC prescaler divider register high", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DIVL", + "displayName": "DIVL", + "description": "RTC Prescaler Divider Register Low", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "DIVL", + "description": "RTC prescaler divider register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTH", + "displayName": "CNTH", + "description": "RTC Counter Register High", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTH", + "description": "RTC counter register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTL", + "displayName": "CNTL", + "description": "RTC Counter Register Low", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTL", + "description": "RTC counter register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRH", + "displayName": "ALRH", + "description": "RTC Alarm Register High", + "addressOffset": "0x20", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRH", + "description": "RTC alarm register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRL", + "displayName": "ALRL", + "description": "RTC Alarm Register Low", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRL", + "description": "RTC alarm register low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "BKP", + "description": "Backup registers", + "groupName": "BKP", + "baseAddress": "0x40006C04", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR1", + "displayName": "DR1", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D1", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR2", + "displayName": "DR2", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D2", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR3", + "displayName": "DR3", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D3", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR4", + "displayName": "DR4", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D4", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR5", + "displayName": "DR5", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D5", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR6", + "displayName": "DR6", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D6", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR7", + "displayName": "DR7", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D7", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR8", + "displayName": "DR8", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D8", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR9", + "displayName": "DR9", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D9", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR10", + "displayName": "DR10", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D10", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR11", + "displayName": "DR11", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR11", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR12", + "displayName": "DR12", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR12", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR13", + "displayName": "DR13", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR13", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR14", + "displayName": "DR14", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D14", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR15", + "displayName": "DR15", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D15", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR16", + "displayName": "DR16", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D16", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR17", + "displayName": "DR17", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D17", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR18", + "displayName": "DR18", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D18", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR19", + "displayName": "DR19", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D19", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR20", + "displayName": "DR20", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D20", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR21", + "displayName": "DR21", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D21", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR22", + "displayName": "DR22", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D22", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR23", + "displayName": "DR23", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D23", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR24", + "displayName": "DR24", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D24", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR25", + "displayName": "DR25", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D25", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR26", + "displayName": "DR26", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D26", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR27", + "displayName": "DR27", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D27", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR28", + "displayName": "DR28", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D28", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR29", + "displayName": "DR29", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D29", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR30", + "displayName": "DR30", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D30", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR31", + "displayName": "DR31", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D31", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR32", + "displayName": "DR32", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D32", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR33", + "displayName": "DR33", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D33", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR34", + "displayName": "DR34", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D34", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR35", + "displayName": "DR35", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D35", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR36", + "displayName": "DR36", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D36", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR37", + "displayName": "DR37", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D37", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR38", + "displayName": "DR38", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D38", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR39", + "displayName": "DR39", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D39", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR40", + "displayName": "DR40", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D40", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR41", + "displayName": "DR41", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D41", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR42", + "displayName": "DR42", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D42", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RTCCR", + "displayName": "RTCCR", + "description": "RTC clock calibration register (BKP_RTCCR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CAL", + "description": "Calibration value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "CCO", + "description": "Calibration Clock Output", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ASOE", + "description": "Alarm or second output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ASOS", + "description": "Alarm or second output selection", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Backup control register (BKP_CR)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPE", + "description": "Tamper pin enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPAL", + "description": "Tamper pin active level", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "BKP_CSR control/status register (BKP_CSR)", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTE", + "description": "Clear Tamper event", + "bitOffset": "0", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CTI", + "description": "Clear Tamper Interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TPIE", + "description": "Tamper Pin interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TEF", + "description": "Tamper Event Flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIF", + "description": "Tamper Interrupt Flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ] + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register (IWDG_KR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register (IWDG_PR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register (IWDG_RLR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (IWDG_SR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (WWDG_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register (WWDG_CFR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB", + "description": "Timer Base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (WWDG_SR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced timer", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40013400", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + }, + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + }, + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + }, + { + "name": "TIM8_CC", + "description": "TIM8 Capture Compare interrupt", + "value": "46" + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM2", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "derivedFrom": "TIM2", + "baseAddress": "0x40000C00", + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ] + }, + { + "name": "TIM9", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40014C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM12", + "derivedFrom": "TIM9", + "baseAddress": "0x40001800", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + } + ] + }, + { + "name": "TIM10", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40015000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM11", + "derivedFrom": "TIM10", + "baseAddress": "0x40015400", + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ] + }, + { + "name": "TIM13", + "derivedFrom": "TIM10", + "baseAddress": "0x40001C00", + "interrupts": [ + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + } + ] + }, + { + "name": "TIM14", + "derivedFrom": "TIM10", + "baseAddress": "0x40002000", + "interrupts": [ + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + } + ] + }, + { + "name": "TIM6", + "description": "Basic timer", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6", + "description": "TIM6 global interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "I2C1", + "description": "Inter integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ] + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ] + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C0", + "fields": [ + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ] + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ] + }, + { + "name": "ADC1", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DUALMOD", + "description": "Dual mode selection", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sample time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sample time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ADC2DATA", + "description": "ADC2 data", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "ADC2", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sample time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sample time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sample time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sample time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sample time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sample time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sample time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sample time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sample time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sample time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "ADC3", + "derivedFrom": "ADC2", + "baseAddress": "0x40013C00", + "interrupts": [ + { + "name": "ADC3", + "description": "ADC3 global interrupt", + "value": "47" + } + ] + }, + { + "name": "CAN", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupt", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_ESR", + "displayName": "CAN_ESR", + "description": "CAN_ESR", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_BTR", + "displayName": "CAN_BTR", + "description": "CAN_BTR", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + } + ] + }, + { + "name": "CAN_TI0R", + "displayName": "CAN_TI0R", + "description": "CAN_TI0R", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TDT0R", + "displayName": "CAN_TDT0R", + "description": "CAN_TDT0R", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_TDL0R", + "displayName": "CAN_TDL0R", + "description": "CAN_TDL0R", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH0R", + "displayName": "CAN_TDH0R", + "description": "CAN_TDH0R", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI1R", + "displayName": "CAN_TI1R", + "description": "CAN_TI1R", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TDT1R", + "displayName": "CAN_TDT1R", + "description": "CAN_TDT1R", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_TDL1R", + "displayName": "CAN_TDL1R", + "description": "CAN_TDL1R", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH1R", + "displayName": "CAN_TDH1R", + "description": "CAN_TDH1R", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI2R", + "displayName": "CAN_TI2R", + "description": "CAN_TI2R", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TDT2R", + "displayName": "CAN_TDT2R", + "description": "CAN_TDT2R", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_TDL2R", + "displayName": "CAN_TDL2R", + "description": "CAN_TDL2R", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH2R", + "displayName": "CAN_TDH2R", + "description": "CAN_TDH2R", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI0R", + "displayName": "CAN_RI0R", + "description": "CAN_RI0R", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_RDT0R", + "displayName": "CAN_RDT0R", + "description": "CAN_RDT0R", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_RDL0R", + "displayName": "CAN_RDL0R", + "description": "CAN_RDL0R", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH0R", + "displayName": "CAN_RDH0R", + "description": "CAN_RDH0R", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI1R", + "displayName": "CAN_RI1R", + "description": "CAN_RI1R", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_RDT1R", + "displayName": "CAN_RDT1R", + "description": "CAN_RDT1R", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_RDL1R", + "displayName": "CAN_RDL1R", + "description": "CAN_RDL1R", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH1R", + "displayName": "CAN_RDH1R", + "description": "CAN_RDH1R", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_FMR", + "displayName": "CAN_FMR", + "description": "CAN_FMR", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FM1R", + "displayName": "CAN_FM1R", + "description": "CAN_FM1R", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FS1R", + "displayName": "CAN_FS1R", + "description": "CAN_FS1R", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital to analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (DAC_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "DAC software trigger register (DAC_SWTRIGR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "20", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "DAC channel1 data output register (DAC_DOR1)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "DAC channel2 data output register (DAC_DOR2)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "DBGMCU_IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "DBGMCU_CR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "DBG_IWDG_STOP", + "description": "DBG_IWDG_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBG_TIM1_STOP", + "description": "DBG_TIM1_STOP", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DBG_I2C1_SMBUS_TIMEOUT", + "description": "DBG_I2C1_SMBUS_TIMEOUT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "DBG_TIM8_STOP", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "21", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "UART4", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART4_SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART4_DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART4_BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART4_CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART4_CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART4_CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "UART5", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40005000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART4_SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "PE", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "FE", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "NE", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "ORE", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "RXNE", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "TC", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "TXE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LBD", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART4_DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART4_BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART4_CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "SBK", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "RWU", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLEIE", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNEIE", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "TCIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXEIE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PEIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "PS", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "PCE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "WAKE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "M", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "UE", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART4_CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "ADD", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "LBDL", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LBDIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LINEN", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART4_CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "CRC calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "HLFCYA", + "description": "Flash half cycle access enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "Prefetch buffer enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "Prefetch buffer status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRTERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFFC", + "fields": [ + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RDPRT", + "description": "Read protection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "10", + "bitWidth": "8" + }, + { + "name": "Data1", + "description": "Data1", + "bitOffset": "18", + "bitWidth": "8" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1001", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ICTR", + "displayName": "ICTR", + "description": "Interrupt Controller Type Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTLINESNUM", + "description": "Total number of interrupt lines in groups", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "STIR", + "displayName": "STIR", + "description": "Software Triggered Interrupt Register", + "addressOffset": "0xF00", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTID", + "description": "Interrupt to be triggered", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "ISER0", + "displayName": "ISER0", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER1", + "displayName": "ISER1", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER0", + "displayName": "ICER0", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER1", + "displayName": "ICER1", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR0", + "displayName": "ISPR0", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR1", + "displayName": "ISPR1", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR0", + "displayName": "ICPR0", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR1", + "displayName": "ICPR1", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR0", + "displayName": "IABR0", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR1", + "displayName": "IABR1", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register", + "addressOffset": "0x404", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register", + "addressOffset": "0x408", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register", + "addressOffset": "0x40C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register", + "addressOffset": "0x410", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register", + "addressOffset": "0x414", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register", + "addressOffset": "0x418", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register", + "addressOffset": "0x41C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR8", + "displayName": "IPR8", + "description": "Interrupt Priority Register", + "addressOffset": "0x420", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR9", + "displayName": "IPR9", + "description": "Interrupt Priority Register", + "addressOffset": "0x424", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR10", + "displayName": "IPR10", + "description": "Interrupt Priority Register", + "addressOffset": "0x428", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR11", + "displayName": "IPR11", + "description": "Interrupt Priority Register", + "addressOffset": "0x42C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR12", + "displayName": "IPR12", + "description": "Interrupt Priority Register", + "addressOffset": "0x430", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR13", + "displayName": "IPR13", + "description": "Interrupt Priority Register", + "addressOffset": "0x434", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR14", + "displayName": "IPR14", + "description": "Interrupt Priority Register", + "addressOffset": "0x438", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "USB", + "description": "Universal serial bus full-speed device interface", + "groupName": "USB", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USB_FS_WKUP", + "description": "USB Device FS Wakeup through EXTI line interrupt", + "value": "42" + } + ], + "registers": [ + { + "name": "EP0R", + "displayName": "EP0R", + "description": "Endpoint 0 register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP1R", + "displayName": "EP1R", + "description": "Endpoint 1 register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP2R", + "displayName": "EP2R", + "description": "Endpoint 2 register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP3R", + "displayName": "EP3R", + "description": "Endpoint 3 register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP4R", + "displayName": "EP4R", + "description": "Endpoint 4 register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP5R", + "displayName": "EP5R", + "description": "Endpoint 5 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP6R", + "displayName": "EP6R", + "description": "Endpoint 6 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "EP7R", + "displayName": "EP7R", + "description": "Endpoint 7 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EA", + "description": "Endpoint address", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "STAT_TX", + "description": "Status bits, for transmission transfers", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DTOG_TX", + "description": "Data Toggle, for transmission transfers", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTR_TX", + "description": "Correct Transfer for transmission", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "EP_KIND", + "description": "Endpoint kind", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "EP_TYPE", + "description": "Endpoint type", + "bitOffset": "9", + "bitWidth": "2" + }, + { + "name": "SETUP", + "description": "Setup transaction completed", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "STAT_RX", + "description": "Status bits, for reception transfers", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "DTOG_RX", + "description": "Data Toggle, for reception transfers", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR_RX", + "description": "Correct transfer for reception", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "CNTR", + "displayName": "USB_CNTR", + "description": "Control register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000003", + "fields": [ + { + "name": "FRES", + "description": "Force USB Reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDWN", + "description": "Power down", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPMODE", + "description": "Low-power mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSUSP", + "description": "Force suspend", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RESUME", + "description": "Resume request", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ESOFM", + "description": "Expected start of frame interrupt mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOFM", + "description": "Start of frame interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESETM", + "description": "USB reset interrupt mask", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSPM", + "description": "Suspend mode interrupt mask", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUPM", + "description": "Wakeup interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERRM", + "description": "Error interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVRM", + "description": "Packet memory area over / underrun interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTRM", + "description": "Correct transfer interrupt mask", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ISTR", + "displayName": "ISTR", + "description": "Interrupt status register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EP_ID", + "description": "Endpoint Identifier", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIR", + "description": "Direction of transaction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ESOF", + "description": "Expected start frame", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "Reset request", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SUSP", + "description": "Suspend mode request", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WKUP", + "description": "Wakeup", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ERR", + "description": "Error", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PMAOVR", + "description": "Packet memory area over / underrun", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CTR", + "description": "Correct transfer", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "FNR", + "displayName": "FNR", + "description": "Frame number register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FN", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "LSOF", + "description": "Lost SOF", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "LCK", + "description": "Locked", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "RXDM", + "description": "Receive data - line status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXDP", + "description": "Receive data + line status", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "DADDR", + "displayName": "DADDR", + "description": "Device address", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD", + "description": "Device address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "EF", + "description": "Enable function", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "BTABLE", + "displayName": "BTABLE", + "description": "Buffer table address", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BTABLE", + "description": "Buffer table", + "bitOffset": "3", + "bitWidth": "13" + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/adc1.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc1.c new file mode 100644 index 0000000000..d084f312d9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc1.c @@ -0,0 +1,382 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smpr1 = cm_object_get_child_by_name(obj, "SMPR1"); + state->u.f1.reg.smpr2 = cm_object_get_child_by_name(obj, "SMPR2"); + state->u.f1.reg.jofr1 = cm_object_get_child_by_name(obj, "JOFR1"); + state->u.f1.reg.jofr2 = cm_object_get_child_by_name(obj, "JOFR2"); + state->u.f1.reg.jofr3 = cm_object_get_child_by_name(obj, "JOFR3"); + state->u.f1.reg.jofr4 = cm_object_get_child_by_name(obj, "JOFR4"); + state->u.f1.reg.htr = cm_object_get_child_by_name(obj, "HTR"); + state->u.f1.reg.ltr = cm_object_get_child_by_name(obj, "LTR"); + state->u.f1.reg.sqr1 = cm_object_get_child_by_name(obj, "SQR1"); + state->u.f1.reg.sqr2 = cm_object_get_child_by_name(obj, "SQR2"); + state->u.f1.reg.sqr3 = cm_object_get_child_by_name(obj, "SQR3"); + state->u.f1.reg.jsqr = cm_object_get_child_by_name(obj, "JSQR"); + state->u.f1.reg.jdr1 = cm_object_get_child_by_name(obj, "JDR1"); + state->u.f1.reg.jdr2 = cm_object_get_child_by_name(obj, "JDR2"); + state->u.f1.reg.jdr3 = cm_object_get_child_by_name(obj, "JDR3"); + state->u.f1.reg.jdr4 = cm_object_get_child_by_name(obj, "JDR4"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // SR bitfields. + state->u.f1.fld.sr.awd = cm_object_get_child_by_name(state->u.f1.reg.sr, "AWD"); + state->u.f1.fld.sr.eoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "EOC"); + state->u.f1.fld.sr.jeoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "JEOC"); + state->u.f1.fld.sr.jstrt = cm_object_get_child_by_name(state->u.f1.reg.sr, "JSTRT"); + state->u.f1.fld.sr.strt = cm_object_get_child_by_name(state->u.f1.reg.sr, "STRT"); + + // CR1 bitfields. + state->u.f1.fld.cr1.awdch = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDCH"); + state->u.f1.fld.cr1.eocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "EOCIE"); + state->u.f1.fld.cr1.awdie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDIE"); + state->u.f1.fld.cr1.jeocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JEOCIE"); + state->u.f1.fld.cr1.scan = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SCAN"); + state->u.f1.fld.cr1.awdsgl = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDSGL"); + state->u.f1.fld.cr1.jauto = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAUTO"); + state->u.f1.fld.cr1.discen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCEN"); + state->u.f1.fld.cr1.jdiscen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JDISCEN"); + state->u.f1.fld.cr1.discnum = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCNUM"); + state->u.f1.fld.cr1.dualmod = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DUALMOD"); + state->u.f1.fld.cr1.jawden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAWDEN"); + state->u.f1.fld.cr1.awden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDEN"); + + // CR2 bitfields. + state->u.f1.fld.cr2.adon = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADON"); + state->u.f1.fld.cr2.cont = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CONT"); + state->u.f1.fld.cr2.cal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CAL"); + state->u.f1.fld.cr2.rstcal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RSTCAL"); + state->u.f1.fld.cr2.dma = cm_object_get_child_by_name(state->u.f1.reg.cr2, "DMA"); + state->u.f1.fld.cr2.align = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ALIGN"); + state->u.f1.fld.cr2.jextsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTSEL"); + state->u.f1.fld.cr2.jexttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTTRIG"); + state->u.f1.fld.cr2.extsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTSEL"); + state->u.f1.fld.cr2.exttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTTRIG"); + state->u.f1.fld.cr2.jswstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JSWSTART"); + state->u.f1.fld.cr2.swstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "SWSTART"); + state->u.f1.fld.cr2.tsvrefe = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TSVREFE"); + + // SMPR1 bitfields. + state->u.f1.fld.smpr1.smp10 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP10"); + state->u.f1.fld.smpr1.smp11 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP11"); + state->u.f1.fld.smpr1.smp12 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP12"); + state->u.f1.fld.smpr1.smp13 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP13"); + state->u.f1.fld.smpr1.smp14 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP14"); + state->u.f1.fld.smpr1.smp15 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP15"); + state->u.f1.fld.smpr1.smp16 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP16"); + state->u.f1.fld.smpr1.smp17 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP17"); + + // SMPR2 bitfields. + state->u.f1.fld.smpr2.smp0 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP0"); + state->u.f1.fld.smpr2.smp1 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP1"); + state->u.f1.fld.smpr2.smp2 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP2"); + state->u.f1.fld.smpr2.smp3 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP3"); + state->u.f1.fld.smpr2.smp4 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP4"); + state->u.f1.fld.smpr2.smp5 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP5"); + state->u.f1.fld.smpr2.smp6 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP6"); + state->u.f1.fld.smpr2.smp7 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP7"); + state->u.f1.fld.smpr2.smp8 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP8"); + state->u.f1.fld.smpr2.smp9 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP9"); + + // JOFR1 bitfields. + state->u.f1.fld.jofr1.joffset1 = cm_object_get_child_by_name(state->u.f1.reg.jofr1, "JOFFSET1"); + + // JOFR2 bitfields. + state->u.f1.fld.jofr2.joffset2 = cm_object_get_child_by_name(state->u.f1.reg.jofr2, "JOFFSET2"); + + // JOFR3 bitfields. + state->u.f1.fld.jofr3.joffset3 = cm_object_get_child_by_name(state->u.f1.reg.jofr3, "JOFFSET3"); + + // JOFR4 bitfields. + state->u.f1.fld.jofr4.joffset4 = cm_object_get_child_by_name(state->u.f1.reg.jofr4, "JOFFSET4"); + + // HTR bitfields. + state->u.f1.fld.htr.ht = cm_object_get_child_by_name(state->u.f1.reg.htr, "HT"); + + // LTR bitfields. + state->u.f1.fld.ltr.lt = cm_object_get_child_by_name(state->u.f1.reg.ltr, "LT"); + + // SQR1 bitfields. + state->u.f1.fld.sqr1.sq13 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ13"); + state->u.f1.fld.sqr1.sq14 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ14"); + state->u.f1.fld.sqr1.sq15 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ15"); + state->u.f1.fld.sqr1.sq16 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ16"); + state->u.f1.fld.sqr1.l = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "L"); + + // SQR2 bitfields. + state->u.f1.fld.sqr2.sq7 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ7"); + state->u.f1.fld.sqr2.sq8 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ8"); + state->u.f1.fld.sqr2.sq9 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ9"); + state->u.f1.fld.sqr2.sq10 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ10"); + state->u.f1.fld.sqr2.sq11 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ11"); + state->u.f1.fld.sqr2.sq12 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ12"); + + // SQR3 bitfields. + state->u.f1.fld.sqr3.sq1 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ1"); + state->u.f1.fld.sqr3.sq2 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ2"); + state->u.f1.fld.sqr3.sq3 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ3"); + state->u.f1.fld.sqr3.sq4 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ4"); + state->u.f1.fld.sqr3.sq5 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ5"); + state->u.f1.fld.sqr3.sq6 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ6"); + + // JSQR bitfields. + state->u.f1.fld.jsqr.jsq1 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ1"); + state->u.f1.fld.jsqr.jsq2 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ2"); + state->u.f1.fld.jsqr.jsq3 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ3"); + state->u.f1.fld.jsqr.jsq4 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ4"); + state->u.f1.fld.jsqr.jl = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JL"); + + // JDR1 bitfields. + state->u.f1.fld.jdr1.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr1, "JDATA"); + + // JDR2 bitfields. + state->u.f1.fld.jdr2.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr2, "JDATA"); + + // JDR3 bitfields. + state->u.f1.fld.jdr3.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr3, "JDATA"); + + // JDR4 bitfields. + state->u.f1.fld.jdr4.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr4, "JDATA"); + + // DR bitfields. + state->u.f1.fld.dr.data = cm_object_get_child_by_name(state->u.f1.reg.dr, "DATA"); + state->u.f1.fld.dr.adc2data = cm_object_get_child_by_name(state->u.f1.reg.dr, "ADC2DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_ADC_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC%dEN", + 1 + state->port_index - STM32_PORT_ADC1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/adc1.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc1.h new file mode 100644 index 0000000000..ece9ae1e5a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc1.h @@ -0,0 +1,294 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_ADC1, + STM32_PORT_ADC2, + STM32_PORT_ADC3, + STM32_PORT_ADC_UNDEFINED = 0xFF, +} stm32_adc_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_adc_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ADC (Analog to digital converter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *cr1; // 0x4 (Control register 1) + Object *cr2; // 0x8 (Control register 2) + Object *smpr1; // 0xC (Sample time register 1) + Object *smpr2; // 0x10 (Sample time register 2) + Object *jofr1; // 0x14 (Injected channel data offset register x) + Object *jofr2; // 0x18 (Injected channel data offset register x) + Object *jofr3; // 0x1C (Injected channel data offset register x) + Object *jofr4; // 0x20 (Injected channel data offset register x) + Object *htr; // 0x24 (Watchdog higher threshold register) + Object *ltr; // 0x28 (Watchdog lower threshold register) + Object *sqr1; // 0x2C (Regular sequence register 1) + Object *sqr2; // 0x30 (Regular sequence register 2) + Object *sqr3; // 0x34 (Regular sequence register 3) + Object *jsqr; // 0x38 (Injected sequence register) + Object *jdr1; // 0x3C (Injected data register x) + Object *jdr2; // 0x40 (Injected data register x) + Object *jdr3; // 0x44 (Injected data register x) + Object *jdr4; // 0x48 (Injected data register x) + Object *dr; // 0x4C (Regular data register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *awd; // [0:0] Analog watchdog flag + Object *eoc; // [1:1] Regular channel end of conversion + Object *jeoc; // [2:2] Injected channel end of conversion + Object *jstrt; // [3:3] Injected channel start flag + Object *strt; // [4:4] Regular channel start flag + } sr; + + // CR1 (Control register 1) bitfields. + struct { + Object *awdch; // [0:4] Analog watchdog channel select bits + Object *eocie; // [5:5] Interrupt enable for EOC + Object *awdie; // [6:6] Analog watchdog interrupt enable + Object *jeocie; // [7:7] Interrupt enable for injected channels + Object *scan; // [8:8] Scan mode + Object *awdsgl; // [9:9] Enable the watchdog on a single channel in scan mode + Object *jauto; // [10:10] Automatic injected group conversion + Object *discen; // [11:11] Discontinuous mode on regular channels + Object *jdiscen; // [12:12] Discontinuous mode on injected channels + Object *discnum; // [13:15] Discontinuous mode channel count + Object *dualmod; // [16:19] Dual mode selection + Object *jawden; // [22:22] Analog watchdog enable on injected channels + Object *awden; // [23:23] Analog watchdog enable on regular channels + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *adon; // [0:0] A/D converter ON / OFF + Object *cont; // [1:1] Continuous conversion + Object *cal; // [2:2] A/D calibration + Object *rstcal; // [3:3] Reset calibration + Object *dma; // [8:8] Direct memory access mode + Object *align; // [11:11] Data alignment + Object *jextsel; // [12:14] External event select for injected group + Object *jexttrig; // [15:15] External trigger conversion mode for injected channels + Object *extsel; // [17:19] External event select for regular group + Object *exttrig; // [20:20] External trigger conversion mode for regular channels + Object *jswstart; // [21:21] Start conversion of injected channels + Object *swstart; // [22:22] Start conversion of regular channels + Object *tsvrefe; // [23:23] Temperature sensor and VREFINT enable + } cr2; + + // SMPR1 (Sample time register 1) bitfields. + struct { + Object *smp10; // [0:2] Channel 10 sample time selection + Object *smp11; // [3:5] Channel 11 sample time selection + Object *smp12; // [6:8] Channel 12 sample time selection + Object *smp13; // [9:11] Channel 13 sample time selection + Object *smp14; // [12:14] Channel 14 sample time selection + Object *smp15; // [15:17] Channel 15 sample time selection + Object *smp16; // [18:20] Channel 16 sample time selection + Object *smp17; // [21:23] Channel 17 sample time selection + } smpr1; + + // SMPR2 (Sample time register 2) bitfields. + struct { + Object *smp0; // [0:2] Channel 0 sample time selection + Object *smp1; // [3:5] Channel 1 sample time selection + Object *smp2; // [6:8] Channel 2 sample time selection + Object *smp3; // [9:11] Channel 3 sample time selection + Object *smp4; // [12:14] Channel 4 sample time selection + Object *smp5; // [15:17] Channel 5 sample time selection + Object *smp6; // [18:20] Channel 6 sample time selection + Object *smp7; // [21:23] Channel 7 sample time selection + Object *smp8; // [24:26] Channel 8 sample time selection + Object *smp9; // [27:29] Channel 9 sample time selection + } smpr2; + + // JOFR1 (Injected channel data offset register x) bitfields. + struct { + Object *joffset1; // [0:11] Data offset for injected channel x + } jofr1; + + // JOFR2 (Injected channel data offset register x) bitfields. + struct { + Object *joffset2; // [0:11] Data offset for injected channel x + } jofr2; + + // JOFR3 (Injected channel data offset register x) bitfields. + struct { + Object *joffset3; // [0:11] Data offset for injected channel x + } jofr3; + + // JOFR4 (Injected channel data offset register x) bitfields. + struct { + Object *joffset4; // [0:11] Data offset for injected channel x + } jofr4; + + // HTR (Watchdog higher threshold register) bitfields. + struct { + Object *ht; // [0:11] Analog watchdog higher threshold + } htr; + + // LTR (Watchdog lower threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + } ltr; + + // SQR1 (Regular sequence register 1) bitfields. + struct { + Object *sq13; // [0:4] 13th conversion in regular sequence + Object *sq14; // [5:9] 14th conversion in regular sequence + Object *sq15; // [10:14] 15th conversion in regular sequence + Object *sq16; // [15:19] 16th conversion in regular sequence + Object *l; // [20:23] Regular channel sequence length + } sqr1; + + // SQR2 (Regular sequence register 2) bitfields. + struct { + Object *sq7; // [0:4] 7th conversion in regular sequence + Object *sq8; // [5:9] 8th conversion in regular sequence + Object *sq9; // [10:14] 9th conversion in regular sequence + Object *sq10; // [15:19] 10th conversion in regular sequence + Object *sq11; // [20:24] 11th conversion in regular sequence + Object *sq12; // [25:29] 12th conversion in regular sequence + } sqr2; + + // SQR3 (Regular sequence register 3) bitfields. + struct { + Object *sq1; // [0:4] 1st conversion in regular sequence + Object *sq2; // [5:9] 2nd conversion in regular sequence + Object *sq3; // [10:14] 3rd conversion in regular sequence + Object *sq4; // [15:19] 4th conversion in regular sequence + Object *sq5; // [20:24] 5th conversion in regular sequence + Object *sq6; // [25:29] 6th conversion in regular sequence + } sqr3; + + // JSQR (Injected sequence register) bitfields. + struct { + Object *jsq1; // [0:4] 1st conversion in injected sequence + Object *jsq2; // [5:9] 2nd conversion in injected sequence + Object *jsq3; // [10:14] 3rd conversion in injected sequence + Object *jsq4; // [15:19] 4th conversion in injected sequence + Object *jl; // [20:21] Injected sequence length + } jsqr; + + // JDR1 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr1; + + // JDR2 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr2; + + // JDR3 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr3; + + // JDR4 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr4; + + // DR (Regular data register) bitfields. + struct { + Object *data; // [0:15] Regular data + Object *adc2data; // [16:31] ADC2 data + } dr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/adc2.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc2.c new file mode 100644 index 0000000000..f3be28feec --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc2.c @@ -0,0 +1,380 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smpr1 = cm_object_get_child_by_name(obj, "SMPR1"); + state->u.f1.reg.smpr2 = cm_object_get_child_by_name(obj, "SMPR2"); + state->u.f1.reg.jofr1 = cm_object_get_child_by_name(obj, "JOFR1"); + state->u.f1.reg.jofr2 = cm_object_get_child_by_name(obj, "JOFR2"); + state->u.f1.reg.jofr3 = cm_object_get_child_by_name(obj, "JOFR3"); + state->u.f1.reg.jofr4 = cm_object_get_child_by_name(obj, "JOFR4"); + state->u.f1.reg.htr = cm_object_get_child_by_name(obj, "HTR"); + state->u.f1.reg.ltr = cm_object_get_child_by_name(obj, "LTR"); + state->u.f1.reg.sqr1 = cm_object_get_child_by_name(obj, "SQR1"); + state->u.f1.reg.sqr2 = cm_object_get_child_by_name(obj, "SQR2"); + state->u.f1.reg.sqr3 = cm_object_get_child_by_name(obj, "SQR3"); + state->u.f1.reg.jsqr = cm_object_get_child_by_name(obj, "JSQR"); + state->u.f1.reg.jdr1 = cm_object_get_child_by_name(obj, "JDR1"); + state->u.f1.reg.jdr2 = cm_object_get_child_by_name(obj, "JDR2"); + state->u.f1.reg.jdr3 = cm_object_get_child_by_name(obj, "JDR3"); + state->u.f1.reg.jdr4 = cm_object_get_child_by_name(obj, "JDR4"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // SR bitfields. + state->u.f1.fld.sr.awd = cm_object_get_child_by_name(state->u.f1.reg.sr, "AWD"); + state->u.f1.fld.sr.eoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "EOC"); + state->u.f1.fld.sr.jeoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "JEOC"); + state->u.f1.fld.sr.jstrt = cm_object_get_child_by_name(state->u.f1.reg.sr, "JSTRT"); + state->u.f1.fld.sr.strt = cm_object_get_child_by_name(state->u.f1.reg.sr, "STRT"); + + // CR1 bitfields. + state->u.f1.fld.cr1.awdch = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDCH"); + state->u.f1.fld.cr1.eocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "EOCIE"); + state->u.f1.fld.cr1.awdie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDIE"); + state->u.f1.fld.cr1.jeocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JEOCIE"); + state->u.f1.fld.cr1.scan = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SCAN"); + state->u.f1.fld.cr1.awdsgl = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDSGL"); + state->u.f1.fld.cr1.jauto = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAUTO"); + state->u.f1.fld.cr1.discen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCEN"); + state->u.f1.fld.cr1.jdiscen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JDISCEN"); + state->u.f1.fld.cr1.discnum = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCNUM"); + state->u.f1.fld.cr1.jawden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAWDEN"); + state->u.f1.fld.cr1.awden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDEN"); + + // CR2 bitfields. + state->u.f1.fld.cr2.adon = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADON"); + state->u.f1.fld.cr2.cont = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CONT"); + state->u.f1.fld.cr2.cal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CAL"); + state->u.f1.fld.cr2.rstcal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RSTCAL"); + state->u.f1.fld.cr2.dma = cm_object_get_child_by_name(state->u.f1.reg.cr2, "DMA"); + state->u.f1.fld.cr2.align = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ALIGN"); + state->u.f1.fld.cr2.jextsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTSEL"); + state->u.f1.fld.cr2.jexttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTTRIG"); + state->u.f1.fld.cr2.extsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTSEL"); + state->u.f1.fld.cr2.exttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTTRIG"); + state->u.f1.fld.cr2.jswstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JSWSTART"); + state->u.f1.fld.cr2.swstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "SWSTART"); + state->u.f1.fld.cr2.tsvrefe = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TSVREFE"); + + // SMPR1 bitfields. + state->u.f1.fld.smpr1.smp10 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP10"); + state->u.f1.fld.smpr1.smp11 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP11"); + state->u.f1.fld.smpr1.smp12 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP12"); + state->u.f1.fld.smpr1.smp13 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP13"); + state->u.f1.fld.smpr1.smp14 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP14"); + state->u.f1.fld.smpr1.smp15 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP15"); + state->u.f1.fld.smpr1.smp16 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP16"); + state->u.f1.fld.smpr1.smp17 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP17"); + + // SMPR2 bitfields. + state->u.f1.fld.smpr2.smp0 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP0"); + state->u.f1.fld.smpr2.smp1 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP1"); + state->u.f1.fld.smpr2.smp2 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP2"); + state->u.f1.fld.smpr2.smp3 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP3"); + state->u.f1.fld.smpr2.smp4 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP4"); + state->u.f1.fld.smpr2.smp5 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP5"); + state->u.f1.fld.smpr2.smp6 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP6"); + state->u.f1.fld.smpr2.smp7 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP7"); + state->u.f1.fld.smpr2.smp8 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP8"); + state->u.f1.fld.smpr2.smp9 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP9"); + + // JOFR1 bitfields. + state->u.f1.fld.jofr1.joffset1 = cm_object_get_child_by_name(state->u.f1.reg.jofr1, "JOFFSET1"); + + // JOFR2 bitfields. + state->u.f1.fld.jofr2.joffset2 = cm_object_get_child_by_name(state->u.f1.reg.jofr2, "JOFFSET2"); + + // JOFR3 bitfields. + state->u.f1.fld.jofr3.joffset3 = cm_object_get_child_by_name(state->u.f1.reg.jofr3, "JOFFSET3"); + + // JOFR4 bitfields. + state->u.f1.fld.jofr4.joffset4 = cm_object_get_child_by_name(state->u.f1.reg.jofr4, "JOFFSET4"); + + // HTR bitfields. + state->u.f1.fld.htr.ht = cm_object_get_child_by_name(state->u.f1.reg.htr, "HT"); + + // LTR bitfields. + state->u.f1.fld.ltr.lt = cm_object_get_child_by_name(state->u.f1.reg.ltr, "LT"); + + // SQR1 bitfields. + state->u.f1.fld.sqr1.sq13 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ13"); + state->u.f1.fld.sqr1.sq14 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ14"); + state->u.f1.fld.sqr1.sq15 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ15"); + state->u.f1.fld.sqr1.sq16 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ16"); + state->u.f1.fld.sqr1.l = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "L"); + + // SQR2 bitfields. + state->u.f1.fld.sqr2.sq7 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ7"); + state->u.f1.fld.sqr2.sq8 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ8"); + state->u.f1.fld.sqr2.sq9 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ9"); + state->u.f1.fld.sqr2.sq10 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ10"); + state->u.f1.fld.sqr2.sq11 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ11"); + state->u.f1.fld.sqr2.sq12 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ12"); + + // SQR3 bitfields. + state->u.f1.fld.sqr3.sq1 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ1"); + state->u.f1.fld.sqr3.sq2 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ2"); + state->u.f1.fld.sqr3.sq3 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ3"); + state->u.f1.fld.sqr3.sq4 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ4"); + state->u.f1.fld.sqr3.sq5 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ5"); + state->u.f1.fld.sqr3.sq6 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ6"); + + // JSQR bitfields. + state->u.f1.fld.jsqr.jsq1 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ1"); + state->u.f1.fld.jsqr.jsq2 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ2"); + state->u.f1.fld.jsqr.jsq3 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ3"); + state->u.f1.fld.jsqr.jsq4 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ4"); + state->u.f1.fld.jsqr.jl = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JL"); + + // JDR1 bitfields. + state->u.f1.fld.jdr1.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr1, "JDATA"); + + // JDR2 bitfields. + state->u.f1.fld.jdr2.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr2, "JDATA"); + + // JDR3 bitfields. + state->u.f1.fld.jdr3.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr3, "JDATA"); + + // JDR4 bitfields. + state->u.f1.fld.jdr4.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr4, "JDATA"); + + // DR bitfields. + state->u.f1.fld.dr.data = cm_object_get_child_by_name(state->u.f1.reg.dr, "DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_ADC_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC%dEN", + 1 + state->port_index - STM32_PORT_ADC1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/adc2.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc2.h new file mode 100644 index 0000000000..2397233438 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/adc2.h @@ -0,0 +1,292 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_ADC1, + STM32_PORT_ADC2, + STM32_PORT_ADC3, + STM32_PORT_ADC_UNDEFINED = 0xFF, +} stm32_adc_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_adc_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ADC (Analog to digital converter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *cr1; // 0x4 (Control register 1) + Object *cr2; // 0x8 (Control register 2) + Object *smpr1; // 0xC (Sample time register 1) + Object *smpr2; // 0x10 (Sample time register 2) + Object *jofr1; // 0x14 (Injected channel data offset register x) + Object *jofr2; // 0x18 (Injected channel data offset register x) + Object *jofr3; // 0x1C (Injected channel data offset register x) + Object *jofr4; // 0x20 (Injected channel data offset register x) + Object *htr; // 0x24 (Watchdog higher threshold register) + Object *ltr; // 0x28 (Watchdog lower threshold register) + Object *sqr1; // 0x2C (Regular sequence register 1) + Object *sqr2; // 0x30 (Regular sequence register 2) + Object *sqr3; // 0x34 (Regular sequence register 3) + Object *jsqr; // 0x38 (Injected sequence register) + Object *jdr1; // 0x3C (Injected data register x) + Object *jdr2; // 0x40 (Injected data register x) + Object *jdr3; // 0x44 (Injected data register x) + Object *jdr4; // 0x48 (Injected data register x) + Object *dr; // 0x4C (Regular data register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *awd; // [0:0] Analog watchdog flag + Object *eoc; // [1:1] Regular channel end of conversion + Object *jeoc; // [2:2] Injected channel end of conversion + Object *jstrt; // [3:3] Injected channel start flag + Object *strt; // [4:4] Regular channel start flag + } sr; + + // CR1 (Control register 1) bitfields. + struct { + Object *awdch; // [0:4] Analog watchdog channel select bits + Object *eocie; // [5:5] Interrupt enable for EOC + Object *awdie; // [6:6] Analog watchdog interrupt enable + Object *jeocie; // [7:7] Interrupt enable for injected channels + Object *scan; // [8:8] Scan mode + Object *awdsgl; // [9:9] Enable the watchdog on a single channel in scan mode + Object *jauto; // [10:10] Automatic injected group conversion + Object *discen; // [11:11] Discontinuous mode on regular channels + Object *jdiscen; // [12:12] Discontinuous mode on injected channels + Object *discnum; // [13:15] Discontinuous mode channel count + Object *jawden; // [22:22] Analog watchdog enable on injected channels + Object *awden; // [23:23] Analog watchdog enable on regular channels + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *adon; // [0:0] A/D converter ON / OFF + Object *cont; // [1:1] Continuous conversion + Object *cal; // [2:2] A/D calibration + Object *rstcal; // [3:3] Reset calibration + Object *dma; // [8:8] Direct memory access mode + Object *align; // [11:11] Data alignment + Object *jextsel; // [12:14] External event select for injected group + Object *jexttrig; // [15:15] External trigger conversion mode for injected channels + Object *extsel; // [17:19] External event select for regular group + Object *exttrig; // [20:20] External trigger conversion mode for regular channels + Object *jswstart; // [21:21] Start conversion of injected channels + Object *swstart; // [22:22] Start conversion of regular channels + Object *tsvrefe; // [23:23] Temperature sensor and VREFINT enable + } cr2; + + // SMPR1 (Sample time register 1) bitfields. + struct { + Object *smp10; // [0:2] Channel 10 sample time selection + Object *smp11; // [3:5] Channel 11 sample time selection + Object *smp12; // [6:8] Channel 12 sample time selection + Object *smp13; // [9:11] Channel 13 sample time selection + Object *smp14; // [12:14] Channel 14 sample time selection + Object *smp15; // [15:17] Channel 15 sample time selection + Object *smp16; // [18:20] Channel 16 sample time selection + Object *smp17; // [21:23] Channel 17 sample time selection + } smpr1; + + // SMPR2 (Sample time register 2) bitfields. + struct { + Object *smp0; // [0:2] Channel 0 sample time selection + Object *smp1; // [3:5] Channel 1 sample time selection + Object *smp2; // [6:8] Channel 2 sample time selection + Object *smp3; // [9:11] Channel 3 sample time selection + Object *smp4; // [12:14] Channel 4 sample time selection + Object *smp5; // [15:17] Channel 5 sample time selection + Object *smp6; // [18:20] Channel 6 sample time selection + Object *smp7; // [21:23] Channel 7 sample time selection + Object *smp8; // [24:26] Channel 8 sample time selection + Object *smp9; // [27:29] Channel 9 sample time selection + } smpr2; + + // JOFR1 (Injected channel data offset register x) bitfields. + struct { + Object *joffset1; // [0:11] Data offset for injected channel x + } jofr1; + + // JOFR2 (Injected channel data offset register x) bitfields. + struct { + Object *joffset2; // [0:11] Data offset for injected channel x + } jofr2; + + // JOFR3 (Injected channel data offset register x) bitfields. + struct { + Object *joffset3; // [0:11] Data offset for injected channel x + } jofr3; + + // JOFR4 (Injected channel data offset register x) bitfields. + struct { + Object *joffset4; // [0:11] Data offset for injected channel x + } jofr4; + + // HTR (Watchdog higher threshold register) bitfields. + struct { + Object *ht; // [0:11] Analog watchdog higher threshold + } htr; + + // LTR (Watchdog lower threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + } ltr; + + // SQR1 (Regular sequence register 1) bitfields. + struct { + Object *sq13; // [0:4] 13th conversion in regular sequence + Object *sq14; // [5:9] 14th conversion in regular sequence + Object *sq15; // [10:14] 15th conversion in regular sequence + Object *sq16; // [15:19] 16th conversion in regular sequence + Object *l; // [20:23] Regular channel sequence length + } sqr1; + + // SQR2 (Regular sequence register 2) bitfields. + struct { + Object *sq7; // [0:4] 7th conversion in regular sequence + Object *sq8; // [5:9] 8th conversion in regular sequence + Object *sq9; // [10:14] 9th conversion in regular sequence + Object *sq10; // [15:19] 10th conversion in regular sequence + Object *sq11; // [20:24] 11th conversion in regular sequence + Object *sq12; // [25:29] 12th conversion in regular sequence + } sqr2; + + // SQR3 (Regular sequence register 3) bitfields. + struct { + Object *sq1; // [0:4] 1st conversion in regular sequence + Object *sq2; // [5:9] 2nd conversion in regular sequence + Object *sq3; // [10:14] 3rd conversion in regular sequence + Object *sq4; // [15:19] 4th conversion in regular sequence + Object *sq5; // [20:24] 5th conversion in regular sequence + Object *sq6; // [25:29] 6th conversion in regular sequence + } sqr3; + + // JSQR (Injected sequence register) bitfields. + struct { + Object *jsq1; // [0:4] 1st conversion in injected sequence + Object *jsq2; // [5:9] 2nd conversion in injected sequence + Object *jsq3; // [10:14] 3rd conversion in injected sequence + Object *jsq4; // [15:19] 4th conversion in injected sequence + Object *jl; // [20:21] Injected sequence length + } jsqr; + + // JDR1 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr1; + + // JDR2 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr2; + + // JDR3 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr3; + + // JDR4 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr4; + + // DR (Regular data register) bitfields. + struct { + Object *data; // [0:15] Regular data + } dr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/afio.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/afio.c new file mode 100644 index 0000000000..52beccd6bc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/afio.c @@ -0,0 +1,297 @@ +/* + * STM32 - AFIO (Alternate function I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_afio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32AFIOState *state = STM32_AFIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.evcr = cm_object_get_child_by_name(obj, "EVCR"); + state->u.f1.reg.mapr = cm_object_get_child_by_name(obj, "MAPR"); + state->u.f1.reg.exticr1 = cm_object_get_child_by_name(obj, "EXTICR1"); + state->u.f1.reg.exticr2 = cm_object_get_child_by_name(obj, "EXTICR2"); + state->u.f1.reg.exticr3 = cm_object_get_child_by_name(obj, "EXTICR3"); + state->u.f1.reg.exticr4 = cm_object_get_child_by_name(obj, "EXTICR4"); + state->u.f1.reg.mapr2 = cm_object_get_child_by_name(obj, "MAPR2"); + + + // EVCR bitfields. + state->u.f1.fld.evcr.pin = cm_object_get_child_by_name(state->u.f1.reg.evcr, "PIN"); + state->u.f1.fld.evcr.port = cm_object_get_child_by_name(state->u.f1.reg.evcr, "PORT"); + state->u.f1.fld.evcr.evoe = cm_object_get_child_by_name(state->u.f1.reg.evcr, "EVOE"); + + // MAPR bitfields. + state->u.f1.fld.mapr.spi1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "SPI1_REMAP"); + state->u.f1.fld.mapr.i2c1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "I2C1_REMAP"); + state->u.f1.fld.mapr.usart1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "USART1_REMAP"); + state->u.f1.fld.mapr.usart2_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "USART2_REMAP"); + state->u.f1.fld.mapr.usart3_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "USART3_REMAP"); + state->u.f1.fld.mapr.tim1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM1_REMAP"); + state->u.f1.fld.mapr.tim2_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM2_REMAP"); + state->u.f1.fld.mapr.tim3_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM3_REMAP"); + state->u.f1.fld.mapr.tim4_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM4_REMAP"); + state->u.f1.fld.mapr.can_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "CAN_REMAP"); + state->u.f1.fld.mapr.pd01_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "PD01_REMAP"); + state->u.f1.fld.mapr.tim5ch4_iremap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM5CH4_IREMAP"); + state->u.f1.fld.mapr.adc1_etrginj_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "ADC1_ETRGINJ_REMAP"); + state->u.f1.fld.mapr.adc1_etrgreg_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "ADC1_ETRGREG_REMAP"); + state->u.f1.fld.mapr.adc2_etrginj_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "ADC2_ETRGINJ_REMAP"); + state->u.f1.fld.mapr.adc2_etrgreg_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "ADC2_ETRGREG_REMAP"); + state->u.f1.fld.mapr.swj_cfg = cm_object_get_child_by_name(state->u.f1.reg.mapr, "SWJ_CFG"); + + // EXTICR1 bitfields. + state->u.f1.fld.exticr1.exti0 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI0"); + state->u.f1.fld.exticr1.exti1 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI1"); + state->u.f1.fld.exticr1.exti2 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI2"); + state->u.f1.fld.exticr1.exti3 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI3"); + + // EXTICR2 bitfields. + state->u.f1.fld.exticr2.exti4 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI4"); + state->u.f1.fld.exticr2.exti5 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI5"); + state->u.f1.fld.exticr2.exti6 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI6"); + state->u.f1.fld.exticr2.exti7 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI7"); + + // EXTICR3 bitfields. + state->u.f1.fld.exticr3.exti8 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI8"); + state->u.f1.fld.exticr3.exti9 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI9"); + state->u.f1.fld.exticr3.exti10 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI10"); + state->u.f1.fld.exticr3.exti11 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI11"); + + // EXTICR4 bitfields. + state->u.f1.fld.exticr4.exti12 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI12"); + state->u.f1.fld.exticr4.exti13 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI13"); + state->u.f1.fld.exticr4.exti14 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI14"); + state->u.f1.fld.exticr4.exti15 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI15"); + + // MAPR2 bitfields. + state->u.f1.fld.mapr2.tim9_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM9_REMAP"); + state->u.f1.fld.mapr2.tim10_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM10_REMAP"); + state->u.f1.fld.mapr2.tim11_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM11_REMAP"); + state->u.f1.fld.mapr2.tim13_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM13_REMAP"); + state->u.f1.fld.mapr2.tim14_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM14_REMAP"); + state->u.f1.fld.mapr2.fsmc_nadv = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "FSMC_NADV"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_afio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_afio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_afio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_afio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_afio_is_enabled(Object *obj) +{ + STM32AFIOState *state = STM32_AFIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_afio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32AFIOState *state = STM32_AFIO_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_afio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_AFIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32AFIOState *state = STM32_AFIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "AFIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_afio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_afio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_afio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_afio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_afio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/AFIOEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_afio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_AFIO); +} + +static void stm32_afio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_afio_reset_callback; + dc->realize = stm32_afio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_afio_is_enabled; +} + +static const TypeInfo stm32_afio_type_info = { + .name = TYPE_STM32_AFIO, + .parent = TYPE_STM32_AFIO_PARENT, + .instance_init = stm32_afio_instance_init_callback, + .instance_size = sizeof(STM32AFIOState), + .class_init = stm32_afio_class_init_callback, + .class_size = sizeof(STM32AFIOClass) }; + +static void stm32_afio_register_types(void) +{ + type_register_static(&stm32_afio_type_info); +} + +type_init(stm32_afio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/afio.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/afio.h new file mode 100644 index 0000000000..70fba75abd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/afio.h @@ -0,0 +1,176 @@ +/* + * STM32 - AFIO (Alternate function I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_AFIO_H_ +#define STM32_AFIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_AFIO DEVICE_PATH_STM32 "AFIO" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_AFIO TYPE_STM32_PREFIX "afio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_AFIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32AFIOParentClass; +typedef PeripheralState STM32AFIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_AFIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32AFIOClass, (obj), TYPE_STM32_AFIO) +#define STM32_AFIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32AFIOClass, (klass), TYPE_STM32_AFIO) + +typedef struct { + // private: + STM32AFIOParentClass parent_class; + // public: + + // None, so far. +} STM32AFIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_AFIO_STATE(obj) \ + OBJECT_CHECK(STM32AFIOState, (obj), TYPE_STM32_AFIO) + +typedef struct { + // private: + STM32AFIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 AFIO (Alternate function I/O) registers. + struct { + Object *evcr; // 0x0 (Event Control Register (AFIO_EVCR)) + Object *mapr; // 0x4 (AF remap and debug I/O configuration register (AFIO_MAPR)) + Object *exticr1; // 0x8 (External interrupt configuration register 1 (AFIO_EXTICR1)) + Object *exticr2; // 0xC (External interrupt configuration register 2 (AFIO_EXTICR2)) + Object *exticr3; // 0x10 (External interrupt configuration register 3 (AFIO_EXTICR3)) + Object *exticr4; // 0x14 (External interrupt configuration register 4 (AFIO_EXTICR4)) + Object *mapr2; // 0x1C (AF remap and debug I/O configuration register) + } reg; + + struct { + + // EVCR (Event Control Register (AFIO_EVCR)) bitfields. + struct { + Object *pin; // [0:3] Pin selection + Object *port; // [4:6] Port selection + Object *evoe; // [7:7] Event Output Enable + } evcr; + + // MAPR (AF remap and debug I/O configuration register (AFIO_MAPR)) bitfields. + struct { + Object *spi1_remap; // [0:0] SPI1 remapping + Object *i2c1_remap; // [1:1] I2C1 remapping + Object *usart1_remap; // [2:2] USART1 remapping + Object *usart2_remap; // [3:3] USART2 remapping + Object *usart3_remap; // [4:5] USART3 remapping + Object *tim1_remap; // [6:7] TIM1 remapping + Object *tim2_remap; // [8:9] TIM2 remapping + Object *tim3_remap; // [10:11] TIM3 remapping + Object *tim4_remap; // [12:12] TIM4 remapping + Object *can_remap; // [13:14] CAN1 remapping + Object *pd01_remap; // [15:15] Port D0/Port D1 mapping on OSCIN/OSCOUT + Object *tim5ch4_iremap; // [16:16] Set and cleared by software + Object *adc1_etrginj_remap; // [17:17] ADC 1 External trigger injected conversion remapping + Object *adc1_etrgreg_remap; // [18:18] ADC 1 external trigger regular conversion remapping + Object *adc2_etrginj_remap; // [19:19] ADC 2 external trigger injected conversion remapping + Object *adc2_etrgreg_remap; // [20:20] ADC 2 external trigger regular conversion remapping + Object *swj_cfg; // [24:26] Serial wire JTAG configuration + } mapr; + + // EXTICR1 (External interrupt configuration register 1 (AFIO_EXTICR1)) bitfields. + struct { + Object *exti0; // [0:3] EXTI0 configuration + Object *exti1; // [4:7] EXTI1 configuration + Object *exti2; // [8:11] EXTI2 configuration + Object *exti3; // [12:15] EXTI3 configuration + } exticr1; + + // EXTICR2 (External interrupt configuration register 2 (AFIO_EXTICR2)) bitfields. + struct { + Object *exti4; // [0:3] EXTI4 configuration + Object *exti5; // [4:7] EXTI5 configuration + Object *exti6; // [8:11] EXTI6 configuration + Object *exti7; // [12:15] EXTI7 configuration + } exticr2; + + // EXTICR3 (External interrupt configuration register 3 (AFIO_EXTICR3)) bitfields. + struct { + Object *exti8; // [0:3] EXTI8 configuration + Object *exti9; // [4:7] EXTI9 configuration + Object *exti10; // [8:11] EXTI10 configuration + Object *exti11; // [12:15] EXTI11 configuration + } exticr3; + + // EXTICR4 (External interrupt configuration register 4 (AFIO_EXTICR4)) bitfields. + struct { + Object *exti12; // [0:3] EXTI12 configuration + Object *exti13; // [4:7] EXTI13 configuration + Object *exti14; // [8:11] EXTI14 configuration + Object *exti15; // [12:15] EXTI15 configuration + } exticr4; + + // MAPR2 (AF remap and debug I/O configuration register) bitfields. + struct { + Object *tim9_remap; // [5:5] TIM9 remapping + Object *tim10_remap; // [6:6] TIM10 remapping + Object *tim11_remap; // [7:7] TIM11 remapping + Object *tim13_remap; // [8:8] TIM13 remapping + Object *tim14_remap; // [9:9] TIM14 remapping + Object *fsmc_nadv; // [10:10] NADV connect/disconnect + } mapr2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32AFIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_AFIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/bkp.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/bkp.c new file mode 100644 index 0000000000..90fe857e59 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/bkp.c @@ -0,0 +1,422 @@ +/* + * STM32 - BKP (Backup registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_bkp_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32BKPState *state = STM32_BKP_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.dr1 = cm_object_get_child_by_name(obj, "DR1"); + state->u.f1.reg.dr2 = cm_object_get_child_by_name(obj, "DR2"); + state->u.f1.reg.dr3 = cm_object_get_child_by_name(obj, "DR3"); + state->u.f1.reg.dr4 = cm_object_get_child_by_name(obj, "DR4"); + state->u.f1.reg.dr5 = cm_object_get_child_by_name(obj, "DR5"); + state->u.f1.reg.dr6 = cm_object_get_child_by_name(obj, "DR6"); + state->u.f1.reg.dr7 = cm_object_get_child_by_name(obj, "DR7"); + state->u.f1.reg.dr8 = cm_object_get_child_by_name(obj, "DR8"); + state->u.f1.reg.dr9 = cm_object_get_child_by_name(obj, "DR9"); + state->u.f1.reg.dr10 = cm_object_get_child_by_name(obj, "DR10"); + state->u.f1.reg.dr11 = cm_object_get_child_by_name(obj, "DR11"); + state->u.f1.reg.dr12 = cm_object_get_child_by_name(obj, "DR12"); + state->u.f1.reg.dr13 = cm_object_get_child_by_name(obj, "DR13"); + state->u.f1.reg.dr14 = cm_object_get_child_by_name(obj, "DR14"); + state->u.f1.reg.dr15 = cm_object_get_child_by_name(obj, "DR15"); + state->u.f1.reg.dr16 = cm_object_get_child_by_name(obj, "DR16"); + state->u.f1.reg.dr17 = cm_object_get_child_by_name(obj, "DR17"); + state->u.f1.reg.dr18 = cm_object_get_child_by_name(obj, "DR18"); + state->u.f1.reg.dr19 = cm_object_get_child_by_name(obj, "DR19"); + state->u.f1.reg.dr20 = cm_object_get_child_by_name(obj, "DR20"); + state->u.f1.reg.dr21 = cm_object_get_child_by_name(obj, "DR21"); + state->u.f1.reg.dr22 = cm_object_get_child_by_name(obj, "DR22"); + state->u.f1.reg.dr23 = cm_object_get_child_by_name(obj, "DR23"); + state->u.f1.reg.dr24 = cm_object_get_child_by_name(obj, "DR24"); + state->u.f1.reg.dr25 = cm_object_get_child_by_name(obj, "DR25"); + state->u.f1.reg.dr26 = cm_object_get_child_by_name(obj, "DR26"); + state->u.f1.reg.dr27 = cm_object_get_child_by_name(obj, "DR27"); + state->u.f1.reg.dr28 = cm_object_get_child_by_name(obj, "DR28"); + state->u.f1.reg.dr29 = cm_object_get_child_by_name(obj, "DR29"); + state->u.f1.reg.dr30 = cm_object_get_child_by_name(obj, "DR30"); + state->u.f1.reg.dr31 = cm_object_get_child_by_name(obj, "DR31"); + state->u.f1.reg.dr32 = cm_object_get_child_by_name(obj, "DR32"); + state->u.f1.reg.dr33 = cm_object_get_child_by_name(obj, "DR33"); + state->u.f1.reg.dr34 = cm_object_get_child_by_name(obj, "DR34"); + state->u.f1.reg.dr35 = cm_object_get_child_by_name(obj, "DR35"); + state->u.f1.reg.dr36 = cm_object_get_child_by_name(obj, "DR36"); + state->u.f1.reg.dr37 = cm_object_get_child_by_name(obj, "DR37"); + state->u.f1.reg.dr38 = cm_object_get_child_by_name(obj, "DR38"); + state->u.f1.reg.dr39 = cm_object_get_child_by_name(obj, "DR39"); + state->u.f1.reg.dr40 = cm_object_get_child_by_name(obj, "DR40"); + state->u.f1.reg.dr41 = cm_object_get_child_by_name(obj, "DR41"); + state->u.f1.reg.dr42 = cm_object_get_child_by_name(obj, "DR42"); + state->u.f1.reg.rtccr = cm_object_get_child_by_name(obj, "RTCCR"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // DR1 bitfields. + state->u.f1.fld.dr1.d1 = cm_object_get_child_by_name(state->u.f1.reg.dr1, "D1"); + + // DR2 bitfields. + state->u.f1.fld.dr2.d2 = cm_object_get_child_by_name(state->u.f1.reg.dr2, "D2"); + + // DR3 bitfields. + state->u.f1.fld.dr3.d3 = cm_object_get_child_by_name(state->u.f1.reg.dr3, "D3"); + + // DR4 bitfields. + state->u.f1.fld.dr4.d4 = cm_object_get_child_by_name(state->u.f1.reg.dr4, "D4"); + + // DR5 bitfields. + state->u.f1.fld.dr5.d5 = cm_object_get_child_by_name(state->u.f1.reg.dr5, "D5"); + + // DR6 bitfields. + state->u.f1.fld.dr6.d6 = cm_object_get_child_by_name(state->u.f1.reg.dr6, "D6"); + + // DR7 bitfields. + state->u.f1.fld.dr7.d7 = cm_object_get_child_by_name(state->u.f1.reg.dr7, "D7"); + + // DR8 bitfields. + state->u.f1.fld.dr8.d8 = cm_object_get_child_by_name(state->u.f1.reg.dr8, "D8"); + + // DR9 bitfields. + state->u.f1.fld.dr9.d9 = cm_object_get_child_by_name(state->u.f1.reg.dr9, "D9"); + + // DR10 bitfields. + state->u.f1.fld.dr10.d10 = cm_object_get_child_by_name(state->u.f1.reg.dr10, "D10"); + + // DR11 bitfields. + state->u.f1.fld.dr11.dr11 = cm_object_get_child_by_name(state->u.f1.reg.dr11, "DR11"); + + // DR12 bitfields. + state->u.f1.fld.dr12.dr12 = cm_object_get_child_by_name(state->u.f1.reg.dr12, "DR12"); + + // DR13 bitfields. + state->u.f1.fld.dr13.dr13 = cm_object_get_child_by_name(state->u.f1.reg.dr13, "DR13"); + + // DR14 bitfields. + state->u.f1.fld.dr14.d14 = cm_object_get_child_by_name(state->u.f1.reg.dr14, "D14"); + + // DR15 bitfields. + state->u.f1.fld.dr15.d15 = cm_object_get_child_by_name(state->u.f1.reg.dr15, "D15"); + + // DR16 bitfields. + state->u.f1.fld.dr16.d16 = cm_object_get_child_by_name(state->u.f1.reg.dr16, "D16"); + + // DR17 bitfields. + state->u.f1.fld.dr17.d17 = cm_object_get_child_by_name(state->u.f1.reg.dr17, "D17"); + + // DR18 bitfields. + state->u.f1.fld.dr18.d18 = cm_object_get_child_by_name(state->u.f1.reg.dr18, "D18"); + + // DR19 bitfields. + state->u.f1.fld.dr19.d19 = cm_object_get_child_by_name(state->u.f1.reg.dr19, "D19"); + + // DR20 bitfields. + state->u.f1.fld.dr20.d20 = cm_object_get_child_by_name(state->u.f1.reg.dr20, "D20"); + + // DR21 bitfields. + state->u.f1.fld.dr21.d21 = cm_object_get_child_by_name(state->u.f1.reg.dr21, "D21"); + + // DR22 bitfields. + state->u.f1.fld.dr22.d22 = cm_object_get_child_by_name(state->u.f1.reg.dr22, "D22"); + + // DR23 bitfields. + state->u.f1.fld.dr23.d23 = cm_object_get_child_by_name(state->u.f1.reg.dr23, "D23"); + + // DR24 bitfields. + state->u.f1.fld.dr24.d24 = cm_object_get_child_by_name(state->u.f1.reg.dr24, "D24"); + + // DR25 bitfields. + state->u.f1.fld.dr25.d25 = cm_object_get_child_by_name(state->u.f1.reg.dr25, "D25"); + + // DR26 bitfields. + state->u.f1.fld.dr26.d26 = cm_object_get_child_by_name(state->u.f1.reg.dr26, "D26"); + + // DR27 bitfields. + state->u.f1.fld.dr27.d27 = cm_object_get_child_by_name(state->u.f1.reg.dr27, "D27"); + + // DR28 bitfields. + state->u.f1.fld.dr28.d28 = cm_object_get_child_by_name(state->u.f1.reg.dr28, "D28"); + + // DR29 bitfields. + state->u.f1.fld.dr29.d29 = cm_object_get_child_by_name(state->u.f1.reg.dr29, "D29"); + + // DR30 bitfields. + state->u.f1.fld.dr30.d30 = cm_object_get_child_by_name(state->u.f1.reg.dr30, "D30"); + + // DR31 bitfields. + state->u.f1.fld.dr31.d31 = cm_object_get_child_by_name(state->u.f1.reg.dr31, "D31"); + + // DR32 bitfields. + state->u.f1.fld.dr32.d32 = cm_object_get_child_by_name(state->u.f1.reg.dr32, "D32"); + + // DR33 bitfields. + state->u.f1.fld.dr33.d33 = cm_object_get_child_by_name(state->u.f1.reg.dr33, "D33"); + + // DR34 bitfields. + state->u.f1.fld.dr34.d34 = cm_object_get_child_by_name(state->u.f1.reg.dr34, "D34"); + + // DR35 bitfields. + state->u.f1.fld.dr35.d35 = cm_object_get_child_by_name(state->u.f1.reg.dr35, "D35"); + + // DR36 bitfields. + state->u.f1.fld.dr36.d36 = cm_object_get_child_by_name(state->u.f1.reg.dr36, "D36"); + + // DR37 bitfields. + state->u.f1.fld.dr37.d37 = cm_object_get_child_by_name(state->u.f1.reg.dr37, "D37"); + + // DR38 bitfields. + state->u.f1.fld.dr38.d38 = cm_object_get_child_by_name(state->u.f1.reg.dr38, "D38"); + + // DR39 bitfields. + state->u.f1.fld.dr39.d39 = cm_object_get_child_by_name(state->u.f1.reg.dr39, "D39"); + + // DR40 bitfields. + state->u.f1.fld.dr40.d40 = cm_object_get_child_by_name(state->u.f1.reg.dr40, "D40"); + + // DR41 bitfields. + state->u.f1.fld.dr41.d41 = cm_object_get_child_by_name(state->u.f1.reg.dr41, "D41"); + + // DR42 bitfields. + state->u.f1.fld.dr42.d42 = cm_object_get_child_by_name(state->u.f1.reg.dr42, "D42"); + + // RTCCR bitfields. + state->u.f1.fld.rtccr.cal = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "CAL"); + state->u.f1.fld.rtccr.cco = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "CCO"); + state->u.f1.fld.rtccr.asoe = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "ASOE"); + state->u.f1.fld.rtccr.asos = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "ASOS"); + + // CR bitfields. + state->u.f1.fld.cr.tpe = cm_object_get_child_by_name(state->u.f1.reg.cr, "TPE"); + state->u.f1.fld.cr.tpal = cm_object_get_child_by_name(state->u.f1.reg.cr, "TPAL"); + + // CSR bitfields. + state->u.f1.fld.csr.cte = cm_object_get_child_by_name(state->u.f1.reg.csr, "CTE"); + state->u.f1.fld.csr.cti = cm_object_get_child_by_name(state->u.f1.reg.csr, "CTI"); + state->u.f1.fld.csr.tpie = cm_object_get_child_by_name(state->u.f1.reg.csr, "TPIE"); + state->u.f1.fld.csr.tef = cm_object_get_child_by_name(state->u.f1.reg.csr, "TEF"); + state->u.f1.fld.csr.tif = cm_object_get_child_by_name(state->u.f1.reg.csr, "TIF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_bkp_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_bkp_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_bkp_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_bkp_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_bkp_is_enabled(Object *obj) +{ + STM32BKPState *state = STM32_BKP_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_bkp_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32BKPState *state = STM32_BKP_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_bkp_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_BKP)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32BKPState *state = STM32_BKP_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "BKP"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_bkp_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_bkp_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_bkp_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_bkp_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_bkp_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/BKPEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_bkp_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_BKP); +} + +static void stm32_bkp_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_bkp_reset_callback; + dc->realize = stm32_bkp_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_bkp_is_enabled; +} + +static const TypeInfo stm32_bkp_type_info = { + .name = TYPE_STM32_BKP, + .parent = TYPE_STM32_BKP_PARENT, + .instance_init = stm32_bkp_instance_init_callback, + .instance_size = sizeof(STM32BKPState), + .class_init = stm32_bkp_class_init_callback, + .class_size = sizeof(STM32BKPClass) }; + +static void stm32_bkp_register_types(void) +{ + type_register_static(&stm32_bkp_type_info); +} + +type_init(stm32_bkp_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/bkp.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/bkp.h new file mode 100644 index 0000000000..045070f100 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/bkp.h @@ -0,0 +1,377 @@ +/* + * STM32 - BKP (Backup registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_BKP_H_ +#define STM32_BKP_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_BKP DEVICE_PATH_STM32 "BKP" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_BKP TYPE_STM32_PREFIX "bkp" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_BKP_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32BKPParentClass; +typedef PeripheralState STM32BKPParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_BKP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32BKPClass, (obj), TYPE_STM32_BKP) +#define STM32_BKP_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32BKPClass, (klass), TYPE_STM32_BKP) + +typedef struct { + // private: + STM32BKPParentClass parent_class; + // public: + + // None, so far. +} STM32BKPClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_BKP_STATE(obj) \ + OBJECT_CHECK(STM32BKPState, (obj), TYPE_STM32_BKP) + +typedef struct { + // private: + STM32BKPParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 BKP (Backup registers) registers. + struct { + Object *dr1; // 0x0 (Backup data register (BKP_DR)) + Object *dr2; // 0x4 (Backup data register (BKP_DR)) + Object *dr3; // 0x8 (Backup data register (BKP_DR)) + Object *dr4; // 0xC (Backup data register (BKP_DR)) + Object *dr5; // 0x10 (Backup data register (BKP_DR)) + Object *dr6; // 0x14 (Backup data register (BKP_DR)) + Object *dr7; // 0x18 (Backup data register (BKP_DR)) + Object *dr8; // 0x1C (Backup data register (BKP_DR)) + Object *dr9; // 0x20 (Backup data register (BKP_DR)) + Object *dr10; // 0x24 (Backup data register (BKP_DR)) + Object *dr11; // 0x3C (Backup data register (BKP_DR)) + Object *dr12; // 0x40 (Backup data register (BKP_DR)) + Object *dr13; // 0x44 (Backup data register (BKP_DR)) + Object *dr14; // 0x48 (Backup data register (BKP_DR)) + Object *dr15; // 0x4C (Backup data register (BKP_DR)) + Object *dr16; // 0x50 (Backup data register (BKP_DR)) + Object *dr17; // 0x54 (Backup data register (BKP_DR)) + Object *dr18; // 0x58 (Backup data register (BKP_DR)) + Object *dr19; // 0x5C (Backup data register (BKP_DR)) + Object *dr20; // 0x60 (Backup data register (BKP_DR)) + Object *dr21; // 0x64 (Backup data register (BKP_DR)) + Object *dr22; // 0x68 (Backup data register (BKP_DR)) + Object *dr23; // 0x6C (Backup data register (BKP_DR)) + Object *dr24; // 0x70 (Backup data register (BKP_DR)) + Object *dr25; // 0x74 (Backup data register (BKP_DR)) + Object *dr26; // 0x78 (Backup data register (BKP_DR)) + Object *dr27; // 0x7C (Backup data register (BKP_DR)) + Object *dr28; // 0x80 (Backup data register (BKP_DR)) + Object *dr29; // 0x84 (Backup data register (BKP_DR)) + Object *dr30; // 0x88 (Backup data register (BKP_DR)) + Object *dr31; // 0x8C (Backup data register (BKP_DR)) + Object *dr32; // 0x90 (Backup data register (BKP_DR)) + Object *dr33; // 0x94 (Backup data register (BKP_DR)) + Object *dr34; // 0x98 (Backup data register (BKP_DR)) + Object *dr35; // 0x9C (Backup data register (BKP_DR)) + Object *dr36; // 0xA0 (Backup data register (BKP_DR)) + Object *dr37; // 0xA4 (Backup data register (BKP_DR)) + Object *dr38; // 0xA8 (Backup data register (BKP_DR)) + Object *dr39; // 0xAC (Backup data register (BKP_DR)) + Object *dr40; // 0xB0 (Backup data register (BKP_DR)) + Object *dr41; // 0xB4 (Backup data register (BKP_DR)) + Object *dr42; // 0xB8 (Backup data register (BKP_DR)) + Object *rtccr; // 0x28 (RTC clock calibration register (BKP_RTCCR)) + Object *cr; // 0x2C (Backup control register (BKP_CR)) + Object *csr; // 0x30 (BKP_CSR control/status register (BKP_CSR)) + } reg; + + struct { + + // DR1 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d1; // [0:15] Backup data + } dr1; + + // DR2 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d2; // [0:15] Backup data + } dr2; + + // DR3 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d3; // [0:15] Backup data + } dr3; + + // DR4 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d4; // [0:15] Backup data + } dr4; + + // DR5 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d5; // [0:15] Backup data + } dr5; + + // DR6 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d6; // [0:15] Backup data + } dr6; + + // DR7 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d7; // [0:15] Backup data + } dr7; + + // DR8 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d8; // [0:15] Backup data + } dr8; + + // DR9 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d9; // [0:15] Backup data + } dr9; + + // DR10 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d10; // [0:15] Backup data + } dr10; + + // DR11 (Backup data register (BKP_DR)) bitfields. + struct { + Object *dr11; // [0:15] Backup data + } dr11; + + // DR12 (Backup data register (BKP_DR)) bitfields. + struct { + Object *dr12; // [0:15] Backup data + } dr12; + + // DR13 (Backup data register (BKP_DR)) bitfields. + struct { + Object *dr13; // [0:15] Backup data + } dr13; + + // DR14 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d14; // [0:15] Backup data + } dr14; + + // DR15 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d15; // [0:15] Backup data + } dr15; + + // DR16 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d16; // [0:15] Backup data + } dr16; + + // DR17 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d17; // [0:15] Backup data + } dr17; + + // DR18 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d18; // [0:15] Backup data + } dr18; + + // DR19 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d19; // [0:15] Backup data + } dr19; + + // DR20 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d20; // [0:15] Backup data + } dr20; + + // DR21 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d21; // [0:15] Backup data + } dr21; + + // DR22 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d22; // [0:15] Backup data + } dr22; + + // DR23 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d23; // [0:15] Backup data + } dr23; + + // DR24 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d24; // [0:15] Backup data + } dr24; + + // DR25 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d25; // [0:15] Backup data + } dr25; + + // DR26 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d26; // [0:15] Backup data + } dr26; + + // DR27 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d27; // [0:15] Backup data + } dr27; + + // DR28 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d28; // [0:15] Backup data + } dr28; + + // DR29 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d29; // [0:15] Backup data + } dr29; + + // DR30 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d30; // [0:15] Backup data + } dr30; + + // DR31 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d31; // [0:15] Backup data + } dr31; + + // DR32 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d32; // [0:15] Backup data + } dr32; + + // DR33 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d33; // [0:15] Backup data + } dr33; + + // DR34 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d34; // [0:15] Backup data + } dr34; + + // DR35 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d35; // [0:15] Backup data + } dr35; + + // DR36 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d36; // [0:15] Backup data + } dr36; + + // DR37 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d37; // [0:15] Backup data + } dr37; + + // DR38 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d38; // [0:15] Backup data + } dr38; + + // DR39 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d39; // [0:15] Backup data + } dr39; + + // DR40 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d40; // [0:15] Backup data + } dr40; + + // DR41 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d41; // [0:15] Backup data + } dr41; + + // DR42 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d42; // [0:15] Backup data + } dr42; + + // RTCCR (RTC clock calibration register (BKP_RTCCR)) bitfields. + struct { + Object *cal; // [0:6] Calibration value + Object *cco; // [7:7] Calibration Clock Output + Object *asoe; // [8:8] Alarm or second output enable + Object *asos; // [9:9] Alarm or second output selection + } rtccr; + + // CR (Backup control register (BKP_CR)) bitfields. + struct { + Object *tpe; // [0:0] Tamper pin enable + Object *tpal; // [1:1] Tamper pin active level + } cr; + + // CSR (BKP_CSR control/status register (BKP_CSR)) bitfields. + struct { + Object *cte; // [0:0] Clear Tamper event + Object *cti; // [1:1] Clear Tamper Interrupt + Object *tpie; // [2:2] Tamper Pin interrupt enable + Object *tef; // [8:8] Tamper Event Flag + Object *tif; // [9:9] Tamper Interrupt Flag + } csr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32BKPState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_BKP_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/can.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/can.c new file mode 100644 index 0000000000..41498423f0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/can.c @@ -0,0 +1,1523 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_can_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.can_mcr = cm_object_get_child_by_name(obj, "CAN_MCR"); + state->u.f1.reg.can_msr = cm_object_get_child_by_name(obj, "CAN_MSR"); + state->u.f1.reg.can_tsr = cm_object_get_child_by_name(obj, "CAN_TSR"); + state->u.f1.reg.can_rf0r = cm_object_get_child_by_name(obj, "CAN_RF0R"); + state->u.f1.reg.can_rf1r = cm_object_get_child_by_name(obj, "CAN_RF1R"); + state->u.f1.reg.can_ier = cm_object_get_child_by_name(obj, "CAN_IER"); + state->u.f1.reg.can_esr = cm_object_get_child_by_name(obj, "CAN_ESR"); + state->u.f1.reg.can_btr = cm_object_get_child_by_name(obj, "CAN_BTR"); + state->u.f1.reg.can_ti0r = cm_object_get_child_by_name(obj, "CAN_TI0R"); + state->u.f1.reg.can_tdt0r = cm_object_get_child_by_name(obj, "CAN_TDT0R"); + state->u.f1.reg.can_tdl0r = cm_object_get_child_by_name(obj, "CAN_TDL0R"); + state->u.f1.reg.can_tdh0r = cm_object_get_child_by_name(obj, "CAN_TDH0R"); + state->u.f1.reg.can_ti1r = cm_object_get_child_by_name(obj, "CAN_TI1R"); + state->u.f1.reg.can_tdt1r = cm_object_get_child_by_name(obj, "CAN_TDT1R"); + state->u.f1.reg.can_tdl1r = cm_object_get_child_by_name(obj, "CAN_TDL1R"); + state->u.f1.reg.can_tdh1r = cm_object_get_child_by_name(obj, "CAN_TDH1R"); + state->u.f1.reg.can_ti2r = cm_object_get_child_by_name(obj, "CAN_TI2R"); + state->u.f1.reg.can_tdt2r = cm_object_get_child_by_name(obj, "CAN_TDT2R"); + state->u.f1.reg.can_tdl2r = cm_object_get_child_by_name(obj, "CAN_TDL2R"); + state->u.f1.reg.can_tdh2r = cm_object_get_child_by_name(obj, "CAN_TDH2R"); + state->u.f1.reg.can_ri0r = cm_object_get_child_by_name(obj, "CAN_RI0R"); + state->u.f1.reg.can_rdt0r = cm_object_get_child_by_name(obj, "CAN_RDT0R"); + state->u.f1.reg.can_rdl0r = cm_object_get_child_by_name(obj, "CAN_RDL0R"); + state->u.f1.reg.can_rdh0r = cm_object_get_child_by_name(obj, "CAN_RDH0R"); + state->u.f1.reg.can_ri1r = cm_object_get_child_by_name(obj, "CAN_RI1R"); + state->u.f1.reg.can_rdt1r = cm_object_get_child_by_name(obj, "CAN_RDT1R"); + state->u.f1.reg.can_rdl1r = cm_object_get_child_by_name(obj, "CAN_RDL1R"); + state->u.f1.reg.can_rdh1r = cm_object_get_child_by_name(obj, "CAN_RDH1R"); + state->u.f1.reg.can_fmr = cm_object_get_child_by_name(obj, "CAN_FMR"); + state->u.f1.reg.can_fm1r = cm_object_get_child_by_name(obj, "CAN_FM1R"); + state->u.f1.reg.can_fs1r = cm_object_get_child_by_name(obj, "CAN_FS1R"); + state->u.f1.reg.can_ffa1r = cm_object_get_child_by_name(obj, "CAN_FFA1R"); + state->u.f1.reg.can_fa1r = cm_object_get_child_by_name(obj, "CAN_FA1R"); + state->u.f1.reg.f0r1 = cm_object_get_child_by_name(obj, "F0R1"); + state->u.f1.reg.f0r2 = cm_object_get_child_by_name(obj, "F0R2"); + state->u.f1.reg.f1r1 = cm_object_get_child_by_name(obj, "F1R1"); + state->u.f1.reg.f1r2 = cm_object_get_child_by_name(obj, "F1R2"); + state->u.f1.reg.f2r1 = cm_object_get_child_by_name(obj, "F2R1"); + state->u.f1.reg.f2r2 = cm_object_get_child_by_name(obj, "F2R2"); + state->u.f1.reg.f3r1 = cm_object_get_child_by_name(obj, "F3R1"); + state->u.f1.reg.f3r2 = cm_object_get_child_by_name(obj, "F3R2"); + state->u.f1.reg.f4r1 = cm_object_get_child_by_name(obj, "F4R1"); + state->u.f1.reg.f4r2 = cm_object_get_child_by_name(obj, "F4R2"); + state->u.f1.reg.f5r1 = cm_object_get_child_by_name(obj, "F5R1"); + state->u.f1.reg.f5r2 = cm_object_get_child_by_name(obj, "F5R2"); + state->u.f1.reg.f6r1 = cm_object_get_child_by_name(obj, "F6R1"); + state->u.f1.reg.f6r2 = cm_object_get_child_by_name(obj, "F6R2"); + state->u.f1.reg.f7r1 = cm_object_get_child_by_name(obj, "F7R1"); + state->u.f1.reg.f7r2 = cm_object_get_child_by_name(obj, "F7R2"); + state->u.f1.reg.f8r1 = cm_object_get_child_by_name(obj, "F8R1"); + state->u.f1.reg.f8r2 = cm_object_get_child_by_name(obj, "F8R2"); + state->u.f1.reg.f9r1 = cm_object_get_child_by_name(obj, "F9R1"); + state->u.f1.reg.f9r2 = cm_object_get_child_by_name(obj, "F9R2"); + state->u.f1.reg.f10r1 = cm_object_get_child_by_name(obj, "F10R1"); + state->u.f1.reg.f10r2 = cm_object_get_child_by_name(obj, "F10R2"); + state->u.f1.reg.f11r1 = cm_object_get_child_by_name(obj, "F11R1"); + state->u.f1.reg.f11r2 = cm_object_get_child_by_name(obj, "F11R2"); + state->u.f1.reg.f12r1 = cm_object_get_child_by_name(obj, "F12R1"); + state->u.f1.reg.f12r2 = cm_object_get_child_by_name(obj, "F12R2"); + state->u.f1.reg.f13r1 = cm_object_get_child_by_name(obj, "F13R1"); + state->u.f1.reg.f13r2 = cm_object_get_child_by_name(obj, "F13R2"); + + + // CAN_MCR bitfields. + state->u.f1.fld.can_mcr.inrq = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "INRQ"); + state->u.f1.fld.can_mcr.sleep = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "SLEEP"); + state->u.f1.fld.can_mcr.txfp = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "TXFP"); + state->u.f1.fld.can_mcr.rflm = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "RFLM"); + state->u.f1.fld.can_mcr.nart = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "NART"); + state->u.f1.fld.can_mcr.awum = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "AWUM"); + state->u.f1.fld.can_mcr.abom = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "ABOM"); + state->u.f1.fld.can_mcr.ttcm = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "TTCM"); + state->u.f1.fld.can_mcr.reset = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "RESET"); + state->u.f1.fld.can_mcr.dbf = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "DBF"); + + // CAN_MSR bitfields. + state->u.f1.fld.can_msr.inak = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "INAK"); + state->u.f1.fld.can_msr.slak = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "SLAK"); + state->u.f1.fld.can_msr.erri = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "ERRI"); + state->u.f1.fld.can_msr.wkui = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "WKUI"); + state->u.f1.fld.can_msr.slaki = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "SLAKI"); + state->u.f1.fld.can_msr.txm = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "TXM"); + state->u.f1.fld.can_msr.rxm = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "RXM"); + state->u.f1.fld.can_msr.samp = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "SAMP"); + state->u.f1.fld.can_msr.rx = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "RX"); + + // CAN_TSR bitfields. + state->u.f1.fld.can_tsr.rqcp0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "RQCP0"); + state->u.f1.fld.can_tsr.txok0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TXOK0"); + state->u.f1.fld.can_tsr.alst0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ALST0"); + state->u.f1.fld.can_tsr.terr0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TERR0"); + state->u.f1.fld.can_tsr.abrq0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ABRQ0"); + state->u.f1.fld.can_tsr.rqcp1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "RQCP1"); + state->u.f1.fld.can_tsr.txok1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TXOK1"); + state->u.f1.fld.can_tsr.alst1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ALST1"); + state->u.f1.fld.can_tsr.terr1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TERR1"); + state->u.f1.fld.can_tsr.abrq1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ABRQ1"); + state->u.f1.fld.can_tsr.rqcp2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "RQCP2"); + state->u.f1.fld.can_tsr.txok2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TXOK2"); + state->u.f1.fld.can_tsr.alst2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ALST2"); + state->u.f1.fld.can_tsr.terr2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TERR2"); + state->u.f1.fld.can_tsr.abrq2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ABRQ2"); + state->u.f1.fld.can_tsr.code = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "CODE"); + state->u.f1.fld.can_tsr.tme0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TME0"); + state->u.f1.fld.can_tsr.tme1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TME1"); + state->u.f1.fld.can_tsr.tme2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TME2"); + state->u.f1.fld.can_tsr.low0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "LOW0"); + state->u.f1.fld.can_tsr.low1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "LOW1"); + state->u.f1.fld.can_tsr.low2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "LOW2"); + + // CAN_RF0R bitfields. + state->u.f1.fld.can_rf0r.fmp0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "FMP0"); + state->u.f1.fld.can_rf0r.full0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "FULL0"); + state->u.f1.fld.can_rf0r.fovr0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "FOVR0"); + state->u.f1.fld.can_rf0r.rfom0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "RFOM0"); + + // CAN_RF1R bitfields. + state->u.f1.fld.can_rf1r.fmp1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "FMP1"); + state->u.f1.fld.can_rf1r.full1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "FULL1"); + state->u.f1.fld.can_rf1r.fovr1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "FOVR1"); + state->u.f1.fld.can_rf1r.rfom1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "RFOM1"); + + // CAN_IER bitfields. + state->u.f1.fld.can_ier.tmeie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "TMEIE"); + state->u.f1.fld.can_ier.fmpie0 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FMPIE0"); + state->u.f1.fld.can_ier.ffie0 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FFIE0"); + state->u.f1.fld.can_ier.fovie0 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FOVIE0"); + state->u.f1.fld.can_ier.fmpie1 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FMPIE1"); + state->u.f1.fld.can_ier.ffie1 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FFIE1"); + state->u.f1.fld.can_ier.fovie1 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FOVIE1"); + state->u.f1.fld.can_ier.ewgie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "EWGIE"); + state->u.f1.fld.can_ier.epvie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "EPVIE"); + state->u.f1.fld.can_ier.bofie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "BOFIE"); + state->u.f1.fld.can_ier.lecie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "LECIE"); + state->u.f1.fld.can_ier.errie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "ERRIE"); + state->u.f1.fld.can_ier.wkuie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "WKUIE"); + state->u.f1.fld.can_ier.slkie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "SLKIE"); + + // CAN_ESR bitfields. + state->u.f1.fld.can_esr.ewgf = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "EWGF"); + state->u.f1.fld.can_esr.epvf = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "EPVF"); + state->u.f1.fld.can_esr.boff = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "BOFF"); + state->u.f1.fld.can_esr.lec = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "LEC"); + state->u.f1.fld.can_esr.tec = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "TEC"); + state->u.f1.fld.can_esr.rec = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "REC"); + + // CAN_BTR bitfields. + state->u.f1.fld.can_btr.brp = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "BRP"); + state->u.f1.fld.can_btr.ts1 = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "TS1"); + state->u.f1.fld.can_btr.ts2 = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "TS2"); + state->u.f1.fld.can_btr.sjw = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "SJW"); + state->u.f1.fld.can_btr.lbkm = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "LBKM"); + state->u.f1.fld.can_btr.silm = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "SILM"); + + // CAN_TI0R bitfields. + state->u.f1.fld.can_ti0r.txrq = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "TXRQ"); + state->u.f1.fld.can_ti0r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "RTR"); + state->u.f1.fld.can_ti0r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "IDE"); + state->u.f1.fld.can_ti0r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "EXID"); + state->u.f1.fld.can_ti0r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "STID"); + + // CAN_TDT0R bitfields. + state->u.f1.fld.can_tdt0r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_tdt0r, "DLC"); + state->u.f1.fld.can_tdt0r.tgt = cm_object_get_child_by_name(state->u.f1.reg.can_tdt0r, "TGT"); + state->u.f1.fld.can_tdt0r.time = cm_object_get_child_by_name(state->u.f1.reg.can_tdt0r, "TIME"); + + // CAN_TDL0R bitfields. + state->u.f1.fld.can_tdl0r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA0"); + state->u.f1.fld.can_tdl0r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA1"); + state->u.f1.fld.can_tdl0r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA2"); + state->u.f1.fld.can_tdl0r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA3"); + + // CAN_TDH0R bitfields. + state->u.f1.fld.can_tdh0r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA4"); + state->u.f1.fld.can_tdh0r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA5"); + state->u.f1.fld.can_tdh0r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA6"); + state->u.f1.fld.can_tdh0r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA7"); + + // CAN_TI1R bitfields. + state->u.f1.fld.can_ti1r.txrq = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "TXRQ"); + state->u.f1.fld.can_ti1r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "RTR"); + state->u.f1.fld.can_ti1r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "IDE"); + state->u.f1.fld.can_ti1r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "EXID"); + state->u.f1.fld.can_ti1r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "STID"); + + // CAN_TDT1R bitfields. + state->u.f1.fld.can_tdt1r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_tdt1r, "DLC"); + state->u.f1.fld.can_tdt1r.tgt = cm_object_get_child_by_name(state->u.f1.reg.can_tdt1r, "TGT"); + state->u.f1.fld.can_tdt1r.time = cm_object_get_child_by_name(state->u.f1.reg.can_tdt1r, "TIME"); + + // CAN_TDL1R bitfields. + state->u.f1.fld.can_tdl1r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA0"); + state->u.f1.fld.can_tdl1r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA1"); + state->u.f1.fld.can_tdl1r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA2"); + state->u.f1.fld.can_tdl1r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA3"); + + // CAN_TDH1R bitfields. + state->u.f1.fld.can_tdh1r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA4"); + state->u.f1.fld.can_tdh1r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA5"); + state->u.f1.fld.can_tdh1r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA6"); + state->u.f1.fld.can_tdh1r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA7"); + + // CAN_TI2R bitfields. + state->u.f1.fld.can_ti2r.txrq = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "TXRQ"); + state->u.f1.fld.can_ti2r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "RTR"); + state->u.f1.fld.can_ti2r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "IDE"); + state->u.f1.fld.can_ti2r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "EXID"); + state->u.f1.fld.can_ti2r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "STID"); + + // CAN_TDT2R bitfields. + state->u.f1.fld.can_tdt2r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_tdt2r, "DLC"); + state->u.f1.fld.can_tdt2r.tgt = cm_object_get_child_by_name(state->u.f1.reg.can_tdt2r, "TGT"); + state->u.f1.fld.can_tdt2r.time = cm_object_get_child_by_name(state->u.f1.reg.can_tdt2r, "TIME"); + + // CAN_TDL2R bitfields. + state->u.f1.fld.can_tdl2r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA0"); + state->u.f1.fld.can_tdl2r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA1"); + state->u.f1.fld.can_tdl2r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA2"); + state->u.f1.fld.can_tdl2r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA3"); + + // CAN_TDH2R bitfields. + state->u.f1.fld.can_tdh2r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA4"); + state->u.f1.fld.can_tdh2r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA5"); + state->u.f1.fld.can_tdh2r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA6"); + state->u.f1.fld.can_tdh2r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA7"); + + // CAN_RI0R bitfields. + state->u.f1.fld.can_ri0r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "RTR"); + state->u.f1.fld.can_ri0r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "IDE"); + state->u.f1.fld.can_ri0r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "EXID"); + state->u.f1.fld.can_ri0r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "STID"); + + // CAN_RDT0R bitfields. + state->u.f1.fld.can_rdt0r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_rdt0r, "DLC"); + state->u.f1.fld.can_rdt0r.fmi = cm_object_get_child_by_name(state->u.f1.reg.can_rdt0r, "FMI"); + state->u.f1.fld.can_rdt0r.time = cm_object_get_child_by_name(state->u.f1.reg.can_rdt0r, "TIME"); + + // CAN_RDL0R bitfields. + state->u.f1.fld.can_rdl0r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA0"); + state->u.f1.fld.can_rdl0r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA1"); + state->u.f1.fld.can_rdl0r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA2"); + state->u.f1.fld.can_rdl0r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA3"); + + // CAN_RDH0R bitfields. + state->u.f1.fld.can_rdh0r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA4"); + state->u.f1.fld.can_rdh0r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA5"); + state->u.f1.fld.can_rdh0r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA6"); + state->u.f1.fld.can_rdh0r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA7"); + + // CAN_RI1R bitfields. + state->u.f1.fld.can_ri1r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "RTR"); + state->u.f1.fld.can_ri1r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "IDE"); + state->u.f1.fld.can_ri1r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "EXID"); + state->u.f1.fld.can_ri1r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "STID"); + + // CAN_RDT1R bitfields. + state->u.f1.fld.can_rdt1r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_rdt1r, "DLC"); + state->u.f1.fld.can_rdt1r.fmi = cm_object_get_child_by_name(state->u.f1.reg.can_rdt1r, "FMI"); + state->u.f1.fld.can_rdt1r.time = cm_object_get_child_by_name(state->u.f1.reg.can_rdt1r, "TIME"); + + // CAN_RDL1R bitfields. + state->u.f1.fld.can_rdl1r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA0"); + state->u.f1.fld.can_rdl1r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA1"); + state->u.f1.fld.can_rdl1r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA2"); + state->u.f1.fld.can_rdl1r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA3"); + + // CAN_RDH1R bitfields. + state->u.f1.fld.can_rdh1r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA4"); + state->u.f1.fld.can_rdh1r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA5"); + state->u.f1.fld.can_rdh1r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA6"); + state->u.f1.fld.can_rdh1r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA7"); + + // CAN_FMR bitfields. + state->u.f1.fld.can_fmr.finit = cm_object_get_child_by_name(state->u.f1.reg.can_fmr, "FINIT"); + + // CAN_FM1R bitfields. + state->u.f1.fld.can_fm1r.fbm0 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM0"); + state->u.f1.fld.can_fm1r.fbm1 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM1"); + state->u.f1.fld.can_fm1r.fbm2 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM2"); + state->u.f1.fld.can_fm1r.fbm3 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM3"); + state->u.f1.fld.can_fm1r.fbm4 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM4"); + state->u.f1.fld.can_fm1r.fbm5 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM5"); + state->u.f1.fld.can_fm1r.fbm6 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM6"); + state->u.f1.fld.can_fm1r.fbm7 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM7"); + state->u.f1.fld.can_fm1r.fbm8 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM8"); + state->u.f1.fld.can_fm1r.fbm9 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM9"); + state->u.f1.fld.can_fm1r.fbm10 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM10"); + state->u.f1.fld.can_fm1r.fbm11 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM11"); + state->u.f1.fld.can_fm1r.fbm12 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM12"); + state->u.f1.fld.can_fm1r.fbm13 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM13"); + + // CAN_FS1R bitfields. + state->u.f1.fld.can_fs1r.fsc0 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC0"); + state->u.f1.fld.can_fs1r.fsc1 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC1"); + state->u.f1.fld.can_fs1r.fsc2 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC2"); + state->u.f1.fld.can_fs1r.fsc3 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC3"); + state->u.f1.fld.can_fs1r.fsc4 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC4"); + state->u.f1.fld.can_fs1r.fsc5 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC5"); + state->u.f1.fld.can_fs1r.fsc6 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC6"); + state->u.f1.fld.can_fs1r.fsc7 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC7"); + state->u.f1.fld.can_fs1r.fsc8 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC8"); + state->u.f1.fld.can_fs1r.fsc9 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC9"); + state->u.f1.fld.can_fs1r.fsc10 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC10"); + state->u.f1.fld.can_fs1r.fsc11 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC11"); + state->u.f1.fld.can_fs1r.fsc12 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC12"); + state->u.f1.fld.can_fs1r.fsc13 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC13"); + + // CAN_FFA1R bitfields. + state->u.f1.fld.can_ffa1r.ffa0 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA0"); + state->u.f1.fld.can_ffa1r.ffa1 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA1"); + state->u.f1.fld.can_ffa1r.ffa2 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA2"); + state->u.f1.fld.can_ffa1r.ffa3 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA3"); + state->u.f1.fld.can_ffa1r.ffa4 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA4"); + state->u.f1.fld.can_ffa1r.ffa5 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA5"); + state->u.f1.fld.can_ffa1r.ffa6 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA6"); + state->u.f1.fld.can_ffa1r.ffa7 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA7"); + state->u.f1.fld.can_ffa1r.ffa8 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA8"); + state->u.f1.fld.can_ffa1r.ffa9 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA9"); + state->u.f1.fld.can_ffa1r.ffa10 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA10"); + state->u.f1.fld.can_ffa1r.ffa11 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA11"); + state->u.f1.fld.can_ffa1r.ffa12 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA12"); + state->u.f1.fld.can_ffa1r.ffa13 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA13"); + + // CAN_FA1R bitfields. + state->u.f1.fld.can_fa1r.fact0 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT0"); + state->u.f1.fld.can_fa1r.fact1 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT1"); + state->u.f1.fld.can_fa1r.fact2 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT2"); + state->u.f1.fld.can_fa1r.fact3 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT3"); + state->u.f1.fld.can_fa1r.fact4 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT4"); + state->u.f1.fld.can_fa1r.fact5 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT5"); + state->u.f1.fld.can_fa1r.fact6 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT6"); + state->u.f1.fld.can_fa1r.fact7 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT7"); + state->u.f1.fld.can_fa1r.fact8 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT8"); + state->u.f1.fld.can_fa1r.fact9 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT9"); + state->u.f1.fld.can_fa1r.fact10 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT10"); + state->u.f1.fld.can_fa1r.fact11 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT11"); + state->u.f1.fld.can_fa1r.fact12 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT12"); + state->u.f1.fld.can_fa1r.fact13 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT13"); + + // F0R1 bitfields. + state->u.f1.fld.f0r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB0"); + state->u.f1.fld.f0r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB1"); + state->u.f1.fld.f0r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB2"); + state->u.f1.fld.f0r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB3"); + state->u.f1.fld.f0r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB4"); + state->u.f1.fld.f0r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB5"); + state->u.f1.fld.f0r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB6"); + state->u.f1.fld.f0r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB7"); + state->u.f1.fld.f0r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB8"); + state->u.f1.fld.f0r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB9"); + state->u.f1.fld.f0r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB10"); + state->u.f1.fld.f0r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB11"); + state->u.f1.fld.f0r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB12"); + state->u.f1.fld.f0r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB13"); + state->u.f1.fld.f0r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB14"); + state->u.f1.fld.f0r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB15"); + state->u.f1.fld.f0r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB16"); + state->u.f1.fld.f0r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB17"); + state->u.f1.fld.f0r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB18"); + state->u.f1.fld.f0r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB19"); + state->u.f1.fld.f0r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB20"); + state->u.f1.fld.f0r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB21"); + state->u.f1.fld.f0r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB22"); + state->u.f1.fld.f0r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB23"); + state->u.f1.fld.f0r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB24"); + state->u.f1.fld.f0r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB25"); + state->u.f1.fld.f0r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB26"); + state->u.f1.fld.f0r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB27"); + state->u.f1.fld.f0r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB28"); + state->u.f1.fld.f0r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB29"); + state->u.f1.fld.f0r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB30"); + state->u.f1.fld.f0r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB31"); + + // F0R2 bitfields. + state->u.f1.fld.f0r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB0"); + state->u.f1.fld.f0r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB1"); + state->u.f1.fld.f0r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB2"); + state->u.f1.fld.f0r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB3"); + state->u.f1.fld.f0r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB4"); + state->u.f1.fld.f0r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB5"); + state->u.f1.fld.f0r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB6"); + state->u.f1.fld.f0r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB7"); + state->u.f1.fld.f0r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB8"); + state->u.f1.fld.f0r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB9"); + state->u.f1.fld.f0r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB10"); + state->u.f1.fld.f0r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB11"); + state->u.f1.fld.f0r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB12"); + state->u.f1.fld.f0r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB13"); + state->u.f1.fld.f0r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB14"); + state->u.f1.fld.f0r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB15"); + state->u.f1.fld.f0r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB16"); + state->u.f1.fld.f0r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB17"); + state->u.f1.fld.f0r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB18"); + state->u.f1.fld.f0r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB19"); + state->u.f1.fld.f0r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB20"); + state->u.f1.fld.f0r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB21"); + state->u.f1.fld.f0r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB22"); + state->u.f1.fld.f0r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB23"); + state->u.f1.fld.f0r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB24"); + state->u.f1.fld.f0r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB25"); + state->u.f1.fld.f0r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB26"); + state->u.f1.fld.f0r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB27"); + state->u.f1.fld.f0r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB28"); + state->u.f1.fld.f0r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB29"); + state->u.f1.fld.f0r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB30"); + state->u.f1.fld.f0r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB31"); + + // F1R1 bitfields. + state->u.f1.fld.f1r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB0"); + state->u.f1.fld.f1r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB1"); + state->u.f1.fld.f1r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB2"); + state->u.f1.fld.f1r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB3"); + state->u.f1.fld.f1r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB4"); + state->u.f1.fld.f1r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB5"); + state->u.f1.fld.f1r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB6"); + state->u.f1.fld.f1r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB7"); + state->u.f1.fld.f1r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB8"); + state->u.f1.fld.f1r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB9"); + state->u.f1.fld.f1r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB10"); + state->u.f1.fld.f1r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB11"); + state->u.f1.fld.f1r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB12"); + state->u.f1.fld.f1r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB13"); + state->u.f1.fld.f1r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB14"); + state->u.f1.fld.f1r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB15"); + state->u.f1.fld.f1r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB16"); + state->u.f1.fld.f1r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB17"); + state->u.f1.fld.f1r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB18"); + state->u.f1.fld.f1r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB19"); + state->u.f1.fld.f1r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB20"); + state->u.f1.fld.f1r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB21"); + state->u.f1.fld.f1r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB22"); + state->u.f1.fld.f1r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB23"); + state->u.f1.fld.f1r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB24"); + state->u.f1.fld.f1r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB25"); + state->u.f1.fld.f1r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB26"); + state->u.f1.fld.f1r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB27"); + state->u.f1.fld.f1r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB28"); + state->u.f1.fld.f1r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB29"); + state->u.f1.fld.f1r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB30"); + state->u.f1.fld.f1r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB31"); + + // F1R2 bitfields. + state->u.f1.fld.f1r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB0"); + state->u.f1.fld.f1r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB1"); + state->u.f1.fld.f1r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB2"); + state->u.f1.fld.f1r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB3"); + state->u.f1.fld.f1r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB4"); + state->u.f1.fld.f1r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB5"); + state->u.f1.fld.f1r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB6"); + state->u.f1.fld.f1r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB7"); + state->u.f1.fld.f1r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB8"); + state->u.f1.fld.f1r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB9"); + state->u.f1.fld.f1r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB10"); + state->u.f1.fld.f1r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB11"); + state->u.f1.fld.f1r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB12"); + state->u.f1.fld.f1r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB13"); + state->u.f1.fld.f1r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB14"); + state->u.f1.fld.f1r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB15"); + state->u.f1.fld.f1r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB16"); + state->u.f1.fld.f1r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB17"); + state->u.f1.fld.f1r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB18"); + state->u.f1.fld.f1r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB19"); + state->u.f1.fld.f1r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB20"); + state->u.f1.fld.f1r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB21"); + state->u.f1.fld.f1r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB22"); + state->u.f1.fld.f1r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB23"); + state->u.f1.fld.f1r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB24"); + state->u.f1.fld.f1r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB25"); + state->u.f1.fld.f1r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB26"); + state->u.f1.fld.f1r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB27"); + state->u.f1.fld.f1r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB28"); + state->u.f1.fld.f1r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB29"); + state->u.f1.fld.f1r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB30"); + state->u.f1.fld.f1r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB31"); + + // F2R1 bitfields. + state->u.f1.fld.f2r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB0"); + state->u.f1.fld.f2r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB1"); + state->u.f1.fld.f2r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB2"); + state->u.f1.fld.f2r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB3"); + state->u.f1.fld.f2r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB4"); + state->u.f1.fld.f2r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB5"); + state->u.f1.fld.f2r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB6"); + state->u.f1.fld.f2r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB7"); + state->u.f1.fld.f2r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB8"); + state->u.f1.fld.f2r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB9"); + state->u.f1.fld.f2r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB10"); + state->u.f1.fld.f2r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB11"); + state->u.f1.fld.f2r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB12"); + state->u.f1.fld.f2r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB13"); + state->u.f1.fld.f2r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB14"); + state->u.f1.fld.f2r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB15"); + state->u.f1.fld.f2r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB16"); + state->u.f1.fld.f2r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB17"); + state->u.f1.fld.f2r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB18"); + state->u.f1.fld.f2r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB19"); + state->u.f1.fld.f2r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB20"); + state->u.f1.fld.f2r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB21"); + state->u.f1.fld.f2r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB22"); + state->u.f1.fld.f2r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB23"); + state->u.f1.fld.f2r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB24"); + state->u.f1.fld.f2r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB25"); + state->u.f1.fld.f2r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB26"); + state->u.f1.fld.f2r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB27"); + state->u.f1.fld.f2r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB28"); + state->u.f1.fld.f2r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB29"); + state->u.f1.fld.f2r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB30"); + state->u.f1.fld.f2r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB31"); + + // F2R2 bitfields. + state->u.f1.fld.f2r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB0"); + state->u.f1.fld.f2r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB1"); + state->u.f1.fld.f2r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB2"); + state->u.f1.fld.f2r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB3"); + state->u.f1.fld.f2r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB4"); + state->u.f1.fld.f2r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB5"); + state->u.f1.fld.f2r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB6"); + state->u.f1.fld.f2r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB7"); + state->u.f1.fld.f2r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB8"); + state->u.f1.fld.f2r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB9"); + state->u.f1.fld.f2r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB10"); + state->u.f1.fld.f2r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB11"); + state->u.f1.fld.f2r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB12"); + state->u.f1.fld.f2r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB13"); + state->u.f1.fld.f2r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB14"); + state->u.f1.fld.f2r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB15"); + state->u.f1.fld.f2r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB16"); + state->u.f1.fld.f2r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB17"); + state->u.f1.fld.f2r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB18"); + state->u.f1.fld.f2r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB19"); + state->u.f1.fld.f2r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB20"); + state->u.f1.fld.f2r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB21"); + state->u.f1.fld.f2r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB22"); + state->u.f1.fld.f2r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB23"); + state->u.f1.fld.f2r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB24"); + state->u.f1.fld.f2r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB25"); + state->u.f1.fld.f2r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB26"); + state->u.f1.fld.f2r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB27"); + state->u.f1.fld.f2r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB28"); + state->u.f1.fld.f2r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB29"); + state->u.f1.fld.f2r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB30"); + state->u.f1.fld.f2r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB31"); + + // F3R1 bitfields. + state->u.f1.fld.f3r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB0"); + state->u.f1.fld.f3r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB1"); + state->u.f1.fld.f3r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB2"); + state->u.f1.fld.f3r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB3"); + state->u.f1.fld.f3r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB4"); + state->u.f1.fld.f3r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB5"); + state->u.f1.fld.f3r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB6"); + state->u.f1.fld.f3r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB7"); + state->u.f1.fld.f3r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB8"); + state->u.f1.fld.f3r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB9"); + state->u.f1.fld.f3r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB10"); + state->u.f1.fld.f3r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB11"); + state->u.f1.fld.f3r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB12"); + state->u.f1.fld.f3r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB13"); + state->u.f1.fld.f3r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB14"); + state->u.f1.fld.f3r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB15"); + state->u.f1.fld.f3r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB16"); + state->u.f1.fld.f3r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB17"); + state->u.f1.fld.f3r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB18"); + state->u.f1.fld.f3r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB19"); + state->u.f1.fld.f3r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB20"); + state->u.f1.fld.f3r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB21"); + state->u.f1.fld.f3r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB22"); + state->u.f1.fld.f3r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB23"); + state->u.f1.fld.f3r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB24"); + state->u.f1.fld.f3r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB25"); + state->u.f1.fld.f3r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB26"); + state->u.f1.fld.f3r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB27"); + state->u.f1.fld.f3r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB28"); + state->u.f1.fld.f3r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB29"); + state->u.f1.fld.f3r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB30"); + state->u.f1.fld.f3r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB31"); + + // F3R2 bitfields. + state->u.f1.fld.f3r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB0"); + state->u.f1.fld.f3r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB1"); + state->u.f1.fld.f3r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB2"); + state->u.f1.fld.f3r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB3"); + state->u.f1.fld.f3r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB4"); + state->u.f1.fld.f3r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB5"); + state->u.f1.fld.f3r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB6"); + state->u.f1.fld.f3r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB7"); + state->u.f1.fld.f3r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB8"); + state->u.f1.fld.f3r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB9"); + state->u.f1.fld.f3r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB10"); + state->u.f1.fld.f3r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB11"); + state->u.f1.fld.f3r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB12"); + state->u.f1.fld.f3r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB13"); + state->u.f1.fld.f3r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB14"); + state->u.f1.fld.f3r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB15"); + state->u.f1.fld.f3r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB16"); + state->u.f1.fld.f3r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB17"); + state->u.f1.fld.f3r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB18"); + state->u.f1.fld.f3r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB19"); + state->u.f1.fld.f3r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB20"); + state->u.f1.fld.f3r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB21"); + state->u.f1.fld.f3r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB22"); + state->u.f1.fld.f3r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB23"); + state->u.f1.fld.f3r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB24"); + state->u.f1.fld.f3r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB25"); + state->u.f1.fld.f3r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB26"); + state->u.f1.fld.f3r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB27"); + state->u.f1.fld.f3r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB28"); + state->u.f1.fld.f3r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB29"); + state->u.f1.fld.f3r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB30"); + state->u.f1.fld.f3r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB31"); + + // F4R1 bitfields. + state->u.f1.fld.f4r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB0"); + state->u.f1.fld.f4r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB1"); + state->u.f1.fld.f4r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB2"); + state->u.f1.fld.f4r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB3"); + state->u.f1.fld.f4r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB4"); + state->u.f1.fld.f4r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB5"); + state->u.f1.fld.f4r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB6"); + state->u.f1.fld.f4r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB7"); + state->u.f1.fld.f4r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB8"); + state->u.f1.fld.f4r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB9"); + state->u.f1.fld.f4r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB10"); + state->u.f1.fld.f4r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB11"); + state->u.f1.fld.f4r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB12"); + state->u.f1.fld.f4r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB13"); + state->u.f1.fld.f4r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB14"); + state->u.f1.fld.f4r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB15"); + state->u.f1.fld.f4r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB16"); + state->u.f1.fld.f4r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB17"); + state->u.f1.fld.f4r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB18"); + state->u.f1.fld.f4r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB19"); + state->u.f1.fld.f4r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB20"); + state->u.f1.fld.f4r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB21"); + state->u.f1.fld.f4r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB22"); + state->u.f1.fld.f4r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB23"); + state->u.f1.fld.f4r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB24"); + state->u.f1.fld.f4r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB25"); + state->u.f1.fld.f4r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB26"); + state->u.f1.fld.f4r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB27"); + state->u.f1.fld.f4r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB28"); + state->u.f1.fld.f4r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB29"); + state->u.f1.fld.f4r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB30"); + state->u.f1.fld.f4r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB31"); + + // F4R2 bitfields. + state->u.f1.fld.f4r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB0"); + state->u.f1.fld.f4r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB1"); + state->u.f1.fld.f4r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB2"); + state->u.f1.fld.f4r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB3"); + state->u.f1.fld.f4r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB4"); + state->u.f1.fld.f4r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB5"); + state->u.f1.fld.f4r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB6"); + state->u.f1.fld.f4r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB7"); + state->u.f1.fld.f4r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB8"); + state->u.f1.fld.f4r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB9"); + state->u.f1.fld.f4r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB10"); + state->u.f1.fld.f4r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB11"); + state->u.f1.fld.f4r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB12"); + state->u.f1.fld.f4r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB13"); + state->u.f1.fld.f4r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB14"); + state->u.f1.fld.f4r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB15"); + state->u.f1.fld.f4r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB16"); + state->u.f1.fld.f4r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB17"); + state->u.f1.fld.f4r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB18"); + state->u.f1.fld.f4r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB19"); + state->u.f1.fld.f4r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB20"); + state->u.f1.fld.f4r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB21"); + state->u.f1.fld.f4r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB22"); + state->u.f1.fld.f4r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB23"); + state->u.f1.fld.f4r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB24"); + state->u.f1.fld.f4r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB25"); + state->u.f1.fld.f4r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB26"); + state->u.f1.fld.f4r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB27"); + state->u.f1.fld.f4r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB28"); + state->u.f1.fld.f4r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB29"); + state->u.f1.fld.f4r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB30"); + state->u.f1.fld.f4r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB31"); + + // F5R1 bitfields. + state->u.f1.fld.f5r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB0"); + state->u.f1.fld.f5r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB1"); + state->u.f1.fld.f5r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB2"); + state->u.f1.fld.f5r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB3"); + state->u.f1.fld.f5r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB4"); + state->u.f1.fld.f5r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB5"); + state->u.f1.fld.f5r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB6"); + state->u.f1.fld.f5r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB7"); + state->u.f1.fld.f5r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB8"); + state->u.f1.fld.f5r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB9"); + state->u.f1.fld.f5r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB10"); + state->u.f1.fld.f5r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB11"); + state->u.f1.fld.f5r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB12"); + state->u.f1.fld.f5r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB13"); + state->u.f1.fld.f5r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB14"); + state->u.f1.fld.f5r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB15"); + state->u.f1.fld.f5r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB16"); + state->u.f1.fld.f5r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB17"); + state->u.f1.fld.f5r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB18"); + state->u.f1.fld.f5r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB19"); + state->u.f1.fld.f5r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB20"); + state->u.f1.fld.f5r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB21"); + state->u.f1.fld.f5r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB22"); + state->u.f1.fld.f5r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB23"); + state->u.f1.fld.f5r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB24"); + state->u.f1.fld.f5r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB25"); + state->u.f1.fld.f5r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB26"); + state->u.f1.fld.f5r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB27"); + state->u.f1.fld.f5r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB28"); + state->u.f1.fld.f5r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB29"); + state->u.f1.fld.f5r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB30"); + state->u.f1.fld.f5r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB31"); + + // F5R2 bitfields. + state->u.f1.fld.f5r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB0"); + state->u.f1.fld.f5r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB1"); + state->u.f1.fld.f5r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB2"); + state->u.f1.fld.f5r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB3"); + state->u.f1.fld.f5r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB4"); + state->u.f1.fld.f5r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB5"); + state->u.f1.fld.f5r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB6"); + state->u.f1.fld.f5r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB7"); + state->u.f1.fld.f5r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB8"); + state->u.f1.fld.f5r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB9"); + state->u.f1.fld.f5r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB10"); + state->u.f1.fld.f5r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB11"); + state->u.f1.fld.f5r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB12"); + state->u.f1.fld.f5r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB13"); + state->u.f1.fld.f5r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB14"); + state->u.f1.fld.f5r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB15"); + state->u.f1.fld.f5r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB16"); + state->u.f1.fld.f5r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB17"); + state->u.f1.fld.f5r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB18"); + state->u.f1.fld.f5r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB19"); + state->u.f1.fld.f5r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB20"); + state->u.f1.fld.f5r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB21"); + state->u.f1.fld.f5r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB22"); + state->u.f1.fld.f5r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB23"); + state->u.f1.fld.f5r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB24"); + state->u.f1.fld.f5r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB25"); + state->u.f1.fld.f5r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB26"); + state->u.f1.fld.f5r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB27"); + state->u.f1.fld.f5r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB28"); + state->u.f1.fld.f5r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB29"); + state->u.f1.fld.f5r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB30"); + state->u.f1.fld.f5r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB31"); + + // F6R1 bitfields. + state->u.f1.fld.f6r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB0"); + state->u.f1.fld.f6r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB1"); + state->u.f1.fld.f6r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB2"); + state->u.f1.fld.f6r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB3"); + state->u.f1.fld.f6r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB4"); + state->u.f1.fld.f6r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB5"); + state->u.f1.fld.f6r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB6"); + state->u.f1.fld.f6r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB7"); + state->u.f1.fld.f6r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB8"); + state->u.f1.fld.f6r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB9"); + state->u.f1.fld.f6r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB10"); + state->u.f1.fld.f6r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB11"); + state->u.f1.fld.f6r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB12"); + state->u.f1.fld.f6r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB13"); + state->u.f1.fld.f6r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB14"); + state->u.f1.fld.f6r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB15"); + state->u.f1.fld.f6r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB16"); + state->u.f1.fld.f6r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB17"); + state->u.f1.fld.f6r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB18"); + state->u.f1.fld.f6r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB19"); + state->u.f1.fld.f6r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB20"); + state->u.f1.fld.f6r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB21"); + state->u.f1.fld.f6r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB22"); + state->u.f1.fld.f6r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB23"); + state->u.f1.fld.f6r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB24"); + state->u.f1.fld.f6r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB25"); + state->u.f1.fld.f6r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB26"); + state->u.f1.fld.f6r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB27"); + state->u.f1.fld.f6r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB28"); + state->u.f1.fld.f6r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB29"); + state->u.f1.fld.f6r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB30"); + state->u.f1.fld.f6r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB31"); + + // F6R2 bitfields. + state->u.f1.fld.f6r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB0"); + state->u.f1.fld.f6r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB1"); + state->u.f1.fld.f6r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB2"); + state->u.f1.fld.f6r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB3"); + state->u.f1.fld.f6r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB4"); + state->u.f1.fld.f6r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB5"); + state->u.f1.fld.f6r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB6"); + state->u.f1.fld.f6r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB7"); + state->u.f1.fld.f6r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB8"); + state->u.f1.fld.f6r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB9"); + state->u.f1.fld.f6r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB10"); + state->u.f1.fld.f6r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB11"); + state->u.f1.fld.f6r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB12"); + state->u.f1.fld.f6r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB13"); + state->u.f1.fld.f6r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB14"); + state->u.f1.fld.f6r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB15"); + state->u.f1.fld.f6r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB16"); + state->u.f1.fld.f6r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB17"); + state->u.f1.fld.f6r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB18"); + state->u.f1.fld.f6r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB19"); + state->u.f1.fld.f6r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB20"); + state->u.f1.fld.f6r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB21"); + state->u.f1.fld.f6r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB22"); + state->u.f1.fld.f6r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB23"); + state->u.f1.fld.f6r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB24"); + state->u.f1.fld.f6r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB25"); + state->u.f1.fld.f6r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB26"); + state->u.f1.fld.f6r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB27"); + state->u.f1.fld.f6r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB28"); + state->u.f1.fld.f6r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB29"); + state->u.f1.fld.f6r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB30"); + state->u.f1.fld.f6r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB31"); + + // F7R1 bitfields. + state->u.f1.fld.f7r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB0"); + state->u.f1.fld.f7r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB1"); + state->u.f1.fld.f7r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB2"); + state->u.f1.fld.f7r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB3"); + state->u.f1.fld.f7r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB4"); + state->u.f1.fld.f7r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB5"); + state->u.f1.fld.f7r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB6"); + state->u.f1.fld.f7r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB7"); + state->u.f1.fld.f7r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB8"); + state->u.f1.fld.f7r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB9"); + state->u.f1.fld.f7r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB10"); + state->u.f1.fld.f7r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB11"); + state->u.f1.fld.f7r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB12"); + state->u.f1.fld.f7r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB13"); + state->u.f1.fld.f7r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB14"); + state->u.f1.fld.f7r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB15"); + state->u.f1.fld.f7r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB16"); + state->u.f1.fld.f7r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB17"); + state->u.f1.fld.f7r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB18"); + state->u.f1.fld.f7r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB19"); + state->u.f1.fld.f7r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB20"); + state->u.f1.fld.f7r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB21"); + state->u.f1.fld.f7r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB22"); + state->u.f1.fld.f7r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB23"); + state->u.f1.fld.f7r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB24"); + state->u.f1.fld.f7r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB25"); + state->u.f1.fld.f7r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB26"); + state->u.f1.fld.f7r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB27"); + state->u.f1.fld.f7r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB28"); + state->u.f1.fld.f7r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB29"); + state->u.f1.fld.f7r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB30"); + state->u.f1.fld.f7r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB31"); + + // F7R2 bitfields. + state->u.f1.fld.f7r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB0"); + state->u.f1.fld.f7r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB1"); + state->u.f1.fld.f7r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB2"); + state->u.f1.fld.f7r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB3"); + state->u.f1.fld.f7r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB4"); + state->u.f1.fld.f7r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB5"); + state->u.f1.fld.f7r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB6"); + state->u.f1.fld.f7r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB7"); + state->u.f1.fld.f7r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB8"); + state->u.f1.fld.f7r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB9"); + state->u.f1.fld.f7r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB10"); + state->u.f1.fld.f7r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB11"); + state->u.f1.fld.f7r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB12"); + state->u.f1.fld.f7r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB13"); + state->u.f1.fld.f7r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB14"); + state->u.f1.fld.f7r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB15"); + state->u.f1.fld.f7r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB16"); + state->u.f1.fld.f7r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB17"); + state->u.f1.fld.f7r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB18"); + state->u.f1.fld.f7r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB19"); + state->u.f1.fld.f7r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB20"); + state->u.f1.fld.f7r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB21"); + state->u.f1.fld.f7r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB22"); + state->u.f1.fld.f7r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB23"); + state->u.f1.fld.f7r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB24"); + state->u.f1.fld.f7r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB25"); + state->u.f1.fld.f7r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB26"); + state->u.f1.fld.f7r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB27"); + state->u.f1.fld.f7r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB28"); + state->u.f1.fld.f7r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB29"); + state->u.f1.fld.f7r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB30"); + state->u.f1.fld.f7r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB31"); + + // F8R1 bitfields. + state->u.f1.fld.f8r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB0"); + state->u.f1.fld.f8r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB1"); + state->u.f1.fld.f8r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB2"); + state->u.f1.fld.f8r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB3"); + state->u.f1.fld.f8r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB4"); + state->u.f1.fld.f8r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB5"); + state->u.f1.fld.f8r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB6"); + state->u.f1.fld.f8r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB7"); + state->u.f1.fld.f8r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB8"); + state->u.f1.fld.f8r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB9"); + state->u.f1.fld.f8r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB10"); + state->u.f1.fld.f8r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB11"); + state->u.f1.fld.f8r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB12"); + state->u.f1.fld.f8r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB13"); + state->u.f1.fld.f8r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB14"); + state->u.f1.fld.f8r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB15"); + state->u.f1.fld.f8r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB16"); + state->u.f1.fld.f8r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB17"); + state->u.f1.fld.f8r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB18"); + state->u.f1.fld.f8r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB19"); + state->u.f1.fld.f8r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB20"); + state->u.f1.fld.f8r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB21"); + state->u.f1.fld.f8r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB22"); + state->u.f1.fld.f8r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB23"); + state->u.f1.fld.f8r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB24"); + state->u.f1.fld.f8r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB25"); + state->u.f1.fld.f8r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB26"); + state->u.f1.fld.f8r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB27"); + state->u.f1.fld.f8r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB28"); + state->u.f1.fld.f8r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB29"); + state->u.f1.fld.f8r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB30"); + state->u.f1.fld.f8r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB31"); + + // F8R2 bitfields. + state->u.f1.fld.f8r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB0"); + state->u.f1.fld.f8r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB1"); + state->u.f1.fld.f8r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB2"); + state->u.f1.fld.f8r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB3"); + state->u.f1.fld.f8r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB4"); + state->u.f1.fld.f8r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB5"); + state->u.f1.fld.f8r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB6"); + state->u.f1.fld.f8r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB7"); + state->u.f1.fld.f8r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB8"); + state->u.f1.fld.f8r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB9"); + state->u.f1.fld.f8r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB10"); + state->u.f1.fld.f8r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB11"); + state->u.f1.fld.f8r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB12"); + state->u.f1.fld.f8r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB13"); + state->u.f1.fld.f8r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB14"); + state->u.f1.fld.f8r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB15"); + state->u.f1.fld.f8r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB16"); + state->u.f1.fld.f8r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB17"); + state->u.f1.fld.f8r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB18"); + state->u.f1.fld.f8r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB19"); + state->u.f1.fld.f8r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB20"); + state->u.f1.fld.f8r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB21"); + state->u.f1.fld.f8r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB22"); + state->u.f1.fld.f8r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB23"); + state->u.f1.fld.f8r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB24"); + state->u.f1.fld.f8r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB25"); + state->u.f1.fld.f8r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB26"); + state->u.f1.fld.f8r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB27"); + state->u.f1.fld.f8r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB28"); + state->u.f1.fld.f8r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB29"); + state->u.f1.fld.f8r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB30"); + state->u.f1.fld.f8r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB31"); + + // F9R1 bitfields. + state->u.f1.fld.f9r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB0"); + state->u.f1.fld.f9r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB1"); + state->u.f1.fld.f9r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB2"); + state->u.f1.fld.f9r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB3"); + state->u.f1.fld.f9r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB4"); + state->u.f1.fld.f9r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB5"); + state->u.f1.fld.f9r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB6"); + state->u.f1.fld.f9r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB7"); + state->u.f1.fld.f9r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB8"); + state->u.f1.fld.f9r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB9"); + state->u.f1.fld.f9r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB10"); + state->u.f1.fld.f9r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB11"); + state->u.f1.fld.f9r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB12"); + state->u.f1.fld.f9r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB13"); + state->u.f1.fld.f9r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB14"); + state->u.f1.fld.f9r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB15"); + state->u.f1.fld.f9r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB16"); + state->u.f1.fld.f9r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB17"); + state->u.f1.fld.f9r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB18"); + state->u.f1.fld.f9r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB19"); + state->u.f1.fld.f9r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB20"); + state->u.f1.fld.f9r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB21"); + state->u.f1.fld.f9r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB22"); + state->u.f1.fld.f9r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB23"); + state->u.f1.fld.f9r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB24"); + state->u.f1.fld.f9r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB25"); + state->u.f1.fld.f9r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB26"); + state->u.f1.fld.f9r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB27"); + state->u.f1.fld.f9r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB28"); + state->u.f1.fld.f9r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB29"); + state->u.f1.fld.f9r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB30"); + state->u.f1.fld.f9r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB31"); + + // F9R2 bitfields. + state->u.f1.fld.f9r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB0"); + state->u.f1.fld.f9r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB1"); + state->u.f1.fld.f9r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB2"); + state->u.f1.fld.f9r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB3"); + state->u.f1.fld.f9r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB4"); + state->u.f1.fld.f9r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB5"); + state->u.f1.fld.f9r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB6"); + state->u.f1.fld.f9r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB7"); + state->u.f1.fld.f9r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB8"); + state->u.f1.fld.f9r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB9"); + state->u.f1.fld.f9r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB10"); + state->u.f1.fld.f9r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB11"); + state->u.f1.fld.f9r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB12"); + state->u.f1.fld.f9r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB13"); + state->u.f1.fld.f9r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB14"); + state->u.f1.fld.f9r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB15"); + state->u.f1.fld.f9r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB16"); + state->u.f1.fld.f9r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB17"); + state->u.f1.fld.f9r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB18"); + state->u.f1.fld.f9r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB19"); + state->u.f1.fld.f9r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB20"); + state->u.f1.fld.f9r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB21"); + state->u.f1.fld.f9r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB22"); + state->u.f1.fld.f9r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB23"); + state->u.f1.fld.f9r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB24"); + state->u.f1.fld.f9r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB25"); + state->u.f1.fld.f9r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB26"); + state->u.f1.fld.f9r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB27"); + state->u.f1.fld.f9r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB28"); + state->u.f1.fld.f9r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB29"); + state->u.f1.fld.f9r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB30"); + state->u.f1.fld.f9r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB31"); + + // F10R1 bitfields. + state->u.f1.fld.f10r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB0"); + state->u.f1.fld.f10r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB1"); + state->u.f1.fld.f10r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB2"); + state->u.f1.fld.f10r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB3"); + state->u.f1.fld.f10r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB4"); + state->u.f1.fld.f10r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB5"); + state->u.f1.fld.f10r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB6"); + state->u.f1.fld.f10r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB7"); + state->u.f1.fld.f10r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB8"); + state->u.f1.fld.f10r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB9"); + state->u.f1.fld.f10r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB10"); + state->u.f1.fld.f10r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB11"); + state->u.f1.fld.f10r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB12"); + state->u.f1.fld.f10r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB13"); + state->u.f1.fld.f10r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB14"); + state->u.f1.fld.f10r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB15"); + state->u.f1.fld.f10r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB16"); + state->u.f1.fld.f10r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB17"); + state->u.f1.fld.f10r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB18"); + state->u.f1.fld.f10r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB19"); + state->u.f1.fld.f10r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB20"); + state->u.f1.fld.f10r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB21"); + state->u.f1.fld.f10r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB22"); + state->u.f1.fld.f10r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB23"); + state->u.f1.fld.f10r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB24"); + state->u.f1.fld.f10r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB25"); + state->u.f1.fld.f10r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB26"); + state->u.f1.fld.f10r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB27"); + state->u.f1.fld.f10r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB28"); + state->u.f1.fld.f10r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB29"); + state->u.f1.fld.f10r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB30"); + state->u.f1.fld.f10r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB31"); + + // F10R2 bitfields. + state->u.f1.fld.f10r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB0"); + state->u.f1.fld.f10r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB1"); + state->u.f1.fld.f10r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB2"); + state->u.f1.fld.f10r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB3"); + state->u.f1.fld.f10r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB4"); + state->u.f1.fld.f10r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB5"); + state->u.f1.fld.f10r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB6"); + state->u.f1.fld.f10r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB7"); + state->u.f1.fld.f10r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB8"); + state->u.f1.fld.f10r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB9"); + state->u.f1.fld.f10r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB10"); + state->u.f1.fld.f10r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB11"); + state->u.f1.fld.f10r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB12"); + state->u.f1.fld.f10r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB13"); + state->u.f1.fld.f10r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB14"); + state->u.f1.fld.f10r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB15"); + state->u.f1.fld.f10r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB16"); + state->u.f1.fld.f10r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB17"); + state->u.f1.fld.f10r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB18"); + state->u.f1.fld.f10r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB19"); + state->u.f1.fld.f10r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB20"); + state->u.f1.fld.f10r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB21"); + state->u.f1.fld.f10r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB22"); + state->u.f1.fld.f10r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB23"); + state->u.f1.fld.f10r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB24"); + state->u.f1.fld.f10r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB25"); + state->u.f1.fld.f10r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB26"); + state->u.f1.fld.f10r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB27"); + state->u.f1.fld.f10r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB28"); + state->u.f1.fld.f10r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB29"); + state->u.f1.fld.f10r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB30"); + state->u.f1.fld.f10r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB31"); + + // F11R1 bitfields. + state->u.f1.fld.f11r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB0"); + state->u.f1.fld.f11r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB1"); + state->u.f1.fld.f11r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB2"); + state->u.f1.fld.f11r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB3"); + state->u.f1.fld.f11r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB4"); + state->u.f1.fld.f11r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB5"); + state->u.f1.fld.f11r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB6"); + state->u.f1.fld.f11r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB7"); + state->u.f1.fld.f11r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB8"); + state->u.f1.fld.f11r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB9"); + state->u.f1.fld.f11r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB10"); + state->u.f1.fld.f11r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB11"); + state->u.f1.fld.f11r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB12"); + state->u.f1.fld.f11r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB13"); + state->u.f1.fld.f11r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB14"); + state->u.f1.fld.f11r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB15"); + state->u.f1.fld.f11r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB16"); + state->u.f1.fld.f11r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB17"); + state->u.f1.fld.f11r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB18"); + state->u.f1.fld.f11r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB19"); + state->u.f1.fld.f11r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB20"); + state->u.f1.fld.f11r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB21"); + state->u.f1.fld.f11r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB22"); + state->u.f1.fld.f11r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB23"); + state->u.f1.fld.f11r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB24"); + state->u.f1.fld.f11r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB25"); + state->u.f1.fld.f11r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB26"); + state->u.f1.fld.f11r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB27"); + state->u.f1.fld.f11r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB28"); + state->u.f1.fld.f11r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB29"); + state->u.f1.fld.f11r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB30"); + state->u.f1.fld.f11r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB31"); + + // F11R2 bitfields. + state->u.f1.fld.f11r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB0"); + state->u.f1.fld.f11r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB1"); + state->u.f1.fld.f11r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB2"); + state->u.f1.fld.f11r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB3"); + state->u.f1.fld.f11r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB4"); + state->u.f1.fld.f11r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB5"); + state->u.f1.fld.f11r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB6"); + state->u.f1.fld.f11r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB7"); + state->u.f1.fld.f11r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB8"); + state->u.f1.fld.f11r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB9"); + state->u.f1.fld.f11r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB10"); + state->u.f1.fld.f11r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB11"); + state->u.f1.fld.f11r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB12"); + state->u.f1.fld.f11r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB13"); + state->u.f1.fld.f11r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB14"); + state->u.f1.fld.f11r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB15"); + state->u.f1.fld.f11r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB16"); + state->u.f1.fld.f11r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB17"); + state->u.f1.fld.f11r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB18"); + state->u.f1.fld.f11r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB19"); + state->u.f1.fld.f11r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB20"); + state->u.f1.fld.f11r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB21"); + state->u.f1.fld.f11r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB22"); + state->u.f1.fld.f11r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB23"); + state->u.f1.fld.f11r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB24"); + state->u.f1.fld.f11r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB25"); + state->u.f1.fld.f11r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB26"); + state->u.f1.fld.f11r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB27"); + state->u.f1.fld.f11r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB28"); + state->u.f1.fld.f11r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB29"); + state->u.f1.fld.f11r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB30"); + state->u.f1.fld.f11r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB31"); + + // F12R1 bitfields. + state->u.f1.fld.f12r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB0"); + state->u.f1.fld.f12r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB1"); + state->u.f1.fld.f12r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB2"); + state->u.f1.fld.f12r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB3"); + state->u.f1.fld.f12r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB4"); + state->u.f1.fld.f12r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB5"); + state->u.f1.fld.f12r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB6"); + state->u.f1.fld.f12r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB7"); + state->u.f1.fld.f12r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB8"); + state->u.f1.fld.f12r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB9"); + state->u.f1.fld.f12r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB10"); + state->u.f1.fld.f12r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB11"); + state->u.f1.fld.f12r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB12"); + state->u.f1.fld.f12r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB13"); + state->u.f1.fld.f12r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB14"); + state->u.f1.fld.f12r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB15"); + state->u.f1.fld.f12r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB16"); + state->u.f1.fld.f12r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB17"); + state->u.f1.fld.f12r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB18"); + state->u.f1.fld.f12r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB19"); + state->u.f1.fld.f12r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB20"); + state->u.f1.fld.f12r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB21"); + state->u.f1.fld.f12r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB22"); + state->u.f1.fld.f12r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB23"); + state->u.f1.fld.f12r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB24"); + state->u.f1.fld.f12r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB25"); + state->u.f1.fld.f12r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB26"); + state->u.f1.fld.f12r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB27"); + state->u.f1.fld.f12r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB28"); + state->u.f1.fld.f12r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB29"); + state->u.f1.fld.f12r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB30"); + state->u.f1.fld.f12r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB31"); + + // F12R2 bitfields. + state->u.f1.fld.f12r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB0"); + state->u.f1.fld.f12r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB1"); + state->u.f1.fld.f12r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB2"); + state->u.f1.fld.f12r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB3"); + state->u.f1.fld.f12r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB4"); + state->u.f1.fld.f12r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB5"); + state->u.f1.fld.f12r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB6"); + state->u.f1.fld.f12r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB7"); + state->u.f1.fld.f12r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB8"); + state->u.f1.fld.f12r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB9"); + state->u.f1.fld.f12r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB10"); + state->u.f1.fld.f12r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB11"); + state->u.f1.fld.f12r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB12"); + state->u.f1.fld.f12r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB13"); + state->u.f1.fld.f12r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB14"); + state->u.f1.fld.f12r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB15"); + state->u.f1.fld.f12r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB16"); + state->u.f1.fld.f12r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB17"); + state->u.f1.fld.f12r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB18"); + state->u.f1.fld.f12r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB19"); + state->u.f1.fld.f12r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB20"); + state->u.f1.fld.f12r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB21"); + state->u.f1.fld.f12r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB22"); + state->u.f1.fld.f12r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB23"); + state->u.f1.fld.f12r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB24"); + state->u.f1.fld.f12r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB25"); + state->u.f1.fld.f12r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB26"); + state->u.f1.fld.f12r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB27"); + state->u.f1.fld.f12r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB28"); + state->u.f1.fld.f12r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB29"); + state->u.f1.fld.f12r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB30"); + state->u.f1.fld.f12r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB31"); + + // F13R1 bitfields. + state->u.f1.fld.f13r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB0"); + state->u.f1.fld.f13r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB1"); + state->u.f1.fld.f13r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB2"); + state->u.f1.fld.f13r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB3"); + state->u.f1.fld.f13r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB4"); + state->u.f1.fld.f13r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB5"); + state->u.f1.fld.f13r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB6"); + state->u.f1.fld.f13r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB7"); + state->u.f1.fld.f13r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB8"); + state->u.f1.fld.f13r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB9"); + state->u.f1.fld.f13r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB10"); + state->u.f1.fld.f13r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB11"); + state->u.f1.fld.f13r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB12"); + state->u.f1.fld.f13r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB13"); + state->u.f1.fld.f13r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB14"); + state->u.f1.fld.f13r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB15"); + state->u.f1.fld.f13r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB16"); + state->u.f1.fld.f13r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB17"); + state->u.f1.fld.f13r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB18"); + state->u.f1.fld.f13r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB19"); + state->u.f1.fld.f13r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB20"); + state->u.f1.fld.f13r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB21"); + state->u.f1.fld.f13r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB22"); + state->u.f1.fld.f13r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB23"); + state->u.f1.fld.f13r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB24"); + state->u.f1.fld.f13r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB25"); + state->u.f1.fld.f13r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB26"); + state->u.f1.fld.f13r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB27"); + state->u.f1.fld.f13r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB28"); + state->u.f1.fld.f13r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB29"); + state->u.f1.fld.f13r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB30"); + state->u.f1.fld.f13r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB31"); + + // F13R2 bitfields. + state->u.f1.fld.f13r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB0"); + state->u.f1.fld.f13r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB1"); + state->u.f1.fld.f13r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB2"); + state->u.f1.fld.f13r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB3"); + state->u.f1.fld.f13r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB4"); + state->u.f1.fld.f13r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB5"); + state->u.f1.fld.f13r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB6"); + state->u.f1.fld.f13r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB7"); + state->u.f1.fld.f13r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB8"); + state->u.f1.fld.f13r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB9"); + state->u.f1.fld.f13r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB10"); + state->u.f1.fld.f13r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB11"); + state->u.f1.fld.f13r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB12"); + state->u.f1.fld.f13r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB13"); + state->u.f1.fld.f13r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB14"); + state->u.f1.fld.f13r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB15"); + state->u.f1.fld.f13r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB16"); + state->u.f1.fld.f13r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB17"); + state->u.f1.fld.f13r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB18"); + state->u.f1.fld.f13r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB19"); + state->u.f1.fld.f13r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB20"); + state->u.f1.fld.f13r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB21"); + state->u.f1.fld.f13r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB22"); + state->u.f1.fld.f13r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB23"); + state->u.f1.fld.f13r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB24"); + state->u.f1.fld.f13r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB25"); + state->u.f1.fld.f13r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB26"); + state->u.f1.fld.f13r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB27"); + state->u.f1.fld.f13r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB28"); + state->u.f1.fld.f13r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB29"); + state->u.f1.fld.f13r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB30"); + state->u.f1.fld.f13r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB31"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_can_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_can_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_can_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_can_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_can_is_enabled(Object *obj) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_can_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CANState *state = STM32_CAN_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_can_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CAN)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CANState *state = STM32_CAN_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CAN"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_can_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_can_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_can_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_can_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_can_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CANEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_can_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CAN); +} + +static void stm32_can_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_can_reset_callback; + dc->realize = stm32_can_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_can_is_enabled; +} + +static const TypeInfo stm32_can_type_info = { + .name = TYPE_STM32_CAN, + .parent = TYPE_STM32_CAN_PARENT, + .instance_init = stm32_can_instance_init_callback, + .instance_size = sizeof(STM32CANState), + .class_init = stm32_can_class_init_callback, + .class_size = sizeof(STM32CANClass) }; + +static void stm32_can_register_types(void) +{ + type_register_static(&stm32_can_type_info); +} + +type_init(stm32_can_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/can.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/can.h new file mode 100644 index 0000000000..36a4f897ac --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/can.h @@ -0,0 +1,1510 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CAN_H_ +#define STM32_CAN_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CAN DEVICE_PATH_STM32 "CAN" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CAN TYPE_STM32_PREFIX "can" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CAN_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CANParentClass; +typedef PeripheralState STM32CANParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CAN_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CANClass, (obj), TYPE_STM32_CAN) +#define STM32_CAN_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CANClass, (klass), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentClass parent_class; + // public: + + // None, so far. +} STM32CANClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CAN_STATE(obj) \ + OBJECT_CHECK(STM32CANState, (obj), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 CAN (Controller area network) registers. + struct { + Object *can_mcr; // 0x0 (CAN_MCR) + Object *can_msr; // 0x4 (CAN_MSR) + Object *can_tsr; // 0x8 (CAN_TSR) + Object *can_rf0r; // 0xC (CAN_RF0R) + Object *can_rf1r; // 0x10 (CAN_RF1R) + Object *can_ier; // 0x14 (CAN_IER) + Object *can_esr; // 0x18 (CAN_ESR) + Object *can_btr; // 0x1C (CAN_BTR) + Object *can_ti0r; // 0x180 (CAN_TI0R) + Object *can_tdt0r; // 0x184 (CAN_TDT0R) + Object *can_tdl0r; // 0x188 (CAN_TDL0R) + Object *can_tdh0r; // 0x18C (CAN_TDH0R) + Object *can_ti1r; // 0x190 (CAN_TI1R) + Object *can_tdt1r; // 0x194 (CAN_TDT1R) + Object *can_tdl1r; // 0x198 (CAN_TDL1R) + Object *can_tdh1r; // 0x19C (CAN_TDH1R) + Object *can_ti2r; // 0x1A0 (CAN_TI2R) + Object *can_tdt2r; // 0x1A4 (CAN_TDT2R) + Object *can_tdl2r; // 0x1A8 (CAN_TDL2R) + Object *can_tdh2r; // 0x1AC (CAN_TDH2R) + Object *can_ri0r; // 0x1B0 (CAN_RI0R) + Object *can_rdt0r; // 0x1B4 (CAN_RDT0R) + Object *can_rdl0r; // 0x1B8 (CAN_RDL0R) + Object *can_rdh0r; // 0x1BC (CAN_RDH0R) + Object *can_ri1r; // 0x1C0 (CAN_RI1R) + Object *can_rdt1r; // 0x1C4 (CAN_RDT1R) + Object *can_rdl1r; // 0x1C8 (CAN_RDL1R) + Object *can_rdh1r; // 0x1CC (CAN_RDH1R) + Object *can_fmr; // 0x200 (CAN_FMR) + Object *can_fm1r; // 0x204 (CAN_FM1R) + Object *can_fs1r; // 0x20C (CAN_FS1R) + Object *can_ffa1r; // 0x214 (CAN_FFA1R) + Object *can_fa1r; // 0x21C (CAN_FA1R) + Object *f0r1; // 0x240 (Filter bank 0 register 1) + Object *f0r2; // 0x244 (Filter bank 0 register 2) + Object *f1r1; // 0x248 (Filter bank 1 register 1) + Object *f1r2; // 0x24C (Filter bank 1 register 2) + Object *f2r1; // 0x250 (Filter bank 2 register 1) + Object *f2r2; // 0x254 (Filter bank 2 register 2) + Object *f3r1; // 0x258 (Filter bank 3 register 1) + Object *f3r2; // 0x25C (Filter bank 3 register 2) + Object *f4r1; // 0x260 (Filter bank 4 register 1) + Object *f4r2; // 0x264 (Filter bank 4 register 2) + Object *f5r1; // 0x268 (Filter bank 5 register 1) + Object *f5r2; // 0x26C (Filter bank 5 register 2) + Object *f6r1; // 0x270 (Filter bank 6 register 1) + Object *f6r2; // 0x274 (Filter bank 6 register 2) + Object *f7r1; // 0x278 (Filter bank 7 register 1) + Object *f7r2; // 0x27C (Filter bank 7 register 2) + Object *f8r1; // 0x280 (Filter bank 8 register 1) + Object *f8r2; // 0x284 (Filter bank 8 register 2) + Object *f9r1; // 0x288 (Filter bank 9 register 1) + Object *f9r2; // 0x28C (Filter bank 9 register 2) + Object *f10r1; // 0x290 (Filter bank 10 register 1) + Object *f10r2; // 0x294 (Filter bank 10 register 2) + Object *f11r1; // 0x298 (Filter bank 11 register 1) + Object *f11r2; // 0x29C (Filter bank 11 register 2) + Object *f12r1; // 0x2A0 (Filter bank 4 register 1) + Object *f12r2; // 0x2A4 (Filter bank 12 register 2) + Object *f13r1; // 0x2A8 (Filter bank 13 register 1) + Object *f13r2; // 0x2AC (Filter bank 13 register 2) + } reg; + + struct { + + // CAN_MCR (CAN_MCR) bitfields. + struct { + Object *inrq; // [0:0] INRQ + Object *sleep; // [1:1] SLEEP + Object *txfp; // [2:2] TXFP + Object *rflm; // [3:3] RFLM + Object *nart; // [4:4] NART + Object *awum; // [5:5] AWUM + Object *abom; // [6:6] ABOM + Object *ttcm; // [7:7] TTCM + Object *reset; // [15:15] RESET + Object *dbf; // [16:16] DBF + } can_mcr; + + // CAN_MSR (CAN_MSR) bitfields. + struct { + Object *inak; // [0:0] INAK + Object *slak; // [1:1] SLAK + Object *erri; // [2:2] ERRI + Object *wkui; // [3:3] WKUI + Object *slaki; // [4:4] SLAKI + Object *txm; // [8:8] TXM + Object *rxm; // [9:9] RXM + Object *samp; // [10:10] SAMP + Object *rx; // [11:11] RX + } can_msr; + + // CAN_TSR (CAN_TSR) bitfields. + struct { + Object *rqcp0; // [0:0] RQCP0 + Object *txok0; // [1:1] TXOK0 + Object *alst0; // [2:2] ALST0 + Object *terr0; // [3:3] TERR0 + Object *abrq0; // [7:7] ABRQ0 + Object *rqcp1; // [8:8] RQCP1 + Object *txok1; // [9:9] TXOK1 + Object *alst1; // [10:10] ALST1 + Object *terr1; // [11:11] TERR1 + Object *abrq1; // [15:15] ABRQ1 + Object *rqcp2; // [16:16] RQCP2 + Object *txok2; // [17:17] TXOK2 + Object *alst2; // [18:18] ALST2 + Object *terr2; // [19:19] TERR2 + Object *abrq2; // [23:23] ABRQ2 + Object *code; // [24:25] CODE + Object *tme0; // [26:26] Lowest priority flag for mailbox 0 + Object *tme1; // [27:27] Lowest priority flag for mailbox 1 + Object *tme2; // [28:28] Lowest priority flag for mailbox 2 + Object *low0; // [29:29] Lowest priority flag for mailbox 0 + Object *low1; // [30:30] Lowest priority flag for mailbox 1 + Object *low2; // [31:31] Lowest priority flag for mailbox 2 + } can_tsr; + + // CAN_RF0R (CAN_RF0R) bitfields. + struct { + Object *fmp0; // [0:1] FMP0 + Object *full0; // [3:3] FULL0 + Object *fovr0; // [4:4] FOVR0 + Object *rfom0; // [5:5] RFOM0 + } can_rf0r; + + // CAN_RF1R (CAN_RF1R) bitfields. + struct { + Object *fmp1; // [0:1] FMP1 + Object *full1; // [3:3] FULL1 + Object *fovr1; // [4:4] FOVR1 + Object *rfom1; // [5:5] RFOM1 + } can_rf1r; + + // CAN_IER (CAN_IER) bitfields. + struct { + Object *tmeie; // [0:0] TMEIE + Object *fmpie0; // [1:1] FMPIE0 + Object *ffie0; // [2:2] FFIE0 + Object *fovie0; // [3:3] FOVIE0 + Object *fmpie1; // [4:4] FMPIE1 + Object *ffie1; // [5:5] FFIE1 + Object *fovie1; // [6:6] FOVIE1 + Object *ewgie; // [8:8] EWGIE + Object *epvie; // [9:9] EPVIE + Object *bofie; // [10:10] BOFIE + Object *lecie; // [11:11] LECIE + Object *errie; // [15:15] ERRIE + Object *wkuie; // [16:16] WKUIE + Object *slkie; // [17:17] SLKIE + } can_ier; + + // CAN_ESR (CAN_ESR) bitfields. + struct { + Object *ewgf; // [0:0] EWGF + Object *epvf; // [1:1] EPVF + Object *boff; // [2:2] BOFF + Object *lec; // [4:6] LEC + Object *tec; // [16:23] TEC + Object *rec; // [24:31] REC + } can_esr; + + // CAN_BTR (CAN_BTR) bitfields. + struct { + Object *brp; // [0:9] BRP + Object *ts1; // [16:19] TS1 + Object *ts2; // [20:22] TS2 + Object *sjw; // [24:25] SJW + Object *lbkm; // [30:30] LBKM + Object *silm; // [31:31] SILM + } can_btr; + + // CAN_TI0R (CAN_TI0R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti0r; + + // CAN_TDT0R (CAN_TDT0R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt0r; + + // CAN_TDL0R (CAN_TDL0R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl0r; + + // CAN_TDH0R (CAN_TDH0R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh0r; + + // CAN_TI1R (CAN_TI1R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti1r; + + // CAN_TDT1R (CAN_TDT1R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt1r; + + // CAN_TDL1R (CAN_TDL1R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl1r; + + // CAN_TDH1R (CAN_TDH1R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh1r; + + // CAN_TI2R (CAN_TI2R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti2r; + + // CAN_TDT2R (CAN_TDT2R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt2r; + + // CAN_TDL2R (CAN_TDL2R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl2r; + + // CAN_TDH2R (CAN_TDH2R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh2r; + + // CAN_RI0R (CAN_RI0R) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ri0r; + + // CAN_RDT0R (CAN_RDT0R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } can_rdt0r; + + // CAN_RDL0R (CAN_RDL0R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_rdl0r; + + // CAN_RDH0R (CAN_RDH0R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_rdh0r; + + // CAN_RI1R (CAN_RI1R) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ri1r; + + // CAN_RDT1R (CAN_RDT1R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } can_rdt1r; + + // CAN_RDL1R (CAN_RDL1R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_rdl1r; + + // CAN_RDH1R (CAN_RDH1R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_rdh1r; + + // CAN_FMR (CAN_FMR) bitfields. + struct { + Object *finit; // [0:0] FINIT + } can_fmr; + + // CAN_FM1R (CAN_FM1R) bitfields. + struct { + Object *fbm0; // [0:0] Filter mode + Object *fbm1; // [1:1] Filter mode + Object *fbm2; // [2:2] Filter mode + Object *fbm3; // [3:3] Filter mode + Object *fbm4; // [4:4] Filter mode + Object *fbm5; // [5:5] Filter mode + Object *fbm6; // [6:6] Filter mode + Object *fbm7; // [7:7] Filter mode + Object *fbm8; // [8:8] Filter mode + Object *fbm9; // [9:9] Filter mode + Object *fbm10; // [10:10] Filter mode + Object *fbm11; // [11:11] Filter mode + Object *fbm12; // [12:12] Filter mode + Object *fbm13; // [13:13] Filter mode + } can_fm1r; + + // CAN_FS1R (CAN_FS1R) bitfields. + struct { + Object *fsc0; // [0:0] Filter scale configuration + Object *fsc1; // [1:1] Filter scale configuration + Object *fsc2; // [2:2] Filter scale configuration + Object *fsc3; // [3:3] Filter scale configuration + Object *fsc4; // [4:4] Filter scale configuration + Object *fsc5; // [5:5] Filter scale configuration + Object *fsc6; // [6:6] Filter scale configuration + Object *fsc7; // [7:7] Filter scale configuration + Object *fsc8; // [8:8] Filter scale configuration + Object *fsc9; // [9:9] Filter scale configuration + Object *fsc10; // [10:10] Filter scale configuration + Object *fsc11; // [11:11] Filter scale configuration + Object *fsc12; // [12:12] Filter scale configuration + Object *fsc13; // [13:13] Filter scale configuration + } can_fs1r; + + // CAN_FFA1R (CAN_FFA1R) bitfields. + struct { + Object *ffa0; // [0:0] Filter FIFO assignment for filter 0 + Object *ffa1; // [1:1] Filter FIFO assignment for filter 1 + Object *ffa2; // [2:2] Filter FIFO assignment for filter 2 + Object *ffa3; // [3:3] Filter FIFO assignment for filter 3 + Object *ffa4; // [4:4] Filter FIFO assignment for filter 4 + Object *ffa5; // [5:5] Filter FIFO assignment for filter 5 + Object *ffa6; // [6:6] Filter FIFO assignment for filter 6 + Object *ffa7; // [7:7] Filter FIFO assignment for filter 7 + Object *ffa8; // [8:8] Filter FIFO assignment for filter 8 + Object *ffa9; // [9:9] Filter FIFO assignment for filter 9 + Object *ffa10; // [10:10] Filter FIFO assignment for filter 10 + Object *ffa11; // [11:11] Filter FIFO assignment for filter 11 + Object *ffa12; // [12:12] Filter FIFO assignment for filter 12 + Object *ffa13; // [13:13] Filter FIFO assignment for filter 13 + } can_ffa1r; + + // CAN_FA1R (CAN_FA1R) bitfields. + struct { + Object *fact0; // [0:0] Filter active + Object *fact1; // [1:1] Filter active + Object *fact2; // [2:2] Filter active + Object *fact3; // [3:3] Filter active + Object *fact4; // [4:4] Filter active + Object *fact5; // [5:5] Filter active + Object *fact6; // [6:6] Filter active + Object *fact7; // [7:7] Filter active + Object *fact8; // [8:8] Filter active + Object *fact9; // [9:9] Filter active + Object *fact10; // [10:10] Filter active + Object *fact11; // [11:11] Filter active + Object *fact12; // [12:12] Filter active + Object *fact13; // [13:13] Filter active + } can_fa1r; + + // F0R1 (Filter bank 0 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r1; + + // F0R2 (Filter bank 0 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r2; + + // F1R1 (Filter bank 1 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r1; + + // F1R2 (Filter bank 1 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r2; + + // F2R1 (Filter bank 2 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r1; + + // F2R2 (Filter bank 2 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r2; + + // F3R1 (Filter bank 3 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r1; + + // F3R2 (Filter bank 3 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r2; + + // F4R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r1; + + // F4R2 (Filter bank 4 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r2; + + // F5R1 (Filter bank 5 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r1; + + // F5R2 (Filter bank 5 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r2; + + // F6R1 (Filter bank 6 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r1; + + // F6R2 (Filter bank 6 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r2; + + // F7R1 (Filter bank 7 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r1; + + // F7R2 (Filter bank 7 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r2; + + // F8R1 (Filter bank 8 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r1; + + // F8R2 (Filter bank 8 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r2; + + // F9R1 (Filter bank 9 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r1; + + // F9R2 (Filter bank 9 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r2; + + // F10R1 (Filter bank 10 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r1; + + // F10R2 (Filter bank 10 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r2; + + // F11R1 (Filter bank 11 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r1; + + // F11R2 (Filter bank 11 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r2; + + // F12R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r1; + + // F12R2 (Filter bank 12 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r2; + + // F13R1 (Filter bank 13 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r1; + + // F13R2 (Filter bank 13 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CANState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CAN_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/crc.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/crc.c new file mode 100644 index 0000000000..a7f0d819ad --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/crc.c @@ -0,0 +1,246 @@ +/* + * STM32 - CRC (CRC calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_crc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // IDR bitfields. + state->u.f1.fld.idr.idr = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR"); + + // CR bitfields. + state->u.f1.fld.cr.reset = cm_object_get_child_by_name(state->u.f1.reg.cr, "RESET"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crc_is_enabled(Object *obj) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRCState *state = STM32_CRC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRCState *state = STM32_CRC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_crc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_crc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_crc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_crc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_crc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRC); +} + +static void stm32_crc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crc_reset_callback; + dc->realize = stm32_crc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crc_is_enabled; +} + +static const TypeInfo stm32_crc_type_info = { + .name = TYPE_STM32_CRC, + .parent = TYPE_STM32_CRC_PARENT, + .instance_init = stm32_crc_instance_init_callback, + .instance_size = sizeof(STM32CRCState), + .class_init = stm32_crc_class_init_callback, + .class_size = sizeof(STM32CRCClass) }; + +static void stm32_crc_register_types(void) +{ + type_register_static(&stm32_crc_type_info); +} + +type_init(stm32_crc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/crc.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/crc.h new file mode 100644 index 0000000000..c9b09529c6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/crc.h @@ -0,0 +1,117 @@ +/* + * STM32 - CRC (CRC calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRC_H_ +#define STM32_CRC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRC DEVICE_PATH_STM32 "CRC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRC TYPE_STM32_PREFIX "crc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRCParentClass; +typedef PeripheralState STM32CRCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRCClass, (obj), TYPE_STM32_CRC) +#define STM32_CRC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRCClass, (klass), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentClass parent_class; + // public: + + // None, so far. +} STM32CRCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRC_STATE(obj) \ + OBJECT_CHECK(STM32CRCState, (obj), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 CRC (CRC calculation unit) registers. + struct { + Object *dr; // 0x0 (Data register) + Object *idr; // 0x4 (Independent Data register) + Object *cr; // 0x8 (Control register) + } reg; + + struct { + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:31] Data Register + } dr; + + // IDR (Independent Data register) bitfields. + struct { + Object *idr; // [0:7] Independent Data register + } idr; + + // CR (Control register) bitfields. + struct { + Object *reset; // [0:0] Reset bit + } cr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/dac.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/dac.c new file mode 100644 index 0000000000..0932a35581 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/dac.c @@ -0,0 +1,303 @@ +/* + * STM32 - DAC (Digital to analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_dac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.swtrigr = cm_object_get_child_by_name(obj, "SWTRIGR"); + state->u.f1.reg.dhr12r1 = cm_object_get_child_by_name(obj, "DHR12R1"); + state->u.f1.reg.dhr12l1 = cm_object_get_child_by_name(obj, "DHR12L1"); + state->u.f1.reg.dhr8r1 = cm_object_get_child_by_name(obj, "DHR8R1"); + state->u.f1.reg.dhr12r2 = cm_object_get_child_by_name(obj, "DHR12R2"); + state->u.f1.reg.dhr12l2 = cm_object_get_child_by_name(obj, "DHR12L2"); + state->u.f1.reg.dhr8r2 = cm_object_get_child_by_name(obj, "DHR8R2"); + state->u.f1.reg.dhr12rd = cm_object_get_child_by_name(obj, "DHR12RD"); + state->u.f1.reg.dhr12ld = cm_object_get_child_by_name(obj, "DHR12LD"); + state->u.f1.reg.dhr8rd = cm_object_get_child_by_name(obj, "DHR8RD"); + state->u.f1.reg.dor1 = cm_object_get_child_by_name(obj, "DOR1"); + state->u.f1.reg.dor2 = cm_object_get_child_by_name(obj, "DOR2"); + + + // CR bitfields. + state->u.f1.fld.cr.en1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "EN1"); + state->u.f1.fld.cr.boff1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "BOFF1"); + state->u.f1.fld.cr.ten1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TEN1"); + state->u.f1.fld.cr.tsel1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TSEL1"); + state->u.f1.fld.cr.wave1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "WAVE1"); + state->u.f1.fld.cr.mamp1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "MAMP1"); + state->u.f1.fld.cr.dmaen1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "DMAEN1"); + state->u.f1.fld.cr.en2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "EN2"); + state->u.f1.fld.cr.boff2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "BOFF2"); + state->u.f1.fld.cr.ten2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TEN2"); + state->u.f1.fld.cr.tsel2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TSEL2"); + state->u.f1.fld.cr.wave2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "WAVE2"); + state->u.f1.fld.cr.mamp2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "MAMP2"); + state->u.f1.fld.cr.dmaen2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "DMAEN2"); + + // SWTRIGR bitfields. + state->u.f1.fld.swtrigr.swtrig1 = cm_object_get_child_by_name(state->u.f1.reg.swtrigr, "SWTRIG1"); + state->u.f1.fld.swtrigr.swtrig2 = cm_object_get_child_by_name(state->u.f1.reg.swtrigr, "SWTRIG2"); + + // DHR12R1 bitfields. + state->u.f1.fld.dhr12r1.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12r1, "DACC1DHR"); + + // DHR12L1 bitfields. + state->u.f1.fld.dhr12l1.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12l1, "DACC1DHR"); + + // DHR8R1 bitfields. + state->u.f1.fld.dhr8r1.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8r1, "DACC1DHR"); + + // DHR12R2 bitfields. + state->u.f1.fld.dhr12r2.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12r2, "DACC2DHR"); + + // DHR12L2 bitfields. + state->u.f1.fld.dhr12l2.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12l2, "DACC2DHR"); + + // DHR8R2 bitfields. + state->u.f1.fld.dhr8r2.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8r2, "DACC2DHR"); + + // DHR12RD bitfields. + state->u.f1.fld.dhr12rd.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12rd, "DACC1DHR"); + state->u.f1.fld.dhr12rd.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12rd, "DACC2DHR"); + + // DHR12LD bitfields. + state->u.f1.fld.dhr12ld.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12ld, "DACC1DHR"); + state->u.f1.fld.dhr12ld.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12ld, "DACC2DHR"); + + // DHR8RD bitfields. + state->u.f1.fld.dhr8rd.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8rd, "DACC1DHR"); + state->u.f1.fld.dhr8rd.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8rd, "DACC2DHR"); + + // DOR1 bitfields. + state->u.f1.fld.dor1.dacc1dor = cm_object_get_child_by_name(state->u.f1.reg.dor1, "DACC1DOR"); + + // DOR2 bitfields. + state->u.f1.fld.dor2.dacc2dor = cm_object_get_child_by_name(state->u.f1.reg.dor2, "DACC2DOR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dac_is_enabled(Object *obj) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DACState *state = STM32_DAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DACState *state = STM32_DAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_dac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_dac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_dac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DAC); +} + +static void stm32_dac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dac_reset_callback; + dc->realize = stm32_dac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dac_is_enabled; +} + +static const TypeInfo stm32_dac_type_info = { + .name = TYPE_STM32_DAC, + .parent = TYPE_STM32_DAC_PARENT, + .instance_init = stm32_dac_instance_init_callback, + .instance_size = sizeof(STM32DACState), + .class_init = stm32_dac_class_init_callback, + .class_size = sizeof(STM32DACClass) }; + +static void stm32_dac_register_types(void) +{ + type_register_static(&stm32_dac_type_info); +} + +type_init(stm32_dac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/dac.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/dac.h new file mode 100644 index 0000000000..8c703fe1d1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/dac.h @@ -0,0 +1,194 @@ +/* + * STM32 - DAC (Digital to analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DAC_H_ +#define STM32_DAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DAC DEVICE_PATH_STM32 "DAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DAC TYPE_STM32_PREFIX "dac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DACParentClass; +typedef PeripheralState STM32DACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DACClass, (obj), TYPE_STM32_DAC) +#define STM32_DAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DACClass, (klass), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentClass parent_class; + // public: + + // None, so far. +} STM32DACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DAC_STATE(obj) \ + OBJECT_CHECK(STM32DACState, (obj), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 DAC (Digital to analog converter) registers. + struct { + Object *cr; // 0x0 (Control register (DAC_CR)) + Object *swtrigr; // 0x4 (DAC software trigger register (DAC_SWTRIGR)) + Object *dhr12r1; // 0x8 (DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)) + Object *dhr12l1; // 0xC (DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)) + Object *dhr8r1; // 0x10 (DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)) + Object *dhr12r2; // 0x14 (DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)) + Object *dhr12l2; // 0x18 (DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)) + Object *dhr8r2; // 0x1C (DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)) + Object *dhr12rd; // 0x20 (Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved) + Object *dhr12ld; // 0x24 (DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved) + Object *dhr8rd; // 0x28 (DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved) + Object *dor1; // 0x2C (DAC channel1 data output register (DAC_DOR1)) + Object *dor2; // 0x30 (DAC channel2 data output register (DAC_DOR2)) + } reg; + + struct { + + // CR (Control register (DAC_CR)) bitfields. + struct { + Object *en1; // [0:0] DAC channel1 enable + Object *boff1; // [1:1] DAC channel1 output buffer disable + Object *ten1; // [2:2] DAC channel1 trigger enable + Object *tsel1; // [3:5] DAC channel1 trigger selection + Object *wave1; // [6:7] DAC channel1 noise/triangle wave generation enable + Object *mamp1; // [8:11] DAC channel1 mask/amplitude selector + Object *dmaen1; // [12:12] DAC channel1 DMA enable + Object *en2; // [16:16] DAC channel2 enable + Object *boff2; // [17:17] DAC channel2 output buffer disable + Object *ten2; // [18:18] DAC channel2 trigger enable + Object *tsel2; // [19:21] DAC channel2 trigger selection + Object *wave2; // [22:23] DAC channel2 noise/triangle wave generation enable + Object *mamp2; // [24:27] DAC channel2 mask/amplitude selector + Object *dmaen2; // [28:28] DAC channel2 DMA enable + } cr; + + // SWTRIGR (DAC software trigger register (DAC_SWTRIGR)) bitfields. + struct { + Object *swtrig1; // [0:0] DAC channel1 software trigger + Object *swtrig2; // [1:1] DAC channel2 software trigger + } swtrigr; + + // DHR12R1 (DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + } dhr12r1; + + // DHR12L1 (DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + } dhr12l1; + + // DHR8R1 (DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + } dhr8r1; + + // DHR12R2 (DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)) bitfields. + struct { + Object *dacc2dhr; // [0:11] DAC channel2 12-bit right-aligned data + } dhr12r2; + + // DHR12L2 (DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)) bitfields. + struct { + Object *dacc2dhr; // [4:15] DAC channel2 12-bit left-aligned data + } dhr12l2; + + // DHR8R2 (DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)) bitfields. + struct { + Object *dacc2dhr; // [0:7] DAC channel2 8-bit right-aligned data + } dhr8r2; + + // DHR12RD (Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + Object *dacc2dhr; // [16:27] DAC channel2 12-bit right-aligned data + } dhr12rd; + + // DHR12LD (DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + Object *dacc2dhr; // [20:31] DAC channel2 12-bit right-aligned data + } dhr12ld; + + // DHR8RD (DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + Object *dacc2dhr; // [8:15] DAC channel2 8-bit right-aligned data + } dhr8rd; + + // DOR1 (DAC channel1 data output register (DAC_DOR1)) bitfields. + struct { + Object *dacc1dor; // [0:11] DAC channel1 data output + } dor1; + + // DOR2 (DAC channel2 data output register (DAC_DOR2)) bitfields. + struct { + Object *dacc2dor; // [0:11] DAC channel2 data output + } dor2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/dbg.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/dbg.c new file mode 100644 index 0000000000..9b7ca880c5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/dbg.c @@ -0,0 +1,261 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_dbg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.idcode = cm_object_get_child_by_name(obj, "IDCODE"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + + + // IDCODE bitfields. + state->u.f1.fld.idcode.dev_id = cm_object_get_child_by_name(state->u.f1.reg.idcode, "DEV_ID"); + state->u.f1.fld.idcode.rev_id = cm_object_get_child_by_name(state->u.f1.reg.idcode, "REV_ID"); + + // CR bitfields. + state->u.f1.fld.cr.dbg_sleep = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_SLEEP"); + state->u.f1.fld.cr.dbg_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_STOP"); + state->u.f1.fld.cr.dbg_standby = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_STANDBY"); + state->u.f1.fld.cr.trace_ioen = cm_object_get_child_by_name(state->u.f1.reg.cr, "TRACE_IOEN"); + state->u.f1.fld.cr.trace_mode = cm_object_get_child_by_name(state->u.f1.reg.cr, "TRACE_MODE"); + state->u.f1.fld.cr.dbg_iwdg_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_IWDG_STOP"); + state->u.f1.fld.cr.dbg_wwdg_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_WWDG_STOP"); + state->u.f1.fld.cr.dbg_tim1_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM1_STOP"); + state->u.f1.fld.cr.dbg_tim2_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM2_STOP"); + state->u.f1.fld.cr.dbg_tim3_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM3_STOP"); + state->u.f1.fld.cr.dbg_tim4_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM4_STOP"); + state->u.f1.fld.cr.dbg_can1_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_CAN1_STOP"); + state->u.f1.fld.cr.dbg_i2c1_smbus_timeout = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_I2C1_SMBUS_TIMEOUT"); + state->u.f1.fld.cr.dbg_i2c2_smbus_timeout = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_I2C2_SMBUS_TIMEOUT"); + state->u.f1.fld.cr.dbg_tim8_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM8_STOP"); + state->u.f1.fld.cr.dbg_tim5_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM5_STOP"); + state->u.f1.fld.cr.dbg_tim6_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM6_STOP"); + state->u.f1.fld.cr.dbg_tim7_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM7_STOP"); + state->u.f1.fld.cr.dbg_can2_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_CAN2_STOP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dbg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dbg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dbg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dbg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dbg_is_enabled(Object *obj) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dbg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DBGState *state = STM32_DBG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dbg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DBG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DBGState *state = STM32_DBG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DBG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_dbg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dbg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_dbg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dbg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_dbg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DBGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dbg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DBG); +} + +static void stm32_dbg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dbg_reset_callback; + dc->realize = stm32_dbg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dbg_is_enabled; +} + +static const TypeInfo stm32_dbg_type_info = { + .name = TYPE_STM32_DBG, + .parent = TYPE_STM32_DBG_PARENT, + .instance_init = stm32_dbg_instance_init_callback, + .instance_size = sizeof(STM32DBGState), + .class_init = stm32_dbg_class_init_callback, + .class_size = sizeof(STM32DBGClass) }; + +static void stm32_dbg_register_types(void) +{ + type_register_static(&stm32_dbg_type_info); +} + +type_init(stm32_dbg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/dbg.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/dbg.h new file mode 100644 index 0000000000..a9a49c6e05 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/dbg.h @@ -0,0 +1,130 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DBG_H_ +#define STM32_DBG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DBG DEVICE_PATH_STM32 "DBG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DBG TYPE_STM32_PREFIX "dbg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DBG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DBGParentClass; +typedef PeripheralState STM32DBGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DBG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DBGClass, (obj), TYPE_STM32_DBG) +#define STM32_DBG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DBGClass, (klass), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentClass parent_class; + // public: + + // None, so far. +} STM32DBGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DBG_STATE(obj) \ + OBJECT_CHECK(STM32DBGState, (obj), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 DBG (Debug support) registers. + struct { + Object *idcode; // 0x0 (DBGMCU_IDCODE) + Object *cr; // 0x4 (DBGMCU_CR) + } reg; + + struct { + + // IDCODE (DBGMCU_IDCODE) bitfields. + struct { + Object *dev_id; // [0:11] DEV_ID + Object *rev_id; // [16:31] REV_ID + } idcode; + + // CR (DBGMCU_CR) bitfields. + struct { + Object *dbg_sleep; // [0:0] DBG_SLEEP + Object *dbg_stop; // [1:1] DBG_STOP + Object *dbg_standby; // [2:2] DBG_STANDBY + Object *trace_ioen; // [5:5] TRACE_IOEN + Object *trace_mode; // [6:7] TRACE_MODE + Object *dbg_iwdg_stop; // [8:8] DBG_IWDG_STOP + Object *dbg_wwdg_stop; // [9:9] DBG_WWDG_STOP + Object *dbg_tim1_stop; // [10:10] DBG_TIM1_STOP + Object *dbg_tim2_stop; // [11:11] DBG_TIM2_STOP + Object *dbg_tim3_stop; // [12:12] DBG_TIM3_STOP + Object *dbg_tim4_stop; // [13:13] DBG_TIM4_STOP + Object *dbg_can1_stop; // [14:14] DBG_CAN1_STOP + Object *dbg_i2c1_smbus_timeout; // [15:15] DBG_I2C1_SMBUS_TIMEOUT + Object *dbg_i2c2_smbus_timeout; // [16:16] DBG_I2C2_SMBUS_TIMEOUT + Object *dbg_tim8_stop; // [17:17] DBG_TIM8_STOP + Object *dbg_tim5_stop; // [18:18] DBG_TIM5_STOP + Object *dbg_tim6_stop; // [19:19] DBG_TIM6_STOP + Object *dbg_tim7_stop; // [20:20] DBG_TIM7_STOP + Object *dbg_can2_stop; // [21:21] DBG_CAN2_STOP + } cr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DBGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DBG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/dma1.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/dma1.c new file mode 100644 index 0000000000..fedc5fdb4c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/dma1.c @@ -0,0 +1,490 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f1.reg.ifcr = cm_object_get_child_by_name(obj, "IFCR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f1.reg.cndtr1 = cm_object_get_child_by_name(obj, "CNDTR1"); + state->u.f1.reg.cpar1 = cm_object_get_child_by_name(obj, "CPAR1"); + state->u.f1.reg.cmar1 = cm_object_get_child_by_name(obj, "CMAR1"); + state->u.f1.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f1.reg.cndtr2 = cm_object_get_child_by_name(obj, "CNDTR2"); + state->u.f1.reg.cpar2 = cm_object_get_child_by_name(obj, "CPAR2"); + state->u.f1.reg.cmar2 = cm_object_get_child_by_name(obj, "CMAR2"); + state->u.f1.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f1.reg.cndtr3 = cm_object_get_child_by_name(obj, "CNDTR3"); + state->u.f1.reg.cpar3 = cm_object_get_child_by_name(obj, "CPAR3"); + state->u.f1.reg.cmar3 = cm_object_get_child_by_name(obj, "CMAR3"); + state->u.f1.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f1.reg.cndtr4 = cm_object_get_child_by_name(obj, "CNDTR4"); + state->u.f1.reg.cpar4 = cm_object_get_child_by_name(obj, "CPAR4"); + state->u.f1.reg.cmar4 = cm_object_get_child_by_name(obj, "CMAR4"); + state->u.f1.reg.ccr5 = cm_object_get_child_by_name(obj, "CCR5"); + state->u.f1.reg.cndtr5 = cm_object_get_child_by_name(obj, "CNDTR5"); + state->u.f1.reg.cpar5 = cm_object_get_child_by_name(obj, "CPAR5"); + state->u.f1.reg.cmar5 = cm_object_get_child_by_name(obj, "CMAR5"); + state->u.f1.reg.ccr6 = cm_object_get_child_by_name(obj, "CCR6"); + state->u.f1.reg.cndtr6 = cm_object_get_child_by_name(obj, "CNDTR6"); + state->u.f1.reg.cpar6 = cm_object_get_child_by_name(obj, "CPAR6"); + state->u.f1.reg.cmar6 = cm_object_get_child_by_name(obj, "CMAR6"); + state->u.f1.reg.ccr7 = cm_object_get_child_by_name(obj, "CCR7"); + state->u.f1.reg.cndtr7 = cm_object_get_child_by_name(obj, "CNDTR7"); + state->u.f1.reg.cpar7 = cm_object_get_child_by_name(obj, "CPAR7"); + state->u.f1.reg.cmar7 = cm_object_get_child_by_name(obj, "CMAR7"); + + + // ISR bitfields. + state->u.f1.fld.isr.gif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF1"); + state->u.f1.fld.isr.tcif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF1"); + state->u.f1.fld.isr.htif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF1"); + state->u.f1.fld.isr.teif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF1"); + state->u.f1.fld.isr.gif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF2"); + state->u.f1.fld.isr.tcif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF2"); + state->u.f1.fld.isr.htif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF2"); + state->u.f1.fld.isr.teif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF2"); + state->u.f1.fld.isr.gif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF3"); + state->u.f1.fld.isr.tcif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF3"); + state->u.f1.fld.isr.htif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF3"); + state->u.f1.fld.isr.teif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF3"); + state->u.f1.fld.isr.gif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF4"); + state->u.f1.fld.isr.tcif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF4"); + state->u.f1.fld.isr.htif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF4"); + state->u.f1.fld.isr.teif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF4"); + state->u.f1.fld.isr.gif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF5"); + state->u.f1.fld.isr.tcif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF5"); + state->u.f1.fld.isr.htif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF5"); + state->u.f1.fld.isr.teif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF5"); + state->u.f1.fld.isr.gif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF6"); + state->u.f1.fld.isr.tcif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF6"); + state->u.f1.fld.isr.htif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF6"); + state->u.f1.fld.isr.teif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF6"); + state->u.f1.fld.isr.gif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF7"); + state->u.f1.fld.isr.tcif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF7"); + state->u.f1.fld.isr.htif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF7"); + state->u.f1.fld.isr.teif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF7"); + + // IFCR bitfields. + state->u.f1.fld.ifcr.cgif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF1"); + state->u.f1.fld.ifcr.ctcif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF1"); + state->u.f1.fld.ifcr.chtif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF1"); + state->u.f1.fld.ifcr.cteif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF1"); + state->u.f1.fld.ifcr.cgif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF2"); + state->u.f1.fld.ifcr.ctcif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF2"); + state->u.f1.fld.ifcr.chtif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF2"); + state->u.f1.fld.ifcr.cteif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF2"); + state->u.f1.fld.ifcr.cgif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF3"); + state->u.f1.fld.ifcr.ctcif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF3"); + state->u.f1.fld.ifcr.chtif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF3"); + state->u.f1.fld.ifcr.cteif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF3"); + state->u.f1.fld.ifcr.cgif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF4"); + state->u.f1.fld.ifcr.ctcif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF4"); + state->u.f1.fld.ifcr.chtif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF4"); + state->u.f1.fld.ifcr.cteif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF4"); + state->u.f1.fld.ifcr.cgif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF5"); + state->u.f1.fld.ifcr.ctcif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF5"); + state->u.f1.fld.ifcr.chtif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF5"); + state->u.f1.fld.ifcr.cteif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF5"); + state->u.f1.fld.ifcr.cgif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF6"); + state->u.f1.fld.ifcr.ctcif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF6"); + state->u.f1.fld.ifcr.chtif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF6"); + state->u.f1.fld.ifcr.cteif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF6"); + state->u.f1.fld.ifcr.cgif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF7"); + state->u.f1.fld.ifcr.ctcif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF7"); + state->u.f1.fld.ifcr.chtif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF7"); + state->u.f1.fld.ifcr.cteif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF7"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.en = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "EN"); + state->u.f1.fld.ccr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "TCIE"); + state->u.f1.fld.ccr1.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "HTIE"); + state->u.f1.fld.ccr1.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "TEIE"); + state->u.f1.fld.ccr1.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "DIR"); + state->u.f1.fld.ccr1.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CIRC"); + state->u.f1.fld.ccr1.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "PINC"); + state->u.f1.fld.ccr1.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "MINC"); + state->u.f1.fld.ccr1.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "PSIZE"); + state->u.f1.fld.ccr1.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "MSIZE"); + state->u.f1.fld.ccr1.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "PL"); + state->u.f1.fld.ccr1.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "MEM2MEM"); + + // CNDTR1 bitfields. + state->u.f1.fld.cndtr1.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr1, "NDT"); + + // CPAR1 bitfields. + state->u.f1.fld.cpar1.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar1, "PA"); + + // CMAR1 bitfields. + state->u.f1.fld.cmar1.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar1, "MA"); + + // CCR2 bitfields. + state->u.f1.fld.ccr2.en = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "EN"); + state->u.f1.fld.ccr2.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "TCIE"); + state->u.f1.fld.ccr2.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "HTIE"); + state->u.f1.fld.ccr2.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "TEIE"); + state->u.f1.fld.ccr2.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "DIR"); + state->u.f1.fld.ccr2.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "CIRC"); + state->u.f1.fld.ccr2.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "PINC"); + state->u.f1.fld.ccr2.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "MINC"); + state->u.f1.fld.ccr2.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "PSIZE"); + state->u.f1.fld.ccr2.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "MSIZE"); + state->u.f1.fld.ccr2.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "PL"); + state->u.f1.fld.ccr2.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "MEM2MEM"); + + // CNDTR2 bitfields. + state->u.f1.fld.cndtr2.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr2, "NDT"); + + // CPAR2 bitfields. + state->u.f1.fld.cpar2.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar2, "PA"); + + // CMAR2 bitfields. + state->u.f1.fld.cmar2.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar2, "MA"); + + // CCR3 bitfields. + state->u.f1.fld.ccr3.en = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "EN"); + state->u.f1.fld.ccr3.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "TCIE"); + state->u.f1.fld.ccr3.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "HTIE"); + state->u.f1.fld.ccr3.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "TEIE"); + state->u.f1.fld.ccr3.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "DIR"); + state->u.f1.fld.ccr3.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "CIRC"); + state->u.f1.fld.ccr3.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "PINC"); + state->u.f1.fld.ccr3.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "MINC"); + state->u.f1.fld.ccr3.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "PSIZE"); + state->u.f1.fld.ccr3.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "MSIZE"); + state->u.f1.fld.ccr3.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "PL"); + state->u.f1.fld.ccr3.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "MEM2MEM"); + + // CNDTR3 bitfields. + state->u.f1.fld.cndtr3.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr3, "NDT"); + + // CPAR3 bitfields. + state->u.f1.fld.cpar3.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar3, "PA"); + + // CMAR3 bitfields. + state->u.f1.fld.cmar3.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar3, "MA"); + + // CCR4 bitfields. + state->u.f1.fld.ccr4.en = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "EN"); + state->u.f1.fld.ccr4.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "TCIE"); + state->u.f1.fld.ccr4.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "HTIE"); + state->u.f1.fld.ccr4.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "TEIE"); + state->u.f1.fld.ccr4.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "DIR"); + state->u.f1.fld.ccr4.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "CIRC"); + state->u.f1.fld.ccr4.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "PINC"); + state->u.f1.fld.ccr4.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "MINC"); + state->u.f1.fld.ccr4.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "PSIZE"); + state->u.f1.fld.ccr4.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "MSIZE"); + state->u.f1.fld.ccr4.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "PL"); + state->u.f1.fld.ccr4.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "MEM2MEM"); + + // CNDTR4 bitfields. + state->u.f1.fld.cndtr4.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr4, "NDT"); + + // CPAR4 bitfields. + state->u.f1.fld.cpar4.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar4, "PA"); + + // CMAR4 bitfields. + state->u.f1.fld.cmar4.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar4, "MA"); + + // CCR5 bitfields. + state->u.f1.fld.ccr5.en = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "EN"); + state->u.f1.fld.ccr5.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "TCIE"); + state->u.f1.fld.ccr5.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "HTIE"); + state->u.f1.fld.ccr5.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "TEIE"); + state->u.f1.fld.ccr5.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "DIR"); + state->u.f1.fld.ccr5.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "CIRC"); + state->u.f1.fld.ccr5.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "PINC"); + state->u.f1.fld.ccr5.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "MINC"); + state->u.f1.fld.ccr5.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "PSIZE"); + state->u.f1.fld.ccr5.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "MSIZE"); + state->u.f1.fld.ccr5.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "PL"); + state->u.f1.fld.ccr5.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "MEM2MEM"); + + // CNDTR5 bitfields. + state->u.f1.fld.cndtr5.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr5, "NDT"); + + // CPAR5 bitfields. + state->u.f1.fld.cpar5.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar5, "PA"); + + // CMAR5 bitfields. + state->u.f1.fld.cmar5.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar5, "MA"); + + // CCR6 bitfields. + state->u.f1.fld.ccr6.en = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "EN"); + state->u.f1.fld.ccr6.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "TCIE"); + state->u.f1.fld.ccr6.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "HTIE"); + state->u.f1.fld.ccr6.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "TEIE"); + state->u.f1.fld.ccr6.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "DIR"); + state->u.f1.fld.ccr6.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "CIRC"); + state->u.f1.fld.ccr6.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "PINC"); + state->u.f1.fld.ccr6.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "MINC"); + state->u.f1.fld.ccr6.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "PSIZE"); + state->u.f1.fld.ccr6.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "MSIZE"); + state->u.f1.fld.ccr6.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "PL"); + state->u.f1.fld.ccr6.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "MEM2MEM"); + + // CNDTR6 bitfields. + state->u.f1.fld.cndtr6.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr6, "NDT"); + + // CPAR6 bitfields. + state->u.f1.fld.cpar6.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar6, "PA"); + + // CMAR6 bitfields. + state->u.f1.fld.cmar6.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar6, "MA"); + + // CCR7 bitfields. + state->u.f1.fld.ccr7.en = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "EN"); + state->u.f1.fld.ccr7.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "TCIE"); + state->u.f1.fld.ccr7.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "HTIE"); + state->u.f1.fld.ccr7.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "TEIE"); + state->u.f1.fld.ccr7.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "DIR"); + state->u.f1.fld.ccr7.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "CIRC"); + state->u.f1.fld.ccr7.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "PINC"); + state->u.f1.fld.ccr7.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "MINC"); + state->u.f1.fld.ccr7.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "PSIZE"); + state->u.f1.fld.ccr7.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "MSIZE"); + state->u.f1.fld.ccr7.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "PL"); + state->u.f1.fld.ccr7.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "MEM2MEM"); + + // CNDTR7 bitfields. + state->u.f1.fld.cndtr7.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr7, "NDT"); + + // CPAR7 bitfields. + state->u.f1.fld.cpar7.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar7, "PA"); + + // CMAR7 bitfields. + state->u.f1.fld.cmar7.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar7, "MA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma_is_enabled(Object *obj) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMAState *state = STM32_DMA_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_DMA_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMAState *state = STM32_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA%dEN", + 1 + state->port_index - STM32_PORT_DMA1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA); +} + +static void stm32_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma_reset_callback; + dc->realize = stm32_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma_is_enabled; +} + +static const TypeInfo stm32_dma_type_info = { + .name = TYPE_STM32_DMA, + .parent = TYPE_STM32_DMA_PARENT, + .instance_init = stm32_dma_instance_init_callback, + .instance_size = sizeof(STM32DMAState), + .class_init = stm32_dma_class_init_callback, + .class_size = sizeof(STM32DMAClass) }; + +static void stm32_dma_register_types(void) +{ + type_register_static(&stm32_dma_type_info); +} + +type_init(stm32_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/dma1.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/dma1.h new file mode 100644 index 0000000000..bdc4d98c43 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/dma1.h @@ -0,0 +1,421 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA_H_ +#define STM32_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMA DEVICE_PATH_STM32 "DMA" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_DMA1, + STM32_PORT_DMA2, + STM32_PORT_DMA_UNDEFINED = 0xFF, +} stm32_dma_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMA TYPE_STM32_PREFIX "dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMAParentClass; +typedef PeripheralState STM32DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMAClass, (obj), TYPE_STM32_DMA) +#define STM32_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMAClass, (klass), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentClass parent_class; + // public: + + // None, so far. +} STM32DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA_STATE(obj) \ + OBJECT_CHECK(STM32DMAState, (obj), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_dma_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 DMA (DMA controller) registers. + struct { + Object *isr; // 0x0 (DMA interrupt status register (DMA_ISR)) + Object *ifcr; // 0x4 (DMA interrupt flag clear register (DMA_IFCR)) + Object *ccr1; // 0x8 (DMA channel configuration register (DMA_CCR)) + Object *cndtr1; // 0xC (DMA channel 1 number of data register) + Object *cpar1; // 0x10 (DMA channel 1 peripheral address register) + Object *cmar1; // 0x14 (DMA channel 1 memory address register) + Object *ccr2; // 0x1C (DMA channel configuration register (DMA_CCR)) + Object *cndtr2; // 0x20 (DMA channel 2 number of data register) + Object *cpar2; // 0x24 (DMA channel 2 peripheral address register) + Object *cmar2; // 0x28 (DMA channel 2 memory address register) + Object *ccr3; // 0x30 (DMA channel configuration register (DMA_CCR)) + Object *cndtr3; // 0x34 (DMA channel 3 number of data register) + Object *cpar3; // 0x38 (DMA channel 3 peripheral address register) + Object *cmar3; // 0x3C (DMA channel 3 memory address register) + Object *ccr4; // 0x44 (DMA channel configuration register (DMA_CCR)) + Object *cndtr4; // 0x48 (DMA channel 4 number of data register) + Object *cpar4; // 0x4C (DMA channel 4 peripheral address register) + Object *cmar4; // 0x50 (DMA channel 4 memory address register) + Object *ccr5; // 0x58 (DMA channel configuration register (DMA_CCR)) + Object *cndtr5; // 0x5C (DMA channel 5 number of data register) + Object *cpar5; // 0x60 (DMA channel 5 peripheral address register) + Object *cmar5; // 0x64 (DMA channel 5 memory address register) + Object *ccr6; // 0x6C (DMA channel configuration register (DMA_CCR)) + Object *cndtr6; // 0x70 (DMA channel 6 number of data register) + Object *cpar6; // 0x74 (DMA channel 6 peripheral address register) + Object *cmar6; // 0x78 (DMA channel 6 memory address register) + Object *ccr7; // 0x80 (DMA channel configuration register (DMA_CCR)) + Object *cndtr7; // 0x84 (DMA channel 7 number of data register) + Object *cpar7; // 0x88 (DMA channel 7 peripheral address register) + Object *cmar7; // 0x8C (DMA channel 7 memory address register) + } reg; + + struct { + + // ISR (DMA interrupt status register (DMA_ISR)) bitfields. + struct { + Object *gif1; // [0:0] Channel 1 Global interrupt flag + Object *tcif1; // [1:1] Channel 1 Transfer Complete flag + Object *htif1; // [2:2] Channel 1 Half Transfer Complete flag + Object *teif1; // [3:3] Channel 1 Transfer Error flag + Object *gif2; // [4:4] Channel 2 Global interrupt flag + Object *tcif2; // [5:5] Channel 2 Transfer Complete flag + Object *htif2; // [6:6] Channel 2 Half Transfer Complete flag + Object *teif2; // [7:7] Channel 2 Transfer Error flag + Object *gif3; // [8:8] Channel 3 Global interrupt flag + Object *tcif3; // [9:9] Channel 3 Transfer Complete flag + Object *htif3; // [10:10] Channel 3 Half Transfer Complete flag + Object *teif3; // [11:11] Channel 3 Transfer Error flag + Object *gif4; // [12:12] Channel 4 Global interrupt flag + Object *tcif4; // [13:13] Channel 4 Transfer Complete flag + Object *htif4; // [14:14] Channel 4 Half Transfer Complete flag + Object *teif4; // [15:15] Channel 4 Transfer Error flag + Object *gif5; // [16:16] Channel 5 Global interrupt flag + Object *tcif5; // [17:17] Channel 5 Transfer Complete flag + Object *htif5; // [18:18] Channel 5 Half Transfer Complete flag + Object *teif5; // [19:19] Channel 5 Transfer Error flag + Object *gif6; // [20:20] Channel 6 Global interrupt flag + Object *tcif6; // [21:21] Channel 6 Transfer Complete flag + Object *htif6; // [22:22] Channel 6 Half Transfer Complete flag + Object *teif6; // [23:23] Channel 6 Transfer Error flag + Object *gif7; // [24:24] Channel 7 Global interrupt flag + Object *tcif7; // [25:25] Channel 7 Transfer Complete flag + Object *htif7; // [26:26] Channel 7 Half Transfer Complete flag + Object *teif7; // [27:27] Channel 7 Transfer Error flag + } isr; + + // IFCR (DMA interrupt flag clear register (DMA_IFCR)) bitfields. + struct { + Object *cgif1; // [0:0] Channel 1 Global interrupt clear + Object *ctcif1; // [1:1] Channel 1 Transfer Complete clear + Object *chtif1; // [2:2] Channel 1 Half Transfer clear + Object *cteif1; // [3:3] Channel 1 Transfer Error clear + Object *cgif2; // [4:4] Channel 2 Global interrupt clear + Object *ctcif2; // [5:5] Channel 2 Transfer Complete clear + Object *chtif2; // [6:6] Channel 2 Half Transfer clear + Object *cteif2; // [7:7] Channel 2 Transfer Error clear + Object *cgif3; // [8:8] Channel 3 Global interrupt clear + Object *ctcif3; // [9:9] Channel 3 Transfer Complete clear + Object *chtif3; // [10:10] Channel 3 Half Transfer clear + Object *cteif3; // [11:11] Channel 3 Transfer Error clear + Object *cgif4; // [12:12] Channel 4 Global interrupt clear + Object *ctcif4; // [13:13] Channel 4 Transfer Complete clear + Object *chtif4; // [14:14] Channel 4 Half Transfer clear + Object *cteif4; // [15:15] Channel 4 Transfer Error clear + Object *cgif5; // [16:16] Channel 5 Global interrupt clear + Object *ctcif5; // [17:17] Channel 5 Transfer Complete clear + Object *chtif5; // [18:18] Channel 5 Half Transfer clear + Object *cteif5; // [19:19] Channel 5 Transfer Error clear + Object *cgif6; // [20:20] Channel 6 Global interrupt clear + Object *ctcif6; // [21:21] Channel 6 Transfer Complete clear + Object *chtif6; // [22:22] Channel 6 Half Transfer clear + Object *cteif6; // [23:23] Channel 6 Transfer Error clear + Object *cgif7; // [24:24] Channel 7 Global interrupt clear + Object *ctcif7; // [25:25] Channel 7 Transfer Complete clear + Object *chtif7; // [26:26] Channel 7 Half Transfer clear + Object *cteif7; // [27:27] Channel 7 Transfer Error clear + } ifcr; + + // CCR1 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr1; + + // CNDTR1 (DMA channel 1 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr1; + + // CPAR1 (DMA channel 1 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar1; + + // CMAR1 (DMA channel 1 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar1; + + // CCR2 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr2; + + // CNDTR2 (DMA channel 2 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr2; + + // CPAR2 (DMA channel 2 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar2; + + // CMAR2 (DMA channel 2 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar2; + + // CCR3 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr3; + + // CNDTR3 (DMA channel 3 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr3; + + // CPAR3 (DMA channel 3 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar3; + + // CMAR3 (DMA channel 3 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar3; + + // CCR4 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr4; + + // CNDTR4 (DMA channel 4 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr4; + + // CPAR4 (DMA channel 4 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar4; + + // CMAR4 (DMA channel 4 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar4; + + // CCR5 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr5; + + // CNDTR5 (DMA channel 5 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr5; + + // CPAR5 (DMA channel 5 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar5; + + // CMAR5 (DMA channel 5 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar5; + + // CCR6 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr6; + + // CNDTR6 (DMA channel 6 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr6; + + // CPAR6 (DMA channel 6 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar6; + + // CMAR6 (DMA channel 6 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar6; + + // CCR7 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr7; + + // CNDTR7 (DMA channel 7 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr7; + + // CPAR7 (DMA channel 7 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar7; + + // CMAR7 (DMA channel 7 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar7; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/exti.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/exti.c new file mode 100644 index 0000000000..1439288187 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/exti.c @@ -0,0 +1,366 @@ +/* + * STM32 - EXTI (EXTI) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_exti_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.imr = cm_object_get_child_by_name(obj, "IMR"); + state->u.f1.reg.emr = cm_object_get_child_by_name(obj, "EMR"); + state->u.f1.reg.rtsr = cm_object_get_child_by_name(obj, "RTSR"); + state->u.f1.reg.ftsr = cm_object_get_child_by_name(obj, "FTSR"); + state->u.f1.reg.swier = cm_object_get_child_by_name(obj, "SWIER"); + state->u.f1.reg.pr = cm_object_get_child_by_name(obj, "PR"); + + + // IMR bitfields. + state->u.f1.fld.imr.mr0 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR0"); + state->u.f1.fld.imr.mr1 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR1"); + state->u.f1.fld.imr.mr2 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR2"); + state->u.f1.fld.imr.mr3 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR3"); + state->u.f1.fld.imr.mr4 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR4"); + state->u.f1.fld.imr.mr5 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR5"); + state->u.f1.fld.imr.mr6 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR6"); + state->u.f1.fld.imr.mr7 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR7"); + state->u.f1.fld.imr.mr8 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR8"); + state->u.f1.fld.imr.mr9 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR9"); + state->u.f1.fld.imr.mr10 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR10"); + state->u.f1.fld.imr.mr11 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR11"); + state->u.f1.fld.imr.mr12 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR12"); + state->u.f1.fld.imr.mr13 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR13"); + state->u.f1.fld.imr.mr14 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR14"); + state->u.f1.fld.imr.mr15 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR15"); + state->u.f1.fld.imr.mr16 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR16"); + state->u.f1.fld.imr.mr17 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR17"); + state->u.f1.fld.imr.mr18 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR18"); + + // EMR bitfields. + state->u.f1.fld.emr.mr0 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR0"); + state->u.f1.fld.emr.mr1 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR1"); + state->u.f1.fld.emr.mr2 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR2"); + state->u.f1.fld.emr.mr3 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR3"); + state->u.f1.fld.emr.mr4 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR4"); + state->u.f1.fld.emr.mr5 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR5"); + state->u.f1.fld.emr.mr6 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR6"); + state->u.f1.fld.emr.mr7 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR7"); + state->u.f1.fld.emr.mr8 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR8"); + state->u.f1.fld.emr.mr9 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR9"); + state->u.f1.fld.emr.mr10 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR10"); + state->u.f1.fld.emr.mr11 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR11"); + state->u.f1.fld.emr.mr12 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR12"); + state->u.f1.fld.emr.mr13 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR13"); + state->u.f1.fld.emr.mr14 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR14"); + state->u.f1.fld.emr.mr15 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR15"); + state->u.f1.fld.emr.mr16 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR16"); + state->u.f1.fld.emr.mr17 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR17"); + state->u.f1.fld.emr.mr18 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR18"); + + // RTSR bitfields. + state->u.f1.fld.rtsr.tr0 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR0"); + state->u.f1.fld.rtsr.tr1 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR1"); + state->u.f1.fld.rtsr.tr2 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR2"); + state->u.f1.fld.rtsr.tr3 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR3"); + state->u.f1.fld.rtsr.tr4 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR4"); + state->u.f1.fld.rtsr.tr5 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR5"); + state->u.f1.fld.rtsr.tr6 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR6"); + state->u.f1.fld.rtsr.tr7 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR7"); + state->u.f1.fld.rtsr.tr8 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR8"); + state->u.f1.fld.rtsr.tr9 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR9"); + state->u.f1.fld.rtsr.tr10 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR10"); + state->u.f1.fld.rtsr.tr11 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR11"); + state->u.f1.fld.rtsr.tr12 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR12"); + state->u.f1.fld.rtsr.tr13 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR13"); + state->u.f1.fld.rtsr.tr14 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR14"); + state->u.f1.fld.rtsr.tr15 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR15"); + state->u.f1.fld.rtsr.tr16 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR16"); + state->u.f1.fld.rtsr.tr17 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR17"); + state->u.f1.fld.rtsr.tr18 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR18"); + + // FTSR bitfields. + state->u.f1.fld.ftsr.tr0 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR0"); + state->u.f1.fld.ftsr.tr1 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR1"); + state->u.f1.fld.ftsr.tr2 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR2"); + state->u.f1.fld.ftsr.tr3 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR3"); + state->u.f1.fld.ftsr.tr4 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR4"); + state->u.f1.fld.ftsr.tr5 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR5"); + state->u.f1.fld.ftsr.tr6 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR6"); + state->u.f1.fld.ftsr.tr7 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR7"); + state->u.f1.fld.ftsr.tr8 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR8"); + state->u.f1.fld.ftsr.tr9 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR9"); + state->u.f1.fld.ftsr.tr10 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR10"); + state->u.f1.fld.ftsr.tr11 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR11"); + state->u.f1.fld.ftsr.tr12 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR12"); + state->u.f1.fld.ftsr.tr13 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR13"); + state->u.f1.fld.ftsr.tr14 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR14"); + state->u.f1.fld.ftsr.tr15 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR15"); + state->u.f1.fld.ftsr.tr16 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR16"); + state->u.f1.fld.ftsr.tr17 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR17"); + state->u.f1.fld.ftsr.tr18 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR18"); + + // SWIER bitfields. + state->u.f1.fld.swier.swier0 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER0"); + state->u.f1.fld.swier.swier1 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER1"); + state->u.f1.fld.swier.swier2 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER2"); + state->u.f1.fld.swier.swier3 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER3"); + state->u.f1.fld.swier.swier4 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER4"); + state->u.f1.fld.swier.swier5 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER5"); + state->u.f1.fld.swier.swier6 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER6"); + state->u.f1.fld.swier.swier7 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER7"); + state->u.f1.fld.swier.swier8 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER8"); + state->u.f1.fld.swier.swier9 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER9"); + state->u.f1.fld.swier.swier10 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER10"); + state->u.f1.fld.swier.swier11 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER11"); + state->u.f1.fld.swier.swier12 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER12"); + state->u.f1.fld.swier.swier13 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER13"); + state->u.f1.fld.swier.swier14 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER14"); + state->u.f1.fld.swier.swier15 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER15"); + state->u.f1.fld.swier.swier16 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER16"); + state->u.f1.fld.swier.swier17 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER17"); + state->u.f1.fld.swier.swier18 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER18"); + + // PR bitfields. + state->u.f1.fld.pr.pr0 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR0"); + state->u.f1.fld.pr.pr1 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR1"); + state->u.f1.fld.pr.pr2 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR2"); + state->u.f1.fld.pr.pr3 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR3"); + state->u.f1.fld.pr.pr4 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR4"); + state->u.f1.fld.pr.pr5 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR5"); + state->u.f1.fld.pr.pr6 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR6"); + state->u.f1.fld.pr.pr7 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR7"); + state->u.f1.fld.pr.pr8 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR8"); + state->u.f1.fld.pr.pr9 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR9"); + state->u.f1.fld.pr.pr10 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR10"); + state->u.f1.fld.pr.pr11 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR11"); + state->u.f1.fld.pr.pr12 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR12"); + state->u.f1.fld.pr.pr13 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR13"); + state->u.f1.fld.pr.pr14 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR14"); + state->u.f1.fld.pr.pr15 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR15"); + state->u.f1.fld.pr.pr16 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR16"); + state->u.f1.fld.pr.pr17 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR17"); + state->u.f1.fld.pr.pr18 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR18"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_exti_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_exti_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_exti_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_exti_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_exti_is_enabled(Object *obj) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_exti_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_exti_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_EXTI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32EXTIState *state = STM32_EXTI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "EXTI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_exti_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_exti_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_exti_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_exti_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_exti_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/EXTIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_exti_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_EXTI); +} + +static void stm32_exti_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_exti_reset_callback; + dc->realize = stm32_exti_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_exti_is_enabled; +} + +static const TypeInfo stm32_exti_type_info = { + .name = TYPE_STM32_EXTI, + .parent = TYPE_STM32_EXTI_PARENT, + .instance_init = stm32_exti_instance_init_callback, + .instance_size = sizeof(STM32EXTIState), + .class_init = stm32_exti_class_init_callback, + .class_size = sizeof(STM32EXTIClass) }; + +static void stm32_exti_register_types(void) +{ + type_register_static(&stm32_exti_type_info); +} + +type_init(stm32_exti_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/exti.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/exti.h new file mode 100644 index 0000000000..345aa0ddcc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/exti.h @@ -0,0 +1,243 @@ +/* + * STM32 - EXTI (EXTI) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_EXTI_H_ +#define STM32_EXTI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_EXTI DEVICE_PATH_STM32 "EXTI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_EXTI TYPE_STM32_PREFIX "exti" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_EXTI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32EXTIParentClass; +typedef PeripheralState STM32EXTIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_EXTI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32EXTIClass, (obj), TYPE_STM32_EXTI) +#define STM32_EXTI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32EXTIClass, (klass), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentClass parent_class; + // public: + + // None, so far. +} STM32EXTIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_EXTI_STATE(obj) \ + OBJECT_CHECK(STM32EXTIState, (obj), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 EXTI (EXTI) registers. + struct { + Object *imr; // 0x0 (Interrupt mask register (EXTI_IMR)) + Object *emr; // 0x4 (Event mask register (EXTI_EMR)) + Object *rtsr; // 0x8 (Rising Trigger selection register (EXTI_RTSR)) + Object *ftsr; // 0xC (Falling Trigger selection register (EXTI_FTSR)) + Object *swier; // 0x10 (Software interrupt event register (EXTI_SWIER)) + Object *pr; // 0x14 (Pending register (EXTI_PR)) + } reg; + + struct { + + // IMR (Interrupt mask register (EXTI_IMR)) bitfields. + struct { + Object *mr0; // [0:0] Interrupt Mask on line 0 + Object *mr1; // [1:1] Interrupt Mask on line 1 + Object *mr2; // [2:2] Interrupt Mask on line 2 + Object *mr3; // [3:3] Interrupt Mask on line 3 + Object *mr4; // [4:4] Interrupt Mask on line 4 + Object *mr5; // [5:5] Interrupt Mask on line 5 + Object *mr6; // [6:6] Interrupt Mask on line 6 + Object *mr7; // [7:7] Interrupt Mask on line 7 + Object *mr8; // [8:8] Interrupt Mask on line 8 + Object *mr9; // [9:9] Interrupt Mask on line 9 + Object *mr10; // [10:10] Interrupt Mask on line 10 + Object *mr11; // [11:11] Interrupt Mask on line 11 + Object *mr12; // [12:12] Interrupt Mask on line 12 + Object *mr13; // [13:13] Interrupt Mask on line 13 + Object *mr14; // [14:14] Interrupt Mask on line 14 + Object *mr15; // [15:15] Interrupt Mask on line 15 + Object *mr16; // [16:16] Interrupt Mask on line 16 + Object *mr17; // [17:17] Interrupt Mask on line 17 + Object *mr18; // [18:18] Interrupt Mask on line 18 + } imr; + + // EMR (Event mask register (EXTI_EMR)) bitfields. + struct { + Object *mr0; // [0:0] Event Mask on line 0 + Object *mr1; // [1:1] Event Mask on line 1 + Object *mr2; // [2:2] Event Mask on line 2 + Object *mr3; // [3:3] Event Mask on line 3 + Object *mr4; // [4:4] Event Mask on line 4 + Object *mr5; // [5:5] Event Mask on line 5 + Object *mr6; // [6:6] Event Mask on line 6 + Object *mr7; // [7:7] Event Mask on line 7 + Object *mr8; // [8:8] Event Mask on line 8 + Object *mr9; // [9:9] Event Mask on line 9 + Object *mr10; // [10:10] Event Mask on line 10 + Object *mr11; // [11:11] Event Mask on line 11 + Object *mr12; // [12:12] Event Mask on line 12 + Object *mr13; // [13:13] Event Mask on line 13 + Object *mr14; // [14:14] Event Mask on line 14 + Object *mr15; // [15:15] Event Mask on line 15 + Object *mr16; // [16:16] Event Mask on line 16 + Object *mr17; // [17:17] Event Mask on line 17 + Object *mr18; // [18:18] Event Mask on line 18 + } emr; + + // RTSR (Rising Trigger selection register (EXTI_RTSR)) bitfields. + struct { + Object *tr0; // [0:0] Rising trigger event configuration of line 0 + Object *tr1; // [1:1] Rising trigger event configuration of line 1 + Object *tr2; // [2:2] Rising trigger event configuration of line 2 + Object *tr3; // [3:3] Rising trigger event configuration of line 3 + Object *tr4; // [4:4] Rising trigger event configuration of line 4 + Object *tr5; // [5:5] Rising trigger event configuration of line 5 + Object *tr6; // [6:6] Rising trigger event configuration of line 6 + Object *tr7; // [7:7] Rising trigger event configuration of line 7 + Object *tr8; // [8:8] Rising trigger event configuration of line 8 + Object *tr9; // [9:9] Rising trigger event configuration of line 9 + Object *tr10; // [10:10] Rising trigger event configuration of line 10 + Object *tr11; // [11:11] Rising trigger event configuration of line 11 + Object *tr12; // [12:12] Rising trigger event configuration of line 12 + Object *tr13; // [13:13] Rising trigger event configuration of line 13 + Object *tr14; // [14:14] Rising trigger event configuration of line 14 + Object *tr15; // [15:15] Rising trigger event configuration of line 15 + Object *tr16; // [16:16] Rising trigger event configuration of line 16 + Object *tr17; // [17:17] Rising trigger event configuration of line 17 + Object *tr18; // [18:18] Rising trigger event configuration of line 18 + } rtsr; + + // FTSR (Falling Trigger selection register (EXTI_FTSR)) bitfields. + struct { + Object *tr0; // [0:0] Falling trigger event configuration of line 0 + Object *tr1; // [1:1] Falling trigger event configuration of line 1 + Object *tr2; // [2:2] Falling trigger event configuration of line 2 + Object *tr3; // [3:3] Falling trigger event configuration of line 3 + Object *tr4; // [4:4] Falling trigger event configuration of line 4 + Object *tr5; // [5:5] Falling trigger event configuration of line 5 + Object *tr6; // [6:6] Falling trigger event configuration of line 6 + Object *tr7; // [7:7] Falling trigger event configuration of line 7 + Object *tr8; // [8:8] Falling trigger event configuration of line 8 + Object *tr9; // [9:9] Falling trigger event configuration of line 9 + Object *tr10; // [10:10] Falling trigger event configuration of line 10 + Object *tr11; // [11:11] Falling trigger event configuration of line 11 + Object *tr12; // [12:12] Falling trigger event configuration of line 12 + Object *tr13; // [13:13] Falling trigger event configuration of line 13 + Object *tr14; // [14:14] Falling trigger event configuration of line 14 + Object *tr15; // [15:15] Falling trigger event configuration of line 15 + Object *tr16; // [16:16] Falling trigger event configuration of line 16 + Object *tr17; // [17:17] Falling trigger event configuration of line 17 + Object *tr18; // [18:18] Falling trigger event configuration of line 18 + } ftsr; + + // SWIER (Software interrupt event register (EXTI_SWIER)) bitfields. + struct { + Object *swier0; // [0:0] Software Interrupt on line 0 + Object *swier1; // [1:1] Software Interrupt on line 1 + Object *swier2; // [2:2] Software Interrupt on line 2 + Object *swier3; // [3:3] Software Interrupt on line 3 + Object *swier4; // [4:4] Software Interrupt on line 4 + Object *swier5; // [5:5] Software Interrupt on line 5 + Object *swier6; // [6:6] Software Interrupt on line 6 + Object *swier7; // [7:7] Software Interrupt on line 7 + Object *swier8; // [8:8] Software Interrupt on line 8 + Object *swier9; // [9:9] Software Interrupt on line 9 + Object *swier10; // [10:10] Software Interrupt on line 10 + Object *swier11; // [11:11] Software Interrupt on line 11 + Object *swier12; // [12:12] Software Interrupt on line 12 + Object *swier13; // [13:13] Software Interrupt on line 13 + Object *swier14; // [14:14] Software Interrupt on line 14 + Object *swier15; // [15:15] Software Interrupt on line 15 + Object *swier16; // [16:16] Software Interrupt on line 16 + Object *swier17; // [17:17] Software Interrupt on line 17 + Object *swier18; // [18:18] Software Interrupt on line 18 + } swier; + + // PR (Pending register (EXTI_PR)) bitfields. + struct { + Object *pr0; // [0:0] Pending bit 0 + Object *pr1; // [1:1] Pending bit 1 + Object *pr2; // [2:2] Pending bit 2 + Object *pr3; // [3:3] Pending bit 3 + Object *pr4; // [4:4] Pending bit 4 + Object *pr5; // [5:5] Pending bit 5 + Object *pr6; // [6:6] Pending bit 6 + Object *pr7; // [7:7] Pending bit 7 + Object *pr8; // [8:8] Pending bit 8 + Object *pr9; // [9:9] Pending bit 9 + Object *pr10; // [10:10] Pending bit 10 + Object *pr11; // [11:11] Pending bit 11 + Object *pr12; // [12:12] Pending bit 12 + Object *pr13; // [13:13] Pending bit 13 + Object *pr14; // [14:14] Pending bit 14 + Object *pr15; // [15:15] Pending bit 15 + Object *pr16; // [16:16] Pending bit 16 + Object *pr17; // [17:17] Pending bit 17 + Object *pr18; // [18:18] Pending bit 18 + } pr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32EXTIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_EXTI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/flash.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/flash.c new file mode 100644 index 0000000000..03423f5922 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/flash.c @@ -0,0 +1,287 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_flash_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.acr = cm_object_get_child_by_name(obj, "ACR"); + state->u.f1.reg.keyr = cm_object_get_child_by_name(obj, "KEYR"); + state->u.f1.reg.optkeyr = cm_object_get_child_by_name(obj, "OPTKEYR"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.ar = cm_object_get_child_by_name(obj, "AR"); + state->u.f1.reg.obr = cm_object_get_child_by_name(obj, "OBR"); + state->u.f1.reg.wrpr = cm_object_get_child_by_name(obj, "WRPR"); + + + // ACR bitfields. + state->u.f1.fld.acr.latency = cm_object_get_child_by_name(state->u.f1.reg.acr, "LATENCY"); + state->u.f1.fld.acr.hlfcya = cm_object_get_child_by_name(state->u.f1.reg.acr, "HLFCYA"); + state->u.f1.fld.acr.prftbe = cm_object_get_child_by_name(state->u.f1.reg.acr, "PRFTBE"); + state->u.f1.fld.acr.prftbs = cm_object_get_child_by_name(state->u.f1.reg.acr, "PRFTBS"); + + // KEYR bitfields. + state->u.f1.fld.keyr.key = cm_object_get_child_by_name(state->u.f1.reg.keyr, "KEY"); + + // OPTKEYR bitfields. + state->u.f1.fld.optkeyr.optkey = cm_object_get_child_by_name(state->u.f1.reg.optkeyr, "OPTKEY"); + + // SR bitfields. + state->u.f1.fld.sr.bsy = cm_object_get_child_by_name(state->u.f1.reg.sr, "BSY"); + state->u.f1.fld.sr.pgerr = cm_object_get_child_by_name(state->u.f1.reg.sr, "PGERR"); + state->u.f1.fld.sr.wrprterr = cm_object_get_child_by_name(state->u.f1.reg.sr, "WRPRTERR"); + state->u.f1.fld.sr.eop = cm_object_get_child_by_name(state->u.f1.reg.sr, "EOP"); + + // CR bitfields. + state->u.f1.fld.cr.pg = cm_object_get_child_by_name(state->u.f1.reg.cr, "PG"); + state->u.f1.fld.cr.per = cm_object_get_child_by_name(state->u.f1.reg.cr, "PER"); + state->u.f1.fld.cr.mer = cm_object_get_child_by_name(state->u.f1.reg.cr, "MER"); + state->u.f1.fld.cr.optpg = cm_object_get_child_by_name(state->u.f1.reg.cr, "OPTPG"); + state->u.f1.fld.cr.opter = cm_object_get_child_by_name(state->u.f1.reg.cr, "OPTER"); + state->u.f1.fld.cr.strt = cm_object_get_child_by_name(state->u.f1.reg.cr, "STRT"); + state->u.f1.fld.cr.lock = cm_object_get_child_by_name(state->u.f1.reg.cr, "LOCK"); + state->u.f1.fld.cr.optwre = cm_object_get_child_by_name(state->u.f1.reg.cr, "OPTWRE"); + state->u.f1.fld.cr.errie = cm_object_get_child_by_name(state->u.f1.reg.cr, "ERRIE"); + state->u.f1.fld.cr.eopie = cm_object_get_child_by_name(state->u.f1.reg.cr, "EOPIE"); + + // AR bitfields. + state->u.f1.fld.ar.far_ = cm_object_get_child_by_name(state->u.f1.reg.ar, "FAR"); + + // OBR bitfields. + state->u.f1.fld.obr.opterr = cm_object_get_child_by_name(state->u.f1.reg.obr, "OPTERR"); + state->u.f1.fld.obr.rdprt = cm_object_get_child_by_name(state->u.f1.reg.obr, "RDPRT"); + state->u.f1.fld.obr.wdg_sw = cm_object_get_child_by_name(state->u.f1.reg.obr, "WDG_SW"); + state->u.f1.fld.obr.nrst_stop = cm_object_get_child_by_name(state->u.f1.reg.obr, "nRST_STOP"); + state->u.f1.fld.obr.nrst_stdby = cm_object_get_child_by_name(state->u.f1.reg.obr, "nRST_STDBY"); + state->u.f1.fld.obr.data0 = cm_object_get_child_by_name(state->u.f1.reg.obr, "Data0"); + state->u.f1.fld.obr.data1 = cm_object_get_child_by_name(state->u.f1.reg.obr, "Data1"); + + // WRPR bitfields. + state->u.f1.fld.wrpr.wrp = cm_object_get_child_by_name(state->u.f1.reg.wrpr, "WRP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_flash_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_flash_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_flash_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_flash_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_flash_is_enabled(Object *obj) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_flash_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_flash_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FLASH)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FLASHState *state = STM32_FLASH_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FLASH"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_flash_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_flash_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_flash_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_flash_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_flash_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FLASHEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_flash_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FLASH); +} + +static void stm32_flash_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_flash_reset_callback; + dc->realize = stm32_flash_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_flash_is_enabled; +} + +static const TypeInfo stm32_flash_type_info = { + .name = TYPE_STM32_FLASH, + .parent = TYPE_STM32_FLASH_PARENT, + .instance_init = stm32_flash_instance_init_callback, + .instance_size = sizeof(STM32FLASHState), + .class_init = stm32_flash_class_init_callback, + .class_size = sizeof(STM32FLASHClass) }; + +static void stm32_flash_register_types(void) +{ + type_register_static(&stm32_flash_type_info); +} + +type_init(stm32_flash_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/flash.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/flash.h new file mode 100644 index 0000000000..316c484c38 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/flash.h @@ -0,0 +1,168 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FLASH_H_ +#define STM32_FLASH_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FLASH DEVICE_PATH_STM32 "FLASH" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FLASH TYPE_STM32_PREFIX "flash" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FLASH_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FLASHParentClass; +typedef PeripheralState STM32FLASHParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FLASH_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FLASHClass, (obj), TYPE_STM32_FLASH) +#define STM32_FLASH_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FLASHClass, (klass), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentClass parent_class; + // public: + + // None, so far. +} STM32FLASHClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FLASH_STATE(obj) \ + OBJECT_CHECK(STM32FLASHState, (obj), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 FLASH (FLASH) registers. + struct { + Object *acr; // 0x0 (Flash access control register) + Object *keyr; // 0x4 (Flash key register) + Object *optkeyr; // 0x8 (Flash option key register) + Object *sr; // 0xC (Status register) + Object *cr; // 0x10 (Control register) + Object *ar; // 0x14 (Flash address register) + Object *obr; // 0x1C (Option byte register) + Object *wrpr; // 0x20 (Write protection register) + } reg; + + struct { + + // ACR (Flash access control register) bitfields. + struct { + Object *latency; // [0:2] Latency + Object *hlfcya; // [3:3] Flash half cycle access enable + Object *prftbe; // [4:4] Prefetch buffer enable + Object *prftbs; // [5:5] Prefetch buffer status + } acr; + + // KEYR (Flash key register) bitfields. + struct { + Object *key; // [0:31] FPEC key + } keyr; + + // OPTKEYR (Flash option key register) bitfields. + struct { + Object *optkey; // [0:31] Option byte key + } optkeyr; + + // SR (Status register) bitfields. + struct { + Object *bsy; // [0:0] Busy + Object *pgerr; // [2:2] Programming error + Object *wrprterr; // [4:4] Write protection error + Object *eop; // [5:5] End of operation + } sr; + + // CR (Control register) bitfields. + struct { + Object *pg; // [0:0] Programming + Object *per; // [1:1] Page Erase + Object *mer; // [2:2] Mass Erase + Object *optpg; // [4:4] Option byte programming + Object *opter; // [5:5] Option byte erase + Object *strt; // [6:6] Start + Object *lock; // [7:7] Lock + Object *optwre; // [9:9] Option bytes write enable + Object *errie; // [10:10] Error interrupt enable + Object *eopie; // [12:12] End of operation interrupt enable + } cr; + + // AR (Flash address register) bitfields. + struct { + Object *far_; // [0:31] Flash Address + } ar; + + // OBR (Option byte register) bitfields. + struct { + Object *opterr; // [0:0] Option byte error + Object *rdprt; // [1:1] Read protection + Object *wdg_sw; // [2:2] WDG_SW + Object *nrst_stop; // [3:3] NRST_STOP + Object *nrst_stdby; // [4:4] NRST_STDBY + Object *data0; // [10:17] Data0 + Object *data1; // [18:25] Data1 + } obr; + + // WRPR (Write protection register) bitfields. + struct { + Object *wrp; // [0:31] Write protect + } wrpr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FLASHState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FLASH_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/fsmc.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/fsmc.c new file mode 100644 index 0000000000..79fc4ad14d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/fsmc.c @@ -0,0 +1,497 @@ +/* + * STM32 - FSMC (Flexible static memory controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_fsmc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FSMCState *state = STM32_FSMC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.bcr1 = cm_object_get_child_by_name(obj, "BCR1"); + state->u.f1.reg.btr1 = cm_object_get_child_by_name(obj, "BTR1"); + state->u.f1.reg.bcr2 = cm_object_get_child_by_name(obj, "BCR2"); + state->u.f1.reg.btr2 = cm_object_get_child_by_name(obj, "BTR2"); + state->u.f1.reg.bcr3 = cm_object_get_child_by_name(obj, "BCR3"); + state->u.f1.reg.btr3 = cm_object_get_child_by_name(obj, "BTR3"); + state->u.f1.reg.bcr4 = cm_object_get_child_by_name(obj, "BCR4"); + state->u.f1.reg.btr4 = cm_object_get_child_by_name(obj, "BTR4"); + state->u.f1.reg.pcr2 = cm_object_get_child_by_name(obj, "PCR2"); + state->u.f1.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f1.reg.pmem2 = cm_object_get_child_by_name(obj, "PMEM2"); + state->u.f1.reg.patt2 = cm_object_get_child_by_name(obj, "PATT2"); + state->u.f1.reg.eccr2 = cm_object_get_child_by_name(obj, "ECCR2"); + state->u.f1.reg.pcr3 = cm_object_get_child_by_name(obj, "PCR3"); + state->u.f1.reg.sr3 = cm_object_get_child_by_name(obj, "SR3"); + state->u.f1.reg.pmem3 = cm_object_get_child_by_name(obj, "PMEM3"); + state->u.f1.reg.patt3 = cm_object_get_child_by_name(obj, "PATT3"); + state->u.f1.reg.eccr3 = cm_object_get_child_by_name(obj, "ECCR3"); + state->u.f1.reg.pcr4 = cm_object_get_child_by_name(obj, "PCR4"); + state->u.f1.reg.sr4 = cm_object_get_child_by_name(obj, "SR4"); + state->u.f1.reg.pmem4 = cm_object_get_child_by_name(obj, "PMEM4"); + state->u.f1.reg.patt4 = cm_object_get_child_by_name(obj, "PATT4"); + state->u.f1.reg.pio4 = cm_object_get_child_by_name(obj, "PIO4"); + state->u.f1.reg.bwtr1 = cm_object_get_child_by_name(obj, "BWTR1"); + state->u.f1.reg.bwtr2 = cm_object_get_child_by_name(obj, "BWTR2"); + state->u.f1.reg.bwtr3 = cm_object_get_child_by_name(obj, "BWTR3"); + state->u.f1.reg.bwtr4 = cm_object_get_child_by_name(obj, "BWTR4"); + + + // BCR1 bitfields. + state->u.f1.fld.bcr1.mbken = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "MBKEN"); + state->u.f1.fld.bcr1.muxen = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "MUXEN"); + state->u.f1.fld.bcr1.mtyp = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "MTYP"); + state->u.f1.fld.bcr1.mwid = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "MWID"); + state->u.f1.fld.bcr1.faccen = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "FACCEN"); + state->u.f1.fld.bcr1.bursten = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "BURSTEN"); + state->u.f1.fld.bcr1.waitpol = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "WAITPOL"); + state->u.f1.fld.bcr1.waitcfg = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "WAITCFG"); + state->u.f1.fld.bcr1.wren = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "WREN"); + state->u.f1.fld.bcr1.waiten = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "WAITEN"); + state->u.f1.fld.bcr1.extmod = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "EXTMOD"); + state->u.f1.fld.bcr1.asyncwait = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "ASYNCWAIT"); + state->u.f1.fld.bcr1.cburstrw = cm_object_get_child_by_name(state->u.f1.reg.bcr1, "CBURSTRW"); + + // BTR1 bitfields. + state->u.f1.fld.btr1.addset = cm_object_get_child_by_name(state->u.f1.reg.btr1, "ADDSET"); + state->u.f1.fld.btr1.addhld = cm_object_get_child_by_name(state->u.f1.reg.btr1, "ADDHLD"); + state->u.f1.fld.btr1.datast = cm_object_get_child_by_name(state->u.f1.reg.btr1, "DATAST"); + state->u.f1.fld.btr1.busturn = cm_object_get_child_by_name(state->u.f1.reg.btr1, "BUSTURN"); + state->u.f1.fld.btr1.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.btr1, "CLKDIV"); + state->u.f1.fld.btr1.datlat = cm_object_get_child_by_name(state->u.f1.reg.btr1, "DATLAT"); + state->u.f1.fld.btr1.accmod = cm_object_get_child_by_name(state->u.f1.reg.btr1, "ACCMOD"); + + // BCR2 bitfields. + state->u.f1.fld.bcr2.mbken = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "MBKEN"); + state->u.f1.fld.bcr2.muxen = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "MUXEN"); + state->u.f1.fld.bcr2.mtyp = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "MTYP"); + state->u.f1.fld.bcr2.mwid = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "MWID"); + state->u.f1.fld.bcr2.faccen = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "FACCEN"); + state->u.f1.fld.bcr2.bursten = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "BURSTEN"); + state->u.f1.fld.bcr2.waitpol = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "WAITPOL"); + state->u.f1.fld.bcr2.wrapmod = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "WRAPMOD"); + state->u.f1.fld.bcr2.waitcfg = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "WAITCFG"); + state->u.f1.fld.bcr2.wren = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "WREN"); + state->u.f1.fld.bcr2.waiten = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "WAITEN"); + state->u.f1.fld.bcr2.extmod = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "EXTMOD"); + state->u.f1.fld.bcr2.asyncwait = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "ASYNCWAIT"); + state->u.f1.fld.bcr2.cburstrw = cm_object_get_child_by_name(state->u.f1.reg.bcr2, "CBURSTRW"); + + // BTR2 bitfields. + state->u.f1.fld.btr2.addset = cm_object_get_child_by_name(state->u.f1.reg.btr2, "ADDSET"); + state->u.f1.fld.btr2.addhld = cm_object_get_child_by_name(state->u.f1.reg.btr2, "ADDHLD"); + state->u.f1.fld.btr2.datast = cm_object_get_child_by_name(state->u.f1.reg.btr2, "DATAST"); + state->u.f1.fld.btr2.busturn = cm_object_get_child_by_name(state->u.f1.reg.btr2, "BUSTURN"); + state->u.f1.fld.btr2.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.btr2, "CLKDIV"); + state->u.f1.fld.btr2.datlat = cm_object_get_child_by_name(state->u.f1.reg.btr2, "DATLAT"); + state->u.f1.fld.btr2.accmod = cm_object_get_child_by_name(state->u.f1.reg.btr2, "ACCMOD"); + + // BCR3 bitfields. + state->u.f1.fld.bcr3.mbken = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "MBKEN"); + state->u.f1.fld.bcr3.muxen = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "MUXEN"); + state->u.f1.fld.bcr3.mtyp = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "MTYP"); + state->u.f1.fld.bcr3.mwid = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "MWID"); + state->u.f1.fld.bcr3.faccen = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "FACCEN"); + state->u.f1.fld.bcr3.bursten = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "BURSTEN"); + state->u.f1.fld.bcr3.waitpol = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "WAITPOL"); + state->u.f1.fld.bcr3.wrapmod = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "WRAPMOD"); + state->u.f1.fld.bcr3.waitcfg = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "WAITCFG"); + state->u.f1.fld.bcr3.wren = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "WREN"); + state->u.f1.fld.bcr3.waiten = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "WAITEN"); + state->u.f1.fld.bcr3.extmod = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "EXTMOD"); + state->u.f1.fld.bcr3.asyncwait = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "ASYNCWAIT"); + state->u.f1.fld.bcr3.cburstrw = cm_object_get_child_by_name(state->u.f1.reg.bcr3, "CBURSTRW"); + + // BTR3 bitfields. + state->u.f1.fld.btr3.addset = cm_object_get_child_by_name(state->u.f1.reg.btr3, "ADDSET"); + state->u.f1.fld.btr3.addhld = cm_object_get_child_by_name(state->u.f1.reg.btr3, "ADDHLD"); + state->u.f1.fld.btr3.datast = cm_object_get_child_by_name(state->u.f1.reg.btr3, "DATAST"); + state->u.f1.fld.btr3.busturn = cm_object_get_child_by_name(state->u.f1.reg.btr3, "BUSTURN"); + state->u.f1.fld.btr3.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.btr3, "CLKDIV"); + state->u.f1.fld.btr3.datlat = cm_object_get_child_by_name(state->u.f1.reg.btr3, "DATLAT"); + state->u.f1.fld.btr3.accmod = cm_object_get_child_by_name(state->u.f1.reg.btr3, "ACCMOD"); + + // BCR4 bitfields. + state->u.f1.fld.bcr4.mbken = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "MBKEN"); + state->u.f1.fld.bcr4.muxen = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "MUXEN"); + state->u.f1.fld.bcr4.mtyp = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "MTYP"); + state->u.f1.fld.bcr4.mwid = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "MWID"); + state->u.f1.fld.bcr4.faccen = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "FACCEN"); + state->u.f1.fld.bcr4.bursten = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "BURSTEN"); + state->u.f1.fld.bcr4.waitpol = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "WAITPOL"); + state->u.f1.fld.bcr4.wrapmod = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "WRAPMOD"); + state->u.f1.fld.bcr4.waitcfg = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "WAITCFG"); + state->u.f1.fld.bcr4.wren = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "WREN"); + state->u.f1.fld.bcr4.waiten = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "WAITEN"); + state->u.f1.fld.bcr4.extmod = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "EXTMOD"); + state->u.f1.fld.bcr4.asyncwait = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "ASYNCWAIT"); + state->u.f1.fld.bcr4.cburstrw = cm_object_get_child_by_name(state->u.f1.reg.bcr4, "CBURSTRW"); + + // BTR4 bitfields. + state->u.f1.fld.btr4.addset = cm_object_get_child_by_name(state->u.f1.reg.btr4, "ADDSET"); + state->u.f1.fld.btr4.addhld = cm_object_get_child_by_name(state->u.f1.reg.btr4, "ADDHLD"); + state->u.f1.fld.btr4.datast = cm_object_get_child_by_name(state->u.f1.reg.btr4, "DATAST"); + state->u.f1.fld.btr4.busturn = cm_object_get_child_by_name(state->u.f1.reg.btr4, "BUSTURN"); + state->u.f1.fld.btr4.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.btr4, "CLKDIV"); + state->u.f1.fld.btr4.datlat = cm_object_get_child_by_name(state->u.f1.reg.btr4, "DATLAT"); + state->u.f1.fld.btr4.accmod = cm_object_get_child_by_name(state->u.f1.reg.btr4, "ACCMOD"); + + // PCR2 bitfields. + state->u.f1.fld.pcr2.pwaiten = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "PWAITEN"); + state->u.f1.fld.pcr2.pbken = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "PBKEN"); + state->u.f1.fld.pcr2.ptyp = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "PTYP"); + state->u.f1.fld.pcr2.pwid = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "PWID"); + state->u.f1.fld.pcr2.eccen = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "ECCEN"); + state->u.f1.fld.pcr2.tclr = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "TCLR"); + state->u.f1.fld.pcr2.tar = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "TAR"); + state->u.f1.fld.pcr2.eccps = cm_object_get_child_by_name(state->u.f1.reg.pcr2, "ECCPS"); + + // SR2 bitfields. + state->u.f1.fld.sr2.irs = cm_object_get_child_by_name(state->u.f1.reg.sr2, "IRS"); + state->u.f1.fld.sr2.ils = cm_object_get_child_by_name(state->u.f1.reg.sr2, "ILS"); + state->u.f1.fld.sr2.ifs = cm_object_get_child_by_name(state->u.f1.reg.sr2, "IFS"); + state->u.f1.fld.sr2.iren = cm_object_get_child_by_name(state->u.f1.reg.sr2, "IREN"); + state->u.f1.fld.sr2.ilen = cm_object_get_child_by_name(state->u.f1.reg.sr2, "ILEN"); + state->u.f1.fld.sr2.ifen = cm_object_get_child_by_name(state->u.f1.reg.sr2, "IFEN"); + state->u.f1.fld.sr2.fempt = cm_object_get_child_by_name(state->u.f1.reg.sr2, "FEMPT"); + + // PMEM2 bitfields. + state->u.f1.fld.pmem2.memsetx = cm_object_get_child_by_name(state->u.f1.reg.pmem2, "MEMSETx"); + state->u.f1.fld.pmem2.memwaitx = cm_object_get_child_by_name(state->u.f1.reg.pmem2, "MEMWAITx"); + state->u.f1.fld.pmem2.memholdx = cm_object_get_child_by_name(state->u.f1.reg.pmem2, "MEMHOLDx"); + state->u.f1.fld.pmem2.memhizx = cm_object_get_child_by_name(state->u.f1.reg.pmem2, "MEMHIZx"); + + // PATT2 bitfields. + state->u.f1.fld.patt2.attsetx = cm_object_get_child_by_name(state->u.f1.reg.patt2, "ATTSETx"); + state->u.f1.fld.patt2.attwaitx = cm_object_get_child_by_name(state->u.f1.reg.patt2, "ATTWAITx"); + state->u.f1.fld.patt2.attholdx = cm_object_get_child_by_name(state->u.f1.reg.patt2, "ATTHOLDx"); + state->u.f1.fld.patt2.atthizx = cm_object_get_child_by_name(state->u.f1.reg.patt2, "ATTHIZx"); + + // ECCR2 bitfields. + state->u.f1.fld.eccr2.eccx = cm_object_get_child_by_name(state->u.f1.reg.eccr2, "ECCx"); + + // PCR3 bitfields. + state->u.f1.fld.pcr3.pwaiten = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "PWAITEN"); + state->u.f1.fld.pcr3.pbken = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "PBKEN"); + state->u.f1.fld.pcr3.ptyp = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "PTYP"); + state->u.f1.fld.pcr3.pwid = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "PWID"); + state->u.f1.fld.pcr3.eccen = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "ECCEN"); + state->u.f1.fld.pcr3.tclr = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "TCLR"); + state->u.f1.fld.pcr3.tar = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "TAR"); + state->u.f1.fld.pcr3.eccps = cm_object_get_child_by_name(state->u.f1.reg.pcr3, "ECCPS"); + + // SR3 bitfields. + state->u.f1.fld.sr3.irs = cm_object_get_child_by_name(state->u.f1.reg.sr3, "IRS"); + state->u.f1.fld.sr3.ils = cm_object_get_child_by_name(state->u.f1.reg.sr3, "ILS"); + state->u.f1.fld.sr3.ifs = cm_object_get_child_by_name(state->u.f1.reg.sr3, "IFS"); + state->u.f1.fld.sr3.iren = cm_object_get_child_by_name(state->u.f1.reg.sr3, "IREN"); + state->u.f1.fld.sr3.ilen = cm_object_get_child_by_name(state->u.f1.reg.sr3, "ILEN"); + state->u.f1.fld.sr3.ifen = cm_object_get_child_by_name(state->u.f1.reg.sr3, "IFEN"); + state->u.f1.fld.sr3.fempt = cm_object_get_child_by_name(state->u.f1.reg.sr3, "FEMPT"); + + // PMEM3 bitfields. + state->u.f1.fld.pmem3.memsetx = cm_object_get_child_by_name(state->u.f1.reg.pmem3, "MEMSETx"); + state->u.f1.fld.pmem3.memwaitx = cm_object_get_child_by_name(state->u.f1.reg.pmem3, "MEMWAITx"); + state->u.f1.fld.pmem3.memholdx = cm_object_get_child_by_name(state->u.f1.reg.pmem3, "MEMHOLDx"); + state->u.f1.fld.pmem3.memhizx = cm_object_get_child_by_name(state->u.f1.reg.pmem3, "MEMHIZx"); + + // PATT3 bitfields. + state->u.f1.fld.patt3.attsetx = cm_object_get_child_by_name(state->u.f1.reg.patt3, "ATTSETx"); + state->u.f1.fld.patt3.attwaitx = cm_object_get_child_by_name(state->u.f1.reg.patt3, "ATTWAITx"); + state->u.f1.fld.patt3.attholdx = cm_object_get_child_by_name(state->u.f1.reg.patt3, "ATTHOLDx"); + state->u.f1.fld.patt3.atthizx = cm_object_get_child_by_name(state->u.f1.reg.patt3, "ATTHIZx"); + + // ECCR3 bitfields. + state->u.f1.fld.eccr3.eccx = cm_object_get_child_by_name(state->u.f1.reg.eccr3, "ECCx"); + + // PCR4 bitfields. + state->u.f1.fld.pcr4.pwaiten = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "PWAITEN"); + state->u.f1.fld.pcr4.pbken = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "PBKEN"); + state->u.f1.fld.pcr4.ptyp = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "PTYP"); + state->u.f1.fld.pcr4.pwid = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "PWID"); + state->u.f1.fld.pcr4.eccen = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "ECCEN"); + state->u.f1.fld.pcr4.tclr = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "TCLR"); + state->u.f1.fld.pcr4.tar = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "TAR"); + state->u.f1.fld.pcr4.eccps = cm_object_get_child_by_name(state->u.f1.reg.pcr4, "ECCPS"); + + // SR4 bitfields. + state->u.f1.fld.sr4.irs = cm_object_get_child_by_name(state->u.f1.reg.sr4, "IRS"); + state->u.f1.fld.sr4.ils = cm_object_get_child_by_name(state->u.f1.reg.sr4, "ILS"); + state->u.f1.fld.sr4.ifs = cm_object_get_child_by_name(state->u.f1.reg.sr4, "IFS"); + state->u.f1.fld.sr4.iren = cm_object_get_child_by_name(state->u.f1.reg.sr4, "IREN"); + state->u.f1.fld.sr4.ilen = cm_object_get_child_by_name(state->u.f1.reg.sr4, "ILEN"); + state->u.f1.fld.sr4.ifen = cm_object_get_child_by_name(state->u.f1.reg.sr4, "IFEN"); + state->u.f1.fld.sr4.fempt = cm_object_get_child_by_name(state->u.f1.reg.sr4, "FEMPT"); + + // PMEM4 bitfields. + state->u.f1.fld.pmem4.memsetx = cm_object_get_child_by_name(state->u.f1.reg.pmem4, "MEMSETx"); + state->u.f1.fld.pmem4.memwaitx = cm_object_get_child_by_name(state->u.f1.reg.pmem4, "MEMWAITx"); + state->u.f1.fld.pmem4.memholdx = cm_object_get_child_by_name(state->u.f1.reg.pmem4, "MEMHOLDx"); + state->u.f1.fld.pmem4.memhizx = cm_object_get_child_by_name(state->u.f1.reg.pmem4, "MEMHIZx"); + + // PATT4 bitfields. + state->u.f1.fld.patt4.attsetx = cm_object_get_child_by_name(state->u.f1.reg.patt4, "ATTSETx"); + state->u.f1.fld.patt4.attwaitx = cm_object_get_child_by_name(state->u.f1.reg.patt4, "ATTWAITx"); + state->u.f1.fld.patt4.attholdx = cm_object_get_child_by_name(state->u.f1.reg.patt4, "ATTHOLDx"); + state->u.f1.fld.patt4.atthizx = cm_object_get_child_by_name(state->u.f1.reg.patt4, "ATTHIZx"); + + // PIO4 bitfields. + state->u.f1.fld.pio4.iosetx = cm_object_get_child_by_name(state->u.f1.reg.pio4, "IOSETx"); + state->u.f1.fld.pio4.iowaitx = cm_object_get_child_by_name(state->u.f1.reg.pio4, "IOWAITx"); + state->u.f1.fld.pio4.ioholdx = cm_object_get_child_by_name(state->u.f1.reg.pio4, "IOHOLDx"); + state->u.f1.fld.pio4.iohizx = cm_object_get_child_by_name(state->u.f1.reg.pio4, "IOHIZx"); + + // BWTR1 bitfields. + state->u.f1.fld.bwtr1.addset = cm_object_get_child_by_name(state->u.f1.reg.bwtr1, "ADDSET"); + state->u.f1.fld.bwtr1.addhld = cm_object_get_child_by_name(state->u.f1.reg.bwtr1, "ADDHLD"); + state->u.f1.fld.bwtr1.datast = cm_object_get_child_by_name(state->u.f1.reg.bwtr1, "DATAST"); + state->u.f1.fld.bwtr1.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.bwtr1, "CLKDIV"); + state->u.f1.fld.bwtr1.datlat = cm_object_get_child_by_name(state->u.f1.reg.bwtr1, "DATLAT"); + state->u.f1.fld.bwtr1.accmod = cm_object_get_child_by_name(state->u.f1.reg.bwtr1, "ACCMOD"); + + // BWTR2 bitfields. + state->u.f1.fld.bwtr2.addset = cm_object_get_child_by_name(state->u.f1.reg.bwtr2, "ADDSET"); + state->u.f1.fld.bwtr2.addhld = cm_object_get_child_by_name(state->u.f1.reg.bwtr2, "ADDHLD"); + state->u.f1.fld.bwtr2.datast = cm_object_get_child_by_name(state->u.f1.reg.bwtr2, "DATAST"); + state->u.f1.fld.bwtr2.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.bwtr2, "CLKDIV"); + state->u.f1.fld.bwtr2.datlat = cm_object_get_child_by_name(state->u.f1.reg.bwtr2, "DATLAT"); + state->u.f1.fld.bwtr2.accmod = cm_object_get_child_by_name(state->u.f1.reg.bwtr2, "ACCMOD"); + + // BWTR3 bitfields. + state->u.f1.fld.bwtr3.addset = cm_object_get_child_by_name(state->u.f1.reg.bwtr3, "ADDSET"); + state->u.f1.fld.bwtr3.addhld = cm_object_get_child_by_name(state->u.f1.reg.bwtr3, "ADDHLD"); + state->u.f1.fld.bwtr3.datast = cm_object_get_child_by_name(state->u.f1.reg.bwtr3, "DATAST"); + state->u.f1.fld.bwtr3.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.bwtr3, "CLKDIV"); + state->u.f1.fld.bwtr3.datlat = cm_object_get_child_by_name(state->u.f1.reg.bwtr3, "DATLAT"); + state->u.f1.fld.bwtr3.accmod = cm_object_get_child_by_name(state->u.f1.reg.bwtr3, "ACCMOD"); + + // BWTR4 bitfields. + state->u.f1.fld.bwtr4.addset = cm_object_get_child_by_name(state->u.f1.reg.bwtr4, "ADDSET"); + state->u.f1.fld.bwtr4.addhld = cm_object_get_child_by_name(state->u.f1.reg.bwtr4, "ADDHLD"); + state->u.f1.fld.bwtr4.datast = cm_object_get_child_by_name(state->u.f1.reg.bwtr4, "DATAST"); + state->u.f1.fld.bwtr4.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.bwtr4, "CLKDIV"); + state->u.f1.fld.bwtr4.datlat = cm_object_get_child_by_name(state->u.f1.reg.bwtr4, "DATLAT"); + state->u.f1.fld.bwtr4.accmod = cm_object_get_child_by_name(state->u.f1.reg.bwtr4, "ACCMOD"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_fsmc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_fsmc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_fsmc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_fsmc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_fsmc_is_enabled(Object *obj) +{ + STM32FSMCState *state = STM32_FSMC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_fsmc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FSMCState *state = STM32_FSMC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_fsmc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FSMC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FSMCState *state = STM32_FSMC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FSMC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_fsmc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_fsmc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_fsmc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_fsmc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_fsmc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FSMCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_fsmc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FSMC); +} + +static void stm32_fsmc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_fsmc_reset_callback; + dc->realize = stm32_fsmc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_fsmc_is_enabled; +} + +static const TypeInfo stm32_fsmc_type_info = { + .name = TYPE_STM32_FSMC, + .parent = TYPE_STM32_FSMC_PARENT, + .instance_init = stm32_fsmc_instance_init_callback, + .instance_size = sizeof(STM32FSMCState), + .class_init = stm32_fsmc_class_init_callback, + .class_size = sizeof(STM32FSMCClass) }; + +static void stm32_fsmc_register_types(void) +{ + type_register_static(&stm32_fsmc_type_info); +} + +type_init(stm32_fsmc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/fsmc.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/fsmc.h new file mode 100644 index 0000000000..fae9e94c60 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/fsmc.h @@ -0,0 +1,416 @@ +/* + * STM32 - FSMC (Flexible static memory controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FSMC_H_ +#define STM32_FSMC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FSMC DEVICE_PATH_STM32 "FSMC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FSMC TYPE_STM32_PREFIX "fsmc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FSMC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FSMCParentClass; +typedef PeripheralState STM32FSMCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FSMC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FSMCClass, (obj), TYPE_STM32_FSMC) +#define STM32_FSMC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FSMCClass, (klass), TYPE_STM32_FSMC) + +typedef struct { + // private: + STM32FSMCParentClass parent_class; + // public: + + // None, so far. +} STM32FSMCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FSMC_STATE(obj) \ + OBJECT_CHECK(STM32FSMCState, (obj), TYPE_STM32_FSMC) + +typedef struct { + // private: + STM32FSMCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 FSMC (Flexible static memory controller) registers. + struct { + Object *bcr1; // 0x0 (SRAM/NOR-Flash chip-select control register 1) + Object *btr1; // 0x4 (SRAM/NOR-Flash chip-select timing register 1) + Object *bcr2; // 0x8 (SRAM/NOR-Flash chip-select control register 2) + Object *btr2; // 0xC (SRAM/NOR-Flash chip-select timing register 2) + Object *bcr3; // 0x10 (SRAM/NOR-Flash chip-select control register 3) + Object *btr3; // 0x14 (SRAM/NOR-Flash chip-select timing register 3) + Object *bcr4; // 0x18 (SRAM/NOR-Flash chip-select control register 4) + Object *btr4; // 0x1C (SRAM/NOR-Flash chip-select timing register 4) + Object *pcr2; // 0x60 (PC Card/NAND Flash control register 2) + Object *sr2; // 0x64 (FIFO status and interrupt register 2) + Object *pmem2; // 0x68 (Common memory space timing register 2) + Object *patt2; // 0x6C (Attribute memory space timing register 2) + Object *eccr2; // 0x74 (ECC result register 2) + Object *pcr3; // 0x80 (PC Card/NAND Flash control register 3) + Object *sr3; // 0x84 (FIFO status and interrupt register 3) + Object *pmem3; // 0x88 (Common memory space timing register 3) + Object *patt3; // 0x8C (Attribute memory space timing register 3) + Object *eccr3; // 0x94 (ECC result register 3) + Object *pcr4; // 0xA0 (PC Card/NAND Flash control register 4) + Object *sr4; // 0xA4 (FIFO status and interrupt register 4) + Object *pmem4; // 0xA8 (Common memory space timing register 4) + Object *patt4; // 0xAC (Attribute memory space timing register 4) + Object *pio4; // 0xB0 (I/O space timing register 4) + Object *bwtr1; // 0x104 (SRAM/NOR-Flash write timing registers 1) + Object *bwtr2; // 0x10C (SRAM/NOR-Flash write timing registers 2) + Object *bwtr3; // 0x114 (SRAM/NOR-Flash write timing registers 3) + Object *bwtr4; // 0x11C (SRAM/NOR-Flash write timing registers 4) + } reg; + + struct { + + // BCR1 (SRAM/NOR-Flash chip-select control register 1) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr1; + + // BTR1 (SRAM/NOR-Flash chip-select timing register 1) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr1; + + // BCR2 (SRAM/NOR-Flash chip-select control register 2) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr2; + + // BTR2 (SRAM/NOR-Flash chip-select timing register 2) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr2; + + // BCR3 (SRAM/NOR-Flash chip-select control register 3) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr3; + + // BTR3 (SRAM/NOR-Flash chip-select timing register 3) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr3; + + // BCR4 (SRAM/NOR-Flash chip-select control register 4) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr4; + + // BTR4 (SRAM/NOR-Flash chip-select timing register 4) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr4; + + // PCR2 (PC Card/NAND Flash control register 2) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr2; + + // SR2 (FIFO status and interrupt register 2) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr2; + + // PMEM2 (Common memory space timing register 2) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem2; + + // PATT2 (Attribute memory space timing register 2) bitfields. + struct { + Object *attsetx; // [0:7] Attribute memory x setup time + Object *attwaitx; // [8:15] Attribute memory x wait time + Object *attholdx; // [16:23] Attribute memory x hold time + Object *atthizx; // [24:31] Attribute memory x databus HiZ time + } patt2; + + // ECCR2 (ECC result register 2) bitfields. + struct { + Object *eccx; // [0:31] ECC result + } eccr2; + + // PCR3 (PC Card/NAND Flash control register 3) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr3; + + // SR3 (FIFO status and interrupt register 3) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr3; + + // PMEM3 (Common memory space timing register 3) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem3; + + // PATT3 (Attribute memory space timing register 3) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt3; + + // ECCR3 (ECC result register 3) bitfields. + struct { + Object *eccx; // [0:31] ECCx + } eccr3; + + // PCR4 (PC Card/NAND Flash control register 4) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr4; + + // SR4 (FIFO status and interrupt register 4) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr4; + + // PMEM4 (Common memory space timing register 4) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem4; + + // PATT4 (Attribute memory space timing register 4) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt4; + + // PIO4 (I/O space timing register 4) bitfields. + struct { + Object *iosetx; // [0:7] IOSETx + Object *iowaitx; // [8:15] IOWAITx + Object *ioholdx; // [16:23] IOHOLDx + Object *iohizx; // [24:31] IOHIZx + } pio4; + + // BWTR1 (SRAM/NOR-Flash write timing registers 1) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr1; + + // BWTR2 (SRAM/NOR-Flash write timing registers 2) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr2; + + // BWTR3 (SRAM/NOR-Flash write timing registers 3) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr3; + + // BWTR4 (SRAM/NOR-Flash write timing registers 4) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr4; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FSMCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FSMC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/gpioa.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/gpioa.c new file mode 100644 index 0000000000..239422be0d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/gpioa.c @@ -0,0 +1,389 @@ +/* + * STM32 - GPIO (General purpose I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.crl = cm_object_get_child_by_name(obj, "CRL"); + state->u.f1.reg.crh = cm_object_get_child_by_name(obj, "CRH"); + state->u.f1.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f1.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f1.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + + + // CRL bitfields. + state->u.f1.fld.crl.mode0 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE0"); + state->u.f1.fld.crl.cnf0 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF0"); + state->u.f1.fld.crl.mode1 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE1"); + state->u.f1.fld.crl.cnf1 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF1"); + state->u.f1.fld.crl.mode2 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE2"); + state->u.f1.fld.crl.cnf2 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF2"); + state->u.f1.fld.crl.mode3 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE3"); + state->u.f1.fld.crl.cnf3 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF3"); + state->u.f1.fld.crl.mode4 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE4"); + state->u.f1.fld.crl.cnf4 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF4"); + state->u.f1.fld.crl.mode5 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE5"); + state->u.f1.fld.crl.cnf5 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF5"); + state->u.f1.fld.crl.mode6 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE6"); + state->u.f1.fld.crl.cnf6 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF6"); + state->u.f1.fld.crl.mode7 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE7"); + state->u.f1.fld.crl.cnf7 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF7"); + + // CRH bitfields. + state->u.f1.fld.crh.mode8 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE8"); + state->u.f1.fld.crh.cnf8 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF8"); + state->u.f1.fld.crh.mode9 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE9"); + state->u.f1.fld.crh.cnf9 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF9"); + state->u.f1.fld.crh.mode10 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE10"); + state->u.f1.fld.crh.cnf10 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF10"); + state->u.f1.fld.crh.mode11 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE11"); + state->u.f1.fld.crh.cnf11 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF11"); + state->u.f1.fld.crh.mode12 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE12"); + state->u.f1.fld.crh.cnf12 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF12"); + state->u.f1.fld.crh.mode13 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE13"); + state->u.f1.fld.crh.cnf13 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF13"); + state->u.f1.fld.crh.mode14 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE14"); + state->u.f1.fld.crh.cnf14 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF14"); + state->u.f1.fld.crh.mode15 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE15"); + state->u.f1.fld.crh.cnf15 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF15"); + + // IDR bitfields. + state->u.f1.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR0"); + state->u.f1.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR1"); + state->u.f1.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR2"); + state->u.f1.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR3"); + state->u.f1.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR4"); + state->u.f1.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR5"); + state->u.f1.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR6"); + state->u.f1.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR7"); + state->u.f1.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR8"); + state->u.f1.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR9"); + state->u.f1.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR10"); + state->u.f1.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR11"); + state->u.f1.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR12"); + state->u.f1.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR13"); + state->u.f1.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR14"); + state->u.f1.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f1.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR0"); + state->u.f1.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR1"); + state->u.f1.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR2"); + state->u.f1.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR3"); + state->u.f1.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR4"); + state->u.f1.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR5"); + state->u.f1.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR6"); + state->u.f1.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR7"); + state->u.f1.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR8"); + state->u.f1.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR9"); + state->u.f1.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR10"); + state->u.f1.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR11"); + state->u.f1.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR12"); + state->u.f1.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR13"); + state->u.f1.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR14"); + state->u.f1.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f1.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS0"); + state->u.f1.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS1"); + state->u.f1.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS2"); + state->u.f1.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS3"); + state->u.f1.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS4"); + state->u.f1.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS5"); + state->u.f1.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS6"); + state->u.f1.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS7"); + state->u.f1.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS8"); + state->u.f1.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS9"); + state->u.f1.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS10"); + state->u.f1.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS11"); + state->u.f1.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS12"); + state->u.f1.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS13"); + state->u.f1.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS14"); + state->u.f1.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS15"); + state->u.f1.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR0"); + state->u.f1.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR1"); + state->u.f1.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR2"); + state->u.f1.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR3"); + state->u.f1.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR4"); + state->u.f1.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR5"); + state->u.f1.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR6"); + state->u.f1.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR7"); + state->u.f1.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR8"); + state->u.f1.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR9"); + state->u.f1.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR10"); + state->u.f1.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR11"); + state->u.f1.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR12"); + state->u.f1.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR13"); + state->u.f1.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR14"); + state->u.f1.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR15"); + + // BRR bitfields. + state->u.f1.fld.brr.br0 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR0"); + state->u.f1.fld.brr.br1 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR1"); + state->u.f1.fld.brr.br2 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR2"); + state->u.f1.fld.brr.br3 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR3"); + state->u.f1.fld.brr.br4 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR4"); + state->u.f1.fld.brr.br5 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR5"); + state->u.f1.fld.brr.br6 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR6"); + state->u.f1.fld.brr.br7 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR7"); + state->u.f1.fld.brr.br8 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR8"); + state->u.f1.fld.brr.br9 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR9"); + state->u.f1.fld.brr.br10 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR10"); + state->u.f1.fld.brr.br11 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR11"); + state->u.f1.fld.brr.br12 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR12"); + state->u.f1.fld.brr.br13 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR13"); + state->u.f1.fld.brr.br14 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR14"); + state->u.f1.fld.brr.br15 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR15"); + + // LCKR bitfields. + state->u.f1.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK0"); + state->u.f1.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK1"); + state->u.f1.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK2"); + state->u.f1.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK3"); + state->u.f1.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK4"); + state->u.f1.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK5"); + state->u.f1.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK6"); + state->u.f1.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK7"); + state->u.f1.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK8"); + state->u.f1.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK9"); + state->u.f1.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK10"); + state->u.f1.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK11"); + state->u.f1.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK12"); + state->u.f1.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK13"); + state->u.f1.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK14"); + state->u.f1.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK15"); + state->u.f1.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCKK"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/gpioa.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/gpioa.h new file mode 100644 index 0000000000..f7105b34c5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/gpioa.h @@ -0,0 +1,278 @@ +/* + * STM32 - GPIO (General purpose I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 GPIO (General purpose I/O) registers. + struct { + Object *crl; // 0x0 (Port configuration register low (GPIOn_CRL)) + Object *crh; // 0x4 (Port configuration register high (GPIOn_CRL)) + Object *idr; // 0x8 (Port input data register (GPIOn_IDR)) + Object *odr; // 0xC (Port output data register (GPIOn_ODR)) + Object *bsrr; // 0x10 (Port bit set/reset register (GPIOn_BSRR)) + Object *brr; // 0x14 (Port bit reset register (GPIOn_BRR)) + Object *lckr; // 0x18 (Port configuration lock register) + } reg; + + struct { + + // CRL (Port configuration register low (GPIOn_CRL)) bitfields. + struct { + Object *mode0; // [0:1] Port n.0 mode bits + Object *cnf0; // [2:3] Port n.0 configuration bits + Object *mode1; // [4:5] Port n.1 mode bits + Object *cnf1; // [6:7] Port n.1 configuration bits + Object *mode2; // [8:9] Port n.2 mode bits + Object *cnf2; // [10:11] Port n.2 configuration bits + Object *mode3; // [12:13] Port n.3 mode bits + Object *cnf3; // [14:15] Port n.3 configuration bits + Object *mode4; // [16:17] Port n.4 mode bits + Object *cnf4; // [18:19] Port n.4 configuration bits + Object *mode5; // [20:21] Port n.5 mode bits + Object *cnf5; // [22:23] Port n.5 configuration bits + Object *mode6; // [24:25] Port n.6 mode bits + Object *cnf6; // [26:27] Port n.6 configuration bits + Object *mode7; // [28:29] Port n.7 mode bits + Object *cnf7; // [30:31] Port n.7 configuration bits + } crl; + + // CRH (Port configuration register high (GPIOn_CRL)) bitfields. + struct { + Object *mode8; // [0:1] Port n.8 mode bits + Object *cnf8; // [2:3] Port n.8 configuration bits + Object *mode9; // [4:5] Port n.9 mode bits + Object *cnf9; // [6:7] Port n.9 configuration bits + Object *mode10; // [8:9] Port n.10 mode bits + Object *cnf10; // [10:11] Port n.10 configuration bits + Object *mode11; // [12:13] Port n.11 mode bits + Object *cnf11; // [14:15] Port n.11 configuration bits + Object *mode12; // [16:17] Port n.12 mode bits + Object *cnf12; // [18:19] Port n.12 configuration bits + Object *mode13; // [20:21] Port n.13 mode bits + Object *cnf13; // [22:23] Port n.13 configuration bits + Object *mode14; // [24:25] Port n.14 mode bits + Object *cnf14; // [26:27] Port n.14 configuration bits + Object *mode15; // [28:29] Port n.15 mode bits + Object *cnf15; // [30:31] Port n.15 configuration bits + } crh; + + // IDR (Port input data register (GPIOn_IDR)) bitfields. + struct { + Object *idr0; // [0:0] Port input data + Object *idr1; // [1:1] Port input data + Object *idr2; // [2:2] Port input data + Object *idr3; // [3:3] Port input data + Object *idr4; // [4:4] Port input data + Object *idr5; // [5:5] Port input data + Object *idr6; // [6:6] Port input data + Object *idr7; // [7:7] Port input data + Object *idr8; // [8:8] Port input data + Object *idr9; // [9:9] Port input data + Object *idr10; // [10:10] Port input data + Object *idr11; // [11:11] Port input data + Object *idr12; // [12:12] Port input data + Object *idr13; // [13:13] Port input data + Object *idr14; // [14:14] Port input data + Object *idr15; // [15:15] Port input data + } idr; + + // ODR (Port output data register (GPIOn_ODR)) bitfields. + struct { + Object *odr0; // [0:0] Port output data + Object *odr1; // [1:1] Port output data + Object *odr2; // [2:2] Port output data + Object *odr3; // [3:3] Port output data + Object *odr4; // [4:4] Port output data + Object *odr5; // [5:5] Port output data + Object *odr6; // [6:6] Port output data + Object *odr7; // [7:7] Port output data + Object *odr8; // [8:8] Port output data + Object *odr9; // [9:9] Port output data + Object *odr10; // [10:10] Port output data + Object *odr11; // [11:11] Port output data + Object *odr12; // [12:12] Port output data + Object *odr13; // [13:13] Port output data + Object *odr14; // [14:14] Port output data + Object *odr15; // [15:15] Port output data + } odr; + + // BSRR (Port bit set/reset register (GPIOn_BSRR)) bitfields. + struct { + Object *bs0; // [0:0] Set bit 0 + Object *bs1; // [1:1] Set bit 1 + Object *bs2; // [2:2] Set bit 1 + Object *bs3; // [3:3] Set bit 3 + Object *bs4; // [4:4] Set bit 4 + Object *bs5; // [5:5] Set bit 5 + Object *bs6; // [6:6] Set bit 6 + Object *bs7; // [7:7] Set bit 7 + Object *bs8; // [8:8] Set bit 8 + Object *bs9; // [9:9] Set bit 9 + Object *bs10; // [10:10] Set bit 10 + Object *bs11; // [11:11] Set bit 11 + Object *bs12; // [12:12] Set bit 12 + Object *bs13; // [13:13] Set bit 13 + Object *bs14; // [14:14] Set bit 14 + Object *bs15; // [15:15] Set bit 15 + Object *br0; // [16:16] Reset bit 0 + Object *br1; // [17:17] Reset bit 1 + Object *br2; // [18:18] Reset bit 2 + Object *br3; // [19:19] Reset bit 3 + Object *br4; // [20:20] Reset bit 4 + Object *br5; // [21:21] Reset bit 5 + Object *br6; // [22:22] Reset bit 6 + Object *br7; // [23:23] Reset bit 7 + Object *br8; // [24:24] Reset bit 8 + Object *br9; // [25:25] Reset bit 9 + Object *br10; // [26:26] Reset bit 10 + Object *br11; // [27:27] Reset bit 11 + Object *br12; // [28:28] Reset bit 12 + Object *br13; // [29:29] Reset bit 13 + Object *br14; // [30:30] Reset bit 14 + Object *br15; // [31:31] Reset bit 15 + } bsrr; + + // BRR (Port bit reset register (GPIOn_BRR)) bitfields. + struct { + Object *br0; // [0:0] Reset bit 0 + Object *br1; // [1:1] Reset bit 1 + Object *br2; // [2:2] Reset bit 1 + Object *br3; // [3:3] Reset bit 3 + Object *br4; // [4:4] Reset bit 4 + Object *br5; // [5:5] Reset bit 5 + Object *br6; // [6:6] Reset bit 6 + Object *br7; // [7:7] Reset bit 7 + Object *br8; // [8:8] Reset bit 8 + Object *br9; // [9:9] Reset bit 9 + Object *br10; // [10:10] Reset bit 10 + Object *br11; // [11:11] Reset bit 11 + Object *br12; // [12:12] Reset bit 12 + Object *br13; // [13:13] Reset bit 13 + Object *br14; // [14:14] Reset bit 14 + Object *br15; // [15:15] Reset bit 15 + } brr; + + // LCKR (Port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port A Lock bit 0 + Object *lck1; // [1:1] Port A Lock bit 1 + Object *lck2; // [2:2] Port A Lock bit 2 + Object *lck3; // [3:3] Port A Lock bit 3 + Object *lck4; // [4:4] Port A Lock bit 4 + Object *lck5; // [5:5] Port A Lock bit 5 + Object *lck6; // [6:6] Port A Lock bit 6 + Object *lck7; // [7:7] Port A Lock bit 7 + Object *lck8; // [8:8] Port A Lock bit 8 + Object *lck9; // [9:9] Port A Lock bit 9 + Object *lck10; // [10:10] Port A Lock bit 10 + Object *lck11; // [11:11] Port A Lock bit 11 + Object *lck12; // [12:12] Port A Lock bit 12 + Object *lck13; // [13:13] Port A Lock bit 13 + Object *lck14; // [14:14] Port A Lock bit 14 + Object *lck15; // [15:15] Port A Lock bit 15 + Object *lckk; // [16:16] Lock key + } lckr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/i2c1.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/i2c1.c new file mode 100644 index 0000000000..6728bebdae --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/i2c1.c @@ -0,0 +1,319 @@ +/* + * STM32 - I2C (Inter integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_i2c_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.oar1 = cm_object_get_child_by_name(obj, "OAR1"); + state->u.f1.reg.oar2 = cm_object_get_child_by_name(obj, "OAR2"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.sr1 = cm_object_get_child_by_name(obj, "SR1"); + state->u.f1.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f1.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + state->u.f1.reg.trise = cm_object_get_child_by_name(obj, "TRISE"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.pe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PE"); + state->u.f1.fld.cr1.smbus = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SMBUS"); + state->u.f1.fld.cr1.smbtype = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SMBTYPE"); + state->u.f1.fld.cr1.enarp = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ENARP"); + state->u.f1.fld.cr1.enpec = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ENPEC"); + state->u.f1.fld.cr1.engc = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ENGC"); + state->u.f1.fld.cr1.nostretch = cm_object_get_child_by_name(state->u.f1.reg.cr1, "NOSTRETCH"); + state->u.f1.fld.cr1.start = cm_object_get_child_by_name(state->u.f1.reg.cr1, "START"); + state->u.f1.fld.cr1.stop = cm_object_get_child_by_name(state->u.f1.reg.cr1, "STOP"); + state->u.f1.fld.cr1.ack = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ACK"); + state->u.f1.fld.cr1.pos = cm_object_get_child_by_name(state->u.f1.reg.cr1, "POS"); + state->u.f1.fld.cr1.pec = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEC"); + state->u.f1.fld.cr1.alert = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ALERT"); + state->u.f1.fld.cr1.swrst = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SWRST"); + + // CR2 bitfields. + state->u.f1.fld.cr2.freq = cm_object_get_child_by_name(state->u.f1.reg.cr2, "FREQ"); + state->u.f1.fld.cr2.iterren = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ITERREN"); + state->u.f1.fld.cr2.itevten = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ITEVTEN"); + state->u.f1.fld.cr2.itbufen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ITBUFEN"); + state->u.f1.fld.cr2.dmaen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "DMAEN"); + state->u.f1.fld.cr2.last = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LAST"); + + // OAR1 bitfields. + state->u.f1.fld.oar1.add0 = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADD0"); + state->u.f1.fld.oar1.add7 = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADD7"); + state->u.f1.fld.oar1.add10 = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADD10"); + state->u.f1.fld.oar1.addmode = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADDMODE"); + + // OAR2 bitfields. + state->u.f1.fld.oar2.endual = cm_object_get_child_by_name(state->u.f1.reg.oar2, "ENDUAL"); + state->u.f1.fld.oar2.add2 = cm_object_get_child_by_name(state->u.f1.reg.oar2, "ADD2"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // SR1 bitfields. + state->u.f1.fld.sr1.sb = cm_object_get_child_by_name(state->u.f1.reg.sr1, "SB"); + state->u.f1.fld.sr1.addr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "ADDR"); + state->u.f1.fld.sr1.btf = cm_object_get_child_by_name(state->u.f1.reg.sr1, "BTF"); + state->u.f1.fld.sr1.add10 = cm_object_get_child_by_name(state->u.f1.reg.sr1, "ADD10"); + state->u.f1.fld.sr1.stopf = cm_object_get_child_by_name(state->u.f1.reg.sr1, "STOPF"); + state->u.f1.fld.sr1.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr1, "RxNE"); + state->u.f1.fld.sr1.txe = cm_object_get_child_by_name(state->u.f1.reg.sr1, "TxE"); + state->u.f1.fld.sr1.berr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "BERR"); + state->u.f1.fld.sr1.arlo = cm_object_get_child_by_name(state->u.f1.reg.sr1, "ARLO"); + state->u.f1.fld.sr1.af = cm_object_get_child_by_name(state->u.f1.reg.sr1, "AF"); + state->u.f1.fld.sr1.ovr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "OVR"); + state->u.f1.fld.sr1.pecerr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "PECERR"); + state->u.f1.fld.sr1.timeout = cm_object_get_child_by_name(state->u.f1.reg.sr1, "TIMEOUT"); + state->u.f1.fld.sr1.smbalert = cm_object_get_child_by_name(state->u.f1.reg.sr1, "SMBALERT"); + + // SR2 bitfields. + state->u.f1.fld.sr2.msl = cm_object_get_child_by_name(state->u.f1.reg.sr2, "MSL"); + state->u.f1.fld.sr2.busy = cm_object_get_child_by_name(state->u.f1.reg.sr2, "BUSY"); + state->u.f1.fld.sr2.tra = cm_object_get_child_by_name(state->u.f1.reg.sr2, "TRA"); + state->u.f1.fld.sr2.gencall = cm_object_get_child_by_name(state->u.f1.reg.sr2, "GENCALL"); + state->u.f1.fld.sr2.smbdefault = cm_object_get_child_by_name(state->u.f1.reg.sr2, "SMBDEFAULT"); + state->u.f1.fld.sr2.smbhost = cm_object_get_child_by_name(state->u.f1.reg.sr2, "SMBHOST"); + state->u.f1.fld.sr2.dualf = cm_object_get_child_by_name(state->u.f1.reg.sr2, "DUALF"); + state->u.f1.fld.sr2.pec = cm_object_get_child_by_name(state->u.f1.reg.sr2, "PEC"); + + // CCR bitfields. + state->u.f1.fld.ccr.ccr = cm_object_get_child_by_name(state->u.f1.reg.ccr, "CCR"); + state->u.f1.fld.ccr.duty = cm_object_get_child_by_name(state->u.f1.reg.ccr, "DUTY"); + state->u.f1.fld.ccr.f_s = cm_object_get_child_by_name(state->u.f1.reg.ccr, "F_S"); + + // TRISE bitfields. + state->u.f1.fld.trise.trise = cm_object_get_child_by_name(state->u.f1.reg.trise, "TRISE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2c_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2c_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2c_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2c_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2c_is_enabled(Object *obj) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2c_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2CState *state = STM32_I2C_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_I2C_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2c_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2C)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2CState *state = STM32_I2C_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2C"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_i2c_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_i2c_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_i2c_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_i2c_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_i2c_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2C%dEN", + 1 + state->port_index - STM32_PORT_I2C1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2c_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2C); +} + +static void stm32_i2c_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2c_reset_callback; + dc->realize = stm32_i2c_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2c_is_enabled; +} + +static const TypeInfo stm32_i2c_type_info = { + .name = TYPE_STM32_I2C, + .parent = TYPE_STM32_I2C_PARENT, + .instance_init = stm32_i2c_instance_init_callback, + .instance_size = sizeof(STM32I2CState), + .class_init = stm32_i2c_class_init_callback, + .class_size = sizeof(STM32I2CClass) }; + +static void stm32_i2c_register_types(void) +{ + type_register_static(&stm32_i2c_type_info); +} + +type_init(stm32_i2c_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/i2c1.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/i2c1.h new file mode 100644 index 0000000000..cd9c0eb808 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/i2c1.h @@ -0,0 +1,208 @@ +/* + * STM32 - I2C (Inter integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2C_H_ +#define STM32_I2C_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2C DEVICE_PATH_STM32 "I2C" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_I2C1, + STM32_PORT_I2C2, + STM32_PORT_I2C_UNDEFINED = 0xFF, +} stm32_i2c_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2C TYPE_STM32_PREFIX "i2c" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2C_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2CParentClass; +typedef PeripheralState STM32I2CParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2CClass, (obj), TYPE_STM32_I2C) +#define STM32_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2CClass, (klass), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentClass parent_class; + // public: + + // None, so far. +} STM32I2CClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2C_STATE(obj) \ + OBJECT_CHECK(STM32I2CState, (obj), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_i2c_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 I2C (Inter integrated circuit) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *oar1; // 0x8 (Own address register 1) + Object *oar2; // 0xC (Own address register 2) + Object *dr; // 0x10 (Data register) + Object *sr1; // 0x14 (Status register 1) + Object *sr2; // 0x18 (Status register 2) + Object *ccr; // 0x1C (Clock control register) + Object *trise; // 0x20 (TRISE register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *pe; // [0:0] Peripheral enable + Object *smbus; // [1:1] SMBus mode + Object *smbtype; // [3:3] SMBus type + Object *enarp; // [4:4] ARP enable + Object *enpec; // [5:5] PEC enable + Object *engc; // [6:6] General call enable + Object *nostretch; // [7:7] Clock stretching disable (Slave mode) + Object *start; // [8:8] Start generation + Object *stop; // [9:9] Stop generation + Object *ack; // [10:10] Acknowledge enable + Object *pos; // [11:11] Acknowledge/PEC Position (for data reception) + Object *pec; // [12:12] Packet error checking + Object *alert; // [13:13] SMBus alert + Object *swrst; // [15:15] Software reset + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *freq; // [0:5] Peripheral clock frequency + Object *iterren; // [8:8] Error interrupt enable + Object *itevten; // [9:9] Event interrupt enable + Object *itbufen; // [10:10] Buffer interrupt enable + Object *dmaen; // [11:11] DMA requests enable + Object *last; // [12:12] DMA last transfer + } cr2; + + // OAR1 (Own address register 1) bitfields. + struct { + Object *add0; // [0:0] Interface address + Object *add7; // [1:7] Interface address + Object *add10; // [8:9] Interface address + Object *addmode; // [15:15] Addressing mode (slave mode) + } oar1; + + // OAR2 (Own address register 2) bitfields. + struct { + Object *endual; // [0:0] Dual addressing mode enable + Object *add2; // [1:7] Interface address + } oar2; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:7] 8-bit data register + } dr; + + // SR1 (Status register 1) bitfields. + struct { + Object *sb; // [0:0] Start bit (Master mode) + Object *addr; // [1:1] Address sent (master mode)/matched (slave mode) + Object *btf; // [2:2] Byte transfer finished + Object *add10; // [3:3] 10-bit header sent (Master mode) + Object *stopf; // [4:4] Stop detection (slave mode) + Object *rxne; // [6:6] Data register not empty (receivers) + Object *txe; // [7:7] Data register empty (transmitters) + Object *berr; // [8:8] Bus error + Object *arlo; // [9:9] Arbitration lost (master mode) + Object *af; // [10:10] Acknowledge failure + Object *ovr; // [11:11] Overrun/Underrun + Object *pecerr; // [12:12] PEC Error in reception + Object *timeout; // [14:14] Timeout or Tlow error + Object *smbalert; // [15:15] SMBus alert + } sr1; + + // SR2 (Status register 2) bitfields. + struct { + Object *msl; // [0:0] Master/slave + Object *busy; // [1:1] Bus busy + Object *tra; // [2:2] Transmitter/receiver + Object *gencall; // [4:4] General call address (Slave mode) + Object *smbdefault; // [5:5] SMBus device default address (Slave mode) + Object *smbhost; // [6:6] SMBus host header (Slave mode) + Object *dualf; // [7:7] Dual flag (Slave mode) + Object *pec; // [8:15] Acket error checking register + } sr2; + + // CCR (Clock control register) bitfields. + struct { + Object *ccr; // [0:11] Clock control register in Fast/Standard mode (Master mode) + Object *duty; // [14:14] Fast mode duty cycle + Object *f_s; // [15:15] I2C master mode selection + } ccr; + + // TRISE (TRISE register) bitfields. + struct { + Object *trise; // [0:5] Maximum rise time in Fast/Standard mode (Master mode) + } trise; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2CState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2C_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/iwdg.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/iwdg.c new file mode 100644 index 0000000000..f560ce826a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/iwdg.c @@ -0,0 +1,251 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_iwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.kr = cm_object_get_child_by_name(obj, "KR"); + state->u.f1.reg.pr = cm_object_get_child_by_name(obj, "PR"); + state->u.f1.reg.rlr = cm_object_get_child_by_name(obj, "RLR"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // KR bitfields. + state->u.f1.fld.kr.key = cm_object_get_child_by_name(state->u.f1.reg.kr, "KEY"); + + // PR bitfields. + state->u.f1.fld.pr.pr = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR"); + + // RLR bitfields. + state->u.f1.fld.rlr.rl = cm_object_get_child_by_name(state->u.f1.reg.rlr, "RL"); + + // SR bitfields. + state->u.f1.fld.sr.pvu = cm_object_get_child_by_name(state->u.f1.reg.sr, "PVU"); + state->u.f1.fld.sr.rvu = cm_object_get_child_by_name(state->u.f1.reg.sr, "RVU"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_iwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_iwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_iwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_iwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_iwdg_is_enabled(Object *obj) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_iwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_iwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_IWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32IWDGState *state = STM32_IWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "IWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_iwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_iwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_iwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_iwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_iwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/IWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_iwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_IWDG); +} + +static void stm32_iwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_iwdg_reset_callback; + dc->realize = stm32_iwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_iwdg_is_enabled; +} + +static const TypeInfo stm32_iwdg_type_info = { + .name = TYPE_STM32_IWDG, + .parent = TYPE_STM32_IWDG_PARENT, + .instance_init = stm32_iwdg_instance_init_callback, + .instance_size = sizeof(STM32IWDGState), + .class_init = stm32_iwdg_class_init_callback, + .class_size = sizeof(STM32IWDGClass) }; + +static void stm32_iwdg_register_types(void) +{ + type_register_static(&stm32_iwdg_type_info); +} + +type_init(stm32_iwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/iwdg.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/iwdg.h new file mode 100644 index 0000000000..b1eeb71a8c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/iwdg.h @@ -0,0 +1,124 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_IWDG_H_ +#define STM32_IWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_IWDG DEVICE_PATH_STM32 "IWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_IWDG TYPE_STM32_PREFIX "iwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_IWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32IWDGParentClass; +typedef PeripheralState STM32IWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_IWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32IWDGClass, (obj), TYPE_STM32_IWDG) +#define STM32_IWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32IWDGClass, (klass), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentClass parent_class; + // public: + + // None, so far. +} STM32IWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_IWDG_STATE(obj) \ + OBJECT_CHECK(STM32IWDGState, (obj), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 IWDG (Independent watchdog) registers. + struct { + Object *kr; // 0x0 (Key register (IWDG_KR)) + Object *pr; // 0x4 (Prescaler register (IWDG_PR)) + Object *rlr; // 0x8 (Reload register (IWDG_RLR)) + Object *sr; // 0xC (Status register (IWDG_SR)) + } reg; + + struct { + + // KR (Key register (IWDG_KR)) bitfields. + struct { + Object *key; // [0:15] Key value + } kr; + + // PR (Prescaler register (IWDG_PR)) bitfields. + struct { + Object *pr; // [0:2] Prescaler divider + } pr; + + // RLR (Reload register (IWDG_RLR)) bitfields. + struct { + Object *rl; // [0:11] Watchdog counter reload value + } rlr; + + // SR (Status register (IWDG_SR)) bitfields. + struct { + Object *pvu; // [0:0] Watchdog prescaler value update + Object *rvu; // [1:1] Watchdog counter reload value update + } sr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32IWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_IWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/pwr.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/pwr.c new file mode 100644 index 0000000000..40cfaefe39 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/pwr.c @@ -0,0 +1,251 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_pwr_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CR bitfields. + state->u.f1.fld.cr.lpds = cm_object_get_child_by_name(state->u.f1.reg.cr, "LPDS"); + state->u.f1.fld.cr.pdds = cm_object_get_child_by_name(state->u.f1.reg.cr, "PDDS"); + state->u.f1.fld.cr.cwuf = cm_object_get_child_by_name(state->u.f1.reg.cr, "CWUF"); + state->u.f1.fld.cr.csbf = cm_object_get_child_by_name(state->u.f1.reg.cr, "CSBF"); + state->u.f1.fld.cr.pvde = cm_object_get_child_by_name(state->u.f1.reg.cr, "PVDE"); + state->u.f1.fld.cr.pls = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLS"); + state->u.f1.fld.cr.dbp = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBP"); + + // CSR bitfields. + state->u.f1.fld.csr.wuf = cm_object_get_child_by_name(state->u.f1.reg.csr, "WUF"); + state->u.f1.fld.csr.sbf = cm_object_get_child_by_name(state->u.f1.reg.csr, "SBF"); + state->u.f1.fld.csr.pvdo = cm_object_get_child_by_name(state->u.f1.reg.csr, "PVDO"); + state->u.f1.fld.csr.ewup = cm_object_get_child_by_name(state->u.f1.reg.csr, "EWUP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_pwr_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_pwr_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_pwr_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_pwr_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_pwr_is_enabled(Object *obj) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_pwr_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32PWRState *state = STM32_PWR_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_pwr_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_PWR)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32PWRState *state = STM32_PWR_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "PWR"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_pwr_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_pwr_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_pwr_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_pwr_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_pwr_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/PWREN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_pwr_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_PWR); +} + +static void stm32_pwr_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_pwr_reset_callback; + dc->realize = stm32_pwr_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_pwr_is_enabled; +} + +static const TypeInfo stm32_pwr_type_info = { + .name = TYPE_STM32_PWR, + .parent = TYPE_STM32_PWR_PARENT, + .instance_init = stm32_pwr_instance_init_callback, + .instance_size = sizeof(STM32PWRState), + .class_init = stm32_pwr_class_init_callback, + .class_size = sizeof(STM32PWRClass) }; + +static void stm32_pwr_register_types(void) +{ + type_register_static(&stm32_pwr_type_info); +} + +type_init(stm32_pwr_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/pwr.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/pwr.h new file mode 100644 index 0000000000..bd3ec3526f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/pwr.h @@ -0,0 +1,120 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_PWR_H_ +#define STM32_PWR_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_PWR DEVICE_PATH_STM32 "PWR" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_PWR TYPE_STM32_PREFIX "pwr" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_PWR_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32PWRParentClass; +typedef PeripheralState STM32PWRParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_PWR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32PWRClass, (obj), TYPE_STM32_PWR) +#define STM32_PWR_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32PWRClass, (klass), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentClass parent_class; + // public: + + // None, so far. +} STM32PWRClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_PWR_STATE(obj) \ + OBJECT_CHECK(STM32PWRState, (obj), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 PWR (Power control) registers. + struct { + Object *cr; // 0x0 (Power control register (PWR_CR)) + Object *csr; // 0x4 (Power control register (PWR_CR)) + } reg; + + struct { + + // CR (Power control register (PWR_CR)) bitfields. + struct { + Object *lpds; // [0:0] Low Power Deep Sleep + Object *pdds; // [1:1] Power Down Deep Sleep + Object *cwuf; // [2:2] Clear Wake-up Flag + Object *csbf; // [3:3] Clear STANDBY Flag + Object *pvde; // [4:4] Power Voltage Detector Enable + Object *pls; // [5:7] PVD Level Selection + Object *dbp; // [8:8] Disable Backup Domain write protection + } cr; + + // CSR (Power control register (PWR_CR)) bitfields. + struct { + Object *wuf; // [0:0] Wake-Up Flag + Object *sbf; // [1:1] STANDBY Flag + Object *pvdo; // [2:2] PVD Output + Object *ewup; // [8:8] Enable WKUP pin + } csr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32PWRState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_PWR_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/rcc.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/rcc.c new file mode 100644 index 0000000000..2abd3e38a9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/rcc.c @@ -0,0 +1,406 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_rcc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f1.reg.cir = cm_object_get_child_by_name(obj, "CIR"); + state->u.f1.reg.apb2rstr = cm_object_get_child_by_name(obj, "APB2RSTR"); + state->u.f1.reg.apb1rstr = cm_object_get_child_by_name(obj, "APB1RSTR"); + state->u.f1.reg.ahbenr = cm_object_get_child_by_name(obj, "AHBENR"); + state->u.f1.reg.apb2enr = cm_object_get_child_by_name(obj, "APB2ENR"); + state->u.f1.reg.apb1enr = cm_object_get_child_by_name(obj, "APB1ENR"); + state->u.f1.reg.bdcr = cm_object_get_child_by_name(obj, "BDCR"); + state->u.f1.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CR bitfields. + state->u.f1.fld.cr.hsion = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSION"); + state->u.f1.fld.cr.hsirdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSIRDY"); + state->u.f1.fld.cr.hsitrim = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSITRIM"); + state->u.f1.fld.cr.hsical = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSICAL"); + state->u.f1.fld.cr.hseon = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSEON"); + state->u.f1.fld.cr.hserdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSERDY"); + state->u.f1.fld.cr.hsebyp = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSEBYP"); + state->u.f1.fld.cr.csson = cm_object_get_child_by_name(state->u.f1.reg.cr, "CSSON"); + state->u.f1.fld.cr.pllon = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLLON"); + state->u.f1.fld.cr.pllrdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLLRDY"); + + // CFGR bitfields. + state->u.f1.fld.cfgr.sw = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "SW"); + state->u.f1.fld.cfgr.sws = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "SWS"); + state->u.f1.fld.cfgr.hpre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "HPRE"); + state->u.f1.fld.cfgr.ppre1 = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PPRE1"); + state->u.f1.fld.cfgr.ppre2 = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PPRE2"); + state->u.f1.fld.cfgr.adcpre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "ADCPRE"); + state->u.f1.fld.cfgr.pllsrc = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PLLSRC"); + state->u.f1.fld.cfgr.pllxtpre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PLLXTPRE"); + state->u.f1.fld.cfgr.pllmul = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PLLMUL"); + state->u.f1.fld.cfgr.otgfspre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "OTGFSPRE"); + state->u.f1.fld.cfgr.mco = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "MCO"); + + // CIR bitfields. + state->u.f1.fld.cir.lsirdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSIRDYF"); + state->u.f1.fld.cir.lserdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSERDYF"); + state->u.f1.fld.cir.hsirdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSIRDYF"); + state->u.f1.fld.cir.hserdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSERDYF"); + state->u.f1.fld.cir.pllrdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLLRDYF"); + state->u.f1.fld.cir.cssf = cm_object_get_child_by_name(state->u.f1.reg.cir, "CSSF"); + state->u.f1.fld.cir.lsirdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSIRDYIE"); + state->u.f1.fld.cir.lserdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSERDYIE"); + state->u.f1.fld.cir.hsirdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSIRDYIE"); + state->u.f1.fld.cir.hserdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSERDYIE"); + state->u.f1.fld.cir.pllrdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLLRDYIE"); + state->u.f1.fld.cir.lsirdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSIRDYC"); + state->u.f1.fld.cir.lserdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSERDYC"); + state->u.f1.fld.cir.hsirdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSIRDYC"); + state->u.f1.fld.cir.hserdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSERDYC"); + state->u.f1.fld.cir.pllrdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLLRDYC"); + state->u.f1.fld.cir.cssc = cm_object_get_child_by_name(state->u.f1.reg.cir, "CSSC"); + + // APB2RSTR bitfields. + state->u.f1.fld.apb2rstr.afiorst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "AFIORST"); + state->u.f1.fld.apb2rstr.ioparst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPARST"); + state->u.f1.fld.apb2rstr.iopbrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPBRST"); + state->u.f1.fld.apb2rstr.iopcrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPCRST"); + state->u.f1.fld.apb2rstr.iopdrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPDRST"); + state->u.f1.fld.apb2rstr.ioperst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPERST"); + state->u.f1.fld.apb2rstr.iopfrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPFRST"); + state->u.f1.fld.apb2rstr.iopgrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPGRST"); + state->u.f1.fld.apb2rstr.adc1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "ADC1RST"); + state->u.f1.fld.apb2rstr.adc2rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "ADC2RST"); + state->u.f1.fld.apb2rstr.tim1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "TIM1RST"); + state->u.f1.fld.apb2rstr.spi1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "SPI1RST"); + state->u.f1.fld.apb2rstr.tim8rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "TIM8RST"); + state->u.f1.fld.apb2rstr.usart1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "USART1RST"); + state->u.f1.fld.apb2rstr.adc3rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "ADC3RST"); + state->u.f1.fld.apb2rstr.tim9rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "TIM9RST"); + state->u.f1.fld.apb2rstr.tim10rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "TIM10RST"); + state->u.f1.fld.apb2rstr.tim11rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "TIM11RST"); + + // APB1RSTR bitfields. + state->u.f1.fld.apb1rstr.tim2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM2RST"); + state->u.f1.fld.apb1rstr.tim3rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM3RST"); + state->u.f1.fld.apb1rstr.tim4rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM4RST"); + state->u.f1.fld.apb1rstr.tim5rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM5RST"); + state->u.f1.fld.apb1rstr.tim6rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM6RST"); + state->u.f1.fld.apb1rstr.tim7rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM7RST"); + state->u.f1.fld.apb1rstr.tim12rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM12RST"); + state->u.f1.fld.apb1rstr.tim13rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM13RST"); + state->u.f1.fld.apb1rstr.tim14rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM14RST"); + state->u.f1.fld.apb1rstr.wwdgrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "WWDGRST"); + state->u.f1.fld.apb1rstr.spi2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "SPI2RST"); + state->u.f1.fld.apb1rstr.spi3rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "SPI3RST"); + state->u.f1.fld.apb1rstr.usart2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "USART2RST"); + state->u.f1.fld.apb1rstr.usart3rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "USART3RST"); + state->u.f1.fld.apb1rstr.uart4rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "UART4RST"); + state->u.f1.fld.apb1rstr.uart5rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "UART5RST"); + state->u.f1.fld.apb1rstr.i2c1rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "I2C1RST"); + state->u.f1.fld.apb1rstr.i2c2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "I2C2RST"); + state->u.f1.fld.apb1rstr.usbrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "USBRST"); + state->u.f1.fld.apb1rstr.canrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "CANRST"); + state->u.f1.fld.apb1rstr.bkprst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "BKPRST"); + state->u.f1.fld.apb1rstr.pwrrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "PWRRST"); + state->u.f1.fld.apb1rstr.dacrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "DACRST"); + + // AHBENR bitfields. + state->u.f1.fld.ahbenr.dma1en = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "DMA1EN"); + state->u.f1.fld.ahbenr.dma2en = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "DMA2EN"); + state->u.f1.fld.ahbenr.sramen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "SRAMEN"); + state->u.f1.fld.ahbenr.flitfen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "FLITFEN"); + state->u.f1.fld.ahbenr.crcen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "CRCEN"); + state->u.f1.fld.ahbenr.fsmcen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "FSMCEN"); + state->u.f1.fld.ahbenr.sdioen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "SDIOEN"); + + // APB2ENR bitfields. + state->u.f1.fld.apb2enr.afioen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "AFIOEN"); + state->u.f1.fld.apb2enr.iopaen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPAEN"); + state->u.f1.fld.apb2enr.iopben = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPBEN"); + state->u.f1.fld.apb2enr.iopcen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPCEN"); + state->u.f1.fld.apb2enr.iopden = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPDEN"); + state->u.f1.fld.apb2enr.iopeen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPEEN"); + state->u.f1.fld.apb2enr.iopfen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPFEN"); + state->u.f1.fld.apb2enr.iopgen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPGEN"); + state->u.f1.fld.apb2enr.adc1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "ADC1EN"); + state->u.f1.fld.apb2enr.adc2en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "ADC2EN"); + state->u.f1.fld.apb2enr.tim1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "TIM1EN"); + state->u.f1.fld.apb2enr.spi1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "SPI1EN"); + state->u.f1.fld.apb2enr.tim8en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "TIM8EN"); + state->u.f1.fld.apb2enr.usart1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "USART1EN"); + state->u.f1.fld.apb2enr.adc3en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "ADC3EN"); + state->u.f1.fld.apb2enr.tim9en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "TIM9EN"); + state->u.f1.fld.apb2enr.tim10en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "TIM10EN"); + state->u.f1.fld.apb2enr.tim11en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "TIM11EN"); + + // APB1ENR bitfields. + state->u.f1.fld.apb1enr.tim2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM2EN"); + state->u.f1.fld.apb1enr.tim3en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM3EN"); + state->u.f1.fld.apb1enr.tim4en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM4EN"); + state->u.f1.fld.apb1enr.tim5en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM5EN"); + state->u.f1.fld.apb1enr.tim6en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM6EN"); + state->u.f1.fld.apb1enr.tim7en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM7EN"); + state->u.f1.fld.apb1enr.tim12en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM12EN"); + state->u.f1.fld.apb1enr.tim13en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM13EN"); + state->u.f1.fld.apb1enr.tim14en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM14EN"); + state->u.f1.fld.apb1enr.wwdgen = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "WWDGEN"); + state->u.f1.fld.apb1enr.spi2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "SPI2EN"); + state->u.f1.fld.apb1enr.spi3en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "SPI3EN"); + state->u.f1.fld.apb1enr.usart2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "USART2EN"); + state->u.f1.fld.apb1enr.usart3en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "USART3EN"); + state->u.f1.fld.apb1enr.uart4en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "UART4EN"); + state->u.f1.fld.apb1enr.uart5en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "UART5EN"); + state->u.f1.fld.apb1enr.i2c1en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "I2C1EN"); + state->u.f1.fld.apb1enr.i2c2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "I2C2EN"); + state->u.f1.fld.apb1enr.usben = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "USBEN"); + state->u.f1.fld.apb1enr.canen = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "CANEN"); + state->u.f1.fld.apb1enr.bkpen = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "BKPEN"); + state->u.f1.fld.apb1enr.pwren = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "PWREN"); + state->u.f1.fld.apb1enr.dacen = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "DACEN"); + + // BDCR bitfields. + state->u.f1.fld.bdcr.lseon = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "LSEON"); + state->u.f1.fld.bdcr.lserdy = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "LSERDY"); + state->u.f1.fld.bdcr.lsebyp = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "LSEBYP"); + state->u.f1.fld.bdcr.rtcsel = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "RTCSEL"); + state->u.f1.fld.bdcr.rtcen = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "RTCEN"); + state->u.f1.fld.bdcr.bdrst = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "BDRST"); + + // CSR bitfields. + state->u.f1.fld.csr.lsion = cm_object_get_child_by_name(state->u.f1.reg.csr, "LSION"); + state->u.f1.fld.csr.lsirdy = cm_object_get_child_by_name(state->u.f1.reg.csr, "LSIRDY"); + state->u.f1.fld.csr.rmvf = cm_object_get_child_by_name(state->u.f1.reg.csr, "RMVF"); + state->u.f1.fld.csr.pinrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "PINRSTF"); + state->u.f1.fld.csr.porrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "PORRSTF"); + state->u.f1.fld.csr.sftrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "SFTRSTF"); + state->u.f1.fld.csr.iwdgrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "IWDGRSTF"); + state->u.f1.fld.csr.wwdgrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "WWDGRSTF"); + state->u.f1.fld.csr.lpwrrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "LPWRRSTF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rcc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rcc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rcc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rcc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rcc_is_enabled(Object *obj) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rcc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RCCState *state = STM32_RCC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rcc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RCC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RCCState *state = STM32_RCC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RCC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_rcc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rcc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_rcc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rcc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_rcc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RCCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rcc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RCC); +} + +static void stm32_rcc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rcc_reset_callback; + dc->realize = stm32_rcc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rcc_is_enabled; +} + +static const TypeInfo stm32_rcc_type_info = { + .name = TYPE_STM32_RCC, + .parent = TYPE_STM32_RCC_PARENT, + .instance_init = stm32_rcc_instance_init_callback, + .instance_size = sizeof(STM32RCCState), + .class_init = stm32_rcc_class_init_callback, + .class_size = sizeof(STM32RCCClass) }; + +static void stm32_rcc_register_types(void) +{ + type_register_static(&stm32_rcc_type_info); +} + +type_init(stm32_rcc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/rcc.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/rcc.h new file mode 100644 index 0000000000..115ed54a85 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/rcc.h @@ -0,0 +1,291 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RCC_H_ +#define STM32_RCC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RCC DEVICE_PATH_STM32 "RCC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RCC TYPE_STM32_PREFIX "rcc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RCC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RCCParentClass; +typedef PeripheralState STM32RCCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RCCClass, (obj), TYPE_STM32_RCC) +#define STM32_RCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RCCClass, (klass), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentClass parent_class; + // public: + + // None, so far. +} STM32RCCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RCC_STATE(obj) \ + OBJECT_CHECK(STM32RCCState, (obj), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 RCC (Reset and clock control) registers. + struct { + Object *cr; // 0x0 (Clock control register) + Object *cfgr; // 0x4 (Clock configuration register (RCC_CFGR)) + Object *cir; // 0x8 (Clock interrupt register (RCC_CIR)) + Object *apb2rstr; // 0xC (APB2 peripheral reset register (RCC_APB2RSTR)) + Object *apb1rstr; // 0x10 (APB1 peripheral reset register (RCC_APB1RSTR)) + Object *ahbenr; // 0x14 (AHB Peripheral Clock enable register (RCC_AHBENR)) + Object *apb2enr; // 0x18 (APB2 peripheral clock enable register (RCC_APB2ENR)) + Object *apb1enr; // 0x1C (APB1 peripheral clock enable register (RCC_APB1ENR)) + Object *bdcr; // 0x20 (Backup domain control register (RCC_BDCR)) + Object *csr; // 0x24 (Control/status register (RCC_CSR)) + } reg; + + struct { + + // CR (Clock control register) bitfields. + struct { + Object *hsion; // [0:0] Internal High Speed clock enable + Object *hsirdy; // [1:1] Internal High Speed clock ready flag + Object *hsitrim; // [3:7] Internal High Speed clock trimming + Object *hsical; // [8:15] Internal High Speed clock Calibration + Object *hseon; // [16:16] External High Speed clock enable + Object *hserdy; // [17:17] External High Speed clock ready flag + Object *hsebyp; // [18:18] External High Speed clock Bypass + Object *csson; // [19:19] Clock Security System enable + Object *pllon; // [24:24] PLL enable + Object *pllrdy; // [25:25] PLL clock ready flag + } cr; + + // CFGR (Clock configuration register (RCC_CFGR)) bitfields. + struct { + Object *sw; // [0:1] System clock Switch + Object *sws; // [2:3] System Clock Switch Status + Object *hpre; // [4:7] AHB prescaler + Object *ppre1; // [8:10] APB Low speed prescaler (APB1) + Object *ppre2; // [11:13] APB High speed prescaler (APB2) + Object *adcpre; // [14:15] ADC prescaler + Object *pllsrc; // [16:16] PLL entry clock source + Object *pllxtpre; // [17:17] HSE divider for PLL entry + Object *pllmul; // [18:21] PLL Multiplication Factor + Object *otgfspre; // [22:22] USB OTG FS prescaler + Object *mco; // [24:26] Microcontroller clock output + } cfgr; + + // CIR (Clock interrupt register (RCC_CIR)) bitfields. + struct { + Object *lsirdyf; // [0:0] LSI Ready Interrupt flag + Object *lserdyf; // [1:1] LSE Ready Interrupt flag + Object *hsirdyf; // [2:2] HSI Ready Interrupt flag + Object *hserdyf; // [3:3] HSE Ready Interrupt flag + Object *pllrdyf; // [4:4] PLL Ready Interrupt flag + Object *cssf; // [7:7] Clock Security System Interrupt flag + Object *lsirdyie; // [8:8] LSI Ready Interrupt Enable + Object *lserdyie; // [9:9] LSE Ready Interrupt Enable + Object *hsirdyie; // [10:10] HSI Ready Interrupt Enable + Object *hserdyie; // [11:11] HSE Ready Interrupt Enable + Object *pllrdyie; // [12:12] PLL Ready Interrupt Enable + Object *lsirdyc; // [16:16] LSI Ready Interrupt Clear + Object *lserdyc; // [17:17] LSE Ready Interrupt Clear + Object *hsirdyc; // [18:18] HSI Ready Interrupt Clear + Object *hserdyc; // [19:19] HSE Ready Interrupt Clear + Object *pllrdyc; // [20:20] PLL Ready Interrupt Clear + Object *cssc; // [23:23] Clock security system interrupt clear + } cir; + + // APB2RSTR (APB2 peripheral reset register (RCC_APB2RSTR)) bitfields. + struct { + Object *afiorst; // [0:0] Alternate function I/O reset + Object *ioparst; // [2:2] IO port A reset + Object *iopbrst; // [3:3] IO port B reset + Object *iopcrst; // [4:4] IO port C reset + Object *iopdrst; // [5:5] IO port D reset + Object *ioperst; // [6:6] IO port E reset + Object *iopfrst; // [7:7] IO port F reset + Object *iopgrst; // [8:8] IO port G reset + Object *adc1rst; // [9:9] ADC 1 interface reset + Object *adc2rst; // [10:10] ADC 2 interface reset + Object *tim1rst; // [11:11] TIM1 timer reset + Object *spi1rst; // [12:12] SPI 1 reset + Object *tim8rst; // [13:13] TIM8 timer reset + Object *usart1rst; // [14:14] USART1 reset + Object *adc3rst; // [15:15] ADC 3 interface reset + Object *tim9rst; // [19:19] TIM9 timer reset + Object *tim10rst; // [20:20] TIM10 timer reset + Object *tim11rst; // [21:21] TIM11 timer reset + } apb2rstr; + + // APB1RSTR (APB1 peripheral reset register (RCC_APB1RSTR)) bitfields. + struct { + Object *tim2rst; // [0:0] Timer 2 reset + Object *tim3rst; // [1:1] Timer 3 reset + Object *tim4rst; // [2:2] Timer 4 reset + Object *tim5rst; // [3:3] Timer 5 reset + Object *tim6rst; // [4:4] Timer 6 reset + Object *tim7rst; // [5:5] Timer 7 reset + Object *tim12rst; // [6:6] Timer 12 reset + Object *tim13rst; // [7:7] Timer 13 reset + Object *tim14rst; // [8:8] Timer 14 reset + Object *wwdgrst; // [11:11] Window watchdog reset + Object *spi2rst; // [14:14] SPI2 reset + Object *spi3rst; // [15:15] SPI3 reset + Object *usart2rst; // [17:17] USART 2 reset + Object *usart3rst; // [18:18] USART 3 reset + Object *uart4rst; // [19:19] UART 4 reset + Object *uart5rst; // [20:20] UART 5 reset + Object *i2c1rst; // [21:21] I2C1 reset + Object *i2c2rst; // [22:22] I2C2 reset + Object *usbrst; // [23:23] USB reset + Object *canrst; // [25:25] CAN reset + Object *bkprst; // [27:27] Backup interface reset + Object *pwrrst; // [28:28] Power interface reset + Object *dacrst; // [29:29] DAC interface reset + } apb1rstr; + + // AHBENR (AHB Peripheral Clock enable register (RCC_AHBENR)) bitfields. + struct { + Object *dma1en; // [0:0] DMA1 clock enable + Object *dma2en; // [1:1] DMA2 clock enable + Object *sramen; // [2:2] SRAM interface clock enable + Object *flitfen; // [4:4] FLITF clock enable + Object *crcen; // [6:6] CRC clock enable + Object *fsmcen; // [8:8] FSMC clock enable + Object *sdioen; // [10:10] SDIO clock enable + } ahbenr; + + // APB2ENR (APB2 peripheral clock enable register (RCC_APB2ENR)) bitfields. + struct { + Object *afioen; // [0:0] Alternate function I/O clock enable + Object *iopaen; // [2:2] I/O port A clock enable + Object *iopben; // [3:3] I/O port B clock enable + Object *iopcen; // [4:4] I/O port C clock enable + Object *iopden; // [5:5] I/O port D clock enable + Object *iopeen; // [6:6] I/O port E clock enable + Object *iopfen; // [7:7] I/O port F clock enable + Object *iopgen; // [8:8] I/O port G clock enable + Object *adc1en; // [9:9] ADC 1 interface clock enable + Object *adc2en; // [10:10] ADC 2 interface clock enable + Object *tim1en; // [11:11] TIM1 Timer clock enable + Object *spi1en; // [12:12] SPI 1 clock enable + Object *tim8en; // [13:13] TIM8 Timer clock enable + Object *usart1en; // [14:14] USART1 clock enable + Object *adc3en; // [15:15] ADC3 interface clock enable + Object *tim9en; // [19:19] TIM9 Timer clock enable + Object *tim10en; // [20:20] TIM10 Timer clock enable + Object *tim11en; // [21:21] TIM11 Timer clock enable + } apb2enr; + + // APB1ENR (APB1 peripheral clock enable register (RCC_APB1ENR)) bitfields. + struct { + Object *tim2en; // [0:0] Timer 2 clock enable + Object *tim3en; // [1:1] Timer 3 clock enable + Object *tim4en; // [2:2] Timer 4 clock enable + Object *tim5en; // [3:3] Timer 5 clock enable + Object *tim6en; // [4:4] Timer 6 clock enable + Object *tim7en; // [5:5] Timer 7 clock enable + Object *tim12en; // [6:6] Timer 12 clock enable + Object *tim13en; // [7:7] Timer 13 clock enable + Object *tim14en; // [8:8] Timer 14 clock enable + Object *wwdgen; // [11:11] Window watchdog clock enable + Object *spi2en; // [14:14] SPI 2 clock enable + Object *spi3en; // [15:15] SPI 3 clock enable + Object *usart2en; // [17:17] USART 2 clock enable + Object *usart3en; // [18:18] USART 3 clock enable + Object *uart4en; // [19:19] UART 4 clock enable + Object *uart5en; // [20:20] UART 5 clock enable + Object *i2c1en; // [21:21] I2C 1 clock enable + Object *i2c2en; // [22:22] I2C 2 clock enable + Object *usben; // [23:23] USB clock enable + Object *canen; // [25:25] CAN clock enable + Object *bkpen; // [27:27] Backup interface clock enable + Object *pwren; // [28:28] Power interface clock enable + Object *dacen; // [29:29] DAC interface clock enable + } apb1enr; + + // BDCR (Backup domain control register (RCC_BDCR)) bitfields. + struct { + Object *lseon; // [0:0] External Low Speed oscillator enable + Object *lserdy; // [1:1] External Low Speed oscillator ready + Object *lsebyp; // [2:2] External Low Speed oscillator bypass + Object *rtcsel; // [8:9] RTC clock source selection + Object *rtcen; // [15:15] RTC clock enable + Object *bdrst; // [16:16] Backup domain software reset + } bdcr; + + // CSR (Control/status register (RCC_CSR)) bitfields. + struct { + Object *lsion; // [0:0] Internal low speed oscillator enable + Object *lsirdy; // [1:1] Internal low speed oscillator ready + Object *rmvf; // [24:24] Remove reset flag + Object *pinrstf; // [26:26] PIN reset flag + Object *porrstf; // [27:27] POR/PDR reset flag + Object *sftrstf; // [28:28] Software reset flag + Object *iwdgrstf; // [29:29] Independent watchdog reset flag + Object *wwdgrstf; // [30:30] Window watchdog reset flag + Object *lpwrrstf; // [31:31] Low-power reset flag + } csr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RCCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RCC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/rtc.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/rtc.c new file mode 100644 index 0000000000..9cf6b45919 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/rtc.c @@ -0,0 +1,281 @@ +/* + * STM32 - RTC (Real time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_rtc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.crh = cm_object_get_child_by_name(obj, "CRH"); + state->u.f1.reg.crl = cm_object_get_child_by_name(obj, "CRL"); + state->u.f1.reg.prlh = cm_object_get_child_by_name(obj, "PRLH"); + state->u.f1.reg.prll = cm_object_get_child_by_name(obj, "PRLL"); + state->u.f1.reg.divh = cm_object_get_child_by_name(obj, "DIVH"); + state->u.f1.reg.divl = cm_object_get_child_by_name(obj, "DIVL"); + state->u.f1.reg.cnth = cm_object_get_child_by_name(obj, "CNTH"); + state->u.f1.reg.cntl = cm_object_get_child_by_name(obj, "CNTL"); + state->u.f1.reg.alrh = cm_object_get_child_by_name(obj, "ALRH"); + state->u.f1.reg.alrl = cm_object_get_child_by_name(obj, "ALRL"); + + + // CRH bitfields. + state->u.f1.fld.crh.secie = cm_object_get_child_by_name(state->u.f1.reg.crh, "SECIE"); + state->u.f1.fld.crh.alrie = cm_object_get_child_by_name(state->u.f1.reg.crh, "ALRIE"); + state->u.f1.fld.crh.owie = cm_object_get_child_by_name(state->u.f1.reg.crh, "OWIE"); + + // CRL bitfields. + state->u.f1.fld.crl.secf = cm_object_get_child_by_name(state->u.f1.reg.crl, "SECF"); + state->u.f1.fld.crl.alrf = cm_object_get_child_by_name(state->u.f1.reg.crl, "ALRF"); + state->u.f1.fld.crl.owf = cm_object_get_child_by_name(state->u.f1.reg.crl, "OWF"); + state->u.f1.fld.crl.rsf = cm_object_get_child_by_name(state->u.f1.reg.crl, "RSF"); + state->u.f1.fld.crl.cnf = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF"); + state->u.f1.fld.crl.rtoff = cm_object_get_child_by_name(state->u.f1.reg.crl, "RTOFF"); + + // PRLH bitfields. + state->u.f1.fld.prlh.prlh = cm_object_get_child_by_name(state->u.f1.reg.prlh, "PRLH"); + + // PRLL bitfields. + state->u.f1.fld.prll.prll = cm_object_get_child_by_name(state->u.f1.reg.prll, "PRLL"); + + // DIVH bitfields. + state->u.f1.fld.divh.divh = cm_object_get_child_by_name(state->u.f1.reg.divh, "DIVH"); + + // DIVL bitfields. + state->u.f1.fld.divl.divl = cm_object_get_child_by_name(state->u.f1.reg.divl, "DIVL"); + + // CNTH bitfields. + state->u.f1.fld.cnth.cnth = cm_object_get_child_by_name(state->u.f1.reg.cnth, "CNTH"); + + // CNTL bitfields. + state->u.f1.fld.cntl.cntl = cm_object_get_child_by_name(state->u.f1.reg.cntl, "CNTL"); + + // ALRH bitfields. + state->u.f1.fld.alrh.alrh = cm_object_get_child_by_name(state->u.f1.reg.alrh, "ALRH"); + + // ALRL bitfields. + state->u.f1.fld.alrl.alrl = cm_object_get_child_by_name(state->u.f1.reg.alrl, "ALRL"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rtc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rtc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rtc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rtc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rtc_is_enabled(Object *obj) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rtc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RTCState *state = STM32_RTC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rtc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RTC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RTCState *state = STM32_RTC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RTC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_rtc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rtc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_rtc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rtc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_rtc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RTCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rtc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RTC); +} + +static void stm32_rtc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rtc_reset_callback; + dc->realize = stm32_rtc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rtc_is_enabled; +} + +static const TypeInfo stm32_rtc_type_info = { + .name = TYPE_STM32_RTC, + .parent = TYPE_STM32_RTC_PARENT, + .instance_init = stm32_rtc_instance_init_callback, + .instance_size = sizeof(STM32RTCState), + .class_init = stm32_rtc_class_init_callback, + .class_size = sizeof(STM32RTCClass) }; + +static void stm32_rtc_register_types(void) +{ + type_register_static(&stm32_rtc_type_info); +} + +type_init(stm32_rtc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/rtc.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/rtc.h new file mode 100644 index 0000000000..36b03457b1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/rtc.h @@ -0,0 +1,166 @@ +/* + * STM32 - RTC (Real time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RTC_H_ +#define STM32_RTC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RTC DEVICE_PATH_STM32 "RTC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RTC TYPE_STM32_PREFIX "rtc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RTC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RTCParentClass; +typedef PeripheralState STM32RTCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RTCClass, (obj), TYPE_STM32_RTC) +#define STM32_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RTCClass, (klass), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentClass parent_class; + // public: + + // None, so far. +} STM32RTCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RTC_STATE(obj) \ + OBJECT_CHECK(STM32RTCState, (obj), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 RTC (Real time clock) registers. + struct { + Object *crh; // 0x0 (RTC Control Register High) + Object *crl; // 0x4 (RTC Control Register Low) + Object *prlh; // 0x8 (RTC Prescaler Load Register High) + Object *prll; // 0xC (RTC Prescaler Load Register Low) + Object *divh; // 0x10 (RTC Prescaler Divider Register High) + Object *divl; // 0x14 (RTC Prescaler Divider Register Low) + Object *cnth; // 0x18 (RTC Counter Register High) + Object *cntl; // 0x1C (RTC Counter Register Low) + Object *alrh; // 0x20 (RTC Alarm Register High) + Object *alrl; // 0x24 (RTC Alarm Register Low) + } reg; + + struct { + + // CRH (RTC Control Register High) bitfields. + struct { + Object *secie; // [0:0] Second interrupt Enable + Object *alrie; // [1:1] Alarm interrupt Enable + Object *owie; // [2:2] Overflow interrupt Enable + } crh; + + // CRL (RTC Control Register Low) bitfields. + struct { + Object *secf; // [0:0] Second Flag + Object *alrf; // [1:1] Alarm Flag + Object *owf; // [2:2] Overflow Flag + Object *rsf; // [3:3] Registers Synchronized Flag + Object *cnf; // [4:4] Configuration Flag + Object *rtoff; // [5:5] RTC operation OFF + } crl; + + // PRLH (RTC Prescaler Load Register High) bitfields. + struct { + Object *prlh; // [0:3] RTC Prescaler Load Register High + } prlh; + + // PRLL (RTC Prescaler Load Register Low) bitfields. + struct { + Object *prll; // [0:15] RTC Prescaler Divider Register Low + } prll; + + // DIVH (RTC Prescaler Divider Register High) bitfields. + struct { + Object *divh; // [0:3] RTC prescaler divider register high + } divh; + + // DIVL (RTC Prescaler Divider Register Low) bitfields. + struct { + Object *divl; // [0:15] RTC prescaler divider register Low + } divl; + + // CNTH (RTC Counter Register High) bitfields. + struct { + Object *cnth; // [0:15] RTC counter register high + } cnth; + + // CNTL (RTC Counter Register Low) bitfields. + struct { + Object *cntl; // [0:15] RTC counter register Low + } cntl; + + // ALRH (RTC Alarm Register High) bitfields. + struct { + Object *alrh; // [0:15] RTC alarm register high + } alrh; + + // ALRL (RTC Alarm Register Low) bitfields. + struct { + Object *alrl; // [0:15] RTC alarm register low + } alrl; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RTCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RTC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/sdio.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/sdio.c new file mode 100644 index 0000000000..b88dabfaa8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/sdio.c @@ -0,0 +1,386 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_sdio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.power = cm_object_get_child_by_name(obj, "POWER"); + state->u.f1.reg.clkcr = cm_object_get_child_by_name(obj, "CLKCR"); + state->u.f1.reg.arg = cm_object_get_child_by_name(obj, "ARG"); + state->u.f1.reg.cmd = cm_object_get_child_by_name(obj, "CMD"); + state->u.f1.reg.respcmd = cm_object_get_child_by_name(obj, "RESPCMD"); + state->u.f1.reg.respi1 = cm_object_get_child_by_name(obj, "RESPI1"); + state->u.f1.reg.resp2 = cm_object_get_child_by_name(obj, "RESP2"); + state->u.f1.reg.resp3 = cm_object_get_child_by_name(obj, "RESP3"); + state->u.f1.reg.resp4 = cm_object_get_child_by_name(obj, "RESP4"); + state->u.f1.reg.dtimer = cm_object_get_child_by_name(obj, "DTIMER"); + state->u.f1.reg.dlen = cm_object_get_child_by_name(obj, "DLEN"); + state->u.f1.reg.dctrl = cm_object_get_child_by_name(obj, "DCTRL"); + state->u.f1.reg.dcount = cm_object_get_child_by_name(obj, "DCOUNT"); + state->u.f1.reg.sta = cm_object_get_child_by_name(obj, "STA"); + state->u.f1.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f1.reg.mask = cm_object_get_child_by_name(obj, "MASK"); + state->u.f1.reg.fifocnt = cm_object_get_child_by_name(obj, "FIFOCNT"); + state->u.f1.reg.fifo = cm_object_get_child_by_name(obj, "FIFO"); + + + // POWER bitfields. + state->u.f1.fld.power.pwrctrl = cm_object_get_child_by_name(state->u.f1.reg.power, "PWRCTRL"); + + // CLKCR bitfields. + state->u.f1.fld.clkcr.clkdiv = cm_object_get_child_by_name(state->u.f1.reg.clkcr, "CLKDIV"); + state->u.f1.fld.clkcr.clken = cm_object_get_child_by_name(state->u.f1.reg.clkcr, "CLKEN"); + state->u.f1.fld.clkcr.pwrsav = cm_object_get_child_by_name(state->u.f1.reg.clkcr, "PWRSAV"); + state->u.f1.fld.clkcr.bypass = cm_object_get_child_by_name(state->u.f1.reg.clkcr, "BYPASS"); + state->u.f1.fld.clkcr.widbus = cm_object_get_child_by_name(state->u.f1.reg.clkcr, "WIDBUS"); + state->u.f1.fld.clkcr.negedge = cm_object_get_child_by_name(state->u.f1.reg.clkcr, "NEGEDGE"); + state->u.f1.fld.clkcr.hwfc_en = cm_object_get_child_by_name(state->u.f1.reg.clkcr, "HWFC_EN"); + + // ARG bitfields. + state->u.f1.fld.arg.cmdarg = cm_object_get_child_by_name(state->u.f1.reg.arg, "CMDARG"); + + // CMD bitfields. + state->u.f1.fld.cmd.cmdindex = cm_object_get_child_by_name(state->u.f1.reg.cmd, "CMDINDEX"); + state->u.f1.fld.cmd.waitresp = cm_object_get_child_by_name(state->u.f1.reg.cmd, "WAITRESP"); + state->u.f1.fld.cmd.waitint = cm_object_get_child_by_name(state->u.f1.reg.cmd, "WAITINT"); + state->u.f1.fld.cmd.waitpend = cm_object_get_child_by_name(state->u.f1.reg.cmd, "WAITPEND"); + state->u.f1.fld.cmd.cpsmen = cm_object_get_child_by_name(state->u.f1.reg.cmd, "CPSMEN"); + state->u.f1.fld.cmd.sdiosuspend = cm_object_get_child_by_name(state->u.f1.reg.cmd, "SDIOSuspend"); + state->u.f1.fld.cmd.encmdcompl = cm_object_get_child_by_name(state->u.f1.reg.cmd, "ENCMDcompl"); + state->u.f1.fld.cmd.nien = cm_object_get_child_by_name(state->u.f1.reg.cmd, "nIEN"); + state->u.f1.fld.cmd.ce_atacmd = cm_object_get_child_by_name(state->u.f1.reg.cmd, "CE_ATACMD"); + + // RESPCMD bitfields. + state->u.f1.fld.respcmd.respcmd = cm_object_get_child_by_name(state->u.f1.reg.respcmd, "RESPCMD"); + + // RESPI1 bitfields. + state->u.f1.fld.respi1.cardstatus1 = cm_object_get_child_by_name(state->u.f1.reg.respi1, "CARDSTATUS1"); + + // RESP2 bitfields. + state->u.f1.fld.resp2.cardstatus2 = cm_object_get_child_by_name(state->u.f1.reg.resp2, "CARDSTATUS2"); + + // RESP3 bitfields. + state->u.f1.fld.resp3.cardstatus3 = cm_object_get_child_by_name(state->u.f1.reg.resp3, "CARDSTATUS3"); + + // RESP4 bitfields. + state->u.f1.fld.resp4.cardstatus4 = cm_object_get_child_by_name(state->u.f1.reg.resp4, "CARDSTATUS4"); + + // DTIMER bitfields. + state->u.f1.fld.dtimer.datatime = cm_object_get_child_by_name(state->u.f1.reg.dtimer, "DATATIME"); + + // DLEN bitfields. + state->u.f1.fld.dlen.datalength = cm_object_get_child_by_name(state->u.f1.reg.dlen, "DATALENGTH"); + + // DCTRL bitfields. + state->u.f1.fld.dctrl.dten = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "DTEN"); + state->u.f1.fld.dctrl.dtdir = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "DTDIR"); + state->u.f1.fld.dctrl.dtmode = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "DTMODE"); + state->u.f1.fld.dctrl.dmaen = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "DMAEN"); + state->u.f1.fld.dctrl.dblocksize = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "DBLOCKSIZE"); + state->u.f1.fld.dctrl.pwstart = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "PWSTART"); + state->u.f1.fld.dctrl.pwstop = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "PWSTOP"); + state->u.f1.fld.dctrl.rwmod = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "RWMOD"); + state->u.f1.fld.dctrl.sdioen = cm_object_get_child_by_name(state->u.f1.reg.dctrl, "SDIOEN"); + + // DCOUNT bitfields. + state->u.f1.fld.dcount.datacount = cm_object_get_child_by_name(state->u.f1.reg.dcount, "DATACOUNT"); + + // STA bitfields. + state->u.f1.fld.sta.ccrcfail = cm_object_get_child_by_name(state->u.f1.reg.sta, "CCRCFAIL"); + state->u.f1.fld.sta.dcrcfail = cm_object_get_child_by_name(state->u.f1.reg.sta, "DCRCFAIL"); + state->u.f1.fld.sta.ctimeout = cm_object_get_child_by_name(state->u.f1.reg.sta, "CTIMEOUT"); + state->u.f1.fld.sta.dtimeout = cm_object_get_child_by_name(state->u.f1.reg.sta, "DTIMEOUT"); + state->u.f1.fld.sta.txunderr = cm_object_get_child_by_name(state->u.f1.reg.sta, "TXUNDERR"); + state->u.f1.fld.sta.rxoverr = cm_object_get_child_by_name(state->u.f1.reg.sta, "RXOVERR"); + state->u.f1.fld.sta.cmdrend = cm_object_get_child_by_name(state->u.f1.reg.sta, "CMDREND"); + state->u.f1.fld.sta.cmdsent = cm_object_get_child_by_name(state->u.f1.reg.sta, "CMDSENT"); + state->u.f1.fld.sta.dataend = cm_object_get_child_by_name(state->u.f1.reg.sta, "DATAEND"); + state->u.f1.fld.sta.stbiterr = cm_object_get_child_by_name(state->u.f1.reg.sta, "STBITERR"); + state->u.f1.fld.sta.dbckend = cm_object_get_child_by_name(state->u.f1.reg.sta, "DBCKEND"); + state->u.f1.fld.sta.cmdact = cm_object_get_child_by_name(state->u.f1.reg.sta, "CMDACT"); + state->u.f1.fld.sta.txact = cm_object_get_child_by_name(state->u.f1.reg.sta, "TXACT"); + state->u.f1.fld.sta.rxact = cm_object_get_child_by_name(state->u.f1.reg.sta, "RXACT"); + state->u.f1.fld.sta.txfifohe = cm_object_get_child_by_name(state->u.f1.reg.sta, "TXFIFOHE"); + state->u.f1.fld.sta.rxfifohf = cm_object_get_child_by_name(state->u.f1.reg.sta, "RXFIFOHF"); + state->u.f1.fld.sta.txfifof = cm_object_get_child_by_name(state->u.f1.reg.sta, "TXFIFOF"); + state->u.f1.fld.sta.rxfifof = cm_object_get_child_by_name(state->u.f1.reg.sta, "RXFIFOF"); + state->u.f1.fld.sta.txfifoe = cm_object_get_child_by_name(state->u.f1.reg.sta, "TXFIFOE"); + state->u.f1.fld.sta.rxfifoe = cm_object_get_child_by_name(state->u.f1.reg.sta, "RXFIFOE"); + state->u.f1.fld.sta.txdavl = cm_object_get_child_by_name(state->u.f1.reg.sta, "TXDAVL"); + state->u.f1.fld.sta.rxdavl = cm_object_get_child_by_name(state->u.f1.reg.sta, "RXDAVL"); + state->u.f1.fld.sta.sdioit = cm_object_get_child_by_name(state->u.f1.reg.sta, "SDIOIT"); + state->u.f1.fld.sta.ceataend = cm_object_get_child_by_name(state->u.f1.reg.sta, "CEATAEND"); + + // ICR bitfields. + state->u.f1.fld.icr.ccrcfailc = cm_object_get_child_by_name(state->u.f1.reg.icr, "CCRCFAILC"); + state->u.f1.fld.icr.dcrcfailc = cm_object_get_child_by_name(state->u.f1.reg.icr, "DCRCFAILC"); + state->u.f1.fld.icr.ctimeoutc = cm_object_get_child_by_name(state->u.f1.reg.icr, "CTIMEOUTC"); + state->u.f1.fld.icr.dtimeoutc = cm_object_get_child_by_name(state->u.f1.reg.icr, "DTIMEOUTC"); + state->u.f1.fld.icr.txunderrc = cm_object_get_child_by_name(state->u.f1.reg.icr, "TXUNDERRC"); + state->u.f1.fld.icr.rxoverrc = cm_object_get_child_by_name(state->u.f1.reg.icr, "RXOVERRC"); + state->u.f1.fld.icr.cmdrendc = cm_object_get_child_by_name(state->u.f1.reg.icr, "CMDRENDC"); + state->u.f1.fld.icr.cmdsentc = cm_object_get_child_by_name(state->u.f1.reg.icr, "CMDSENTC"); + state->u.f1.fld.icr.dataendc = cm_object_get_child_by_name(state->u.f1.reg.icr, "DATAENDC"); + state->u.f1.fld.icr.stbiterrc = cm_object_get_child_by_name(state->u.f1.reg.icr, "STBITERRC"); + state->u.f1.fld.icr.dbckendc = cm_object_get_child_by_name(state->u.f1.reg.icr, "DBCKENDC"); + state->u.f1.fld.icr.sdioitc = cm_object_get_child_by_name(state->u.f1.reg.icr, "SDIOITC"); + state->u.f1.fld.icr.ceataendc = cm_object_get_child_by_name(state->u.f1.reg.icr, "CEATAENDC"); + + // MASK bitfields. + state->u.f1.fld.mask.ccrcfailie = cm_object_get_child_by_name(state->u.f1.reg.mask, "CCRCFAILIE"); + state->u.f1.fld.mask.dcrcfailie = cm_object_get_child_by_name(state->u.f1.reg.mask, "DCRCFAILIE"); + state->u.f1.fld.mask.ctimeoutie = cm_object_get_child_by_name(state->u.f1.reg.mask, "CTIMEOUTIE"); + state->u.f1.fld.mask.dtimeoutie = cm_object_get_child_by_name(state->u.f1.reg.mask, "DTIMEOUTIE"); + state->u.f1.fld.mask.txunderrie = cm_object_get_child_by_name(state->u.f1.reg.mask, "TXUNDERRIE"); + state->u.f1.fld.mask.rxoverrie = cm_object_get_child_by_name(state->u.f1.reg.mask, "RXOVERRIE"); + state->u.f1.fld.mask.cmdrendie = cm_object_get_child_by_name(state->u.f1.reg.mask, "CMDRENDIE"); + state->u.f1.fld.mask.cmdsentie = cm_object_get_child_by_name(state->u.f1.reg.mask, "CMDSENTIE"); + state->u.f1.fld.mask.dataendie = cm_object_get_child_by_name(state->u.f1.reg.mask, "DATAENDIE"); + state->u.f1.fld.mask.stbiterrie = cm_object_get_child_by_name(state->u.f1.reg.mask, "STBITERRIE"); + state->u.f1.fld.mask.dbackendie = cm_object_get_child_by_name(state->u.f1.reg.mask, "DBACKENDIE"); + state->u.f1.fld.mask.cmdactie = cm_object_get_child_by_name(state->u.f1.reg.mask, "CMDACTIE"); + state->u.f1.fld.mask.txactie = cm_object_get_child_by_name(state->u.f1.reg.mask, "TXACTIE"); + state->u.f1.fld.mask.rxactie = cm_object_get_child_by_name(state->u.f1.reg.mask, "RXACTIE"); + state->u.f1.fld.mask.txfifoheie = cm_object_get_child_by_name(state->u.f1.reg.mask, "TXFIFOHEIE"); + state->u.f1.fld.mask.rxfifohfie = cm_object_get_child_by_name(state->u.f1.reg.mask, "RXFIFOHFIE"); + state->u.f1.fld.mask.txfifofie = cm_object_get_child_by_name(state->u.f1.reg.mask, "TXFIFOFIE"); + state->u.f1.fld.mask.rxfifofie = cm_object_get_child_by_name(state->u.f1.reg.mask, "RXFIFOFIE"); + state->u.f1.fld.mask.txfifoeie = cm_object_get_child_by_name(state->u.f1.reg.mask, "TXFIFOEIE"); + state->u.f1.fld.mask.rxfifoeie = cm_object_get_child_by_name(state->u.f1.reg.mask, "RXFIFOEIE"); + state->u.f1.fld.mask.txdavlie = cm_object_get_child_by_name(state->u.f1.reg.mask, "TXDAVLIE"); + state->u.f1.fld.mask.rxdavlie = cm_object_get_child_by_name(state->u.f1.reg.mask, "RXDAVLIE"); + state->u.f1.fld.mask.sdioitie = cm_object_get_child_by_name(state->u.f1.reg.mask, "SDIOITIE"); + state->u.f1.fld.mask.ceatendie = cm_object_get_child_by_name(state->u.f1.reg.mask, "CEATENDIE"); + + // FIFOCNT bitfields. + state->u.f1.fld.fifocnt.fif0count = cm_object_get_child_by_name(state->u.f1.reg.fifocnt, "FIF0COUNT"); + + // FIFO bitfields. + state->u.f1.fld.fifo.fifodata = cm_object_get_child_by_name(state->u.f1.reg.fifo, "FIFOData"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_sdio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_sdio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_sdio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_sdio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_sdio_is_enabled(Object *obj) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_sdio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_sdio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SDIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SDIOState *state = STM32_SDIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SDIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_sdio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_sdio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_sdio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_sdio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_sdio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SDIOEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_sdio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SDIO); +} + +static void stm32_sdio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_sdio_reset_callback; + dc->realize = stm32_sdio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_sdio_is_enabled; +} + +static const TypeInfo stm32_sdio_type_info = { + .name = TYPE_STM32_SDIO, + .parent = TYPE_STM32_SDIO_PARENT, + .instance_init = stm32_sdio_instance_init_callback, + .instance_size = sizeof(STM32SDIOState), + .class_init = stm32_sdio_class_init_callback, + .class_size = sizeof(STM32SDIOClass) }; + +static void stm32_sdio_register_types(void) +{ + type_register_static(&stm32_sdio_type_info); +} + +type_init(stm32_sdio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/sdio.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/sdio.h new file mode 100644 index 0000000000..afb2f97b19 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/sdio.h @@ -0,0 +1,287 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SDIO_H_ +#define STM32_SDIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SDIO DEVICE_PATH_STM32 "SDIO" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SDIO TYPE_STM32_PREFIX "sdio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SDIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SDIOParentClass; +typedef PeripheralState STM32SDIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SDIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SDIOClass, (obj), TYPE_STM32_SDIO) +#define STM32_SDIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SDIOClass, (klass), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentClass parent_class; + // public: + + // None, so far. +} STM32SDIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SDIO_STATE(obj) \ + OBJECT_CHECK(STM32SDIOState, (obj), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 SDIO (Secure digital input/output interface) registers. + struct { + Object *power; // 0x0 (Bits 1:0 = PWRCTRL: Power supply control bits) + Object *clkcr; // 0x4 (SDI clock control register (SDIO_CLKCR)) + Object *arg; // 0x8 (Bits 31:0 = : Command argument) + Object *cmd; // 0xC (SDIO command register (SDIO_CMD)) + Object *respcmd; // 0x10 (SDIO command register) + Object *respi1; // 0x14 (Bits 31:0 = CARDSTATUS1) + Object *resp2; // 0x18 (Bits 31:0 = CARDSTATUS2) + Object *resp3; // 0x1C (Bits 31:0 = CARDSTATUS3) + Object *resp4; // 0x20 (Bits 31:0 = CARDSTATUS4) + Object *dtimer; // 0x24 (Bits 31:0 = DATATIME: Data timeout period) + Object *dlen; // 0x28 (Bits 24:0 = DATALENGTH: Data length value) + Object *dctrl; // 0x2C (SDIO data control register (SDIO_DCTRL)) + Object *dcount; // 0x30 (Bits 24:0 = DATACOUNT: Data count value) + Object *sta; // 0x34 (SDIO status register (SDIO_STA)) + Object *icr; // 0x38 (SDIO interrupt clear register (SDIO_ICR)) + Object *mask; // 0x3C (SDIO mask register (SDIO_MASK)) + Object *fifocnt; // 0x48 (Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO) + Object *fifo; // 0x80 (Bits 31:0 = FIFOData: Receive and transmit FIFO data) + } reg; + + struct { + + // POWER (Bits 1:0 = PWRCTRL: Power supply control bits) bitfields. + struct { + Object *pwrctrl; // [0:1] PWRCTRL + } power; + + // CLKCR (SDI clock control register (SDIO_CLKCR)) bitfields. + struct { + Object *clkdiv; // [0:7] Clock divide factor + Object *clken; // [8:8] Clock enable bit + Object *pwrsav; // [9:9] Power saving configuration bit + Object *bypass; // [10:10] Clock divider bypass enable bit + Object *widbus; // [11:12] Wide bus mode enable bit + Object *negedge; // [13:13] SDIO_CK dephasing selection bit + Object *hwfc_en; // [14:14] HW Flow Control enable + } clkcr; + + // ARG (Bits 31:0 = : Command argument) bitfields. + struct { + Object *cmdarg; // [0:31] Command argument + } arg; + + // CMD (SDIO command register (SDIO_CMD)) bitfields. + struct { + Object *cmdindex; // [0:5] CMDINDEX + Object *waitresp; // [6:7] WAITRESP + Object *waitint; // [8:8] WAITINT + Object *waitpend; // [9:9] WAITPEND + Object *cpsmen; // [10:10] CPSMEN + Object *sdiosuspend; // [11:11] SDIOSuspend + Object *encmdcompl; // [12:12] ENCMDcompl + Object *nien; // [13:13] NIEN + Object *ce_atacmd; // [14:14] CE_ATACMD + } cmd; + + // RESPCMD (SDIO command register) bitfields. + struct { + Object *respcmd; // [0:5] RESPCMD + } respcmd; + + // RESPI1 (Bits 31:0 = CARDSTATUS1) bitfields. + struct { + Object *cardstatus1; // [0:31] CARDSTATUS1 + } respi1; + + // RESP2 (Bits 31:0 = CARDSTATUS2) bitfields. + struct { + Object *cardstatus2; // [0:31] CARDSTATUS2 + } resp2; + + // RESP3 (Bits 31:0 = CARDSTATUS3) bitfields. + struct { + Object *cardstatus3; // [0:31] CARDSTATUS3 + } resp3; + + // RESP4 (Bits 31:0 = CARDSTATUS4) bitfields. + struct { + Object *cardstatus4; // [0:31] CARDSTATUS4 + } resp4; + + // DTIMER (Bits 31:0 = DATATIME: Data timeout period) bitfields. + struct { + Object *datatime; // [0:31] Data timeout period + } dtimer; + + // DLEN (Bits 24:0 = DATALENGTH: Data length value) bitfields. + struct { + Object *datalength; // [0:24] Data length value + } dlen; + + // DCTRL (SDIO data control register (SDIO_DCTRL)) bitfields. + struct { + Object *dten; // [0:0] DTEN + Object *dtdir; // [1:1] DTDIR + Object *dtmode; // [2:2] DTMODE + Object *dmaen; // [3:3] DMAEN + Object *dblocksize; // [4:7] DBLOCKSIZE + Object *pwstart; // [8:8] PWSTART + Object *pwstop; // [9:9] PWSTOP + Object *rwmod; // [10:10] RWMOD + Object *sdioen; // [11:11] SDIOEN + } dctrl; + + // DCOUNT (Bits 24:0 = DATACOUNT: Data count value) bitfields. + struct { + Object *datacount; // [0:24] Data count value + } dcount; + + // STA (SDIO status register (SDIO_STA)) bitfields. + struct { + Object *ccrcfail; // [0:0] CCRCFAIL + Object *dcrcfail; // [1:1] DCRCFAIL + Object *ctimeout; // [2:2] CTIMEOUT + Object *dtimeout; // [3:3] DTIMEOUT + Object *txunderr; // [4:4] TXUNDERR + Object *rxoverr; // [5:5] RXOVERR + Object *cmdrend; // [6:6] CMDREND + Object *cmdsent; // [7:7] CMDSENT + Object *dataend; // [8:8] DATAEND + Object *stbiterr; // [9:9] STBITERR + Object *dbckend; // [10:10] DBCKEND + Object *cmdact; // [11:11] CMDACT + Object *txact; // [12:12] TXACT + Object *rxact; // [13:13] RXACT + Object *txfifohe; // [14:14] TXFIFOHE + Object *rxfifohf; // [15:15] RXFIFOHF + Object *txfifof; // [16:16] TXFIFOF + Object *rxfifof; // [17:17] RXFIFOF + Object *txfifoe; // [18:18] TXFIFOE + Object *rxfifoe; // [19:19] RXFIFOE + Object *txdavl; // [20:20] TXDAVL + Object *rxdavl; // [21:21] RXDAVL + Object *sdioit; // [22:22] SDIOIT + Object *ceataend; // [23:23] CEATAEND + } sta; + + // ICR (SDIO interrupt clear register (SDIO_ICR)) bitfields. + struct { + Object *ccrcfailc; // [0:0] CCRCFAILC + Object *dcrcfailc; // [1:1] DCRCFAILC + Object *ctimeoutc; // [2:2] CTIMEOUTC + Object *dtimeoutc; // [3:3] DTIMEOUTC + Object *txunderrc; // [4:4] TXUNDERRC + Object *rxoverrc; // [5:5] RXOVERRC + Object *cmdrendc; // [6:6] CMDRENDC + Object *cmdsentc; // [7:7] CMDSENTC + Object *dataendc; // [8:8] DATAENDC + Object *stbiterrc; // [9:9] STBITERRC + Object *dbckendc; // [10:10] DBCKENDC + Object *sdioitc; // [22:22] SDIOITC + Object *ceataendc; // [23:23] CEATAENDC + } icr; + + // MASK (SDIO mask register (SDIO_MASK)) bitfields. + struct { + Object *ccrcfailie; // [0:0] CCRCFAILIE + Object *dcrcfailie; // [1:1] DCRCFAILIE + Object *ctimeoutie; // [2:2] CTIMEOUTIE + Object *dtimeoutie; // [3:3] DTIMEOUTIE + Object *txunderrie; // [4:4] TXUNDERRIE + Object *rxoverrie; // [5:5] RXOVERRIE + Object *cmdrendie; // [6:6] CMDRENDIE + Object *cmdsentie; // [7:7] CMDSENTIE + Object *dataendie; // [8:8] DATAENDIE + Object *stbiterrie; // [9:9] STBITERRIE + Object *dbackendie; // [10:10] DBACKENDIE + Object *cmdactie; // [11:11] CMDACTIE + Object *txactie; // [12:12] TXACTIE + Object *rxactie; // [13:13] RXACTIE + Object *txfifoheie; // [14:14] TXFIFOHEIE + Object *rxfifohfie; // [15:15] RXFIFOHFIE + Object *txfifofie; // [16:16] TXFIFOFIE + Object *rxfifofie; // [17:17] RXFIFOFIE + Object *txfifoeie; // [18:18] TXFIFOEIE + Object *rxfifoeie; // [19:19] RXFIFOEIE + Object *txdavlie; // [20:20] TXDAVLIE + Object *rxdavlie; // [21:21] RXDAVLIE + Object *sdioitie; // [22:22] SDIOITIE + Object *ceatendie; // [23:23] CEATENDIE + } mask; + + // FIFOCNT (Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO) bitfields. + struct { + Object *fif0count; // [0:23] FIF0COUNT + } fifocnt; + + // FIFO (Bits 31:0 = FIFOData: Receive and transmit FIFO data) bitfields. + struct { + Object *fifodata; // [0:31] FIFOData + } fifo; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SDIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SDIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/spi1.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/spi1.c new file mode 100644 index 0000000000..fb0ecbf366 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/spi1.c @@ -0,0 +1,309 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_spi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.crcpr = cm_object_get_child_by_name(obj, "CRCPR"); + state->u.f1.reg.rxcrcr = cm_object_get_child_by_name(obj, "RXCRCR"); + state->u.f1.reg.txcrcr = cm_object_get_child_by_name(obj, "TXCRCR"); + state->u.f1.reg.i2scfgr = cm_object_get_child_by_name(obj, "I2SCFGR"); + state->u.f1.reg.i2spr = cm_object_get_child_by_name(obj, "I2SPR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cpha = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CPHA"); + state->u.f1.fld.cr1.cpol = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CPOL"); + state->u.f1.fld.cr1.mstr = cm_object_get_child_by_name(state->u.f1.reg.cr1, "MSTR"); + state->u.f1.fld.cr1.br = cm_object_get_child_by_name(state->u.f1.reg.cr1, "BR"); + state->u.f1.fld.cr1.spe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SPE"); + state->u.f1.fld.cr1.lsbfirst = cm_object_get_child_by_name(state->u.f1.reg.cr1, "LSBFIRST"); + state->u.f1.fld.cr1.ssi = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SSI"); + state->u.f1.fld.cr1.ssm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SSM"); + state->u.f1.fld.cr1.rxonly = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXONLY"); + state->u.f1.fld.cr1.dff = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DFF"); + state->u.f1.fld.cr1.crcnext = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CRCNEXT"); + state->u.f1.fld.cr1.crcen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CRCEN"); + state->u.f1.fld.cr1.bidioe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "BIDIOE"); + state->u.f1.fld.cr1.bidimode = cm_object_get_child_by_name(state->u.f1.reg.cr1, "BIDIMODE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.rxdmaen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RXDMAEN"); + state->u.f1.fld.cr2.txdmaen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TXDMAEN"); + state->u.f1.fld.cr2.ssoe = cm_object_get_child_by_name(state->u.f1.reg.cr2, "SSOE"); + state->u.f1.fld.cr2.errie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ERRIE"); + state->u.f1.fld.cr2.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RXNEIE"); + state->u.f1.fld.cr2.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TXEIE"); + + // SR bitfields. + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.chside = cm_object_get_child_by_name(state->u.f1.reg.sr, "CHSIDE"); + state->u.f1.fld.sr.udr = cm_object_get_child_by_name(state->u.f1.reg.sr, "UDR"); + state->u.f1.fld.sr.crcerr = cm_object_get_child_by_name(state->u.f1.reg.sr, "CRCERR"); + state->u.f1.fld.sr.modf = cm_object_get_child_by_name(state->u.f1.reg.sr, "MODF"); + state->u.f1.fld.sr.ovr = cm_object_get_child_by_name(state->u.f1.reg.sr, "OVR"); + state->u.f1.fld.sr.bsy = cm_object_get_child_by_name(state->u.f1.reg.sr, "BSY"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // CRCPR bitfields. + state->u.f1.fld.crcpr.crcpoly = cm_object_get_child_by_name(state->u.f1.reg.crcpr, "CRCPOLY"); + + // RXCRCR bitfields. + state->u.f1.fld.rxcrcr.rxcrc = cm_object_get_child_by_name(state->u.f1.reg.rxcrcr, "RxCRC"); + + // TXCRCR bitfields. + state->u.f1.fld.txcrcr.txcrc = cm_object_get_child_by_name(state->u.f1.reg.txcrcr, "TxCRC"); + + // I2SCFGR bitfields. + state->u.f1.fld.i2scfgr.chlen = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "CHLEN"); + state->u.f1.fld.i2scfgr.datlen = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "DATLEN"); + state->u.f1.fld.i2scfgr.ckpol = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "CKPOL"); + state->u.f1.fld.i2scfgr.i2sstd = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SSTD"); + state->u.f1.fld.i2scfgr.pcmsync = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "PCMSYNC"); + state->u.f1.fld.i2scfgr.i2scfg = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SCFG"); + state->u.f1.fld.i2scfgr.i2se = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SE"); + state->u.f1.fld.i2scfgr.i2smod = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SMOD"); + + // I2SPR bitfields. + state->u.f1.fld.i2spr.i2sdiv = cm_object_get_child_by_name(state->u.f1.reg.i2spr, "I2SDIV"); + state->u.f1.fld.i2spr.odd = cm_object_get_child_by_name(state->u.f1.reg.i2spr, "ODD"); + state->u.f1.fld.i2spr.mckoe = cm_object_get_child_by_name(state->u.f1.reg.i2spr, "MCKOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_spi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_spi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_spi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_spi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_spi_is_enabled(Object *obj) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_spi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SPIState *state = STM32_SPI_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_SPI_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_spi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SPI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SPIState *state = STM32_SPI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SPI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_spi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_spi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_spi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_spi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_spi_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SPI%dEN", + 1 + state->port_index - STM32_PORT_SPI1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_spi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SPI); +} + +static void stm32_spi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_spi_reset_callback; + dc->realize = stm32_spi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_spi_is_enabled; +} + +static const TypeInfo stm32_spi_type_info = { + .name = TYPE_STM32_SPI, + .parent = TYPE_STM32_SPI_PARENT, + .instance_init = stm32_spi_instance_init_callback, + .instance_size = sizeof(STM32SPIState), + .class_init = stm32_spi_class_init_callback, + .class_size = sizeof(STM32SPIClass) }; + +static void stm32_spi_register_types(void) +{ + type_register_static(&stm32_spi_type_info); +} + +type_init(stm32_spi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/spi1.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/spi1.h new file mode 100644 index 0000000000..e31c614200 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/spi1.h @@ -0,0 +1,199 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SPI_H_ +#define STM32_SPI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SPI DEVICE_PATH_STM32 "SPI" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_SPI1, + STM32_PORT_SPI2, + STM32_PORT_SPI3, + STM32_PORT_SPI_UNDEFINED = 0xFF, +} stm32_spi_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SPI TYPE_STM32_PREFIX "spi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SPI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SPIParentClass; +typedef PeripheralState STM32SPIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SPI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SPIClass, (obj), TYPE_STM32_SPI) +#define STM32_SPI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SPIClass, (klass), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentClass parent_class; + // public: + + // None, so far. +} STM32SPIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SPI_STATE(obj) \ + OBJECT_CHECK(STM32SPIState, (obj), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_spi_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 SPI (Serial peripheral interface) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *sr; // 0x8 (Status register) + Object *dr; // 0xC (Data register) + Object *crcpr; // 0x10 (CRC polynomial register) + Object *rxcrcr; // 0x14 (RX CRC register) + Object *txcrcr; // 0x18 (TX CRC register) + Object *i2scfgr; // 0x1C (I2S configuration register) + Object *i2spr; // 0x20 (I2S prescaler register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cpha; // [0:0] Clock phase + Object *cpol; // [1:1] Clock polarity + Object *mstr; // [2:2] Master selection + Object *br; // [3:5] Baud rate control + Object *spe; // [6:6] SPI enable + Object *lsbfirst; // [7:7] Frame format + Object *ssi; // [8:8] Internal slave select + Object *ssm; // [9:9] Software slave management + Object *rxonly; // [10:10] Receive only + Object *dff; // [11:11] Data frame format + Object *crcnext; // [12:12] CRC transfer next + Object *crcen; // [13:13] Hardware CRC calculation enable + Object *bidioe; // [14:14] Output enable in bidirectional mode + Object *bidimode; // [15:15] Bidirectional data mode enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *rxdmaen; // [0:0] Rx buffer DMA enable + Object *txdmaen; // [1:1] Tx buffer DMA enable + Object *ssoe; // [2:2] SS output enable + Object *errie; // [5:5] Error interrupt enable + Object *rxneie; // [6:6] RX buffer not empty interrupt enable + Object *txeie; // [7:7] Tx buffer empty interrupt enable + } cr2; + + // SR (Status register) bitfields. + struct { + Object *rxne; // [0:0] Receive buffer not empty + Object *txe; // [1:1] Transmit buffer empty + Object *chside; // [2:2] Channel side + Object *udr; // [3:3] Underrun flag + Object *crcerr; // [4:4] CRC error flag + Object *modf; // [5:5] Mode fault + Object *ovr; // [6:6] Overrun flag + Object *bsy; // [7:7] Busy flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:15] Data register + } dr; + + // CRCPR (CRC polynomial register) bitfields. + struct { + Object *crcpoly; // [0:15] CRC polynomial register + } crcpr; + + // RXCRCR (RX CRC register) bitfields. + struct { + Object *rxcrc; // [0:15] Rx CRC register + } rxcrcr; + + // TXCRCR (TX CRC register) bitfields. + struct { + Object *txcrc; // [0:15] Tx CRC register + } txcrcr; + + // I2SCFGR (I2S configuration register) bitfields. + struct { + Object *chlen; // [0:0] Channel length (number of bits per audio channel) + Object *datlen; // [1:2] Data length to be transferred + Object *ckpol; // [3:3] Steady state clock polarity + Object *i2sstd; // [4:5] I2S standard selection + Object *pcmsync; // [7:7] PCM frame synchronization + Object *i2scfg; // [8:9] I2S configuration mode + Object *i2se; // [10:10] I2S Enable + Object *i2smod; // [11:11] I2S mode selection + } i2scfgr; + + // I2SPR (I2S prescaler register) bitfields. + struct { + Object *i2sdiv; // [0:7] I2S Linear prescaler + Object *odd; // [8:8] Odd factor for the prescaler + Object *mckoe; // [9:9] Master clock output enable + } i2spr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SPIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SPI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim1.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim1.c new file mode 100644 index 0000000000..dc4ef5fcae --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim1.c @@ -0,0 +1,427 @@ +/* + * STM32 - TIM1 (Advanced timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_tim1_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f1.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f1.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f1.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f1.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f1.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f1.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f1.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f1.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f1.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f1.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f1.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.opm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "OPM"); + state->u.f1.fld.cr1.dir = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DIR"); + state->u.f1.fld.cr1.cms = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CMS"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + state->u.f1.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f1.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCPC"); + state->u.f1.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCUS"); + state->u.f1.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCDS"); + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + state->u.f1.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TI1S"); + state->u.f1.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS1"); + state->u.f1.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS1N"); + state->u.f1.fld.cr2.ois2 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS2"); + state->u.f1.fld.cr2.ois2n = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS2N"); + state->u.f1.fld.cr2.ois3 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS3"); + state->u.f1.fld.cr2.ois3n = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS3N"); + state->u.f1.fld.cr2.ois4 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS4"); + + // SMCR bitfields. + state->u.f1.fld.smcr.sms = cm_object_get_child_by_name(state->u.f1.reg.smcr, "SMS"); + state->u.f1.fld.smcr.ts = cm_object_get_child_by_name(state->u.f1.reg.smcr, "TS"); + state->u.f1.fld.smcr.msm = cm_object_get_child_by_name(state->u.f1.reg.smcr, "MSM"); + state->u.f1.fld.smcr.etf = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETF"); + state->u.f1.fld.smcr.etps = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETPS"); + state->u.f1.fld.smcr.ece = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ECE"); + state->u.f1.fld.smcr.etp = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1IE"); + state->u.f1.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2IE"); + state->u.f1.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3IE"); + state->u.f1.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4IE"); + state->u.f1.fld.dier.comie = cm_object_get_child_by_name(state->u.f1.reg.dier, "COMIE"); + state->u.f1.fld.dier.tie = cm_object_get_child_by_name(state->u.f1.reg.dier, "TIE"); + state->u.f1.fld.dier.bie = cm_object_get_child_by_name(state->u.f1.reg.dier, "BIE"); + state->u.f1.fld.dier.ude = cm_object_get_child_by_name(state->u.f1.reg.dier, "UDE"); + state->u.f1.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1DE"); + state->u.f1.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2DE"); + state->u.f1.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3DE"); + state->u.f1.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4DE"); + state->u.f1.fld.dier.comde = cm_object_get_child_by_name(state->u.f1.reg.dier, "COMDE"); + state->u.f1.fld.dier.tde = cm_object_get_child_by_name(state->u.f1.reg.dier, "TDE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + state->u.f1.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1IF"); + state->u.f1.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2IF"); + state->u.f1.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3IF"); + state->u.f1.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4IF"); + state->u.f1.fld.sr.comif = cm_object_get_child_by_name(state->u.f1.reg.sr, "COMIF"); + state->u.f1.fld.sr.tif = cm_object_get_child_by_name(state->u.f1.reg.sr, "TIF"); + state->u.f1.fld.sr.bif = cm_object_get_child_by_name(state->u.f1.reg.sr, "BIF"); + state->u.f1.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1OF"); + state->u.f1.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2OF"); + state->u.f1.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3OF"); + state->u.f1.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + state->u.f1.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC1G"); + state->u.f1.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC2G"); + state->u.f1.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC3G"); + state->u.f1.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC4G"); + state->u.f1.fld.egr.comg = cm_object_get_child_by_name(state->u.f1.reg.egr, "COMG"); + state->u.f1.fld.egr.tg = cm_object_get_child_by_name(state->u.f1.reg.egr, "TG"); + state->u.f1.fld.egr.bg = cm_object_get_child_by_name(state->u.f1.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f1.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC1S"); + state->u.f1.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1FE"); + state->u.f1.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1PE"); + state->u.f1.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1M"); + state->u.f1.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1CE"); + state->u.f1.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC2S"); + state->u.f1.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2FE"); + state->u.f1.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2PE"); + state->u.f1.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2M"); + state->u.f1.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f1.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC1S"); + state->u.f1.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "ICPCS"); + state->u.f1.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1F"); + state->u.f1.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC2S"); + state->u.f1.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2PCS"); + state->u.f1.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f1.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC3S"); + state->u.f1.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3FE"); + state->u.f1.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3PE"); + state->u.f1.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3M"); + state->u.f1.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3CE"); + state->u.f1.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC4S"); + state->u.f1.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4FE"); + state->u.f1.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4PE"); + state->u.f1.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4M"); + state->u.f1.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f1.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC3S"); + state->u.f1.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3PSC"); + state->u.f1.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3F"); + state->u.f1.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC4S"); + state->u.f1.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4PSC"); + state->u.f1.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f1.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1E"); + state->u.f1.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1P"); + state->u.f1.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1NE"); + state->u.f1.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1NP"); + state->u.f1.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2E"); + state->u.f1.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2P"); + state->u.f1.fld.ccer.cc2ne = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2NE"); + state->u.f1.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2NP"); + state->u.f1.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3E"); + state->u.f1.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3P"); + state->u.f1.fld.ccer.cc3ne = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3NE"); + state->u.f1.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3NP"); + state->u.f1.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4E"); + state->u.f1.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f1.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f1.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f1.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "CCR4"); + + // DCR bitfields. + state->u.f1.fld.dcr.dba = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBA"); + state->u.f1.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f1.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f1.reg.dmar, "DMAB"); + + // RCR bitfields. + state->u.f1.fld.rcr.rep = cm_object_get_child_by_name(state->u.f1.reg.rcr, "REP"); + + // BDTR bitfields. + state->u.f1.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "DTG"); + state->u.f1.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "LOCK"); + state->u.f1.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "OSSI"); + state->u.f1.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "OSSR"); + state->u.f1.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "BKE"); + state->u.f1.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "BKP"); + state->u.f1.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "AOE"); + state->u.f1.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "MOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim1_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim1_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim1_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim1_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim1_is_enabled(Object *obj) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim1_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim1_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM1)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM1State *state = STM32_TIM1_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM1"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_tim1_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim1_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim1_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim1_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim1_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM1EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim1_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM1); +} + +static void stm32_tim1_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim1_reset_callback; + dc->realize = stm32_tim1_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim1_is_enabled; +} + +static const TypeInfo stm32_tim1_type_info = { + .name = TYPE_STM32_TIM1, + .parent = TYPE_STM32_TIM1_PARENT, + .instance_init = stm32_tim1_instance_init_callback, + .instance_size = sizeof(STM32TIM1State), + .class_init = stm32_tim1_class_init_callback, + .class_size = sizeof(STM32TIM1Class) }; + +static void stm32_tim1_register_types(void) +{ + type_register_static(&stm32_tim1_type_info); +} + +type_init(stm32_tim1_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim1.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim1.h new file mode 100644 index 0000000000..8d7109ff8e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim1.h @@ -0,0 +1,336 @@ +/* + * STM32 - TIM1 (Advanced timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM1_H_ +#define STM32_TIM1_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM1 DEVICE_PATH_STM32 "TIM1" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM1 TYPE_STM32_PREFIX "tim1" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM1_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM1ParentClass; +typedef PeripheralState STM32TIM1ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM1_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM1Class, (obj), TYPE_STM32_TIM1) +#define STM32_TIM1_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM1Class, (klass), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM1Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM1_STATE(obj) \ + OBJECT_CHECK(STM32TIM1State, (obj), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM1 (Advanced timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *rcr; // 0x30 (Repetition counter register) + Object *bdtr; // 0x44 (Break and dead-time register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + Object *ois2; // [10:10] Output Idle state 2 + Object *ois2n; // [11:11] Output Idle state 2 + Object *ois3; // [12:12] Output Idle state 3 + Object *ois3n; // [13:13] Output Idle state 3 + Object *ois4; // [14:14] Output Idle state 4 + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *comde; // [13:13] COM DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *oc1ce; // [7:7] Output Compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + Object *oc2ce; // [15:15] Output Compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2ne; // [6:6] Capture/Compare 2 complementary output enable + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3ne; // [10:10] Capture/Compare 3 complementary output enable + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM1State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM1_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim10.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim10.c new file mode 100644 index 0000000000..6413ed8929 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim10.c @@ -0,0 +1,296 @@ +/* + * STM32 - TIM10 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_tim10_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f1.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f1.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + state->u.f1.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + state->u.f1.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1IF"); + state->u.f1.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + state->u.f1.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f1.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC1S"); + state->u.f1.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1PE"); + state->u.f1.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f1.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC1S"); + state->u.f1.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1PSC"); + state->u.f1.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f1.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1E"); + state->u.f1.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1P"); + state->u.f1.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CCR1"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim10_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim10_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim10_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim10_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim10_is_enabled(Object *obj) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim10_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim10_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM10)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM10State *state = STM32_TIM10_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM10"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_tim10_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim10_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim10_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim10_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim10_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM10EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim10_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM10); +} + +static void stm32_tim10_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim10_reset_callback; + dc->realize = stm32_tim10_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim10_is_enabled; +} + +static const TypeInfo stm32_tim10_type_info = { + .name = TYPE_STM32_TIM10, + .parent = TYPE_STM32_TIM10_PARENT, + .instance_init = stm32_tim10_instance_init_callback, + .instance_size = sizeof(STM32TIM10State), + .class_init = stm32_tim10_class_init_callback, + .class_size = sizeof(STM32TIM10Class) }; + +static void stm32_tim10_register_types(void) +{ + type_register_static(&stm32_tim10_type_info); +} + +type_init(stm32_tim10_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim10.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim10.h new file mode 100644 index 0000000000..a8212e08a4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim10.h @@ -0,0 +1,185 @@ +/* + * STM32 - TIM10 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM10_H_ +#define STM32_TIM10_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM10 DEVICE_PATH_STM32 "TIM10" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM10 TYPE_STM32_PREFIX "tim10" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM10_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM10ParentClass; +typedef PeripheralState STM32TIM10ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM10_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM10Class, (obj), TYPE_STM32_TIM10) +#define STM32_TIM10_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM10Class, (klass), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM10Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM10_STATE(obj) \ + OBJECT_CHECK(STM32TIM10State, (obj), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM10 (General purpose timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM10State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM10_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim2.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim2.c new file mode 100644 index 0000000000..5ff1ae8c77 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim2.c @@ -0,0 +1,390 @@ +/* + * STM32 - TIM2 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_tim2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f1.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f1.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f1.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f1.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f1.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f1.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f1.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f1.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f1.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.opm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "OPM"); + state->u.f1.fld.cr1.dir = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DIR"); + state->u.f1.fld.cr1.cms = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CMS"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + state->u.f1.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f1.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCDS"); + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + state->u.f1.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f1.fld.smcr.sms = cm_object_get_child_by_name(state->u.f1.reg.smcr, "SMS"); + state->u.f1.fld.smcr.ts = cm_object_get_child_by_name(state->u.f1.reg.smcr, "TS"); + state->u.f1.fld.smcr.msm = cm_object_get_child_by_name(state->u.f1.reg.smcr, "MSM"); + state->u.f1.fld.smcr.etf = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETF"); + state->u.f1.fld.smcr.etps = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETPS"); + state->u.f1.fld.smcr.ece = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ECE"); + state->u.f1.fld.smcr.etp = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1IE"); + state->u.f1.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2IE"); + state->u.f1.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3IE"); + state->u.f1.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4IE"); + state->u.f1.fld.dier.tie = cm_object_get_child_by_name(state->u.f1.reg.dier, "TIE"); + state->u.f1.fld.dier.ude = cm_object_get_child_by_name(state->u.f1.reg.dier, "UDE"); + state->u.f1.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1DE"); + state->u.f1.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2DE"); + state->u.f1.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3DE"); + state->u.f1.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4DE"); + state->u.f1.fld.dier.tde = cm_object_get_child_by_name(state->u.f1.reg.dier, "TDE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + state->u.f1.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1IF"); + state->u.f1.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2IF"); + state->u.f1.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3IF"); + state->u.f1.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4IF"); + state->u.f1.fld.sr.tif = cm_object_get_child_by_name(state->u.f1.reg.sr, "TIF"); + state->u.f1.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1OF"); + state->u.f1.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2OF"); + state->u.f1.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3OF"); + state->u.f1.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + state->u.f1.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC1G"); + state->u.f1.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC2G"); + state->u.f1.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC3G"); + state->u.f1.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC4G"); + state->u.f1.fld.egr.tg = cm_object_get_child_by_name(state->u.f1.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f1.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC1S"); + state->u.f1.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1FE"); + state->u.f1.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1PE"); + state->u.f1.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1M"); + state->u.f1.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1CE"); + state->u.f1.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC2S"); + state->u.f1.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2FE"); + state->u.f1.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2PE"); + state->u.f1.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2M"); + state->u.f1.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f1.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC1S"); + state->u.f1.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1PSC"); + state->u.f1.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1F"); + state->u.f1.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC2S"); + state->u.f1.fld.ccmr1_input.ic2psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2PSC"); + state->u.f1.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f1.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC3S"); + state->u.f1.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3FE"); + state->u.f1.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3PE"); + state->u.f1.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3M"); + state->u.f1.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3CE"); + state->u.f1.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC4S"); + state->u.f1.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4FE"); + state->u.f1.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4PE"); + state->u.f1.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4M"); + state->u.f1.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f1.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC3S"); + state->u.f1.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3PSC"); + state->u.f1.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3F"); + state->u.f1.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC4S"); + state->u.f1.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4PSC"); + state->u.f1.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f1.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1E"); + state->u.f1.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1P"); + state->u.f1.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2E"); + state->u.f1.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2P"); + state->u.f1.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3E"); + state->u.f1.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3P"); + state->u.f1.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4E"); + state->u.f1.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f1.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f1.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f1.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "CCR4"); + + // DCR bitfields. + state->u.f1.fld.dcr.dba = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBA"); + state->u.f1.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f1.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f1.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim2_is_enabled(Object *obj) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM2State *state = STM32_TIM2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_tim2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim2_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM2EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM2); +} + +static void stm32_tim2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim2_reset_callback; + dc->realize = stm32_tim2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim2_is_enabled; +} + +static const TypeInfo stm32_tim2_type_info = { + .name = TYPE_STM32_TIM2, + .parent = TYPE_STM32_TIM2_PARENT, + .instance_init = stm32_tim2_instance_init_callback, + .instance_size = sizeof(STM32TIM2State), + .class_init = stm32_tim2_class_init_callback, + .class_size = sizeof(STM32TIM2Class) }; + +static void stm32_tim2_register_types(void) +{ + type_register_static(&stm32_tim2_type_info); +} + +type_init(stm32_tim2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim2.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim2.h new file mode 100644 index 0000000000..36b06f5418 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim2.h @@ -0,0 +1,295 @@ +/* + * STM32 - TIM2 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM2_H_ +#define STM32_TIM2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM2 DEVICE_PATH_STM32 "TIM2" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM2 TYPE_STM32_PREFIX "tim2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM2ParentClass; +typedef PeripheralState STM32TIM2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM2Class, (obj), TYPE_STM32_TIM2) +#define STM32_TIM2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM2Class, (klass), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM2_STATE(obj) \ + OBJECT_CHECK(STM32TIM2State, (obj), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM2 (General purpose timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output compare 1 fast enable + Object *oc1pe; // [3:3] Output compare 1 preload enable + Object *oc1m; // [4:6] Output compare 1 mode + Object *oc1ce; // [7:7] Output compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output compare 2 fast enable + Object *oc2pe; // [11:11] Output compare 2 preload enable + Object *oc2m; // [12:14] Output compare 2 mode + Object *oc2ce; // [15:15] Output compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/compare 2 selection + Object *ic2psc; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *o24ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim6.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim6.c new file mode 100644 index 0000000000..e27c7c6817 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim6.c @@ -0,0 +1,271 @@ +/* + * STM32 - TIM6 (Basic timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_tim6_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.opm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "OPM"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.ude = cm_object_get_child_by_name(state->u.f1.reg.dier, "UDE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim6_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim6_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim6_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim6_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim6_is_enabled(Object *obj) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim6_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim6_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM6)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM6State *state = STM32_TIM6_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM6"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_tim6_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim6_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim6_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim6_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim6_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM6EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim6_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM6); +} + +static void stm32_tim6_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim6_reset_callback; + dc->realize = stm32_tim6_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim6_is_enabled; +} + +static const TypeInfo stm32_tim6_type_info = { + .name = TYPE_STM32_TIM6, + .parent = TYPE_STM32_TIM6_PARENT, + .instance_init = stm32_tim6_instance_init_callback, + .instance_size = sizeof(STM32TIM6State), + .class_init = stm32_tim6_class_init_callback, + .class_size = sizeof(STM32TIM6Class) }; + +static void stm32_tim6_register_types(void) +{ + type_register_static(&stm32_tim6_type_info); +} + +type_init(stm32_tim6_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim6.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim6.h new file mode 100644 index 0000000000..2370d39c78 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim6.h @@ -0,0 +1,152 @@ +/* + * STM32 - TIM6 (Basic timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM6_H_ +#define STM32_TIM6_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM6 DEVICE_PATH_STM32 "TIM6" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM6 TYPE_STM32_PREFIX "tim6" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM6_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM6ParentClass; +typedef PeripheralState STM32TIM6ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM6_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM6Class, (obj), TYPE_STM32_TIM6) +#define STM32_TIM6_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM6Class, (klass), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM6Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM6_STATE(obj) \ + OBJECT_CHECK(STM32TIM6State, (obj), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM6 (Basic timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *ude; // [8:8] Update DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + } egr; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Low counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Low Auto-reload value + } arr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM6State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM6_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim9.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim9.c new file mode 100644 index 0000000000..e23ad85812 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim9.c @@ -0,0 +1,325 @@ +/* + * STM32 - TIM9 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_tim9_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f1.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f1.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f1.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.opm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "OPM"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + state->u.f1.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + + // SMCR bitfields. + state->u.f1.fld.smcr.sms = cm_object_get_child_by_name(state->u.f1.reg.smcr, "SMS"); + state->u.f1.fld.smcr.ts = cm_object_get_child_by_name(state->u.f1.reg.smcr, "TS"); + state->u.f1.fld.smcr.msm = cm_object_get_child_by_name(state->u.f1.reg.smcr, "MSM"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1IE"); + state->u.f1.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2IE"); + state->u.f1.fld.dier.tie = cm_object_get_child_by_name(state->u.f1.reg.dier, "TIE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + state->u.f1.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1IF"); + state->u.f1.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2IF"); + state->u.f1.fld.sr.tif = cm_object_get_child_by_name(state->u.f1.reg.sr, "TIF"); + state->u.f1.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1OF"); + state->u.f1.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2OF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + state->u.f1.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC1G"); + state->u.f1.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC2G"); + state->u.f1.fld.egr.tg = cm_object_get_child_by_name(state->u.f1.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f1.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC1S"); + state->u.f1.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1FE"); + state->u.f1.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1PE"); + state->u.f1.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1M"); + state->u.f1.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC2S"); + state->u.f1.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2FE"); + state->u.f1.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2PE"); + state->u.f1.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2M"); + + // CCMR1_Input bitfields. + state->u.f1.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC1S"); + state->u.f1.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1PSC"); + state->u.f1.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1F"); + state->u.f1.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC2S"); + state->u.f1.fld.ccmr1_input.ic2psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2PSC"); + state->u.f1.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2F"); + + // CCER bitfields. + state->u.f1.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1E"); + state->u.f1.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1P"); + state->u.f1.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1NP"); + state->u.f1.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2E"); + state->u.f1.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2P"); + state->u.f1.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2NP"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f1.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "CCR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim9_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim9_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim9_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim9_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim9_is_enabled(Object *obj) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim9_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim9_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM9)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM9State *state = STM32_TIM9_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM9"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_tim9_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim9_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim9_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim9_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim9_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM9EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim9_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM9); +} + +static void stm32_tim9_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim9_reset_callback; + dc->realize = stm32_tim9_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim9_is_enabled; +} + +static const TypeInfo stm32_tim9_type_info = { + .name = TYPE_STM32_TIM9, + .parent = TYPE_STM32_TIM9_PARENT, + .instance_init = stm32_tim9_instance_init_callback, + .instance_size = sizeof(STM32TIM9State), + .class_init = stm32_tim9_class_init_callback, + .class_size = sizeof(STM32TIM9Class) }; + +static void stm32_tim9_register_types(void) +{ + type_register_static(&stm32_tim9_type_info); +} + +type_init(stm32_tim9_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/tim9.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim9.h new file mode 100644 index 0000000000..348164945e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/tim9.h @@ -0,0 +1,218 @@ +/* + * STM32 - TIM9 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM9_H_ +#define STM32_TIM9_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM9 DEVICE_PATH_STM32 "TIM9" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM9 TYPE_STM32_PREFIX "tim9" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM9_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM9ParentClass; +typedef PeripheralState STM32TIM9ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM9_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM9Class, (obj), TYPE_STM32_TIM9) +#define STM32_TIM9_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM9Class, (klass), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM9Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM9_STATE(obj) \ + OBJECT_CHECK(STM32TIM9State, (obj), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM9 (General purpose timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2psc; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM9State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM9_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/uart4.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart4.c new file mode 100644 index 0000000000..5084112af9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart4.c @@ -0,0 +1,294 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_uart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + + + // SR bitfields. + state->u.f1.fld.sr.pe = cm_object_get_child_by_name(state->u.f1.reg.sr, "PE"); + state->u.f1.fld.sr.fe = cm_object_get_child_by_name(state->u.f1.reg.sr, "FE"); + state->u.f1.fld.sr.ne = cm_object_get_child_by_name(state->u.f1.reg.sr, "NE"); + state->u.f1.fld.sr.ore = cm_object_get_child_by_name(state->u.f1.reg.sr, "ORE"); + state->u.f1.fld.sr.idle = cm_object_get_child_by_name(state->u.f1.reg.sr, "IDLE"); + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.tc = cm_object_get_child_by_name(state->u.f1.reg.sr, "TC"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.lbd = cm_object_get_child_by_name(state->u.f1.reg.sr, "LBD"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // BRR bitfields. + state->u.f1.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Fraction"); + state->u.f1.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f1.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SBK"); + state->u.f1.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RWU"); + state->u.f1.fld.cr1.re = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RE"); + state->u.f1.fld.cr1.te = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TE"); + state->u.f1.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "IDLEIE"); + state->u.f1.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXNEIE"); + state->u.f1.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TCIE"); + state->u.f1.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TXEIE"); + state->u.f1.fld.cr1.peie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEIE"); + state->u.f1.fld.cr1.ps = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PS"); + state->u.f1.fld.cr1.pce = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PCE"); + state->u.f1.fld.cr1.wake = cm_object_get_child_by_name(state->u.f1.reg.cr1, "WAKE"); + state->u.f1.fld.cr1.m = cm_object_get_child_by_name(state->u.f1.reg.cr1, "M"); + state->u.f1.fld.cr1.ue = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.add = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADD"); + state->u.f1.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDL"); + state->u.f1.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDIE"); + state->u.f1.fld.cr2.stop = cm_object_get_child_by_name(state->u.f1.reg.cr2, "STOP"); + state->u.f1.fld.cr2.linen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f1.fld.cr3.eie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "EIE"); + state->u.f1.fld.cr3.iren = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IREN"); + state->u.f1.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IRLP"); + state->u.f1.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f1.reg.cr3, "HDSEL"); + state->u.f1.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAR"); + state->u.f1.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_uart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_uart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_uart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_uart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_uart_is_enabled(Object *obj) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_uart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32UARTState *state = STM32_UART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_UART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_uart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_UART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32UARTState *state = STM32_UART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "UART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_uart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_uart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_uart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/UART%dEN", + 1 + state->port_index - STM32_PORT_UART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_uart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_UART); +} + +static void stm32_uart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_uart_reset_callback; + dc->realize = stm32_uart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_uart_is_enabled; +} + +static const TypeInfo stm32_uart_type_info = { + .name = TYPE_STM32_UART, + .parent = TYPE_STM32_UART_PARENT, + .instance_init = stm32_uart_instance_init_callback, + .instance_size = sizeof(STM32UARTState), + .class_init = stm32_uart_class_init_callback, + .class_size = sizeof(STM32UARTClass) }; + +static void stm32_uart_register_types(void) +{ + type_register_static(&stm32_uart_type_info); +} + +type_init(stm32_uart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/uart4.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart4.h new file mode 100644 index 0000000000..6e05f0b4bc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart4.h @@ -0,0 +1,177 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_UART_H_ +#define STM32_UART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_UART DEVICE_PATH_STM32 "UART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_UART4, + STM32_PORT_UART5, + STM32_PORT_UART_UNDEFINED = 0xFF, +} stm32_uart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_UART TYPE_STM32_PREFIX "uart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_UART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32UARTParentClass; +typedef PeripheralState STM32UARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32UARTClass, (obj), TYPE_STM32_UART) +#define STM32_UART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32UARTClass, (klass), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentClass parent_class; + // public: + + // None, so far. +} STM32UARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_UART_STATE(obj) \ + OBJECT_CHECK(STM32UARTState, (obj), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_uart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 UART (Universal asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (UART4_SR) + Object *dr; // 0x4 (UART4_DR) + Object *brr; // 0x8 (UART4_BRR) + Object *cr1; // 0xC (UART4_CR1) + Object *cr2; // 0x10 (UART4_CR2) + Object *cr3; // 0x14 (UART4_CR3) + } reg; + + struct { + + // SR (UART4_SR) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *ne; // [2:2] Noise error flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + } sr; + + // DR (UART4_DR) bitfields. + struct { + Object *dr; // [0:8] DR + } dr; + + // BRR (UART4_BRR) bitfields. + struct { + Object *div_fraction; // [0:3] DIV_Fraction + Object *div_mantissa; // [4:15] DIV_Mantissa + } brr; + + // CR1 (UART4_CR1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + } cr1; + + // CR2 (UART4_CR2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (UART4_CR3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + } cr3; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32UARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_UART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/uart5.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart5.c new file mode 100644 index 0000000000..9da8f4c55d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart5.c @@ -0,0 +1,293 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_uart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + + + // SR bitfields. + state->u.f1.fld.sr.pe = cm_object_get_child_by_name(state->u.f1.reg.sr, "PE"); + state->u.f1.fld.sr.fe = cm_object_get_child_by_name(state->u.f1.reg.sr, "FE"); + state->u.f1.fld.sr.ne = cm_object_get_child_by_name(state->u.f1.reg.sr, "NE"); + state->u.f1.fld.sr.ore = cm_object_get_child_by_name(state->u.f1.reg.sr, "ORE"); + state->u.f1.fld.sr.idle = cm_object_get_child_by_name(state->u.f1.reg.sr, "IDLE"); + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.tc = cm_object_get_child_by_name(state->u.f1.reg.sr, "TC"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.lbd = cm_object_get_child_by_name(state->u.f1.reg.sr, "LBD"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // BRR bitfields. + state->u.f1.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Fraction"); + state->u.f1.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f1.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SBK"); + state->u.f1.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RWU"); + state->u.f1.fld.cr1.re = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RE"); + state->u.f1.fld.cr1.te = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TE"); + state->u.f1.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "IDLEIE"); + state->u.f1.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXNEIE"); + state->u.f1.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TCIE"); + state->u.f1.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TXEIE"); + state->u.f1.fld.cr1.peie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEIE"); + state->u.f1.fld.cr1.ps = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PS"); + state->u.f1.fld.cr1.pce = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PCE"); + state->u.f1.fld.cr1.wake = cm_object_get_child_by_name(state->u.f1.reg.cr1, "WAKE"); + state->u.f1.fld.cr1.m = cm_object_get_child_by_name(state->u.f1.reg.cr1, "M"); + state->u.f1.fld.cr1.ue = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.add = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADD"); + state->u.f1.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDL"); + state->u.f1.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDIE"); + state->u.f1.fld.cr2.stop = cm_object_get_child_by_name(state->u.f1.reg.cr2, "STOP"); + state->u.f1.fld.cr2.linen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f1.fld.cr3.eie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "EIE"); + state->u.f1.fld.cr3.iren = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IREN"); + state->u.f1.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IRLP"); + state->u.f1.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f1.reg.cr3, "HDSEL"); + state->u.f1.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_uart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_uart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_uart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_uart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_uart_is_enabled(Object *obj) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_uart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32UARTState *state = STM32_UART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_UART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_uart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_UART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32UARTState *state = STM32_UART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "UART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_uart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_uart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_uart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/UART%dEN", + 1 + state->port_index - STM32_PORT_UART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_uart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_UART); +} + +static void stm32_uart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_uart_reset_callback; + dc->realize = stm32_uart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_uart_is_enabled; +} + +static const TypeInfo stm32_uart_type_info = { + .name = TYPE_STM32_UART, + .parent = TYPE_STM32_UART_PARENT, + .instance_init = stm32_uart_instance_init_callback, + .instance_size = sizeof(STM32UARTState), + .class_init = stm32_uart_class_init_callback, + .class_size = sizeof(STM32UARTClass) }; + +static void stm32_uart_register_types(void) +{ + type_register_static(&stm32_uart_type_info); +} + +type_init(stm32_uart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/uart5.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart5.h new file mode 100644 index 0000000000..ed061443f1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/uart5.h @@ -0,0 +1,176 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_UART_H_ +#define STM32_UART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_UART DEVICE_PATH_STM32 "UART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_UART4, + STM32_PORT_UART5, + STM32_PORT_UART_UNDEFINED = 0xFF, +} stm32_uart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_UART TYPE_STM32_PREFIX "uart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_UART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32UARTParentClass; +typedef PeripheralState STM32UARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32UARTClass, (obj), TYPE_STM32_UART) +#define STM32_UART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32UARTClass, (klass), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentClass parent_class; + // public: + + // None, so far. +} STM32UARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_UART_STATE(obj) \ + OBJECT_CHECK(STM32UARTState, (obj), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_uart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 UART (Universal asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (UART4_SR) + Object *dr; // 0x4 (UART4_DR) + Object *brr; // 0x8 (UART4_BRR) + Object *cr1; // 0xC (UART4_CR1) + Object *cr2; // 0x10 (UART4_CR2) + Object *cr3; // 0x14 (UART4_CR3) + } reg; + + struct { + + // SR (UART4_SR) bitfields. + struct { + Object *pe; // [0:0] PE + Object *fe; // [1:1] FE + Object *ne; // [2:2] NE + Object *ore; // [3:3] ORE + Object *idle; // [4:4] IDLE + Object *rxne; // [5:5] RXNE + Object *tc; // [6:6] TC + Object *txe; // [7:7] TXE + Object *lbd; // [8:8] LBD + } sr; + + // DR (UART4_DR) bitfields. + struct { + Object *dr; // [0:8] DR + } dr; + + // BRR (UART4_BRR) bitfields. + struct { + Object *div_fraction; // [0:3] DIV_Fraction + Object *div_mantissa; // [4:15] DIV_Mantissa + } brr; + + // CR1 (UART4_CR1) bitfields. + struct { + Object *sbk; // [0:0] SBK + Object *rwu; // [1:1] RWU + Object *re; // [2:2] RE + Object *te; // [3:3] TE + Object *idleie; // [4:4] IDLEIE + Object *rxneie; // [5:5] RXNEIE + Object *tcie; // [6:6] TCIE + Object *txeie; // [7:7] TXEIE + Object *peie; // [8:8] PEIE + Object *ps; // [9:9] PS + Object *pce; // [10:10] PCE + Object *wake; // [11:11] WAKE + Object *m; // [12:12] M + Object *ue; // [13:13] UE + } cr1; + + // CR2 (UART4_CR2) bitfields. + struct { + Object *add; // [0:3] ADD + Object *lbdl; // [5:5] LBDL + Object *lbdie; // [6:6] LBDIE + Object *stop; // [12:13] STOP + Object *linen; // [14:14] LINEN + } cr2; + + // CR3 (UART4_CR3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *dmat; // [7:7] DMA enable transmitter + } cr3; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32UARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_UART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/usart1.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/usart1.c new file mode 100644 index 0000000000..3e36168adc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/usart1.c @@ -0,0 +1,309 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_usart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + state->u.f1.reg.gtpr = cm_object_get_child_by_name(obj, "GTPR"); + + + // SR bitfields. + state->u.f1.fld.sr.pe = cm_object_get_child_by_name(state->u.f1.reg.sr, "PE"); + state->u.f1.fld.sr.fe = cm_object_get_child_by_name(state->u.f1.reg.sr, "FE"); + state->u.f1.fld.sr.ne = cm_object_get_child_by_name(state->u.f1.reg.sr, "NE"); + state->u.f1.fld.sr.ore = cm_object_get_child_by_name(state->u.f1.reg.sr, "ORE"); + state->u.f1.fld.sr.idle = cm_object_get_child_by_name(state->u.f1.reg.sr, "IDLE"); + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.tc = cm_object_get_child_by_name(state->u.f1.reg.sr, "TC"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.lbd = cm_object_get_child_by_name(state->u.f1.reg.sr, "LBD"); + state->u.f1.fld.sr.cts = cm_object_get_child_by_name(state->u.f1.reg.sr, "CTS"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // BRR bitfields. + state->u.f1.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Fraction"); + state->u.f1.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f1.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SBK"); + state->u.f1.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RWU"); + state->u.f1.fld.cr1.re = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RE"); + state->u.f1.fld.cr1.te = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TE"); + state->u.f1.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "IDLEIE"); + state->u.f1.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXNEIE"); + state->u.f1.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TCIE"); + state->u.f1.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TXEIE"); + state->u.f1.fld.cr1.peie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEIE"); + state->u.f1.fld.cr1.ps = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PS"); + state->u.f1.fld.cr1.pce = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PCE"); + state->u.f1.fld.cr1.wake = cm_object_get_child_by_name(state->u.f1.reg.cr1, "WAKE"); + state->u.f1.fld.cr1.m = cm_object_get_child_by_name(state->u.f1.reg.cr1, "M"); + state->u.f1.fld.cr1.ue = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.add = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADD"); + state->u.f1.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDL"); + state->u.f1.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDIE"); + state->u.f1.fld.cr2.lbcl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBCL"); + state->u.f1.fld.cr2.cpha = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CPHA"); + state->u.f1.fld.cr2.cpol = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CPOL"); + state->u.f1.fld.cr2.clken = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CLKEN"); + state->u.f1.fld.cr2.stop = cm_object_get_child_by_name(state->u.f1.reg.cr2, "STOP"); + state->u.f1.fld.cr2.linen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f1.fld.cr3.eie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "EIE"); + state->u.f1.fld.cr3.iren = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IREN"); + state->u.f1.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IRLP"); + state->u.f1.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f1.reg.cr3, "HDSEL"); + state->u.f1.fld.cr3.nack = cm_object_get_child_by_name(state->u.f1.reg.cr3, "NACK"); + state->u.f1.fld.cr3.scen = cm_object_get_child_by_name(state->u.f1.reg.cr3, "SCEN"); + state->u.f1.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAR"); + state->u.f1.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAT"); + state->u.f1.fld.cr3.rtse = cm_object_get_child_by_name(state->u.f1.reg.cr3, "RTSE"); + state->u.f1.fld.cr3.ctse = cm_object_get_child_by_name(state->u.f1.reg.cr3, "CTSE"); + state->u.f1.fld.cr3.ctsie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "CTSIE"); + + // GTPR bitfields. + state->u.f1.fld.gtpr.psc = cm_object_get_child_by_name(state->u.f1.reg.gtpr, "PSC"); + state->u.f1.fld.gtpr.gt = cm_object_get_child_by_name(state->u.f1.reg.gtpr, "GT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usart_is_enabled(Object *obj) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USARTState *state = STM32_USART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_USART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USARTState *state = STM32_USART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_usart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_usart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_usart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USART%dEN", + 1 + state->port_index - STM32_PORT_USART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USART); +} + +static void stm32_usart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usart_reset_callback; + dc->realize = stm32_usart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usart_is_enabled; +} + +static const TypeInfo stm32_usart_type_info = { + .name = TYPE_STM32_USART, + .parent = TYPE_STM32_USART_PARENT, + .instance_init = stm32_usart_instance_init_callback, + .instance_size = sizeof(STM32USARTState), + .class_init = stm32_usart_class_init_callback, + .class_size = sizeof(STM32USARTClass) }; + +static void stm32_usart_register_types(void) +{ + type_register_static(&stm32_usart_type_info); +} + +type_init(stm32_usart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/usart1.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/usart1.h new file mode 100644 index 0000000000..10629eb585 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/usart1.h @@ -0,0 +1,195 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USART_H_ +#define STM32_USART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USART DEVICE_PATH_STM32 "USART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_USART1, + STM32_PORT_USART2, + STM32_PORT_USART3, + STM32_PORT_USART_UNDEFINED = 0xFF, +} stm32_usart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USART TYPE_STM32_PREFIX "usart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USARTParentClass; +typedef PeripheralState STM32USARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USARTClass, (obj), TYPE_STM32_USART) +#define STM32_USART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USARTClass, (klass), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentClass parent_class; + // public: + + // None, so far. +} STM32USARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USART_STATE(obj) \ + OBJECT_CHECK(STM32USARTState, (obj), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_usart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 USART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *dr; // 0x4 (Data register) + Object *brr; // 0x8 (Baud rate register) + Object *cr1; // 0xC (Control register 1) + Object *cr2; // 0x10 (Control register 2) + Object *cr3; // 0x14 (Control register 3) + Object *gtpr; // 0x18 (Guard time and prescaler register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *ne; // [2:2] Noise error flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + Object *cts; // [9:9] CTS flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:8] Data value + } dr; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // CR1 (Control register 1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *lbcl; // [8:8] Last bit clock pulse + Object *cpha; // [9:9] Clock phase + Object *cpol; // [10:10] Clock polarity + Object *clken; // [11:11] Clock enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *nack; // [4:4] Smartcard NACK enable + Object *scen; // [5:5] Smartcard mode enable + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *rtse; // [8:8] RTS enable + Object *ctse; // [9:9] CTS enable + Object *ctsie; // [10:10] CTS interrupt enable + } cr3; + + // GTPR (Guard time and prescaler register) bitfields. + struct { + Object *psc; // [0:7] Prescaler value + Object *gt; // [8:15] Guard time value + } gtpr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/usb.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/usb.c new file mode 100644 index 0000000000..d61736462c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/usb.c @@ -0,0 +1,384 @@ +/* + * STM32 - USB (Universal serial bus full-speed device interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_usb_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USBState *state = STM32_USB_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.ep0r = cm_object_get_child_by_name(obj, "EP0R"); + state->u.f1.reg.ep1r = cm_object_get_child_by_name(obj, "EP1R"); + state->u.f1.reg.ep2r = cm_object_get_child_by_name(obj, "EP2R"); + state->u.f1.reg.ep3r = cm_object_get_child_by_name(obj, "EP3R"); + state->u.f1.reg.ep4r = cm_object_get_child_by_name(obj, "EP4R"); + state->u.f1.reg.ep5r = cm_object_get_child_by_name(obj, "EP5R"); + state->u.f1.reg.ep6r = cm_object_get_child_by_name(obj, "EP6R"); + state->u.f1.reg.ep7r = cm_object_get_child_by_name(obj, "EP7R"); + state->u.f1.reg.cntr = cm_object_get_child_by_name(obj, "CNTR"); + state->u.f1.reg.istr = cm_object_get_child_by_name(obj, "ISTR"); + state->u.f1.reg.fnr = cm_object_get_child_by_name(obj, "FNR"); + state->u.f1.reg.daddr = cm_object_get_child_by_name(obj, "DADDR"); + state->u.f1.reg.btable = cm_object_get_child_by_name(obj, "BTABLE"); + + + // EP0R bitfields. + state->u.f1.fld.ep0r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "EA"); + state->u.f1.fld.ep0r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "STAT_TX"); + state->u.f1.fld.ep0r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "DTOG_TX"); + state->u.f1.fld.ep0r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "CTR_TX"); + state->u.f1.fld.ep0r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "EP_KIND"); + state->u.f1.fld.ep0r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "EP_TYPE"); + state->u.f1.fld.ep0r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "SETUP"); + state->u.f1.fld.ep0r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "STAT_RX"); + state->u.f1.fld.ep0r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "DTOG_RX"); + state->u.f1.fld.ep0r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep0r, "CTR_RX"); + + // EP1R bitfields. + state->u.f1.fld.ep1r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "EA"); + state->u.f1.fld.ep1r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "STAT_TX"); + state->u.f1.fld.ep1r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "DTOG_TX"); + state->u.f1.fld.ep1r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "CTR_TX"); + state->u.f1.fld.ep1r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "EP_KIND"); + state->u.f1.fld.ep1r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "EP_TYPE"); + state->u.f1.fld.ep1r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "SETUP"); + state->u.f1.fld.ep1r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "STAT_RX"); + state->u.f1.fld.ep1r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "DTOG_RX"); + state->u.f1.fld.ep1r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep1r, "CTR_RX"); + + // EP2R bitfields. + state->u.f1.fld.ep2r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "EA"); + state->u.f1.fld.ep2r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "STAT_TX"); + state->u.f1.fld.ep2r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "DTOG_TX"); + state->u.f1.fld.ep2r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "CTR_TX"); + state->u.f1.fld.ep2r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "EP_KIND"); + state->u.f1.fld.ep2r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "EP_TYPE"); + state->u.f1.fld.ep2r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "SETUP"); + state->u.f1.fld.ep2r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "STAT_RX"); + state->u.f1.fld.ep2r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "DTOG_RX"); + state->u.f1.fld.ep2r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep2r, "CTR_RX"); + + // EP3R bitfields. + state->u.f1.fld.ep3r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "EA"); + state->u.f1.fld.ep3r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "STAT_TX"); + state->u.f1.fld.ep3r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "DTOG_TX"); + state->u.f1.fld.ep3r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "CTR_TX"); + state->u.f1.fld.ep3r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "EP_KIND"); + state->u.f1.fld.ep3r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "EP_TYPE"); + state->u.f1.fld.ep3r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "SETUP"); + state->u.f1.fld.ep3r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "STAT_RX"); + state->u.f1.fld.ep3r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "DTOG_RX"); + state->u.f1.fld.ep3r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep3r, "CTR_RX"); + + // EP4R bitfields. + state->u.f1.fld.ep4r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "EA"); + state->u.f1.fld.ep4r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "STAT_TX"); + state->u.f1.fld.ep4r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "DTOG_TX"); + state->u.f1.fld.ep4r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "CTR_TX"); + state->u.f1.fld.ep4r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "EP_KIND"); + state->u.f1.fld.ep4r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "EP_TYPE"); + state->u.f1.fld.ep4r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "SETUP"); + state->u.f1.fld.ep4r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "STAT_RX"); + state->u.f1.fld.ep4r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "DTOG_RX"); + state->u.f1.fld.ep4r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep4r, "CTR_RX"); + + // EP5R bitfields. + state->u.f1.fld.ep5r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "EA"); + state->u.f1.fld.ep5r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "STAT_TX"); + state->u.f1.fld.ep5r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "DTOG_TX"); + state->u.f1.fld.ep5r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "CTR_TX"); + state->u.f1.fld.ep5r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "EP_KIND"); + state->u.f1.fld.ep5r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "EP_TYPE"); + state->u.f1.fld.ep5r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "SETUP"); + state->u.f1.fld.ep5r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "STAT_RX"); + state->u.f1.fld.ep5r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "DTOG_RX"); + state->u.f1.fld.ep5r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep5r, "CTR_RX"); + + // EP6R bitfields. + state->u.f1.fld.ep6r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "EA"); + state->u.f1.fld.ep6r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "STAT_TX"); + state->u.f1.fld.ep6r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "DTOG_TX"); + state->u.f1.fld.ep6r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "CTR_TX"); + state->u.f1.fld.ep6r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "EP_KIND"); + state->u.f1.fld.ep6r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "EP_TYPE"); + state->u.f1.fld.ep6r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "SETUP"); + state->u.f1.fld.ep6r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "STAT_RX"); + state->u.f1.fld.ep6r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "DTOG_RX"); + state->u.f1.fld.ep6r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep6r, "CTR_RX"); + + // EP7R bitfields. + state->u.f1.fld.ep7r.ea = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "EA"); + state->u.f1.fld.ep7r.stat_tx = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "STAT_TX"); + state->u.f1.fld.ep7r.dtog_tx = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "DTOG_TX"); + state->u.f1.fld.ep7r.ctr_tx = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "CTR_TX"); + state->u.f1.fld.ep7r.ep_kind = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "EP_KIND"); + state->u.f1.fld.ep7r.ep_type = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "EP_TYPE"); + state->u.f1.fld.ep7r.setup = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "SETUP"); + state->u.f1.fld.ep7r.stat_rx = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "STAT_RX"); + state->u.f1.fld.ep7r.dtog_rx = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "DTOG_RX"); + state->u.f1.fld.ep7r.ctr_rx = cm_object_get_child_by_name(state->u.f1.reg.ep7r, "CTR_RX"); + + // CNTR bitfields. + state->u.f1.fld.cntr.fres = cm_object_get_child_by_name(state->u.f1.reg.cntr, "FRES"); + state->u.f1.fld.cntr.pdwn = cm_object_get_child_by_name(state->u.f1.reg.cntr, "PDWN"); + state->u.f1.fld.cntr.lpmode = cm_object_get_child_by_name(state->u.f1.reg.cntr, "LPMODE"); + state->u.f1.fld.cntr.fsusp = cm_object_get_child_by_name(state->u.f1.reg.cntr, "FSUSP"); + state->u.f1.fld.cntr.resume = cm_object_get_child_by_name(state->u.f1.reg.cntr, "RESUME"); + state->u.f1.fld.cntr.esofm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "ESOFM"); + state->u.f1.fld.cntr.sofm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "SOFM"); + state->u.f1.fld.cntr.resetm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "RESETM"); + state->u.f1.fld.cntr.suspm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "SUSPM"); + state->u.f1.fld.cntr.wkupm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "WKUPM"); + state->u.f1.fld.cntr.errm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "ERRM"); + state->u.f1.fld.cntr.pmaovrm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "PMAOVRM"); + state->u.f1.fld.cntr.ctrm = cm_object_get_child_by_name(state->u.f1.reg.cntr, "CTRM"); + + // ISTR bitfields. + state->u.f1.fld.istr.ep_id = cm_object_get_child_by_name(state->u.f1.reg.istr, "EP_ID"); + state->u.f1.fld.istr.dir = cm_object_get_child_by_name(state->u.f1.reg.istr, "DIR"); + state->u.f1.fld.istr.esof = cm_object_get_child_by_name(state->u.f1.reg.istr, "ESOF"); + state->u.f1.fld.istr.sof = cm_object_get_child_by_name(state->u.f1.reg.istr, "SOF"); + state->u.f1.fld.istr.reset = cm_object_get_child_by_name(state->u.f1.reg.istr, "RESET"); + state->u.f1.fld.istr.susp = cm_object_get_child_by_name(state->u.f1.reg.istr, "SUSP"); + state->u.f1.fld.istr.wkup = cm_object_get_child_by_name(state->u.f1.reg.istr, "WKUP"); + state->u.f1.fld.istr.err = cm_object_get_child_by_name(state->u.f1.reg.istr, "ERR"); + state->u.f1.fld.istr.pmaovr = cm_object_get_child_by_name(state->u.f1.reg.istr, "PMAOVR"); + state->u.f1.fld.istr.ctr = cm_object_get_child_by_name(state->u.f1.reg.istr, "CTR"); + + // FNR bitfields. + state->u.f1.fld.fnr.fn = cm_object_get_child_by_name(state->u.f1.reg.fnr, "FN"); + state->u.f1.fld.fnr.lsof = cm_object_get_child_by_name(state->u.f1.reg.fnr, "LSOF"); + state->u.f1.fld.fnr.lck = cm_object_get_child_by_name(state->u.f1.reg.fnr, "LCK"); + state->u.f1.fld.fnr.rxdm = cm_object_get_child_by_name(state->u.f1.reg.fnr, "RXDM"); + state->u.f1.fld.fnr.rxdp = cm_object_get_child_by_name(state->u.f1.reg.fnr, "RXDP"); + + // DADDR bitfields. + state->u.f1.fld.daddr.add = cm_object_get_child_by_name(state->u.f1.reg.daddr, "ADD"); + state->u.f1.fld.daddr.ef = cm_object_get_child_by_name(state->u.f1.reg.daddr, "EF"); + + // BTABLE bitfields. + state->u.f1.fld.btable.btable = cm_object_get_child_by_name(state->u.f1.reg.btable, "BTABLE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usb_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usb_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usb_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usb_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USBState *state = STM32_USB_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usb_is_enabled(Object *obj) +{ + STM32USBState *state = STM32_USB_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usb_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USBState *state = STM32_USB_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usb_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USB)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USBState *state = STM32_USB_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USB"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_usb_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_usb_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_usb_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USBEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usb_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USB); +} + +static void stm32_usb_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usb_reset_callback; + dc->realize = stm32_usb_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usb_is_enabled; +} + +static const TypeInfo stm32_usb_type_info = { + .name = TYPE_STM32_USB, + .parent = TYPE_STM32_USB_PARENT, + .instance_init = stm32_usb_instance_init_callback, + .instance_size = sizeof(STM32USBState), + .class_init = stm32_usb_class_init_callback, + .class_size = sizeof(STM32USBClass) }; + +static void stm32_usb_register_types(void) +{ + type_register_static(&stm32_usb_type_info); +} + +type_init(stm32_usb_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/usb.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/usb.h new file mode 100644 index 0000000000..adc372ec0e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/usb.h @@ -0,0 +1,275 @@ +/* + * STM32 - USB (Universal serial bus full-speed device interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USB_H_ +#define STM32_USB_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USB DEVICE_PATH_STM32 "USB" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USB TYPE_STM32_PREFIX "usb" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USB_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USBParentClass; +typedef PeripheralState STM32USBParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USB_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USBClass, (obj), TYPE_STM32_USB) +#define STM32_USB_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USBClass, (klass), TYPE_STM32_USB) + +typedef struct { + // private: + STM32USBParentClass parent_class; + // public: + + // None, so far. +} STM32USBClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USB_STATE(obj) \ + OBJECT_CHECK(STM32USBState, (obj), TYPE_STM32_USB) + +typedef struct { + // private: + STM32USBParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 USB (Universal serial bus full-speed device interface) registers. + struct { + Object *ep0r; // 0x0 (Endpoint 0 register) + Object *ep1r; // 0x4 (Endpoint 1 register) + Object *ep2r; // 0x8 (Endpoint 2 register) + Object *ep3r; // 0xC (Endpoint 3 register) + Object *ep4r; // 0x10 (Endpoint 4 register) + Object *ep5r; // 0x14 (Endpoint 5 register) + Object *ep6r; // 0x18 (Endpoint 6 register) + Object *ep7r; // 0x1C (Endpoint 7 register) + Object *cntr; // 0x40 (Control register) + Object *istr; // 0x44 (Interrupt status register) + Object *fnr; // 0x48 (Frame number register) + Object *daddr; // 0x4C (Device address) + Object *btable; // 0x50 (Buffer table address) + } reg; + + struct { + + // EP0R (Endpoint 0 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep0r; + + // EP1R (Endpoint 1 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep1r; + + // EP2R (Endpoint 2 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep2r; + + // EP3R (Endpoint 3 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep3r; + + // EP4R (Endpoint 4 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep4r; + + // EP5R (Endpoint 5 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep5r; + + // EP6R (Endpoint 6 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep6r; + + // EP7R (Endpoint 7 register) bitfields. + struct { + Object *ea; // [0:3] Endpoint address + Object *stat_tx; // [4:5] Status bits, for transmission transfers + Object *dtog_tx; // [6:6] Data Toggle, for transmission transfers + Object *ctr_tx; // [7:7] Correct Transfer for transmission + Object *ep_kind; // [8:8] Endpoint kind + Object *ep_type; // [9:10] Endpoint type + Object *setup; // [11:11] Setup transaction completed + Object *stat_rx; // [12:13] Status bits, for reception transfers + Object *dtog_rx; // [14:14] Data Toggle, for reception transfers + Object *ctr_rx; // [15:15] Correct transfer for reception + } ep7r; + + // CNTR (Control register) bitfields. + struct { + Object *fres; // [0:0] Force USB Reset + Object *pdwn; // [1:1] Power down + Object *lpmode; // [2:2] Low-power mode + Object *fsusp; // [3:3] Force suspend + Object *resume; // [4:4] Resume request + Object *esofm; // [8:8] Expected start of frame interrupt mask + Object *sofm; // [9:9] Start of frame interrupt mask + Object *resetm; // [10:10] USB reset interrupt mask + Object *suspm; // [11:11] Suspend mode interrupt mask + Object *wkupm; // [12:12] Wakeup interrupt mask + Object *errm; // [13:13] Error interrupt mask + Object *pmaovrm; // [14:14] Packet memory area over / underrun interrupt mask + Object *ctrm; // [15:15] Correct transfer interrupt mask + } cntr; + + // ISTR (Interrupt status register) bitfields. + struct { + Object *ep_id; // [0:3] Endpoint Identifier + Object *dir; // [4:4] Direction of transaction + Object *esof; // [8:8] Expected start frame + Object *sof; // [9:9] Start of frame + Object *reset; // [10:10] Reset request + Object *susp; // [11:11] Suspend mode request + Object *wkup; // [12:12] Wakeup + Object *err; // [13:13] Error + Object *pmaovr; // [14:14] Packet memory area over / underrun + Object *ctr; // [15:15] Correct transfer + } istr; + + // FNR (Frame number register) bitfields. + struct { + Object *fn; // [0:10] Frame number + Object *lsof; // [11:12] Lost SOF + Object *lck; // [13:13] Locked + Object *rxdm; // [14:14] Receive data - line status + Object *rxdp; // [15:15] Receive data + line status + } fnr; + + // DADDR (Device address) bitfields. + struct { + Object *add; // [0:6] Device address + Object *ef; // [7:7] Enable function + } daddr; + + // BTABLE (Buffer table address) bitfields. + struct { + Object *btable; // [3:15] Buffer table + } btable; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USBState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USB_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/wwdg.c b/gnu-mcu-eclipse/devices/support/STM32F103xx/wwdg.c new file mode 100644 index 0000000000..ff4d1f4ff1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/wwdg.c @@ -0,0 +1,249 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f103xx_wwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.cfr = cm_object_get_child_by_name(obj, "CFR"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f1.fld.cr.t = cm_object_get_child_by_name(state->u.f1.reg.cr, "T"); + state->u.f1.fld.cr.wdga = cm_object_get_child_by_name(state->u.f1.reg.cr, "WDGA"); + + // CFR bitfields. + state->u.f1.fld.cfr.w = cm_object_get_child_by_name(state->u.f1.reg.cfr, "W"); + state->u.f1.fld.cfr.wdgtb = cm_object_get_child_by_name(state->u.f1.reg.cfr, "WDGTB"); + state->u.f1.fld.cfr.ewi = cm_object_get_child_by_name(state->u.f1.reg.cfr, "EWI"); + + // SR bitfields. + state->u.f1.fld.sr.ewi = cm_object_get_child_by_name(state->u.f1.reg.sr, "EWI"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_wwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_wwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_wwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_wwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_wwdg_is_enabled(Object *obj) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_wwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_wwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_WWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32WWDGState *state = STM32_WWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "WWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_103xx ) { + + stm32f103xx_wwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_wwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_wwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_wwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_wwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/WWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_wwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_WWDG); +} + +static void stm32_wwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_wwdg_reset_callback; + dc->realize = stm32_wwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_wwdg_is_enabled; +} + +static const TypeInfo stm32_wwdg_type_info = { + .name = TYPE_STM32_WWDG, + .parent = TYPE_STM32_WWDG_PARENT, + .instance_init = stm32_wwdg_instance_init_callback, + .instance_size = sizeof(STM32WWDGState), + .class_init = stm32_wwdg_class_init_callback, + .class_size = sizeof(STM32WWDGClass) }; + +static void stm32_wwdg_register_types(void) +{ + type_register_static(&stm32_wwdg_type_info); +} + +type_init(stm32_wwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F103xx/wwdg.h b/gnu-mcu-eclipse/devices/support/STM32F103xx/wwdg.h new file mode 100644 index 0000000000..7b0bc72dab --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F103xx/wwdg.h @@ -0,0 +1,120 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_WWDG_H_ +#define STM32_WWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_WWDG DEVICE_PATH_STM32 "WWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_WWDG TYPE_STM32_PREFIX "wwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_WWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32WWDGParentClass; +typedef PeripheralState STM32WWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_WWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32WWDGClass, (obj), TYPE_STM32_WWDG) +#define STM32_WWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32WWDGClass, (klass), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentClass parent_class; + // public: + + // None, so far. +} STM32WWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_WWDG_STATE(obj) \ + OBJECT_CHECK(STM32WWDGState, (obj), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 WWDG (Window watchdog) registers. + struct { + Object *cr; // 0x0 (Control register (WWDG_CR)) + Object *cfr; // 0x4 (Configuration register (WWDG_CFR)) + Object *sr; // 0x8 (Status register (WWDG_SR)) + } reg; + + struct { + + // CR (Control register (WWDG_CR)) bitfields. + struct { + Object *t; // [0:6] 7-bit counter (MSB to LSB) + Object *wdga; // [7:7] Activation bit + } cr; + + // CFR (Configuration register (WWDG_CFR)) bitfields. + struct { + Object *w; // [0:6] 7-bit window value + Object *wdgtb; // [7:8] Timer Base + Object *ewi; // [9:9] Early Wakeup Interrupt + } cfr; + + // SR (Status register (WWDG_SR)) bitfields. + struct { + Object *ewi; // [0:0] Early Wakeup Interrupt + } sr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32WWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_WWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx-patch.json b/gnu-mcu-eclipse/devices/support/STM32F107xx-patch.json new file mode 100644 index 0000000000..e326aaf1da --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx-patch.json @@ -0,0 +1,151 @@ +{ + "comment": "Patch for QEMU use.", + "device": { + "name": "STM32F107xx", + "cpu": { + "name": "CM3", + "revision": "r1p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "false", + "nvicPrioBits": "4", + "deviceNumInterrupts": "68", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "access": "read-write", + "qemuAlignment": "any", + "peripherals": [ + { + "name": "EXTI", + "qemuAlignment": "word" + }, + { + "name": "FLASH", + "qemuAlignment": "any" + }, + { + "name": "PWR", + "qemuAlignment": "word-halfWord" + }, + { + "name": "RCC", + "qemuAlignment": "any" + }, + { + "name": "SYSCFG", + "qemuAlignment": "any" + }, + { + "name": "GPIOA", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "qemuAlignment": "word", + "qemuGroupName": "GPIO" + }, + { + "name": "USART1", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART2", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART3", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART4", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART5", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART6", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART7", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART8", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "DMA1", + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "qemuGroupName": "DMA" + }, + { + "name": "I2C1", + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "qemuGroupName": "I2C" + }, + { + "name": "SPI1", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "qemuGroupName": "SPI" + }, + { + "name": "ADC1", + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "qemuGroupName": "ADC" + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx-xsvd.json b/gnu-mcu-eclipse/devices/support/STM32F107xx-xsvd.json new file mode 100644 index 0000000000..7a20d60227 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx-xsvd.json @@ -0,0 +1,33373 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F107xx.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.10", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F107xx.svd", + "--output", + "STM32F107xx-xsvd.json" + ], + "date": "2016-12-26T08:23:50.887Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F107xx", + "version": "1.2", + "description": "STM32F107xx", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LPDS", + "description": "Low Power Deep Sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power Down Deep Sleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear Wake-up Flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear STANDBY Flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power Voltage Detector Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD Level Selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable Backup Domain write protection", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control register (PWR_CR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wake-Up Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "STANDBY Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD Output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40021000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "HSION", + "description": "Internal High Speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal High Speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal High Speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal High Speed clock Calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "External High Speed clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "External High Speed clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEBYP", + "description": "External High Speed clock Bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock Security System enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLON", + "description": "PLL enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "PLL clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL2ON", + "description": "PLL2 enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL2RDY", + "description": "PLL2 clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL3ON", + "description": "PLL3 enable", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL3RDY", + "description": "PLL3 clock ready flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register (RCC_CFGR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SW", + "description": "System clock Switch", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SWS", + "description": "System Clock Switch Status", + "bitOffset": "2", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB High speed prescaler (APB2)", + "bitOffset": "11", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "14", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PLLSRC", + "description": "PLL entry clock source", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLXTPRE", + "description": "HSE divider for PLL entry", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLMUL", + "description": "PLL Multiplication Factor", + "bitOffset": "18", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "OTGFSPRE", + "description": "USB OTG FS prescaler", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO", + "description": "Microcontroller clock output", + "bitOffset": "24", + "bitWidth": "4", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register (RCC_CIR)", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI Ready Interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE Ready Interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI Ready Interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE Ready Interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "PLL Ready Interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL2RDYF", + "description": "PLL2 Ready Interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLL3RDYF", + "description": "PLL3 Ready Interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CSSF", + "description": "Clock Security System Interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYIE", + "description": "LSI Ready Interrupt Enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE Ready Interrupt Enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI Ready Interrupt Enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE Ready Interrupt Enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "PLL Ready Interrupt Enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL2RDYIE", + "description": "PLL2 Ready Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLL3RDYIE", + "description": "PLL3 Ready Interrupt Enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYC", + "description": "LSI Ready Interrupt Clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE Ready Interrupt Clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI Ready Interrupt Clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE Ready Interrupt Clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "PLL Ready Interrupt Clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLL2RDYC", + "description": "PLL2 Ready Interrupt Clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLL3RDYC", + "description": "PLL3 Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register (RCC_APB2RSTR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000000", + "fields": [ + { + "name": "AFIORST", + "description": "Alternate function I/O reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPARST", + "description": "IO port A reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBRST", + "description": "IO port B reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCRST", + "description": "IO port C reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDRST", + "description": "IO port D reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPERST", + "description": "IO port E reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ADC1RST", + "description": "ADC 1 interface reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2RST", + "description": "ADC 2 interface reset", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 timer reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register (RCC_APB1RSTR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "Timer 2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "Timer 3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "Timer 4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "Timer 5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "Timer 6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "Timer 7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART4RST", + "description": "USART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART5RST", + "description": "USART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CAN1RST", + "description": "CAN1 reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2RST", + "description": "CAN2 reset", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BKPRST", + "description": "Backup interface reset", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC interface reset", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "AHBENR", + "displayName": "AHBENR", + "description": "AHB Peripheral Clock enable register (RCC_AHBENR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SRAMEN", + "description": "SRAM interface clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FLITFEN", + "description": "FLITF clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ETHMACEN", + "description": "Ethernet MAC clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETHMACTXEN", + "description": "Ethernet MAC TX clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ETHMACRXEN", + "description": "Ethernet MAC RX clock enable", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register (RCC_APB2ENR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFIOEN", + "description": "Alternate function I/O clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IOPAEN", + "description": "I/O port A clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IOPBEN", + "description": "I/O port B clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IOPCEN", + "description": "I/O port C clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IOPDEN", + "description": "I/O port D clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IOPEEN", + "description": "I/O port E clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC 1 interface clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC 2 interface clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 Timer clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI 1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register (RCC_APB1ENR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "Timer 2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "Timer 3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "Timer 4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "Timer 5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "Timer 6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "Timer 7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI 2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI 3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART 3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART 4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART 5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C 1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C 2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CAN1EN", + "description": "CAN1 clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2EN", + "description": "CAN2 clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BKPEN", + "description": "Backup interface clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register (RCC_BDCR)", + "addressOffset": "0x20", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LSEON", + "description": "External Low Speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External Low Speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEBYP", + "description": "External Low Speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Control/status register (RCC_CSR)", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x0C000000", + "fields": [ + { + "name": "LSION", + "description": "Internal low speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PINRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IWDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "AHBRSTR", + "displayName": "AHBRSTR", + "description": "AHB peripheral clock reset register (RCC_AHBRSTR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSRST", + "description": "USB OTG FS reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ETHMACRST", + "description": "Ethernet MAC reset", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR2", + "displayName": "CFGR2", + "description": "Clock configuration register2 (RCC_CFGR2)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PREDIV1", + "description": "PREDIV1 division factor", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "PREDIV2", + "description": "PREDIV2 division factor", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "PLL2MUL", + "description": "PLL2 Multiplication Factor", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "PLL3MUL", + "description": "PLL3 Multiplication Factor", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "PREDIV1SRC", + "description": "PREDIV1 entry clock source", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2S2SRC", + "description": "I2S2 clock source", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "I2S3SRC", + "description": "I2S3 clock source", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General purpose I/O", + "groupName": "GPIO", + "baseAddress": "0x40010800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CRL", + "displayName": "CRL", + "description": "Port configuration register low (GPIOn_CRL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE0", + "description": "Port n.0 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF0", + "description": "Port n.0 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE1", + "description": "Port n.1 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF1", + "description": "Port n.1 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE2", + "description": "Port n.2 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF2", + "description": "Port n.2 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE3", + "description": "Port n.3 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF3", + "description": "Port n.3 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE4", + "description": "Port n.4 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF4", + "description": "Port n.4 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE5", + "description": "Port n.5 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF5", + "description": "Port n.5 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE6", + "description": "Port n.6 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF6", + "description": "Port n.6 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE7", + "description": "Port n.7 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF7", + "description": "Port n.7 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "CRH", + "displayName": "CRH", + "description": "Port configuration register high (GPIOn_CRL)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x44444444", + "fields": [ + { + "name": "MODE8", + "description": "Port n.8 mode bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "CNF8", + "description": "Port n.8 configuration bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE9", + "description": "Port n.9 mode bits", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CNF9", + "description": "Port n.9 configuration bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODE10", + "description": "Port n.10 mode bits", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "CNF10", + "description": "Port n.10 configuration bits", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODE11", + "description": "Port n.11 mode bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CNF11", + "description": "Port n.11 configuration bits", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODE12", + "description": "Port n.12 mode bits", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CNF12", + "description": "Port n.12 configuration bits", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODE13", + "description": "Port n.13 mode bits", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "CNF13", + "description": "Port n.13 configuration bits", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODE14", + "description": "Port n.14 mode bits", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "CNF14", + "description": "Port n.14 configuration bits", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODE15", + "description": "Port n.15 mode bits", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "CNF15", + "description": "Port n.15 configuration bits", + "bitOffset": "30", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Port input data register (GPIOn_IDR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR0", + "description": "Port input data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR15", + "description": "Port input data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "Port output data register (GPIOn_ODR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR0", + "description": "Port output data", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR15", + "description": "Port output data", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "Port bit set/reset register (GPIOn_BSRR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BS0", + "description": "Set bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Set bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Set bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Set bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Set bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Set bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Set bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Set bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Set bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Set bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Set bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Set bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Set bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Set bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Set bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Set bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 2", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Port bit reset register (GPIOn_BRR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR0", + "description": "Reset bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Reset bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Reset bit 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Reset bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Reset bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Reset bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Reset bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Reset bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Reset bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Reset bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Reset bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Reset bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Reset bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Reset bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Reset bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BR15", + "description": "Reset bit 15", + "bitOffset": "15", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "Port configuration lock register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCK0", + "description": "Port A Lock bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port A Lock bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port A Lock bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port A Lock bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port A Lock bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port A Lock bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port A Lock bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port A Lock bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port A Lock bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port A Lock bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port A Lock bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port A Lock bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port A Lock bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port A Lock bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port A Lock bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port A Lock bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCKK", + "description": "Lock key", + "bitOffset": "16", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "GPIOB", + "derivedFrom": "GPIOA", + "baseAddress": "0x40010C00" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011000" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011400" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOA", + "baseAddress": "0x40011800" + }, + { + "name": "AFIO", + "description": "Alternate function I/O", + "groupName": "AFIO", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "EVCR", + "displayName": "EVCR", + "description": "Event Control Register (AFIO_EVCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PIN", + "description": "Pin selection", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "PORT", + "description": "Port selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "EVOE", + "description": "Event Output Enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "MAPR", + "displayName": "MAPR", + "description": "AF remap and debug I/O configuration register (AFIO_MAPR)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SPI1_REMAP", + "description": "SPI1 remapping", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "I2C1_REMAP", + "description": "I2C1 remapping", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART1_REMAP", + "description": "USART1 remapping", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART2_REMAP", + "description": "USART2 remapping", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USART3_REMAP", + "description": "USART3 remapping", + "bitOffset": "4", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM1_REMAP", + "description": "TIM1 remapping", + "bitOffset": "6", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM2_REMAP", + "description": "TIM2 remapping", + "bitOffset": "8", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM3_REMAP", + "description": "TIM3 remapping", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "TIM4_REMAP", + "description": "TIM4 remapping", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CAN1_REMAP", + "description": "CAN1 remapping", + "bitOffset": "13", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "PD01_REMAP", + "description": "Port D0/Port D1 mapping on OSCIN/OSCOUT", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIM5CH4_IREMAP", + "description": "Set and cleared by software", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETH_REMAP", + "description": "Ethernet MAC I/O remapping", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CAN2_REMAP", + "description": "CAN2 I/O remapping", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MII_RMII_SEL", + "description": "MII or RMII selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SWJ_CFG", + "description": "Serial wire JTAG configuration", + "bitOffset": "24", + "bitWidth": "3", + "access": "write-only" + }, + { + "name": "SPI3_REMAP", + "description": "SPI3/I2S3 remapping", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIM2ITR1_IREMAP", + "description": "TIM2 internal trigger 1 remapping", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTP_PPS_REMAP", + "description": "Ethernet PTP PPS remapping", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1 (AFIO_EXTICR1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI0", + "description": "EXTI0 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI1 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI2 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI3", + "description": "EXTI3 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2 (AFIO_EXTICR2)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI4", + "description": "EXTI4 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI5 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI6 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI7", + "description": "EXTI7 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3 (AFIO_EXTICR3)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI8", + "description": "EXTI8 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI9 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI11", + "description": "EXTI11 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4 (AFIO_EXTICR4)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EXTI12", + "description": "EXTI12 configuration", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI13 configuration", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI14 configuration", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI15", + "description": "EXTI15 configuration", + "bitOffset": "12", + "bitWidth": "4" + } + ] + }, + { + "name": "MAPR2", + "displayName": "MAPR2", + "description": "AF remap and debug I/O configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM9_REMAP", + "description": "TIM9 remapping", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM10_REMAP", + "description": "TIM10 remapping", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM11_REMAP", + "description": "TIM11 remapping", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM13_REMAP", + "description": "TIM13 remapping", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIM14_REMAP", + "description": "TIM14 remapping", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSMC_NADV", + "description": "NADV connect/disconnect", + "bitOffset": "10", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "EXTI", + "description": "EXTI", + "groupName": "EXTI", + "baseAddress": "0x40010400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMPER", + "description": "Tamper interrupt", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA1", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA1_Channel1", + "description": "DMA1 Channel1 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Channel2", + "description": "DMA1 Channel2 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Channel3", + "description": "DMA1 Channel3 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Channel4", + "description": "DMA1 Channel4 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Channel5", + "description": "DMA1 Channel5 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Channel6", + "description": "DMA1 Channel6 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Channel7", + "description": "DMA1 Channel7 global interrupt", + "value": "17" + } + ], + "registers": [ + { + "name": "ISR", + "displayName": "ISR", + "description": "DMA interrupt status register (DMA_ISR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GIF1", + "description": "Channel 1 Global interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Channel 1 Transfer Complete flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Channel 1 Half Transfer Complete flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Channel 1 Transfer Error flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GIF2", + "description": "Channel 2 Global interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Channel 2 Transfer Complete flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Channel 2 Half Transfer Complete flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Channel 2 Transfer Error flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GIF3", + "description": "Channel 3 Global interrupt flag", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TCIF3", + "description": "Channel 3 Transfer Complete flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Channel 3 Half Transfer Complete flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Channel 3 Transfer Error flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "GIF4", + "description": "Channel 4 Global interrupt flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Channel 4 Transfer Complete flag", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Channel 4 Half Transfer Complete flag", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Channel 4 Transfer Error flag", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "GIF5", + "description": "Channel 5 Global interrupt flag", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Channel 5 Transfer Complete flag", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Channel 5 Half Transfer Complete flag", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Channel 5 Transfer Error flag", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "GIF6", + "description": "Channel 6 Global interrupt flag", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Channel 6 Transfer Complete flag", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Channel 6 Half Transfer Complete flag", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Channel 6 Transfer Error flag", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "GIF7", + "description": "Channel 7 Global interrupt flag", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "TCIF7", + "description": "Channel 7 Transfer Complete flag", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Channel 7 Half Transfer Complete flag", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Channel 7 Transfer Error flag", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "DMA interrupt flag clear register (DMA_IFCR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CGIF1", + "description": "Channel 1 Global interrupt clear", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CGIF2", + "description": "Channel 2 Global interrupt clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CGIF3", + "description": "Channel 3 Global interrupt clear", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CGIF4", + "description": "Channel 4 Global interrupt clear", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CGIF5", + "description": "Channel 5 Global interrupt clear", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CGIF6", + "description": "Channel 6 Global interrupt clear", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CGIF7", + "description": "Channel 7 Global interrupt clear", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Channel 1 Transfer Complete clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Channel 2 Transfer Complete clear", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CTCIF3", + "description": "Channel 3 Transfer Complete clear", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Channel 4 Transfer Complete clear", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Channel 5 Transfer Complete clear", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Channel 6 Transfer Complete clear", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CTCIF7", + "description": "Channel 7 Transfer Complete clear", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Channel 1 Half Transfer clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Channel 2 Half Transfer clear", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Channel 3 Half Transfer clear", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Channel 4 Half Transfer clear", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Channel 5 Half Transfer clear", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Channel 6 Half Transfer clear", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Channel 7 Half Transfer clear", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Channel 1 Transfer Error clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Channel 2 Transfer Error clear", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Channel 3 Transfer Error clear", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Channel 4 Transfer Error clear", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Channel 5 Transfer Error clear", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Channel 6 Transfer Error clear", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Channel 7 Transfer Error clear", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR1", + "displayName": "CNDTR1", + "description": "DMA channel 1 number of data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR1", + "displayName": "CPAR1", + "description": "DMA channel 1 peripheral address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR1", + "displayName": "CMAR1", + "description": "DMA channel 1 memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR2", + "displayName": "CNDTR2", + "description": "DMA channel 2 number of data register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR2", + "displayName": "CPAR2", + "description": "DMA channel 2 peripheral address register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR2", + "displayName": "CMAR2", + "description": "DMA channel 2 memory address register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR3", + "displayName": "CNDTR3", + "description": "DMA channel 3 number of data register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR3", + "displayName": "CPAR3", + "description": "DMA channel 3 peripheral address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR3", + "displayName": "CMAR3", + "description": "DMA channel 3 memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR4", + "displayName": "CNDTR4", + "description": "DMA channel 4 number of data register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR4", + "displayName": "CPAR4", + "description": "DMA channel 4 peripheral address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR4", + "displayName": "CMAR4", + "description": "DMA channel 4 memory address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR5", + "displayName": "CCR5", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR5", + "displayName": "CNDTR5", + "description": "DMA channel 5 number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR5", + "displayName": "CPAR5", + "description": "DMA channel 5 peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR5", + "displayName": "CMAR5", + "description": "DMA channel 5 memory address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR6", + "displayName": "CCR6", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR6", + "displayName": "CNDTR6", + "description": "DMA channel 6 number of data register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR6", + "displayName": "CPAR6", + "description": "DMA channel 6 peripheral address register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR6", + "displayName": "CMAR6", + "description": "DMA channel 6 memory address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CCR7", + "displayName": "CCR7", + "description": "DMA channel configuration register (DMA_CCR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN", + "description": "Channel enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half Transfer interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PSIZE", + "description": "Peripheral size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MSIZE", + "description": "Memory size", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PL", + "description": "Channel Priority level", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MEM2MEM", + "description": "Memory to memory mode", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CNDTR7", + "displayName": "CNDTR7", + "description": "DMA channel 7 number of data register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CPAR7", + "displayName": "CPAR7", + "description": "DMA channel 7 peripheral address register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMAR7", + "displayName": "CMAR7", + "description": "DMA channel 7 memory address register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DMA2", + "derivedFrom": "DMA1", + "baseAddress": "0x40020400", + "interrupts": [ + { + "name": "DMA2_Channel1", + "description": "DMA2 Channel1 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Channel2", + "description": "DMA2 Channel2 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Channel3", + "description": "DMA2 Channel3 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Channel4", + "description": "DMA2 Channel4 global interrupt", + "value": "59" + }, + { + "name": "DMA2_Channel5", + "description": "DMA2 Channel5 global interrupt", + "value": "60" + } + ] + }, + { + "name": "RTC", + "description": "Real time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC", + "description": "RTC global interrupt", + "value": "3" + }, + { + "name": "RTCAlarm", + "description": "RTC Alarms through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "CRH", + "displayName": "CRH", + "description": "RTC Control Register High", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SECIE", + "description": "Second interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ALRIE", + "description": "Alarm interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OWIE", + "description": "Overflow interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "CRL", + "displayName": "CRL", + "description": "RTC Control Register Low", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000020", + "fields": [ + { + "name": "SECF", + "description": "Second Flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRF", + "description": "Alarm Flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OWF", + "description": "Overflow Flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RSF", + "description": "Registers Synchronized Flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNF", + "description": "Configuration Flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTOFF", + "description": "RTC operation OFF", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRLH", + "displayName": "PRLH", + "description": "RTC Prescaler Load Register High", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PRLH", + "description": "RTC Prescaler Load Register High", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "PRLL", + "displayName": "PRLL", + "description": "RTC Prescaler Load Register Low", + "addressOffset": "0xC", + "size": "0x20", + "access": "write-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "PRLL", + "description": "RTC Prescaler Divider Register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DIVH", + "displayName": "DIVH", + "description": "RTC Prescaler Divider Register High", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DIVH", + "description": "RTC prescaler divider register high", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DIVL", + "displayName": "DIVL", + "description": "RTC Prescaler Divider Register Low", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x8000", + "fields": [ + { + "name": "DIVL", + "description": "RTC prescaler divider register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTH", + "displayName": "CNTH", + "description": "RTC Counter Register High", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTH", + "description": "RTC counter register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CNTL", + "displayName": "CNTL", + "description": "RTC Counter Register Low", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNTL", + "description": "RTC counter register Low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRH", + "displayName": "ALRH", + "description": "RTC Alarm Register High", + "addressOffset": "0x20", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRH", + "description": "RTC alarm register high", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ALRL", + "displayName": "ALRL", + "description": "RTC Alarm Register Low", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0xFFFF", + "fields": [ + { + "name": "ALRL", + "description": "RTC alarm register low", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "BKP", + "description": "Backup registers", + "groupName": "BKP", + "baseAddress": "0x40006C04", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR1", + "displayName": "DR1", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D1", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR2", + "displayName": "DR2", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D2", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR3", + "displayName": "DR3", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D3", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR4", + "displayName": "DR4", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D4", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR5", + "displayName": "DR5", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D5", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR6", + "displayName": "DR6", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D6", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR7", + "displayName": "DR7", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D7", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR8", + "displayName": "DR8", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D8", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR9", + "displayName": "DR9", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D9", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR10", + "displayName": "DR10", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D10", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR11", + "displayName": "DR11", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR11", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR12", + "displayName": "DR12", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR12", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR13", + "displayName": "DR13", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR13", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR14", + "displayName": "DR14", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D14", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR15", + "displayName": "DR15", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D15", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR16", + "displayName": "DR16", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D16", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR17", + "displayName": "DR17", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D17", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR18", + "displayName": "DR18", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D18", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR19", + "displayName": "DR19", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D19", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR20", + "displayName": "DR20", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D20", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR21", + "displayName": "DR21", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D21", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR22", + "displayName": "DR22", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D22", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR23", + "displayName": "DR23", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D23", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR24", + "displayName": "DR24", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D24", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR25", + "displayName": "DR25", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D25", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR26", + "displayName": "DR26", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D26", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR27", + "displayName": "DR27", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D27", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR28", + "displayName": "DR28", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D28", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR29", + "displayName": "DR29", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D29", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR30", + "displayName": "DR30", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D30", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR31", + "displayName": "DR31", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D31", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR32", + "displayName": "DR32", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D32", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR33", + "displayName": "DR33", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D33", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR34", + "displayName": "DR34", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D34", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR35", + "displayName": "DR35", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D35", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR36", + "displayName": "DR36", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D36", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR37", + "displayName": "DR37", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D37", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR38", + "displayName": "DR38", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D38", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR39", + "displayName": "DR39", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D39", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR40", + "displayName": "DR40", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D40", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR41", + "displayName": "DR41", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D41", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR42", + "displayName": "DR42", + "description": "Backup data register (BKP_DR)", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "D42", + "description": "Backup data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RTCCR", + "displayName": "RTCCR", + "description": "RTC clock calibration register (BKP_RTCCR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CAL", + "description": "Calibration value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "CCO", + "description": "Calibration Clock Output", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ASOE", + "description": "Alarm or second output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ASOS", + "description": "Alarm or second output selection", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Backup control register (BKP_CR)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPE", + "description": "Tamper pin enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPAL", + "description": "Tamper pin active level", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "BKP_CSR control/status register", + "addressOffset": "0x30", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTE", + "description": "Clear Tamper event", + "bitOffset": "0", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CTI", + "description": "Clear Tamper Interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TPIE", + "description": "Tamper Pin interrupt enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TEF", + "description": "Tamper Event Flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TIF", + "description": "Tamper Interrupt Flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + } + ] + } + ] + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register (IWDG_KR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register (IWDG_PR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register (IWDG_RLR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (IWDG_SR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (WWDG_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register (WWDG_CFR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000007F", + "fields": [ + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "WDGTB", + "description": "Timer Base", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register (WWDG_SR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EWI", + "description": "Early Wakeup Interrupt", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced timer", + "groupName": "TIM", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK", + "description": "TIM1 Break interrupt", + "value": "24" + }, + { + "name": "TIM1_UP", + "description": "TIM1 Update interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM", + "description": "TIM1 Trigger and Commutation interrupts", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timer", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PSC", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC1PSC", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM3", + "derivedFrom": "TIM2", + "baseAddress": "0x40000400", + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM2", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "derivedFrom": "TIM2", + "baseAddress": "0x40000C00", + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ] + }, + { + "name": "TIM6", + "description": "Basic timer", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6", + "description": "TIM6 global interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "I2C1", + "description": "Inter integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ] + }, + { + "name": "I2C2", + "derivedFrom": "I2C1", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ] + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C0", + "fields": [ + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ] + }, + { + "name": "USART3", + "derivedFrom": "USART1", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ] + }, + { + "name": "ADC1", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DUALMOD", + "description": "Dual mode selection", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sampling time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sampling time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "ADC2DATA", + "description": "ADC2 data", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "ADC2", + "description": "Analog to digital converter", + "groupName": "ADC", + "baseAddress": "0x40012800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupts", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "EXTTRIG", + "description": "External trigger conversion mode for regular channels", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JEXTTRIG", + "description": "External trigger conversion mode for injected channels", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RSTCAL", + "description": "Reset calibration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CAL", + "description": "A/D calibration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADON", + "description": "A/D converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP10", + "description": "Channel 10 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP11", + "description": "Channel 11 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP12", + "description": "Channel 12 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP13", + "description": "Channel 13 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP14", + "description": "Channel 14 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP15", + "description": "Channel 15 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP16", + "description": "Channel 16 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP17", + "description": "Channel 17 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMP0", + "description": "Channel 0 sampling time selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "SMP1", + "description": "Channel 1 sampling time selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "SMP2", + "description": "Channel 2 sampling time selection", + "bitOffset": "6", + "bitWidth": "3" + }, + { + "name": "SMP3", + "description": "Channel 3 sampling time selection", + "bitOffset": "9", + "bitWidth": "3" + }, + { + "name": "SMP4", + "description": "Channel 4 sampling time selection", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "SMP5", + "description": "Channel 5 sampling time selection", + "bitOffset": "15", + "bitWidth": "3" + }, + { + "name": "SMP6", + "description": "Channel 6 sampling time selection", + "bitOffset": "18", + "bitWidth": "3" + }, + { + "name": "SMP7", + "description": "Channel 7 sampling time selection", + "bitOffset": "21", + "bitWidth": "3" + }, + { + "name": "SMP8", + "description": "Channel 8 sampling time selection", + "bitOffset": "24", + "bitWidth": "3" + }, + { + "name": "SMP9", + "description": "Channel 9 sampling time selection", + "bitOffset": "27", + "bitWidth": "3" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "CAN2", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN2_TX", + "description": "CAN2 TX interrupts", + "value": "63" + }, + { + "name": "CAN2_RX0", + "description": "CAN2 RX0 interrupts", + "value": "64" + }, + { + "name": "CAN2_RX1", + "description": "CAN2 RX1 interrupts", + "value": "65" + }, + { + "name": "CAN2_SCE", + "description": "CAN2 SCE interrupt", + "value": "66" + } + ], + "registers": [ + { + "name": "CAN_MCR", + "displayName": "CAN_MCR", + "description": "CAN_MCR", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_MSR", + "displayName": "CAN_MSR", + "description": "CAN_MSR", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_TSR", + "displayName": "CAN_TSR", + "description": "CAN_TSR", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": 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"description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CAN_RF0R", + "displayName": "CAN_RF0R", + "description": "CAN_RF0R", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_RF1R", + "displayName": "CAN_RF1R", + "description": "CAN_RF1R", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "CAN_IER", + "displayName": "CAN_IER", + "description": "CAN_IER", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_ESR", + "displayName": "CAN_ESR", + "description": "CAN_ESR", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CAN_BTR", + "displayName": "CAN_BTR", + "description": "CAN_BTR", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + } + ] + }, + { + "name": "CAN_TI0R", + "displayName": "CAN_TI0R", + "description": "CAN_TI0R", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TDT0R", + "displayName": "CAN_TDT0R", + "description": "CAN_TDT0R", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_TDL0R", + "displayName": "CAN_TDL0R", + "description": "CAN_TDL0R", + "addressOffset": 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"bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_TDL1R", + "displayName": "CAN_TDL1R", + "description": "CAN_TDL1R", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH1R", + "displayName": "CAN_TDH1R", + "description": "CAN_TDH1R", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TI2R", + "displayName": "CAN_TI2R", + "description": "CAN_TI2R", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_TDT2R", + "displayName": "CAN_TDT2R", + "description": "CAN_TDT2R", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_TDL2R", + "displayName": "CAN_TDL2R", + "description": "CAN_TDL2R", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_TDH2R", + "displayName": "CAN_TDH2R", + "description": "CAN_TDH2R", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RI0R", + "displayName": "CAN_RI0R", + "description": "CAN_RI0R", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_RDT0R", + "displayName": "CAN_RDT0R", + "description": "CAN_RDT0R", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_RDL0R", + "displayName": "CAN_RDL0R", + "description": "CAN_RDL0R", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", 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+ "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_RDT1R", + "displayName": "CAN_RDT1R", + "description": "CAN_RDT1R", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CAN_RDL1R", + "displayName": "CAN_RDL1R", + "description": "CAN_RDL1R", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_RDH1R", + "displayName": "CAN_RDH1R", + "description": "CAN_RDH1R", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CAN_FMR", + "displayName": "CAN_FMR", + "description": "CAN_FMR", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CAN2SB", + "description": "CAN2SB", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FM1R", + "displayName": "CAN_FM1R", + "description": "CAN_FM1R", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FBM14", + "description": "Filter mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FS1R", + "displayName": "CAN_FS1R", + "description": "CAN_FS1R", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FFA1R", + "displayName": "CAN_FFA1R", + "description": "CAN_FFA1R", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "CAN_FA1R", + "displayName": "CAN_FA1R", + "description": "CAN_FA1R", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN1", + "derivedFrom": "CAN2", + "baseAddress": "0x40006400", + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupts", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ] + }, + { + "name": "ETHERNET_MAC", + "description": "Ethernet: media access control", + "groupName": "ETHERNET", + "baseAddress": "0x40028000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ETH", + "description": "Ethernet global interrupt", + "value": "61" + }, + { + "name": "ETH_WKUP", + "description": "Ethernet Wakeup through EXTI line interrupt", + "value": "62" + } + ], + "registers": [ + { + "name": "MACCR", + "displayName": "MACCR", + "description": "Ethernet MAC configuration register (ETH_MACCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00008000", + "fields": [ + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "Deferral check", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BL", + "description": "Back-off limit", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "APCS", + "description": "Automatic pad/CRC stripping", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RD", + "description": "Retry disable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IPCO", + "description": "IPv4 checksum offload", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DM", + "description": "Duplex mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LM", + "description": "Loopback mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ROD", + "description": "Receive own disable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FES", + "description": "Fast Ethernet speed", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CSD", + "description": "Carrier sense disable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "IFG", + "description": "Interframe gap", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JD", + "description": "Jabber disable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WD", + "description": "Watchdog disable", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "MACFFR", + "displayName": "MACFFR", + "description": "Ethernet MAC frame filter register (ETH_MACCFFR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "Promiscuous mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "Hash unicast", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HM", + "description": "Hash multicast", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAIF", + "description": "Destination address inverse filtering", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PAM", + "description": "Pass all multicast", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BFD", + "description": "Broadcast frames disable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PCF", + "description": "Pass control frames", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "SAIF", + "description": "Source address inverse filtering", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SAF", + "description": "Source address filter", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HPF", + "description": "Hash or perfect filter", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "RA", + "description": "Receive all", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACHTHR", + "displayName": "MACHTHR", + "description": "Ethernet MAC hash table high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTH", + "description": "Hash table high", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACHTLR", + "displayName": "MACHTLR", + "description": "Ethernet MAC hash table low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTL", + "description": "Hash table low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACMIIAR", + "displayName": "MACMIIAR", + "description": "Ethernet MAC MII address register (ETH_MACMIIAR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MB", + "description": "MII busy", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MW", + "description": "MII write", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CR", + "description": "Clock range", + "bitOffset": "2", + "bitWidth": "3" + }, + { + "name": "MR", + "description": "MII register", + "bitOffset": "6", + "bitWidth": "5" + }, + { + "name": "PA", + "description": "PHY address", + "bitOffset": "11", + "bitWidth": "5" + } + ] + }, + { + "name": "MACMIIDR", + "displayName": "MACMIIDR", + "description": "Ethernet MAC MII data register (ETH_MACMIIDR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MD", + "description": "MII data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "MACFCR", + "displayName": "MACFCR", + "description": "Ethernet MAC flow control register (ETH_MACFCR)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FCB_BPA", + "description": "Flow control busy/back pressure activate", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TFCE", + "description": "Transmit flow control enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RFCE", + "description": "Receive flow control enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UPFD", + "description": "Unicast pause frame detect", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLT", + "description": "Pause low threshold", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ZQPD", + "description": "Zero-quanta pause disable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PT", + "description": "Pass control frames", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "MACVLANTR", + "displayName": "MACVLANTR", + "description": "Ethernet MAC VLAN tag register (ETH_MACVLANTR)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VLANTI", + "description": "VLAN tag identifier (for receive frames)", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "VLANTC", + "description": "12-bit VLAN tag comparison", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MACRWUFFR", + "displayName": "MACRWUFFR", + "description": "Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000" + }, + { + "name": "MACPMTCSR", + "displayName": "MACPMTCSR", + "description": "Ethernet MAC PMT control and status register (ETH_MACPMTCSR)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PD", + "description": "Power down", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MPE", + "description": "Magic Packet enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WFE", + "description": "Wakeup frame enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MPR", + "description": "Magic packet received", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WFR", + "description": "Wakeup frame received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GU", + "description": "Global unicast", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WFFRPR", + "description": "Wakeup frame filter register pointer reset", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACSR", + "displayName": "MACSR", + "description": "Ethernet MAC interrupt status register (ETH_MACSR)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTS", + "description": "PMT status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MMCS", + "description": "MMC status", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MMCRS", + "description": "MMC receive status", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MMCTS", + "description": "MMC transmit status", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TSTS", + "description": "Time stamp trigger status", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACIMR", + "displayName": "MACIMR", + "description": "Ethernet MAC interrupt mask register (ETH_MACIMR)", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTIM", + "description": "PMT interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSTIM", + "description": "Time stamp trigger interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA0HR", + "displayName": "MACA0HR", + "description": "Ethernet MAC address 0 high register (ETH_MACA0HR)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x0010FFFF", + "fields": [ + { + "name": "MACA0H", + "description": "MAC address0 high", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "MO", + "description": "Always 1", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "MACA0LR", + "displayName": "MACA0LR", + "description": "Ethernet MAC address 0 low register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA0L", + "description": "MAC address0 low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA1HR", + "displayName": "MACA1HR", + "description": "Ethernet MAC address 1 high register (ETH_MACA1HR)", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA1H", + "description": "MAC address1 high", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "Mask byte control", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "Source address", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "Address enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA1LR", + "displayName": "MACA1LR", + "description": "Ethernet MAC address1 low register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA1L", + "description": "MAC address1 low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA2HR", + "displayName": "MACA2HR", + "description": "Ethernet MAC address 2 high register (ETH_MACA2HR)", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0050", + "fields": [ + { + "name": "ETH_MACA2HR", + "description": "Ethernet MAC address 2 high register", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "Mask byte control", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "Source address", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "Address enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA2LR", + "displayName": "MACA2LR", + "description": "Ethernet MAC address 2 low register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA2L", + "description": "MAC address2 low", + "bitOffset": "0", + "bitWidth": "31" + } + ] + }, + { + "name": "MACA3HR", + "displayName": "MACA3HR", + "description": "Ethernet MAC address 3 high register (ETH_MACA3HR)", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA3H", + "description": "MAC address3 high", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "Mask byte control", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "Source address", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "Address enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA3LR", + "displayName": "MACA3LR", + "description": "Ethernet MAC address 3 low register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MBCA3L", + "description": "MAC address3 low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ETHERNET_MMC", + "description": "Ethernet: MAC management counters", + "groupName": "ETHERNET", + "baseAddress": "0x40028100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MMCCR", + "displayName": "MMCCR", + "description": "Ethernet MMC control register (ETH_MMCCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Counter reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "Counter stop rollover", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "Reset on read", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "MMC counter freeze", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIR", + "displayName": "MMCRIR", + "description": "Ethernet MMC receive interrupt register (ETH_MMCRIR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCES", + "description": "Received frames CRC error status", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAES", + "description": "Received frames alignment error status", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFS", + "description": "Received Good Unicast Frames Status", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIR", + "displayName": "MMCTIR", + "description": "Ethernet MMC transmit interrupt register (ETH_MMCTIR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCS", + "description": "Transmitted good frames single collision status", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCS", + "description": "Transmitted good frames more single collision status", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFS", + "description": "Transmitted good frames status", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIMR", + "displayName": "MMCRIMR", + "description": "Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCEM", + "description": "Received frame CRC error mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAEM", + "description": "Received frames alignment error mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFM", + "description": "Received good unicast frames mask", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIMR", + "displayName": "MMCTIMR", + "description": "Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCM", + "description": "Transmitted good frames single collision mask", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCM", + "description": "Transmitted good frames more single collision mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFM", + "description": "Transmitted good frames mask", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTGFSCCR", + "displayName": "MMCTGFSCCR", + "description": "Ethernet MMC transmitted good frames after a single collision counter", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCC", + "description": "Transmitted good frames after a single collision counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFMSCCR", + "displayName": "MMCTGFMSCCR", + "description": "Ethernet MMC transmitted good frames after more than a single collision", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFMSCC", + "description": "Transmitted good frames after more than a single collision counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFCR", + "displayName": "MMCTGFCR", + "description": "Ethernet MMC transmitted good frames counter register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFC", + "description": "Transmitted good frames counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFCECR", + "displayName": "MMCRFCECR", + "description": "Ethernet MMC received frames with CRC error counter register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCFC", + "description": "Received frames with CRC error counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFAECR", + "displayName": "MMCRFAECR", + "description": "Ethernet MMC received frames with alignment error counter register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFAEC", + "description": "Received frames with alignment error counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRGUFCR", + "displayName": "MMCRGUFCR", + "description": "MMC received good unicast frames counter register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RGUFC", + "description": "Received good unicast frames counter", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ETHERNET_PTP", + "description": "Ethernet: Precision time protocol", + "groupName": "ETHERNET", + "baseAddress": "0x40028700", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "PTPTSCR", + "displayName": "PTPTSCR", + "description": "Ethernet PTP time stamp control register (ETH_PTPTSCR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSFCU", + "description": "Time stamp fine or coarse update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSSTI", + "description": "Time stamp system time initialize", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSSTU", + "description": "Time stamp system time update", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSITE", + "description": "Time stamp interrupt trigger enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TSARU", + "description": "Time stamp addend register update", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPSSIR", + "displayName": "PTPSSIR", + "description": "Ethernet PTP subsecond increment register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSSI", + "description": "System time subsecond increment", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PTPTSHR", + "displayName": "PTPTSHR", + "description": "Ethernet PTP time stamp high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STS", + "description": "System time second", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLR", + "displayName": "PTPTSLR", + "description": "Ethernet PTP time stamp low register (ETH_PTPTSLR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSS", + "description": "System time subseconds", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "STPNS", + "description": "System time positive or negative sign", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSHUR", + "displayName": "PTPTSHUR", + "description": "Ethernet PTP time stamp high update register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUS", + "description": "Time stamp update second", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLUR", + "displayName": "PTPTSLUR", + "description": "Ethernet PTP time stamp low update register (ETH_PTPTSLUR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUSS", + "description": "Time stamp update subseconds", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "TSUPNS", + "description": "Time stamp update positive or negative sign", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSAR", + "displayName": "PTPTSAR", + "description": "Ethernet PTP time stamp addend register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSA", + "description": "Time stamp addend", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTHR", + "displayName": "PTPTTHR", + "description": "Ethernet PTP target time high register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSH", + "description": "Target time stamp high", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTLR", + "displayName": "PTPTTLR", + "description": "Ethernet PTP target time low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSL", + "description": "Target time stamp low", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ETHERNET_DMA", + "description": "Ethernet: DMA controller operation", + "groupName": "ETHERNET", + "baseAddress": "0x40029000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DMABMR", + "displayName": "DMABMR", + "description": "Ethernet DMA bus mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20101", + "fields": [ + { + "name": "SR", + "description": "Software reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DA", + "description": "DMA Arbitration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DSL", + "description": "Descriptor skip length", + "bitOffset": "2", + "bitWidth": "5" + }, + { + "name": "PBL", + "description": "Programmable burst length", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "RTPR", + "description": "Rx Tx priority ratio", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "FB", + "description": "Fixed burst", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Rx DMA PBL", + "bitOffset": "17", + "bitWidth": "6" + }, + { + "name": "USP", + "description": "Use separate PBL", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FPM", + "description": "4xPBL mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AAB", + "description": "Address-aligned beats", + "bitOffset": "25", + "bitWidth": "1" + } + ] + }, + { + "name": "DMATPDR", + "displayName": "DMATPDR", + "description": "Ethernet DMA transmit poll demand register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPD", + "description": "Transmit poll demand", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARPDR", + "displayName": "DMARPDR", + "description": "EHERNET DMA receive poll demand register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RPD", + "description": "Receive poll demand", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARDLAR", + "displayName": "DMARDLAR", + "description": "Ethernet DMA receive descriptor list address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SRL", + "description": "Start of receive list", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMATDLAR", + "displayName": "DMATDLAR", + "description": "Ethernet DMA transmit descriptor list address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STL", + "description": "Start of transmit list", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMASR", + "displayName": "DMASR", + "description": "Ethernet DMA status register", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TS", + "description": "Transmit status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TPSS", + "description": "Transmit process stopped status", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TBUS", + "description": "Transmit buffer unavailable status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TJTS", + "description": "Transmit jabber timeout status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ROS", + "description": "Receive overflow status", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TUS", + "description": "Transmit underflow status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RS", + "description": "Receive status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RBUS", + "description": "Receive buffer unavailable status", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPSS", + "description": "Receive process stopped status", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PWTS", + "description": "Receive watchdog timeout status", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETS", + "description": "Early transmit status", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FBES", + "description": "Fatal bus error status", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERS", + "description": "Early receive status", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AIS", + "description": "Abnormal interrupt summary", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NIS", + "description": "Normal interrupt summary", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPS", + "description": "Receive process state", + "bitOffset": "17", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "TPS", + "description": "Transmit process state", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "EBS", + "description": "Error bits status", + "bitOffset": "23", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "MMC status", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PMTS", + "description": "PMT status", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "Time stamp trigger status", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DMAOMR", + "displayName": "DMAOMR", + "description": "Ethernet DMA operation mode register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SR", + "description": "SR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OSF", + "description": "OSF", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTC", + "description": "RTC", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "FUGF", + "description": "FUGF", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FEF", + "description": "FEF", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "ST", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TTC", + "description": "TTC", + "bitOffset": "14", + "bitWidth": "3" + }, + { + "name": "FTF", + "description": "FTF", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TSF", + "description": "TSF", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DFRF", + "description": "DFRF", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "RSF", + "description": "RSF", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DTCEFD", + "description": "DTCEFD", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAIER", + "displayName": "DMAIER", + "description": "Ethernet DMA interrupt enable register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIE", + "description": "Transmit interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPSIE", + "description": "Transmit process stopped interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TBUIE", + "description": "Transmit buffer unavailable interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TJTIE", + "description": "Transmit jabber timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ROIE", + "description": "Overflow interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TUIE", + "description": "Underflow interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RIE", + "description": "Receive interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RBUIE", + "description": "Receive buffer unavailable interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RPSIE", + "description": "Receive process stopped interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWTIE", + "description": "Receive watchdog timeout interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ETIE", + "description": "Early transmit interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBEIE", + "description": "Fatal bus error interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ERIE", + "description": "Early receive interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AISE", + "description": "Abnormal interrupt summary enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NISE", + "description": "Normal interrupt summary enable", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAMFBOCR", + "displayName": "DMAMFBOCR", + "description": "Ethernet DMA missed frame and buffer overflow counter register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MFC", + "description": "Missed frames by the controller", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OMFC", + "description": "Overflow bit for missed frame counter", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MFA", + "description": "Missed frames by the application", + "bitOffset": "17", + "bitWidth": "11" + }, + { + "name": "OFOC", + "description": "Overflow bit for FIFO overflow counter", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "DMACHTDR", + "displayName": "DMACHTDR", + "description": "Ethernet DMA current host transmit descriptor register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTDAP", + "description": "Host transmit descriptor address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRDR", + "displayName": "DMACHRDR", + "description": "Ethernet DMA current host receive descriptor register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRDAP", + "description": "Host receive descriptor address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHTBAR", + "displayName": "DMACHTBAR", + "description": "Ethernet DMA current host transmit buffer address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTBAP", + "description": "Host transmit buffer address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRBAR", + "displayName": "DMACHRBAR", + "description": "Ethernet DMA current host receive buffer address register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRBAP", + "description": "Host receive buffer address pointer", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "USB_OTG_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "7", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "USB_OTG_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "USB_OTG_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + } + ] + }, + { + "name": "USB_OTG_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DAC", + "description": "Digital to analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register (DAC_CR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "DAC software trigger register (DAC_SWTRIGR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "20", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "DAC channel1 data output register (DAC_DOR1)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "DAC channel2 data output register (DAC_DOR2)", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "IDCODE", + "displayName": "IDCODE", + "description": "DBGMCU_IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "DBGMCU_CR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "DBG_IWDG_STOP", + "description": "DBG_IWDG_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBG_TIM1_STOP", + "description": "DBG_TIM1_STOP", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "DBG_I2C1_SMBUS_TIMEOUT", + "description": "DBG_I2C1_SMBUS_TIMEOUT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "21", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "UART4", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART4 SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "Noise error flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART4 DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART4 BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART4 CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART4 CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART4 CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "UART5", + "description": "Universal asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40005000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "UART5 SR", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x0", + "fields": [ + { + "name": "PE", + "description": "PE", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "FE", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NE", + "description": "NE", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "ORE", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IDLE", + "description": "IDLE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "RXNE", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TC", + "description": "TC", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "TXE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LBD", + "description": "LBD", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "UART5 DR", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DR", + "description": "DR", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "UART5 BRR", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DIV_Fraction", + "description": "DIV_Fraction", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "DIV_Mantissa", + "description": "DIV_Mantissa", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "UART5 CR1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SBK", + "description": "SBK", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "RWU", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLEIE", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNEIE", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "TCIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXEIE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PEIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "PS", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "PCE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "WAKE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "M", + "description": "M", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "UE", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "UART5 CR2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "ADD", + "description": "ADD", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "LBDL", + "description": "LBDL", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LBDIE", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LINEN", + "description": "LINEN", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "UART5 CR3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "CRC calculation unit", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESET", + "description": "Reset bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000030", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "HLFCYA", + "description": "Flash half cycle access enable", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBE", + "description": "Prefetch buffer enable", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRFTBS", + "description": "Prefetch buffer status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPRTERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGERR", + "description": "Programming error", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PER", + "description": "Page Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OPTPG", + "description": "Option byte programming", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPTER", + "description": "Option byte erase", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPTWRE", + "description": "Option bytes write enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + } + ] + }, + { + "name": "AR", + "displayName": "AR", + "description": "Flash address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FAR", + "description": "Flash Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OBR", + "displayName": "OBR", + "description": "Option byte register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x03FFFFFC", + "fields": [ + { + "name": "OPTERR", + "description": "Option byte error", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "RDPRT", + "description": "Read protection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WDG_SW", + "description": "WDG_SW", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "Data0", + "description": "Data0", + "bitOffset": "10", + "bitWidth": "8" + }, + { + "name": "Data1", + "description": "Data1", + "bitOffset": "18", + "bitWidth": "8" + } + ] + }, + { + "name": "WRPR", + "displayName": "WRPR", + "description": "Write protection register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "WRP", + "description": "Write protect", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt\r Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1001", + "usage": "registers" + }, + { + "offset": "0x1001", + "size": "0xFFFFF3FF", + "usage": "reserved" + } + ], + "registers": [ + { + "name": "ICTR", + "displayName": "ICTR", + "description": "Interrupt Controller Type\r Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTLINESNUM", + "description": "Total number of interrupt lines in\r groups", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "STIR", + "displayName": "STIR", + "description": "Software Triggered Interrupt\r Register", + "addressOffset": "0xF00", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTID", + "description": "Interrupt to be triggered", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "ISER0", + "displayName": "ISER0", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER1", + "displayName": "ISER1", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER2", + "displayName": "ISER2", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER0", + "displayName": "ICER0", + "description": "Interrupt Clear-Enable\r Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER1", + "displayName": "ICER1", + "description": "Interrupt Clear-Enable\r Register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER2", + "displayName": "ICER2", + "description": "Interrupt Clear-Enable\r Register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR0", + "displayName": "ISPR0", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR1", + "displayName": "ISPR1", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR2", + "displayName": "ISPR2", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x208", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR0", + "displayName": "ICPR0", + "description": "Interrupt Clear-Pending\r Register", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR1", + "displayName": "ICPR1", + "description": "Interrupt Clear-Pending\r Register", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR2", + "displayName": "ICPR2", + "description": "Interrupt Clear-Pending\r Register", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR0", + "displayName": "IABR0", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR1", + "displayName": "IABR1", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR2", + "displayName": "IABR2", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register", + "addressOffset": "0x404", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register", + "addressOffset": "0x408", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register", + "addressOffset": "0x40C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register", + "addressOffset": "0x410", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register", + "addressOffset": "0x414", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register", + "addressOffset": "0x418", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register", + "addressOffset": "0x41C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR8", + "displayName": "IPR8", + "description": "Interrupt Priority Register", + "addressOffset": "0x420", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR9", + "displayName": "IPR9", + "description": "Interrupt Priority Register", + "addressOffset": "0x424", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR10", + "displayName": "IPR10", + "description": "Interrupt Priority Register", + "addressOffset": "0x428", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR11", + "displayName": "IPR11", + "description": "Interrupt Priority Register", + "addressOffset": "0x42C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR12", + "displayName": "IPR12", + "description": "Interrupt Priority Register", + "addressOffset": "0x430", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR13", + "displayName": "IPR13", + "description": "Interrupt Priority Register", + "addressOffset": "0x434", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR14", + "displayName": "IPR14", + "description": "Interrupt Priority Register", + "addressOffset": "0x438", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR15", + "displayName": "IPR15", + "description": "Interrupt Priority Register", + "addressOffset": "0x43C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR16", + "displayName": "IPR16", + "description": "Interrupt Priority Register", + "addressOffset": "0x440", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/adc1.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc1.c new file mode 100644 index 0000000000..ffdfb0b0d1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc1.c @@ -0,0 +1,382 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smpr1 = cm_object_get_child_by_name(obj, "SMPR1"); + state->u.f1.reg.smpr2 = cm_object_get_child_by_name(obj, "SMPR2"); + state->u.f1.reg.jofr1 = cm_object_get_child_by_name(obj, "JOFR1"); + state->u.f1.reg.jofr2 = cm_object_get_child_by_name(obj, "JOFR2"); + state->u.f1.reg.jofr3 = cm_object_get_child_by_name(obj, "JOFR3"); + state->u.f1.reg.jofr4 = cm_object_get_child_by_name(obj, "JOFR4"); + state->u.f1.reg.htr = cm_object_get_child_by_name(obj, "HTR"); + state->u.f1.reg.ltr = cm_object_get_child_by_name(obj, "LTR"); + state->u.f1.reg.sqr1 = cm_object_get_child_by_name(obj, "SQR1"); + state->u.f1.reg.sqr2 = cm_object_get_child_by_name(obj, "SQR2"); + state->u.f1.reg.sqr3 = cm_object_get_child_by_name(obj, "SQR3"); + state->u.f1.reg.jsqr = cm_object_get_child_by_name(obj, "JSQR"); + state->u.f1.reg.jdr1 = cm_object_get_child_by_name(obj, "JDR1"); + state->u.f1.reg.jdr2 = cm_object_get_child_by_name(obj, "JDR2"); + state->u.f1.reg.jdr3 = cm_object_get_child_by_name(obj, "JDR3"); + state->u.f1.reg.jdr4 = cm_object_get_child_by_name(obj, "JDR4"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // SR bitfields. + state->u.f1.fld.sr.awd = cm_object_get_child_by_name(state->u.f1.reg.sr, "AWD"); + state->u.f1.fld.sr.eoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "EOC"); + state->u.f1.fld.sr.jeoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "JEOC"); + state->u.f1.fld.sr.jstrt = cm_object_get_child_by_name(state->u.f1.reg.sr, "JSTRT"); + state->u.f1.fld.sr.strt = cm_object_get_child_by_name(state->u.f1.reg.sr, "STRT"); + + // CR1 bitfields. + state->u.f1.fld.cr1.awdch = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDCH"); + state->u.f1.fld.cr1.eocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "EOCIE"); + state->u.f1.fld.cr1.awdie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDIE"); + state->u.f1.fld.cr1.jeocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JEOCIE"); + state->u.f1.fld.cr1.scan = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SCAN"); + state->u.f1.fld.cr1.awdsgl = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDSGL"); + state->u.f1.fld.cr1.jauto = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAUTO"); + state->u.f1.fld.cr1.discen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCEN"); + state->u.f1.fld.cr1.jdiscen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JDISCEN"); + state->u.f1.fld.cr1.discnum = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCNUM"); + state->u.f1.fld.cr1.dualmod = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DUALMOD"); + state->u.f1.fld.cr1.jawden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAWDEN"); + state->u.f1.fld.cr1.awden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDEN"); + + // CR2 bitfields. + state->u.f1.fld.cr2.adon = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADON"); + state->u.f1.fld.cr2.cont = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CONT"); + state->u.f1.fld.cr2.cal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CAL"); + state->u.f1.fld.cr2.rstcal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RSTCAL"); + state->u.f1.fld.cr2.dma = cm_object_get_child_by_name(state->u.f1.reg.cr2, "DMA"); + state->u.f1.fld.cr2.align = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ALIGN"); + state->u.f1.fld.cr2.jextsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTSEL"); + state->u.f1.fld.cr2.jexttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTTRIG"); + state->u.f1.fld.cr2.extsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTSEL"); + state->u.f1.fld.cr2.exttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTTRIG"); + state->u.f1.fld.cr2.jswstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JSWSTART"); + state->u.f1.fld.cr2.swstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "SWSTART"); + state->u.f1.fld.cr2.tsvrefe = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TSVREFE"); + + // SMPR1 bitfields. + state->u.f1.fld.smpr1.smp10 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP10"); + state->u.f1.fld.smpr1.smp11 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP11"); + state->u.f1.fld.smpr1.smp12 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP12"); + state->u.f1.fld.smpr1.smp13 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP13"); + state->u.f1.fld.smpr1.smp14 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP14"); + state->u.f1.fld.smpr1.smp15 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP15"); + state->u.f1.fld.smpr1.smp16 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP16"); + state->u.f1.fld.smpr1.smp17 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP17"); + + // SMPR2 bitfields. + state->u.f1.fld.smpr2.smp0 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP0"); + state->u.f1.fld.smpr2.smp1 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP1"); + state->u.f1.fld.smpr2.smp2 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP2"); + state->u.f1.fld.smpr2.smp3 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP3"); + state->u.f1.fld.smpr2.smp4 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP4"); + state->u.f1.fld.smpr2.smp5 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP5"); + state->u.f1.fld.smpr2.smp6 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP6"); + state->u.f1.fld.smpr2.smp7 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP7"); + state->u.f1.fld.smpr2.smp8 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP8"); + state->u.f1.fld.smpr2.smp9 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP9"); + + // JOFR1 bitfields. + state->u.f1.fld.jofr1.joffset1 = cm_object_get_child_by_name(state->u.f1.reg.jofr1, "JOFFSET1"); + + // JOFR2 bitfields. + state->u.f1.fld.jofr2.joffset2 = cm_object_get_child_by_name(state->u.f1.reg.jofr2, "JOFFSET2"); + + // JOFR3 bitfields. + state->u.f1.fld.jofr3.joffset3 = cm_object_get_child_by_name(state->u.f1.reg.jofr3, "JOFFSET3"); + + // JOFR4 bitfields. + state->u.f1.fld.jofr4.joffset4 = cm_object_get_child_by_name(state->u.f1.reg.jofr4, "JOFFSET4"); + + // HTR bitfields. + state->u.f1.fld.htr.ht = cm_object_get_child_by_name(state->u.f1.reg.htr, "HT"); + + // LTR bitfields. + state->u.f1.fld.ltr.lt = cm_object_get_child_by_name(state->u.f1.reg.ltr, "LT"); + + // SQR1 bitfields. + state->u.f1.fld.sqr1.sq13 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ13"); + state->u.f1.fld.sqr1.sq14 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ14"); + state->u.f1.fld.sqr1.sq15 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ15"); + state->u.f1.fld.sqr1.sq16 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ16"); + state->u.f1.fld.sqr1.l = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "L"); + + // SQR2 bitfields. + state->u.f1.fld.sqr2.sq7 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ7"); + state->u.f1.fld.sqr2.sq8 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ8"); + state->u.f1.fld.sqr2.sq9 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ9"); + state->u.f1.fld.sqr2.sq10 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ10"); + state->u.f1.fld.sqr2.sq11 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ11"); + state->u.f1.fld.sqr2.sq12 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ12"); + + // SQR3 bitfields. + state->u.f1.fld.sqr3.sq1 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ1"); + state->u.f1.fld.sqr3.sq2 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ2"); + state->u.f1.fld.sqr3.sq3 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ3"); + state->u.f1.fld.sqr3.sq4 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ4"); + state->u.f1.fld.sqr3.sq5 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ5"); + state->u.f1.fld.sqr3.sq6 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ6"); + + // JSQR bitfields. + state->u.f1.fld.jsqr.jsq1 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ1"); + state->u.f1.fld.jsqr.jsq2 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ2"); + state->u.f1.fld.jsqr.jsq3 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ3"); + state->u.f1.fld.jsqr.jsq4 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ4"); + state->u.f1.fld.jsqr.jl = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JL"); + + // JDR1 bitfields. + state->u.f1.fld.jdr1.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr1, "JDATA"); + + // JDR2 bitfields. + state->u.f1.fld.jdr2.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr2, "JDATA"); + + // JDR3 bitfields. + state->u.f1.fld.jdr3.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr3, "JDATA"); + + // JDR4 bitfields. + state->u.f1.fld.jdr4.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr4, "JDATA"); + + // DR bitfields. + state->u.f1.fld.dr.data = cm_object_get_child_by_name(state->u.f1.reg.dr, "DATA"); + state->u.f1.fld.dr.adc2data = cm_object_get_child_by_name(state->u.f1.reg.dr, "ADC2DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_ADC_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC%dEN", + 1 + state->port_index - STM32_PORT_ADC1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/adc1.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc1.h new file mode 100644 index 0000000000..57a060f3d6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc1.h @@ -0,0 +1,293 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_ADC1, + STM32_PORT_ADC2, + STM32_PORT_ADC_UNDEFINED = 0xFF, +} stm32_adc_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_adc_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ADC (Analog to digital converter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *cr1; // 0x4 (Control register 1) + Object *cr2; // 0x8 (Control register 2) + Object *smpr1; // 0xC (Sample time register 1) + Object *smpr2; // 0x10 (Sample time register 2) + Object *jofr1; // 0x14 (Injected channel data offset register x) + Object *jofr2; // 0x18 (Injected channel data offset register x) + Object *jofr3; // 0x1C (Injected channel data offset register x) + Object *jofr4; // 0x20 (Injected channel data offset register x) + Object *htr; // 0x24 (Watchdog higher threshold register) + Object *ltr; // 0x28 (Watchdog lower threshold register) + Object *sqr1; // 0x2C (Regular sequence register 1) + Object *sqr2; // 0x30 (Regular sequence register 2) + Object *sqr3; // 0x34 (Regular sequence register 3) + Object *jsqr; // 0x38 (Injected sequence register) + Object *jdr1; // 0x3C (Injected data register x) + Object *jdr2; // 0x40 (Injected data register x) + Object *jdr3; // 0x44 (Injected data register x) + Object *jdr4; // 0x48 (Injected data register x) + Object *dr; // 0x4C (Regular data register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *awd; // [0:0] Analog watchdog flag + Object *eoc; // [1:1] Regular channel end of conversion + Object *jeoc; // [2:2] Injected channel end of conversion + Object *jstrt; // [3:3] Injected channel start flag + Object *strt; // [4:4] Regular channel start flag + } sr; + + // CR1 (Control register 1) bitfields. + struct { + Object *awdch; // [0:4] Analog watchdog channel select bits + Object *eocie; // [5:5] Interrupt enable for EOC + Object *awdie; // [6:6] Analog watchdog interrupt enable + Object *jeocie; // [7:7] Interrupt enable for injected channels + Object *scan; // [8:8] Scan mode + Object *awdsgl; // [9:9] Enable the watchdog on a single channel in scan mode + Object *jauto; // [10:10] Automatic injected group conversion + Object *discen; // [11:11] Discontinuous mode on regular channels + Object *jdiscen; // [12:12] Discontinuous mode on injected channels + Object *discnum; // [13:15] Discontinuous mode channel count + Object *dualmod; // [16:19] Dual mode selection + Object *jawden; // [22:22] Analog watchdog enable on injected channels + Object *awden; // [23:23] Analog watchdog enable on regular channels + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *adon; // [0:0] A/D converter ON / OFF + Object *cont; // [1:1] Continuous conversion + Object *cal; // [2:2] A/D calibration + Object *rstcal; // [3:3] Reset calibration + Object *dma; // [8:8] Direct memory access mode + Object *align; // [11:11] Data alignment + Object *jextsel; // [12:14] External event select for injected group + Object *jexttrig; // [15:15] External trigger conversion mode for injected channels + Object *extsel; // [17:19] External event select for regular group + Object *exttrig; // [20:20] External trigger conversion mode for regular channels + Object *jswstart; // [21:21] Start conversion of injected channels + Object *swstart; // [22:22] Start conversion of regular channels + Object *tsvrefe; // [23:23] Temperature sensor and VREFINT enable + } cr2; + + // SMPR1 (Sample time register 1) bitfields. + struct { + Object *smp10; // [0:2] Channel 10 sampling time selection + Object *smp11; // [3:5] Channel 11 sampling time selection + Object *smp12; // [6:8] Channel 12 sampling time selection + Object *smp13; // [9:11] Channel 13 sampling time selection + Object *smp14; // [12:14] Channel 14 sampling time selection + Object *smp15; // [15:17] Channel 15 sampling time selection + Object *smp16; // [18:20] Channel 16 sampling time selection + Object *smp17; // [21:23] Channel 17 sampling time selection + } smpr1; + + // SMPR2 (Sample time register 2) bitfields. + struct { + Object *smp0; // [0:2] Channel 0 sampling time selection + Object *smp1; // [3:5] Channel 1 sampling time selection + Object *smp2; // [6:8] Channel 2 sampling time selection + Object *smp3; // [9:11] Channel 3 sampling time selection + Object *smp4; // [12:14] Channel 4 sampling time selection + Object *smp5; // [15:17] Channel 5 sampling time selection + Object *smp6; // [18:20] Channel 6 sampling time selection + Object *smp7; // [21:23] Channel 7 sampling time selection + Object *smp8; // [24:26] Channel 8 sampling time selection + Object *smp9; // [27:29] Channel 9 sampling time selection + } smpr2; + + // JOFR1 (Injected channel data offset register x) bitfields. + struct { + Object *joffset1; // [0:11] Data offset for injected channel x + } jofr1; + + // JOFR2 (Injected channel data offset register x) bitfields. + struct { + Object *joffset2; // [0:11] Data offset for injected channel x + } jofr2; + + // JOFR3 (Injected channel data offset register x) bitfields. + struct { + Object *joffset3; // [0:11] Data offset for injected channel x + } jofr3; + + // JOFR4 (Injected channel data offset register x) bitfields. + struct { + Object *joffset4; // [0:11] Data offset for injected channel x + } jofr4; + + // HTR (Watchdog higher threshold register) bitfields. + struct { + Object *ht; // [0:11] Analog watchdog higher threshold + } htr; + + // LTR (Watchdog lower threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + } ltr; + + // SQR1 (Regular sequence register 1) bitfields. + struct { + Object *sq13; // [0:4] 13th conversion in regular sequence + Object *sq14; // [5:9] 14th conversion in regular sequence + Object *sq15; // [10:14] 15th conversion in regular sequence + Object *sq16; // [15:19] 16th conversion in regular sequence + Object *l; // [20:23] Regular channel sequence length + } sqr1; + + // SQR2 (Regular sequence register 2) bitfields. + struct { + Object *sq7; // [0:4] 7th conversion in regular sequence + Object *sq8; // [5:9] 8th conversion in regular sequence + Object *sq9; // [10:14] 9th conversion in regular sequence + Object *sq10; // [15:19] 10th conversion in regular sequence + Object *sq11; // [20:24] 11th conversion in regular sequence + Object *sq12; // [25:29] 12th conversion in regular sequence + } sqr2; + + // SQR3 (Regular sequence register 3) bitfields. + struct { + Object *sq1; // [0:4] 1st conversion in regular sequence + Object *sq2; // [5:9] 2nd conversion in regular sequence + Object *sq3; // [10:14] 3rd conversion in regular sequence + Object *sq4; // [15:19] 4th conversion in regular sequence + Object *sq5; // [20:24] 5th conversion in regular sequence + Object *sq6; // [25:29] 6th conversion in regular sequence + } sqr3; + + // JSQR (Injected sequence register) bitfields. + struct { + Object *jsq1; // [0:4] 1st conversion in injected sequence + Object *jsq2; // [5:9] 2nd conversion in injected sequence + Object *jsq3; // [10:14] 3rd conversion in injected sequence + Object *jsq4; // [15:19] 4th conversion in injected sequence + Object *jl; // [20:21] Injected sequence length + } jsqr; + + // JDR1 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr1; + + // JDR2 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr2; + + // JDR3 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr3; + + // JDR4 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr4; + + // DR (Regular data register) bitfields. + struct { + Object *data; // [0:15] Regular data + Object *adc2data; // [16:31] ADC2 data + } dr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/adc2.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc2.c new file mode 100644 index 0000000000..43aff8b0ab --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc2.c @@ -0,0 +1,380 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smpr1 = cm_object_get_child_by_name(obj, "SMPR1"); + state->u.f1.reg.smpr2 = cm_object_get_child_by_name(obj, "SMPR2"); + state->u.f1.reg.jofr1 = cm_object_get_child_by_name(obj, "JOFR1"); + state->u.f1.reg.jofr2 = cm_object_get_child_by_name(obj, "JOFR2"); + state->u.f1.reg.jofr3 = cm_object_get_child_by_name(obj, "JOFR3"); + state->u.f1.reg.jofr4 = cm_object_get_child_by_name(obj, "JOFR4"); + state->u.f1.reg.htr = cm_object_get_child_by_name(obj, "HTR"); + state->u.f1.reg.ltr = cm_object_get_child_by_name(obj, "LTR"); + state->u.f1.reg.sqr1 = cm_object_get_child_by_name(obj, "SQR1"); + state->u.f1.reg.sqr2 = cm_object_get_child_by_name(obj, "SQR2"); + state->u.f1.reg.sqr3 = cm_object_get_child_by_name(obj, "SQR3"); + state->u.f1.reg.jsqr = cm_object_get_child_by_name(obj, "JSQR"); + state->u.f1.reg.jdr1 = cm_object_get_child_by_name(obj, "JDR1"); + state->u.f1.reg.jdr2 = cm_object_get_child_by_name(obj, "JDR2"); + state->u.f1.reg.jdr3 = cm_object_get_child_by_name(obj, "JDR3"); + state->u.f1.reg.jdr4 = cm_object_get_child_by_name(obj, "JDR4"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // SR bitfields. + state->u.f1.fld.sr.awd = cm_object_get_child_by_name(state->u.f1.reg.sr, "AWD"); + state->u.f1.fld.sr.eoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "EOC"); + state->u.f1.fld.sr.jeoc = cm_object_get_child_by_name(state->u.f1.reg.sr, "JEOC"); + state->u.f1.fld.sr.jstrt = cm_object_get_child_by_name(state->u.f1.reg.sr, "JSTRT"); + state->u.f1.fld.sr.strt = cm_object_get_child_by_name(state->u.f1.reg.sr, "STRT"); + + // CR1 bitfields. + state->u.f1.fld.cr1.awdch = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDCH"); + state->u.f1.fld.cr1.eocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "EOCIE"); + state->u.f1.fld.cr1.awdie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDIE"); + state->u.f1.fld.cr1.jeocie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JEOCIE"); + state->u.f1.fld.cr1.scan = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SCAN"); + state->u.f1.fld.cr1.awdsgl = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDSGL"); + state->u.f1.fld.cr1.jauto = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAUTO"); + state->u.f1.fld.cr1.discen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCEN"); + state->u.f1.fld.cr1.jdiscen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JDISCEN"); + state->u.f1.fld.cr1.discnum = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DISCNUM"); + state->u.f1.fld.cr1.jawden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "JAWDEN"); + state->u.f1.fld.cr1.awden = cm_object_get_child_by_name(state->u.f1.reg.cr1, "AWDEN"); + + // CR2 bitfields. + state->u.f1.fld.cr2.adon = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADON"); + state->u.f1.fld.cr2.cont = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CONT"); + state->u.f1.fld.cr2.cal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CAL"); + state->u.f1.fld.cr2.rstcal = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RSTCAL"); + state->u.f1.fld.cr2.dma = cm_object_get_child_by_name(state->u.f1.reg.cr2, "DMA"); + state->u.f1.fld.cr2.align = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ALIGN"); + state->u.f1.fld.cr2.jextsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTSEL"); + state->u.f1.fld.cr2.jexttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JEXTTRIG"); + state->u.f1.fld.cr2.extsel = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTSEL"); + state->u.f1.fld.cr2.exttrig = cm_object_get_child_by_name(state->u.f1.reg.cr2, "EXTTRIG"); + state->u.f1.fld.cr2.jswstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "JSWSTART"); + state->u.f1.fld.cr2.swstart = cm_object_get_child_by_name(state->u.f1.reg.cr2, "SWSTART"); + state->u.f1.fld.cr2.tsvrefe = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TSVREFE"); + + // SMPR1 bitfields. + state->u.f1.fld.smpr1.smp10 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP10"); + state->u.f1.fld.smpr1.smp11 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP11"); + state->u.f1.fld.smpr1.smp12 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP12"); + state->u.f1.fld.smpr1.smp13 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP13"); + state->u.f1.fld.smpr1.smp14 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP14"); + state->u.f1.fld.smpr1.smp15 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP15"); + state->u.f1.fld.smpr1.smp16 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP16"); + state->u.f1.fld.smpr1.smp17 = cm_object_get_child_by_name(state->u.f1.reg.smpr1, "SMP17"); + + // SMPR2 bitfields. + state->u.f1.fld.smpr2.smp0 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP0"); + state->u.f1.fld.smpr2.smp1 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP1"); + state->u.f1.fld.smpr2.smp2 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP2"); + state->u.f1.fld.smpr2.smp3 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP3"); + state->u.f1.fld.smpr2.smp4 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP4"); + state->u.f1.fld.smpr2.smp5 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP5"); + state->u.f1.fld.smpr2.smp6 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP6"); + state->u.f1.fld.smpr2.smp7 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP7"); + state->u.f1.fld.smpr2.smp8 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP8"); + state->u.f1.fld.smpr2.smp9 = cm_object_get_child_by_name(state->u.f1.reg.smpr2, "SMP9"); + + // JOFR1 bitfields. + state->u.f1.fld.jofr1.joffset1 = cm_object_get_child_by_name(state->u.f1.reg.jofr1, "JOFFSET1"); + + // JOFR2 bitfields. + state->u.f1.fld.jofr2.joffset2 = cm_object_get_child_by_name(state->u.f1.reg.jofr2, "JOFFSET2"); + + // JOFR3 bitfields. + state->u.f1.fld.jofr3.joffset3 = cm_object_get_child_by_name(state->u.f1.reg.jofr3, "JOFFSET3"); + + // JOFR4 bitfields. + state->u.f1.fld.jofr4.joffset4 = cm_object_get_child_by_name(state->u.f1.reg.jofr4, "JOFFSET4"); + + // HTR bitfields. + state->u.f1.fld.htr.ht = cm_object_get_child_by_name(state->u.f1.reg.htr, "HT"); + + // LTR bitfields. + state->u.f1.fld.ltr.lt = cm_object_get_child_by_name(state->u.f1.reg.ltr, "LT"); + + // SQR1 bitfields. + state->u.f1.fld.sqr1.sq13 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ13"); + state->u.f1.fld.sqr1.sq14 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ14"); + state->u.f1.fld.sqr1.sq15 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ15"); + state->u.f1.fld.sqr1.sq16 = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "SQ16"); + state->u.f1.fld.sqr1.l = cm_object_get_child_by_name(state->u.f1.reg.sqr1, "L"); + + // SQR2 bitfields. + state->u.f1.fld.sqr2.sq7 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ7"); + state->u.f1.fld.sqr2.sq8 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ8"); + state->u.f1.fld.sqr2.sq9 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ9"); + state->u.f1.fld.sqr2.sq10 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ10"); + state->u.f1.fld.sqr2.sq11 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ11"); + state->u.f1.fld.sqr2.sq12 = cm_object_get_child_by_name(state->u.f1.reg.sqr2, "SQ12"); + + // SQR3 bitfields. + state->u.f1.fld.sqr3.sq1 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ1"); + state->u.f1.fld.sqr3.sq2 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ2"); + state->u.f1.fld.sqr3.sq3 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ3"); + state->u.f1.fld.sqr3.sq4 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ4"); + state->u.f1.fld.sqr3.sq5 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ5"); + state->u.f1.fld.sqr3.sq6 = cm_object_get_child_by_name(state->u.f1.reg.sqr3, "SQ6"); + + // JSQR bitfields. + state->u.f1.fld.jsqr.jsq1 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ1"); + state->u.f1.fld.jsqr.jsq2 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ2"); + state->u.f1.fld.jsqr.jsq3 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ3"); + state->u.f1.fld.jsqr.jsq4 = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JSQ4"); + state->u.f1.fld.jsqr.jl = cm_object_get_child_by_name(state->u.f1.reg.jsqr, "JL"); + + // JDR1 bitfields. + state->u.f1.fld.jdr1.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr1, "JDATA"); + + // JDR2 bitfields. + state->u.f1.fld.jdr2.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr2, "JDATA"); + + // JDR3 bitfields. + state->u.f1.fld.jdr3.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr3, "JDATA"); + + // JDR4 bitfields. + state->u.f1.fld.jdr4.jdata = cm_object_get_child_by_name(state->u.f1.reg.jdr4, "JDATA"); + + // DR bitfields. + state->u.f1.fld.dr.data = cm_object_get_child_by_name(state->u.f1.reg.dr, "DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_ADC_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC%dEN", + 1 + state->port_index - STM32_PORT_ADC1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/adc2.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc2.h new file mode 100644 index 0000000000..90be878b4a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/adc2.h @@ -0,0 +1,291 @@ +/* + * STM32 - ADC (Analog to digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_ADC1, + STM32_PORT_ADC2, + STM32_PORT_ADC_UNDEFINED = 0xFF, +} stm32_adc_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_adc_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ADC (Analog to digital converter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *cr1; // 0x4 (Control register 1) + Object *cr2; // 0x8 (Control register 2) + Object *smpr1; // 0xC (Sample time register 1) + Object *smpr2; // 0x10 (Sample time register 2) + Object *jofr1; // 0x14 (Injected channel data offset register x) + Object *jofr2; // 0x18 (Injected channel data offset register x) + Object *jofr3; // 0x1C (Injected channel data offset register x) + Object *jofr4; // 0x20 (Injected channel data offset register x) + Object *htr; // 0x24 (Watchdog higher threshold register) + Object *ltr; // 0x28 (Watchdog lower threshold register) + Object *sqr1; // 0x2C (Regular sequence register 1) + Object *sqr2; // 0x30 (Regular sequence register 2) + Object *sqr3; // 0x34 (Regular sequence register 3) + Object *jsqr; // 0x38 (Injected sequence register) + Object *jdr1; // 0x3C (Injected data register x) + Object *jdr2; // 0x40 (Injected data register x) + Object *jdr3; // 0x44 (Injected data register x) + Object *jdr4; // 0x48 (Injected data register x) + Object *dr; // 0x4C (Regular data register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *awd; // [0:0] Analog watchdog flag + Object *eoc; // [1:1] Regular channel end of conversion + Object *jeoc; // [2:2] Injected channel end of conversion + Object *jstrt; // [3:3] Injected channel start flag + Object *strt; // [4:4] Regular channel start flag + } sr; + + // CR1 (Control register 1) bitfields. + struct { + Object *awdch; // [0:4] Analog watchdog channel select bits + Object *eocie; // [5:5] Interrupt enable for EOC + Object *awdie; // [6:6] Analog watchdog interrupt enable + Object *jeocie; // [7:7] Interrupt enable for injected channels + Object *scan; // [8:8] Scan mode + Object *awdsgl; // [9:9] Enable the watchdog on a single channel in scan mode + Object *jauto; // [10:10] Automatic injected group conversion + Object *discen; // [11:11] Discontinuous mode on regular channels + Object *jdiscen; // [12:12] Discontinuous mode on injected channels + Object *discnum; // [13:15] Discontinuous mode channel count + Object *jawden; // [22:22] Analog watchdog enable on injected channels + Object *awden; // [23:23] Analog watchdog enable on regular channels + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *adon; // [0:0] A/D converter ON / OFF + Object *cont; // [1:1] Continuous conversion + Object *cal; // [2:2] A/D calibration + Object *rstcal; // [3:3] Reset calibration + Object *dma; // [8:8] Direct memory access mode + Object *align; // [11:11] Data alignment + Object *jextsel; // [12:14] External event select for injected group + Object *jexttrig; // [15:15] External trigger conversion mode for injected channels + Object *extsel; // [17:19] External event select for regular group + Object *exttrig; // [20:20] External trigger conversion mode for regular channels + Object *jswstart; // [21:21] Start conversion of injected channels + Object *swstart; // [22:22] Start conversion of regular channels + Object *tsvrefe; // [23:23] Temperature sensor and VREFINT enable + } cr2; + + // SMPR1 (Sample time register 1) bitfields. + struct { + Object *smp10; // [0:2] Channel 10 sampling time selection + Object *smp11; // [3:5] Channel 11 sampling time selection + Object *smp12; // [6:8] Channel 12 sampling time selection + Object *smp13; // [9:11] Channel 13 sampling time selection + Object *smp14; // [12:14] Channel 14 sampling time selection + Object *smp15; // [15:17] Channel 15 sampling time selection + Object *smp16; // [18:20] Channel 16 sampling time selection + Object *smp17; // [21:23] Channel 17 sampling time selection + } smpr1; + + // SMPR2 (Sample time register 2) bitfields. + struct { + Object *smp0; // [0:2] Channel 0 sampling time selection + Object *smp1; // [3:5] Channel 1 sampling time selection + Object *smp2; // [6:8] Channel 2 sampling time selection + Object *smp3; // [9:11] Channel 3 sampling time selection + Object *smp4; // [12:14] Channel 4 sampling time selection + Object *smp5; // [15:17] Channel 5 sampling time selection + Object *smp6; // [18:20] Channel 6 sampling time selection + Object *smp7; // [21:23] Channel 7 sampling time selection + Object *smp8; // [24:26] Channel 8 sampling time selection + Object *smp9; // [27:29] Channel 9 sampling time selection + } smpr2; + + // JOFR1 (Injected channel data offset register x) bitfields. + struct { + Object *joffset1; // [0:11] Data offset for injected channel x + } jofr1; + + // JOFR2 (Injected channel data offset register x) bitfields. + struct { + Object *joffset2; // [0:11] Data offset for injected channel x + } jofr2; + + // JOFR3 (Injected channel data offset register x) bitfields. + struct { + Object *joffset3; // [0:11] Data offset for injected channel x + } jofr3; + + // JOFR4 (Injected channel data offset register x) bitfields. + struct { + Object *joffset4; // [0:11] Data offset for injected channel x + } jofr4; + + // HTR (Watchdog higher threshold register) bitfields. + struct { + Object *ht; // [0:11] Analog watchdog higher threshold + } htr; + + // LTR (Watchdog lower threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + } ltr; + + // SQR1 (Regular sequence register 1) bitfields. + struct { + Object *sq13; // [0:4] 13th conversion in regular sequence + Object *sq14; // [5:9] 14th conversion in regular sequence + Object *sq15; // [10:14] 15th conversion in regular sequence + Object *sq16; // [15:19] 16th conversion in regular sequence + Object *l; // [20:23] Regular channel sequence length + } sqr1; + + // SQR2 (Regular sequence register 2) bitfields. + struct { + Object *sq7; // [0:4] 7th conversion in regular sequence + Object *sq8; // [5:9] 8th conversion in regular sequence + Object *sq9; // [10:14] 9th conversion in regular sequence + Object *sq10; // [15:19] 10th conversion in regular sequence + Object *sq11; // [20:24] 11th conversion in regular sequence + Object *sq12; // [25:29] 12th conversion in regular sequence + } sqr2; + + // SQR3 (Regular sequence register 3) bitfields. + struct { + Object *sq1; // [0:4] 1st conversion in regular sequence + Object *sq2; // [5:9] 2nd conversion in regular sequence + Object *sq3; // [10:14] 3rd conversion in regular sequence + Object *sq4; // [15:19] 4th conversion in regular sequence + Object *sq5; // [20:24] 5th conversion in regular sequence + Object *sq6; // [25:29] 6th conversion in regular sequence + } sqr3; + + // JSQR (Injected sequence register) bitfields. + struct { + Object *jsq1; // [0:4] 1st conversion in injected sequence + Object *jsq2; // [5:9] 2nd conversion in injected sequence + Object *jsq3; // [10:14] 3rd conversion in injected sequence + Object *jsq4; // [15:19] 4th conversion in injected sequence + Object *jl; // [20:21] Injected sequence length + } jsqr; + + // JDR1 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr1; + + // JDR2 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr2; + + // JDR3 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr3; + + // JDR4 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr4; + + // DR (Regular data register) bitfields. + struct { + Object *data; // [0:15] Regular data + } dr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/afio.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/afio.c new file mode 100644 index 0000000000..06313bc659 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/afio.c @@ -0,0 +1,299 @@ +/* + * STM32 - AFIO (Alternate function I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_afio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32AFIOState *state = STM32_AFIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.evcr = cm_object_get_child_by_name(obj, "EVCR"); + state->u.f1.reg.mapr = cm_object_get_child_by_name(obj, "MAPR"); + state->u.f1.reg.exticr1 = cm_object_get_child_by_name(obj, "EXTICR1"); + state->u.f1.reg.exticr2 = cm_object_get_child_by_name(obj, "EXTICR2"); + state->u.f1.reg.exticr3 = cm_object_get_child_by_name(obj, "EXTICR3"); + state->u.f1.reg.exticr4 = cm_object_get_child_by_name(obj, "EXTICR4"); + state->u.f1.reg.mapr2 = cm_object_get_child_by_name(obj, "MAPR2"); + + + // EVCR bitfields. + state->u.f1.fld.evcr.pin = cm_object_get_child_by_name(state->u.f1.reg.evcr, "PIN"); + state->u.f1.fld.evcr.port = cm_object_get_child_by_name(state->u.f1.reg.evcr, "PORT"); + state->u.f1.fld.evcr.evoe = cm_object_get_child_by_name(state->u.f1.reg.evcr, "EVOE"); + + // MAPR bitfields. + state->u.f1.fld.mapr.spi1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "SPI1_REMAP"); + state->u.f1.fld.mapr.i2c1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "I2C1_REMAP"); + state->u.f1.fld.mapr.usart1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "USART1_REMAP"); + state->u.f1.fld.mapr.usart2_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "USART2_REMAP"); + state->u.f1.fld.mapr.usart3_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "USART3_REMAP"); + state->u.f1.fld.mapr.tim1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM1_REMAP"); + state->u.f1.fld.mapr.tim2_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM2_REMAP"); + state->u.f1.fld.mapr.tim3_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM3_REMAP"); + state->u.f1.fld.mapr.tim4_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM4_REMAP"); + state->u.f1.fld.mapr.can1_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "CAN1_REMAP"); + state->u.f1.fld.mapr.pd01_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "PD01_REMAP"); + state->u.f1.fld.mapr.tim5ch4_iremap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM5CH4_IREMAP"); + state->u.f1.fld.mapr.eth_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "ETH_REMAP"); + state->u.f1.fld.mapr.can2_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "CAN2_REMAP"); + state->u.f1.fld.mapr.mii_rmii_sel = cm_object_get_child_by_name(state->u.f1.reg.mapr, "MII_RMII_SEL"); + state->u.f1.fld.mapr.swj_cfg = cm_object_get_child_by_name(state->u.f1.reg.mapr, "SWJ_CFG"); + state->u.f1.fld.mapr.spi3_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "SPI3_REMAP"); + state->u.f1.fld.mapr.tim2itr1_iremap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "TIM2ITR1_IREMAP"); + state->u.f1.fld.mapr.ptp_pps_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr, "PTP_PPS_REMAP"); + + // EXTICR1 bitfields. + state->u.f1.fld.exticr1.exti0 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI0"); + state->u.f1.fld.exticr1.exti1 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI1"); + state->u.f1.fld.exticr1.exti2 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI2"); + state->u.f1.fld.exticr1.exti3 = cm_object_get_child_by_name(state->u.f1.reg.exticr1, "EXTI3"); + + // EXTICR2 bitfields. + state->u.f1.fld.exticr2.exti4 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI4"); + state->u.f1.fld.exticr2.exti5 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI5"); + state->u.f1.fld.exticr2.exti6 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI6"); + state->u.f1.fld.exticr2.exti7 = cm_object_get_child_by_name(state->u.f1.reg.exticr2, "EXTI7"); + + // EXTICR3 bitfields. + state->u.f1.fld.exticr3.exti8 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI8"); + state->u.f1.fld.exticr3.exti9 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI9"); + state->u.f1.fld.exticr3.exti10 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI10"); + state->u.f1.fld.exticr3.exti11 = cm_object_get_child_by_name(state->u.f1.reg.exticr3, "EXTI11"); + + // EXTICR4 bitfields. + state->u.f1.fld.exticr4.exti12 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI12"); + state->u.f1.fld.exticr4.exti13 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI13"); + state->u.f1.fld.exticr4.exti14 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI14"); + state->u.f1.fld.exticr4.exti15 = cm_object_get_child_by_name(state->u.f1.reg.exticr4, "EXTI15"); + + // MAPR2 bitfields. + state->u.f1.fld.mapr2.tim9_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM9_REMAP"); + state->u.f1.fld.mapr2.tim10_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM10_REMAP"); + state->u.f1.fld.mapr2.tim11_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM11_REMAP"); + state->u.f1.fld.mapr2.tim13_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM13_REMAP"); + state->u.f1.fld.mapr2.tim14_remap = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "TIM14_REMAP"); + state->u.f1.fld.mapr2.fsmc_nadv = cm_object_get_child_by_name(state->u.f1.reg.mapr2, "FSMC_NADV"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_afio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_afio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_afio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_afio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32AFIOState *state = STM32_AFIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_afio_is_enabled(Object *obj) +{ + STM32AFIOState *state = STM32_AFIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_afio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32AFIOState *state = STM32_AFIO_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_afio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_AFIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32AFIOState *state = STM32_AFIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "AFIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_afio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_afio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_afio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_afio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_afio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/AFIOEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_afio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_AFIO); +} + +static void stm32_afio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_afio_reset_callback; + dc->realize = stm32_afio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_afio_is_enabled; +} + +static const TypeInfo stm32_afio_type_info = { + .name = TYPE_STM32_AFIO, + .parent = TYPE_STM32_AFIO_PARENT, + .instance_init = stm32_afio_instance_init_callback, + .instance_size = sizeof(STM32AFIOState), + .class_init = stm32_afio_class_init_callback, + .class_size = sizeof(STM32AFIOClass) }; + +static void stm32_afio_register_types(void) +{ + type_register_static(&stm32_afio_type_info); +} + +type_init(stm32_afio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/afio.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/afio.h new file mode 100644 index 0000000000..a8d03a921f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/afio.h @@ -0,0 +1,178 @@ +/* + * STM32 - AFIO (Alternate function I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_AFIO_H_ +#define STM32_AFIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_AFIO DEVICE_PATH_STM32 "AFIO" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_AFIO TYPE_STM32_PREFIX "afio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_AFIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32AFIOParentClass; +typedef PeripheralState STM32AFIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_AFIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32AFIOClass, (obj), TYPE_STM32_AFIO) +#define STM32_AFIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32AFIOClass, (klass), TYPE_STM32_AFIO) + +typedef struct { + // private: + STM32AFIOParentClass parent_class; + // public: + + // None, so far. +} STM32AFIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_AFIO_STATE(obj) \ + OBJECT_CHECK(STM32AFIOState, (obj), TYPE_STM32_AFIO) + +typedef struct { + // private: + STM32AFIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 AFIO (Alternate function I/O) registers. + struct { + Object *evcr; // 0x0 (Event Control Register (AFIO_EVCR)) + Object *mapr; // 0x4 (AF remap and debug I/O configuration register (AFIO_MAPR)) + Object *exticr1; // 0x8 (External interrupt configuration register 1 (AFIO_EXTICR1)) + Object *exticr2; // 0xC (External interrupt configuration register 2 (AFIO_EXTICR2)) + Object *exticr3; // 0x10 (External interrupt configuration register 3 (AFIO_EXTICR3)) + Object *exticr4; // 0x14 (External interrupt configuration register 4 (AFIO_EXTICR4)) + Object *mapr2; // 0x1C (AF remap and debug I/O configuration register) + } reg; + + struct { + + // EVCR (Event Control Register (AFIO_EVCR)) bitfields. + struct { + Object *pin; // [0:3] Pin selection + Object *port; // [4:6] Port selection + Object *evoe; // [7:7] Event Output Enable + } evcr; + + // MAPR (AF remap and debug I/O configuration register (AFIO_MAPR)) bitfields. + struct { + Object *spi1_remap; // [0:0] SPI1 remapping + Object *i2c1_remap; // [1:1] I2C1 remapping + Object *usart1_remap; // [2:2] USART1 remapping + Object *usart2_remap; // [3:3] USART2 remapping + Object *usart3_remap; // [4:5] USART3 remapping + Object *tim1_remap; // [6:7] TIM1 remapping + Object *tim2_remap; // [8:9] TIM2 remapping + Object *tim3_remap; // [10:11] TIM3 remapping + Object *tim4_remap; // [12:12] TIM4 remapping + Object *can1_remap; // [13:14] CAN1 remapping + Object *pd01_remap; // [15:15] Port D0/Port D1 mapping on OSCIN/OSCOUT + Object *tim5ch4_iremap; // [16:16] Set and cleared by software + Object *eth_remap; // [21:21] Ethernet MAC I/O remapping + Object *can2_remap; // [22:22] CAN2 I/O remapping + Object *mii_rmii_sel; // [23:23] MII or RMII selection + Object *swj_cfg; // [24:26] Serial wire JTAG configuration + Object *spi3_remap; // [28:28] SPI3/I2S3 remapping + Object *tim2itr1_iremap; // [29:29] TIM2 internal trigger 1 remapping + Object *ptp_pps_remap; // [30:30] Ethernet PTP PPS remapping + } mapr; + + // EXTICR1 (External interrupt configuration register 1 (AFIO_EXTICR1)) bitfields. + struct { + Object *exti0; // [0:3] EXTI0 configuration + Object *exti1; // [4:7] EXTI1 configuration + Object *exti2; // [8:11] EXTI2 configuration + Object *exti3; // [12:15] EXTI3 configuration + } exticr1; + + // EXTICR2 (External interrupt configuration register 2 (AFIO_EXTICR2)) bitfields. + struct { + Object *exti4; // [0:3] EXTI4 configuration + Object *exti5; // [4:7] EXTI5 configuration + Object *exti6; // [8:11] EXTI6 configuration + Object *exti7; // [12:15] EXTI7 configuration + } exticr2; + + // EXTICR3 (External interrupt configuration register 3 (AFIO_EXTICR3)) bitfields. + struct { + Object *exti8; // [0:3] EXTI8 configuration + Object *exti9; // [4:7] EXTI9 configuration + Object *exti10; // [8:11] EXTI10 configuration + Object *exti11; // [12:15] EXTI11 configuration + } exticr3; + + // EXTICR4 (External interrupt configuration register 4 (AFIO_EXTICR4)) bitfields. + struct { + Object *exti12; // [0:3] EXTI12 configuration + Object *exti13; // [4:7] EXTI13 configuration + Object *exti14; // [8:11] EXTI14 configuration + Object *exti15; // [12:15] EXTI15 configuration + } exticr4; + + // MAPR2 (AF remap and debug I/O configuration register) bitfields. + struct { + Object *tim9_remap; // [5:5] TIM9 remapping + Object *tim10_remap; // [6:6] TIM10 remapping + Object *tim11_remap; // [7:7] TIM11 remapping + Object *tim13_remap; // [8:8] TIM13 remapping + Object *tim14_remap; // [9:9] TIM14 remapping + Object *fsmc_nadv; // [10:10] NADV connect/disconnect + } mapr2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32AFIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_AFIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/bkp.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/bkp.c new file mode 100644 index 0000000000..0b2b0edf49 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/bkp.c @@ -0,0 +1,422 @@ +/* + * STM32 - BKP (Backup registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_bkp_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32BKPState *state = STM32_BKP_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.dr1 = cm_object_get_child_by_name(obj, "DR1"); + state->u.f1.reg.dr2 = cm_object_get_child_by_name(obj, "DR2"); + state->u.f1.reg.dr3 = cm_object_get_child_by_name(obj, "DR3"); + state->u.f1.reg.dr4 = cm_object_get_child_by_name(obj, "DR4"); + state->u.f1.reg.dr5 = cm_object_get_child_by_name(obj, "DR5"); + state->u.f1.reg.dr6 = cm_object_get_child_by_name(obj, "DR6"); + state->u.f1.reg.dr7 = cm_object_get_child_by_name(obj, "DR7"); + state->u.f1.reg.dr8 = cm_object_get_child_by_name(obj, "DR8"); + state->u.f1.reg.dr9 = cm_object_get_child_by_name(obj, "DR9"); + state->u.f1.reg.dr10 = cm_object_get_child_by_name(obj, "DR10"); + state->u.f1.reg.dr11 = cm_object_get_child_by_name(obj, "DR11"); + state->u.f1.reg.dr12 = cm_object_get_child_by_name(obj, "DR12"); + state->u.f1.reg.dr13 = cm_object_get_child_by_name(obj, "DR13"); + state->u.f1.reg.dr14 = cm_object_get_child_by_name(obj, "DR14"); + state->u.f1.reg.dr15 = cm_object_get_child_by_name(obj, "DR15"); + state->u.f1.reg.dr16 = cm_object_get_child_by_name(obj, "DR16"); + state->u.f1.reg.dr17 = cm_object_get_child_by_name(obj, "DR17"); + state->u.f1.reg.dr18 = cm_object_get_child_by_name(obj, "DR18"); + state->u.f1.reg.dr19 = cm_object_get_child_by_name(obj, "DR19"); + state->u.f1.reg.dr20 = cm_object_get_child_by_name(obj, "DR20"); + state->u.f1.reg.dr21 = cm_object_get_child_by_name(obj, "DR21"); + state->u.f1.reg.dr22 = cm_object_get_child_by_name(obj, "DR22"); + state->u.f1.reg.dr23 = cm_object_get_child_by_name(obj, "DR23"); + state->u.f1.reg.dr24 = cm_object_get_child_by_name(obj, "DR24"); + state->u.f1.reg.dr25 = cm_object_get_child_by_name(obj, "DR25"); + state->u.f1.reg.dr26 = cm_object_get_child_by_name(obj, "DR26"); + state->u.f1.reg.dr27 = cm_object_get_child_by_name(obj, "DR27"); + state->u.f1.reg.dr28 = cm_object_get_child_by_name(obj, "DR28"); + state->u.f1.reg.dr29 = cm_object_get_child_by_name(obj, "DR29"); + state->u.f1.reg.dr30 = cm_object_get_child_by_name(obj, "DR30"); + state->u.f1.reg.dr31 = cm_object_get_child_by_name(obj, "DR31"); + state->u.f1.reg.dr32 = cm_object_get_child_by_name(obj, "DR32"); + state->u.f1.reg.dr33 = cm_object_get_child_by_name(obj, "DR33"); + state->u.f1.reg.dr34 = cm_object_get_child_by_name(obj, "DR34"); + state->u.f1.reg.dr35 = cm_object_get_child_by_name(obj, "DR35"); + state->u.f1.reg.dr36 = cm_object_get_child_by_name(obj, "DR36"); + state->u.f1.reg.dr37 = cm_object_get_child_by_name(obj, "DR37"); + state->u.f1.reg.dr38 = cm_object_get_child_by_name(obj, "DR38"); + state->u.f1.reg.dr39 = cm_object_get_child_by_name(obj, "DR39"); + state->u.f1.reg.dr40 = cm_object_get_child_by_name(obj, "DR40"); + state->u.f1.reg.dr41 = cm_object_get_child_by_name(obj, "DR41"); + state->u.f1.reg.dr42 = cm_object_get_child_by_name(obj, "DR42"); + state->u.f1.reg.rtccr = cm_object_get_child_by_name(obj, "RTCCR"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // DR1 bitfields. + state->u.f1.fld.dr1.d1 = cm_object_get_child_by_name(state->u.f1.reg.dr1, "D1"); + + // DR2 bitfields. + state->u.f1.fld.dr2.d2 = cm_object_get_child_by_name(state->u.f1.reg.dr2, "D2"); + + // DR3 bitfields. + state->u.f1.fld.dr3.d3 = cm_object_get_child_by_name(state->u.f1.reg.dr3, "D3"); + + // DR4 bitfields. + state->u.f1.fld.dr4.d4 = cm_object_get_child_by_name(state->u.f1.reg.dr4, "D4"); + + // DR5 bitfields. + state->u.f1.fld.dr5.d5 = cm_object_get_child_by_name(state->u.f1.reg.dr5, "D5"); + + // DR6 bitfields. + state->u.f1.fld.dr6.d6 = cm_object_get_child_by_name(state->u.f1.reg.dr6, "D6"); + + // DR7 bitfields. + state->u.f1.fld.dr7.d7 = cm_object_get_child_by_name(state->u.f1.reg.dr7, "D7"); + + // DR8 bitfields. + state->u.f1.fld.dr8.d8 = cm_object_get_child_by_name(state->u.f1.reg.dr8, "D8"); + + // DR9 bitfields. + state->u.f1.fld.dr9.d9 = cm_object_get_child_by_name(state->u.f1.reg.dr9, "D9"); + + // DR10 bitfields. + state->u.f1.fld.dr10.d10 = cm_object_get_child_by_name(state->u.f1.reg.dr10, "D10"); + + // DR11 bitfields. + state->u.f1.fld.dr11.dr11 = cm_object_get_child_by_name(state->u.f1.reg.dr11, "DR11"); + + // DR12 bitfields. + state->u.f1.fld.dr12.dr12 = cm_object_get_child_by_name(state->u.f1.reg.dr12, "DR12"); + + // DR13 bitfields. + state->u.f1.fld.dr13.dr13 = cm_object_get_child_by_name(state->u.f1.reg.dr13, "DR13"); + + // DR14 bitfields. + state->u.f1.fld.dr14.d14 = cm_object_get_child_by_name(state->u.f1.reg.dr14, "D14"); + + // DR15 bitfields. + state->u.f1.fld.dr15.d15 = cm_object_get_child_by_name(state->u.f1.reg.dr15, "D15"); + + // DR16 bitfields. + state->u.f1.fld.dr16.d16 = cm_object_get_child_by_name(state->u.f1.reg.dr16, "D16"); + + // DR17 bitfields. + state->u.f1.fld.dr17.d17 = cm_object_get_child_by_name(state->u.f1.reg.dr17, "D17"); + + // DR18 bitfields. + state->u.f1.fld.dr18.d18 = cm_object_get_child_by_name(state->u.f1.reg.dr18, "D18"); + + // DR19 bitfields. + state->u.f1.fld.dr19.d19 = cm_object_get_child_by_name(state->u.f1.reg.dr19, "D19"); + + // DR20 bitfields. + state->u.f1.fld.dr20.d20 = cm_object_get_child_by_name(state->u.f1.reg.dr20, "D20"); + + // DR21 bitfields. + state->u.f1.fld.dr21.d21 = cm_object_get_child_by_name(state->u.f1.reg.dr21, "D21"); + + // DR22 bitfields. + state->u.f1.fld.dr22.d22 = cm_object_get_child_by_name(state->u.f1.reg.dr22, "D22"); + + // DR23 bitfields. + state->u.f1.fld.dr23.d23 = cm_object_get_child_by_name(state->u.f1.reg.dr23, "D23"); + + // DR24 bitfields. + state->u.f1.fld.dr24.d24 = cm_object_get_child_by_name(state->u.f1.reg.dr24, "D24"); + + // DR25 bitfields. + state->u.f1.fld.dr25.d25 = cm_object_get_child_by_name(state->u.f1.reg.dr25, "D25"); + + // DR26 bitfields. + state->u.f1.fld.dr26.d26 = cm_object_get_child_by_name(state->u.f1.reg.dr26, "D26"); + + // DR27 bitfields. + state->u.f1.fld.dr27.d27 = cm_object_get_child_by_name(state->u.f1.reg.dr27, "D27"); + + // DR28 bitfields. + state->u.f1.fld.dr28.d28 = cm_object_get_child_by_name(state->u.f1.reg.dr28, "D28"); + + // DR29 bitfields. + state->u.f1.fld.dr29.d29 = cm_object_get_child_by_name(state->u.f1.reg.dr29, "D29"); + + // DR30 bitfields. + state->u.f1.fld.dr30.d30 = cm_object_get_child_by_name(state->u.f1.reg.dr30, "D30"); + + // DR31 bitfields. + state->u.f1.fld.dr31.d31 = cm_object_get_child_by_name(state->u.f1.reg.dr31, "D31"); + + // DR32 bitfields. + state->u.f1.fld.dr32.d32 = cm_object_get_child_by_name(state->u.f1.reg.dr32, "D32"); + + // DR33 bitfields. + state->u.f1.fld.dr33.d33 = cm_object_get_child_by_name(state->u.f1.reg.dr33, "D33"); + + // DR34 bitfields. + state->u.f1.fld.dr34.d34 = cm_object_get_child_by_name(state->u.f1.reg.dr34, "D34"); + + // DR35 bitfields. + state->u.f1.fld.dr35.d35 = cm_object_get_child_by_name(state->u.f1.reg.dr35, "D35"); + + // DR36 bitfields. + state->u.f1.fld.dr36.d36 = cm_object_get_child_by_name(state->u.f1.reg.dr36, "D36"); + + // DR37 bitfields. + state->u.f1.fld.dr37.d37 = cm_object_get_child_by_name(state->u.f1.reg.dr37, "D37"); + + // DR38 bitfields. + state->u.f1.fld.dr38.d38 = cm_object_get_child_by_name(state->u.f1.reg.dr38, "D38"); + + // DR39 bitfields. + state->u.f1.fld.dr39.d39 = cm_object_get_child_by_name(state->u.f1.reg.dr39, "D39"); + + // DR40 bitfields. + state->u.f1.fld.dr40.d40 = cm_object_get_child_by_name(state->u.f1.reg.dr40, "D40"); + + // DR41 bitfields. + state->u.f1.fld.dr41.d41 = cm_object_get_child_by_name(state->u.f1.reg.dr41, "D41"); + + // DR42 bitfields. + state->u.f1.fld.dr42.d42 = cm_object_get_child_by_name(state->u.f1.reg.dr42, "D42"); + + // RTCCR bitfields. + state->u.f1.fld.rtccr.cal = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "CAL"); + state->u.f1.fld.rtccr.cco = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "CCO"); + state->u.f1.fld.rtccr.asoe = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "ASOE"); + state->u.f1.fld.rtccr.asos = cm_object_get_child_by_name(state->u.f1.reg.rtccr, "ASOS"); + + // CR bitfields. + state->u.f1.fld.cr.tpe = cm_object_get_child_by_name(state->u.f1.reg.cr, "TPE"); + state->u.f1.fld.cr.tpal = cm_object_get_child_by_name(state->u.f1.reg.cr, "TPAL"); + + // CSR bitfields. + state->u.f1.fld.csr.cte = cm_object_get_child_by_name(state->u.f1.reg.csr, "CTE"); + state->u.f1.fld.csr.cti = cm_object_get_child_by_name(state->u.f1.reg.csr, "CTI"); + state->u.f1.fld.csr.tpie = cm_object_get_child_by_name(state->u.f1.reg.csr, "TPIE"); + state->u.f1.fld.csr.tef = cm_object_get_child_by_name(state->u.f1.reg.csr, "TEF"); + state->u.f1.fld.csr.tif = cm_object_get_child_by_name(state->u.f1.reg.csr, "TIF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_bkp_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_bkp_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_bkp_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_bkp_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32BKPState *state = STM32_BKP_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_bkp_is_enabled(Object *obj) +{ + STM32BKPState *state = STM32_BKP_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_bkp_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32BKPState *state = STM32_BKP_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_bkp_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_BKP)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32BKPState *state = STM32_BKP_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "BKP"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_bkp_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_bkp_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_bkp_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_bkp_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_bkp_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/BKPEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_bkp_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_BKP); +} + +static void stm32_bkp_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_bkp_reset_callback; + dc->realize = stm32_bkp_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_bkp_is_enabled; +} + +static const TypeInfo stm32_bkp_type_info = { + .name = TYPE_STM32_BKP, + .parent = TYPE_STM32_BKP_PARENT, + .instance_init = stm32_bkp_instance_init_callback, + .instance_size = sizeof(STM32BKPState), + .class_init = stm32_bkp_class_init_callback, + .class_size = sizeof(STM32BKPClass) }; + +static void stm32_bkp_register_types(void) +{ + type_register_static(&stm32_bkp_type_info); +} + +type_init(stm32_bkp_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/bkp.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/bkp.h new file mode 100644 index 0000000000..d646e19efc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/bkp.h @@ -0,0 +1,377 @@ +/* + * STM32 - BKP (Backup registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_BKP_H_ +#define STM32_BKP_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_BKP DEVICE_PATH_STM32 "BKP" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_BKP TYPE_STM32_PREFIX "bkp" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_BKP_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32BKPParentClass; +typedef PeripheralState STM32BKPParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_BKP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32BKPClass, (obj), TYPE_STM32_BKP) +#define STM32_BKP_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32BKPClass, (klass), TYPE_STM32_BKP) + +typedef struct { + // private: + STM32BKPParentClass parent_class; + // public: + + // None, so far. +} STM32BKPClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_BKP_STATE(obj) \ + OBJECT_CHECK(STM32BKPState, (obj), TYPE_STM32_BKP) + +typedef struct { + // private: + STM32BKPParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 BKP (Backup registers) registers. + struct { + Object *dr1; // 0x0 (Backup data register (BKP_DR)) + Object *dr2; // 0x4 (Backup data register (BKP_DR)) + Object *dr3; // 0x8 (Backup data register (BKP_DR)) + Object *dr4; // 0xC (Backup data register (BKP_DR)) + Object *dr5; // 0x10 (Backup data register (BKP_DR)) + Object *dr6; // 0x14 (Backup data register (BKP_DR)) + Object *dr7; // 0x18 (Backup data register (BKP_DR)) + Object *dr8; // 0x1C (Backup data register (BKP_DR)) + Object *dr9; // 0x20 (Backup data register (BKP_DR)) + Object *dr10; // 0x24 (Backup data register (BKP_DR)) + Object *dr11; // 0x3C (Backup data register (BKP_DR)) + Object *dr12; // 0x40 (Backup data register (BKP_DR)) + Object *dr13; // 0x44 (Backup data register (BKP_DR)) + Object *dr14; // 0x48 (Backup data register (BKP_DR)) + Object *dr15; // 0x4C (Backup data register (BKP_DR)) + Object *dr16; // 0x50 (Backup data register (BKP_DR)) + Object *dr17; // 0x54 (Backup data register (BKP_DR)) + Object *dr18; // 0x58 (Backup data register (BKP_DR)) + Object *dr19; // 0x5C (Backup data register (BKP_DR)) + Object *dr20; // 0x60 (Backup data register (BKP_DR)) + Object *dr21; // 0x64 (Backup data register (BKP_DR)) + Object *dr22; // 0x68 (Backup data register (BKP_DR)) + Object *dr23; // 0x6C (Backup data register (BKP_DR)) + Object *dr24; // 0x70 (Backup data register (BKP_DR)) + Object *dr25; // 0x74 (Backup data register (BKP_DR)) + Object *dr26; // 0x78 (Backup data register (BKP_DR)) + Object *dr27; // 0x7C (Backup data register (BKP_DR)) + Object *dr28; // 0x80 (Backup data register (BKP_DR)) + Object *dr29; // 0x84 (Backup data register (BKP_DR)) + Object *dr30; // 0x88 (Backup data register (BKP_DR)) + Object *dr31; // 0x8C (Backup data register (BKP_DR)) + Object *dr32; // 0x90 (Backup data register (BKP_DR)) + Object *dr33; // 0x94 (Backup data register (BKP_DR)) + Object *dr34; // 0x98 (Backup data register (BKP_DR)) + Object *dr35; // 0x9C (Backup data register (BKP_DR)) + Object *dr36; // 0xA0 (Backup data register (BKP_DR)) + Object *dr37; // 0xA4 (Backup data register (BKP_DR)) + Object *dr38; // 0xA8 (Backup data register (BKP_DR)) + Object *dr39; // 0xAC (Backup data register (BKP_DR)) + Object *dr40; // 0xB0 (Backup data register (BKP_DR)) + Object *dr41; // 0xB4 (Backup data register (BKP_DR)) + Object *dr42; // 0xB8 (Backup data register (BKP_DR)) + Object *rtccr; // 0x28 (RTC clock calibration register (BKP_RTCCR)) + Object *cr; // 0x2C (Backup control register (BKP_CR)) + Object *csr; // 0x30 (BKP_CSR control/status register) + } reg; + + struct { + + // DR1 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d1; // [0:15] Backup data + } dr1; + + // DR2 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d2; // [0:15] Backup data + } dr2; + + // DR3 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d3; // [0:15] Backup data + } dr3; + + // DR4 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d4; // [0:15] Backup data + } dr4; + + // DR5 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d5; // [0:15] Backup data + } dr5; + + // DR6 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d6; // [0:15] Backup data + } dr6; + + // DR7 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d7; // [0:15] Backup data + } dr7; + + // DR8 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d8; // [0:15] Backup data + } dr8; + + // DR9 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d9; // [0:15] Backup data + } dr9; + + // DR10 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d10; // [0:15] Backup data + } dr10; + + // DR11 (Backup data register (BKP_DR)) bitfields. + struct { + Object *dr11; // [0:15] Backup data + } dr11; + + // DR12 (Backup data register (BKP_DR)) bitfields. + struct { + Object *dr12; // [0:15] Backup data + } dr12; + + // DR13 (Backup data register (BKP_DR)) bitfields. + struct { + Object *dr13; // [0:15] Backup data + } dr13; + + // DR14 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d14; // [0:15] Backup data + } dr14; + + // DR15 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d15; // [0:15] Backup data + } dr15; + + // DR16 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d16; // [0:15] Backup data + } dr16; + + // DR17 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d17; // [0:15] Backup data + } dr17; + + // DR18 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d18; // [0:15] Backup data + } dr18; + + // DR19 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d19; // [0:15] Backup data + } dr19; + + // DR20 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d20; // [0:15] Backup data + } dr20; + + // DR21 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d21; // [0:15] Backup data + } dr21; + + // DR22 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d22; // [0:15] Backup data + } dr22; + + // DR23 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d23; // [0:15] Backup data + } dr23; + + // DR24 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d24; // [0:15] Backup data + } dr24; + + // DR25 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d25; // [0:15] Backup data + } dr25; + + // DR26 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d26; // [0:15] Backup data + } dr26; + + // DR27 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d27; // [0:15] Backup data + } dr27; + + // DR28 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d28; // [0:15] Backup data + } dr28; + + // DR29 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d29; // [0:15] Backup data + } dr29; + + // DR30 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d30; // [0:15] Backup data + } dr30; + + // DR31 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d31; // [0:15] Backup data + } dr31; + + // DR32 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d32; // [0:15] Backup data + } dr32; + + // DR33 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d33; // [0:15] Backup data + } dr33; + + // DR34 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d34; // [0:15] Backup data + } dr34; + + // DR35 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d35; // [0:15] Backup data + } dr35; + + // DR36 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d36; // [0:15] Backup data + } dr36; + + // DR37 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d37; // [0:15] Backup data + } dr37; + + // DR38 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d38; // [0:15] Backup data + } dr38; + + // DR39 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d39; // [0:15] Backup data + } dr39; + + // DR40 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d40; // [0:15] Backup data + } dr40; + + // DR41 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d41; // [0:15] Backup data + } dr41; + + // DR42 (Backup data register (BKP_DR)) bitfields. + struct { + Object *d42; // [0:15] Backup data + } dr42; + + // RTCCR (RTC clock calibration register (BKP_RTCCR)) bitfields. + struct { + Object *cal; // [0:6] Calibration value + Object *cco; // [7:7] Calibration Clock Output + Object *asoe; // [8:8] Alarm or second output enable + Object *asos; // [9:9] Alarm or second output selection + } rtccr; + + // CR (Backup control register (BKP_CR)) bitfields. + struct { + Object *tpe; // [0:0] Tamper pin enable + Object *tpal; // [1:1] Tamper pin active level + } cr; + + // CSR (BKP_CSR control/status register) bitfields. + struct { + Object *cte; // [0:0] Clear Tamper event + Object *cti; // [1:1] Clear Tamper Interrupt + Object *tpie; // [2:2] Tamper Pin interrupt enable + Object *tef; // [8:8] Tamper Event Flag + Object *tif; // [9:9] Tamper Interrupt Flag + } csr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32BKPState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_BKP_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/can2.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/can2.c new file mode 100644 index 0000000000..cc223ac3b0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/can2.c @@ -0,0 +1,2560 @@ +/* + * STM32 - CAN2 (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_can2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CAN2State *state = STM32_CAN2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.can_mcr = cm_object_get_child_by_name(obj, "CAN_MCR"); + state->u.f1.reg.can_msr = cm_object_get_child_by_name(obj, "CAN_MSR"); + state->u.f1.reg.can_tsr = cm_object_get_child_by_name(obj, "CAN_TSR"); + state->u.f1.reg.can_rf0r = cm_object_get_child_by_name(obj, "CAN_RF0R"); + state->u.f1.reg.can_rf1r = cm_object_get_child_by_name(obj, "CAN_RF1R"); + state->u.f1.reg.can_ier = cm_object_get_child_by_name(obj, "CAN_IER"); + state->u.f1.reg.can_esr = cm_object_get_child_by_name(obj, "CAN_ESR"); + state->u.f1.reg.can_btr = cm_object_get_child_by_name(obj, "CAN_BTR"); + state->u.f1.reg.can_ti0r = cm_object_get_child_by_name(obj, "CAN_TI0R"); + state->u.f1.reg.can_tdt0r = cm_object_get_child_by_name(obj, "CAN_TDT0R"); + state->u.f1.reg.can_tdl0r = cm_object_get_child_by_name(obj, "CAN_TDL0R"); + state->u.f1.reg.can_tdh0r = cm_object_get_child_by_name(obj, "CAN_TDH0R"); + state->u.f1.reg.can_ti1r = cm_object_get_child_by_name(obj, "CAN_TI1R"); + state->u.f1.reg.can_tdt1r = cm_object_get_child_by_name(obj, "CAN_TDT1R"); + state->u.f1.reg.can_tdl1r = cm_object_get_child_by_name(obj, "CAN_TDL1R"); + state->u.f1.reg.can_tdh1r = cm_object_get_child_by_name(obj, "CAN_TDH1R"); + state->u.f1.reg.can_ti2r = cm_object_get_child_by_name(obj, "CAN_TI2R"); + state->u.f1.reg.can_tdt2r = cm_object_get_child_by_name(obj, "CAN_TDT2R"); + state->u.f1.reg.can_tdl2r = cm_object_get_child_by_name(obj, "CAN_TDL2R"); + state->u.f1.reg.can_tdh2r = cm_object_get_child_by_name(obj, "CAN_TDH2R"); + state->u.f1.reg.can_ri0r = cm_object_get_child_by_name(obj, "CAN_RI0R"); + state->u.f1.reg.can_rdt0r = cm_object_get_child_by_name(obj, "CAN_RDT0R"); + state->u.f1.reg.can_rdl0r = cm_object_get_child_by_name(obj, "CAN_RDL0R"); + state->u.f1.reg.can_rdh0r = cm_object_get_child_by_name(obj, "CAN_RDH0R"); + state->u.f1.reg.can_ri1r = cm_object_get_child_by_name(obj, "CAN_RI1R"); + state->u.f1.reg.can_rdt1r = cm_object_get_child_by_name(obj, "CAN_RDT1R"); + state->u.f1.reg.can_rdl1r = cm_object_get_child_by_name(obj, "CAN_RDL1R"); + state->u.f1.reg.can_rdh1r = cm_object_get_child_by_name(obj, "CAN_RDH1R"); + state->u.f1.reg.can_fmr = cm_object_get_child_by_name(obj, "CAN_FMR"); + state->u.f1.reg.can_fm1r = cm_object_get_child_by_name(obj, "CAN_FM1R"); + state->u.f1.reg.can_fs1r = cm_object_get_child_by_name(obj, "CAN_FS1R"); + state->u.f1.reg.can_ffa1r = cm_object_get_child_by_name(obj, "CAN_FFA1R"); + state->u.f1.reg.can_fa1r = cm_object_get_child_by_name(obj, "CAN_FA1R"); + state->u.f1.reg.f0r1 = cm_object_get_child_by_name(obj, "F0R1"); + state->u.f1.reg.f0r2 = cm_object_get_child_by_name(obj, "F0R2"); + state->u.f1.reg.f1r1 = cm_object_get_child_by_name(obj, "F1R1"); + state->u.f1.reg.f1r2 = cm_object_get_child_by_name(obj, "F1R2"); + state->u.f1.reg.f2r1 = cm_object_get_child_by_name(obj, "F2R1"); + state->u.f1.reg.f2r2 = cm_object_get_child_by_name(obj, "F2R2"); + state->u.f1.reg.f3r1 = cm_object_get_child_by_name(obj, "F3R1"); + state->u.f1.reg.f3r2 = cm_object_get_child_by_name(obj, "F3R2"); + state->u.f1.reg.f4r1 = cm_object_get_child_by_name(obj, "F4R1"); + state->u.f1.reg.f4r2 = cm_object_get_child_by_name(obj, "F4R2"); + state->u.f1.reg.f5r1 = cm_object_get_child_by_name(obj, "F5R1"); + state->u.f1.reg.f5r2 = cm_object_get_child_by_name(obj, "F5R2"); + state->u.f1.reg.f6r1 = cm_object_get_child_by_name(obj, "F6R1"); + state->u.f1.reg.f6r2 = cm_object_get_child_by_name(obj, "F6R2"); + state->u.f1.reg.f7r1 = cm_object_get_child_by_name(obj, "F7R1"); + state->u.f1.reg.f7r2 = cm_object_get_child_by_name(obj, "F7R2"); + state->u.f1.reg.f8r1 = cm_object_get_child_by_name(obj, "F8R1"); + state->u.f1.reg.f8r2 = cm_object_get_child_by_name(obj, "F8R2"); + state->u.f1.reg.f9r1 = cm_object_get_child_by_name(obj, "F9R1"); + state->u.f1.reg.f9r2 = cm_object_get_child_by_name(obj, "F9R2"); + state->u.f1.reg.f10r1 = cm_object_get_child_by_name(obj, "F10R1"); + state->u.f1.reg.f10r2 = cm_object_get_child_by_name(obj, "F10R2"); + state->u.f1.reg.f11r1 = cm_object_get_child_by_name(obj, "F11R1"); + state->u.f1.reg.f11r2 = cm_object_get_child_by_name(obj, "F11R2"); + state->u.f1.reg.f12r1 = cm_object_get_child_by_name(obj, "F12R1"); + state->u.f1.reg.f12r2 = cm_object_get_child_by_name(obj, "F12R2"); + state->u.f1.reg.f13r1 = cm_object_get_child_by_name(obj, "F13R1"); + state->u.f1.reg.f13r2 = cm_object_get_child_by_name(obj, "F13R2"); + state->u.f1.reg.f14r1 = cm_object_get_child_by_name(obj, "F14R1"); + state->u.f1.reg.f14r2 = cm_object_get_child_by_name(obj, "F14R2"); + state->u.f1.reg.f15r1 = cm_object_get_child_by_name(obj, "F15R1"); + state->u.f1.reg.f15r2 = cm_object_get_child_by_name(obj, "F15R2"); + state->u.f1.reg.f16r1 = cm_object_get_child_by_name(obj, "F16R1"); + state->u.f1.reg.f16r2 = cm_object_get_child_by_name(obj, "F16R2"); + state->u.f1.reg.f17r1 = cm_object_get_child_by_name(obj, "F17R1"); + state->u.f1.reg.f17r2 = cm_object_get_child_by_name(obj, "F17R2"); + state->u.f1.reg.f18r1 = cm_object_get_child_by_name(obj, "F18R1"); + state->u.f1.reg.f18r2 = cm_object_get_child_by_name(obj, "F18R2"); + state->u.f1.reg.f19r1 = cm_object_get_child_by_name(obj, "F19R1"); + state->u.f1.reg.f19r2 = cm_object_get_child_by_name(obj, "F19R2"); + state->u.f1.reg.f20r1 = cm_object_get_child_by_name(obj, "F20R1"); + state->u.f1.reg.f20r2 = cm_object_get_child_by_name(obj, "F20R2"); + state->u.f1.reg.f21r1 = cm_object_get_child_by_name(obj, "F21R1"); + state->u.f1.reg.f21r2 = cm_object_get_child_by_name(obj, "F21R2"); + state->u.f1.reg.f22r1 = cm_object_get_child_by_name(obj, "F22R1"); + state->u.f1.reg.f22r2 = cm_object_get_child_by_name(obj, "F22R2"); + state->u.f1.reg.f23r1 = cm_object_get_child_by_name(obj, "F23R1"); + state->u.f1.reg.f23r2 = cm_object_get_child_by_name(obj, "F23R2"); + state->u.f1.reg.f24r1 = cm_object_get_child_by_name(obj, "F24R1"); + state->u.f1.reg.f24r2 = cm_object_get_child_by_name(obj, "F24R2"); + state->u.f1.reg.f25r1 = cm_object_get_child_by_name(obj, "F25R1"); + state->u.f1.reg.f25r2 = cm_object_get_child_by_name(obj, "F25R2"); + state->u.f1.reg.f26r1 = cm_object_get_child_by_name(obj, "F26R1"); + state->u.f1.reg.f26r2 = cm_object_get_child_by_name(obj, "F26R2"); + state->u.f1.reg.f27r1 = cm_object_get_child_by_name(obj, "F27R1"); + state->u.f1.reg.f27r2 = cm_object_get_child_by_name(obj, "F27R2"); + + + // CAN_MCR bitfields. + state->u.f1.fld.can_mcr.inrq = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "INRQ"); + state->u.f1.fld.can_mcr.sleep = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "SLEEP"); + state->u.f1.fld.can_mcr.txfp = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "TXFP"); + state->u.f1.fld.can_mcr.rflm = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "RFLM"); + state->u.f1.fld.can_mcr.nart = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "NART"); + state->u.f1.fld.can_mcr.awum = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "AWUM"); + state->u.f1.fld.can_mcr.abom = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "ABOM"); + state->u.f1.fld.can_mcr.ttcm = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "TTCM"); + state->u.f1.fld.can_mcr.reset = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "RESET"); + state->u.f1.fld.can_mcr.dbf = cm_object_get_child_by_name(state->u.f1.reg.can_mcr, "DBF"); + + // CAN_MSR bitfields. + state->u.f1.fld.can_msr.inak = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "INAK"); + state->u.f1.fld.can_msr.slak = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "SLAK"); + state->u.f1.fld.can_msr.erri = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "ERRI"); + state->u.f1.fld.can_msr.wkui = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "WKUI"); + state->u.f1.fld.can_msr.slaki = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "SLAKI"); + state->u.f1.fld.can_msr.txm = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "TXM"); + state->u.f1.fld.can_msr.rxm = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "RXM"); + state->u.f1.fld.can_msr.samp = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "SAMP"); + state->u.f1.fld.can_msr.rx = cm_object_get_child_by_name(state->u.f1.reg.can_msr, "RX"); + + // CAN_TSR bitfields. + state->u.f1.fld.can_tsr.rqcp0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "RQCP0"); + state->u.f1.fld.can_tsr.txok0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TXOK0"); + state->u.f1.fld.can_tsr.alst0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ALST0"); + state->u.f1.fld.can_tsr.terr0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TERR0"); + state->u.f1.fld.can_tsr.abrq0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ABRQ0"); + state->u.f1.fld.can_tsr.rqcp1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "RQCP1"); + state->u.f1.fld.can_tsr.txok1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TXOK1"); + state->u.f1.fld.can_tsr.alst1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ALST1"); + state->u.f1.fld.can_tsr.terr1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TERR1"); + state->u.f1.fld.can_tsr.abrq1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ABRQ1"); + state->u.f1.fld.can_tsr.rqcp2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "RQCP2"); + state->u.f1.fld.can_tsr.txok2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TXOK2"); + state->u.f1.fld.can_tsr.alst2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ALST2"); + state->u.f1.fld.can_tsr.terr2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TERR2"); + state->u.f1.fld.can_tsr.abrq2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "ABRQ2"); + state->u.f1.fld.can_tsr.code = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "CODE"); + state->u.f1.fld.can_tsr.tme0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TME0"); + state->u.f1.fld.can_tsr.tme1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TME1"); + state->u.f1.fld.can_tsr.tme2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "TME2"); + state->u.f1.fld.can_tsr.low0 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "LOW0"); + state->u.f1.fld.can_tsr.low1 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "LOW1"); + state->u.f1.fld.can_tsr.low2 = cm_object_get_child_by_name(state->u.f1.reg.can_tsr, "LOW2"); + + // CAN_RF0R bitfields. + state->u.f1.fld.can_rf0r.fmp0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "FMP0"); + state->u.f1.fld.can_rf0r.full0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "FULL0"); + state->u.f1.fld.can_rf0r.fovr0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "FOVR0"); + state->u.f1.fld.can_rf0r.rfom0 = cm_object_get_child_by_name(state->u.f1.reg.can_rf0r, "RFOM0"); + + // CAN_RF1R bitfields. + state->u.f1.fld.can_rf1r.fmp1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "FMP1"); + state->u.f1.fld.can_rf1r.full1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "FULL1"); + state->u.f1.fld.can_rf1r.fovr1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "FOVR1"); + state->u.f1.fld.can_rf1r.rfom1 = cm_object_get_child_by_name(state->u.f1.reg.can_rf1r, "RFOM1"); + + // CAN_IER bitfields. + state->u.f1.fld.can_ier.tmeie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "TMEIE"); + state->u.f1.fld.can_ier.fmpie0 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FMPIE0"); + state->u.f1.fld.can_ier.ffie0 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FFIE0"); + state->u.f1.fld.can_ier.fovie0 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FOVIE0"); + state->u.f1.fld.can_ier.fmpie1 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FMPIE1"); + state->u.f1.fld.can_ier.ffie1 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FFIE1"); + state->u.f1.fld.can_ier.fovie1 = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "FOVIE1"); + state->u.f1.fld.can_ier.ewgie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "EWGIE"); + state->u.f1.fld.can_ier.epvie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "EPVIE"); + state->u.f1.fld.can_ier.bofie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "BOFIE"); + state->u.f1.fld.can_ier.lecie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "LECIE"); + state->u.f1.fld.can_ier.errie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "ERRIE"); + state->u.f1.fld.can_ier.wkuie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "WKUIE"); + state->u.f1.fld.can_ier.slkie = cm_object_get_child_by_name(state->u.f1.reg.can_ier, "SLKIE"); + + // CAN_ESR bitfields. + state->u.f1.fld.can_esr.ewgf = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "EWGF"); + state->u.f1.fld.can_esr.epvf = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "EPVF"); + state->u.f1.fld.can_esr.boff = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "BOFF"); + state->u.f1.fld.can_esr.lec = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "LEC"); + state->u.f1.fld.can_esr.tec = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "TEC"); + state->u.f1.fld.can_esr.rec = cm_object_get_child_by_name(state->u.f1.reg.can_esr, "REC"); + + // CAN_BTR bitfields. + state->u.f1.fld.can_btr.brp = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "BRP"); + state->u.f1.fld.can_btr.ts1 = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "TS1"); + state->u.f1.fld.can_btr.ts2 = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "TS2"); + state->u.f1.fld.can_btr.sjw = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "SJW"); + state->u.f1.fld.can_btr.lbkm = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "LBKM"); + state->u.f1.fld.can_btr.silm = cm_object_get_child_by_name(state->u.f1.reg.can_btr, "SILM"); + + // CAN_TI0R bitfields. + state->u.f1.fld.can_ti0r.txrq = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "TXRQ"); + state->u.f1.fld.can_ti0r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "RTR"); + state->u.f1.fld.can_ti0r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "IDE"); + state->u.f1.fld.can_ti0r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "EXID"); + state->u.f1.fld.can_ti0r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ti0r, "STID"); + + // CAN_TDT0R bitfields. + state->u.f1.fld.can_tdt0r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_tdt0r, "DLC"); + state->u.f1.fld.can_tdt0r.tgt = cm_object_get_child_by_name(state->u.f1.reg.can_tdt0r, "TGT"); + state->u.f1.fld.can_tdt0r.time = cm_object_get_child_by_name(state->u.f1.reg.can_tdt0r, "TIME"); + + // CAN_TDL0R bitfields. + state->u.f1.fld.can_tdl0r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA0"); + state->u.f1.fld.can_tdl0r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA1"); + state->u.f1.fld.can_tdl0r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA2"); + state->u.f1.fld.can_tdl0r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl0r, "DATA3"); + + // CAN_TDH0R bitfields. + state->u.f1.fld.can_tdh0r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA4"); + state->u.f1.fld.can_tdh0r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA5"); + state->u.f1.fld.can_tdh0r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA6"); + state->u.f1.fld.can_tdh0r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh0r, "DATA7"); + + // CAN_TI1R bitfields. + state->u.f1.fld.can_ti1r.txrq = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "TXRQ"); + state->u.f1.fld.can_ti1r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "RTR"); + state->u.f1.fld.can_ti1r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "IDE"); + state->u.f1.fld.can_ti1r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "EXID"); + state->u.f1.fld.can_ti1r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ti1r, "STID"); + + // CAN_TDT1R bitfields. + state->u.f1.fld.can_tdt1r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_tdt1r, "DLC"); + state->u.f1.fld.can_tdt1r.tgt = cm_object_get_child_by_name(state->u.f1.reg.can_tdt1r, "TGT"); + state->u.f1.fld.can_tdt1r.time = cm_object_get_child_by_name(state->u.f1.reg.can_tdt1r, "TIME"); + + // CAN_TDL1R bitfields. + state->u.f1.fld.can_tdl1r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA0"); + state->u.f1.fld.can_tdl1r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA1"); + state->u.f1.fld.can_tdl1r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA2"); + state->u.f1.fld.can_tdl1r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl1r, "DATA3"); + + // CAN_TDH1R bitfields. + state->u.f1.fld.can_tdh1r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA4"); + state->u.f1.fld.can_tdh1r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA5"); + state->u.f1.fld.can_tdh1r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA6"); + state->u.f1.fld.can_tdh1r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh1r, "DATA7"); + + // CAN_TI2R bitfields. + state->u.f1.fld.can_ti2r.txrq = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "TXRQ"); + state->u.f1.fld.can_ti2r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "RTR"); + state->u.f1.fld.can_ti2r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "IDE"); + state->u.f1.fld.can_ti2r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "EXID"); + state->u.f1.fld.can_ti2r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ti2r, "STID"); + + // CAN_TDT2R bitfields. + state->u.f1.fld.can_tdt2r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_tdt2r, "DLC"); + state->u.f1.fld.can_tdt2r.tgt = cm_object_get_child_by_name(state->u.f1.reg.can_tdt2r, "TGT"); + state->u.f1.fld.can_tdt2r.time = cm_object_get_child_by_name(state->u.f1.reg.can_tdt2r, "TIME"); + + // CAN_TDL2R bitfields. + state->u.f1.fld.can_tdl2r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA0"); + state->u.f1.fld.can_tdl2r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA1"); + state->u.f1.fld.can_tdl2r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA2"); + state->u.f1.fld.can_tdl2r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_tdl2r, "DATA3"); + + // CAN_TDH2R bitfields. + state->u.f1.fld.can_tdh2r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA4"); + state->u.f1.fld.can_tdh2r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA5"); + state->u.f1.fld.can_tdh2r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA6"); + state->u.f1.fld.can_tdh2r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_tdh2r, "DATA7"); + + // CAN_RI0R bitfields. + state->u.f1.fld.can_ri0r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "RTR"); + state->u.f1.fld.can_ri0r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "IDE"); + state->u.f1.fld.can_ri0r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "EXID"); + state->u.f1.fld.can_ri0r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ri0r, "STID"); + + // CAN_RDT0R bitfields. + state->u.f1.fld.can_rdt0r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_rdt0r, "DLC"); + state->u.f1.fld.can_rdt0r.fmi = cm_object_get_child_by_name(state->u.f1.reg.can_rdt0r, "FMI"); + state->u.f1.fld.can_rdt0r.time = cm_object_get_child_by_name(state->u.f1.reg.can_rdt0r, "TIME"); + + // CAN_RDL0R bitfields. + state->u.f1.fld.can_rdl0r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA0"); + state->u.f1.fld.can_rdl0r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA1"); + state->u.f1.fld.can_rdl0r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA2"); + state->u.f1.fld.can_rdl0r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl0r, "DATA3"); + + // CAN_RDH0R bitfields. + state->u.f1.fld.can_rdh0r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA4"); + state->u.f1.fld.can_rdh0r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA5"); + state->u.f1.fld.can_rdh0r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA6"); + state->u.f1.fld.can_rdh0r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh0r, "DATA7"); + + // CAN_RI1R bitfields. + state->u.f1.fld.can_ri1r.rtr = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "RTR"); + state->u.f1.fld.can_ri1r.ide = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "IDE"); + state->u.f1.fld.can_ri1r.exid = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "EXID"); + state->u.f1.fld.can_ri1r.stid = cm_object_get_child_by_name(state->u.f1.reg.can_ri1r, "STID"); + + // CAN_RDT1R bitfields. + state->u.f1.fld.can_rdt1r.dlc = cm_object_get_child_by_name(state->u.f1.reg.can_rdt1r, "DLC"); + state->u.f1.fld.can_rdt1r.fmi = cm_object_get_child_by_name(state->u.f1.reg.can_rdt1r, "FMI"); + state->u.f1.fld.can_rdt1r.time = cm_object_get_child_by_name(state->u.f1.reg.can_rdt1r, "TIME"); + + // CAN_RDL1R bitfields. + state->u.f1.fld.can_rdl1r.data0 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA0"); + state->u.f1.fld.can_rdl1r.data1 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA1"); + state->u.f1.fld.can_rdl1r.data2 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA2"); + state->u.f1.fld.can_rdl1r.data3 = cm_object_get_child_by_name(state->u.f1.reg.can_rdl1r, "DATA3"); + + // CAN_RDH1R bitfields. + state->u.f1.fld.can_rdh1r.data4 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA4"); + state->u.f1.fld.can_rdh1r.data5 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA5"); + state->u.f1.fld.can_rdh1r.data6 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA6"); + state->u.f1.fld.can_rdh1r.data7 = cm_object_get_child_by_name(state->u.f1.reg.can_rdh1r, "DATA7"); + + // CAN_FMR bitfields. + state->u.f1.fld.can_fmr.finit = cm_object_get_child_by_name(state->u.f1.reg.can_fmr, "FINIT"); + state->u.f1.fld.can_fmr.can2sb = cm_object_get_child_by_name(state->u.f1.reg.can_fmr, "CAN2SB"); + + // CAN_FM1R bitfields. + state->u.f1.fld.can_fm1r.fbm0 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM0"); + state->u.f1.fld.can_fm1r.fbm1 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM1"); + state->u.f1.fld.can_fm1r.fbm2 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM2"); + state->u.f1.fld.can_fm1r.fbm3 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM3"); + state->u.f1.fld.can_fm1r.fbm4 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM4"); + state->u.f1.fld.can_fm1r.fbm5 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM5"); + state->u.f1.fld.can_fm1r.fbm6 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM6"); + state->u.f1.fld.can_fm1r.fbm7 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM7"); + state->u.f1.fld.can_fm1r.fbm8 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM8"); + state->u.f1.fld.can_fm1r.fbm9 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM9"); + state->u.f1.fld.can_fm1r.fbm10 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM10"); + state->u.f1.fld.can_fm1r.fbm11 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM11"); + state->u.f1.fld.can_fm1r.fbm12 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM12"); + state->u.f1.fld.can_fm1r.fbm13 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM13"); + state->u.f1.fld.can_fm1r.fbm14 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM14"); + state->u.f1.fld.can_fm1r.fbm15 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM15"); + state->u.f1.fld.can_fm1r.fbm16 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM16"); + state->u.f1.fld.can_fm1r.fbm17 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM17"); + state->u.f1.fld.can_fm1r.fbm18 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM18"); + state->u.f1.fld.can_fm1r.fbm19 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM19"); + state->u.f1.fld.can_fm1r.fbm20 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM20"); + state->u.f1.fld.can_fm1r.fbm21 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM21"); + state->u.f1.fld.can_fm1r.fbm22 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM22"); + state->u.f1.fld.can_fm1r.fbm23 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM23"); + state->u.f1.fld.can_fm1r.fbm24 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM24"); + state->u.f1.fld.can_fm1r.fbm25 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM25"); + state->u.f1.fld.can_fm1r.fbm26 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM26"); + state->u.f1.fld.can_fm1r.fbm27 = cm_object_get_child_by_name(state->u.f1.reg.can_fm1r, "FBM27"); + + // CAN_FS1R bitfields. + state->u.f1.fld.can_fs1r.fsc0 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC0"); + state->u.f1.fld.can_fs1r.fsc1 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC1"); + state->u.f1.fld.can_fs1r.fsc2 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC2"); + state->u.f1.fld.can_fs1r.fsc3 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC3"); + state->u.f1.fld.can_fs1r.fsc4 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC4"); + state->u.f1.fld.can_fs1r.fsc5 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC5"); + state->u.f1.fld.can_fs1r.fsc6 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC6"); + state->u.f1.fld.can_fs1r.fsc7 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC7"); + state->u.f1.fld.can_fs1r.fsc8 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC8"); + state->u.f1.fld.can_fs1r.fsc9 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC9"); + state->u.f1.fld.can_fs1r.fsc10 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC10"); + state->u.f1.fld.can_fs1r.fsc11 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC11"); + state->u.f1.fld.can_fs1r.fsc12 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC12"); + state->u.f1.fld.can_fs1r.fsc13 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC13"); + state->u.f1.fld.can_fs1r.fsc14 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC14"); + state->u.f1.fld.can_fs1r.fsc15 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC15"); + state->u.f1.fld.can_fs1r.fsc16 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC16"); + state->u.f1.fld.can_fs1r.fsc17 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC17"); + state->u.f1.fld.can_fs1r.fsc18 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC18"); + state->u.f1.fld.can_fs1r.fsc19 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC19"); + state->u.f1.fld.can_fs1r.fsc20 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC20"); + state->u.f1.fld.can_fs1r.fsc21 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC21"); + state->u.f1.fld.can_fs1r.fsc22 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC22"); + state->u.f1.fld.can_fs1r.fsc23 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC23"); + state->u.f1.fld.can_fs1r.fsc24 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC24"); + state->u.f1.fld.can_fs1r.fsc25 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC25"); + state->u.f1.fld.can_fs1r.fsc26 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC26"); + state->u.f1.fld.can_fs1r.fsc27 = cm_object_get_child_by_name(state->u.f1.reg.can_fs1r, "FSC27"); + + // CAN_FFA1R bitfields. + state->u.f1.fld.can_ffa1r.ffa0 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA0"); + state->u.f1.fld.can_ffa1r.ffa1 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA1"); + state->u.f1.fld.can_ffa1r.ffa2 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA2"); + state->u.f1.fld.can_ffa1r.ffa3 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA3"); + state->u.f1.fld.can_ffa1r.ffa4 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA4"); + state->u.f1.fld.can_ffa1r.ffa5 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA5"); + state->u.f1.fld.can_ffa1r.ffa6 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA6"); + state->u.f1.fld.can_ffa1r.ffa7 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA7"); + state->u.f1.fld.can_ffa1r.ffa8 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA8"); + state->u.f1.fld.can_ffa1r.ffa9 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA9"); + state->u.f1.fld.can_ffa1r.ffa10 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA10"); + state->u.f1.fld.can_ffa1r.ffa11 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA11"); + state->u.f1.fld.can_ffa1r.ffa12 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA12"); + state->u.f1.fld.can_ffa1r.ffa13 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA13"); + state->u.f1.fld.can_ffa1r.ffa14 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA14"); + state->u.f1.fld.can_ffa1r.ffa15 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA15"); + state->u.f1.fld.can_ffa1r.ffa16 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA16"); + state->u.f1.fld.can_ffa1r.ffa17 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA17"); + state->u.f1.fld.can_ffa1r.ffa18 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA18"); + state->u.f1.fld.can_ffa1r.ffa19 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA19"); + state->u.f1.fld.can_ffa1r.ffa20 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA20"); + state->u.f1.fld.can_ffa1r.ffa21 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA21"); + state->u.f1.fld.can_ffa1r.ffa22 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA22"); + state->u.f1.fld.can_ffa1r.ffa23 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA23"); + state->u.f1.fld.can_ffa1r.ffa24 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA24"); + state->u.f1.fld.can_ffa1r.ffa25 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA25"); + state->u.f1.fld.can_ffa1r.ffa26 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA26"); + state->u.f1.fld.can_ffa1r.ffa27 = cm_object_get_child_by_name(state->u.f1.reg.can_ffa1r, "FFA27"); + + // CAN_FA1R bitfields. + state->u.f1.fld.can_fa1r.fact0 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT0"); + state->u.f1.fld.can_fa1r.fact1 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT1"); + state->u.f1.fld.can_fa1r.fact2 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT2"); + state->u.f1.fld.can_fa1r.fact3 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT3"); + state->u.f1.fld.can_fa1r.fact4 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT4"); + state->u.f1.fld.can_fa1r.fact5 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT5"); + state->u.f1.fld.can_fa1r.fact6 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT6"); + state->u.f1.fld.can_fa1r.fact7 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT7"); + state->u.f1.fld.can_fa1r.fact8 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT8"); + state->u.f1.fld.can_fa1r.fact9 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT9"); + state->u.f1.fld.can_fa1r.fact10 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT10"); + state->u.f1.fld.can_fa1r.fact11 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT11"); + state->u.f1.fld.can_fa1r.fact12 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT12"); + state->u.f1.fld.can_fa1r.fact13 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT13"); + state->u.f1.fld.can_fa1r.fact14 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT14"); + state->u.f1.fld.can_fa1r.fact15 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT15"); + state->u.f1.fld.can_fa1r.fact16 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT16"); + state->u.f1.fld.can_fa1r.fact17 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT17"); + state->u.f1.fld.can_fa1r.fact18 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT18"); + state->u.f1.fld.can_fa1r.fact19 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT19"); + state->u.f1.fld.can_fa1r.fact20 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT20"); + state->u.f1.fld.can_fa1r.fact21 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT21"); + state->u.f1.fld.can_fa1r.fact22 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT22"); + state->u.f1.fld.can_fa1r.fact23 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT23"); + state->u.f1.fld.can_fa1r.fact24 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT24"); + state->u.f1.fld.can_fa1r.fact25 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT25"); + state->u.f1.fld.can_fa1r.fact26 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT26"); + state->u.f1.fld.can_fa1r.fact27 = cm_object_get_child_by_name(state->u.f1.reg.can_fa1r, "FACT27"); + + // F0R1 bitfields. + state->u.f1.fld.f0r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB0"); + state->u.f1.fld.f0r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB1"); + state->u.f1.fld.f0r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB2"); + state->u.f1.fld.f0r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB3"); + state->u.f1.fld.f0r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB4"); + state->u.f1.fld.f0r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB5"); + state->u.f1.fld.f0r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB6"); + state->u.f1.fld.f0r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB7"); + state->u.f1.fld.f0r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB8"); + state->u.f1.fld.f0r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB9"); + state->u.f1.fld.f0r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB10"); + state->u.f1.fld.f0r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB11"); + state->u.f1.fld.f0r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB12"); + state->u.f1.fld.f0r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB13"); + state->u.f1.fld.f0r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB14"); + state->u.f1.fld.f0r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB15"); + state->u.f1.fld.f0r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB16"); + state->u.f1.fld.f0r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB17"); + state->u.f1.fld.f0r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB18"); + state->u.f1.fld.f0r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB19"); + state->u.f1.fld.f0r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB20"); + state->u.f1.fld.f0r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB21"); + state->u.f1.fld.f0r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB22"); + state->u.f1.fld.f0r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB23"); + state->u.f1.fld.f0r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB24"); + state->u.f1.fld.f0r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB25"); + state->u.f1.fld.f0r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB26"); + state->u.f1.fld.f0r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB27"); + state->u.f1.fld.f0r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB28"); + state->u.f1.fld.f0r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB29"); + state->u.f1.fld.f0r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB30"); + state->u.f1.fld.f0r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f0r1, "FB31"); + + // F0R2 bitfields. + state->u.f1.fld.f0r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB0"); + state->u.f1.fld.f0r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB1"); + state->u.f1.fld.f0r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB2"); + state->u.f1.fld.f0r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB3"); + state->u.f1.fld.f0r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB4"); + state->u.f1.fld.f0r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB5"); + state->u.f1.fld.f0r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB6"); + state->u.f1.fld.f0r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB7"); + state->u.f1.fld.f0r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB8"); + state->u.f1.fld.f0r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB9"); + state->u.f1.fld.f0r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB10"); + state->u.f1.fld.f0r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB11"); + state->u.f1.fld.f0r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB12"); + state->u.f1.fld.f0r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB13"); + state->u.f1.fld.f0r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB14"); + state->u.f1.fld.f0r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB15"); + state->u.f1.fld.f0r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB16"); + state->u.f1.fld.f0r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB17"); + state->u.f1.fld.f0r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB18"); + state->u.f1.fld.f0r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB19"); + state->u.f1.fld.f0r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB20"); + state->u.f1.fld.f0r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB21"); + state->u.f1.fld.f0r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB22"); + state->u.f1.fld.f0r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB23"); + state->u.f1.fld.f0r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB24"); + state->u.f1.fld.f0r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB25"); + state->u.f1.fld.f0r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB26"); + state->u.f1.fld.f0r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB27"); + state->u.f1.fld.f0r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB28"); + state->u.f1.fld.f0r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB29"); + state->u.f1.fld.f0r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB30"); + state->u.f1.fld.f0r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f0r2, "FB31"); + + // F1R1 bitfields. + state->u.f1.fld.f1r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB0"); + state->u.f1.fld.f1r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB1"); + state->u.f1.fld.f1r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB2"); + state->u.f1.fld.f1r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB3"); + state->u.f1.fld.f1r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB4"); + state->u.f1.fld.f1r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB5"); + state->u.f1.fld.f1r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB6"); + state->u.f1.fld.f1r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB7"); + state->u.f1.fld.f1r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB8"); + state->u.f1.fld.f1r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB9"); + state->u.f1.fld.f1r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB10"); + state->u.f1.fld.f1r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB11"); + state->u.f1.fld.f1r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB12"); + state->u.f1.fld.f1r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB13"); + state->u.f1.fld.f1r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB14"); + state->u.f1.fld.f1r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB15"); + state->u.f1.fld.f1r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB16"); + state->u.f1.fld.f1r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB17"); + state->u.f1.fld.f1r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB18"); + state->u.f1.fld.f1r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB19"); + state->u.f1.fld.f1r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB20"); + state->u.f1.fld.f1r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB21"); + state->u.f1.fld.f1r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB22"); + state->u.f1.fld.f1r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB23"); + state->u.f1.fld.f1r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB24"); + state->u.f1.fld.f1r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB25"); + state->u.f1.fld.f1r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB26"); + state->u.f1.fld.f1r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB27"); + state->u.f1.fld.f1r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB28"); + state->u.f1.fld.f1r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB29"); + state->u.f1.fld.f1r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB30"); + state->u.f1.fld.f1r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f1r1, "FB31"); + + // F1R2 bitfields. + state->u.f1.fld.f1r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB0"); + state->u.f1.fld.f1r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB1"); + state->u.f1.fld.f1r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB2"); + state->u.f1.fld.f1r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB3"); + state->u.f1.fld.f1r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB4"); + state->u.f1.fld.f1r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB5"); + state->u.f1.fld.f1r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB6"); + state->u.f1.fld.f1r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB7"); + state->u.f1.fld.f1r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB8"); + state->u.f1.fld.f1r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB9"); + state->u.f1.fld.f1r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB10"); + state->u.f1.fld.f1r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB11"); + state->u.f1.fld.f1r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB12"); + state->u.f1.fld.f1r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB13"); + state->u.f1.fld.f1r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB14"); + state->u.f1.fld.f1r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB15"); + state->u.f1.fld.f1r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB16"); + state->u.f1.fld.f1r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB17"); + state->u.f1.fld.f1r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB18"); + state->u.f1.fld.f1r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB19"); + state->u.f1.fld.f1r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB20"); + state->u.f1.fld.f1r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB21"); + state->u.f1.fld.f1r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB22"); + state->u.f1.fld.f1r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB23"); + state->u.f1.fld.f1r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB24"); + state->u.f1.fld.f1r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB25"); + state->u.f1.fld.f1r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB26"); + state->u.f1.fld.f1r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB27"); + state->u.f1.fld.f1r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB28"); + state->u.f1.fld.f1r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB29"); + state->u.f1.fld.f1r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB30"); + state->u.f1.fld.f1r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f1r2, "FB31"); + + // F2R1 bitfields. + state->u.f1.fld.f2r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB0"); + state->u.f1.fld.f2r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB1"); + state->u.f1.fld.f2r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB2"); + state->u.f1.fld.f2r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB3"); + state->u.f1.fld.f2r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB4"); + state->u.f1.fld.f2r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB5"); + state->u.f1.fld.f2r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB6"); + state->u.f1.fld.f2r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB7"); + state->u.f1.fld.f2r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB8"); + state->u.f1.fld.f2r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB9"); + state->u.f1.fld.f2r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB10"); + state->u.f1.fld.f2r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB11"); + state->u.f1.fld.f2r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB12"); + state->u.f1.fld.f2r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB13"); + state->u.f1.fld.f2r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB14"); + state->u.f1.fld.f2r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB15"); + state->u.f1.fld.f2r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB16"); + state->u.f1.fld.f2r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB17"); + state->u.f1.fld.f2r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB18"); + state->u.f1.fld.f2r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB19"); + state->u.f1.fld.f2r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB20"); + state->u.f1.fld.f2r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB21"); + state->u.f1.fld.f2r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB22"); + state->u.f1.fld.f2r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB23"); + state->u.f1.fld.f2r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB24"); + state->u.f1.fld.f2r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB25"); + state->u.f1.fld.f2r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB26"); + state->u.f1.fld.f2r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB27"); + state->u.f1.fld.f2r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB28"); + state->u.f1.fld.f2r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB29"); + state->u.f1.fld.f2r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB30"); + state->u.f1.fld.f2r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f2r1, "FB31"); + + // F2R2 bitfields. + state->u.f1.fld.f2r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB0"); + state->u.f1.fld.f2r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB1"); + state->u.f1.fld.f2r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB2"); + state->u.f1.fld.f2r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB3"); + state->u.f1.fld.f2r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB4"); + state->u.f1.fld.f2r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB5"); + state->u.f1.fld.f2r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB6"); + state->u.f1.fld.f2r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB7"); + state->u.f1.fld.f2r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB8"); + state->u.f1.fld.f2r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB9"); + state->u.f1.fld.f2r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB10"); + state->u.f1.fld.f2r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB11"); + state->u.f1.fld.f2r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB12"); + state->u.f1.fld.f2r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB13"); + state->u.f1.fld.f2r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB14"); + state->u.f1.fld.f2r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB15"); + state->u.f1.fld.f2r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB16"); + state->u.f1.fld.f2r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB17"); + state->u.f1.fld.f2r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB18"); + state->u.f1.fld.f2r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB19"); + state->u.f1.fld.f2r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB20"); + state->u.f1.fld.f2r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB21"); + state->u.f1.fld.f2r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB22"); + state->u.f1.fld.f2r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB23"); + state->u.f1.fld.f2r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB24"); + state->u.f1.fld.f2r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB25"); + state->u.f1.fld.f2r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB26"); + state->u.f1.fld.f2r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB27"); + state->u.f1.fld.f2r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB28"); + state->u.f1.fld.f2r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB29"); + state->u.f1.fld.f2r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB30"); + state->u.f1.fld.f2r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f2r2, "FB31"); + + // F3R1 bitfields. + state->u.f1.fld.f3r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB0"); + state->u.f1.fld.f3r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB1"); + state->u.f1.fld.f3r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB2"); + state->u.f1.fld.f3r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB3"); + state->u.f1.fld.f3r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB4"); + state->u.f1.fld.f3r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB5"); + state->u.f1.fld.f3r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB6"); + state->u.f1.fld.f3r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB7"); + state->u.f1.fld.f3r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB8"); + state->u.f1.fld.f3r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB9"); + state->u.f1.fld.f3r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB10"); + state->u.f1.fld.f3r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB11"); + state->u.f1.fld.f3r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB12"); + state->u.f1.fld.f3r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB13"); + state->u.f1.fld.f3r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB14"); + state->u.f1.fld.f3r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB15"); + state->u.f1.fld.f3r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB16"); + state->u.f1.fld.f3r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB17"); + state->u.f1.fld.f3r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB18"); + state->u.f1.fld.f3r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB19"); + state->u.f1.fld.f3r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB20"); + state->u.f1.fld.f3r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB21"); + state->u.f1.fld.f3r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB22"); + state->u.f1.fld.f3r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB23"); + state->u.f1.fld.f3r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB24"); + state->u.f1.fld.f3r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB25"); + state->u.f1.fld.f3r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB26"); + state->u.f1.fld.f3r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB27"); + state->u.f1.fld.f3r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB28"); + state->u.f1.fld.f3r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB29"); + state->u.f1.fld.f3r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB30"); + state->u.f1.fld.f3r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f3r1, "FB31"); + + // F3R2 bitfields. + state->u.f1.fld.f3r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB0"); + state->u.f1.fld.f3r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB1"); + state->u.f1.fld.f3r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB2"); + state->u.f1.fld.f3r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB3"); + state->u.f1.fld.f3r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB4"); + state->u.f1.fld.f3r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB5"); + state->u.f1.fld.f3r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB6"); + state->u.f1.fld.f3r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB7"); + state->u.f1.fld.f3r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB8"); + state->u.f1.fld.f3r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB9"); + state->u.f1.fld.f3r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB10"); + state->u.f1.fld.f3r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB11"); + state->u.f1.fld.f3r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB12"); + state->u.f1.fld.f3r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB13"); + state->u.f1.fld.f3r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB14"); + state->u.f1.fld.f3r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB15"); + state->u.f1.fld.f3r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB16"); + state->u.f1.fld.f3r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB17"); + state->u.f1.fld.f3r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB18"); + state->u.f1.fld.f3r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB19"); + state->u.f1.fld.f3r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB20"); + state->u.f1.fld.f3r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB21"); + state->u.f1.fld.f3r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB22"); + state->u.f1.fld.f3r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB23"); + state->u.f1.fld.f3r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB24"); + state->u.f1.fld.f3r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB25"); + state->u.f1.fld.f3r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB26"); + state->u.f1.fld.f3r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB27"); + state->u.f1.fld.f3r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB28"); + state->u.f1.fld.f3r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB29"); + state->u.f1.fld.f3r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB30"); + state->u.f1.fld.f3r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f3r2, "FB31"); + + // F4R1 bitfields. + state->u.f1.fld.f4r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB0"); + state->u.f1.fld.f4r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB1"); + state->u.f1.fld.f4r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB2"); + state->u.f1.fld.f4r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB3"); + state->u.f1.fld.f4r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB4"); + state->u.f1.fld.f4r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB5"); + state->u.f1.fld.f4r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB6"); + state->u.f1.fld.f4r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB7"); + state->u.f1.fld.f4r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB8"); + state->u.f1.fld.f4r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB9"); + state->u.f1.fld.f4r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB10"); + state->u.f1.fld.f4r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB11"); + state->u.f1.fld.f4r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB12"); + state->u.f1.fld.f4r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB13"); + state->u.f1.fld.f4r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB14"); + state->u.f1.fld.f4r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB15"); + state->u.f1.fld.f4r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB16"); + state->u.f1.fld.f4r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB17"); + state->u.f1.fld.f4r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB18"); + state->u.f1.fld.f4r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB19"); + state->u.f1.fld.f4r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB20"); + state->u.f1.fld.f4r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB21"); + state->u.f1.fld.f4r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB22"); + state->u.f1.fld.f4r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB23"); + state->u.f1.fld.f4r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB24"); + state->u.f1.fld.f4r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB25"); + state->u.f1.fld.f4r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB26"); + state->u.f1.fld.f4r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB27"); + state->u.f1.fld.f4r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB28"); + state->u.f1.fld.f4r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB29"); + state->u.f1.fld.f4r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB30"); + state->u.f1.fld.f4r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f4r1, "FB31"); + + // F4R2 bitfields. + state->u.f1.fld.f4r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB0"); + state->u.f1.fld.f4r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB1"); + state->u.f1.fld.f4r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB2"); + state->u.f1.fld.f4r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB3"); + state->u.f1.fld.f4r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB4"); + state->u.f1.fld.f4r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB5"); + state->u.f1.fld.f4r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB6"); + state->u.f1.fld.f4r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB7"); + state->u.f1.fld.f4r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB8"); + state->u.f1.fld.f4r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB9"); + state->u.f1.fld.f4r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB10"); + state->u.f1.fld.f4r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB11"); + state->u.f1.fld.f4r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB12"); + state->u.f1.fld.f4r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB13"); + state->u.f1.fld.f4r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB14"); + state->u.f1.fld.f4r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB15"); + state->u.f1.fld.f4r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB16"); + state->u.f1.fld.f4r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB17"); + state->u.f1.fld.f4r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB18"); + state->u.f1.fld.f4r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB19"); + state->u.f1.fld.f4r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB20"); + state->u.f1.fld.f4r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB21"); + state->u.f1.fld.f4r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB22"); + state->u.f1.fld.f4r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB23"); + state->u.f1.fld.f4r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB24"); + state->u.f1.fld.f4r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB25"); + state->u.f1.fld.f4r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB26"); + state->u.f1.fld.f4r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB27"); + state->u.f1.fld.f4r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB28"); + state->u.f1.fld.f4r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB29"); + state->u.f1.fld.f4r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB30"); + state->u.f1.fld.f4r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f4r2, "FB31"); + + // F5R1 bitfields. + state->u.f1.fld.f5r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB0"); + state->u.f1.fld.f5r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB1"); + state->u.f1.fld.f5r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB2"); + state->u.f1.fld.f5r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB3"); + state->u.f1.fld.f5r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB4"); + state->u.f1.fld.f5r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB5"); + state->u.f1.fld.f5r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB6"); + state->u.f1.fld.f5r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB7"); + state->u.f1.fld.f5r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB8"); + state->u.f1.fld.f5r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB9"); + state->u.f1.fld.f5r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB10"); + state->u.f1.fld.f5r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB11"); + state->u.f1.fld.f5r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB12"); + state->u.f1.fld.f5r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB13"); + state->u.f1.fld.f5r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB14"); + state->u.f1.fld.f5r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB15"); + state->u.f1.fld.f5r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB16"); + state->u.f1.fld.f5r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB17"); + state->u.f1.fld.f5r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB18"); + state->u.f1.fld.f5r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB19"); + state->u.f1.fld.f5r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB20"); + state->u.f1.fld.f5r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB21"); + state->u.f1.fld.f5r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB22"); + state->u.f1.fld.f5r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB23"); + state->u.f1.fld.f5r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB24"); + state->u.f1.fld.f5r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB25"); + state->u.f1.fld.f5r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB26"); + state->u.f1.fld.f5r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB27"); + state->u.f1.fld.f5r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB28"); + state->u.f1.fld.f5r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB29"); + state->u.f1.fld.f5r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB30"); + state->u.f1.fld.f5r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f5r1, "FB31"); + + // F5R2 bitfields. + state->u.f1.fld.f5r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB0"); + state->u.f1.fld.f5r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB1"); + state->u.f1.fld.f5r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB2"); + state->u.f1.fld.f5r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB3"); + state->u.f1.fld.f5r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB4"); + state->u.f1.fld.f5r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB5"); + state->u.f1.fld.f5r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB6"); + state->u.f1.fld.f5r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB7"); + state->u.f1.fld.f5r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB8"); + state->u.f1.fld.f5r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB9"); + state->u.f1.fld.f5r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB10"); + state->u.f1.fld.f5r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB11"); + state->u.f1.fld.f5r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB12"); + state->u.f1.fld.f5r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB13"); + state->u.f1.fld.f5r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB14"); + state->u.f1.fld.f5r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB15"); + state->u.f1.fld.f5r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB16"); + state->u.f1.fld.f5r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB17"); + state->u.f1.fld.f5r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB18"); + state->u.f1.fld.f5r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB19"); + state->u.f1.fld.f5r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB20"); + state->u.f1.fld.f5r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB21"); + state->u.f1.fld.f5r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB22"); + state->u.f1.fld.f5r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB23"); + state->u.f1.fld.f5r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB24"); + state->u.f1.fld.f5r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB25"); + state->u.f1.fld.f5r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB26"); + state->u.f1.fld.f5r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB27"); + state->u.f1.fld.f5r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB28"); + state->u.f1.fld.f5r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB29"); + state->u.f1.fld.f5r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB30"); + state->u.f1.fld.f5r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f5r2, "FB31"); + + // F6R1 bitfields. + state->u.f1.fld.f6r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB0"); + state->u.f1.fld.f6r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB1"); + state->u.f1.fld.f6r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB2"); + state->u.f1.fld.f6r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB3"); + state->u.f1.fld.f6r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB4"); + state->u.f1.fld.f6r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB5"); + state->u.f1.fld.f6r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB6"); + state->u.f1.fld.f6r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB7"); + state->u.f1.fld.f6r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB8"); + state->u.f1.fld.f6r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB9"); + state->u.f1.fld.f6r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB10"); + state->u.f1.fld.f6r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB11"); + state->u.f1.fld.f6r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB12"); + state->u.f1.fld.f6r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB13"); + state->u.f1.fld.f6r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB14"); + state->u.f1.fld.f6r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB15"); + state->u.f1.fld.f6r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB16"); + state->u.f1.fld.f6r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB17"); + state->u.f1.fld.f6r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB18"); + state->u.f1.fld.f6r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB19"); + state->u.f1.fld.f6r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB20"); + state->u.f1.fld.f6r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB21"); + state->u.f1.fld.f6r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB22"); + state->u.f1.fld.f6r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB23"); + state->u.f1.fld.f6r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB24"); + state->u.f1.fld.f6r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB25"); + state->u.f1.fld.f6r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB26"); + state->u.f1.fld.f6r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB27"); + state->u.f1.fld.f6r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB28"); + state->u.f1.fld.f6r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB29"); + state->u.f1.fld.f6r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB30"); + state->u.f1.fld.f6r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f6r1, "FB31"); + + // F6R2 bitfields. + state->u.f1.fld.f6r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB0"); + state->u.f1.fld.f6r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB1"); + state->u.f1.fld.f6r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB2"); + state->u.f1.fld.f6r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB3"); + state->u.f1.fld.f6r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB4"); + state->u.f1.fld.f6r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB5"); + state->u.f1.fld.f6r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB6"); + state->u.f1.fld.f6r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB7"); + state->u.f1.fld.f6r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB8"); + state->u.f1.fld.f6r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB9"); + state->u.f1.fld.f6r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB10"); + state->u.f1.fld.f6r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB11"); + state->u.f1.fld.f6r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB12"); + state->u.f1.fld.f6r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB13"); + state->u.f1.fld.f6r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB14"); + state->u.f1.fld.f6r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB15"); + state->u.f1.fld.f6r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB16"); + state->u.f1.fld.f6r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB17"); + state->u.f1.fld.f6r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB18"); + state->u.f1.fld.f6r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB19"); + state->u.f1.fld.f6r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB20"); + state->u.f1.fld.f6r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB21"); + state->u.f1.fld.f6r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB22"); + state->u.f1.fld.f6r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB23"); + state->u.f1.fld.f6r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB24"); + state->u.f1.fld.f6r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB25"); + state->u.f1.fld.f6r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB26"); + state->u.f1.fld.f6r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB27"); + state->u.f1.fld.f6r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB28"); + state->u.f1.fld.f6r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB29"); + state->u.f1.fld.f6r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB30"); + state->u.f1.fld.f6r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f6r2, "FB31"); + + // F7R1 bitfields. + state->u.f1.fld.f7r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB0"); + state->u.f1.fld.f7r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB1"); + state->u.f1.fld.f7r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB2"); + state->u.f1.fld.f7r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB3"); + state->u.f1.fld.f7r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB4"); + state->u.f1.fld.f7r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB5"); + state->u.f1.fld.f7r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB6"); + state->u.f1.fld.f7r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB7"); + state->u.f1.fld.f7r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB8"); + state->u.f1.fld.f7r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB9"); + state->u.f1.fld.f7r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB10"); + state->u.f1.fld.f7r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB11"); + state->u.f1.fld.f7r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB12"); + state->u.f1.fld.f7r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB13"); + state->u.f1.fld.f7r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB14"); + state->u.f1.fld.f7r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB15"); + state->u.f1.fld.f7r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB16"); + state->u.f1.fld.f7r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB17"); + state->u.f1.fld.f7r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB18"); + state->u.f1.fld.f7r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB19"); + state->u.f1.fld.f7r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB20"); + state->u.f1.fld.f7r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB21"); + state->u.f1.fld.f7r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB22"); + state->u.f1.fld.f7r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB23"); + state->u.f1.fld.f7r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB24"); + state->u.f1.fld.f7r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB25"); + state->u.f1.fld.f7r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB26"); + state->u.f1.fld.f7r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB27"); + state->u.f1.fld.f7r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB28"); + state->u.f1.fld.f7r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB29"); + state->u.f1.fld.f7r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB30"); + state->u.f1.fld.f7r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f7r1, "FB31"); + + // F7R2 bitfields. + state->u.f1.fld.f7r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB0"); + state->u.f1.fld.f7r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB1"); + state->u.f1.fld.f7r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB2"); + state->u.f1.fld.f7r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB3"); + state->u.f1.fld.f7r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB4"); + state->u.f1.fld.f7r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB5"); + state->u.f1.fld.f7r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB6"); + state->u.f1.fld.f7r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB7"); + state->u.f1.fld.f7r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB8"); + state->u.f1.fld.f7r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB9"); + state->u.f1.fld.f7r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB10"); + state->u.f1.fld.f7r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB11"); + state->u.f1.fld.f7r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB12"); + state->u.f1.fld.f7r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB13"); + state->u.f1.fld.f7r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB14"); + state->u.f1.fld.f7r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB15"); + state->u.f1.fld.f7r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB16"); + state->u.f1.fld.f7r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB17"); + state->u.f1.fld.f7r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB18"); + state->u.f1.fld.f7r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB19"); + state->u.f1.fld.f7r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB20"); + state->u.f1.fld.f7r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB21"); + state->u.f1.fld.f7r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB22"); + state->u.f1.fld.f7r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB23"); + state->u.f1.fld.f7r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB24"); + state->u.f1.fld.f7r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB25"); + state->u.f1.fld.f7r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB26"); + state->u.f1.fld.f7r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB27"); + state->u.f1.fld.f7r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB28"); + state->u.f1.fld.f7r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB29"); + state->u.f1.fld.f7r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB30"); + state->u.f1.fld.f7r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f7r2, "FB31"); + + // F8R1 bitfields. + state->u.f1.fld.f8r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB0"); + state->u.f1.fld.f8r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB1"); + state->u.f1.fld.f8r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB2"); + state->u.f1.fld.f8r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB3"); + state->u.f1.fld.f8r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB4"); + state->u.f1.fld.f8r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB5"); + state->u.f1.fld.f8r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB6"); + state->u.f1.fld.f8r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB7"); + state->u.f1.fld.f8r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB8"); + state->u.f1.fld.f8r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB9"); + state->u.f1.fld.f8r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB10"); + state->u.f1.fld.f8r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB11"); + state->u.f1.fld.f8r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB12"); + state->u.f1.fld.f8r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB13"); + state->u.f1.fld.f8r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB14"); + state->u.f1.fld.f8r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB15"); + state->u.f1.fld.f8r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB16"); + state->u.f1.fld.f8r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB17"); + state->u.f1.fld.f8r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB18"); + state->u.f1.fld.f8r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB19"); + state->u.f1.fld.f8r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB20"); + state->u.f1.fld.f8r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB21"); + state->u.f1.fld.f8r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB22"); + state->u.f1.fld.f8r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB23"); + state->u.f1.fld.f8r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB24"); + state->u.f1.fld.f8r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB25"); + state->u.f1.fld.f8r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB26"); + state->u.f1.fld.f8r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB27"); + state->u.f1.fld.f8r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB28"); + state->u.f1.fld.f8r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB29"); + state->u.f1.fld.f8r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB30"); + state->u.f1.fld.f8r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f8r1, "FB31"); + + // F8R2 bitfields. + state->u.f1.fld.f8r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB0"); + state->u.f1.fld.f8r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB1"); + state->u.f1.fld.f8r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB2"); + state->u.f1.fld.f8r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB3"); + state->u.f1.fld.f8r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB4"); + state->u.f1.fld.f8r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB5"); + state->u.f1.fld.f8r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB6"); + state->u.f1.fld.f8r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB7"); + state->u.f1.fld.f8r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB8"); + state->u.f1.fld.f8r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB9"); + state->u.f1.fld.f8r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB10"); + state->u.f1.fld.f8r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB11"); + state->u.f1.fld.f8r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB12"); + state->u.f1.fld.f8r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB13"); + state->u.f1.fld.f8r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB14"); + state->u.f1.fld.f8r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB15"); + state->u.f1.fld.f8r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB16"); + state->u.f1.fld.f8r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB17"); + state->u.f1.fld.f8r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB18"); + state->u.f1.fld.f8r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB19"); + state->u.f1.fld.f8r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB20"); + state->u.f1.fld.f8r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB21"); + state->u.f1.fld.f8r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB22"); + state->u.f1.fld.f8r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB23"); + state->u.f1.fld.f8r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB24"); + state->u.f1.fld.f8r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB25"); + state->u.f1.fld.f8r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB26"); + state->u.f1.fld.f8r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB27"); + state->u.f1.fld.f8r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB28"); + state->u.f1.fld.f8r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB29"); + state->u.f1.fld.f8r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB30"); + state->u.f1.fld.f8r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f8r2, "FB31"); + + // F9R1 bitfields. + state->u.f1.fld.f9r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB0"); + state->u.f1.fld.f9r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB1"); + state->u.f1.fld.f9r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB2"); + state->u.f1.fld.f9r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB3"); + state->u.f1.fld.f9r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB4"); + state->u.f1.fld.f9r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB5"); + state->u.f1.fld.f9r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB6"); + state->u.f1.fld.f9r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB7"); + state->u.f1.fld.f9r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB8"); + state->u.f1.fld.f9r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB9"); + state->u.f1.fld.f9r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB10"); + state->u.f1.fld.f9r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB11"); + state->u.f1.fld.f9r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB12"); + state->u.f1.fld.f9r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB13"); + state->u.f1.fld.f9r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB14"); + state->u.f1.fld.f9r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB15"); + state->u.f1.fld.f9r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB16"); + state->u.f1.fld.f9r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB17"); + state->u.f1.fld.f9r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB18"); + state->u.f1.fld.f9r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB19"); + state->u.f1.fld.f9r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB20"); + state->u.f1.fld.f9r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB21"); + state->u.f1.fld.f9r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB22"); + state->u.f1.fld.f9r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB23"); + state->u.f1.fld.f9r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB24"); + state->u.f1.fld.f9r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB25"); + state->u.f1.fld.f9r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB26"); + state->u.f1.fld.f9r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB27"); + state->u.f1.fld.f9r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB28"); + state->u.f1.fld.f9r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB29"); + state->u.f1.fld.f9r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB30"); + state->u.f1.fld.f9r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f9r1, "FB31"); + + // F9R2 bitfields. + state->u.f1.fld.f9r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB0"); + state->u.f1.fld.f9r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB1"); + state->u.f1.fld.f9r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB2"); + state->u.f1.fld.f9r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB3"); + state->u.f1.fld.f9r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB4"); + state->u.f1.fld.f9r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB5"); + state->u.f1.fld.f9r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB6"); + state->u.f1.fld.f9r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB7"); + state->u.f1.fld.f9r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB8"); + state->u.f1.fld.f9r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB9"); + state->u.f1.fld.f9r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB10"); + state->u.f1.fld.f9r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB11"); + state->u.f1.fld.f9r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB12"); + state->u.f1.fld.f9r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB13"); + state->u.f1.fld.f9r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB14"); + state->u.f1.fld.f9r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB15"); + state->u.f1.fld.f9r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB16"); + state->u.f1.fld.f9r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB17"); + state->u.f1.fld.f9r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB18"); + state->u.f1.fld.f9r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB19"); + state->u.f1.fld.f9r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB20"); + state->u.f1.fld.f9r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB21"); + state->u.f1.fld.f9r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB22"); + state->u.f1.fld.f9r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB23"); + state->u.f1.fld.f9r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB24"); + state->u.f1.fld.f9r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB25"); + state->u.f1.fld.f9r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB26"); + state->u.f1.fld.f9r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB27"); + state->u.f1.fld.f9r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB28"); + state->u.f1.fld.f9r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB29"); + state->u.f1.fld.f9r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB30"); + state->u.f1.fld.f9r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f9r2, "FB31"); + + // F10R1 bitfields. + state->u.f1.fld.f10r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB0"); + state->u.f1.fld.f10r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB1"); + state->u.f1.fld.f10r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB2"); + state->u.f1.fld.f10r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB3"); + state->u.f1.fld.f10r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB4"); + state->u.f1.fld.f10r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB5"); + state->u.f1.fld.f10r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB6"); + state->u.f1.fld.f10r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB7"); + state->u.f1.fld.f10r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB8"); + state->u.f1.fld.f10r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB9"); + state->u.f1.fld.f10r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB10"); + state->u.f1.fld.f10r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB11"); + state->u.f1.fld.f10r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB12"); + state->u.f1.fld.f10r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB13"); + state->u.f1.fld.f10r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB14"); + state->u.f1.fld.f10r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB15"); + state->u.f1.fld.f10r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB16"); + state->u.f1.fld.f10r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB17"); + state->u.f1.fld.f10r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB18"); + state->u.f1.fld.f10r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB19"); + state->u.f1.fld.f10r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB20"); + state->u.f1.fld.f10r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB21"); + state->u.f1.fld.f10r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB22"); + state->u.f1.fld.f10r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB23"); + state->u.f1.fld.f10r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB24"); + state->u.f1.fld.f10r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB25"); + state->u.f1.fld.f10r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB26"); + state->u.f1.fld.f10r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB27"); + state->u.f1.fld.f10r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB28"); + state->u.f1.fld.f10r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB29"); + state->u.f1.fld.f10r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB30"); + state->u.f1.fld.f10r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f10r1, "FB31"); + + // F10R2 bitfields. + state->u.f1.fld.f10r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB0"); + state->u.f1.fld.f10r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB1"); + state->u.f1.fld.f10r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB2"); + state->u.f1.fld.f10r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB3"); + state->u.f1.fld.f10r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB4"); + state->u.f1.fld.f10r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB5"); + state->u.f1.fld.f10r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB6"); + state->u.f1.fld.f10r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB7"); + state->u.f1.fld.f10r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB8"); + state->u.f1.fld.f10r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB9"); + state->u.f1.fld.f10r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB10"); + state->u.f1.fld.f10r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB11"); + state->u.f1.fld.f10r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB12"); + state->u.f1.fld.f10r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB13"); + state->u.f1.fld.f10r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB14"); + state->u.f1.fld.f10r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB15"); + state->u.f1.fld.f10r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB16"); + state->u.f1.fld.f10r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB17"); + state->u.f1.fld.f10r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB18"); + state->u.f1.fld.f10r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB19"); + state->u.f1.fld.f10r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB20"); + state->u.f1.fld.f10r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB21"); + state->u.f1.fld.f10r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB22"); + state->u.f1.fld.f10r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB23"); + state->u.f1.fld.f10r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB24"); + state->u.f1.fld.f10r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB25"); + state->u.f1.fld.f10r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB26"); + state->u.f1.fld.f10r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB27"); + state->u.f1.fld.f10r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB28"); + state->u.f1.fld.f10r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB29"); + state->u.f1.fld.f10r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB30"); + state->u.f1.fld.f10r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f10r2, "FB31"); + + // F11R1 bitfields. + state->u.f1.fld.f11r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB0"); + state->u.f1.fld.f11r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB1"); + state->u.f1.fld.f11r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB2"); + state->u.f1.fld.f11r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB3"); + state->u.f1.fld.f11r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB4"); + state->u.f1.fld.f11r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB5"); + state->u.f1.fld.f11r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB6"); + state->u.f1.fld.f11r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB7"); + state->u.f1.fld.f11r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB8"); + state->u.f1.fld.f11r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB9"); + state->u.f1.fld.f11r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB10"); + state->u.f1.fld.f11r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB11"); + state->u.f1.fld.f11r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB12"); + state->u.f1.fld.f11r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB13"); + state->u.f1.fld.f11r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB14"); + state->u.f1.fld.f11r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB15"); + state->u.f1.fld.f11r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB16"); + state->u.f1.fld.f11r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB17"); + state->u.f1.fld.f11r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB18"); + state->u.f1.fld.f11r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB19"); + state->u.f1.fld.f11r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB20"); + state->u.f1.fld.f11r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB21"); + state->u.f1.fld.f11r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB22"); + state->u.f1.fld.f11r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB23"); + state->u.f1.fld.f11r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB24"); + state->u.f1.fld.f11r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB25"); + state->u.f1.fld.f11r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB26"); + state->u.f1.fld.f11r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB27"); + state->u.f1.fld.f11r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB28"); + state->u.f1.fld.f11r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB29"); + state->u.f1.fld.f11r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB30"); + state->u.f1.fld.f11r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f11r1, "FB31"); + + // F11R2 bitfields. + state->u.f1.fld.f11r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB0"); + state->u.f1.fld.f11r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB1"); + state->u.f1.fld.f11r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB2"); + state->u.f1.fld.f11r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB3"); + state->u.f1.fld.f11r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB4"); + state->u.f1.fld.f11r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB5"); + state->u.f1.fld.f11r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB6"); + state->u.f1.fld.f11r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB7"); + state->u.f1.fld.f11r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB8"); + state->u.f1.fld.f11r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB9"); + state->u.f1.fld.f11r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB10"); + state->u.f1.fld.f11r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB11"); + state->u.f1.fld.f11r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB12"); + state->u.f1.fld.f11r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB13"); + state->u.f1.fld.f11r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB14"); + state->u.f1.fld.f11r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB15"); + state->u.f1.fld.f11r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB16"); + state->u.f1.fld.f11r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB17"); + state->u.f1.fld.f11r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB18"); + state->u.f1.fld.f11r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB19"); + state->u.f1.fld.f11r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB20"); + state->u.f1.fld.f11r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB21"); + state->u.f1.fld.f11r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB22"); + state->u.f1.fld.f11r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB23"); + state->u.f1.fld.f11r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB24"); + state->u.f1.fld.f11r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB25"); + state->u.f1.fld.f11r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB26"); + state->u.f1.fld.f11r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB27"); + state->u.f1.fld.f11r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB28"); + state->u.f1.fld.f11r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB29"); + state->u.f1.fld.f11r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB30"); + state->u.f1.fld.f11r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f11r2, "FB31"); + + // F12R1 bitfields. + state->u.f1.fld.f12r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB0"); + state->u.f1.fld.f12r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB1"); + state->u.f1.fld.f12r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB2"); + state->u.f1.fld.f12r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB3"); + state->u.f1.fld.f12r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB4"); + state->u.f1.fld.f12r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB5"); + state->u.f1.fld.f12r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB6"); + state->u.f1.fld.f12r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB7"); + state->u.f1.fld.f12r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB8"); + state->u.f1.fld.f12r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB9"); + state->u.f1.fld.f12r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB10"); + state->u.f1.fld.f12r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB11"); + state->u.f1.fld.f12r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB12"); + state->u.f1.fld.f12r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB13"); + state->u.f1.fld.f12r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB14"); + state->u.f1.fld.f12r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB15"); + state->u.f1.fld.f12r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB16"); + state->u.f1.fld.f12r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB17"); + state->u.f1.fld.f12r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB18"); + state->u.f1.fld.f12r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB19"); + state->u.f1.fld.f12r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB20"); + state->u.f1.fld.f12r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB21"); + state->u.f1.fld.f12r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB22"); + state->u.f1.fld.f12r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB23"); + state->u.f1.fld.f12r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB24"); + state->u.f1.fld.f12r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB25"); + state->u.f1.fld.f12r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB26"); + state->u.f1.fld.f12r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB27"); + state->u.f1.fld.f12r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB28"); + state->u.f1.fld.f12r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB29"); + state->u.f1.fld.f12r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB30"); + state->u.f1.fld.f12r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f12r1, "FB31"); + + // F12R2 bitfields. + state->u.f1.fld.f12r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB0"); + state->u.f1.fld.f12r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB1"); + state->u.f1.fld.f12r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB2"); + state->u.f1.fld.f12r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB3"); + state->u.f1.fld.f12r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB4"); + state->u.f1.fld.f12r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB5"); + state->u.f1.fld.f12r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB6"); + state->u.f1.fld.f12r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB7"); + state->u.f1.fld.f12r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB8"); + state->u.f1.fld.f12r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB9"); + state->u.f1.fld.f12r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB10"); + state->u.f1.fld.f12r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB11"); + state->u.f1.fld.f12r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB12"); + state->u.f1.fld.f12r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB13"); + state->u.f1.fld.f12r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB14"); + state->u.f1.fld.f12r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB15"); + state->u.f1.fld.f12r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB16"); + state->u.f1.fld.f12r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB17"); + state->u.f1.fld.f12r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB18"); + state->u.f1.fld.f12r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB19"); + state->u.f1.fld.f12r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB20"); + state->u.f1.fld.f12r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB21"); + state->u.f1.fld.f12r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB22"); + state->u.f1.fld.f12r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB23"); + state->u.f1.fld.f12r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB24"); + state->u.f1.fld.f12r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB25"); + state->u.f1.fld.f12r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB26"); + state->u.f1.fld.f12r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB27"); + state->u.f1.fld.f12r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB28"); + state->u.f1.fld.f12r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB29"); + state->u.f1.fld.f12r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB30"); + state->u.f1.fld.f12r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f12r2, "FB31"); + + // F13R1 bitfields. + state->u.f1.fld.f13r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB0"); + state->u.f1.fld.f13r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB1"); + state->u.f1.fld.f13r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB2"); + state->u.f1.fld.f13r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB3"); + state->u.f1.fld.f13r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB4"); + state->u.f1.fld.f13r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB5"); + state->u.f1.fld.f13r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB6"); + state->u.f1.fld.f13r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB7"); + state->u.f1.fld.f13r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB8"); + state->u.f1.fld.f13r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB9"); + state->u.f1.fld.f13r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB10"); + state->u.f1.fld.f13r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB11"); + state->u.f1.fld.f13r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB12"); + state->u.f1.fld.f13r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB13"); + state->u.f1.fld.f13r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB14"); + state->u.f1.fld.f13r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB15"); + state->u.f1.fld.f13r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB16"); + state->u.f1.fld.f13r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB17"); + state->u.f1.fld.f13r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB18"); + state->u.f1.fld.f13r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB19"); + state->u.f1.fld.f13r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB20"); + state->u.f1.fld.f13r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB21"); + state->u.f1.fld.f13r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB22"); + state->u.f1.fld.f13r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB23"); + state->u.f1.fld.f13r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB24"); + state->u.f1.fld.f13r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB25"); + state->u.f1.fld.f13r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB26"); + state->u.f1.fld.f13r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB27"); + state->u.f1.fld.f13r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB28"); + state->u.f1.fld.f13r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB29"); + state->u.f1.fld.f13r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB30"); + state->u.f1.fld.f13r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f13r1, "FB31"); + + // F13R2 bitfields. + state->u.f1.fld.f13r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB0"); + state->u.f1.fld.f13r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB1"); + state->u.f1.fld.f13r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB2"); + state->u.f1.fld.f13r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB3"); + state->u.f1.fld.f13r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB4"); + state->u.f1.fld.f13r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB5"); + state->u.f1.fld.f13r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB6"); + state->u.f1.fld.f13r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB7"); + state->u.f1.fld.f13r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB8"); + state->u.f1.fld.f13r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB9"); + state->u.f1.fld.f13r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB10"); + state->u.f1.fld.f13r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB11"); + state->u.f1.fld.f13r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB12"); + state->u.f1.fld.f13r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB13"); + state->u.f1.fld.f13r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB14"); + state->u.f1.fld.f13r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB15"); + state->u.f1.fld.f13r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB16"); + state->u.f1.fld.f13r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB17"); + state->u.f1.fld.f13r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB18"); + state->u.f1.fld.f13r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB19"); + state->u.f1.fld.f13r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB20"); + state->u.f1.fld.f13r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB21"); + state->u.f1.fld.f13r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB22"); + state->u.f1.fld.f13r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB23"); + state->u.f1.fld.f13r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB24"); + state->u.f1.fld.f13r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB25"); + state->u.f1.fld.f13r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB26"); + state->u.f1.fld.f13r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB27"); + state->u.f1.fld.f13r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB28"); + state->u.f1.fld.f13r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB29"); + state->u.f1.fld.f13r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB30"); + state->u.f1.fld.f13r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f13r2, "FB31"); + + // F14R1 bitfields. + state->u.f1.fld.f14r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB0"); + state->u.f1.fld.f14r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB1"); + state->u.f1.fld.f14r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB2"); + state->u.f1.fld.f14r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB3"); + state->u.f1.fld.f14r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB4"); + state->u.f1.fld.f14r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB5"); + state->u.f1.fld.f14r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB6"); + state->u.f1.fld.f14r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB7"); + state->u.f1.fld.f14r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB8"); + state->u.f1.fld.f14r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB9"); + state->u.f1.fld.f14r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB10"); + state->u.f1.fld.f14r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB11"); + state->u.f1.fld.f14r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB12"); + state->u.f1.fld.f14r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB13"); + state->u.f1.fld.f14r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB14"); + state->u.f1.fld.f14r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB15"); + state->u.f1.fld.f14r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB16"); + state->u.f1.fld.f14r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB17"); + state->u.f1.fld.f14r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB18"); + state->u.f1.fld.f14r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB19"); + state->u.f1.fld.f14r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB20"); + state->u.f1.fld.f14r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB21"); + state->u.f1.fld.f14r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB22"); + state->u.f1.fld.f14r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB23"); + state->u.f1.fld.f14r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB24"); + state->u.f1.fld.f14r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB25"); + state->u.f1.fld.f14r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB26"); + state->u.f1.fld.f14r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB27"); + state->u.f1.fld.f14r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB28"); + state->u.f1.fld.f14r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB29"); + state->u.f1.fld.f14r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB30"); + state->u.f1.fld.f14r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f14r1, "FB31"); + + // F14R2 bitfields. + state->u.f1.fld.f14r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB0"); + state->u.f1.fld.f14r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB1"); + state->u.f1.fld.f14r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB2"); + state->u.f1.fld.f14r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB3"); + state->u.f1.fld.f14r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB4"); + state->u.f1.fld.f14r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB5"); + state->u.f1.fld.f14r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB6"); + state->u.f1.fld.f14r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB7"); + state->u.f1.fld.f14r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB8"); + state->u.f1.fld.f14r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB9"); + state->u.f1.fld.f14r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB10"); + state->u.f1.fld.f14r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB11"); + state->u.f1.fld.f14r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB12"); + state->u.f1.fld.f14r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB13"); + state->u.f1.fld.f14r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB14"); + state->u.f1.fld.f14r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB15"); + state->u.f1.fld.f14r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB16"); + state->u.f1.fld.f14r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB17"); + state->u.f1.fld.f14r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB18"); + state->u.f1.fld.f14r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB19"); + state->u.f1.fld.f14r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB20"); + state->u.f1.fld.f14r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB21"); + state->u.f1.fld.f14r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB22"); + state->u.f1.fld.f14r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB23"); + state->u.f1.fld.f14r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB24"); + state->u.f1.fld.f14r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB25"); + state->u.f1.fld.f14r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB26"); + state->u.f1.fld.f14r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB27"); + state->u.f1.fld.f14r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB28"); + state->u.f1.fld.f14r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB29"); + state->u.f1.fld.f14r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB30"); + state->u.f1.fld.f14r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f14r2, "FB31"); + + // F15R1 bitfields. + state->u.f1.fld.f15r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB0"); + state->u.f1.fld.f15r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB1"); + state->u.f1.fld.f15r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB2"); + state->u.f1.fld.f15r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB3"); + state->u.f1.fld.f15r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB4"); + state->u.f1.fld.f15r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB5"); + state->u.f1.fld.f15r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB6"); + state->u.f1.fld.f15r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB7"); + state->u.f1.fld.f15r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB8"); + state->u.f1.fld.f15r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB9"); + state->u.f1.fld.f15r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB10"); + state->u.f1.fld.f15r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB11"); + state->u.f1.fld.f15r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB12"); + state->u.f1.fld.f15r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB13"); + state->u.f1.fld.f15r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB14"); + state->u.f1.fld.f15r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB15"); + state->u.f1.fld.f15r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB16"); + state->u.f1.fld.f15r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB17"); + state->u.f1.fld.f15r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB18"); + state->u.f1.fld.f15r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB19"); + state->u.f1.fld.f15r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB20"); + state->u.f1.fld.f15r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB21"); + state->u.f1.fld.f15r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB22"); + state->u.f1.fld.f15r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB23"); + state->u.f1.fld.f15r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB24"); + state->u.f1.fld.f15r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB25"); + state->u.f1.fld.f15r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB26"); + state->u.f1.fld.f15r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB27"); + state->u.f1.fld.f15r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB28"); + state->u.f1.fld.f15r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB29"); + state->u.f1.fld.f15r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB30"); + state->u.f1.fld.f15r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f15r1, "FB31"); + + // F15R2 bitfields. + state->u.f1.fld.f15r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB0"); + state->u.f1.fld.f15r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB1"); + state->u.f1.fld.f15r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB2"); + state->u.f1.fld.f15r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB3"); + state->u.f1.fld.f15r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB4"); + state->u.f1.fld.f15r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB5"); + state->u.f1.fld.f15r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB6"); + state->u.f1.fld.f15r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB7"); + state->u.f1.fld.f15r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB8"); + state->u.f1.fld.f15r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB9"); + state->u.f1.fld.f15r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB10"); + state->u.f1.fld.f15r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB11"); + state->u.f1.fld.f15r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB12"); + state->u.f1.fld.f15r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB13"); + state->u.f1.fld.f15r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB14"); + state->u.f1.fld.f15r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB15"); + state->u.f1.fld.f15r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB16"); + state->u.f1.fld.f15r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB17"); + state->u.f1.fld.f15r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB18"); + state->u.f1.fld.f15r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB19"); + state->u.f1.fld.f15r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB20"); + state->u.f1.fld.f15r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB21"); + state->u.f1.fld.f15r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB22"); + state->u.f1.fld.f15r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB23"); + state->u.f1.fld.f15r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB24"); + state->u.f1.fld.f15r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB25"); + state->u.f1.fld.f15r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB26"); + state->u.f1.fld.f15r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB27"); + state->u.f1.fld.f15r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB28"); + state->u.f1.fld.f15r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB29"); + state->u.f1.fld.f15r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB30"); + state->u.f1.fld.f15r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f15r2, "FB31"); + + // F16R1 bitfields. + state->u.f1.fld.f16r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB0"); + state->u.f1.fld.f16r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB1"); + state->u.f1.fld.f16r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB2"); + state->u.f1.fld.f16r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB3"); + state->u.f1.fld.f16r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB4"); + state->u.f1.fld.f16r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB5"); + state->u.f1.fld.f16r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB6"); + state->u.f1.fld.f16r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB7"); + state->u.f1.fld.f16r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB8"); + state->u.f1.fld.f16r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB9"); + state->u.f1.fld.f16r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB10"); + state->u.f1.fld.f16r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB11"); + state->u.f1.fld.f16r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB12"); + state->u.f1.fld.f16r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB13"); + state->u.f1.fld.f16r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB14"); + state->u.f1.fld.f16r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB15"); + state->u.f1.fld.f16r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB16"); + state->u.f1.fld.f16r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB17"); + state->u.f1.fld.f16r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB18"); + state->u.f1.fld.f16r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB19"); + state->u.f1.fld.f16r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB20"); + state->u.f1.fld.f16r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB21"); + state->u.f1.fld.f16r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB22"); + state->u.f1.fld.f16r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB23"); + state->u.f1.fld.f16r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB24"); + state->u.f1.fld.f16r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB25"); + state->u.f1.fld.f16r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB26"); + state->u.f1.fld.f16r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB27"); + state->u.f1.fld.f16r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB28"); + state->u.f1.fld.f16r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB29"); + state->u.f1.fld.f16r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB30"); + state->u.f1.fld.f16r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f16r1, "FB31"); + + // F16R2 bitfields. + state->u.f1.fld.f16r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB0"); + state->u.f1.fld.f16r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB1"); + state->u.f1.fld.f16r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB2"); + state->u.f1.fld.f16r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB3"); + state->u.f1.fld.f16r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB4"); + state->u.f1.fld.f16r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB5"); + state->u.f1.fld.f16r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB6"); + state->u.f1.fld.f16r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB7"); + state->u.f1.fld.f16r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB8"); + state->u.f1.fld.f16r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB9"); + state->u.f1.fld.f16r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB10"); + state->u.f1.fld.f16r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB11"); + state->u.f1.fld.f16r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB12"); + state->u.f1.fld.f16r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB13"); + state->u.f1.fld.f16r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB14"); + state->u.f1.fld.f16r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB15"); + state->u.f1.fld.f16r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB16"); + state->u.f1.fld.f16r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB17"); + state->u.f1.fld.f16r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB18"); + state->u.f1.fld.f16r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB19"); + state->u.f1.fld.f16r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB20"); + state->u.f1.fld.f16r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB21"); + state->u.f1.fld.f16r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB22"); + state->u.f1.fld.f16r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB23"); + state->u.f1.fld.f16r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB24"); + state->u.f1.fld.f16r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB25"); + state->u.f1.fld.f16r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB26"); + state->u.f1.fld.f16r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB27"); + state->u.f1.fld.f16r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB28"); + state->u.f1.fld.f16r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB29"); + state->u.f1.fld.f16r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB30"); + state->u.f1.fld.f16r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f16r2, "FB31"); + + // F17R1 bitfields. + state->u.f1.fld.f17r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB0"); + state->u.f1.fld.f17r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB1"); + state->u.f1.fld.f17r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB2"); + state->u.f1.fld.f17r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB3"); + state->u.f1.fld.f17r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB4"); + state->u.f1.fld.f17r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB5"); + state->u.f1.fld.f17r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB6"); + state->u.f1.fld.f17r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB7"); + state->u.f1.fld.f17r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB8"); + state->u.f1.fld.f17r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB9"); + state->u.f1.fld.f17r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB10"); + state->u.f1.fld.f17r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB11"); + state->u.f1.fld.f17r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB12"); + state->u.f1.fld.f17r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB13"); + state->u.f1.fld.f17r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB14"); + state->u.f1.fld.f17r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB15"); + state->u.f1.fld.f17r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB16"); + state->u.f1.fld.f17r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB17"); + state->u.f1.fld.f17r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB18"); + state->u.f1.fld.f17r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB19"); + state->u.f1.fld.f17r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB20"); + state->u.f1.fld.f17r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB21"); + state->u.f1.fld.f17r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB22"); + state->u.f1.fld.f17r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB23"); + state->u.f1.fld.f17r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB24"); + state->u.f1.fld.f17r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB25"); + state->u.f1.fld.f17r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB26"); + state->u.f1.fld.f17r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB27"); + state->u.f1.fld.f17r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB28"); + state->u.f1.fld.f17r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB29"); + state->u.f1.fld.f17r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB30"); + state->u.f1.fld.f17r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f17r1, "FB31"); + + // F17R2 bitfields. + state->u.f1.fld.f17r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB0"); + state->u.f1.fld.f17r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB1"); + state->u.f1.fld.f17r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB2"); + state->u.f1.fld.f17r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB3"); + state->u.f1.fld.f17r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB4"); + state->u.f1.fld.f17r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB5"); + state->u.f1.fld.f17r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB6"); + state->u.f1.fld.f17r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB7"); + state->u.f1.fld.f17r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB8"); + state->u.f1.fld.f17r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB9"); + state->u.f1.fld.f17r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB10"); + state->u.f1.fld.f17r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB11"); + state->u.f1.fld.f17r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB12"); + state->u.f1.fld.f17r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB13"); + state->u.f1.fld.f17r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB14"); + state->u.f1.fld.f17r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB15"); + state->u.f1.fld.f17r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB16"); + state->u.f1.fld.f17r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB17"); + state->u.f1.fld.f17r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB18"); + state->u.f1.fld.f17r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB19"); + state->u.f1.fld.f17r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB20"); + state->u.f1.fld.f17r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB21"); + state->u.f1.fld.f17r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB22"); + state->u.f1.fld.f17r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB23"); + state->u.f1.fld.f17r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB24"); + state->u.f1.fld.f17r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB25"); + state->u.f1.fld.f17r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB26"); + state->u.f1.fld.f17r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB27"); + state->u.f1.fld.f17r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB28"); + state->u.f1.fld.f17r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB29"); + state->u.f1.fld.f17r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB30"); + state->u.f1.fld.f17r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f17r2, "FB31"); + + // F18R1 bitfields. + state->u.f1.fld.f18r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB0"); + state->u.f1.fld.f18r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB1"); + state->u.f1.fld.f18r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB2"); + state->u.f1.fld.f18r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB3"); + state->u.f1.fld.f18r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB4"); + state->u.f1.fld.f18r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB5"); + state->u.f1.fld.f18r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB6"); + state->u.f1.fld.f18r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB7"); + state->u.f1.fld.f18r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB8"); + state->u.f1.fld.f18r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB9"); + state->u.f1.fld.f18r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB10"); + state->u.f1.fld.f18r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB11"); + state->u.f1.fld.f18r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB12"); + state->u.f1.fld.f18r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB13"); + state->u.f1.fld.f18r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB14"); + state->u.f1.fld.f18r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB15"); + state->u.f1.fld.f18r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB16"); + state->u.f1.fld.f18r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB17"); + state->u.f1.fld.f18r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB18"); + state->u.f1.fld.f18r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB19"); + state->u.f1.fld.f18r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB20"); + state->u.f1.fld.f18r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB21"); + state->u.f1.fld.f18r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB22"); + state->u.f1.fld.f18r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB23"); + state->u.f1.fld.f18r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB24"); + state->u.f1.fld.f18r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB25"); + state->u.f1.fld.f18r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB26"); + state->u.f1.fld.f18r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB27"); + state->u.f1.fld.f18r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB28"); + state->u.f1.fld.f18r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB29"); + state->u.f1.fld.f18r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB30"); + state->u.f1.fld.f18r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f18r1, "FB31"); + + // F18R2 bitfields. + state->u.f1.fld.f18r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB0"); + state->u.f1.fld.f18r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB1"); + state->u.f1.fld.f18r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB2"); + state->u.f1.fld.f18r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB3"); + state->u.f1.fld.f18r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB4"); + state->u.f1.fld.f18r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB5"); + state->u.f1.fld.f18r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB6"); + state->u.f1.fld.f18r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB7"); + state->u.f1.fld.f18r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB8"); + state->u.f1.fld.f18r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB9"); + state->u.f1.fld.f18r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB10"); + state->u.f1.fld.f18r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB11"); + state->u.f1.fld.f18r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB12"); + state->u.f1.fld.f18r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB13"); + state->u.f1.fld.f18r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB14"); + state->u.f1.fld.f18r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB15"); + state->u.f1.fld.f18r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB16"); + state->u.f1.fld.f18r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB17"); + state->u.f1.fld.f18r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB18"); + state->u.f1.fld.f18r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB19"); + state->u.f1.fld.f18r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB20"); + state->u.f1.fld.f18r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB21"); + state->u.f1.fld.f18r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB22"); + state->u.f1.fld.f18r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB23"); + state->u.f1.fld.f18r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB24"); + state->u.f1.fld.f18r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB25"); + state->u.f1.fld.f18r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB26"); + state->u.f1.fld.f18r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB27"); + state->u.f1.fld.f18r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB28"); + state->u.f1.fld.f18r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB29"); + state->u.f1.fld.f18r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB30"); + state->u.f1.fld.f18r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f18r2, "FB31"); + + // F19R1 bitfields. + state->u.f1.fld.f19r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB0"); + state->u.f1.fld.f19r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB1"); + state->u.f1.fld.f19r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB2"); + state->u.f1.fld.f19r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB3"); + state->u.f1.fld.f19r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB4"); + state->u.f1.fld.f19r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB5"); + state->u.f1.fld.f19r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB6"); + state->u.f1.fld.f19r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB7"); + state->u.f1.fld.f19r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB8"); + state->u.f1.fld.f19r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB9"); + state->u.f1.fld.f19r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB10"); + state->u.f1.fld.f19r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB11"); + state->u.f1.fld.f19r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB12"); + state->u.f1.fld.f19r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB13"); + state->u.f1.fld.f19r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB14"); + state->u.f1.fld.f19r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB15"); + state->u.f1.fld.f19r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB16"); + state->u.f1.fld.f19r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB17"); + state->u.f1.fld.f19r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB18"); + state->u.f1.fld.f19r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB19"); + state->u.f1.fld.f19r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB20"); + state->u.f1.fld.f19r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB21"); + state->u.f1.fld.f19r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB22"); + state->u.f1.fld.f19r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB23"); + state->u.f1.fld.f19r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB24"); + state->u.f1.fld.f19r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB25"); + state->u.f1.fld.f19r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB26"); + state->u.f1.fld.f19r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB27"); + state->u.f1.fld.f19r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB28"); + state->u.f1.fld.f19r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB29"); + state->u.f1.fld.f19r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB30"); + state->u.f1.fld.f19r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f19r1, "FB31"); + + // F19R2 bitfields. + state->u.f1.fld.f19r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB0"); + state->u.f1.fld.f19r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB1"); + state->u.f1.fld.f19r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB2"); + state->u.f1.fld.f19r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB3"); + state->u.f1.fld.f19r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB4"); + state->u.f1.fld.f19r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB5"); + state->u.f1.fld.f19r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB6"); + state->u.f1.fld.f19r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB7"); + state->u.f1.fld.f19r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB8"); + state->u.f1.fld.f19r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB9"); + state->u.f1.fld.f19r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB10"); + state->u.f1.fld.f19r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB11"); + state->u.f1.fld.f19r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB12"); + state->u.f1.fld.f19r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB13"); + state->u.f1.fld.f19r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB14"); + state->u.f1.fld.f19r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB15"); + state->u.f1.fld.f19r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB16"); + state->u.f1.fld.f19r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB17"); + state->u.f1.fld.f19r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB18"); + state->u.f1.fld.f19r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB19"); + state->u.f1.fld.f19r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB20"); + state->u.f1.fld.f19r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB21"); + state->u.f1.fld.f19r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB22"); + state->u.f1.fld.f19r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB23"); + state->u.f1.fld.f19r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB24"); + state->u.f1.fld.f19r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB25"); + state->u.f1.fld.f19r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB26"); + state->u.f1.fld.f19r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB27"); + state->u.f1.fld.f19r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB28"); + state->u.f1.fld.f19r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB29"); + state->u.f1.fld.f19r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB30"); + state->u.f1.fld.f19r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f19r2, "FB31"); + + // F20R1 bitfields. + state->u.f1.fld.f20r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB0"); + state->u.f1.fld.f20r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB1"); + state->u.f1.fld.f20r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB2"); + state->u.f1.fld.f20r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB3"); + state->u.f1.fld.f20r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB4"); + state->u.f1.fld.f20r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB5"); + state->u.f1.fld.f20r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB6"); + state->u.f1.fld.f20r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB7"); + state->u.f1.fld.f20r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB8"); + state->u.f1.fld.f20r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB9"); + state->u.f1.fld.f20r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB10"); + state->u.f1.fld.f20r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB11"); + state->u.f1.fld.f20r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB12"); + state->u.f1.fld.f20r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB13"); + state->u.f1.fld.f20r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB14"); + state->u.f1.fld.f20r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB15"); + state->u.f1.fld.f20r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB16"); + state->u.f1.fld.f20r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB17"); + state->u.f1.fld.f20r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB18"); + state->u.f1.fld.f20r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB19"); + state->u.f1.fld.f20r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB20"); + state->u.f1.fld.f20r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB21"); + state->u.f1.fld.f20r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB22"); + state->u.f1.fld.f20r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB23"); + state->u.f1.fld.f20r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB24"); + state->u.f1.fld.f20r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB25"); + state->u.f1.fld.f20r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB26"); + state->u.f1.fld.f20r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB27"); + state->u.f1.fld.f20r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB28"); + state->u.f1.fld.f20r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB29"); + state->u.f1.fld.f20r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB30"); + state->u.f1.fld.f20r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f20r1, "FB31"); + + // F20R2 bitfields. + state->u.f1.fld.f20r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB0"); + state->u.f1.fld.f20r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB1"); + state->u.f1.fld.f20r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB2"); + state->u.f1.fld.f20r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB3"); + state->u.f1.fld.f20r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB4"); + state->u.f1.fld.f20r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB5"); + state->u.f1.fld.f20r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB6"); + state->u.f1.fld.f20r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB7"); + state->u.f1.fld.f20r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB8"); + state->u.f1.fld.f20r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB9"); + state->u.f1.fld.f20r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB10"); + state->u.f1.fld.f20r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB11"); + state->u.f1.fld.f20r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB12"); + state->u.f1.fld.f20r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB13"); + state->u.f1.fld.f20r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB14"); + state->u.f1.fld.f20r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB15"); + state->u.f1.fld.f20r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB16"); + state->u.f1.fld.f20r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB17"); + state->u.f1.fld.f20r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB18"); + state->u.f1.fld.f20r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB19"); + state->u.f1.fld.f20r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB20"); + state->u.f1.fld.f20r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB21"); + state->u.f1.fld.f20r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB22"); + state->u.f1.fld.f20r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB23"); + state->u.f1.fld.f20r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB24"); + state->u.f1.fld.f20r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB25"); + state->u.f1.fld.f20r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB26"); + state->u.f1.fld.f20r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB27"); + state->u.f1.fld.f20r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB28"); + state->u.f1.fld.f20r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB29"); + state->u.f1.fld.f20r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB30"); + state->u.f1.fld.f20r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f20r2, "FB31"); + + // F21R1 bitfields. + state->u.f1.fld.f21r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB0"); + state->u.f1.fld.f21r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB1"); + state->u.f1.fld.f21r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB2"); + state->u.f1.fld.f21r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB3"); + state->u.f1.fld.f21r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB4"); + state->u.f1.fld.f21r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB5"); + state->u.f1.fld.f21r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB6"); + state->u.f1.fld.f21r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB7"); + state->u.f1.fld.f21r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB8"); + state->u.f1.fld.f21r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB9"); + state->u.f1.fld.f21r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB10"); + state->u.f1.fld.f21r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB11"); + state->u.f1.fld.f21r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB12"); + state->u.f1.fld.f21r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB13"); + state->u.f1.fld.f21r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB14"); + state->u.f1.fld.f21r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB15"); + state->u.f1.fld.f21r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB16"); + state->u.f1.fld.f21r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB17"); + state->u.f1.fld.f21r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB18"); + state->u.f1.fld.f21r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB19"); + state->u.f1.fld.f21r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB20"); + state->u.f1.fld.f21r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB21"); + state->u.f1.fld.f21r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB22"); + state->u.f1.fld.f21r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB23"); + state->u.f1.fld.f21r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB24"); + state->u.f1.fld.f21r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB25"); + state->u.f1.fld.f21r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB26"); + state->u.f1.fld.f21r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB27"); + state->u.f1.fld.f21r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB28"); + state->u.f1.fld.f21r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB29"); + state->u.f1.fld.f21r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB30"); + state->u.f1.fld.f21r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f21r1, "FB31"); + + // F21R2 bitfields. + state->u.f1.fld.f21r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB0"); + state->u.f1.fld.f21r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB1"); + state->u.f1.fld.f21r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB2"); + state->u.f1.fld.f21r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB3"); + state->u.f1.fld.f21r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB4"); + state->u.f1.fld.f21r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB5"); + state->u.f1.fld.f21r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB6"); + state->u.f1.fld.f21r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB7"); + state->u.f1.fld.f21r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB8"); + state->u.f1.fld.f21r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB9"); + state->u.f1.fld.f21r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB10"); + state->u.f1.fld.f21r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB11"); + state->u.f1.fld.f21r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB12"); + state->u.f1.fld.f21r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB13"); + state->u.f1.fld.f21r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB14"); + state->u.f1.fld.f21r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB15"); + state->u.f1.fld.f21r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB16"); + state->u.f1.fld.f21r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB17"); + state->u.f1.fld.f21r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB18"); + state->u.f1.fld.f21r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB19"); + state->u.f1.fld.f21r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB20"); + state->u.f1.fld.f21r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB21"); + state->u.f1.fld.f21r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB22"); + state->u.f1.fld.f21r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB23"); + state->u.f1.fld.f21r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB24"); + state->u.f1.fld.f21r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB25"); + state->u.f1.fld.f21r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB26"); + state->u.f1.fld.f21r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB27"); + state->u.f1.fld.f21r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB28"); + state->u.f1.fld.f21r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB29"); + state->u.f1.fld.f21r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB30"); + state->u.f1.fld.f21r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f21r2, "FB31"); + + // F22R1 bitfields. + state->u.f1.fld.f22r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB0"); + state->u.f1.fld.f22r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB1"); + state->u.f1.fld.f22r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB2"); + state->u.f1.fld.f22r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB3"); + state->u.f1.fld.f22r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB4"); + state->u.f1.fld.f22r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB5"); + state->u.f1.fld.f22r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB6"); + state->u.f1.fld.f22r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB7"); + state->u.f1.fld.f22r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB8"); + state->u.f1.fld.f22r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB9"); + state->u.f1.fld.f22r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB10"); + state->u.f1.fld.f22r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB11"); + state->u.f1.fld.f22r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB12"); + state->u.f1.fld.f22r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB13"); + state->u.f1.fld.f22r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB14"); + state->u.f1.fld.f22r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB15"); + state->u.f1.fld.f22r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB16"); + state->u.f1.fld.f22r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB17"); + state->u.f1.fld.f22r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB18"); + state->u.f1.fld.f22r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB19"); + state->u.f1.fld.f22r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB20"); + state->u.f1.fld.f22r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB21"); + state->u.f1.fld.f22r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB22"); + state->u.f1.fld.f22r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB23"); + state->u.f1.fld.f22r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB24"); + state->u.f1.fld.f22r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB25"); + state->u.f1.fld.f22r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB26"); + state->u.f1.fld.f22r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB27"); + state->u.f1.fld.f22r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB28"); + state->u.f1.fld.f22r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB29"); + state->u.f1.fld.f22r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB30"); + state->u.f1.fld.f22r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f22r1, "FB31"); + + // F22R2 bitfields. + state->u.f1.fld.f22r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB0"); + state->u.f1.fld.f22r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB1"); + state->u.f1.fld.f22r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB2"); + state->u.f1.fld.f22r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB3"); + state->u.f1.fld.f22r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB4"); + state->u.f1.fld.f22r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB5"); + state->u.f1.fld.f22r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB6"); + state->u.f1.fld.f22r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB7"); + state->u.f1.fld.f22r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB8"); + state->u.f1.fld.f22r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB9"); + state->u.f1.fld.f22r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB10"); + state->u.f1.fld.f22r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB11"); + state->u.f1.fld.f22r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB12"); + state->u.f1.fld.f22r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB13"); + state->u.f1.fld.f22r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB14"); + state->u.f1.fld.f22r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB15"); + state->u.f1.fld.f22r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB16"); + state->u.f1.fld.f22r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB17"); + state->u.f1.fld.f22r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB18"); + state->u.f1.fld.f22r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB19"); + state->u.f1.fld.f22r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB20"); + state->u.f1.fld.f22r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB21"); + state->u.f1.fld.f22r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB22"); + state->u.f1.fld.f22r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB23"); + state->u.f1.fld.f22r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB24"); + state->u.f1.fld.f22r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB25"); + state->u.f1.fld.f22r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB26"); + state->u.f1.fld.f22r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB27"); + state->u.f1.fld.f22r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB28"); + state->u.f1.fld.f22r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB29"); + state->u.f1.fld.f22r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB30"); + state->u.f1.fld.f22r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f22r2, "FB31"); + + // F23R1 bitfields. + state->u.f1.fld.f23r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB0"); + state->u.f1.fld.f23r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB1"); + state->u.f1.fld.f23r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB2"); + state->u.f1.fld.f23r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB3"); + state->u.f1.fld.f23r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB4"); + state->u.f1.fld.f23r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB5"); + state->u.f1.fld.f23r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB6"); + state->u.f1.fld.f23r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB7"); + state->u.f1.fld.f23r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB8"); + state->u.f1.fld.f23r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB9"); + state->u.f1.fld.f23r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB10"); + state->u.f1.fld.f23r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB11"); + state->u.f1.fld.f23r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB12"); + state->u.f1.fld.f23r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB13"); + state->u.f1.fld.f23r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB14"); + state->u.f1.fld.f23r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB15"); + state->u.f1.fld.f23r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB16"); + state->u.f1.fld.f23r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB17"); + state->u.f1.fld.f23r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB18"); + state->u.f1.fld.f23r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB19"); + state->u.f1.fld.f23r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB20"); + state->u.f1.fld.f23r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB21"); + state->u.f1.fld.f23r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB22"); + state->u.f1.fld.f23r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB23"); + state->u.f1.fld.f23r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB24"); + state->u.f1.fld.f23r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB25"); + state->u.f1.fld.f23r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB26"); + state->u.f1.fld.f23r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB27"); + state->u.f1.fld.f23r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB28"); + state->u.f1.fld.f23r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB29"); + state->u.f1.fld.f23r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB30"); + state->u.f1.fld.f23r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f23r1, "FB31"); + + // F23R2 bitfields. + state->u.f1.fld.f23r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB0"); + state->u.f1.fld.f23r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB1"); + state->u.f1.fld.f23r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB2"); + state->u.f1.fld.f23r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB3"); + state->u.f1.fld.f23r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB4"); + state->u.f1.fld.f23r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB5"); + state->u.f1.fld.f23r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB6"); + state->u.f1.fld.f23r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB7"); + state->u.f1.fld.f23r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB8"); + state->u.f1.fld.f23r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB9"); + state->u.f1.fld.f23r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB10"); + state->u.f1.fld.f23r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB11"); + state->u.f1.fld.f23r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB12"); + state->u.f1.fld.f23r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB13"); + state->u.f1.fld.f23r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB14"); + state->u.f1.fld.f23r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB15"); + state->u.f1.fld.f23r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB16"); + state->u.f1.fld.f23r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB17"); + state->u.f1.fld.f23r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB18"); + state->u.f1.fld.f23r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB19"); + state->u.f1.fld.f23r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB20"); + state->u.f1.fld.f23r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB21"); + state->u.f1.fld.f23r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB22"); + state->u.f1.fld.f23r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB23"); + state->u.f1.fld.f23r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB24"); + state->u.f1.fld.f23r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB25"); + state->u.f1.fld.f23r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB26"); + state->u.f1.fld.f23r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB27"); + state->u.f1.fld.f23r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB28"); + state->u.f1.fld.f23r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB29"); + state->u.f1.fld.f23r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB30"); + state->u.f1.fld.f23r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f23r2, "FB31"); + + // F24R1 bitfields. + state->u.f1.fld.f24r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB0"); + state->u.f1.fld.f24r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB1"); + state->u.f1.fld.f24r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB2"); + state->u.f1.fld.f24r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB3"); + state->u.f1.fld.f24r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB4"); + state->u.f1.fld.f24r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB5"); + state->u.f1.fld.f24r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB6"); + state->u.f1.fld.f24r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB7"); + state->u.f1.fld.f24r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB8"); + state->u.f1.fld.f24r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB9"); + state->u.f1.fld.f24r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB10"); + state->u.f1.fld.f24r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB11"); + state->u.f1.fld.f24r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB12"); + state->u.f1.fld.f24r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB13"); + state->u.f1.fld.f24r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB14"); + state->u.f1.fld.f24r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB15"); + state->u.f1.fld.f24r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB16"); + state->u.f1.fld.f24r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB17"); + state->u.f1.fld.f24r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB18"); + state->u.f1.fld.f24r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB19"); + state->u.f1.fld.f24r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB20"); + state->u.f1.fld.f24r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB21"); + state->u.f1.fld.f24r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB22"); + state->u.f1.fld.f24r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB23"); + state->u.f1.fld.f24r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB24"); + state->u.f1.fld.f24r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB25"); + state->u.f1.fld.f24r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB26"); + state->u.f1.fld.f24r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB27"); + state->u.f1.fld.f24r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB28"); + state->u.f1.fld.f24r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB29"); + state->u.f1.fld.f24r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB30"); + state->u.f1.fld.f24r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f24r1, "FB31"); + + // F24R2 bitfields. + state->u.f1.fld.f24r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB0"); + state->u.f1.fld.f24r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB1"); + state->u.f1.fld.f24r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB2"); + state->u.f1.fld.f24r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB3"); + state->u.f1.fld.f24r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB4"); + state->u.f1.fld.f24r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB5"); + state->u.f1.fld.f24r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB6"); + state->u.f1.fld.f24r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB7"); + state->u.f1.fld.f24r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB8"); + state->u.f1.fld.f24r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB9"); + state->u.f1.fld.f24r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB10"); + state->u.f1.fld.f24r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB11"); + state->u.f1.fld.f24r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB12"); + state->u.f1.fld.f24r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB13"); + state->u.f1.fld.f24r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB14"); + state->u.f1.fld.f24r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB15"); + state->u.f1.fld.f24r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB16"); + state->u.f1.fld.f24r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB17"); + state->u.f1.fld.f24r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB18"); + state->u.f1.fld.f24r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB19"); + state->u.f1.fld.f24r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB20"); + state->u.f1.fld.f24r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB21"); + state->u.f1.fld.f24r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB22"); + state->u.f1.fld.f24r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB23"); + state->u.f1.fld.f24r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB24"); + state->u.f1.fld.f24r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB25"); + state->u.f1.fld.f24r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB26"); + state->u.f1.fld.f24r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB27"); + state->u.f1.fld.f24r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB28"); + state->u.f1.fld.f24r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB29"); + state->u.f1.fld.f24r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB30"); + state->u.f1.fld.f24r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f24r2, "FB31"); + + // F25R1 bitfields. + state->u.f1.fld.f25r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB0"); + state->u.f1.fld.f25r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB1"); + state->u.f1.fld.f25r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB2"); + state->u.f1.fld.f25r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB3"); + state->u.f1.fld.f25r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB4"); + state->u.f1.fld.f25r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB5"); + state->u.f1.fld.f25r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB6"); + state->u.f1.fld.f25r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB7"); + state->u.f1.fld.f25r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB8"); + state->u.f1.fld.f25r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB9"); + state->u.f1.fld.f25r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB10"); + state->u.f1.fld.f25r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB11"); + state->u.f1.fld.f25r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB12"); + state->u.f1.fld.f25r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB13"); + state->u.f1.fld.f25r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB14"); + state->u.f1.fld.f25r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB15"); + state->u.f1.fld.f25r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB16"); + state->u.f1.fld.f25r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB17"); + state->u.f1.fld.f25r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB18"); + state->u.f1.fld.f25r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB19"); + state->u.f1.fld.f25r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB20"); + state->u.f1.fld.f25r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB21"); + state->u.f1.fld.f25r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB22"); + state->u.f1.fld.f25r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB23"); + state->u.f1.fld.f25r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB24"); + state->u.f1.fld.f25r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB25"); + state->u.f1.fld.f25r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB26"); + state->u.f1.fld.f25r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB27"); + state->u.f1.fld.f25r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB28"); + state->u.f1.fld.f25r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB29"); + state->u.f1.fld.f25r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB30"); + state->u.f1.fld.f25r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f25r1, "FB31"); + + // F25R2 bitfields. + state->u.f1.fld.f25r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB0"); + state->u.f1.fld.f25r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB1"); + state->u.f1.fld.f25r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB2"); + state->u.f1.fld.f25r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB3"); + state->u.f1.fld.f25r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB4"); + state->u.f1.fld.f25r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB5"); + state->u.f1.fld.f25r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB6"); + state->u.f1.fld.f25r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB7"); + state->u.f1.fld.f25r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB8"); + state->u.f1.fld.f25r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB9"); + state->u.f1.fld.f25r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB10"); + state->u.f1.fld.f25r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB11"); + state->u.f1.fld.f25r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB12"); + state->u.f1.fld.f25r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB13"); + state->u.f1.fld.f25r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB14"); + state->u.f1.fld.f25r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB15"); + state->u.f1.fld.f25r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB16"); + state->u.f1.fld.f25r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB17"); + state->u.f1.fld.f25r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB18"); + state->u.f1.fld.f25r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB19"); + state->u.f1.fld.f25r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB20"); + state->u.f1.fld.f25r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB21"); + state->u.f1.fld.f25r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB22"); + state->u.f1.fld.f25r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB23"); + state->u.f1.fld.f25r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB24"); + state->u.f1.fld.f25r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB25"); + state->u.f1.fld.f25r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB26"); + state->u.f1.fld.f25r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB27"); + state->u.f1.fld.f25r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB28"); + state->u.f1.fld.f25r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB29"); + state->u.f1.fld.f25r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB30"); + state->u.f1.fld.f25r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f25r2, "FB31"); + + // F26R1 bitfields. + state->u.f1.fld.f26r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB0"); + state->u.f1.fld.f26r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB1"); + state->u.f1.fld.f26r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB2"); + state->u.f1.fld.f26r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB3"); + state->u.f1.fld.f26r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB4"); + state->u.f1.fld.f26r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB5"); + state->u.f1.fld.f26r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB6"); + state->u.f1.fld.f26r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB7"); + state->u.f1.fld.f26r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB8"); + state->u.f1.fld.f26r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB9"); + state->u.f1.fld.f26r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB10"); + state->u.f1.fld.f26r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB11"); + state->u.f1.fld.f26r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB12"); + state->u.f1.fld.f26r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB13"); + state->u.f1.fld.f26r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB14"); + state->u.f1.fld.f26r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB15"); + state->u.f1.fld.f26r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB16"); + state->u.f1.fld.f26r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB17"); + state->u.f1.fld.f26r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB18"); + state->u.f1.fld.f26r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB19"); + state->u.f1.fld.f26r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB20"); + state->u.f1.fld.f26r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB21"); + state->u.f1.fld.f26r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB22"); + state->u.f1.fld.f26r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB23"); + state->u.f1.fld.f26r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB24"); + state->u.f1.fld.f26r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB25"); + state->u.f1.fld.f26r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB26"); + state->u.f1.fld.f26r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB27"); + state->u.f1.fld.f26r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB28"); + state->u.f1.fld.f26r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB29"); + state->u.f1.fld.f26r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB30"); + state->u.f1.fld.f26r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f26r1, "FB31"); + + // F26R2 bitfields. + state->u.f1.fld.f26r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB0"); + state->u.f1.fld.f26r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB1"); + state->u.f1.fld.f26r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB2"); + state->u.f1.fld.f26r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB3"); + state->u.f1.fld.f26r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB4"); + state->u.f1.fld.f26r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB5"); + state->u.f1.fld.f26r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB6"); + state->u.f1.fld.f26r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB7"); + state->u.f1.fld.f26r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB8"); + state->u.f1.fld.f26r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB9"); + state->u.f1.fld.f26r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB10"); + state->u.f1.fld.f26r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB11"); + state->u.f1.fld.f26r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB12"); + state->u.f1.fld.f26r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB13"); + state->u.f1.fld.f26r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB14"); + state->u.f1.fld.f26r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB15"); + state->u.f1.fld.f26r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB16"); + state->u.f1.fld.f26r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB17"); + state->u.f1.fld.f26r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB18"); + state->u.f1.fld.f26r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB19"); + state->u.f1.fld.f26r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB20"); + state->u.f1.fld.f26r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB21"); + state->u.f1.fld.f26r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB22"); + state->u.f1.fld.f26r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB23"); + state->u.f1.fld.f26r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB24"); + state->u.f1.fld.f26r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB25"); + state->u.f1.fld.f26r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB26"); + state->u.f1.fld.f26r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB27"); + state->u.f1.fld.f26r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB28"); + state->u.f1.fld.f26r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB29"); + state->u.f1.fld.f26r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB30"); + state->u.f1.fld.f26r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f26r2, "FB31"); + + // F27R1 bitfields. + state->u.f1.fld.f27r1.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB0"); + state->u.f1.fld.f27r1.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB1"); + state->u.f1.fld.f27r1.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB2"); + state->u.f1.fld.f27r1.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB3"); + state->u.f1.fld.f27r1.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB4"); + state->u.f1.fld.f27r1.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB5"); + state->u.f1.fld.f27r1.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB6"); + state->u.f1.fld.f27r1.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB7"); + state->u.f1.fld.f27r1.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB8"); + state->u.f1.fld.f27r1.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB9"); + state->u.f1.fld.f27r1.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB10"); + state->u.f1.fld.f27r1.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB11"); + state->u.f1.fld.f27r1.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB12"); + state->u.f1.fld.f27r1.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB13"); + state->u.f1.fld.f27r1.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB14"); + state->u.f1.fld.f27r1.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB15"); + state->u.f1.fld.f27r1.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB16"); + state->u.f1.fld.f27r1.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB17"); + state->u.f1.fld.f27r1.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB18"); + state->u.f1.fld.f27r1.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB19"); + state->u.f1.fld.f27r1.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB20"); + state->u.f1.fld.f27r1.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB21"); + state->u.f1.fld.f27r1.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB22"); + state->u.f1.fld.f27r1.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB23"); + state->u.f1.fld.f27r1.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB24"); + state->u.f1.fld.f27r1.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB25"); + state->u.f1.fld.f27r1.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB26"); + state->u.f1.fld.f27r1.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB27"); + state->u.f1.fld.f27r1.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB28"); + state->u.f1.fld.f27r1.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB29"); + state->u.f1.fld.f27r1.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB30"); + state->u.f1.fld.f27r1.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f27r1, "FB31"); + + // F27R2 bitfields. + state->u.f1.fld.f27r2.fb0 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB0"); + state->u.f1.fld.f27r2.fb1 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB1"); + state->u.f1.fld.f27r2.fb2 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB2"); + state->u.f1.fld.f27r2.fb3 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB3"); + state->u.f1.fld.f27r2.fb4 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB4"); + state->u.f1.fld.f27r2.fb5 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB5"); + state->u.f1.fld.f27r2.fb6 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB6"); + state->u.f1.fld.f27r2.fb7 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB7"); + state->u.f1.fld.f27r2.fb8 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB8"); + state->u.f1.fld.f27r2.fb9 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB9"); + state->u.f1.fld.f27r2.fb10 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB10"); + state->u.f1.fld.f27r2.fb11 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB11"); + state->u.f1.fld.f27r2.fb12 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB12"); + state->u.f1.fld.f27r2.fb13 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB13"); + state->u.f1.fld.f27r2.fb14 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB14"); + state->u.f1.fld.f27r2.fb15 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB15"); + state->u.f1.fld.f27r2.fb16 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB16"); + state->u.f1.fld.f27r2.fb17 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB17"); + state->u.f1.fld.f27r2.fb18 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB18"); + state->u.f1.fld.f27r2.fb19 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB19"); + state->u.f1.fld.f27r2.fb20 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB20"); + state->u.f1.fld.f27r2.fb21 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB21"); + state->u.f1.fld.f27r2.fb22 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB22"); + state->u.f1.fld.f27r2.fb23 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB23"); + state->u.f1.fld.f27r2.fb24 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB24"); + state->u.f1.fld.f27r2.fb25 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB25"); + state->u.f1.fld.f27r2.fb26 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB26"); + state->u.f1.fld.f27r2.fb27 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB27"); + state->u.f1.fld.f27r2.fb28 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB28"); + state->u.f1.fld.f27r2.fb29 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB29"); + state->u.f1.fld.f27r2.fb30 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB30"); + state->u.f1.fld.f27r2.fb31 = cm_object_get_child_by_name(state->u.f1.reg.f27r2, "FB31"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_can2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CAN2State *state = STM32_CAN2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_can2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CAN2State *state = STM32_CAN2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_can2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CAN2State *state = STM32_CAN2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_can2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CAN2State *state = STM32_CAN2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_can2_is_enabled(Object *obj) +{ + STM32CAN2State *state = STM32_CAN2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_can2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CAN2State *state = STM32_CAN2_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_can2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CAN2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CAN2State *state = STM32_CAN2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CAN2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_can2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_can2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_can2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_can2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_can2_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CAN2EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_can2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CAN2); +} + +static void stm32_can2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_can2_reset_callback; + dc->realize = stm32_can2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_can2_is_enabled; +} + +static const TypeInfo stm32_can2_type_info = { + .name = TYPE_STM32_CAN2, + .parent = TYPE_STM32_CAN2_PARENT, + .instance_init = stm32_can2_instance_init_callback, + .instance_size = sizeof(STM32CAN2State), + .class_init = stm32_can2_class_init_callback, + .class_size = sizeof(STM32CAN2Class) }; + +static void stm32_can2_register_types(void) +{ + type_register_static(&stm32_can2_type_info); +} + +type_init(stm32_can2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/can2.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/can2.h new file mode 100644 index 0000000000..eea8e8c6c8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/can2.h @@ -0,0 +1,2603 @@ +/* + * STM32 - CAN2 (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CAN2_H_ +#define STM32_CAN2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CAN2 DEVICE_PATH_STM32 "CAN2" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CAN2 TYPE_STM32_PREFIX "can2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CAN2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CAN2ParentClass; +typedef PeripheralState STM32CAN2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CAN2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CAN2Class, (obj), TYPE_STM32_CAN2) +#define STM32_CAN2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CAN2Class, (klass), TYPE_STM32_CAN2) + +typedef struct { + // private: + STM32CAN2ParentClass parent_class; + // public: + + // None, so far. +} STM32CAN2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CAN2_STATE(obj) \ + OBJECT_CHECK(STM32CAN2State, (obj), TYPE_STM32_CAN2) + +typedef struct { + // private: + STM32CAN2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 CAN2 (Controller area network) registers. + struct { + Object *can_mcr; // 0x0 (CAN_MCR) + Object *can_msr; // 0x4 (CAN_MSR) + Object *can_tsr; // 0x8 (CAN_TSR) + Object *can_rf0r; // 0xC (CAN_RF0R) + Object *can_rf1r; // 0x10 (CAN_RF1R) + Object *can_ier; // 0x14 (CAN_IER) + Object *can_esr; // 0x18 (CAN_ESR) + Object *can_btr; // 0x1C (CAN_BTR) + Object *can_ti0r; // 0x180 (CAN_TI0R) + Object *can_tdt0r; // 0x184 (CAN_TDT0R) + Object *can_tdl0r; // 0x188 (CAN_TDL0R) + Object *can_tdh0r; // 0x18C (CAN_TDH0R) + Object *can_ti1r; // 0x190 (CAN_TI1R) + Object *can_tdt1r; // 0x194 (CAN_TDT1R) + Object *can_tdl1r; // 0x198 (CAN_TDL1R) + Object *can_tdh1r; // 0x19C (CAN_TDH1R) + Object *can_ti2r; // 0x1A0 (CAN_TI2R) + Object *can_tdt2r; // 0x1A4 (CAN_TDT2R) + Object *can_tdl2r; // 0x1A8 (CAN_TDL2R) + Object *can_tdh2r; // 0x1AC (CAN_TDH2R) + Object *can_ri0r; // 0x1B0 (CAN_RI0R) + Object *can_rdt0r; // 0x1B4 (CAN_RDT0R) + Object *can_rdl0r; // 0x1B8 (CAN_RDL0R) + Object *can_rdh0r; // 0x1BC (CAN_RDH0R) + Object *can_ri1r; // 0x1C0 (CAN_RI1R) + Object *can_rdt1r; // 0x1C4 (CAN_RDT1R) + Object *can_rdl1r; // 0x1C8 (CAN_RDL1R) + Object *can_rdh1r; // 0x1CC (CAN_RDH1R) + Object *can_fmr; // 0x200 (CAN_FMR) + Object *can_fm1r; // 0x204 (CAN_FM1R) + Object *can_fs1r; // 0x20C (CAN_FS1R) + Object *can_ffa1r; // 0x214 (CAN_FFA1R) + Object *can_fa1r; // 0x21C (CAN_FA1R) + Object *f0r1; // 0x240 (Filter bank 0 register 1) + Object *f0r2; // 0x244 (Filter bank 0 register 2) + Object *f1r1; // 0x248 (Filter bank 1 register 1) + Object *f1r2; // 0x24C (Filter bank 1 register 2) + Object *f2r1; // 0x250 (Filter bank 2 register 1) + Object *f2r2; // 0x254 (Filter bank 2 register 2) + Object *f3r1; // 0x258 (Filter bank 3 register 1) + Object *f3r2; // 0x25C (Filter bank 3 register 2) + Object *f4r1; // 0x260 (Filter bank 4 register 1) + Object *f4r2; // 0x264 (Filter bank 4 register 2) + Object *f5r1; // 0x268 (Filter bank 5 register 1) + Object *f5r2; // 0x26C (Filter bank 5 register 2) + Object *f6r1; // 0x270 (Filter bank 6 register 1) + Object *f6r2; // 0x274 (Filter bank 6 register 2) + Object *f7r1; // 0x278 (Filter bank 7 register 1) + Object *f7r2; // 0x27C (Filter bank 7 register 2) + Object *f8r1; // 0x280 (Filter bank 8 register 1) + Object *f8r2; // 0x284 (Filter bank 8 register 2) + Object *f9r1; // 0x288 (Filter bank 9 register 1) + Object *f9r2; // 0x28C (Filter bank 9 register 2) + Object *f10r1; // 0x290 (Filter bank 10 register 1) + Object *f10r2; // 0x294 (Filter bank 10 register 2) + Object *f11r1; // 0x298 (Filter bank 11 register 1) + Object *f11r2; // 0x29C (Filter bank 11 register 2) + Object *f12r1; // 0x2A0 (Filter bank 4 register 1) + Object *f12r2; // 0x2A4 (Filter bank 12 register 2) + Object *f13r1; // 0x2A8 (Filter bank 13 register 1) + Object *f13r2; // 0x2AC (Filter bank 13 register 2) + Object *f14r1; // 0x2B0 (Filter bank 14 register 1) + Object *f14r2; // 0x2B4 (Filter bank 14 register 2) + Object *f15r1; // 0x2B8 (Filter bank 15 register 1) + Object *f15r2; // 0x2BC (Filter bank 15 register 2) + Object *f16r1; // 0x2C0 (Filter bank 16 register 1) + Object *f16r2; // 0x2C4 (Filter bank 16 register 2) + Object *f17r1; // 0x2C8 (Filter bank 17 register 1) + Object *f17r2; // 0x2CC (Filter bank 17 register 2) + Object *f18r1; // 0x2D0 (Filter bank 18 register 1) + Object *f18r2; // 0x2D4 (Filter bank 18 register 2) + Object *f19r1; // 0x2D8 (Filter bank 19 register 1) + Object *f19r2; // 0x2DC (Filter bank 19 register 2) + Object *f20r1; // 0x2E0 (Filter bank 20 register 1) + Object *f20r2; // 0x2E4 (Filter bank 20 register 2) + Object *f21r1; // 0x2E8 (Filter bank 21 register 1) + Object *f21r2; // 0x2EC (Filter bank 21 register 2) + Object *f22r1; // 0x2F0 (Filter bank 22 register 1) + Object *f22r2; // 0x2F4 (Filter bank 22 register 2) + Object *f23r1; // 0x2F8 (Filter bank 23 register 1) + Object *f23r2; // 0x2FC (Filter bank 23 register 2) + Object *f24r1; // 0x300 (Filter bank 24 register 1) + Object *f24r2; // 0x304 (Filter bank 24 register 2) + Object *f25r1; // 0x308 (Filter bank 25 register 1) + Object *f25r2; // 0x30C (Filter bank 25 register 2) + Object *f26r1; // 0x310 (Filter bank 26 register 1) + Object *f26r2; // 0x314 (Filter bank 26 register 2) + Object *f27r1; // 0x318 (Filter bank 27 register 1) + Object *f27r2; // 0x31C (Filter bank 27 register 2) + } reg; + + struct { + + // CAN_MCR (CAN_MCR) bitfields. + struct { + Object *inrq; // [0:0] INRQ + Object *sleep; // [1:1] SLEEP + Object *txfp; // [2:2] TXFP + Object *rflm; // [3:3] RFLM + Object *nart; // [4:4] NART + Object *awum; // [5:5] AWUM + Object *abom; // [6:6] ABOM + Object *ttcm; // [7:7] TTCM + Object *reset; // [15:15] RESET + Object *dbf; // [16:16] DBF + } can_mcr; + + // CAN_MSR (CAN_MSR) bitfields. + struct { + Object *inak; // [0:0] INAK + Object *slak; // [1:1] SLAK + Object *erri; // [2:2] ERRI + Object *wkui; // [3:3] WKUI + Object *slaki; // [4:4] SLAKI + Object *txm; // [8:8] TXM + Object *rxm; // [9:9] RXM + Object *samp; // [10:10] SAMP + Object *rx; // [11:11] RX + } can_msr; + + // CAN_TSR (CAN_TSR) bitfields. + struct { + Object *rqcp0; // [0:0] RQCP0 + Object *txok0; // [1:1] TXOK0 + Object *alst0; // [2:2] ALST0 + Object *terr0; // [3:3] TERR0 + Object *abrq0; // [7:7] ABRQ0 + Object *rqcp1; // [8:8] RQCP1 + Object *txok1; // [9:9] TXOK1 + Object *alst1; // [10:10] ALST1 + Object *terr1; // [11:11] TERR1 + Object *abrq1; // [15:15] ABRQ1 + Object *rqcp2; // [16:16] RQCP2 + Object *txok2; // [17:17] TXOK2 + Object *alst2; // [18:18] ALST2 + Object *terr2; // [19:19] TERR2 + Object *abrq2; // [23:23] ABRQ2 + Object *code; // [24:25] CODE + Object *tme0; // [26:26] Lowest priority flag for mailbox 0 + Object *tme1; // [27:27] Lowest priority flag for mailbox 1 + Object *tme2; // [28:28] Lowest priority flag for mailbox 2 + Object *low0; // [29:29] Lowest priority flag for mailbox 0 + Object *low1; // [30:30] Lowest priority flag for mailbox 1 + Object *low2; // [31:31] Lowest priority flag for mailbox 2 + } can_tsr; + + // CAN_RF0R (CAN_RF0R) bitfields. + struct { + Object *fmp0; // [0:1] FMP0 + Object *full0; // [3:3] FULL0 + Object *fovr0; // [4:4] FOVR0 + Object *rfom0; // [5:5] RFOM0 + } can_rf0r; + + // CAN_RF1R (CAN_RF1R) bitfields. + struct { + Object *fmp1; // [0:1] FMP1 + Object *full1; // [3:3] FULL1 + Object *fovr1; // [4:4] FOVR1 + Object *rfom1; // [5:5] RFOM1 + } can_rf1r; + + // CAN_IER (CAN_IER) bitfields. + struct { + Object *tmeie; // [0:0] TMEIE + Object *fmpie0; // [1:1] FMPIE0 + Object *ffie0; // [2:2] FFIE0 + Object *fovie0; // [3:3] FOVIE0 + Object *fmpie1; // [4:4] FMPIE1 + Object *ffie1; // [5:5] FFIE1 + Object *fovie1; // [6:6] FOVIE1 + Object *ewgie; // [8:8] EWGIE + Object *epvie; // [9:9] EPVIE + Object *bofie; // [10:10] BOFIE + Object *lecie; // [11:11] LECIE + Object *errie; // [15:15] ERRIE + Object *wkuie; // [16:16] WKUIE + Object *slkie; // [17:17] SLKIE + } can_ier; + + // CAN_ESR (CAN_ESR) bitfields. + struct { + Object *ewgf; // [0:0] EWGF + Object *epvf; // [1:1] EPVF + Object *boff; // [2:2] BOFF + Object *lec; // [4:6] LEC + Object *tec; // [16:23] TEC + Object *rec; // [24:31] REC + } can_esr; + + // CAN_BTR (CAN_BTR) bitfields. + struct { + Object *brp; // [0:9] BRP + Object *ts1; // [16:19] TS1 + Object *ts2; // [20:22] TS2 + Object *sjw; // [24:25] SJW + Object *lbkm; // [30:30] LBKM + Object *silm; // [31:31] SILM + } can_btr; + + // CAN_TI0R (CAN_TI0R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti0r; + + // CAN_TDT0R (CAN_TDT0R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt0r; + + // CAN_TDL0R (CAN_TDL0R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl0r; + + // CAN_TDH0R (CAN_TDH0R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh0r; + + // CAN_TI1R (CAN_TI1R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti1r; + + // CAN_TDT1R (CAN_TDT1R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt1r; + + // CAN_TDL1R (CAN_TDL1R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl1r; + + // CAN_TDH1R (CAN_TDH1R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh1r; + + // CAN_TI2R (CAN_TI2R) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ti2r; + + // CAN_TDT2R (CAN_TDT2R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } can_tdt2r; + + // CAN_TDL2R (CAN_TDL2R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_tdl2r; + + // CAN_TDH2R (CAN_TDH2R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_tdh2r; + + // CAN_RI0R (CAN_RI0R) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ri0r; + + // CAN_RDT0R (CAN_RDT0R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } can_rdt0r; + + // CAN_RDL0R (CAN_RDL0R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_rdl0r; + + // CAN_RDH0R (CAN_RDH0R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_rdh0r; + + // CAN_RI1R (CAN_RI1R) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } can_ri1r; + + // CAN_RDT1R (CAN_RDT1R) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } can_rdt1r; + + // CAN_RDL1R (CAN_RDL1R) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } can_rdl1r; + + // CAN_RDH1R (CAN_RDH1R) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } can_rdh1r; + + // CAN_FMR (CAN_FMR) bitfields. + struct { + Object *finit; // [0:0] FINIT + Object *can2sb; // [8:13] CAN2SB + } can_fmr; + + // CAN_FM1R (CAN_FM1R) bitfields. + struct { + Object *fbm0; // [0:0] Filter mode + Object *fbm1; // [1:1] Filter mode + Object *fbm2; // [2:2] Filter mode + Object *fbm3; // [3:3] Filter mode + Object *fbm4; // [4:4] Filter mode + Object *fbm5; // [5:5] Filter mode + Object *fbm6; // [6:6] Filter mode + Object *fbm7; // [7:7] Filter mode + Object *fbm8; // [8:8] Filter mode + Object *fbm9; // [9:9] Filter mode + Object *fbm10; // [10:10] Filter mode + Object *fbm11; // [11:11] Filter mode + Object *fbm12; // [12:12] Filter mode + Object *fbm13; // [13:13] Filter mode + Object *fbm14; // [14:14] Filter mode + Object *fbm15; // [15:15] Filter mode + Object *fbm16; // [16:16] Filter mode + Object *fbm17; // [17:17] Filter mode + Object *fbm18; // [18:18] Filter mode + Object *fbm19; // [19:19] Filter mode + Object *fbm20; // [20:20] Filter mode + Object *fbm21; // [21:21] Filter mode + Object *fbm22; // [22:22] Filter mode + Object *fbm23; // [23:23] Filter mode + Object *fbm24; // [24:24] Filter mode + Object *fbm25; // [25:25] Filter mode + Object *fbm26; // [26:26] Filter mode + Object *fbm27; // [27:27] Filter mode + } can_fm1r; + + // CAN_FS1R (CAN_FS1R) bitfields. + struct { + Object *fsc0; // [0:0] Filter scale configuration + Object *fsc1; // [1:1] Filter scale configuration + Object *fsc2; // [2:2] Filter scale configuration + Object *fsc3; // [3:3] Filter scale configuration + Object *fsc4; // [4:4] Filter scale configuration + Object *fsc5; // [5:5] Filter scale configuration + Object *fsc6; // [6:6] Filter scale configuration + Object *fsc7; // [7:7] Filter scale configuration + Object *fsc8; // [8:8] Filter scale configuration + Object *fsc9; // [9:9] Filter scale configuration + Object *fsc10; // [10:10] Filter scale configuration + Object *fsc11; // [11:11] Filter scale configuration + Object *fsc12; // [12:12] Filter scale configuration + Object *fsc13; // [13:13] Filter scale configuration + Object *fsc14; // [14:14] Filter scale configuration + Object *fsc15; // [15:15] Filter scale configuration + Object *fsc16; // [16:16] Filter scale configuration + Object *fsc17; // [17:17] Filter scale configuration + Object *fsc18; // [18:18] Filter scale configuration + Object *fsc19; // [19:19] Filter scale configuration + Object *fsc20; // [20:20] Filter scale configuration + Object *fsc21; // [21:21] Filter scale configuration + Object *fsc22; // [22:22] Filter scale configuration + Object *fsc23; // [23:23] Filter scale configuration + Object *fsc24; // [24:24] Filter scale configuration + Object *fsc25; // [25:25] Filter scale configuration + Object *fsc26; // [26:26] Filter scale configuration + Object *fsc27; // [27:27] Filter scale configuration + } can_fs1r; + + // CAN_FFA1R (CAN_FFA1R) bitfields. + struct { + Object *ffa0; // [0:0] Filter FIFO assignment for filter 0 + Object *ffa1; // [1:1] Filter FIFO assignment for filter 1 + Object *ffa2; // [2:2] Filter FIFO assignment for filter 2 + Object *ffa3; // [3:3] Filter FIFO assignment for filter 3 + Object *ffa4; // [4:4] Filter FIFO assignment for filter 4 + Object *ffa5; // [5:5] Filter FIFO assignment for filter 5 + Object *ffa6; // [6:6] Filter FIFO assignment for filter 6 + Object *ffa7; // [7:7] Filter FIFO assignment for filter 7 + Object *ffa8; // [8:8] Filter FIFO assignment for filter 8 + Object *ffa9; // [9:9] Filter FIFO assignment for filter 9 + Object *ffa10; // [10:10] Filter FIFO assignment for filter 10 + Object *ffa11; // [11:11] Filter FIFO assignment for filter 11 + Object *ffa12; // [12:12] Filter FIFO assignment for filter 12 + Object *ffa13; // [13:13] Filter FIFO assignment for filter 13 + Object *ffa14; // [14:14] Filter FIFO assignment for filter 14 + Object *ffa15; // [15:15] Filter FIFO assignment for filter 15 + Object *ffa16; // [16:16] Filter FIFO assignment for filter 16 + Object *ffa17; // [17:17] Filter FIFO assignment for filter 17 + Object *ffa18; // [18:18] Filter FIFO assignment for filter 18 + Object *ffa19; // [19:19] Filter FIFO assignment for filter 19 + Object *ffa20; // [20:20] Filter FIFO assignment for filter 20 + Object *ffa21; // [21:21] Filter FIFO assignment for filter 21 + Object *ffa22; // [22:22] Filter FIFO assignment for filter 22 + Object *ffa23; // [23:23] Filter FIFO assignment for filter 23 + Object *ffa24; // [24:24] Filter FIFO assignment for filter 24 + Object *ffa25; // [25:25] Filter FIFO assignment for filter 25 + Object *ffa26; // [26:26] Filter FIFO assignment for filter 26 + Object *ffa27; // [27:27] Filter FIFO assignment for filter 27 + } can_ffa1r; + + // CAN_FA1R (CAN_FA1R) bitfields. + struct { + Object *fact0; // [0:0] Filter active + Object *fact1; // [1:1] Filter active + Object *fact2; // [2:2] Filter active + Object *fact3; // [3:3] Filter active + Object *fact4; // [4:4] Filter active + Object *fact5; // [5:5] Filter active + Object *fact6; // [6:6] Filter active + Object *fact7; // [7:7] Filter active + Object *fact8; // [8:8] Filter active + Object *fact9; // [9:9] Filter active + Object *fact10; // [10:10] Filter active + Object *fact11; // [11:11] Filter active + Object *fact12; // [12:12] Filter active + Object *fact13; // [13:13] Filter active + Object *fact14; // [14:14] Filter active + Object *fact15; // [15:15] Filter active + Object *fact16; // [16:16] Filter active + Object *fact17; // [17:17] Filter active + Object *fact18; // [18:18] Filter active + Object *fact19; // [19:19] Filter active + Object *fact20; // [20:20] Filter active + Object *fact21; // [21:21] Filter active + Object *fact22; // [22:22] Filter active + Object *fact23; // [23:23] Filter active + Object *fact24; // [24:24] Filter active + Object *fact25; // [25:25] Filter active + Object *fact26; // [26:26] Filter active + Object *fact27; // [27:27] Filter active + } can_fa1r; + + // F0R1 (Filter bank 0 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r1; + + // F0R2 (Filter bank 0 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r2; + + // F1R1 (Filter bank 1 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r1; + + // F1R2 (Filter bank 1 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r2; + + // F2R1 (Filter bank 2 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r1; + + // F2R2 (Filter bank 2 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r2; + + // F3R1 (Filter bank 3 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r1; + + // F3R2 (Filter bank 3 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r2; + + // F4R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r1; + + // F4R2 (Filter bank 4 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r2; + + // F5R1 (Filter bank 5 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r1; + + // F5R2 (Filter bank 5 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r2; + + // F6R1 (Filter bank 6 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r1; + + // F6R2 (Filter bank 6 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r2; + + // F7R1 (Filter bank 7 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r1; + + // F7R2 (Filter bank 7 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r2; + + // F8R1 (Filter bank 8 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r1; + + // F8R2 (Filter bank 8 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r2; + + // F9R1 (Filter bank 9 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r1; + + // F9R2 (Filter bank 9 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r2; + + // F10R1 (Filter bank 10 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r1; + + // F10R2 (Filter bank 10 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r2; + + // F11R1 (Filter bank 11 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r1; + + // F11R2 (Filter bank 11 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r2; + + // F12R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r1; + + // F12R2 (Filter bank 12 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r2; + + // F13R1 (Filter bank 13 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r1; + + // F13R2 (Filter bank 13 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r2; + + // F14R1 (Filter bank 14 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r1; + + // F14R2 (Filter bank 14 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r2; + + // F15R1 (Filter bank 15 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r1; + + // F15R2 (Filter bank 15 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r2; + + // F16R1 (Filter bank 16 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r1; + + // F16R2 (Filter bank 16 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r2; + + // F17R1 (Filter bank 17 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r1; + + // F17R2 (Filter bank 17 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r2; + + // F18R1 (Filter bank 18 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r1; + + // F18R2 (Filter bank 18 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r2; + + // F19R1 (Filter bank 19 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r1; + + // F19R2 (Filter bank 19 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r2; + + // F20R1 (Filter bank 20 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r1; + + // F20R2 (Filter bank 20 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r2; + + // F21R1 (Filter bank 21 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r1; + + // F21R2 (Filter bank 21 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r2; + + // F22R1 (Filter bank 22 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r1; + + // F22R2 (Filter bank 22 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r2; + + // F23R1 (Filter bank 23 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r1; + + // F23R2 (Filter bank 23 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r2; + + // F24R1 (Filter bank 24 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r1; + + // F24R2 (Filter bank 24 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r2; + + // F25R1 (Filter bank 25 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r1; + + // F25R2 (Filter bank 25 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r2; + + // F26R1 (Filter bank 26 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r1; + + // F26R2 (Filter bank 26 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r2; + + // F27R1 (Filter bank 27 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r1; + + // F27R2 (Filter bank 27 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CAN2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CAN2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/crc.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/crc.c new file mode 100644 index 0000000000..27c6d645b4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/crc.c @@ -0,0 +1,246 @@ +/* + * STM32 - CRC (CRC calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_crc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // IDR bitfields. + state->u.f1.fld.idr.idr = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR"); + + // CR bitfields. + state->u.f1.fld.cr.reset = cm_object_get_child_by_name(state->u.f1.reg.cr, "RESET"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crc_is_enabled(Object *obj) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRCState *state = STM32_CRC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRCState *state = STM32_CRC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_crc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_crc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_crc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_crc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_crc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRC); +} + +static void stm32_crc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crc_reset_callback; + dc->realize = stm32_crc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crc_is_enabled; +} + +static const TypeInfo stm32_crc_type_info = { + .name = TYPE_STM32_CRC, + .parent = TYPE_STM32_CRC_PARENT, + .instance_init = stm32_crc_instance_init_callback, + .instance_size = sizeof(STM32CRCState), + .class_init = stm32_crc_class_init_callback, + .class_size = sizeof(STM32CRCClass) }; + +static void stm32_crc_register_types(void) +{ + type_register_static(&stm32_crc_type_info); +} + +type_init(stm32_crc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/crc.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/crc.h new file mode 100644 index 0000000000..c9b09529c6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/crc.h @@ -0,0 +1,117 @@ +/* + * STM32 - CRC (CRC calculation unit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRC_H_ +#define STM32_CRC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRC DEVICE_PATH_STM32 "CRC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRC TYPE_STM32_PREFIX "crc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRCParentClass; +typedef PeripheralState STM32CRCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRCClass, (obj), TYPE_STM32_CRC) +#define STM32_CRC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRCClass, (klass), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentClass parent_class; + // public: + + // None, so far. +} STM32CRCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRC_STATE(obj) \ + OBJECT_CHECK(STM32CRCState, (obj), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 CRC (CRC calculation unit) registers. + struct { + Object *dr; // 0x0 (Data register) + Object *idr; // 0x4 (Independent Data register) + Object *cr; // 0x8 (Control register) + } reg; + + struct { + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:31] Data Register + } dr; + + // IDR (Independent Data register) bitfields. + struct { + Object *idr; // [0:7] Independent Data register + } idr; + + // CR (Control register) bitfields. + struct { + Object *reset; // [0:0] Reset bit + } cr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/dac.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/dac.c new file mode 100644 index 0000000000..7b479f00f8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/dac.c @@ -0,0 +1,303 @@ +/* + * STM32 - DAC (Digital to analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_dac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.swtrigr = cm_object_get_child_by_name(obj, "SWTRIGR"); + state->u.f1.reg.dhr12r1 = cm_object_get_child_by_name(obj, "DHR12R1"); + state->u.f1.reg.dhr12l1 = cm_object_get_child_by_name(obj, "DHR12L1"); + state->u.f1.reg.dhr8r1 = cm_object_get_child_by_name(obj, "DHR8R1"); + state->u.f1.reg.dhr12r2 = cm_object_get_child_by_name(obj, "DHR12R2"); + state->u.f1.reg.dhr12l2 = cm_object_get_child_by_name(obj, "DHR12L2"); + state->u.f1.reg.dhr8r2 = cm_object_get_child_by_name(obj, "DHR8R2"); + state->u.f1.reg.dhr12rd = cm_object_get_child_by_name(obj, "DHR12RD"); + state->u.f1.reg.dhr12ld = cm_object_get_child_by_name(obj, "DHR12LD"); + state->u.f1.reg.dhr8rd = cm_object_get_child_by_name(obj, "DHR8RD"); + state->u.f1.reg.dor1 = cm_object_get_child_by_name(obj, "DOR1"); + state->u.f1.reg.dor2 = cm_object_get_child_by_name(obj, "DOR2"); + + + // CR bitfields. + state->u.f1.fld.cr.en1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "EN1"); + state->u.f1.fld.cr.boff1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "BOFF1"); + state->u.f1.fld.cr.ten1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TEN1"); + state->u.f1.fld.cr.tsel1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TSEL1"); + state->u.f1.fld.cr.wave1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "WAVE1"); + state->u.f1.fld.cr.mamp1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "MAMP1"); + state->u.f1.fld.cr.dmaen1 = cm_object_get_child_by_name(state->u.f1.reg.cr, "DMAEN1"); + state->u.f1.fld.cr.en2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "EN2"); + state->u.f1.fld.cr.boff2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "BOFF2"); + state->u.f1.fld.cr.ten2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TEN2"); + state->u.f1.fld.cr.tsel2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "TSEL2"); + state->u.f1.fld.cr.wave2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "WAVE2"); + state->u.f1.fld.cr.mamp2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "MAMP2"); + state->u.f1.fld.cr.dmaen2 = cm_object_get_child_by_name(state->u.f1.reg.cr, "DMAEN2"); + + // SWTRIGR bitfields. + state->u.f1.fld.swtrigr.swtrig1 = cm_object_get_child_by_name(state->u.f1.reg.swtrigr, "SWTRIG1"); + state->u.f1.fld.swtrigr.swtrig2 = cm_object_get_child_by_name(state->u.f1.reg.swtrigr, "SWTRIG2"); + + // DHR12R1 bitfields. + state->u.f1.fld.dhr12r1.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12r1, "DACC1DHR"); + + // DHR12L1 bitfields. + state->u.f1.fld.dhr12l1.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12l1, "DACC1DHR"); + + // DHR8R1 bitfields. + state->u.f1.fld.dhr8r1.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8r1, "DACC1DHR"); + + // DHR12R2 bitfields. + state->u.f1.fld.dhr12r2.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12r2, "DACC2DHR"); + + // DHR12L2 bitfields. + state->u.f1.fld.dhr12l2.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12l2, "DACC2DHR"); + + // DHR8R2 bitfields. + state->u.f1.fld.dhr8r2.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8r2, "DACC2DHR"); + + // DHR12RD bitfields. + state->u.f1.fld.dhr12rd.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12rd, "DACC1DHR"); + state->u.f1.fld.dhr12rd.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12rd, "DACC2DHR"); + + // DHR12LD bitfields. + state->u.f1.fld.dhr12ld.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12ld, "DACC1DHR"); + state->u.f1.fld.dhr12ld.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr12ld, "DACC2DHR"); + + // DHR8RD bitfields. + state->u.f1.fld.dhr8rd.dacc1dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8rd, "DACC1DHR"); + state->u.f1.fld.dhr8rd.dacc2dhr = cm_object_get_child_by_name(state->u.f1.reg.dhr8rd, "DACC2DHR"); + + // DOR1 bitfields. + state->u.f1.fld.dor1.dacc1dor = cm_object_get_child_by_name(state->u.f1.reg.dor1, "DACC1DOR"); + + // DOR2 bitfields. + state->u.f1.fld.dor2.dacc2dor = cm_object_get_child_by_name(state->u.f1.reg.dor2, "DACC2DOR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dac_is_enabled(Object *obj) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DACState *state = STM32_DAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DACState *state = STM32_DAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_dac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_dac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_dac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DAC); +} + +static void stm32_dac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dac_reset_callback; + dc->realize = stm32_dac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dac_is_enabled; +} + +static const TypeInfo stm32_dac_type_info = { + .name = TYPE_STM32_DAC, + .parent = TYPE_STM32_DAC_PARENT, + .instance_init = stm32_dac_instance_init_callback, + .instance_size = sizeof(STM32DACState), + .class_init = stm32_dac_class_init_callback, + .class_size = sizeof(STM32DACClass) }; + +static void stm32_dac_register_types(void) +{ + type_register_static(&stm32_dac_type_info); +} + +type_init(stm32_dac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/dac.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/dac.h new file mode 100644 index 0000000000..8c703fe1d1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/dac.h @@ -0,0 +1,194 @@ +/* + * STM32 - DAC (Digital to analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DAC_H_ +#define STM32_DAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DAC DEVICE_PATH_STM32 "DAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DAC TYPE_STM32_PREFIX "dac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DACParentClass; +typedef PeripheralState STM32DACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DACClass, (obj), TYPE_STM32_DAC) +#define STM32_DAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DACClass, (klass), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentClass parent_class; + // public: + + // None, so far. +} STM32DACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DAC_STATE(obj) \ + OBJECT_CHECK(STM32DACState, (obj), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 DAC (Digital to analog converter) registers. + struct { + Object *cr; // 0x0 (Control register (DAC_CR)) + Object *swtrigr; // 0x4 (DAC software trigger register (DAC_SWTRIGR)) + Object *dhr12r1; // 0x8 (DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)) + Object *dhr12l1; // 0xC (DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)) + Object *dhr8r1; // 0x10 (DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)) + Object *dhr12r2; // 0x14 (DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)) + Object *dhr12l2; // 0x18 (DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)) + Object *dhr8r2; // 0x1C (DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)) + Object *dhr12rd; // 0x20 (Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved) + Object *dhr12ld; // 0x24 (DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved) + Object *dhr8rd; // 0x28 (DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved) + Object *dor1; // 0x2C (DAC channel1 data output register (DAC_DOR1)) + Object *dor2; // 0x30 (DAC channel2 data output register (DAC_DOR2)) + } reg; + + struct { + + // CR (Control register (DAC_CR)) bitfields. + struct { + Object *en1; // [0:0] DAC channel1 enable + Object *boff1; // [1:1] DAC channel1 output buffer disable + Object *ten1; // [2:2] DAC channel1 trigger enable + Object *tsel1; // [3:5] DAC channel1 trigger selection + Object *wave1; // [6:7] DAC channel1 noise/triangle wave generation enable + Object *mamp1; // [8:11] DAC channel1 mask/amplitude selector + Object *dmaen1; // [12:12] DAC channel1 DMA enable + Object *en2; // [16:16] DAC channel2 enable + Object *boff2; // [17:17] DAC channel2 output buffer disable + Object *ten2; // [18:18] DAC channel2 trigger enable + Object *tsel2; // [19:21] DAC channel2 trigger selection + Object *wave2; // [22:23] DAC channel2 noise/triangle wave generation enable + Object *mamp2; // [24:27] DAC channel2 mask/amplitude selector + Object *dmaen2; // [28:28] DAC channel2 DMA enable + } cr; + + // SWTRIGR (DAC software trigger register (DAC_SWTRIGR)) bitfields. + struct { + Object *swtrig1; // [0:0] DAC channel1 software trigger + Object *swtrig2; // [1:1] DAC channel2 software trigger + } swtrigr; + + // DHR12R1 (DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + } dhr12r1; + + // DHR12L1 (DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + } dhr12l1; + + // DHR8R1 (DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + } dhr8r1; + + // DHR12R2 (DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)) bitfields. + struct { + Object *dacc2dhr; // [0:11] DAC channel2 12-bit right-aligned data + } dhr12r2; + + // DHR12L2 (DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)) bitfields. + struct { + Object *dacc2dhr; // [4:15] DAC channel2 12-bit left-aligned data + } dhr12l2; + + // DHR8R2 (DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)) bitfields. + struct { + Object *dacc2dhr; // [0:7] DAC channel2 8-bit right-aligned data + } dhr8r2; + + // DHR12RD (Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + Object *dacc2dhr; // [16:27] DAC channel2 12-bit right-aligned data + } dhr12rd; + + // DHR12LD (DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + Object *dacc2dhr; // [20:31] DAC channel2 12-bit right-aligned data + } dhr12ld; + + // DHR8RD (DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + Object *dacc2dhr; // [8:15] DAC channel2 8-bit right-aligned data + } dhr8rd; + + // DOR1 (DAC channel1 data output register (DAC_DOR1)) bitfields. + struct { + Object *dacc1dor; // [0:11] DAC channel1 data output + } dor1; + + // DOR2 (DAC channel2 data output register (DAC_DOR2)) bitfields. + struct { + Object *dacc2dor; // [0:11] DAC channel2 data output + } dor2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/dbg.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/dbg.c new file mode 100644 index 0000000000..19da2f81f5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/dbg.c @@ -0,0 +1,260 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_dbg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.idcode = cm_object_get_child_by_name(obj, "IDCODE"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + + + // IDCODE bitfields. + state->u.f1.fld.idcode.dev_id = cm_object_get_child_by_name(state->u.f1.reg.idcode, "DEV_ID"); + state->u.f1.fld.idcode.rev_id = cm_object_get_child_by_name(state->u.f1.reg.idcode, "REV_ID"); + + // CR bitfields. + state->u.f1.fld.cr.dbg_sleep = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_SLEEP"); + state->u.f1.fld.cr.dbg_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_STOP"); + state->u.f1.fld.cr.dbg_standby = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_STANDBY"); + state->u.f1.fld.cr.trace_ioen = cm_object_get_child_by_name(state->u.f1.reg.cr, "TRACE_IOEN"); + state->u.f1.fld.cr.trace_mode = cm_object_get_child_by_name(state->u.f1.reg.cr, "TRACE_MODE"); + state->u.f1.fld.cr.dbg_iwdg_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_IWDG_STOP"); + state->u.f1.fld.cr.dbg_wwdg_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_WWDG_STOP"); + state->u.f1.fld.cr.dbg_tim1_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM1_STOP"); + state->u.f1.fld.cr.dbg_tim2_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM2_STOP"); + state->u.f1.fld.cr.dbg_tim3_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM3_STOP"); + state->u.f1.fld.cr.dbg_tim4_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM4_STOP"); + state->u.f1.fld.cr.dbg_can1_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_CAN1_STOP"); + state->u.f1.fld.cr.dbg_i2c1_smbus_timeout = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_I2C1_SMBUS_TIMEOUT"); + state->u.f1.fld.cr.dbg_i2c2_smbus_timeout = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_I2C2_SMBUS_TIMEOUT"); + state->u.f1.fld.cr.dbg_tim5_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM5_STOP"); + state->u.f1.fld.cr.dbg_tim6_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM6_STOP"); + state->u.f1.fld.cr.dbg_tim7_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_TIM7_STOP"); + state->u.f1.fld.cr.dbg_can2_stop = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBG_CAN2_STOP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dbg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dbg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dbg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dbg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dbg_is_enabled(Object *obj) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dbg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DBGState *state = STM32_DBG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dbg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DBG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DBGState *state = STM32_DBG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DBG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_dbg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dbg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_dbg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dbg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_dbg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DBGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dbg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DBG); +} + +static void stm32_dbg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dbg_reset_callback; + dc->realize = stm32_dbg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dbg_is_enabled; +} + +static const TypeInfo stm32_dbg_type_info = { + .name = TYPE_STM32_DBG, + .parent = TYPE_STM32_DBG_PARENT, + .instance_init = stm32_dbg_instance_init_callback, + .instance_size = sizeof(STM32DBGState), + .class_init = stm32_dbg_class_init_callback, + .class_size = sizeof(STM32DBGClass) }; + +static void stm32_dbg_register_types(void) +{ + type_register_static(&stm32_dbg_type_info); +} + +type_init(stm32_dbg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/dbg.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/dbg.h new file mode 100644 index 0000000000..2ff96c5831 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/dbg.h @@ -0,0 +1,129 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DBG_H_ +#define STM32_DBG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DBG DEVICE_PATH_STM32 "DBG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DBG TYPE_STM32_PREFIX "dbg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DBG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DBGParentClass; +typedef PeripheralState STM32DBGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DBG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DBGClass, (obj), TYPE_STM32_DBG) +#define STM32_DBG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DBGClass, (klass), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentClass parent_class; + // public: + + // None, so far. +} STM32DBGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DBG_STATE(obj) \ + OBJECT_CHECK(STM32DBGState, (obj), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 DBG (Debug support) registers. + struct { + Object *idcode; // 0x0 (DBGMCU_IDCODE) + Object *cr; // 0x4 (DBGMCU_CR) + } reg; + + struct { + + // IDCODE (DBGMCU_IDCODE) bitfields. + struct { + Object *dev_id; // [0:11] DEV_ID + Object *rev_id; // [16:31] REV_ID + } idcode; + + // CR (DBGMCU_CR) bitfields. + struct { + Object *dbg_sleep; // [0:0] DBG_SLEEP + Object *dbg_stop; // [1:1] DBG_STOP + Object *dbg_standby; // [2:2] DBG_STANDBY + Object *trace_ioen; // [5:5] TRACE_IOEN + Object *trace_mode; // [6:7] TRACE_MODE + Object *dbg_iwdg_stop; // [8:8] DBG_IWDG_STOP + Object *dbg_wwdg_stop; // [9:9] DBG_WWDG_STOP + Object *dbg_tim1_stop; // [10:10] DBG_TIM1_STOP + Object *dbg_tim2_stop; // [11:11] DBG_TIM2_STOP + Object *dbg_tim3_stop; // [12:12] DBG_TIM3_STOP + Object *dbg_tim4_stop; // [13:13] DBG_TIM4_STOP + Object *dbg_can1_stop; // [14:14] DBG_CAN1_STOP + Object *dbg_i2c1_smbus_timeout; // [15:15] DBG_I2C1_SMBUS_TIMEOUT + Object *dbg_i2c2_smbus_timeout; // [16:16] DBG_I2C2_SMBUS_TIMEOUT + Object *dbg_tim5_stop; // [18:18] DBG_TIM5_STOP + Object *dbg_tim6_stop; // [19:19] DBG_TIM6_STOP + Object *dbg_tim7_stop; // [20:20] DBG_TIM7_STOP + Object *dbg_can2_stop; // [21:21] DBG_CAN2_STOP + } cr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DBGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DBG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/dma1.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/dma1.c new file mode 100644 index 0000000000..40765d6032 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/dma1.c @@ -0,0 +1,490 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f1.reg.ifcr = cm_object_get_child_by_name(obj, "IFCR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f1.reg.cndtr1 = cm_object_get_child_by_name(obj, "CNDTR1"); + state->u.f1.reg.cpar1 = cm_object_get_child_by_name(obj, "CPAR1"); + state->u.f1.reg.cmar1 = cm_object_get_child_by_name(obj, "CMAR1"); + state->u.f1.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f1.reg.cndtr2 = cm_object_get_child_by_name(obj, "CNDTR2"); + state->u.f1.reg.cpar2 = cm_object_get_child_by_name(obj, "CPAR2"); + state->u.f1.reg.cmar2 = cm_object_get_child_by_name(obj, "CMAR2"); + state->u.f1.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f1.reg.cndtr3 = cm_object_get_child_by_name(obj, "CNDTR3"); + state->u.f1.reg.cpar3 = cm_object_get_child_by_name(obj, "CPAR3"); + state->u.f1.reg.cmar3 = cm_object_get_child_by_name(obj, "CMAR3"); + state->u.f1.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f1.reg.cndtr4 = cm_object_get_child_by_name(obj, "CNDTR4"); + state->u.f1.reg.cpar4 = cm_object_get_child_by_name(obj, "CPAR4"); + state->u.f1.reg.cmar4 = cm_object_get_child_by_name(obj, "CMAR4"); + state->u.f1.reg.ccr5 = cm_object_get_child_by_name(obj, "CCR5"); + state->u.f1.reg.cndtr5 = cm_object_get_child_by_name(obj, "CNDTR5"); + state->u.f1.reg.cpar5 = cm_object_get_child_by_name(obj, "CPAR5"); + state->u.f1.reg.cmar5 = cm_object_get_child_by_name(obj, "CMAR5"); + state->u.f1.reg.ccr6 = cm_object_get_child_by_name(obj, "CCR6"); + state->u.f1.reg.cndtr6 = cm_object_get_child_by_name(obj, "CNDTR6"); + state->u.f1.reg.cpar6 = cm_object_get_child_by_name(obj, "CPAR6"); + state->u.f1.reg.cmar6 = cm_object_get_child_by_name(obj, "CMAR6"); + state->u.f1.reg.ccr7 = cm_object_get_child_by_name(obj, "CCR7"); + state->u.f1.reg.cndtr7 = cm_object_get_child_by_name(obj, "CNDTR7"); + state->u.f1.reg.cpar7 = cm_object_get_child_by_name(obj, "CPAR7"); + state->u.f1.reg.cmar7 = cm_object_get_child_by_name(obj, "CMAR7"); + + + // ISR bitfields. + state->u.f1.fld.isr.gif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF1"); + state->u.f1.fld.isr.tcif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF1"); + state->u.f1.fld.isr.htif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF1"); + state->u.f1.fld.isr.teif1 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF1"); + state->u.f1.fld.isr.gif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF2"); + state->u.f1.fld.isr.tcif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF2"); + state->u.f1.fld.isr.htif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF2"); + state->u.f1.fld.isr.teif2 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF2"); + state->u.f1.fld.isr.gif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF3"); + state->u.f1.fld.isr.tcif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF3"); + state->u.f1.fld.isr.htif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF3"); + state->u.f1.fld.isr.teif3 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF3"); + state->u.f1.fld.isr.gif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF4"); + state->u.f1.fld.isr.tcif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF4"); + state->u.f1.fld.isr.htif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF4"); + state->u.f1.fld.isr.teif4 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF4"); + state->u.f1.fld.isr.gif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF5"); + state->u.f1.fld.isr.tcif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF5"); + state->u.f1.fld.isr.htif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF5"); + state->u.f1.fld.isr.teif5 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF5"); + state->u.f1.fld.isr.gif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF6"); + state->u.f1.fld.isr.tcif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF6"); + state->u.f1.fld.isr.htif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF6"); + state->u.f1.fld.isr.teif6 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF6"); + state->u.f1.fld.isr.gif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "GIF7"); + state->u.f1.fld.isr.tcif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TCIF7"); + state->u.f1.fld.isr.htif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "HTIF7"); + state->u.f1.fld.isr.teif7 = cm_object_get_child_by_name(state->u.f1.reg.isr, "TEIF7"); + + // IFCR bitfields. + state->u.f1.fld.ifcr.cgif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF1"); + state->u.f1.fld.ifcr.ctcif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF1"); + state->u.f1.fld.ifcr.chtif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF1"); + state->u.f1.fld.ifcr.cteif1 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF1"); + state->u.f1.fld.ifcr.cgif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF2"); + state->u.f1.fld.ifcr.ctcif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF2"); + state->u.f1.fld.ifcr.chtif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF2"); + state->u.f1.fld.ifcr.cteif2 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF2"); + state->u.f1.fld.ifcr.cgif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF3"); + state->u.f1.fld.ifcr.ctcif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF3"); + state->u.f1.fld.ifcr.chtif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF3"); + state->u.f1.fld.ifcr.cteif3 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF3"); + state->u.f1.fld.ifcr.cgif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF4"); + state->u.f1.fld.ifcr.ctcif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF4"); + state->u.f1.fld.ifcr.chtif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF4"); + state->u.f1.fld.ifcr.cteif4 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF4"); + state->u.f1.fld.ifcr.cgif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF5"); + state->u.f1.fld.ifcr.ctcif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF5"); + state->u.f1.fld.ifcr.chtif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF5"); + state->u.f1.fld.ifcr.cteif5 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF5"); + state->u.f1.fld.ifcr.cgif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF6"); + state->u.f1.fld.ifcr.ctcif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF6"); + state->u.f1.fld.ifcr.chtif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF6"); + state->u.f1.fld.ifcr.cteif6 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF6"); + state->u.f1.fld.ifcr.cgif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CGIF7"); + state->u.f1.fld.ifcr.ctcif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTCIF7"); + state->u.f1.fld.ifcr.chtif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CHTIF7"); + state->u.f1.fld.ifcr.cteif7 = cm_object_get_child_by_name(state->u.f1.reg.ifcr, "CTEIF7"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.en = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "EN"); + state->u.f1.fld.ccr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "TCIE"); + state->u.f1.fld.ccr1.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "HTIE"); + state->u.f1.fld.ccr1.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "TEIE"); + state->u.f1.fld.ccr1.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "DIR"); + state->u.f1.fld.ccr1.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CIRC"); + state->u.f1.fld.ccr1.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "PINC"); + state->u.f1.fld.ccr1.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "MINC"); + state->u.f1.fld.ccr1.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "PSIZE"); + state->u.f1.fld.ccr1.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "MSIZE"); + state->u.f1.fld.ccr1.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "PL"); + state->u.f1.fld.ccr1.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "MEM2MEM"); + + // CNDTR1 bitfields. + state->u.f1.fld.cndtr1.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr1, "NDT"); + + // CPAR1 bitfields. + state->u.f1.fld.cpar1.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar1, "PA"); + + // CMAR1 bitfields. + state->u.f1.fld.cmar1.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar1, "MA"); + + // CCR2 bitfields. + state->u.f1.fld.ccr2.en = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "EN"); + state->u.f1.fld.ccr2.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "TCIE"); + state->u.f1.fld.ccr2.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "HTIE"); + state->u.f1.fld.ccr2.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "TEIE"); + state->u.f1.fld.ccr2.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "DIR"); + state->u.f1.fld.ccr2.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "CIRC"); + state->u.f1.fld.ccr2.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "PINC"); + state->u.f1.fld.ccr2.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "MINC"); + state->u.f1.fld.ccr2.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "PSIZE"); + state->u.f1.fld.ccr2.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "MSIZE"); + state->u.f1.fld.ccr2.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "PL"); + state->u.f1.fld.ccr2.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "MEM2MEM"); + + // CNDTR2 bitfields. + state->u.f1.fld.cndtr2.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr2, "NDT"); + + // CPAR2 bitfields. + state->u.f1.fld.cpar2.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar2, "PA"); + + // CMAR2 bitfields. + state->u.f1.fld.cmar2.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar2, "MA"); + + // CCR3 bitfields. + state->u.f1.fld.ccr3.en = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "EN"); + state->u.f1.fld.ccr3.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "TCIE"); + state->u.f1.fld.ccr3.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "HTIE"); + state->u.f1.fld.ccr3.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "TEIE"); + state->u.f1.fld.ccr3.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "DIR"); + state->u.f1.fld.ccr3.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "CIRC"); + state->u.f1.fld.ccr3.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "PINC"); + state->u.f1.fld.ccr3.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "MINC"); + state->u.f1.fld.ccr3.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "PSIZE"); + state->u.f1.fld.ccr3.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "MSIZE"); + state->u.f1.fld.ccr3.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "PL"); + state->u.f1.fld.ccr3.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "MEM2MEM"); + + // CNDTR3 bitfields. + state->u.f1.fld.cndtr3.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr3, "NDT"); + + // CPAR3 bitfields. + state->u.f1.fld.cpar3.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar3, "PA"); + + // CMAR3 bitfields. + state->u.f1.fld.cmar3.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar3, "MA"); + + // CCR4 bitfields. + state->u.f1.fld.ccr4.en = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "EN"); + state->u.f1.fld.ccr4.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "TCIE"); + state->u.f1.fld.ccr4.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "HTIE"); + state->u.f1.fld.ccr4.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "TEIE"); + state->u.f1.fld.ccr4.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "DIR"); + state->u.f1.fld.ccr4.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "CIRC"); + state->u.f1.fld.ccr4.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "PINC"); + state->u.f1.fld.ccr4.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "MINC"); + state->u.f1.fld.ccr4.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "PSIZE"); + state->u.f1.fld.ccr4.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "MSIZE"); + state->u.f1.fld.ccr4.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "PL"); + state->u.f1.fld.ccr4.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "MEM2MEM"); + + // CNDTR4 bitfields. + state->u.f1.fld.cndtr4.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr4, "NDT"); + + // CPAR4 bitfields. + state->u.f1.fld.cpar4.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar4, "PA"); + + // CMAR4 bitfields. + state->u.f1.fld.cmar4.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar4, "MA"); + + // CCR5 bitfields. + state->u.f1.fld.ccr5.en = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "EN"); + state->u.f1.fld.ccr5.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "TCIE"); + state->u.f1.fld.ccr5.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "HTIE"); + state->u.f1.fld.ccr5.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "TEIE"); + state->u.f1.fld.ccr5.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "DIR"); + state->u.f1.fld.ccr5.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "CIRC"); + state->u.f1.fld.ccr5.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "PINC"); + state->u.f1.fld.ccr5.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "MINC"); + state->u.f1.fld.ccr5.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "PSIZE"); + state->u.f1.fld.ccr5.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "MSIZE"); + state->u.f1.fld.ccr5.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "PL"); + state->u.f1.fld.ccr5.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr5, "MEM2MEM"); + + // CNDTR5 bitfields. + state->u.f1.fld.cndtr5.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr5, "NDT"); + + // CPAR5 bitfields. + state->u.f1.fld.cpar5.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar5, "PA"); + + // CMAR5 bitfields. + state->u.f1.fld.cmar5.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar5, "MA"); + + // CCR6 bitfields. + state->u.f1.fld.ccr6.en = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "EN"); + state->u.f1.fld.ccr6.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "TCIE"); + state->u.f1.fld.ccr6.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "HTIE"); + state->u.f1.fld.ccr6.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "TEIE"); + state->u.f1.fld.ccr6.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "DIR"); + state->u.f1.fld.ccr6.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "CIRC"); + state->u.f1.fld.ccr6.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "PINC"); + state->u.f1.fld.ccr6.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "MINC"); + state->u.f1.fld.ccr6.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "PSIZE"); + state->u.f1.fld.ccr6.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "MSIZE"); + state->u.f1.fld.ccr6.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "PL"); + state->u.f1.fld.ccr6.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr6, "MEM2MEM"); + + // CNDTR6 bitfields. + state->u.f1.fld.cndtr6.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr6, "NDT"); + + // CPAR6 bitfields. + state->u.f1.fld.cpar6.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar6, "PA"); + + // CMAR6 bitfields. + state->u.f1.fld.cmar6.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar6, "MA"); + + // CCR7 bitfields. + state->u.f1.fld.ccr7.en = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "EN"); + state->u.f1.fld.ccr7.tcie = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "TCIE"); + state->u.f1.fld.ccr7.htie = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "HTIE"); + state->u.f1.fld.ccr7.teie = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "TEIE"); + state->u.f1.fld.ccr7.dir = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "DIR"); + state->u.f1.fld.ccr7.circ = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "CIRC"); + state->u.f1.fld.ccr7.pinc = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "PINC"); + state->u.f1.fld.ccr7.minc = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "MINC"); + state->u.f1.fld.ccr7.psize = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "PSIZE"); + state->u.f1.fld.ccr7.msize = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "MSIZE"); + state->u.f1.fld.ccr7.pl = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "PL"); + state->u.f1.fld.ccr7.mem2mem = cm_object_get_child_by_name(state->u.f1.reg.ccr7, "MEM2MEM"); + + // CNDTR7 bitfields. + state->u.f1.fld.cndtr7.ndt = cm_object_get_child_by_name(state->u.f1.reg.cndtr7, "NDT"); + + // CPAR7 bitfields. + state->u.f1.fld.cpar7.pa = cm_object_get_child_by_name(state->u.f1.reg.cpar7, "PA"); + + // CMAR7 bitfields. + state->u.f1.fld.cmar7.ma = cm_object_get_child_by_name(state->u.f1.reg.cmar7, "MA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma_is_enabled(Object *obj) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMAState *state = STM32_DMA_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_DMA_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMAState *state = STM32_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA%dEN", + 1 + state->port_index - STM32_PORT_DMA1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA); +} + +static void stm32_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma_reset_callback; + dc->realize = stm32_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma_is_enabled; +} + +static const TypeInfo stm32_dma_type_info = { + .name = TYPE_STM32_DMA, + .parent = TYPE_STM32_DMA_PARENT, + .instance_init = stm32_dma_instance_init_callback, + .instance_size = sizeof(STM32DMAState), + .class_init = stm32_dma_class_init_callback, + .class_size = sizeof(STM32DMAClass) }; + +static void stm32_dma_register_types(void) +{ + type_register_static(&stm32_dma_type_info); +} + +type_init(stm32_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/dma1.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/dma1.h new file mode 100644 index 0000000000..bdc4d98c43 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/dma1.h @@ -0,0 +1,421 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA_H_ +#define STM32_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMA DEVICE_PATH_STM32 "DMA" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_DMA1, + STM32_PORT_DMA2, + STM32_PORT_DMA_UNDEFINED = 0xFF, +} stm32_dma_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMA TYPE_STM32_PREFIX "dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMAParentClass; +typedef PeripheralState STM32DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMAClass, (obj), TYPE_STM32_DMA) +#define STM32_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMAClass, (klass), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentClass parent_class; + // public: + + // None, so far. +} STM32DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA_STATE(obj) \ + OBJECT_CHECK(STM32DMAState, (obj), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_dma_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 DMA (DMA controller) registers. + struct { + Object *isr; // 0x0 (DMA interrupt status register (DMA_ISR)) + Object *ifcr; // 0x4 (DMA interrupt flag clear register (DMA_IFCR)) + Object *ccr1; // 0x8 (DMA channel configuration register (DMA_CCR)) + Object *cndtr1; // 0xC (DMA channel 1 number of data register) + Object *cpar1; // 0x10 (DMA channel 1 peripheral address register) + Object *cmar1; // 0x14 (DMA channel 1 memory address register) + Object *ccr2; // 0x1C (DMA channel configuration register (DMA_CCR)) + Object *cndtr2; // 0x20 (DMA channel 2 number of data register) + Object *cpar2; // 0x24 (DMA channel 2 peripheral address register) + Object *cmar2; // 0x28 (DMA channel 2 memory address register) + Object *ccr3; // 0x30 (DMA channel configuration register (DMA_CCR)) + Object *cndtr3; // 0x34 (DMA channel 3 number of data register) + Object *cpar3; // 0x38 (DMA channel 3 peripheral address register) + Object *cmar3; // 0x3C (DMA channel 3 memory address register) + Object *ccr4; // 0x44 (DMA channel configuration register (DMA_CCR)) + Object *cndtr4; // 0x48 (DMA channel 4 number of data register) + Object *cpar4; // 0x4C (DMA channel 4 peripheral address register) + Object *cmar4; // 0x50 (DMA channel 4 memory address register) + Object *ccr5; // 0x58 (DMA channel configuration register (DMA_CCR)) + Object *cndtr5; // 0x5C (DMA channel 5 number of data register) + Object *cpar5; // 0x60 (DMA channel 5 peripheral address register) + Object *cmar5; // 0x64 (DMA channel 5 memory address register) + Object *ccr6; // 0x6C (DMA channel configuration register (DMA_CCR)) + Object *cndtr6; // 0x70 (DMA channel 6 number of data register) + Object *cpar6; // 0x74 (DMA channel 6 peripheral address register) + Object *cmar6; // 0x78 (DMA channel 6 memory address register) + Object *ccr7; // 0x80 (DMA channel configuration register (DMA_CCR)) + Object *cndtr7; // 0x84 (DMA channel 7 number of data register) + Object *cpar7; // 0x88 (DMA channel 7 peripheral address register) + Object *cmar7; // 0x8C (DMA channel 7 memory address register) + } reg; + + struct { + + // ISR (DMA interrupt status register (DMA_ISR)) bitfields. + struct { + Object *gif1; // [0:0] Channel 1 Global interrupt flag + Object *tcif1; // [1:1] Channel 1 Transfer Complete flag + Object *htif1; // [2:2] Channel 1 Half Transfer Complete flag + Object *teif1; // [3:3] Channel 1 Transfer Error flag + Object *gif2; // [4:4] Channel 2 Global interrupt flag + Object *tcif2; // [5:5] Channel 2 Transfer Complete flag + Object *htif2; // [6:6] Channel 2 Half Transfer Complete flag + Object *teif2; // [7:7] Channel 2 Transfer Error flag + Object *gif3; // [8:8] Channel 3 Global interrupt flag + Object *tcif3; // [9:9] Channel 3 Transfer Complete flag + Object *htif3; // [10:10] Channel 3 Half Transfer Complete flag + Object *teif3; // [11:11] Channel 3 Transfer Error flag + Object *gif4; // [12:12] Channel 4 Global interrupt flag + Object *tcif4; // [13:13] Channel 4 Transfer Complete flag + Object *htif4; // [14:14] Channel 4 Half Transfer Complete flag + Object *teif4; // [15:15] Channel 4 Transfer Error flag + Object *gif5; // [16:16] Channel 5 Global interrupt flag + Object *tcif5; // [17:17] Channel 5 Transfer Complete flag + Object *htif5; // [18:18] Channel 5 Half Transfer Complete flag + Object *teif5; // [19:19] Channel 5 Transfer Error flag + Object *gif6; // [20:20] Channel 6 Global interrupt flag + Object *tcif6; // [21:21] Channel 6 Transfer Complete flag + Object *htif6; // [22:22] Channel 6 Half Transfer Complete flag + Object *teif6; // [23:23] Channel 6 Transfer Error flag + Object *gif7; // [24:24] Channel 7 Global interrupt flag + Object *tcif7; // [25:25] Channel 7 Transfer Complete flag + Object *htif7; // [26:26] Channel 7 Half Transfer Complete flag + Object *teif7; // [27:27] Channel 7 Transfer Error flag + } isr; + + // IFCR (DMA interrupt flag clear register (DMA_IFCR)) bitfields. + struct { + Object *cgif1; // [0:0] Channel 1 Global interrupt clear + Object *ctcif1; // [1:1] Channel 1 Transfer Complete clear + Object *chtif1; // [2:2] Channel 1 Half Transfer clear + Object *cteif1; // [3:3] Channel 1 Transfer Error clear + Object *cgif2; // [4:4] Channel 2 Global interrupt clear + Object *ctcif2; // [5:5] Channel 2 Transfer Complete clear + Object *chtif2; // [6:6] Channel 2 Half Transfer clear + Object *cteif2; // [7:7] Channel 2 Transfer Error clear + Object *cgif3; // [8:8] Channel 3 Global interrupt clear + Object *ctcif3; // [9:9] Channel 3 Transfer Complete clear + Object *chtif3; // [10:10] Channel 3 Half Transfer clear + Object *cteif3; // [11:11] Channel 3 Transfer Error clear + Object *cgif4; // [12:12] Channel 4 Global interrupt clear + Object *ctcif4; // [13:13] Channel 4 Transfer Complete clear + Object *chtif4; // [14:14] Channel 4 Half Transfer clear + Object *cteif4; // [15:15] Channel 4 Transfer Error clear + Object *cgif5; // [16:16] Channel 5 Global interrupt clear + Object *ctcif5; // [17:17] Channel 5 Transfer Complete clear + Object *chtif5; // [18:18] Channel 5 Half Transfer clear + Object *cteif5; // [19:19] Channel 5 Transfer Error clear + Object *cgif6; // [20:20] Channel 6 Global interrupt clear + Object *ctcif6; // [21:21] Channel 6 Transfer Complete clear + Object *chtif6; // [22:22] Channel 6 Half Transfer clear + Object *cteif6; // [23:23] Channel 6 Transfer Error clear + Object *cgif7; // [24:24] Channel 7 Global interrupt clear + Object *ctcif7; // [25:25] Channel 7 Transfer Complete clear + Object *chtif7; // [26:26] Channel 7 Half Transfer clear + Object *cteif7; // [27:27] Channel 7 Transfer Error clear + } ifcr; + + // CCR1 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr1; + + // CNDTR1 (DMA channel 1 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr1; + + // CPAR1 (DMA channel 1 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar1; + + // CMAR1 (DMA channel 1 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar1; + + // CCR2 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr2; + + // CNDTR2 (DMA channel 2 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr2; + + // CPAR2 (DMA channel 2 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar2; + + // CMAR2 (DMA channel 2 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar2; + + // CCR3 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr3; + + // CNDTR3 (DMA channel 3 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr3; + + // CPAR3 (DMA channel 3 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar3; + + // CMAR3 (DMA channel 3 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar3; + + // CCR4 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr4; + + // CNDTR4 (DMA channel 4 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr4; + + // CPAR4 (DMA channel 4 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar4; + + // CMAR4 (DMA channel 4 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar4; + + // CCR5 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr5; + + // CNDTR5 (DMA channel 5 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr5; + + // CPAR5 (DMA channel 5 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar5; + + // CMAR5 (DMA channel 5 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar5; + + // CCR6 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr6; + + // CNDTR6 (DMA channel 6 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr6; + + // CPAR6 (DMA channel 6 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar6; + + // CMAR6 (DMA channel 6 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar6; + + // CCR7 (DMA channel configuration register (DMA_CCR)) bitfields. + struct { + Object *en; // [0:0] Channel enable + Object *tcie; // [1:1] Transfer complete interrupt enable + Object *htie; // [2:2] Half Transfer interrupt enable + Object *teie; // [3:3] Transfer error interrupt enable + Object *dir; // [4:4] Data transfer direction + Object *circ; // [5:5] Circular mode + Object *pinc; // [6:6] Peripheral increment mode + Object *minc; // [7:7] Memory increment mode + Object *psize; // [8:9] Peripheral size + Object *msize; // [10:11] Memory size + Object *pl; // [12:13] Channel Priority level + Object *mem2mem; // [14:14] Memory to memory mode + } ccr7; + + // CNDTR7 (DMA channel 7 number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data to transfer + } cndtr7; + + // CPAR7 (DMA channel 7 peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } cpar7; + + // CMAR7 (DMA channel 7 memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } cmar7; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_dma.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_dma.c new file mode 100644 index 0000000000..7d0e2aac0f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_dma.c @@ -0,0 +1,343 @@ +/* + * STM32 - ETHERNET_DMA (Ethernet: DMA controller operation) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_ethernet_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.dmabmr = cm_object_get_child_by_name(obj, "DMABMR"); + state->u.f1.reg.dmatpdr = cm_object_get_child_by_name(obj, "DMATPDR"); + state->u.f1.reg.dmarpdr = cm_object_get_child_by_name(obj, "DMARPDR"); + state->u.f1.reg.dmardlar = cm_object_get_child_by_name(obj, "DMARDLAR"); + state->u.f1.reg.dmatdlar = cm_object_get_child_by_name(obj, "DMATDLAR"); + state->u.f1.reg.dmasr = cm_object_get_child_by_name(obj, "DMASR"); + state->u.f1.reg.dmaomr = cm_object_get_child_by_name(obj, "DMAOMR"); + state->u.f1.reg.dmaier = cm_object_get_child_by_name(obj, "DMAIER"); + state->u.f1.reg.dmamfbocr = cm_object_get_child_by_name(obj, "DMAMFBOCR"); + state->u.f1.reg.dmachtdr = cm_object_get_child_by_name(obj, "DMACHTDR"); + state->u.f1.reg.dmachrdr = cm_object_get_child_by_name(obj, "DMACHRDR"); + state->u.f1.reg.dmachtbar = cm_object_get_child_by_name(obj, "DMACHTBAR"); + state->u.f1.reg.dmachrbar = cm_object_get_child_by_name(obj, "DMACHRBAR"); + + + // DMABMR bitfields. + state->u.f1.fld.dmabmr.sr = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "SR"); + state->u.f1.fld.dmabmr.da = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "DA"); + state->u.f1.fld.dmabmr.dsl = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "DSL"); + state->u.f1.fld.dmabmr.pbl = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "PBL"); + state->u.f1.fld.dmabmr.rtpr = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "RTPR"); + state->u.f1.fld.dmabmr.fb = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "FB"); + state->u.f1.fld.dmabmr.rdp = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "RDP"); + state->u.f1.fld.dmabmr.usp = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "USP"); + state->u.f1.fld.dmabmr.fpm = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "FPM"); + state->u.f1.fld.dmabmr.aab = cm_object_get_child_by_name(state->u.f1.reg.dmabmr, "AAB"); + + // DMATPDR bitfields. + state->u.f1.fld.dmatpdr.tpd = cm_object_get_child_by_name(state->u.f1.reg.dmatpdr, "TPD"); + + // DMARPDR bitfields. + state->u.f1.fld.dmarpdr.rpd = cm_object_get_child_by_name(state->u.f1.reg.dmarpdr, "RPD"); + + // DMARDLAR bitfields. + state->u.f1.fld.dmardlar.srl = cm_object_get_child_by_name(state->u.f1.reg.dmardlar, "SRL"); + + // DMATDLAR bitfields. + state->u.f1.fld.dmatdlar.stl = cm_object_get_child_by_name(state->u.f1.reg.dmatdlar, "STL"); + + // DMASR bitfields. + state->u.f1.fld.dmasr.ts = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "TS"); + state->u.f1.fld.dmasr.tpss = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "TPSS"); + state->u.f1.fld.dmasr.tbus = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "TBUS"); + state->u.f1.fld.dmasr.tjts = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "TJTS"); + state->u.f1.fld.dmasr.ros = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "ROS"); + state->u.f1.fld.dmasr.tus = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "TUS"); + state->u.f1.fld.dmasr.rs = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "RS"); + state->u.f1.fld.dmasr.rbus = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "RBUS"); + state->u.f1.fld.dmasr.rpss = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "RPSS"); + state->u.f1.fld.dmasr.pwts = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "PWTS"); + state->u.f1.fld.dmasr.ets = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "ETS"); + state->u.f1.fld.dmasr.fbes = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "FBES"); + state->u.f1.fld.dmasr.ers = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "ERS"); + state->u.f1.fld.dmasr.ais = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "AIS"); + state->u.f1.fld.dmasr.nis = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "NIS"); + state->u.f1.fld.dmasr.rps = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "RPS"); + state->u.f1.fld.dmasr.tps = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "TPS"); + state->u.f1.fld.dmasr.ebs = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "EBS"); + state->u.f1.fld.dmasr.mmcs = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "MMCS"); + state->u.f1.fld.dmasr.pmts = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "PMTS"); + state->u.f1.fld.dmasr.tsts = cm_object_get_child_by_name(state->u.f1.reg.dmasr, "TSTS"); + + // DMAOMR bitfields. + state->u.f1.fld.dmaomr.sr = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "SR"); + state->u.f1.fld.dmaomr.osf = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "OSF"); + state->u.f1.fld.dmaomr.rtc = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "RTC"); + state->u.f1.fld.dmaomr.fugf = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "FUGF"); + state->u.f1.fld.dmaomr.fef = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "FEF"); + state->u.f1.fld.dmaomr.st = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "ST"); + state->u.f1.fld.dmaomr.ttc = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "TTC"); + state->u.f1.fld.dmaomr.ftf = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "FTF"); + state->u.f1.fld.dmaomr.tsf = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "TSF"); + state->u.f1.fld.dmaomr.dfrf = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "DFRF"); + state->u.f1.fld.dmaomr.rsf = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "RSF"); + state->u.f1.fld.dmaomr.dtcefd = cm_object_get_child_by_name(state->u.f1.reg.dmaomr, "DTCEFD"); + + // DMAIER bitfields. + state->u.f1.fld.dmaier.tie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "TIE"); + state->u.f1.fld.dmaier.tpsie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "TPSIE"); + state->u.f1.fld.dmaier.tbuie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "TBUIE"); + state->u.f1.fld.dmaier.tjtie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "TJTIE"); + state->u.f1.fld.dmaier.roie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "ROIE"); + state->u.f1.fld.dmaier.tuie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "TUIE"); + state->u.f1.fld.dmaier.rie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "RIE"); + state->u.f1.fld.dmaier.rbuie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "RBUIE"); + state->u.f1.fld.dmaier.rpsie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "RPSIE"); + state->u.f1.fld.dmaier.rwtie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "RWTIE"); + state->u.f1.fld.dmaier.etie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "ETIE"); + state->u.f1.fld.dmaier.fbeie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "FBEIE"); + state->u.f1.fld.dmaier.erie = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "ERIE"); + state->u.f1.fld.dmaier.aise = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "AISE"); + state->u.f1.fld.dmaier.nise = cm_object_get_child_by_name(state->u.f1.reg.dmaier, "NISE"); + + // DMAMFBOCR bitfields. + state->u.f1.fld.dmamfbocr.mfc = cm_object_get_child_by_name(state->u.f1.reg.dmamfbocr, "MFC"); + state->u.f1.fld.dmamfbocr.omfc = cm_object_get_child_by_name(state->u.f1.reg.dmamfbocr, "OMFC"); + state->u.f1.fld.dmamfbocr.mfa = cm_object_get_child_by_name(state->u.f1.reg.dmamfbocr, "MFA"); + state->u.f1.fld.dmamfbocr.ofoc = cm_object_get_child_by_name(state->u.f1.reg.dmamfbocr, "OFOC"); + + // DMACHTDR bitfields. + state->u.f1.fld.dmachtdr.htdap = cm_object_get_child_by_name(state->u.f1.reg.dmachtdr, "HTDAP"); + + // DMACHRDR bitfields. + state->u.f1.fld.dmachrdr.hrdap = cm_object_get_child_by_name(state->u.f1.reg.dmachrdr, "HRDAP"); + + // DMACHTBAR bitfields. + state->u.f1.fld.dmachtbar.htbap = cm_object_get_child_by_name(state->u.f1.reg.dmachtbar, "HTBAP"); + + // DMACHRBAR bitfields. + state->u.f1.fld.dmachrbar.hrbap = cm_object_get_child_by_name(state->u.f1.reg.dmachrbar, "HRBAP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_dma_is_enabled(Object *obj) +{ + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ETHERNET_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ETHERNET_DMAState *state = STM32_ETHERNET_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ETHERNET_DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_ethernet_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_ethernet_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_ethernet_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ETHERNET_DMAEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ETHERNET_DMA); +} + +static void stm32_ethernet_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_dma_reset_callback; + dc->realize = stm32_ethernet_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_dma_is_enabled; +} + +static const TypeInfo stm32_ethernet_dma_type_info = { + .name = TYPE_STM32_ETHERNET_DMA, + .parent = TYPE_STM32_ETHERNET_DMA_PARENT, + .instance_init = stm32_ethernet_dma_instance_init_callback, + .instance_size = sizeof(STM32ETHERNET_DMAState), + .class_init = stm32_ethernet_dma_class_init_callback, + .class_size = sizeof(STM32ETHERNET_DMAClass) }; + +static void stm32_ethernet_dma_register_types(void) +{ + type_register_static(&stm32_ethernet_dma_type_info); +} + +type_init(stm32_ethernet_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_dma.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_dma.h new file mode 100644 index 0000000000..331112c358 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_dma.h @@ -0,0 +1,234 @@ +/* + * STM32 - ETHERNET_DMA (Ethernet: DMA controller operation) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ETHERNET_DMA_H_ +#define STM32_ETHERNET_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ETHERNET_DMA DEVICE_PATH_STM32 "ETHERNET_DMA" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ETHERNET_DMA TYPE_STM32_PREFIX "ethernet_dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ETHERNET_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ETHERNET_DMAParentClass; +typedef PeripheralState STM32ETHERNET_DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ETHERNET_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ETHERNET_DMAClass, (obj), TYPE_STM32_ETHERNET_DMA) +#define STM32_ETHERNET_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ETHERNET_DMAClass, (klass), TYPE_STM32_ETHERNET_DMA) + +typedef struct { + // private: + STM32ETHERNET_DMAParentClass parent_class; + // public: + + // None, so far. +} STM32ETHERNET_DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ETHERNET_DMA_STATE(obj) \ + OBJECT_CHECK(STM32ETHERNET_DMAState, (obj), TYPE_STM32_ETHERNET_DMA) + +typedef struct { + // private: + STM32ETHERNET_DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ETHERNET_DMA (Ethernet: DMA controller operation) registers. + struct { + Object *dmabmr; // 0x0 (Ethernet DMA bus mode register) + Object *dmatpdr; // 0x4 (Ethernet DMA transmit poll demand register) + Object *dmarpdr; // 0x8 (EHERNET DMA receive poll demand register) + Object *dmardlar; // 0xC (Ethernet DMA receive descriptor list address register) + Object *dmatdlar; // 0x10 (Ethernet DMA transmit descriptor list address register) + Object *dmasr; // 0x14 (Ethernet DMA status register) + Object *dmaomr; // 0x18 (Ethernet DMA operation mode register) + Object *dmaier; // 0x1C (Ethernet DMA interrupt enable register) + Object *dmamfbocr; // 0x20 (Ethernet DMA missed frame and buffer overflow counter register) + Object *dmachtdr; // 0x48 (Ethernet DMA current host transmit descriptor register) + Object *dmachrdr; // 0x4C (Ethernet DMA current host receive descriptor register) + Object *dmachtbar; // 0x50 (Ethernet DMA current host transmit buffer address register) + Object *dmachrbar; // 0x54 (Ethernet DMA current host receive buffer address register) + } reg; + + struct { + + // DMABMR (Ethernet DMA bus mode register) bitfields. + struct { + Object *sr; // [0:0] Software reset + Object *da; // [1:1] DMA Arbitration + Object *dsl; // [2:6] Descriptor skip length + Object *pbl; // [8:13] Programmable burst length + Object *rtpr; // [14:15] Rx Tx priority ratio + Object *fb; // [16:16] Fixed burst + Object *rdp; // [17:22] Rx DMA PBL + Object *usp; // [23:23] Use separate PBL + Object *fpm; // [24:24] 4xPBL mode + Object *aab; // [25:25] Address-aligned beats + } dmabmr; + + // DMATPDR (Ethernet DMA transmit poll demand register) bitfields. + struct { + Object *tpd; // [0:31] Transmit poll demand + } dmatpdr; + + // DMARPDR (EHERNET DMA receive poll demand register) bitfields. + struct { + Object *rpd; // [0:31] Receive poll demand + } dmarpdr; + + // DMARDLAR (Ethernet DMA receive descriptor list address register) bitfields. + struct { + Object *srl; // [0:31] Start of receive list + } dmardlar; + + // DMATDLAR (Ethernet DMA transmit descriptor list address register) bitfields. + struct { + Object *stl; // [0:31] Start of transmit list + } dmatdlar; + + // DMASR (Ethernet DMA status register) bitfields. + struct { + Object *ts; // [0:0] Transmit status + Object *tpss; // [1:1] Transmit process stopped status + Object *tbus; // [2:2] Transmit buffer unavailable status + Object *tjts; // [3:3] Transmit jabber timeout status + Object *ros; // [4:4] Receive overflow status + Object *tus; // [5:5] Transmit underflow status + Object *rs; // [6:6] Receive status + Object *rbus; // [7:7] Receive buffer unavailable status + Object *rpss; // [8:8] Receive process stopped status + Object *pwts; // [9:9] Receive watchdog timeout status + Object *ets; // [10:10] Early transmit status + Object *fbes; // [13:13] Fatal bus error status + Object *ers; // [14:14] Early receive status + Object *ais; // [15:15] Abnormal interrupt summary + Object *nis; // [16:16] Normal interrupt summary + Object *rps; // [17:19] Receive process state + Object *tps; // [20:22] Transmit process state + Object *ebs; // [23:25] Error bits status + Object *mmcs; // [27:27] MMC status + Object *pmts; // [28:28] PMT status + Object *tsts; // [29:29] Time stamp trigger status + } dmasr; + + // DMAOMR (Ethernet DMA operation mode register) bitfields. + struct { + Object *sr; // [1:1] SR + Object *osf; // [2:2] OSF + Object *rtc; // [3:4] RTC + Object *fugf; // [6:6] FUGF + Object *fef; // [7:7] FEF + Object *st; // [13:13] ST + Object *ttc; // [14:16] TTC + Object *ftf; // [20:20] FTF + Object *tsf; // [21:21] TSF + Object *dfrf; // [24:24] DFRF + Object *rsf; // [25:25] RSF + Object *dtcefd; // [26:26] DTCEFD + } dmaomr; + + // DMAIER (Ethernet DMA interrupt enable register) bitfields. + struct { + Object *tie; // [0:0] Transmit interrupt enable + Object *tpsie; // [1:1] Transmit process stopped interrupt enable + Object *tbuie; // [2:2] Transmit buffer unavailable interrupt enable + Object *tjtie; // [3:3] Transmit jabber timeout interrupt enable + Object *roie; // [4:4] Overflow interrupt enable + Object *tuie; // [5:5] Underflow interrupt enable + Object *rie; // [6:6] Receive interrupt enable + Object *rbuie; // [7:7] Receive buffer unavailable interrupt enable + Object *rpsie; // [8:8] Receive process stopped interrupt enable + Object *rwtie; // [9:9] Receive watchdog timeout interrupt enable + Object *etie; // [10:10] Early transmit interrupt enable + Object *fbeie; // [13:13] Fatal bus error interrupt enable + Object *erie; // [14:14] Early receive interrupt enable + Object *aise; // [15:15] Abnormal interrupt summary enable + Object *nise; // [16:16] Normal interrupt summary enable + } dmaier; + + // DMAMFBOCR (Ethernet DMA missed frame and buffer overflow counter register) bitfields. + struct { + Object *mfc; // [0:15] Missed frames by the controller + Object *omfc; // [16:16] Overflow bit for missed frame counter + Object *mfa; // [17:27] Missed frames by the application + Object *ofoc; // [28:28] Overflow bit for FIFO overflow counter + } dmamfbocr; + + // DMACHTDR (Ethernet DMA current host transmit descriptor register) bitfields. + struct { + Object *htdap; // [0:31] Host transmit descriptor address pointer + } dmachtdr; + + // DMACHRDR (Ethernet DMA current host receive descriptor register) bitfields. + struct { + Object *hrdap; // [0:31] Host receive descriptor address pointer + } dmachrdr; + + // DMACHTBAR (Ethernet DMA current host transmit buffer address register) bitfields. + struct { + Object *htbap; // [0:31] Host transmit buffer address pointer + } dmachtbar; + + // DMACHRBAR (Ethernet DMA current host receive buffer address register) bitfields. + struct { + Object *hrbap; // [0:31] Host receive buffer address pointer + } dmachrbar; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ETHERNET_DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ETHERNET_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mac.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mac.c new file mode 100644 index 0000000000..5f590dfb56 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mac.c @@ -0,0 +1,369 @@ +/* + * STM32 - ETHERNET_MAC (Ethernet: media access control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_ethernet_mac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.maccr = cm_object_get_child_by_name(obj, "MACCR"); + state->u.f1.reg.macffr = cm_object_get_child_by_name(obj, "MACFFR"); + state->u.f1.reg.machthr = cm_object_get_child_by_name(obj, "MACHTHR"); + state->u.f1.reg.machtlr = cm_object_get_child_by_name(obj, "MACHTLR"); + state->u.f1.reg.macmiiar = cm_object_get_child_by_name(obj, "MACMIIAR"); + state->u.f1.reg.macmiidr = cm_object_get_child_by_name(obj, "MACMIIDR"); + state->u.f1.reg.macfcr = cm_object_get_child_by_name(obj, "MACFCR"); + state->u.f1.reg.macvlantr = cm_object_get_child_by_name(obj, "MACVLANTR"); + state->u.f1.reg.macrwuffr = cm_object_get_child_by_name(obj, "MACRWUFFR"); + state->u.f1.reg.macpmtcsr = cm_object_get_child_by_name(obj, "MACPMTCSR"); + state->u.f1.reg.macsr = cm_object_get_child_by_name(obj, "MACSR"); + state->u.f1.reg.macimr = cm_object_get_child_by_name(obj, "MACIMR"); + state->u.f1.reg.maca0hr = cm_object_get_child_by_name(obj, "MACA0HR"); + state->u.f1.reg.maca0lr = cm_object_get_child_by_name(obj, "MACA0LR"); + state->u.f1.reg.maca1hr = cm_object_get_child_by_name(obj, "MACA1HR"); + state->u.f1.reg.maca1lr = cm_object_get_child_by_name(obj, "MACA1LR"); + state->u.f1.reg.maca2hr = cm_object_get_child_by_name(obj, "MACA2HR"); + state->u.f1.reg.maca2lr = cm_object_get_child_by_name(obj, "MACA2LR"); + state->u.f1.reg.maca3hr = cm_object_get_child_by_name(obj, "MACA3HR"); + state->u.f1.reg.maca3lr = cm_object_get_child_by_name(obj, "MACA3LR"); + + + // MACCR bitfields. + state->u.f1.fld.maccr.re = cm_object_get_child_by_name(state->u.f1.reg.maccr, "RE"); + state->u.f1.fld.maccr.te = cm_object_get_child_by_name(state->u.f1.reg.maccr, "TE"); + state->u.f1.fld.maccr.dc = cm_object_get_child_by_name(state->u.f1.reg.maccr, "DC"); + state->u.f1.fld.maccr.bl = cm_object_get_child_by_name(state->u.f1.reg.maccr, "BL"); + state->u.f1.fld.maccr.apcs = cm_object_get_child_by_name(state->u.f1.reg.maccr, "APCS"); + state->u.f1.fld.maccr.rd = cm_object_get_child_by_name(state->u.f1.reg.maccr, "RD"); + state->u.f1.fld.maccr.ipco = cm_object_get_child_by_name(state->u.f1.reg.maccr, "IPCO"); + state->u.f1.fld.maccr.dm = cm_object_get_child_by_name(state->u.f1.reg.maccr, "DM"); + state->u.f1.fld.maccr.lm = cm_object_get_child_by_name(state->u.f1.reg.maccr, "LM"); + state->u.f1.fld.maccr.rod = cm_object_get_child_by_name(state->u.f1.reg.maccr, "ROD"); + state->u.f1.fld.maccr.fes = cm_object_get_child_by_name(state->u.f1.reg.maccr, "FES"); + state->u.f1.fld.maccr.csd = cm_object_get_child_by_name(state->u.f1.reg.maccr, "CSD"); + state->u.f1.fld.maccr.ifg = cm_object_get_child_by_name(state->u.f1.reg.maccr, "IFG"); + state->u.f1.fld.maccr.jd = cm_object_get_child_by_name(state->u.f1.reg.maccr, "JD"); + state->u.f1.fld.maccr.wd = cm_object_get_child_by_name(state->u.f1.reg.maccr, "WD"); + + // MACFFR bitfields. + state->u.f1.fld.macffr.pm = cm_object_get_child_by_name(state->u.f1.reg.macffr, "PM"); + state->u.f1.fld.macffr.hu = cm_object_get_child_by_name(state->u.f1.reg.macffr, "HU"); + state->u.f1.fld.macffr.hm = cm_object_get_child_by_name(state->u.f1.reg.macffr, "HM"); + state->u.f1.fld.macffr.daif = cm_object_get_child_by_name(state->u.f1.reg.macffr, "DAIF"); + state->u.f1.fld.macffr.pam = cm_object_get_child_by_name(state->u.f1.reg.macffr, "PAM"); + state->u.f1.fld.macffr.bfd = cm_object_get_child_by_name(state->u.f1.reg.macffr, "BFD"); + state->u.f1.fld.macffr.pcf = cm_object_get_child_by_name(state->u.f1.reg.macffr, "PCF"); + state->u.f1.fld.macffr.saif = cm_object_get_child_by_name(state->u.f1.reg.macffr, "SAIF"); + state->u.f1.fld.macffr.saf = cm_object_get_child_by_name(state->u.f1.reg.macffr, "SAF"); + state->u.f1.fld.macffr.hpf = cm_object_get_child_by_name(state->u.f1.reg.macffr, "HPF"); + state->u.f1.fld.macffr.ra = cm_object_get_child_by_name(state->u.f1.reg.macffr, "RA"); + + // MACHTHR bitfields. + state->u.f1.fld.machthr.hth = cm_object_get_child_by_name(state->u.f1.reg.machthr, "HTH"); + + // MACHTLR bitfields. + state->u.f1.fld.machtlr.htl = cm_object_get_child_by_name(state->u.f1.reg.machtlr, "HTL"); + + // MACMIIAR bitfields. + state->u.f1.fld.macmiiar.mb = cm_object_get_child_by_name(state->u.f1.reg.macmiiar, "MB"); + state->u.f1.fld.macmiiar.mw = cm_object_get_child_by_name(state->u.f1.reg.macmiiar, "MW"); + state->u.f1.fld.macmiiar.cr = cm_object_get_child_by_name(state->u.f1.reg.macmiiar, "CR"); + state->u.f1.fld.macmiiar.mr = cm_object_get_child_by_name(state->u.f1.reg.macmiiar, "MR"); + state->u.f1.fld.macmiiar.pa = cm_object_get_child_by_name(state->u.f1.reg.macmiiar, "PA"); + + // MACMIIDR bitfields. + state->u.f1.fld.macmiidr.md = cm_object_get_child_by_name(state->u.f1.reg.macmiidr, "MD"); + + // MACFCR bitfields. + state->u.f1.fld.macfcr.fcb_bpa = cm_object_get_child_by_name(state->u.f1.reg.macfcr, "FCB_BPA"); + state->u.f1.fld.macfcr.tfce = cm_object_get_child_by_name(state->u.f1.reg.macfcr, "TFCE"); + state->u.f1.fld.macfcr.rfce = cm_object_get_child_by_name(state->u.f1.reg.macfcr, "RFCE"); + state->u.f1.fld.macfcr.upfd = cm_object_get_child_by_name(state->u.f1.reg.macfcr, "UPFD"); + state->u.f1.fld.macfcr.plt = cm_object_get_child_by_name(state->u.f1.reg.macfcr, "PLT"); + state->u.f1.fld.macfcr.zqpd = cm_object_get_child_by_name(state->u.f1.reg.macfcr, "ZQPD"); + state->u.f1.fld.macfcr.pt = cm_object_get_child_by_name(state->u.f1.reg.macfcr, "PT"); + + // MACVLANTR bitfields. + state->u.f1.fld.macvlantr.vlanti = cm_object_get_child_by_name(state->u.f1.reg.macvlantr, "VLANTI"); + state->u.f1.fld.macvlantr.vlantc = cm_object_get_child_by_name(state->u.f1.reg.macvlantr, "VLANTC"); + + // MACRWUFFR bitfields. + + // MACPMTCSR bitfields. + state->u.f1.fld.macpmtcsr.pd = cm_object_get_child_by_name(state->u.f1.reg.macpmtcsr, "PD"); + state->u.f1.fld.macpmtcsr.mpe = cm_object_get_child_by_name(state->u.f1.reg.macpmtcsr, "MPE"); + state->u.f1.fld.macpmtcsr.wfe = cm_object_get_child_by_name(state->u.f1.reg.macpmtcsr, "WFE"); + state->u.f1.fld.macpmtcsr.mpr = cm_object_get_child_by_name(state->u.f1.reg.macpmtcsr, "MPR"); + state->u.f1.fld.macpmtcsr.wfr = cm_object_get_child_by_name(state->u.f1.reg.macpmtcsr, "WFR"); + state->u.f1.fld.macpmtcsr.gu = cm_object_get_child_by_name(state->u.f1.reg.macpmtcsr, "GU"); + state->u.f1.fld.macpmtcsr.wffrpr = cm_object_get_child_by_name(state->u.f1.reg.macpmtcsr, "WFFRPR"); + + // MACSR bitfields. + state->u.f1.fld.macsr.pmts = cm_object_get_child_by_name(state->u.f1.reg.macsr, "PMTS"); + state->u.f1.fld.macsr.mmcs = cm_object_get_child_by_name(state->u.f1.reg.macsr, "MMCS"); + state->u.f1.fld.macsr.mmcrs = cm_object_get_child_by_name(state->u.f1.reg.macsr, "MMCRS"); + state->u.f1.fld.macsr.mmcts = cm_object_get_child_by_name(state->u.f1.reg.macsr, "MMCTS"); + state->u.f1.fld.macsr.tsts = cm_object_get_child_by_name(state->u.f1.reg.macsr, "TSTS"); + + // MACIMR bitfields. + state->u.f1.fld.macimr.pmtim = cm_object_get_child_by_name(state->u.f1.reg.macimr, "PMTIM"); + state->u.f1.fld.macimr.tstim = cm_object_get_child_by_name(state->u.f1.reg.macimr, "TSTIM"); + + // MACA0HR bitfields. + state->u.f1.fld.maca0hr.maca0h = cm_object_get_child_by_name(state->u.f1.reg.maca0hr, "MACA0H"); + state->u.f1.fld.maca0hr.mo = cm_object_get_child_by_name(state->u.f1.reg.maca0hr, "MO"); + + // MACA0LR bitfields. + state->u.f1.fld.maca0lr.maca0l = cm_object_get_child_by_name(state->u.f1.reg.maca0lr, "MACA0L"); + + // MACA1HR bitfields. + state->u.f1.fld.maca1hr.maca1h = cm_object_get_child_by_name(state->u.f1.reg.maca1hr, "MACA1H"); + state->u.f1.fld.maca1hr.mbc = cm_object_get_child_by_name(state->u.f1.reg.maca1hr, "MBC"); + state->u.f1.fld.maca1hr.sa = cm_object_get_child_by_name(state->u.f1.reg.maca1hr, "SA"); + state->u.f1.fld.maca1hr.ae = cm_object_get_child_by_name(state->u.f1.reg.maca1hr, "AE"); + + // MACA1LR bitfields. + state->u.f1.fld.maca1lr.maca1l = cm_object_get_child_by_name(state->u.f1.reg.maca1lr, "MACA1L"); + + // MACA2HR bitfields. + state->u.f1.fld.maca2hr.eth_maca2hr = cm_object_get_child_by_name(state->u.f1.reg.maca2hr, "ETH_MACA2HR"); + state->u.f1.fld.maca2hr.mbc = cm_object_get_child_by_name(state->u.f1.reg.maca2hr, "MBC"); + state->u.f1.fld.maca2hr.sa = cm_object_get_child_by_name(state->u.f1.reg.maca2hr, "SA"); + state->u.f1.fld.maca2hr.ae = cm_object_get_child_by_name(state->u.f1.reg.maca2hr, "AE"); + + // MACA2LR bitfields. + state->u.f1.fld.maca2lr.maca2l = cm_object_get_child_by_name(state->u.f1.reg.maca2lr, "MACA2L"); + + // MACA3HR bitfields. + state->u.f1.fld.maca3hr.maca3h = cm_object_get_child_by_name(state->u.f1.reg.maca3hr, "MACA3H"); + state->u.f1.fld.maca3hr.mbc = cm_object_get_child_by_name(state->u.f1.reg.maca3hr, "MBC"); + state->u.f1.fld.maca3hr.sa = cm_object_get_child_by_name(state->u.f1.reg.maca3hr, "SA"); + state->u.f1.fld.maca3hr.ae = cm_object_get_child_by_name(state->u.f1.reg.maca3hr, "AE"); + + // MACA3LR bitfields. + state->u.f1.fld.maca3lr.mbca3l = cm_object_get_child_by_name(state->u.f1.reg.maca3lr, "MBCA3L"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_mac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_mac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_mac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_mac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_mac_is_enabled(Object *obj) +{ + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_mac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_mac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ETHERNET_MAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ETHERNET_MACState *state = STM32_ETHERNET_MAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ETHERNET_MAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_ethernet_mac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_mac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_ethernet_mac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_mac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_ethernet_mac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ETHERNET_MACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_mac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ETHERNET_MAC); +} + +static void stm32_ethernet_mac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_mac_reset_callback; + dc->realize = stm32_ethernet_mac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_mac_is_enabled; +} + +static const TypeInfo stm32_ethernet_mac_type_info = { + .name = TYPE_STM32_ETHERNET_MAC, + .parent = TYPE_STM32_ETHERNET_MAC_PARENT, + .instance_init = stm32_ethernet_mac_instance_init_callback, + .instance_size = sizeof(STM32ETHERNET_MACState), + .class_init = stm32_ethernet_mac_class_init_callback, + .class_size = sizeof(STM32ETHERNET_MACClass) }; + +static void stm32_ethernet_mac_register_types(void) +{ + type_register_static(&stm32_ethernet_mac_type_info); +} + +type_init(stm32_ethernet_mac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mac.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mac.h new file mode 100644 index 0000000000..ab8ba9d3cb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mac.h @@ -0,0 +1,274 @@ +/* + * STM32 - ETHERNET_MAC (Ethernet: media access control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ETHERNET_MAC_H_ +#define STM32_ETHERNET_MAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ETHERNET_MAC DEVICE_PATH_STM32 "ETHERNET_MAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ETHERNET_MAC TYPE_STM32_PREFIX "ethernet_mac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ETHERNET_MAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ETHERNET_MACParentClass; +typedef PeripheralState STM32ETHERNET_MACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ETHERNET_MAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ETHERNET_MACClass, (obj), TYPE_STM32_ETHERNET_MAC) +#define STM32_ETHERNET_MAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ETHERNET_MACClass, (klass), TYPE_STM32_ETHERNET_MAC) + +typedef struct { + // private: + STM32ETHERNET_MACParentClass parent_class; + // public: + + // None, so far. +} STM32ETHERNET_MACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ETHERNET_MAC_STATE(obj) \ + OBJECT_CHECK(STM32ETHERNET_MACState, (obj), TYPE_STM32_ETHERNET_MAC) + +typedef struct { + // private: + STM32ETHERNET_MACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ETHERNET_MAC (Ethernet: media access control) registers. + struct { + Object *maccr; // 0x0 (Ethernet MAC configuration register (ETH_MACCR)) + Object *macffr; // 0x4 (Ethernet MAC frame filter register (ETH_MACCFFR)) + Object *machthr; // 0x8 (Ethernet MAC hash table high register) + Object *machtlr; // 0xC (Ethernet MAC hash table low register) + Object *macmiiar; // 0x10 (Ethernet MAC MII address register (ETH_MACMIIAR)) + Object *macmiidr; // 0x14 (Ethernet MAC MII data register (ETH_MACMIIDR)) + Object *macfcr; // 0x18 (Ethernet MAC flow control register (ETH_MACFCR)) + Object *macvlantr; // 0x1C (Ethernet MAC VLAN tag register (ETH_MACVLANTR)) + Object *macrwuffr; // 0x28 (Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)) + Object *macpmtcsr; // 0x2C (Ethernet MAC PMT control and status register (ETH_MACPMTCSR)) + Object *macsr; // 0x38 (Ethernet MAC interrupt status register (ETH_MACSR)) + Object *macimr; // 0x3C (Ethernet MAC interrupt mask register (ETH_MACIMR)) + Object *maca0hr; // 0x40 (Ethernet MAC address 0 high register (ETH_MACA0HR)) + Object *maca0lr; // 0x44 (Ethernet MAC address 0 low register) + Object *maca1hr; // 0x48 (Ethernet MAC address 1 high register (ETH_MACA1HR)) + Object *maca1lr; // 0x4C (Ethernet MAC address1 low register) + Object *maca2hr; // 0x50 (Ethernet MAC address 2 high register (ETH_MACA2HR)) + Object *maca2lr; // 0x54 (Ethernet MAC address 2 low register) + Object *maca3hr; // 0x58 (Ethernet MAC address 3 high register (ETH_MACA3HR)) + Object *maca3lr; // 0x5C (Ethernet MAC address 3 low register) + } reg; + + struct { + + // MACCR (Ethernet MAC configuration register (ETH_MACCR)) bitfields. + struct { + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *dc; // [4:4] Deferral check + Object *bl; // [5:6] Back-off limit + Object *apcs; // [7:7] Automatic pad/CRC stripping + Object *rd; // [9:9] Retry disable + Object *ipco; // [10:10] IPv4 checksum offload + Object *dm; // [11:11] Duplex mode + Object *lm; // [12:12] Loopback mode + Object *rod; // [13:13] Receive own disable + Object *fes; // [14:14] Fast Ethernet speed + Object *csd; // [16:16] Carrier sense disable + Object *ifg; // [17:19] Interframe gap + Object *jd; // [22:22] Jabber disable + Object *wd; // [23:23] Watchdog disable + } maccr; + + // MACFFR (Ethernet MAC frame filter register (ETH_MACCFFR)) bitfields. + struct { + Object *pm; // [0:0] Promiscuous mode + Object *hu; // [1:1] Hash unicast + Object *hm; // [2:2] Hash multicast + Object *daif; // [3:3] Destination address inverse filtering + Object *pam; // [4:4] Pass all multicast + Object *bfd; // [5:5] Broadcast frames disable + Object *pcf; // [6:7] Pass control frames + Object *saif; // [8:8] Source address inverse filtering + Object *saf; // [9:9] Source address filter + Object *hpf; // [10:10] Hash or perfect filter + Object *ra; // [31:31] Receive all + } macffr; + + // MACHTHR (Ethernet MAC hash table high register) bitfields. + struct { + Object *hth; // [0:31] Hash table high + } machthr; + + // MACHTLR (Ethernet MAC hash table low register) bitfields. + struct { + Object *htl; // [0:31] Hash table low + } machtlr; + + // MACMIIAR (Ethernet MAC MII address register (ETH_MACMIIAR)) bitfields. + struct { + Object *mb; // [0:0] MII busy + Object *mw; // [1:1] MII write + Object *cr; // [2:4] Clock range + Object *mr; // [6:10] MII register + Object *pa; // [11:15] PHY address + } macmiiar; + + // MACMIIDR (Ethernet MAC MII data register (ETH_MACMIIDR)) bitfields. + struct { + Object *md; // [0:15] MII data + } macmiidr; + + // MACFCR (Ethernet MAC flow control register (ETH_MACFCR)) bitfields. + struct { + Object *fcb_bpa; // [0:0] Flow control busy/back pressure activate + Object *tfce; // [1:1] Transmit flow control enable + Object *rfce; // [2:2] Receive flow control enable + Object *upfd; // [3:3] Unicast pause frame detect + Object *plt; // [4:5] Pause low threshold + Object *zqpd; // [7:7] Zero-quanta pause disable + Object *pt; // [16:31] Pass control frames + } macfcr; + + // MACVLANTR (Ethernet MAC VLAN tag register (ETH_MACVLANTR)) bitfields. + struct { + Object *vlanti; // [0:15] VLAN tag identifier (for receive frames) + Object *vlantc; // [16:16] 12-bit VLAN tag comparison + } macvlantr; + + // MACRWUFFR (Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)) bitfields. + struct { + } macrwuffr; + + // MACPMTCSR (Ethernet MAC PMT control and status register (ETH_MACPMTCSR)) bitfields. + struct { + Object *pd; // [0:0] Power down + Object *mpe; // [1:1] Magic Packet enable + Object *wfe; // [2:2] Wakeup frame enable + Object *mpr; // [5:5] Magic packet received + Object *wfr; // [6:6] Wakeup frame received + Object *gu; // [9:9] Global unicast + Object *wffrpr; // [31:31] Wakeup frame filter register pointer reset + } macpmtcsr; + + // MACSR (Ethernet MAC interrupt status register (ETH_MACSR)) bitfields. + struct { + Object *pmts; // [3:3] PMT status + Object *mmcs; // [4:4] MMC status + Object *mmcrs; // [5:5] MMC receive status + Object *mmcts; // [6:6] MMC transmit status + Object *tsts; // [9:9] Time stamp trigger status + } macsr; + + // MACIMR (Ethernet MAC interrupt mask register (ETH_MACIMR)) bitfields. + struct { + Object *pmtim; // [3:3] PMT interrupt mask + Object *tstim; // [9:9] Time stamp trigger interrupt mask + } macimr; + + // MACA0HR (Ethernet MAC address 0 high register (ETH_MACA0HR)) bitfields. + struct { + Object *maca0h; // [0:15] MAC address0 high + Object *mo; // [31:31] Always 1 + } maca0hr; + + // MACA0LR (Ethernet MAC address 0 low register) bitfields. + struct { + Object *maca0l; // [0:31] MAC address0 low + } maca0lr; + + // MACA1HR (Ethernet MAC address 1 high register (ETH_MACA1HR)) bitfields. + struct { + Object *maca1h; // [0:15] MAC address1 high + Object *mbc; // [24:29] Mask byte control + Object *sa; // [30:30] Source address + Object *ae; // [31:31] Address enable + } maca1hr; + + // MACA1LR (Ethernet MAC address1 low register) bitfields. + struct { + Object *maca1l; // [0:31] MAC address1 low + } maca1lr; + + // MACA2HR (Ethernet MAC address 2 high register (ETH_MACA2HR)) bitfields. + struct { + Object *eth_maca2hr; // [0:15] Ethernet MAC address 2 high register + Object *mbc; // [24:29] Mask byte control + Object *sa; // [30:30] Source address + Object *ae; // [31:31] Address enable + } maca2hr; + + // MACA2LR (Ethernet MAC address 2 low register) bitfields. + struct { + Object *maca2l; // [0:30] MAC address2 low + } maca2lr; + + // MACA3HR (Ethernet MAC address 3 high register (ETH_MACA3HR)) bitfields. + struct { + Object *maca3h; // [0:15] MAC address3 high + Object *mbc; // [24:29] Mask byte control + Object *sa; // [30:30] Source address + Object *ae; // [31:31] Address enable + } maca3hr; + + // MACA3LR (Ethernet MAC address 3 low register) bitfields. + struct { + Object *mbca3l; // [0:31] MAC address3 low + } maca3lr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ETHERNET_MACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ETHERNET_MAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mmc.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mmc.c new file mode 100644 index 0000000000..77c693c9fe --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mmc.c @@ -0,0 +1,289 @@ +/* + * STM32 - ETHERNET_MMC (Ethernet: MAC management counters) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_ethernet_mmc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.mmccr = cm_object_get_child_by_name(obj, "MMCCR"); + state->u.f1.reg.mmcrir = cm_object_get_child_by_name(obj, "MMCRIR"); + state->u.f1.reg.mmctir = cm_object_get_child_by_name(obj, "MMCTIR"); + state->u.f1.reg.mmcrimr = cm_object_get_child_by_name(obj, "MMCRIMR"); + state->u.f1.reg.mmctimr = cm_object_get_child_by_name(obj, "MMCTIMR"); + state->u.f1.reg.mmctgfsccr = cm_object_get_child_by_name(obj, "MMCTGFSCCR"); + state->u.f1.reg.mmctgfmsccr = cm_object_get_child_by_name(obj, "MMCTGFMSCCR"); + state->u.f1.reg.mmctgfcr = cm_object_get_child_by_name(obj, "MMCTGFCR"); + state->u.f1.reg.mmcrfcecr = cm_object_get_child_by_name(obj, "MMCRFCECR"); + state->u.f1.reg.mmcrfaecr = cm_object_get_child_by_name(obj, "MMCRFAECR"); + state->u.f1.reg.mmcrgufcr = cm_object_get_child_by_name(obj, "MMCRGUFCR"); + + + // MMCCR bitfields. + state->u.f1.fld.mmccr.cr = cm_object_get_child_by_name(state->u.f1.reg.mmccr, "CR"); + state->u.f1.fld.mmccr.csr = cm_object_get_child_by_name(state->u.f1.reg.mmccr, "CSR"); + state->u.f1.fld.mmccr.ror = cm_object_get_child_by_name(state->u.f1.reg.mmccr, "ROR"); + state->u.f1.fld.mmccr.mcf = cm_object_get_child_by_name(state->u.f1.reg.mmccr, "MCF"); + + // MMCRIR bitfields. + state->u.f1.fld.mmcrir.rfces = cm_object_get_child_by_name(state->u.f1.reg.mmcrir, "RFCES"); + state->u.f1.fld.mmcrir.rfaes = cm_object_get_child_by_name(state->u.f1.reg.mmcrir, "RFAES"); + state->u.f1.fld.mmcrir.rgufs = cm_object_get_child_by_name(state->u.f1.reg.mmcrir, "RGUFS"); + + // MMCTIR bitfields. + state->u.f1.fld.mmctir.tgfscs = cm_object_get_child_by_name(state->u.f1.reg.mmctir, "TGFSCS"); + state->u.f1.fld.mmctir.tgfmscs = cm_object_get_child_by_name(state->u.f1.reg.mmctir, "TGFMSCS"); + state->u.f1.fld.mmctir.tgfs = cm_object_get_child_by_name(state->u.f1.reg.mmctir, "TGFS"); + + // MMCRIMR bitfields. + state->u.f1.fld.mmcrimr.rfcem = cm_object_get_child_by_name(state->u.f1.reg.mmcrimr, "RFCEM"); + state->u.f1.fld.mmcrimr.rfaem = cm_object_get_child_by_name(state->u.f1.reg.mmcrimr, "RFAEM"); + state->u.f1.fld.mmcrimr.rgufm = cm_object_get_child_by_name(state->u.f1.reg.mmcrimr, "RGUFM"); + + // MMCTIMR bitfields. + state->u.f1.fld.mmctimr.tgfscm = cm_object_get_child_by_name(state->u.f1.reg.mmctimr, "TGFSCM"); + state->u.f1.fld.mmctimr.tgfmscm = cm_object_get_child_by_name(state->u.f1.reg.mmctimr, "TGFMSCM"); + state->u.f1.fld.mmctimr.tgfm = cm_object_get_child_by_name(state->u.f1.reg.mmctimr, "TGFM"); + + // MMCTGFSCCR bitfields. + state->u.f1.fld.mmctgfsccr.tgfscc = cm_object_get_child_by_name(state->u.f1.reg.mmctgfsccr, "TGFSCC"); + + // MMCTGFMSCCR bitfields. + state->u.f1.fld.mmctgfmsccr.tgfmscc = cm_object_get_child_by_name(state->u.f1.reg.mmctgfmsccr, "TGFMSCC"); + + // MMCTGFCR bitfields. + state->u.f1.fld.mmctgfcr.tgfc = cm_object_get_child_by_name(state->u.f1.reg.mmctgfcr, "TGFC"); + + // MMCRFCECR bitfields. + state->u.f1.fld.mmcrfcecr.rfcfc = cm_object_get_child_by_name(state->u.f1.reg.mmcrfcecr, "RFCFC"); + + // MMCRFAECR bitfields. + state->u.f1.fld.mmcrfaecr.rfaec = cm_object_get_child_by_name(state->u.f1.reg.mmcrfaecr, "RFAEC"); + + // MMCRGUFCR bitfields. + state->u.f1.fld.mmcrgufcr.rgufc = cm_object_get_child_by_name(state->u.f1.reg.mmcrgufcr, "RGUFC"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_mmc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_mmc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_mmc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_mmc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_mmc_is_enabled(Object *obj) +{ + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_mmc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_mmc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ETHERNET_MMC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ETHERNET_MMCState *state = STM32_ETHERNET_MMC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ETHERNET_MMC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_ethernet_mmc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_mmc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_ethernet_mmc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_mmc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_ethernet_mmc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ETHERNET_MMCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_mmc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ETHERNET_MMC); +} + +static void stm32_ethernet_mmc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_mmc_reset_callback; + dc->realize = stm32_ethernet_mmc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_mmc_is_enabled; +} + +static const TypeInfo stm32_ethernet_mmc_type_info = { + .name = TYPE_STM32_ETHERNET_MMC, + .parent = TYPE_STM32_ETHERNET_MMC_PARENT, + .instance_init = stm32_ethernet_mmc_instance_init_callback, + .instance_size = sizeof(STM32ETHERNET_MMCState), + .class_init = stm32_ethernet_mmc_class_init_callback, + .class_size = sizeof(STM32ETHERNET_MMCClass) }; + +static void stm32_ethernet_mmc_register_types(void) +{ + type_register_static(&stm32_ethernet_mmc_type_info); +} + +type_init(stm32_ethernet_mmc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mmc.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mmc.h new file mode 100644 index 0000000000..2dad8d6ec5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_mmc.h @@ -0,0 +1,176 @@ +/* + * STM32 - ETHERNET_MMC (Ethernet: MAC management counters) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ETHERNET_MMC_H_ +#define STM32_ETHERNET_MMC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ETHERNET_MMC DEVICE_PATH_STM32 "ETHERNET_MMC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ETHERNET_MMC TYPE_STM32_PREFIX "ethernet_mmc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ETHERNET_MMC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ETHERNET_MMCParentClass; +typedef PeripheralState STM32ETHERNET_MMCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ETHERNET_MMC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ETHERNET_MMCClass, (obj), TYPE_STM32_ETHERNET_MMC) +#define STM32_ETHERNET_MMC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ETHERNET_MMCClass, (klass), TYPE_STM32_ETHERNET_MMC) + +typedef struct { + // private: + STM32ETHERNET_MMCParentClass parent_class; + // public: + + // None, so far. +} STM32ETHERNET_MMCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ETHERNET_MMC_STATE(obj) \ + OBJECT_CHECK(STM32ETHERNET_MMCState, (obj), TYPE_STM32_ETHERNET_MMC) + +typedef struct { + // private: + STM32ETHERNET_MMCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ETHERNET_MMC (Ethernet: MAC management counters) registers. + struct { + Object *mmccr; // 0x0 (Ethernet MMC control register (ETH_MMCCR)) + Object *mmcrir; // 0x4 (Ethernet MMC receive interrupt register (ETH_MMCRIR)) + Object *mmctir; // 0x8 (Ethernet MMC transmit interrupt register (ETH_MMCTIR)) + Object *mmcrimr; // 0xC (Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)) + Object *mmctimr; // 0x10 (Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)) + Object *mmctgfsccr; // 0x4C (Ethernet MMC transmitted good frames after a single collision counter) + Object *mmctgfmsccr; // 0x50 (Ethernet MMC transmitted good frames after more than a single collision) + Object *mmctgfcr; // 0x68 (Ethernet MMC transmitted good frames counter register) + Object *mmcrfcecr; // 0x94 (Ethernet MMC received frames with CRC error counter register) + Object *mmcrfaecr; // 0x98 (Ethernet MMC received frames with alignment error counter register) + Object *mmcrgufcr; // 0xC4 (MMC received good unicast frames counter register) + } reg; + + struct { + + // MMCCR (Ethernet MMC control register (ETH_MMCCR)) bitfields. + struct { + Object *cr; // [0:0] Counter reset + Object *csr; // [1:1] Counter stop rollover + Object *ror; // [2:2] Reset on read + Object *mcf; // [31:31] MMC counter freeze + } mmccr; + + // MMCRIR (Ethernet MMC receive interrupt register (ETH_MMCRIR)) bitfields. + struct { + Object *rfces; // [5:5] Received frames CRC error status + Object *rfaes; // [6:6] Received frames alignment error status + Object *rgufs; // [17:17] Received Good Unicast Frames Status + } mmcrir; + + // MMCTIR (Ethernet MMC transmit interrupt register (ETH_MMCTIR)) bitfields. + struct { + Object *tgfscs; // [14:14] Transmitted good frames single collision status + Object *tgfmscs; // [15:15] Transmitted good frames more single collision status + Object *tgfs; // [21:21] Transmitted good frames status + } mmctir; + + // MMCRIMR (Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)) bitfields. + struct { + Object *rfcem; // [5:5] Received frame CRC error mask + Object *rfaem; // [6:6] Received frames alignment error mask + Object *rgufm; // [17:17] Received good unicast frames mask + } mmcrimr; + + // MMCTIMR (Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)) bitfields. + struct { + Object *tgfscm; // [14:14] Transmitted good frames single collision mask + Object *tgfmscm; // [15:15] Transmitted good frames more single collision mask + Object *tgfm; // [21:21] Transmitted good frames mask + } mmctimr; + + // MMCTGFSCCR (Ethernet MMC transmitted good frames after a single collision counter) bitfields. + struct { + Object *tgfscc; // [0:31] Transmitted good frames after a single collision counter + } mmctgfsccr; + + // MMCTGFMSCCR (Ethernet MMC transmitted good frames after more than a single collision) bitfields. + struct { + Object *tgfmscc; // [0:31] Transmitted good frames after more than a single collision counter + } mmctgfmsccr; + + // MMCTGFCR (Ethernet MMC transmitted good frames counter register) bitfields. + struct { + Object *tgfc; // [0:31] Transmitted good frames counter + } mmctgfcr; + + // MMCRFCECR (Ethernet MMC received frames with CRC error counter register) bitfields. + struct { + Object *rfcfc; // [0:31] Received frames with CRC error counter + } mmcrfcecr; + + // MMCRFAECR (Ethernet MMC received frames with alignment error counter register) bitfields. + struct { + Object *rfaec; // [0:31] Received frames with alignment error counter + } mmcrfaecr; + + // MMCRGUFCR (MMC received good unicast frames counter register) bitfields. + struct { + Object *rgufc; // [0:31] Received good unicast frames counter + } mmcrgufcr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ETHERNET_MMCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ETHERNET_MMC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_ptp.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_ptp.c new file mode 100644 index 0000000000..9593715743 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_ptp.c @@ -0,0 +1,277 @@ +/* + * STM32 - ETHERNET_PTP (Ethernet: Precision time protocol) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_ethernet_ptp_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.ptptscr = cm_object_get_child_by_name(obj, "PTPTSCR"); + state->u.f1.reg.ptpssir = cm_object_get_child_by_name(obj, "PTPSSIR"); + state->u.f1.reg.ptptshr = cm_object_get_child_by_name(obj, "PTPTSHR"); + state->u.f1.reg.ptptslr = cm_object_get_child_by_name(obj, "PTPTSLR"); + state->u.f1.reg.ptptshur = cm_object_get_child_by_name(obj, "PTPTSHUR"); + state->u.f1.reg.ptptslur = cm_object_get_child_by_name(obj, "PTPTSLUR"); + state->u.f1.reg.ptptsar = cm_object_get_child_by_name(obj, "PTPTSAR"); + state->u.f1.reg.ptptthr = cm_object_get_child_by_name(obj, "PTPTTHR"); + state->u.f1.reg.ptpttlr = cm_object_get_child_by_name(obj, "PTPTTLR"); + + + // PTPTSCR bitfields. + state->u.f1.fld.ptptscr.tse = cm_object_get_child_by_name(state->u.f1.reg.ptptscr, "TSE"); + state->u.f1.fld.ptptscr.tsfcu = cm_object_get_child_by_name(state->u.f1.reg.ptptscr, "TSFCU"); + state->u.f1.fld.ptptscr.tssti = cm_object_get_child_by_name(state->u.f1.reg.ptptscr, "TSSTI"); + state->u.f1.fld.ptptscr.tsstu = cm_object_get_child_by_name(state->u.f1.reg.ptptscr, "TSSTU"); + state->u.f1.fld.ptptscr.tsite = cm_object_get_child_by_name(state->u.f1.reg.ptptscr, "TSITE"); + state->u.f1.fld.ptptscr.tsaru = cm_object_get_child_by_name(state->u.f1.reg.ptptscr, "TSARU"); + + // PTPSSIR bitfields. + state->u.f1.fld.ptpssir.stssi = cm_object_get_child_by_name(state->u.f1.reg.ptpssir, "STSSI"); + + // PTPTSHR bitfields. + state->u.f1.fld.ptptshr.sts = cm_object_get_child_by_name(state->u.f1.reg.ptptshr, "STS"); + + // PTPTSLR bitfields. + state->u.f1.fld.ptptslr.stss = cm_object_get_child_by_name(state->u.f1.reg.ptptslr, "STSS"); + state->u.f1.fld.ptptslr.stpns = cm_object_get_child_by_name(state->u.f1.reg.ptptslr, "STPNS"); + + // PTPTSHUR bitfields. + state->u.f1.fld.ptptshur.tsus = cm_object_get_child_by_name(state->u.f1.reg.ptptshur, "TSUS"); + + // PTPTSLUR bitfields. + state->u.f1.fld.ptptslur.tsuss = cm_object_get_child_by_name(state->u.f1.reg.ptptslur, "TSUSS"); + state->u.f1.fld.ptptslur.tsupns = cm_object_get_child_by_name(state->u.f1.reg.ptptslur, "TSUPNS"); + + // PTPTSAR bitfields. + state->u.f1.fld.ptptsar.tsa = cm_object_get_child_by_name(state->u.f1.reg.ptptsar, "TSA"); + + // PTPTTHR bitfields. + state->u.f1.fld.ptptthr.ttsh = cm_object_get_child_by_name(state->u.f1.reg.ptptthr, "TTSH"); + + // PTPTTLR bitfields. + state->u.f1.fld.ptpttlr.ttsl = cm_object_get_child_by_name(state->u.f1.reg.ptpttlr, "TTSL"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_ptp_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_ptp_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_ptp_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_ptp_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_ptp_is_enabled(Object *obj) +{ + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_ptp_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_ptp_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ETHERNET_PTP)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ETHERNET_PTPState *state = STM32_ETHERNET_PTP_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ETHERNET_PTP"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_ethernet_ptp_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_ptp_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_ethernet_ptp_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_ethernet_ptp_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_ethernet_ptp_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ETHERNET_PTPEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_ptp_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ETHERNET_PTP); +} + +static void stm32_ethernet_ptp_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_ptp_reset_callback; + dc->realize = stm32_ethernet_ptp_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_ptp_is_enabled; +} + +static const TypeInfo stm32_ethernet_ptp_type_info = { + .name = TYPE_STM32_ETHERNET_PTP, + .parent = TYPE_STM32_ETHERNET_PTP_PARENT, + .instance_init = stm32_ethernet_ptp_instance_init_callback, + .instance_size = sizeof(STM32ETHERNET_PTPState), + .class_init = stm32_ethernet_ptp_class_init_callback, + .class_size = sizeof(STM32ETHERNET_PTPClass) }; + +static void stm32_ethernet_ptp_register_types(void) +{ + type_register_static(&stm32_ethernet_ptp_type_info); +} + +type_init(stm32_ethernet_ptp_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_ptp.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_ptp.h new file mode 100644 index 0000000000..3949f56344 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/ethernet_ptp.h @@ -0,0 +1,160 @@ +/* + * STM32 - ETHERNET_PTP (Ethernet: Precision time protocol) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ETHERNET_PTP_H_ +#define STM32_ETHERNET_PTP_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ETHERNET_PTP DEVICE_PATH_STM32 "ETHERNET_PTP" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ETHERNET_PTP TYPE_STM32_PREFIX "ethernet_ptp" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ETHERNET_PTP_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ETHERNET_PTPParentClass; +typedef PeripheralState STM32ETHERNET_PTPParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ETHERNET_PTP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ETHERNET_PTPClass, (obj), TYPE_STM32_ETHERNET_PTP) +#define STM32_ETHERNET_PTP_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ETHERNET_PTPClass, (klass), TYPE_STM32_ETHERNET_PTP) + +typedef struct { + // private: + STM32ETHERNET_PTPParentClass parent_class; + // public: + + // None, so far. +} STM32ETHERNET_PTPClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ETHERNET_PTP_STATE(obj) \ + OBJECT_CHECK(STM32ETHERNET_PTPState, (obj), TYPE_STM32_ETHERNET_PTP) + +typedef struct { + // private: + STM32ETHERNET_PTPParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 ETHERNET_PTP (Ethernet: Precision time protocol) registers. + struct { + Object *ptptscr; // 0x0 (Ethernet PTP time stamp control register (ETH_PTPTSCR)) + Object *ptpssir; // 0x4 (Ethernet PTP subsecond increment register) + Object *ptptshr; // 0x8 (Ethernet PTP time stamp high register) + Object *ptptslr; // 0xC (Ethernet PTP time stamp low register (ETH_PTPTSLR)) + Object *ptptshur; // 0x10 (Ethernet PTP time stamp high update register) + Object *ptptslur; // 0x14 (Ethernet PTP time stamp low update register (ETH_PTPTSLUR)) + Object *ptptsar; // 0x18 (Ethernet PTP time stamp addend register) + Object *ptptthr; // 0x1C (Ethernet PTP target time high register) + Object *ptpttlr; // 0x20 (Ethernet PTP target time low register) + } reg; + + struct { + + // PTPTSCR (Ethernet PTP time stamp control register (ETH_PTPTSCR)) bitfields. + struct { + Object *tse; // [0:0] Time stamp enable + Object *tsfcu; // [1:1] Time stamp fine or coarse update + Object *tssti; // [2:2] Time stamp system time initialize + Object *tsstu; // [3:3] Time stamp system time update + Object *tsite; // [4:4] Time stamp interrupt trigger enable + Object *tsaru; // [5:5] Time stamp addend register update + } ptptscr; + + // PTPSSIR (Ethernet PTP subsecond increment register) bitfields. + struct { + Object *stssi; // [0:7] System time subsecond increment + } ptpssir; + + // PTPTSHR (Ethernet PTP time stamp high register) bitfields. + struct { + Object *sts; // [0:31] System time second + } ptptshr; + + // PTPTSLR (Ethernet PTP time stamp low register (ETH_PTPTSLR)) bitfields. + struct { + Object *stss; // [0:30] System time subseconds + Object *stpns; // [31:31] System time positive or negative sign + } ptptslr; + + // PTPTSHUR (Ethernet PTP time stamp high update register) bitfields. + struct { + Object *tsus; // [0:31] Time stamp update second + } ptptshur; + + // PTPTSLUR (Ethernet PTP time stamp low update register (ETH_PTPTSLUR)) bitfields. + struct { + Object *tsuss; // [0:30] Time stamp update subseconds + Object *tsupns; // [31:31] Time stamp update positive or negative sign + } ptptslur; + + // PTPTSAR (Ethernet PTP time stamp addend register) bitfields. + struct { + Object *tsa; // [0:31] Time stamp addend + } ptptsar; + + // PTPTTHR (Ethernet PTP target time high register) bitfields. + struct { + Object *ttsh; // [0:31] Target time stamp high + } ptptthr; + + // PTPTTLR (Ethernet PTP target time low register) bitfields. + struct { + Object *ttsl; // [0:31] Target time stamp low + } ptpttlr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ETHERNET_PTPState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ETHERNET_PTP_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/exti.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/exti.c new file mode 100644 index 0000000000..4478de8561 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/exti.c @@ -0,0 +1,372 @@ +/* + * STM32 - EXTI (EXTI) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_exti_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.imr = cm_object_get_child_by_name(obj, "IMR"); + state->u.f1.reg.emr = cm_object_get_child_by_name(obj, "EMR"); + state->u.f1.reg.rtsr = cm_object_get_child_by_name(obj, "RTSR"); + state->u.f1.reg.ftsr = cm_object_get_child_by_name(obj, "FTSR"); + state->u.f1.reg.swier = cm_object_get_child_by_name(obj, "SWIER"); + state->u.f1.reg.pr = cm_object_get_child_by_name(obj, "PR"); + + + // IMR bitfields. + state->u.f1.fld.imr.mr0 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR0"); + state->u.f1.fld.imr.mr1 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR1"); + state->u.f1.fld.imr.mr2 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR2"); + state->u.f1.fld.imr.mr3 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR3"); + state->u.f1.fld.imr.mr4 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR4"); + state->u.f1.fld.imr.mr5 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR5"); + state->u.f1.fld.imr.mr6 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR6"); + state->u.f1.fld.imr.mr7 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR7"); + state->u.f1.fld.imr.mr8 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR8"); + state->u.f1.fld.imr.mr9 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR9"); + state->u.f1.fld.imr.mr10 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR10"); + state->u.f1.fld.imr.mr11 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR11"); + state->u.f1.fld.imr.mr12 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR12"); + state->u.f1.fld.imr.mr13 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR13"); + state->u.f1.fld.imr.mr14 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR14"); + state->u.f1.fld.imr.mr15 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR15"); + state->u.f1.fld.imr.mr16 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR16"); + state->u.f1.fld.imr.mr17 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR17"); + state->u.f1.fld.imr.mr18 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR18"); + state->u.f1.fld.imr.mr19 = cm_object_get_child_by_name(state->u.f1.reg.imr, "MR19"); + + // EMR bitfields. + state->u.f1.fld.emr.mr0 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR0"); + state->u.f1.fld.emr.mr1 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR1"); + state->u.f1.fld.emr.mr2 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR2"); + state->u.f1.fld.emr.mr3 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR3"); + state->u.f1.fld.emr.mr4 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR4"); + state->u.f1.fld.emr.mr5 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR5"); + state->u.f1.fld.emr.mr6 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR6"); + state->u.f1.fld.emr.mr7 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR7"); + state->u.f1.fld.emr.mr8 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR8"); + state->u.f1.fld.emr.mr9 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR9"); + state->u.f1.fld.emr.mr10 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR10"); + state->u.f1.fld.emr.mr11 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR11"); + state->u.f1.fld.emr.mr12 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR12"); + state->u.f1.fld.emr.mr13 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR13"); + state->u.f1.fld.emr.mr14 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR14"); + state->u.f1.fld.emr.mr15 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR15"); + state->u.f1.fld.emr.mr16 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR16"); + state->u.f1.fld.emr.mr17 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR17"); + state->u.f1.fld.emr.mr18 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR18"); + state->u.f1.fld.emr.mr19 = cm_object_get_child_by_name(state->u.f1.reg.emr, "MR19"); + + // RTSR bitfields. + state->u.f1.fld.rtsr.tr0 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR0"); + state->u.f1.fld.rtsr.tr1 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR1"); + state->u.f1.fld.rtsr.tr2 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR2"); + state->u.f1.fld.rtsr.tr3 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR3"); + state->u.f1.fld.rtsr.tr4 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR4"); + state->u.f1.fld.rtsr.tr5 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR5"); + state->u.f1.fld.rtsr.tr6 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR6"); + state->u.f1.fld.rtsr.tr7 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR7"); + state->u.f1.fld.rtsr.tr8 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR8"); + state->u.f1.fld.rtsr.tr9 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR9"); + state->u.f1.fld.rtsr.tr10 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR10"); + state->u.f1.fld.rtsr.tr11 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR11"); + state->u.f1.fld.rtsr.tr12 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR12"); + state->u.f1.fld.rtsr.tr13 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR13"); + state->u.f1.fld.rtsr.tr14 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR14"); + state->u.f1.fld.rtsr.tr15 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR15"); + state->u.f1.fld.rtsr.tr16 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR16"); + state->u.f1.fld.rtsr.tr17 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR17"); + state->u.f1.fld.rtsr.tr18 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR18"); + state->u.f1.fld.rtsr.tr19 = cm_object_get_child_by_name(state->u.f1.reg.rtsr, "TR19"); + + // FTSR bitfields. + state->u.f1.fld.ftsr.tr0 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR0"); + state->u.f1.fld.ftsr.tr1 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR1"); + state->u.f1.fld.ftsr.tr2 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR2"); + state->u.f1.fld.ftsr.tr3 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR3"); + state->u.f1.fld.ftsr.tr4 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR4"); + state->u.f1.fld.ftsr.tr5 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR5"); + state->u.f1.fld.ftsr.tr6 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR6"); + state->u.f1.fld.ftsr.tr7 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR7"); + state->u.f1.fld.ftsr.tr8 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR8"); + state->u.f1.fld.ftsr.tr9 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR9"); + state->u.f1.fld.ftsr.tr10 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR10"); + state->u.f1.fld.ftsr.tr11 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR11"); + state->u.f1.fld.ftsr.tr12 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR12"); + state->u.f1.fld.ftsr.tr13 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR13"); + state->u.f1.fld.ftsr.tr14 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR14"); + state->u.f1.fld.ftsr.tr15 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR15"); + state->u.f1.fld.ftsr.tr16 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR16"); + state->u.f1.fld.ftsr.tr17 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR17"); + state->u.f1.fld.ftsr.tr18 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR18"); + state->u.f1.fld.ftsr.tr19 = cm_object_get_child_by_name(state->u.f1.reg.ftsr, "TR19"); + + // SWIER bitfields. + state->u.f1.fld.swier.swier0 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER0"); + state->u.f1.fld.swier.swier1 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER1"); + state->u.f1.fld.swier.swier2 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER2"); + state->u.f1.fld.swier.swier3 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER3"); + state->u.f1.fld.swier.swier4 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER4"); + state->u.f1.fld.swier.swier5 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER5"); + state->u.f1.fld.swier.swier6 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER6"); + state->u.f1.fld.swier.swier7 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER7"); + state->u.f1.fld.swier.swier8 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER8"); + state->u.f1.fld.swier.swier9 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER9"); + state->u.f1.fld.swier.swier10 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER10"); + state->u.f1.fld.swier.swier11 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER11"); + state->u.f1.fld.swier.swier12 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER12"); + state->u.f1.fld.swier.swier13 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER13"); + state->u.f1.fld.swier.swier14 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER14"); + state->u.f1.fld.swier.swier15 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER15"); + state->u.f1.fld.swier.swier16 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER16"); + state->u.f1.fld.swier.swier17 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER17"); + state->u.f1.fld.swier.swier18 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER18"); + state->u.f1.fld.swier.swier19 = cm_object_get_child_by_name(state->u.f1.reg.swier, "SWIER19"); + + // PR bitfields. + state->u.f1.fld.pr.pr0 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR0"); + state->u.f1.fld.pr.pr1 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR1"); + state->u.f1.fld.pr.pr2 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR2"); + state->u.f1.fld.pr.pr3 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR3"); + state->u.f1.fld.pr.pr4 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR4"); + state->u.f1.fld.pr.pr5 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR5"); + state->u.f1.fld.pr.pr6 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR6"); + state->u.f1.fld.pr.pr7 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR7"); + state->u.f1.fld.pr.pr8 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR8"); + state->u.f1.fld.pr.pr9 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR9"); + state->u.f1.fld.pr.pr10 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR10"); + state->u.f1.fld.pr.pr11 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR11"); + state->u.f1.fld.pr.pr12 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR12"); + state->u.f1.fld.pr.pr13 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR13"); + state->u.f1.fld.pr.pr14 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR14"); + state->u.f1.fld.pr.pr15 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR15"); + state->u.f1.fld.pr.pr16 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR16"); + state->u.f1.fld.pr.pr17 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR17"); + state->u.f1.fld.pr.pr18 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR18"); + state->u.f1.fld.pr.pr19 = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR19"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_exti_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_exti_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_exti_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_exti_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_exti_is_enabled(Object *obj) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_exti_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_exti_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_EXTI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32EXTIState *state = STM32_EXTI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "EXTI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_exti_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_exti_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_exti_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_exti_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_exti_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/EXTIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_exti_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_EXTI); +} + +static void stm32_exti_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_exti_reset_callback; + dc->realize = stm32_exti_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_exti_is_enabled; +} + +static const TypeInfo stm32_exti_type_info = { + .name = TYPE_STM32_EXTI, + .parent = TYPE_STM32_EXTI_PARENT, + .instance_init = stm32_exti_instance_init_callback, + .instance_size = sizeof(STM32EXTIState), + .class_init = stm32_exti_class_init_callback, + .class_size = sizeof(STM32EXTIClass) }; + +static void stm32_exti_register_types(void) +{ + type_register_static(&stm32_exti_type_info); +} + +type_init(stm32_exti_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/exti.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/exti.h new file mode 100644 index 0000000000..9704ed002d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/exti.h @@ -0,0 +1,249 @@ +/* + * STM32 - EXTI (EXTI) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_EXTI_H_ +#define STM32_EXTI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_EXTI DEVICE_PATH_STM32 "EXTI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_EXTI TYPE_STM32_PREFIX "exti" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_EXTI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32EXTIParentClass; +typedef PeripheralState STM32EXTIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_EXTI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32EXTIClass, (obj), TYPE_STM32_EXTI) +#define STM32_EXTI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32EXTIClass, (klass), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentClass parent_class; + // public: + + // None, so far. +} STM32EXTIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_EXTI_STATE(obj) \ + OBJECT_CHECK(STM32EXTIState, (obj), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 EXTI (EXTI) registers. + struct { + Object *imr; // 0x0 (Interrupt mask register (EXTI_IMR)) + Object *emr; // 0x4 (Event mask register (EXTI_EMR)) + Object *rtsr; // 0x8 (Rising Trigger selection register (EXTI_RTSR)) + Object *ftsr; // 0xC (Falling Trigger selection register (EXTI_FTSR)) + Object *swier; // 0x10 (Software interrupt event register (EXTI_SWIER)) + Object *pr; // 0x14 (Pending register (EXTI_PR)) + } reg; + + struct { + + // IMR (Interrupt mask register (EXTI_IMR)) bitfields. + struct { + Object *mr0; // [0:0] Interrupt Mask on line 0 + Object *mr1; // [1:1] Interrupt Mask on line 1 + Object *mr2; // [2:2] Interrupt Mask on line 2 + Object *mr3; // [3:3] Interrupt Mask on line 3 + Object *mr4; // [4:4] Interrupt Mask on line 4 + Object *mr5; // [5:5] Interrupt Mask on line 5 + Object *mr6; // [6:6] Interrupt Mask on line 6 + Object *mr7; // [7:7] Interrupt Mask on line 7 + Object *mr8; // [8:8] Interrupt Mask on line 8 + Object *mr9; // [9:9] Interrupt Mask on line 9 + Object *mr10; // [10:10] Interrupt Mask on line 10 + Object *mr11; // [11:11] Interrupt Mask on line 11 + Object *mr12; // [12:12] Interrupt Mask on line 12 + Object *mr13; // [13:13] Interrupt Mask on line 13 + Object *mr14; // [14:14] Interrupt Mask on line 14 + Object *mr15; // [15:15] Interrupt Mask on line 15 + Object *mr16; // [16:16] Interrupt Mask on line 16 + Object *mr17; // [17:17] Interrupt Mask on line 17 + Object *mr18; // [18:18] Interrupt Mask on line 18 + Object *mr19; // [19:19] Interrupt Mask on line 19 + } imr; + + // EMR (Event mask register (EXTI_EMR)) bitfields. + struct { + Object *mr0; // [0:0] Event Mask on line 0 + Object *mr1; // [1:1] Event Mask on line 1 + Object *mr2; // [2:2] Event Mask on line 2 + Object *mr3; // [3:3] Event Mask on line 3 + Object *mr4; // [4:4] Event Mask on line 4 + Object *mr5; // [5:5] Event Mask on line 5 + Object *mr6; // [6:6] Event Mask on line 6 + Object *mr7; // [7:7] Event Mask on line 7 + Object *mr8; // [8:8] Event Mask on line 8 + Object *mr9; // [9:9] Event Mask on line 9 + Object *mr10; // [10:10] Event Mask on line 10 + Object *mr11; // [11:11] Event Mask on line 11 + Object *mr12; // [12:12] Event Mask on line 12 + Object *mr13; // [13:13] Event Mask on line 13 + Object *mr14; // [14:14] Event Mask on line 14 + Object *mr15; // [15:15] Event Mask on line 15 + Object *mr16; // [16:16] Event Mask on line 16 + Object *mr17; // [17:17] Event Mask on line 17 + Object *mr18; // [18:18] Event Mask on line 18 + Object *mr19; // [19:19] Event Mask on line 19 + } emr; + + // RTSR (Rising Trigger selection register (EXTI_RTSR)) bitfields. + struct { + Object *tr0; // [0:0] Rising trigger event configuration of line 0 + Object *tr1; // [1:1] Rising trigger event configuration of line 1 + Object *tr2; // [2:2] Rising trigger event configuration of line 2 + Object *tr3; // [3:3] Rising trigger event configuration of line 3 + Object *tr4; // [4:4] Rising trigger event configuration of line 4 + Object *tr5; // [5:5] Rising trigger event configuration of line 5 + Object *tr6; // [6:6] Rising trigger event configuration of line 6 + Object *tr7; // [7:7] Rising trigger event configuration of line 7 + Object *tr8; // [8:8] Rising trigger event configuration of line 8 + Object *tr9; // [9:9] Rising trigger event configuration of line 9 + Object *tr10; // [10:10] Rising trigger event configuration of line 10 + Object *tr11; // [11:11] Rising trigger event configuration of line 11 + Object *tr12; // [12:12] Rising trigger event configuration of line 12 + Object *tr13; // [13:13] Rising trigger event configuration of line 13 + Object *tr14; // [14:14] Rising trigger event configuration of line 14 + Object *tr15; // [15:15] Rising trigger event configuration of line 15 + Object *tr16; // [16:16] Rising trigger event configuration of line 16 + Object *tr17; // [17:17] Rising trigger event configuration of line 17 + Object *tr18; // [18:18] Rising trigger event configuration of line 18 + Object *tr19; // [19:19] Rising trigger event configuration of line 19 + } rtsr; + + // FTSR (Falling Trigger selection register (EXTI_FTSR)) bitfields. + struct { + Object *tr0; // [0:0] Falling trigger event configuration of line 0 + Object *tr1; // [1:1] Falling trigger event configuration of line 1 + Object *tr2; // [2:2] Falling trigger event configuration of line 2 + Object *tr3; // [3:3] Falling trigger event configuration of line 3 + Object *tr4; // [4:4] Falling trigger event configuration of line 4 + Object *tr5; // [5:5] Falling trigger event configuration of line 5 + Object *tr6; // [6:6] Falling trigger event configuration of line 6 + Object *tr7; // [7:7] Falling trigger event configuration of line 7 + Object *tr8; // [8:8] Falling trigger event configuration of line 8 + Object *tr9; // [9:9] Falling trigger event configuration of line 9 + Object *tr10; // [10:10] Falling trigger event configuration of line 10 + Object *tr11; // [11:11] Falling trigger event configuration of line 11 + Object *tr12; // [12:12] Falling trigger event configuration of line 12 + Object *tr13; // [13:13] Falling trigger event configuration of line 13 + Object *tr14; // [14:14] Falling trigger event configuration of line 14 + Object *tr15; // [15:15] Falling trigger event configuration of line 15 + Object *tr16; // [16:16] Falling trigger event configuration of line 16 + Object *tr17; // [17:17] Falling trigger event configuration of line 17 + Object *tr18; // [18:18] Falling trigger event configuration of line 18 + Object *tr19; // [19:19] Falling trigger event configuration of line 19 + } ftsr; + + // SWIER (Software interrupt event register (EXTI_SWIER)) bitfields. + struct { + Object *swier0; // [0:0] Software Interrupt on line 0 + Object *swier1; // [1:1] Software Interrupt on line 1 + Object *swier2; // [2:2] Software Interrupt on line 2 + Object *swier3; // [3:3] Software Interrupt on line 3 + Object *swier4; // [4:4] Software Interrupt on line 4 + Object *swier5; // [5:5] Software Interrupt on line 5 + Object *swier6; // [6:6] Software Interrupt on line 6 + Object *swier7; // [7:7] Software Interrupt on line 7 + Object *swier8; // [8:8] Software Interrupt on line 8 + Object *swier9; // [9:9] Software Interrupt on line 9 + Object *swier10; // [10:10] Software Interrupt on line 10 + Object *swier11; // [11:11] Software Interrupt on line 11 + Object *swier12; // [12:12] Software Interrupt on line 12 + Object *swier13; // [13:13] Software Interrupt on line 13 + Object *swier14; // [14:14] Software Interrupt on line 14 + Object *swier15; // [15:15] Software Interrupt on line 15 + Object *swier16; // [16:16] Software Interrupt on line 16 + Object *swier17; // [17:17] Software Interrupt on line 17 + Object *swier18; // [18:18] Software Interrupt on line 18 + Object *swier19; // [19:19] Software Interrupt on line 19 + } swier; + + // PR (Pending register (EXTI_PR)) bitfields. + struct { + Object *pr0; // [0:0] Pending bit 0 + Object *pr1; // [1:1] Pending bit 1 + Object *pr2; // [2:2] Pending bit 2 + Object *pr3; // [3:3] Pending bit 3 + Object *pr4; // [4:4] Pending bit 4 + Object *pr5; // [5:5] Pending bit 5 + Object *pr6; // [6:6] Pending bit 6 + Object *pr7; // [7:7] Pending bit 7 + Object *pr8; // [8:8] Pending bit 8 + Object *pr9; // [9:9] Pending bit 9 + Object *pr10; // [10:10] Pending bit 10 + Object *pr11; // [11:11] Pending bit 11 + Object *pr12; // [12:12] Pending bit 12 + Object *pr13; // [13:13] Pending bit 13 + Object *pr14; // [14:14] Pending bit 14 + Object *pr15; // [15:15] Pending bit 15 + Object *pr16; // [16:16] Pending bit 16 + Object *pr17; // [17:17] Pending bit 17 + Object *pr18; // [18:18] Pending bit 18 + Object *pr19; // [19:19] Pending bit 19 + } pr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32EXTIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_EXTI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/flash.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/flash.c new file mode 100644 index 0000000000..aa4016682b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/flash.c @@ -0,0 +1,287 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_flash_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.acr = cm_object_get_child_by_name(obj, "ACR"); + state->u.f1.reg.keyr = cm_object_get_child_by_name(obj, "KEYR"); + state->u.f1.reg.optkeyr = cm_object_get_child_by_name(obj, "OPTKEYR"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.ar = cm_object_get_child_by_name(obj, "AR"); + state->u.f1.reg.obr = cm_object_get_child_by_name(obj, "OBR"); + state->u.f1.reg.wrpr = cm_object_get_child_by_name(obj, "WRPR"); + + + // ACR bitfields. + state->u.f1.fld.acr.latency = cm_object_get_child_by_name(state->u.f1.reg.acr, "LATENCY"); + state->u.f1.fld.acr.hlfcya = cm_object_get_child_by_name(state->u.f1.reg.acr, "HLFCYA"); + state->u.f1.fld.acr.prftbe = cm_object_get_child_by_name(state->u.f1.reg.acr, "PRFTBE"); + state->u.f1.fld.acr.prftbs = cm_object_get_child_by_name(state->u.f1.reg.acr, "PRFTBS"); + + // KEYR bitfields. + state->u.f1.fld.keyr.key = cm_object_get_child_by_name(state->u.f1.reg.keyr, "KEY"); + + // OPTKEYR bitfields. + state->u.f1.fld.optkeyr.optkey = cm_object_get_child_by_name(state->u.f1.reg.optkeyr, "OPTKEY"); + + // SR bitfields. + state->u.f1.fld.sr.bsy = cm_object_get_child_by_name(state->u.f1.reg.sr, "BSY"); + state->u.f1.fld.sr.pgerr = cm_object_get_child_by_name(state->u.f1.reg.sr, "PGERR"); + state->u.f1.fld.sr.wrprterr = cm_object_get_child_by_name(state->u.f1.reg.sr, "WRPRTERR"); + state->u.f1.fld.sr.eop = cm_object_get_child_by_name(state->u.f1.reg.sr, "EOP"); + + // CR bitfields. + state->u.f1.fld.cr.pg = cm_object_get_child_by_name(state->u.f1.reg.cr, "PG"); + state->u.f1.fld.cr.per = cm_object_get_child_by_name(state->u.f1.reg.cr, "PER"); + state->u.f1.fld.cr.mer = cm_object_get_child_by_name(state->u.f1.reg.cr, "MER"); + state->u.f1.fld.cr.optpg = cm_object_get_child_by_name(state->u.f1.reg.cr, "OPTPG"); + state->u.f1.fld.cr.opter = cm_object_get_child_by_name(state->u.f1.reg.cr, "OPTER"); + state->u.f1.fld.cr.strt = cm_object_get_child_by_name(state->u.f1.reg.cr, "STRT"); + state->u.f1.fld.cr.lock = cm_object_get_child_by_name(state->u.f1.reg.cr, "LOCK"); + state->u.f1.fld.cr.optwre = cm_object_get_child_by_name(state->u.f1.reg.cr, "OPTWRE"); + state->u.f1.fld.cr.errie = cm_object_get_child_by_name(state->u.f1.reg.cr, "ERRIE"); + state->u.f1.fld.cr.eopie = cm_object_get_child_by_name(state->u.f1.reg.cr, "EOPIE"); + + // AR bitfields. + state->u.f1.fld.ar.far_ = cm_object_get_child_by_name(state->u.f1.reg.ar, "FAR"); + + // OBR bitfields. + state->u.f1.fld.obr.opterr = cm_object_get_child_by_name(state->u.f1.reg.obr, "OPTERR"); + state->u.f1.fld.obr.rdprt = cm_object_get_child_by_name(state->u.f1.reg.obr, "RDPRT"); + state->u.f1.fld.obr.wdg_sw = cm_object_get_child_by_name(state->u.f1.reg.obr, "WDG_SW"); + state->u.f1.fld.obr.nrst_stop = cm_object_get_child_by_name(state->u.f1.reg.obr, "nRST_STOP"); + state->u.f1.fld.obr.nrst_stdby = cm_object_get_child_by_name(state->u.f1.reg.obr, "nRST_STDBY"); + state->u.f1.fld.obr.data0 = cm_object_get_child_by_name(state->u.f1.reg.obr, "Data0"); + state->u.f1.fld.obr.data1 = cm_object_get_child_by_name(state->u.f1.reg.obr, "Data1"); + + // WRPR bitfields. + state->u.f1.fld.wrpr.wrp = cm_object_get_child_by_name(state->u.f1.reg.wrpr, "WRP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_flash_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_flash_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_flash_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_flash_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_flash_is_enabled(Object *obj) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_flash_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_flash_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FLASH)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FLASHState *state = STM32_FLASH_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FLASH"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_flash_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_flash_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_flash_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_flash_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_flash_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FLASHEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_flash_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FLASH); +} + +static void stm32_flash_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_flash_reset_callback; + dc->realize = stm32_flash_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_flash_is_enabled; +} + +static const TypeInfo stm32_flash_type_info = { + .name = TYPE_STM32_FLASH, + .parent = TYPE_STM32_FLASH_PARENT, + .instance_init = stm32_flash_instance_init_callback, + .instance_size = sizeof(STM32FLASHState), + .class_init = stm32_flash_class_init_callback, + .class_size = sizeof(STM32FLASHClass) }; + +static void stm32_flash_register_types(void) +{ + type_register_static(&stm32_flash_type_info); +} + +type_init(stm32_flash_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/flash.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/flash.h new file mode 100644 index 0000000000..316c484c38 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/flash.h @@ -0,0 +1,168 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FLASH_H_ +#define STM32_FLASH_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FLASH DEVICE_PATH_STM32 "FLASH" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FLASH TYPE_STM32_PREFIX "flash" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FLASH_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FLASHParentClass; +typedef PeripheralState STM32FLASHParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FLASH_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FLASHClass, (obj), TYPE_STM32_FLASH) +#define STM32_FLASH_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FLASHClass, (klass), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentClass parent_class; + // public: + + // None, so far. +} STM32FLASHClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FLASH_STATE(obj) \ + OBJECT_CHECK(STM32FLASHState, (obj), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 FLASH (FLASH) registers. + struct { + Object *acr; // 0x0 (Flash access control register) + Object *keyr; // 0x4 (Flash key register) + Object *optkeyr; // 0x8 (Flash option key register) + Object *sr; // 0xC (Status register) + Object *cr; // 0x10 (Control register) + Object *ar; // 0x14 (Flash address register) + Object *obr; // 0x1C (Option byte register) + Object *wrpr; // 0x20 (Write protection register) + } reg; + + struct { + + // ACR (Flash access control register) bitfields. + struct { + Object *latency; // [0:2] Latency + Object *hlfcya; // [3:3] Flash half cycle access enable + Object *prftbe; // [4:4] Prefetch buffer enable + Object *prftbs; // [5:5] Prefetch buffer status + } acr; + + // KEYR (Flash key register) bitfields. + struct { + Object *key; // [0:31] FPEC key + } keyr; + + // OPTKEYR (Flash option key register) bitfields. + struct { + Object *optkey; // [0:31] Option byte key + } optkeyr; + + // SR (Status register) bitfields. + struct { + Object *bsy; // [0:0] Busy + Object *pgerr; // [2:2] Programming error + Object *wrprterr; // [4:4] Write protection error + Object *eop; // [5:5] End of operation + } sr; + + // CR (Control register) bitfields. + struct { + Object *pg; // [0:0] Programming + Object *per; // [1:1] Page Erase + Object *mer; // [2:2] Mass Erase + Object *optpg; // [4:4] Option byte programming + Object *opter; // [5:5] Option byte erase + Object *strt; // [6:6] Start + Object *lock; // [7:7] Lock + Object *optwre; // [9:9] Option bytes write enable + Object *errie; // [10:10] Error interrupt enable + Object *eopie; // [12:12] End of operation interrupt enable + } cr; + + // AR (Flash address register) bitfields. + struct { + Object *far_; // [0:31] Flash Address + } ar; + + // OBR (Option byte register) bitfields. + struct { + Object *opterr; // [0:0] Option byte error + Object *rdprt; // [1:1] Read protection + Object *wdg_sw; // [2:2] WDG_SW + Object *nrst_stop; // [3:3] NRST_STOP + Object *nrst_stdby; // [4:4] NRST_STDBY + Object *data0; // [10:17] Data0 + Object *data1; // [18:25] Data1 + } obr; + + // WRPR (Write protection register) bitfields. + struct { + Object *wrp; // [0:31] Write protect + } wrpr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FLASHState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FLASH_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/gpioa.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/gpioa.c new file mode 100644 index 0000000000..38e3c4fc3c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/gpioa.c @@ -0,0 +1,389 @@ +/* + * STM32 - GPIO (General purpose I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.crl = cm_object_get_child_by_name(obj, "CRL"); + state->u.f1.reg.crh = cm_object_get_child_by_name(obj, "CRH"); + state->u.f1.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f1.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f1.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + + + // CRL bitfields. + state->u.f1.fld.crl.mode0 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE0"); + state->u.f1.fld.crl.cnf0 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF0"); + state->u.f1.fld.crl.mode1 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE1"); + state->u.f1.fld.crl.cnf1 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF1"); + state->u.f1.fld.crl.mode2 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE2"); + state->u.f1.fld.crl.cnf2 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF2"); + state->u.f1.fld.crl.mode3 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE3"); + state->u.f1.fld.crl.cnf3 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF3"); + state->u.f1.fld.crl.mode4 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE4"); + state->u.f1.fld.crl.cnf4 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF4"); + state->u.f1.fld.crl.mode5 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE5"); + state->u.f1.fld.crl.cnf5 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF5"); + state->u.f1.fld.crl.mode6 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE6"); + state->u.f1.fld.crl.cnf6 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF6"); + state->u.f1.fld.crl.mode7 = cm_object_get_child_by_name(state->u.f1.reg.crl, "MODE7"); + state->u.f1.fld.crl.cnf7 = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF7"); + + // CRH bitfields. + state->u.f1.fld.crh.mode8 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE8"); + state->u.f1.fld.crh.cnf8 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF8"); + state->u.f1.fld.crh.mode9 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE9"); + state->u.f1.fld.crh.cnf9 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF9"); + state->u.f1.fld.crh.mode10 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE10"); + state->u.f1.fld.crh.cnf10 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF10"); + state->u.f1.fld.crh.mode11 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE11"); + state->u.f1.fld.crh.cnf11 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF11"); + state->u.f1.fld.crh.mode12 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE12"); + state->u.f1.fld.crh.cnf12 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF12"); + state->u.f1.fld.crh.mode13 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE13"); + state->u.f1.fld.crh.cnf13 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF13"); + state->u.f1.fld.crh.mode14 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE14"); + state->u.f1.fld.crh.cnf14 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF14"); + state->u.f1.fld.crh.mode15 = cm_object_get_child_by_name(state->u.f1.reg.crh, "MODE15"); + state->u.f1.fld.crh.cnf15 = cm_object_get_child_by_name(state->u.f1.reg.crh, "CNF15"); + + // IDR bitfields. + state->u.f1.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR0"); + state->u.f1.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR1"); + state->u.f1.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR2"); + state->u.f1.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR3"); + state->u.f1.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR4"); + state->u.f1.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR5"); + state->u.f1.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR6"); + state->u.f1.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR7"); + state->u.f1.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR8"); + state->u.f1.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR9"); + state->u.f1.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR10"); + state->u.f1.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR11"); + state->u.f1.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR12"); + state->u.f1.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR13"); + state->u.f1.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR14"); + state->u.f1.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f1.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f1.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR0"); + state->u.f1.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR1"); + state->u.f1.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR2"); + state->u.f1.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR3"); + state->u.f1.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR4"); + state->u.f1.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR5"); + state->u.f1.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR6"); + state->u.f1.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR7"); + state->u.f1.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR8"); + state->u.f1.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR9"); + state->u.f1.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR10"); + state->u.f1.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR11"); + state->u.f1.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR12"); + state->u.f1.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR13"); + state->u.f1.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR14"); + state->u.f1.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f1.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f1.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS0"); + state->u.f1.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS1"); + state->u.f1.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS2"); + state->u.f1.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS3"); + state->u.f1.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS4"); + state->u.f1.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS5"); + state->u.f1.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS6"); + state->u.f1.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS7"); + state->u.f1.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS8"); + state->u.f1.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS9"); + state->u.f1.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS10"); + state->u.f1.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS11"); + state->u.f1.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS12"); + state->u.f1.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS13"); + state->u.f1.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS14"); + state->u.f1.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BS15"); + state->u.f1.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR0"); + state->u.f1.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR1"); + state->u.f1.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR2"); + state->u.f1.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR3"); + state->u.f1.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR4"); + state->u.f1.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR5"); + state->u.f1.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR6"); + state->u.f1.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR7"); + state->u.f1.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR8"); + state->u.f1.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR9"); + state->u.f1.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR10"); + state->u.f1.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR11"); + state->u.f1.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR12"); + state->u.f1.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR13"); + state->u.f1.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR14"); + state->u.f1.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f1.reg.bsrr, "BR15"); + + // BRR bitfields. + state->u.f1.fld.brr.br0 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR0"); + state->u.f1.fld.brr.br1 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR1"); + state->u.f1.fld.brr.br2 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR2"); + state->u.f1.fld.brr.br3 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR3"); + state->u.f1.fld.brr.br4 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR4"); + state->u.f1.fld.brr.br5 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR5"); + state->u.f1.fld.brr.br6 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR6"); + state->u.f1.fld.brr.br7 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR7"); + state->u.f1.fld.brr.br8 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR8"); + state->u.f1.fld.brr.br9 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR9"); + state->u.f1.fld.brr.br10 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR10"); + state->u.f1.fld.brr.br11 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR11"); + state->u.f1.fld.brr.br12 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR12"); + state->u.f1.fld.brr.br13 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR13"); + state->u.f1.fld.brr.br14 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR14"); + state->u.f1.fld.brr.br15 = cm_object_get_child_by_name(state->u.f1.reg.brr, "BR15"); + + // LCKR bitfields. + state->u.f1.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK0"); + state->u.f1.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK1"); + state->u.f1.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK2"); + state->u.f1.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK3"); + state->u.f1.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK4"); + state->u.f1.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK5"); + state->u.f1.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK6"); + state->u.f1.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK7"); + state->u.f1.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK8"); + state->u.f1.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK9"); + state->u.f1.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK10"); + state->u.f1.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK11"); + state->u.f1.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK12"); + state->u.f1.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK13"); + state->u.f1.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK14"); + state->u.f1.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCK15"); + state->u.f1.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f1.reg.lckr, "LCKK"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/gpioa.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/gpioa.h new file mode 100644 index 0000000000..1deea10397 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/gpioa.h @@ -0,0 +1,277 @@ +/* + * STM32 - GPIO (General purpose I/O) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 GPIO (General purpose I/O) registers. + struct { + Object *crl; // 0x0 (Port configuration register low (GPIOn_CRL)) + Object *crh; // 0x4 (Port configuration register high (GPIOn_CRL)) + Object *idr; // 0x8 (Port input data register (GPIOn_IDR)) + Object *odr; // 0xC (Port output data register (GPIOn_ODR)) + Object *bsrr; // 0x10 (Port bit set/reset register (GPIOn_BSRR)) + Object *brr; // 0x14 (Port bit reset register (GPIOn_BRR)) + Object *lckr; // 0x18 (Port configuration lock register) + } reg; + + struct { + + // CRL (Port configuration register low (GPIOn_CRL)) bitfields. + struct { + Object *mode0; // [0:1] Port n.0 mode bits + Object *cnf0; // [2:3] Port n.0 configuration bits + Object *mode1; // [4:5] Port n.1 mode bits + Object *cnf1; // [6:7] Port n.1 configuration bits + Object *mode2; // [8:9] Port n.2 mode bits + Object *cnf2; // [10:11] Port n.2 configuration bits + Object *mode3; // [12:13] Port n.3 mode bits + Object *cnf3; // [14:15] Port n.3 configuration bits + Object *mode4; // [16:17] Port n.4 mode bits + Object *cnf4; // [18:19] Port n.4 configuration bits + Object *mode5; // [20:21] Port n.5 mode bits + Object *cnf5; // [22:23] Port n.5 configuration bits + Object *mode6; // [24:25] Port n.6 mode bits + Object *cnf6; // [26:27] Port n.6 configuration bits + Object *mode7; // [28:29] Port n.7 mode bits + Object *cnf7; // [30:31] Port n.7 configuration bits + } crl; + + // CRH (Port configuration register high (GPIOn_CRL)) bitfields. + struct { + Object *mode8; // [0:1] Port n.8 mode bits + Object *cnf8; // [2:3] Port n.8 configuration bits + Object *mode9; // [4:5] Port n.9 mode bits + Object *cnf9; // [6:7] Port n.9 configuration bits + Object *mode10; // [8:9] Port n.10 mode bits + Object *cnf10; // [10:11] Port n.10 configuration bits + Object *mode11; // [12:13] Port n.11 mode bits + Object *cnf11; // [14:15] Port n.11 configuration bits + Object *mode12; // [16:17] Port n.12 mode bits + Object *cnf12; // [18:19] Port n.12 configuration bits + Object *mode13; // [20:21] Port n.13 mode bits + Object *cnf13; // [22:23] Port n.13 configuration bits + Object *mode14; // [24:25] Port n.14 mode bits + Object *cnf14; // [26:27] Port n.14 configuration bits + Object *mode15; // [28:29] Port n.15 mode bits + Object *cnf15; // [30:31] Port n.15 configuration bits + } crh; + + // IDR (Port input data register (GPIOn_IDR)) bitfields. + struct { + Object *idr0; // [0:0] Port input data + Object *idr1; // [1:1] Port input data + Object *idr2; // [2:2] Port input data + Object *idr3; // [3:3] Port input data + Object *idr4; // [4:4] Port input data + Object *idr5; // [5:5] Port input data + Object *idr6; // [6:6] Port input data + Object *idr7; // [7:7] Port input data + Object *idr8; // [8:8] Port input data + Object *idr9; // [9:9] Port input data + Object *idr10; // [10:10] Port input data + Object *idr11; // [11:11] Port input data + Object *idr12; // [12:12] Port input data + Object *idr13; // [13:13] Port input data + Object *idr14; // [14:14] Port input data + Object *idr15; // [15:15] Port input data + } idr; + + // ODR (Port output data register (GPIOn_ODR)) bitfields. + struct { + Object *odr0; // [0:0] Port output data + Object *odr1; // [1:1] Port output data + Object *odr2; // [2:2] Port output data + Object *odr3; // [3:3] Port output data + Object *odr4; // [4:4] Port output data + Object *odr5; // [5:5] Port output data + Object *odr6; // [6:6] Port output data + Object *odr7; // [7:7] Port output data + Object *odr8; // [8:8] Port output data + Object *odr9; // [9:9] Port output data + Object *odr10; // [10:10] Port output data + Object *odr11; // [11:11] Port output data + Object *odr12; // [12:12] Port output data + Object *odr13; // [13:13] Port output data + Object *odr14; // [14:14] Port output data + Object *odr15; // [15:15] Port output data + } odr; + + // BSRR (Port bit set/reset register (GPIOn_BSRR)) bitfields. + struct { + Object *bs0; // [0:0] Set bit 0 + Object *bs1; // [1:1] Set bit 1 + Object *bs2; // [2:2] Set bit 1 + Object *bs3; // [3:3] Set bit 3 + Object *bs4; // [4:4] Set bit 4 + Object *bs5; // [5:5] Set bit 5 + Object *bs6; // [6:6] Set bit 6 + Object *bs7; // [7:7] Set bit 7 + Object *bs8; // [8:8] Set bit 8 + Object *bs9; // [9:9] Set bit 9 + Object *bs10; // [10:10] Set bit 10 + Object *bs11; // [11:11] Set bit 11 + Object *bs12; // [12:12] Set bit 12 + Object *bs13; // [13:13] Set bit 13 + Object *bs14; // [14:14] Set bit 14 + Object *bs15; // [15:15] Set bit 15 + Object *br0; // [16:16] Reset bit 0 + Object *br1; // [17:17] Reset bit 1 + Object *br2; // [18:18] Reset bit 2 + Object *br3; // [19:19] Reset bit 3 + Object *br4; // [20:20] Reset bit 4 + Object *br5; // [21:21] Reset bit 5 + Object *br6; // [22:22] Reset bit 6 + Object *br7; // [23:23] Reset bit 7 + Object *br8; // [24:24] Reset bit 8 + Object *br9; // [25:25] Reset bit 9 + Object *br10; // [26:26] Reset bit 10 + Object *br11; // [27:27] Reset bit 11 + Object *br12; // [28:28] Reset bit 12 + Object *br13; // [29:29] Reset bit 13 + Object *br14; // [30:30] Reset bit 14 + Object *br15; // [31:31] Reset bit 15 + } bsrr; + + // BRR (Port bit reset register (GPIOn_BRR)) bitfields. + struct { + Object *br0; // [0:0] Reset bit 0 + Object *br1; // [1:1] Reset bit 1 + Object *br2; // [2:2] Reset bit 1 + Object *br3; // [3:3] Reset bit 3 + Object *br4; // [4:4] Reset bit 4 + Object *br5; // [5:5] Reset bit 5 + Object *br6; // [6:6] Reset bit 6 + Object *br7; // [7:7] Reset bit 7 + Object *br8; // [8:8] Reset bit 8 + Object *br9; // [9:9] Reset bit 9 + Object *br10; // [10:10] Reset bit 10 + Object *br11; // [11:11] Reset bit 11 + Object *br12; // [12:12] Reset bit 12 + Object *br13; // [13:13] Reset bit 13 + Object *br14; // [14:14] Reset bit 14 + Object *br15; // [15:15] Reset bit 15 + } brr; + + // LCKR (Port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port A Lock bit 0 + Object *lck1; // [1:1] Port A Lock bit 1 + Object *lck2; // [2:2] Port A Lock bit 2 + Object *lck3; // [3:3] Port A Lock bit 3 + Object *lck4; // [4:4] Port A Lock bit 4 + Object *lck5; // [5:5] Port A Lock bit 5 + Object *lck6; // [6:6] Port A Lock bit 6 + Object *lck7; // [7:7] Port A Lock bit 7 + Object *lck8; // [8:8] Port A Lock bit 8 + Object *lck9; // [9:9] Port A Lock bit 9 + Object *lck10; // [10:10] Port A Lock bit 10 + Object *lck11; // [11:11] Port A Lock bit 11 + Object *lck12; // [12:12] Port A Lock bit 12 + Object *lck13; // [13:13] Port A Lock bit 13 + Object *lck14; // [14:14] Port A Lock bit 14 + Object *lck15; // [15:15] Port A Lock bit 15 + Object *lckk; // [16:16] Lock key + } lckr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/i2c1.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/i2c1.c new file mode 100644 index 0000000000..f122e1dcc4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/i2c1.c @@ -0,0 +1,319 @@ +/* + * STM32 - I2C (Inter integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_i2c_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.oar1 = cm_object_get_child_by_name(obj, "OAR1"); + state->u.f1.reg.oar2 = cm_object_get_child_by_name(obj, "OAR2"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.sr1 = cm_object_get_child_by_name(obj, "SR1"); + state->u.f1.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f1.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + state->u.f1.reg.trise = cm_object_get_child_by_name(obj, "TRISE"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.pe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PE"); + state->u.f1.fld.cr1.smbus = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SMBUS"); + state->u.f1.fld.cr1.smbtype = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SMBTYPE"); + state->u.f1.fld.cr1.enarp = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ENARP"); + state->u.f1.fld.cr1.enpec = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ENPEC"); + state->u.f1.fld.cr1.engc = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ENGC"); + state->u.f1.fld.cr1.nostretch = cm_object_get_child_by_name(state->u.f1.reg.cr1, "NOSTRETCH"); + state->u.f1.fld.cr1.start = cm_object_get_child_by_name(state->u.f1.reg.cr1, "START"); + state->u.f1.fld.cr1.stop = cm_object_get_child_by_name(state->u.f1.reg.cr1, "STOP"); + state->u.f1.fld.cr1.ack = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ACK"); + state->u.f1.fld.cr1.pos = cm_object_get_child_by_name(state->u.f1.reg.cr1, "POS"); + state->u.f1.fld.cr1.pec = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEC"); + state->u.f1.fld.cr1.alert = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ALERT"); + state->u.f1.fld.cr1.swrst = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SWRST"); + + // CR2 bitfields. + state->u.f1.fld.cr2.freq = cm_object_get_child_by_name(state->u.f1.reg.cr2, "FREQ"); + state->u.f1.fld.cr2.iterren = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ITERREN"); + state->u.f1.fld.cr2.itevten = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ITEVTEN"); + state->u.f1.fld.cr2.itbufen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ITBUFEN"); + state->u.f1.fld.cr2.dmaen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "DMAEN"); + state->u.f1.fld.cr2.last = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LAST"); + + // OAR1 bitfields. + state->u.f1.fld.oar1.add0 = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADD0"); + state->u.f1.fld.oar1.add7 = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADD7"); + state->u.f1.fld.oar1.add10 = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADD10"); + state->u.f1.fld.oar1.addmode = cm_object_get_child_by_name(state->u.f1.reg.oar1, "ADDMODE"); + + // OAR2 bitfields. + state->u.f1.fld.oar2.endual = cm_object_get_child_by_name(state->u.f1.reg.oar2, "ENDUAL"); + state->u.f1.fld.oar2.add2 = cm_object_get_child_by_name(state->u.f1.reg.oar2, "ADD2"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // SR1 bitfields. + state->u.f1.fld.sr1.sb = cm_object_get_child_by_name(state->u.f1.reg.sr1, "SB"); + state->u.f1.fld.sr1.addr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "ADDR"); + state->u.f1.fld.sr1.btf = cm_object_get_child_by_name(state->u.f1.reg.sr1, "BTF"); + state->u.f1.fld.sr1.add10 = cm_object_get_child_by_name(state->u.f1.reg.sr1, "ADD10"); + state->u.f1.fld.sr1.stopf = cm_object_get_child_by_name(state->u.f1.reg.sr1, "STOPF"); + state->u.f1.fld.sr1.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr1, "RxNE"); + state->u.f1.fld.sr1.txe = cm_object_get_child_by_name(state->u.f1.reg.sr1, "TxE"); + state->u.f1.fld.sr1.berr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "BERR"); + state->u.f1.fld.sr1.arlo = cm_object_get_child_by_name(state->u.f1.reg.sr1, "ARLO"); + state->u.f1.fld.sr1.af = cm_object_get_child_by_name(state->u.f1.reg.sr1, "AF"); + state->u.f1.fld.sr1.ovr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "OVR"); + state->u.f1.fld.sr1.pecerr = cm_object_get_child_by_name(state->u.f1.reg.sr1, "PECERR"); + state->u.f1.fld.sr1.timeout = cm_object_get_child_by_name(state->u.f1.reg.sr1, "TIMEOUT"); + state->u.f1.fld.sr1.smbalert = cm_object_get_child_by_name(state->u.f1.reg.sr1, "SMBALERT"); + + // SR2 bitfields. + state->u.f1.fld.sr2.msl = cm_object_get_child_by_name(state->u.f1.reg.sr2, "MSL"); + state->u.f1.fld.sr2.busy = cm_object_get_child_by_name(state->u.f1.reg.sr2, "BUSY"); + state->u.f1.fld.sr2.tra = cm_object_get_child_by_name(state->u.f1.reg.sr2, "TRA"); + state->u.f1.fld.sr2.gencall = cm_object_get_child_by_name(state->u.f1.reg.sr2, "GENCALL"); + state->u.f1.fld.sr2.smbdefault = cm_object_get_child_by_name(state->u.f1.reg.sr2, "SMBDEFAULT"); + state->u.f1.fld.sr2.smbhost = cm_object_get_child_by_name(state->u.f1.reg.sr2, "SMBHOST"); + state->u.f1.fld.sr2.dualf = cm_object_get_child_by_name(state->u.f1.reg.sr2, "DUALF"); + state->u.f1.fld.sr2.pec = cm_object_get_child_by_name(state->u.f1.reg.sr2, "PEC"); + + // CCR bitfields. + state->u.f1.fld.ccr.ccr = cm_object_get_child_by_name(state->u.f1.reg.ccr, "CCR"); + state->u.f1.fld.ccr.duty = cm_object_get_child_by_name(state->u.f1.reg.ccr, "DUTY"); + state->u.f1.fld.ccr.f_s = cm_object_get_child_by_name(state->u.f1.reg.ccr, "F_S"); + + // TRISE bitfields. + state->u.f1.fld.trise.trise = cm_object_get_child_by_name(state->u.f1.reg.trise, "TRISE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2c_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2c_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2c_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2c_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2c_is_enabled(Object *obj) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2c_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2CState *state = STM32_I2C_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_I2C_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2c_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2C)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2CState *state = STM32_I2C_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2C"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_i2c_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_i2c_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_i2c_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_i2c_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_i2c_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2C%dEN", + 1 + state->port_index - STM32_PORT_I2C1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2c_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2C); +} + +static void stm32_i2c_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2c_reset_callback; + dc->realize = stm32_i2c_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2c_is_enabled; +} + +static const TypeInfo stm32_i2c_type_info = { + .name = TYPE_STM32_I2C, + .parent = TYPE_STM32_I2C_PARENT, + .instance_init = stm32_i2c_instance_init_callback, + .instance_size = sizeof(STM32I2CState), + .class_init = stm32_i2c_class_init_callback, + .class_size = sizeof(STM32I2CClass) }; + +static void stm32_i2c_register_types(void) +{ + type_register_static(&stm32_i2c_type_info); +} + +type_init(stm32_i2c_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/i2c1.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/i2c1.h new file mode 100644 index 0000000000..cd9c0eb808 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/i2c1.h @@ -0,0 +1,208 @@ +/* + * STM32 - I2C (Inter integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2C_H_ +#define STM32_I2C_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2C DEVICE_PATH_STM32 "I2C" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_I2C1, + STM32_PORT_I2C2, + STM32_PORT_I2C_UNDEFINED = 0xFF, +} stm32_i2c_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2C TYPE_STM32_PREFIX "i2c" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2C_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2CParentClass; +typedef PeripheralState STM32I2CParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2CClass, (obj), TYPE_STM32_I2C) +#define STM32_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2CClass, (klass), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentClass parent_class; + // public: + + // None, so far. +} STM32I2CClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2C_STATE(obj) \ + OBJECT_CHECK(STM32I2CState, (obj), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_i2c_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 I2C (Inter integrated circuit) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *oar1; // 0x8 (Own address register 1) + Object *oar2; // 0xC (Own address register 2) + Object *dr; // 0x10 (Data register) + Object *sr1; // 0x14 (Status register 1) + Object *sr2; // 0x18 (Status register 2) + Object *ccr; // 0x1C (Clock control register) + Object *trise; // 0x20 (TRISE register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *pe; // [0:0] Peripheral enable + Object *smbus; // [1:1] SMBus mode + Object *smbtype; // [3:3] SMBus type + Object *enarp; // [4:4] ARP enable + Object *enpec; // [5:5] PEC enable + Object *engc; // [6:6] General call enable + Object *nostretch; // [7:7] Clock stretching disable (Slave mode) + Object *start; // [8:8] Start generation + Object *stop; // [9:9] Stop generation + Object *ack; // [10:10] Acknowledge enable + Object *pos; // [11:11] Acknowledge/PEC Position (for data reception) + Object *pec; // [12:12] Packet error checking + Object *alert; // [13:13] SMBus alert + Object *swrst; // [15:15] Software reset + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *freq; // [0:5] Peripheral clock frequency + Object *iterren; // [8:8] Error interrupt enable + Object *itevten; // [9:9] Event interrupt enable + Object *itbufen; // [10:10] Buffer interrupt enable + Object *dmaen; // [11:11] DMA requests enable + Object *last; // [12:12] DMA last transfer + } cr2; + + // OAR1 (Own address register 1) bitfields. + struct { + Object *add0; // [0:0] Interface address + Object *add7; // [1:7] Interface address + Object *add10; // [8:9] Interface address + Object *addmode; // [15:15] Addressing mode (slave mode) + } oar1; + + // OAR2 (Own address register 2) bitfields. + struct { + Object *endual; // [0:0] Dual addressing mode enable + Object *add2; // [1:7] Interface address + } oar2; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:7] 8-bit data register + } dr; + + // SR1 (Status register 1) bitfields. + struct { + Object *sb; // [0:0] Start bit (Master mode) + Object *addr; // [1:1] Address sent (master mode)/matched (slave mode) + Object *btf; // [2:2] Byte transfer finished + Object *add10; // [3:3] 10-bit header sent (Master mode) + Object *stopf; // [4:4] Stop detection (slave mode) + Object *rxne; // [6:6] Data register not empty (receivers) + Object *txe; // [7:7] Data register empty (transmitters) + Object *berr; // [8:8] Bus error + Object *arlo; // [9:9] Arbitration lost (master mode) + Object *af; // [10:10] Acknowledge failure + Object *ovr; // [11:11] Overrun/Underrun + Object *pecerr; // [12:12] PEC Error in reception + Object *timeout; // [14:14] Timeout or Tlow error + Object *smbalert; // [15:15] SMBus alert + } sr1; + + // SR2 (Status register 2) bitfields. + struct { + Object *msl; // [0:0] Master/slave + Object *busy; // [1:1] Bus busy + Object *tra; // [2:2] Transmitter/receiver + Object *gencall; // [4:4] General call address (Slave mode) + Object *smbdefault; // [5:5] SMBus device default address (Slave mode) + Object *smbhost; // [6:6] SMBus host header (Slave mode) + Object *dualf; // [7:7] Dual flag (Slave mode) + Object *pec; // [8:15] Acket error checking register + } sr2; + + // CCR (Clock control register) bitfields. + struct { + Object *ccr; // [0:11] Clock control register in Fast/Standard mode (Master mode) + Object *duty; // [14:14] Fast mode duty cycle + Object *f_s; // [15:15] I2C master mode selection + } ccr; + + // TRISE (TRISE register) bitfields. + struct { + Object *trise; // [0:5] Maximum rise time in Fast/Standard mode (Master mode) + } trise; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2CState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2C_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/iwdg.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/iwdg.c new file mode 100644 index 0000000000..16e0192bd9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/iwdg.c @@ -0,0 +1,251 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_iwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.kr = cm_object_get_child_by_name(obj, "KR"); + state->u.f1.reg.pr = cm_object_get_child_by_name(obj, "PR"); + state->u.f1.reg.rlr = cm_object_get_child_by_name(obj, "RLR"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // KR bitfields. + state->u.f1.fld.kr.key = cm_object_get_child_by_name(state->u.f1.reg.kr, "KEY"); + + // PR bitfields. + state->u.f1.fld.pr.pr = cm_object_get_child_by_name(state->u.f1.reg.pr, "PR"); + + // RLR bitfields. + state->u.f1.fld.rlr.rl = cm_object_get_child_by_name(state->u.f1.reg.rlr, "RL"); + + // SR bitfields. + state->u.f1.fld.sr.pvu = cm_object_get_child_by_name(state->u.f1.reg.sr, "PVU"); + state->u.f1.fld.sr.rvu = cm_object_get_child_by_name(state->u.f1.reg.sr, "RVU"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_iwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_iwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_iwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_iwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_iwdg_is_enabled(Object *obj) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_iwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_iwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_IWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32IWDGState *state = STM32_IWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "IWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_iwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_iwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_iwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_iwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_iwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/IWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_iwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_IWDG); +} + +static void stm32_iwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_iwdg_reset_callback; + dc->realize = stm32_iwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_iwdg_is_enabled; +} + +static const TypeInfo stm32_iwdg_type_info = { + .name = TYPE_STM32_IWDG, + .parent = TYPE_STM32_IWDG_PARENT, + .instance_init = stm32_iwdg_instance_init_callback, + .instance_size = sizeof(STM32IWDGState), + .class_init = stm32_iwdg_class_init_callback, + .class_size = sizeof(STM32IWDGClass) }; + +static void stm32_iwdg_register_types(void) +{ + type_register_static(&stm32_iwdg_type_info); +} + +type_init(stm32_iwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/iwdg.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/iwdg.h new file mode 100644 index 0000000000..b1eeb71a8c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/iwdg.h @@ -0,0 +1,124 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_IWDG_H_ +#define STM32_IWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_IWDG DEVICE_PATH_STM32 "IWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_IWDG TYPE_STM32_PREFIX "iwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_IWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32IWDGParentClass; +typedef PeripheralState STM32IWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_IWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32IWDGClass, (obj), TYPE_STM32_IWDG) +#define STM32_IWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32IWDGClass, (klass), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentClass parent_class; + // public: + + // None, so far. +} STM32IWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_IWDG_STATE(obj) \ + OBJECT_CHECK(STM32IWDGState, (obj), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 IWDG (Independent watchdog) registers. + struct { + Object *kr; // 0x0 (Key register (IWDG_KR)) + Object *pr; // 0x4 (Prescaler register (IWDG_PR)) + Object *rlr; // 0x8 (Reload register (IWDG_RLR)) + Object *sr; // 0xC (Status register (IWDG_SR)) + } reg; + + struct { + + // KR (Key register (IWDG_KR)) bitfields. + struct { + Object *key; // [0:15] Key value + } kr; + + // PR (Prescaler register (IWDG_PR)) bitfields. + struct { + Object *pr; // [0:2] Prescaler divider + } pr; + + // RLR (Reload register (IWDG_RLR)) bitfields. + struct { + Object *rl; // [0:11] Watchdog counter reload value + } rlr; + + // SR (Status register (IWDG_SR)) bitfields. + struct { + Object *pvu; // [0:0] Watchdog prescaler value update + Object *rvu; // [1:1] Watchdog counter reload value update + } sr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32IWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_IWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/pwr.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/pwr.c new file mode 100644 index 0000000000..cef1485b9f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/pwr.c @@ -0,0 +1,251 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_pwr_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CR bitfields. + state->u.f1.fld.cr.lpds = cm_object_get_child_by_name(state->u.f1.reg.cr, "LPDS"); + state->u.f1.fld.cr.pdds = cm_object_get_child_by_name(state->u.f1.reg.cr, "PDDS"); + state->u.f1.fld.cr.cwuf = cm_object_get_child_by_name(state->u.f1.reg.cr, "CWUF"); + state->u.f1.fld.cr.csbf = cm_object_get_child_by_name(state->u.f1.reg.cr, "CSBF"); + state->u.f1.fld.cr.pvde = cm_object_get_child_by_name(state->u.f1.reg.cr, "PVDE"); + state->u.f1.fld.cr.pls = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLS"); + state->u.f1.fld.cr.dbp = cm_object_get_child_by_name(state->u.f1.reg.cr, "DBP"); + + // CSR bitfields. + state->u.f1.fld.csr.wuf = cm_object_get_child_by_name(state->u.f1.reg.csr, "WUF"); + state->u.f1.fld.csr.sbf = cm_object_get_child_by_name(state->u.f1.reg.csr, "SBF"); + state->u.f1.fld.csr.pvdo = cm_object_get_child_by_name(state->u.f1.reg.csr, "PVDO"); + state->u.f1.fld.csr.ewup = cm_object_get_child_by_name(state->u.f1.reg.csr, "EWUP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_pwr_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_pwr_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_pwr_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_pwr_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_pwr_is_enabled(Object *obj) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_pwr_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32PWRState *state = STM32_PWR_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_pwr_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_PWR)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32PWRState *state = STM32_PWR_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "PWR"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_pwr_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_pwr_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_pwr_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_pwr_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_pwr_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/PWREN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_pwr_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_PWR); +} + +static void stm32_pwr_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_pwr_reset_callback; + dc->realize = stm32_pwr_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_pwr_is_enabled; +} + +static const TypeInfo stm32_pwr_type_info = { + .name = TYPE_STM32_PWR, + .parent = TYPE_STM32_PWR_PARENT, + .instance_init = stm32_pwr_instance_init_callback, + .instance_size = sizeof(STM32PWRState), + .class_init = stm32_pwr_class_init_callback, + .class_size = sizeof(STM32PWRClass) }; + +static void stm32_pwr_register_types(void) +{ + type_register_static(&stm32_pwr_type_info); +} + +type_init(stm32_pwr_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/pwr.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/pwr.h new file mode 100644 index 0000000000..bd3ec3526f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/pwr.h @@ -0,0 +1,120 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_PWR_H_ +#define STM32_PWR_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_PWR DEVICE_PATH_STM32 "PWR" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_PWR TYPE_STM32_PREFIX "pwr" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_PWR_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32PWRParentClass; +typedef PeripheralState STM32PWRParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_PWR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32PWRClass, (obj), TYPE_STM32_PWR) +#define STM32_PWR_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32PWRClass, (klass), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentClass parent_class; + // public: + + // None, so far. +} STM32PWRClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_PWR_STATE(obj) \ + OBJECT_CHECK(STM32PWRState, (obj), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 PWR (Power control) registers. + struct { + Object *cr; // 0x0 (Power control register (PWR_CR)) + Object *csr; // 0x4 (Power control register (PWR_CR)) + } reg; + + struct { + + // CR (Power control register (PWR_CR)) bitfields. + struct { + Object *lpds; // [0:0] Low Power Deep Sleep + Object *pdds; // [1:1] Power Down Deep Sleep + Object *cwuf; // [2:2] Clear Wake-up Flag + Object *csbf; // [3:3] Clear STANDBY Flag + Object *pvde; // [4:4] Power Voltage Detector Enable + Object *pls; // [5:7] PVD Level Selection + Object *dbp; // [8:8] Disable Backup Domain write protection + } cr; + + // CSR (Power control register (PWR_CR)) bitfields. + struct { + Object *wuf; // [0:0] Wake-Up Flag + Object *sbf; // [1:1] STANDBY Flag + Object *pvdo; // [2:2] PVD Output + Object *ewup; // [8:8] Enable WKUP pin + } csr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32PWRState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_PWR_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/rcc.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/rcc.c new file mode 100644 index 0000000000..4c1ef72688 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/rcc.c @@ -0,0 +1,413 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_rcc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f1.reg.cir = cm_object_get_child_by_name(obj, "CIR"); + state->u.f1.reg.apb2rstr = cm_object_get_child_by_name(obj, "APB2RSTR"); + state->u.f1.reg.apb1rstr = cm_object_get_child_by_name(obj, "APB1RSTR"); + state->u.f1.reg.ahbenr = cm_object_get_child_by_name(obj, "AHBENR"); + state->u.f1.reg.apb2enr = cm_object_get_child_by_name(obj, "APB2ENR"); + state->u.f1.reg.apb1enr = cm_object_get_child_by_name(obj, "APB1ENR"); + state->u.f1.reg.bdcr = cm_object_get_child_by_name(obj, "BDCR"); + state->u.f1.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f1.reg.ahbrstr = cm_object_get_child_by_name(obj, "AHBRSTR"); + state->u.f1.reg.cfgr2 = cm_object_get_child_by_name(obj, "CFGR2"); + + + // CR bitfields. + state->u.f1.fld.cr.hsion = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSION"); + state->u.f1.fld.cr.hsirdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSIRDY"); + state->u.f1.fld.cr.hsitrim = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSITRIM"); + state->u.f1.fld.cr.hsical = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSICAL"); + state->u.f1.fld.cr.hseon = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSEON"); + state->u.f1.fld.cr.hserdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSERDY"); + state->u.f1.fld.cr.hsebyp = cm_object_get_child_by_name(state->u.f1.reg.cr, "HSEBYP"); + state->u.f1.fld.cr.csson = cm_object_get_child_by_name(state->u.f1.reg.cr, "CSSON"); + state->u.f1.fld.cr.pllon = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLLON"); + state->u.f1.fld.cr.pllrdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLLRDY"); + state->u.f1.fld.cr.pll2on = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLL2ON"); + state->u.f1.fld.cr.pll2rdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLL2RDY"); + state->u.f1.fld.cr.pll3on = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLL3ON"); + state->u.f1.fld.cr.pll3rdy = cm_object_get_child_by_name(state->u.f1.reg.cr, "PLL3RDY"); + + // CFGR bitfields. + state->u.f1.fld.cfgr.sw = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "SW"); + state->u.f1.fld.cfgr.sws = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "SWS"); + state->u.f1.fld.cfgr.hpre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "HPRE"); + state->u.f1.fld.cfgr.ppre1 = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PPRE1"); + state->u.f1.fld.cfgr.ppre2 = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PPRE2"); + state->u.f1.fld.cfgr.adcpre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "ADCPRE"); + state->u.f1.fld.cfgr.pllsrc = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PLLSRC"); + state->u.f1.fld.cfgr.pllxtpre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PLLXTPRE"); + state->u.f1.fld.cfgr.pllmul = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "PLLMUL"); + state->u.f1.fld.cfgr.otgfspre = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "OTGFSPRE"); + state->u.f1.fld.cfgr.mco = cm_object_get_child_by_name(state->u.f1.reg.cfgr, "MCO"); + + // CIR bitfields. + state->u.f1.fld.cir.lsirdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSIRDYF"); + state->u.f1.fld.cir.lserdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSERDYF"); + state->u.f1.fld.cir.hsirdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSIRDYF"); + state->u.f1.fld.cir.hserdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSERDYF"); + state->u.f1.fld.cir.pllrdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLLRDYF"); + state->u.f1.fld.cir.pll2rdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLL2RDYF"); + state->u.f1.fld.cir.pll3rdyf = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLL3RDYF"); + state->u.f1.fld.cir.cssf = cm_object_get_child_by_name(state->u.f1.reg.cir, "CSSF"); + state->u.f1.fld.cir.lsirdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSIRDYIE"); + state->u.f1.fld.cir.lserdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSERDYIE"); + state->u.f1.fld.cir.hsirdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSIRDYIE"); + state->u.f1.fld.cir.hserdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSERDYIE"); + state->u.f1.fld.cir.pllrdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLLRDYIE"); + state->u.f1.fld.cir.pll2rdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLL2RDYIE"); + state->u.f1.fld.cir.pll3rdyie = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLL3RDYIE"); + state->u.f1.fld.cir.lsirdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSIRDYC"); + state->u.f1.fld.cir.lserdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "LSERDYC"); + state->u.f1.fld.cir.hsirdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSIRDYC"); + state->u.f1.fld.cir.hserdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "HSERDYC"); + state->u.f1.fld.cir.pllrdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLLRDYC"); + state->u.f1.fld.cir.pll2rdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLL2RDYC"); + state->u.f1.fld.cir.pll3rdyc = cm_object_get_child_by_name(state->u.f1.reg.cir, "PLL3RDYC"); + state->u.f1.fld.cir.cssc = cm_object_get_child_by_name(state->u.f1.reg.cir, "CSSC"); + + // APB2RSTR bitfields. + state->u.f1.fld.apb2rstr.afiorst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "AFIORST"); + state->u.f1.fld.apb2rstr.ioparst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPARST"); + state->u.f1.fld.apb2rstr.iopbrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPBRST"); + state->u.f1.fld.apb2rstr.iopcrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPCRST"); + state->u.f1.fld.apb2rstr.iopdrst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPDRST"); + state->u.f1.fld.apb2rstr.ioperst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "IOPERST"); + state->u.f1.fld.apb2rstr.adc1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "ADC1RST"); + state->u.f1.fld.apb2rstr.adc2rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "ADC2RST"); + state->u.f1.fld.apb2rstr.tim1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "TIM1RST"); + state->u.f1.fld.apb2rstr.spi1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "SPI1RST"); + state->u.f1.fld.apb2rstr.usart1rst = cm_object_get_child_by_name(state->u.f1.reg.apb2rstr, "USART1RST"); + + // APB1RSTR bitfields. + state->u.f1.fld.apb1rstr.tim2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM2RST"); + state->u.f1.fld.apb1rstr.tim3rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM3RST"); + state->u.f1.fld.apb1rstr.tim4rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM4RST"); + state->u.f1.fld.apb1rstr.tim5rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM5RST"); + state->u.f1.fld.apb1rstr.tim6rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM6RST"); + state->u.f1.fld.apb1rstr.tim7rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "TIM7RST"); + state->u.f1.fld.apb1rstr.wwdgrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "WWDGRST"); + state->u.f1.fld.apb1rstr.spi2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "SPI2RST"); + state->u.f1.fld.apb1rstr.spi3rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "SPI3RST"); + state->u.f1.fld.apb1rstr.usart2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "USART2RST"); + state->u.f1.fld.apb1rstr.usart3rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "USART3RST"); + state->u.f1.fld.apb1rstr.usart4rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "USART4RST"); + state->u.f1.fld.apb1rstr.usart5rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "USART5RST"); + state->u.f1.fld.apb1rstr.i2c1rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "I2C1RST"); + state->u.f1.fld.apb1rstr.i2c2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "I2C2RST"); + state->u.f1.fld.apb1rstr.can1rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "CAN1RST"); + state->u.f1.fld.apb1rstr.can2rst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "CAN2RST"); + state->u.f1.fld.apb1rstr.bkprst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "BKPRST"); + state->u.f1.fld.apb1rstr.pwrrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "PWRRST"); + state->u.f1.fld.apb1rstr.dacrst = cm_object_get_child_by_name(state->u.f1.reg.apb1rstr, "DACRST"); + + // AHBENR bitfields. + state->u.f1.fld.ahbenr.dma1en = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "DMA1EN"); + state->u.f1.fld.ahbenr.dma2en = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "DMA2EN"); + state->u.f1.fld.ahbenr.sramen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "SRAMEN"); + state->u.f1.fld.ahbenr.flitfen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "FLITFEN"); + state->u.f1.fld.ahbenr.crcen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "CRCEN"); + state->u.f1.fld.ahbenr.otgfsen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "OTGFSEN"); + state->u.f1.fld.ahbenr.ethmacen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "ETHMACEN"); + state->u.f1.fld.ahbenr.ethmactxen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "ETHMACTXEN"); + state->u.f1.fld.ahbenr.ethmacrxen = cm_object_get_child_by_name(state->u.f1.reg.ahbenr, "ETHMACRXEN"); + + // APB2ENR bitfields. + state->u.f1.fld.apb2enr.afioen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "AFIOEN"); + state->u.f1.fld.apb2enr.iopaen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPAEN"); + state->u.f1.fld.apb2enr.iopben = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPBEN"); + state->u.f1.fld.apb2enr.iopcen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPCEN"); + state->u.f1.fld.apb2enr.iopden = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPDEN"); + state->u.f1.fld.apb2enr.iopeen = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "IOPEEN"); + state->u.f1.fld.apb2enr.adc1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "ADC1EN"); + state->u.f1.fld.apb2enr.adc2en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "ADC2EN"); + state->u.f1.fld.apb2enr.tim1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "TIM1EN"); + state->u.f1.fld.apb2enr.spi1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "SPI1EN"); + state->u.f1.fld.apb2enr.usart1en = cm_object_get_child_by_name(state->u.f1.reg.apb2enr, "USART1EN"); + + // APB1ENR bitfields. + state->u.f1.fld.apb1enr.tim2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM2EN"); + state->u.f1.fld.apb1enr.tim3en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM3EN"); + state->u.f1.fld.apb1enr.tim4en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM4EN"); + state->u.f1.fld.apb1enr.tim5en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM5EN"); + state->u.f1.fld.apb1enr.tim6en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM6EN"); + state->u.f1.fld.apb1enr.tim7en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "TIM7EN"); + state->u.f1.fld.apb1enr.wwdgen = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "WWDGEN"); + state->u.f1.fld.apb1enr.spi2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "SPI2EN"); + state->u.f1.fld.apb1enr.spi3en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "SPI3EN"); + state->u.f1.fld.apb1enr.usart2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "USART2EN"); + state->u.f1.fld.apb1enr.usart3en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "USART3EN"); + state->u.f1.fld.apb1enr.uart4en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "UART4EN"); + state->u.f1.fld.apb1enr.uart5en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "UART5EN"); + state->u.f1.fld.apb1enr.i2c1en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "I2C1EN"); + state->u.f1.fld.apb1enr.i2c2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "I2C2EN"); + state->u.f1.fld.apb1enr.can1en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "CAN1EN"); + state->u.f1.fld.apb1enr.can2en = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "CAN2EN"); + state->u.f1.fld.apb1enr.bkpen = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "BKPEN"); + state->u.f1.fld.apb1enr.pwren = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "PWREN"); + state->u.f1.fld.apb1enr.dacen = cm_object_get_child_by_name(state->u.f1.reg.apb1enr, "DACEN"); + + // BDCR bitfields. + state->u.f1.fld.bdcr.lseon = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "LSEON"); + state->u.f1.fld.bdcr.lserdy = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "LSERDY"); + state->u.f1.fld.bdcr.lsebyp = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "LSEBYP"); + state->u.f1.fld.bdcr.rtcsel = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "RTCSEL"); + state->u.f1.fld.bdcr.rtcen = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "RTCEN"); + state->u.f1.fld.bdcr.bdrst = cm_object_get_child_by_name(state->u.f1.reg.bdcr, "BDRST"); + + // CSR bitfields. + state->u.f1.fld.csr.lsion = cm_object_get_child_by_name(state->u.f1.reg.csr, "LSION"); + state->u.f1.fld.csr.lsirdy = cm_object_get_child_by_name(state->u.f1.reg.csr, "LSIRDY"); + state->u.f1.fld.csr.rmvf = cm_object_get_child_by_name(state->u.f1.reg.csr, "RMVF"); + state->u.f1.fld.csr.pinrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "PINRSTF"); + state->u.f1.fld.csr.porrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "PORRSTF"); + state->u.f1.fld.csr.sftrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "SFTRSTF"); + state->u.f1.fld.csr.iwdgrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "IWDGRSTF"); + state->u.f1.fld.csr.wwdgrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "WWDGRSTF"); + state->u.f1.fld.csr.lpwrrstf = cm_object_get_child_by_name(state->u.f1.reg.csr, "LPWRRSTF"); + + // AHBRSTR bitfields. + state->u.f1.fld.ahbrstr.otgfsrst = cm_object_get_child_by_name(state->u.f1.reg.ahbrstr, "OTGFSRST"); + state->u.f1.fld.ahbrstr.ethmacrst = cm_object_get_child_by_name(state->u.f1.reg.ahbrstr, "ETHMACRST"); + + // CFGR2 bitfields. + state->u.f1.fld.cfgr2.prediv1 = cm_object_get_child_by_name(state->u.f1.reg.cfgr2, "PREDIV1"); + state->u.f1.fld.cfgr2.prediv2 = cm_object_get_child_by_name(state->u.f1.reg.cfgr2, "PREDIV2"); + state->u.f1.fld.cfgr2.pll2mul = cm_object_get_child_by_name(state->u.f1.reg.cfgr2, "PLL2MUL"); + state->u.f1.fld.cfgr2.pll3mul = cm_object_get_child_by_name(state->u.f1.reg.cfgr2, "PLL3MUL"); + state->u.f1.fld.cfgr2.prediv1src = cm_object_get_child_by_name(state->u.f1.reg.cfgr2, "PREDIV1SRC"); + state->u.f1.fld.cfgr2.i2s2src = cm_object_get_child_by_name(state->u.f1.reg.cfgr2, "I2S2SRC"); + state->u.f1.fld.cfgr2.i2s3src = cm_object_get_child_by_name(state->u.f1.reg.cfgr2, "I2S3SRC"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rcc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rcc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rcc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rcc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rcc_is_enabled(Object *obj) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rcc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RCCState *state = STM32_RCC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rcc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RCC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RCCState *state = STM32_RCC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RCC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_rcc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rcc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_rcc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rcc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_rcc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RCCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rcc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RCC); +} + +static void stm32_rcc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rcc_reset_callback; + dc->realize = stm32_rcc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rcc_is_enabled; +} + +static const TypeInfo stm32_rcc_type_info = { + .name = TYPE_STM32_RCC, + .parent = TYPE_STM32_RCC_PARENT, + .instance_init = stm32_rcc_instance_init_callback, + .instance_size = sizeof(STM32RCCState), + .class_init = stm32_rcc_class_init_callback, + .class_size = sizeof(STM32RCCClass) }; + +static void stm32_rcc_register_types(void) +{ + type_register_static(&stm32_rcc_type_info); +} + +type_init(stm32_rcc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/rcc.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/rcc.h new file mode 100644 index 0000000000..d9ce512ec0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/rcc.h @@ -0,0 +1,302 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RCC_H_ +#define STM32_RCC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RCC DEVICE_PATH_STM32 "RCC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RCC TYPE_STM32_PREFIX "rcc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RCC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RCCParentClass; +typedef PeripheralState STM32RCCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RCCClass, (obj), TYPE_STM32_RCC) +#define STM32_RCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RCCClass, (klass), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentClass parent_class; + // public: + + // None, so far. +} STM32RCCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RCC_STATE(obj) \ + OBJECT_CHECK(STM32RCCState, (obj), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 RCC (Reset and clock control) registers. + struct { + Object *cr; // 0x0 (Clock control register) + Object *cfgr; // 0x4 (Clock configuration register (RCC_CFGR)) + Object *cir; // 0x8 (Clock interrupt register (RCC_CIR)) + Object *apb2rstr; // 0xC (APB2 peripheral reset register (RCC_APB2RSTR)) + Object *apb1rstr; // 0x10 (APB1 peripheral reset register (RCC_APB1RSTR)) + Object *ahbenr; // 0x14 (AHB Peripheral Clock enable register (RCC_AHBENR)) + Object *apb2enr; // 0x18 (APB2 peripheral clock enable register (RCC_APB2ENR)) + Object *apb1enr; // 0x1C (APB1 peripheral clock enable register (RCC_APB1ENR)) + Object *bdcr; // 0x20 (Backup domain control register (RCC_BDCR)) + Object *csr; // 0x24 (Control/status register (RCC_CSR)) + Object *ahbrstr; // 0x28 (AHB peripheral clock reset register (RCC_AHBRSTR)) + Object *cfgr2; // 0x2C (Clock configuration register2 (RCC_CFGR2)) + } reg; + + struct { + + // CR (Clock control register) bitfields. + struct { + Object *hsion; // [0:0] Internal High Speed clock enable + Object *hsirdy; // [1:1] Internal High Speed clock ready flag + Object *hsitrim; // [3:7] Internal High Speed clock trimming + Object *hsical; // [8:15] Internal High Speed clock Calibration + Object *hseon; // [16:16] External High Speed clock enable + Object *hserdy; // [17:17] External High Speed clock ready flag + Object *hsebyp; // [18:18] External High Speed clock Bypass + Object *csson; // [19:19] Clock Security System enable + Object *pllon; // [24:24] PLL enable + Object *pllrdy; // [25:25] PLL clock ready flag + Object *pll2on; // [26:26] PLL2 enable + Object *pll2rdy; // [27:27] PLL2 clock ready flag + Object *pll3on; // [28:28] PLL3 enable + Object *pll3rdy; // [29:29] PLL3 clock ready flag + } cr; + + // CFGR (Clock configuration register (RCC_CFGR)) bitfields. + struct { + Object *sw; // [0:1] System clock Switch + Object *sws; // [2:3] System Clock Switch Status + Object *hpre; // [4:7] AHB prescaler + Object *ppre1; // [8:10] APB Low speed prescaler (APB1) + Object *ppre2; // [11:13] APB High speed prescaler (APB2) + Object *adcpre; // [14:15] ADC prescaler + Object *pllsrc; // [16:16] PLL entry clock source + Object *pllxtpre; // [17:17] HSE divider for PLL entry + Object *pllmul; // [18:21] PLL Multiplication Factor + Object *otgfspre; // [22:22] USB OTG FS prescaler + Object *mco; // [24:27] Microcontroller clock output + } cfgr; + + // CIR (Clock interrupt register (RCC_CIR)) bitfields. + struct { + Object *lsirdyf; // [0:0] LSI Ready Interrupt flag + Object *lserdyf; // [1:1] LSE Ready Interrupt flag + Object *hsirdyf; // [2:2] HSI Ready Interrupt flag + Object *hserdyf; // [3:3] HSE Ready Interrupt flag + Object *pllrdyf; // [4:4] PLL Ready Interrupt flag + Object *pll2rdyf; // [5:5] PLL2 Ready Interrupt flag + Object *pll3rdyf; // [6:6] PLL3 Ready Interrupt flag + Object *cssf; // [7:7] Clock Security System Interrupt flag + Object *lsirdyie; // [8:8] LSI Ready Interrupt Enable + Object *lserdyie; // [9:9] LSE Ready Interrupt Enable + Object *hsirdyie; // [10:10] HSI Ready Interrupt Enable + Object *hserdyie; // [11:11] HSE Ready Interrupt Enable + Object *pllrdyie; // [12:12] PLL Ready Interrupt Enable + Object *pll2rdyie; // [13:13] PLL2 Ready Interrupt Enable + Object *pll3rdyie; // [14:14] PLL3 Ready Interrupt Enable + Object *lsirdyc; // [16:16] LSI Ready Interrupt Clear + Object *lserdyc; // [17:17] LSE Ready Interrupt Clear + Object *hsirdyc; // [18:18] HSI Ready Interrupt Clear + Object *hserdyc; // [19:19] HSE Ready Interrupt Clear + Object *pllrdyc; // [20:20] PLL Ready Interrupt Clear + Object *pll2rdyc; // [21:21] PLL2 Ready Interrupt Clear + Object *pll3rdyc; // [22:22] PLL3 Ready Interrupt Clear + Object *cssc; // [23:23] Clock security system interrupt clear + } cir; + + // APB2RSTR (APB2 peripheral reset register (RCC_APB2RSTR)) bitfields. + struct { + Object *afiorst; // [0:0] Alternate function I/O reset + Object *ioparst; // [2:2] IO port A reset + Object *iopbrst; // [3:3] IO port B reset + Object *iopcrst; // [4:4] IO port C reset + Object *iopdrst; // [5:5] IO port D reset + Object *ioperst; // [6:6] IO port E reset + Object *adc1rst; // [9:9] ADC 1 interface reset + Object *adc2rst; // [10:10] ADC 2 interface reset + Object *tim1rst; // [11:11] TIM1 timer reset + Object *spi1rst; // [12:12] SPI 1 reset + Object *usart1rst; // [14:14] USART1 reset + } apb2rstr; + + // APB1RSTR (APB1 peripheral reset register (RCC_APB1RSTR)) bitfields. + struct { + Object *tim2rst; // [0:0] Timer 2 reset + Object *tim3rst; // [1:1] Timer 3 reset + Object *tim4rst; // [2:2] Timer 4 reset + Object *tim5rst; // [3:3] Timer 5 reset + Object *tim6rst; // [4:4] Timer 6 reset + Object *tim7rst; // [5:5] Timer 7 reset + Object *wwdgrst; // [11:11] Window watchdog reset + Object *spi2rst; // [14:14] SPI2 reset + Object *spi3rst; // [15:15] SPI3 reset + Object *usart2rst; // [17:17] USART 2 reset + Object *usart3rst; // [18:18] USART 3 reset + Object *usart4rst; // [19:19] USART 4 reset + Object *usart5rst; // [20:20] USART 5 reset + Object *i2c1rst; // [21:21] I2C1 reset + Object *i2c2rst; // [22:22] I2C2 reset + Object *can1rst; // [25:25] CAN1 reset + Object *can2rst; // [26:26] CAN2 reset + Object *bkprst; // [27:27] Backup interface reset + Object *pwrrst; // [28:28] Power interface reset + Object *dacrst; // [29:29] DAC interface reset + } apb1rstr; + + // AHBENR (AHB Peripheral Clock enable register (RCC_AHBENR)) bitfields. + struct { + Object *dma1en; // [0:0] DMA1 clock enable + Object *dma2en; // [1:1] DMA2 clock enable + Object *sramen; // [2:2] SRAM interface clock enable + Object *flitfen; // [4:4] FLITF clock enable + Object *crcen; // [6:6] CRC clock enable + Object *otgfsen; // [12:12] USB OTG FS clock enable + Object *ethmacen; // [14:14] Ethernet MAC clock enable + Object *ethmactxen; // [15:15] Ethernet MAC TX clock enable + Object *ethmacrxen; // [16:16] Ethernet MAC RX clock enable + } ahbenr; + + // APB2ENR (APB2 peripheral clock enable register (RCC_APB2ENR)) bitfields. + struct { + Object *afioen; // [0:0] Alternate function I/O clock enable + Object *iopaen; // [2:2] I/O port A clock enable + Object *iopben; // [3:3] I/O port B clock enable + Object *iopcen; // [4:4] I/O port C clock enable + Object *iopden; // [5:5] I/O port D clock enable + Object *iopeen; // [6:6] I/O port E clock enable + Object *adc1en; // [9:9] ADC 1 interface clock enable + Object *adc2en; // [10:10] ADC 2 interface clock enable + Object *tim1en; // [11:11] TIM1 Timer clock enable + Object *spi1en; // [12:12] SPI 1 clock enable + Object *usart1en; // [14:14] USART1 clock enable + } apb2enr; + + // APB1ENR (APB1 peripheral clock enable register (RCC_APB1ENR)) bitfields. + struct { + Object *tim2en; // [0:0] Timer 2 clock enable + Object *tim3en; // [1:1] Timer 3 clock enable + Object *tim4en; // [2:2] Timer 4 clock enable + Object *tim5en; // [3:3] Timer 5 clock enable + Object *tim6en; // [4:4] Timer 6 clock enable + Object *tim7en; // [5:5] Timer 7 clock enable + Object *wwdgen; // [11:11] Window watchdog clock enable + Object *spi2en; // [14:14] SPI 2 clock enable + Object *spi3en; // [15:15] SPI 3 clock enable + Object *usart2en; // [17:17] USART 2 clock enable + Object *usart3en; // [18:18] USART 3 clock enable + Object *uart4en; // [19:19] UART 4 clock enable + Object *uart5en; // [20:20] UART 5 clock enable + Object *i2c1en; // [21:21] I2C 1 clock enable + Object *i2c2en; // [22:22] I2C 2 clock enable + Object *can1en; // [25:25] CAN1 clock enable + Object *can2en; // [26:26] CAN2 clock enable + Object *bkpen; // [27:27] Backup interface clock enable + Object *pwren; // [28:28] Power interface clock enable + Object *dacen; // [29:29] DAC interface clock enable + } apb1enr; + + // BDCR (Backup domain control register (RCC_BDCR)) bitfields. + struct { + Object *lseon; // [0:0] External Low Speed oscillator enable + Object *lserdy; // [1:1] External Low Speed oscillator ready + Object *lsebyp; // [2:2] External Low Speed oscillator bypass + Object *rtcsel; // [8:9] RTC clock source selection + Object *rtcen; // [15:15] RTC clock enable + Object *bdrst; // [16:16] Backup domain software reset + } bdcr; + + // CSR (Control/status register (RCC_CSR)) bitfields. + struct { + Object *lsion; // [0:0] Internal low speed oscillator enable + Object *lsirdy; // [1:1] Internal low speed oscillator ready + Object *rmvf; // [24:24] Remove reset flag + Object *pinrstf; // [26:26] PIN reset flag + Object *porrstf; // [27:27] POR/PDR reset flag + Object *sftrstf; // [28:28] Software reset flag + Object *iwdgrstf; // [29:29] Independent watchdog reset flag + Object *wwdgrstf; // [30:30] Window watchdog reset flag + Object *lpwrrstf; // [31:31] Low-power reset flag + } csr; + + // AHBRSTR (AHB peripheral clock reset register (RCC_AHBRSTR)) bitfields. + struct { + Object *otgfsrst; // [12:12] USB OTG FS reset + Object *ethmacrst; // [14:14] Ethernet MAC reset + } ahbrstr; + + // CFGR2 (Clock configuration register2 (RCC_CFGR2)) bitfields. + struct { + Object *prediv1; // [0:3] PREDIV1 division factor + Object *prediv2; // [4:7] PREDIV2 division factor + Object *pll2mul; // [8:11] PLL2 Multiplication Factor + Object *pll3mul; // [12:15] PLL3 Multiplication Factor + Object *prediv1src; // [16:16] PREDIV1 entry clock source + Object *i2s2src; // [17:17] I2S2 clock source + Object *i2s3src; // [18:18] I2S3 clock source + } cfgr2; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RCCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RCC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/rtc.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/rtc.c new file mode 100644 index 0000000000..ccd56b2c84 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/rtc.c @@ -0,0 +1,281 @@ +/* + * STM32 - RTC (Real time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_rtc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.crh = cm_object_get_child_by_name(obj, "CRH"); + state->u.f1.reg.crl = cm_object_get_child_by_name(obj, "CRL"); + state->u.f1.reg.prlh = cm_object_get_child_by_name(obj, "PRLH"); + state->u.f1.reg.prll = cm_object_get_child_by_name(obj, "PRLL"); + state->u.f1.reg.divh = cm_object_get_child_by_name(obj, "DIVH"); + state->u.f1.reg.divl = cm_object_get_child_by_name(obj, "DIVL"); + state->u.f1.reg.cnth = cm_object_get_child_by_name(obj, "CNTH"); + state->u.f1.reg.cntl = cm_object_get_child_by_name(obj, "CNTL"); + state->u.f1.reg.alrh = cm_object_get_child_by_name(obj, "ALRH"); + state->u.f1.reg.alrl = cm_object_get_child_by_name(obj, "ALRL"); + + + // CRH bitfields. + state->u.f1.fld.crh.secie = cm_object_get_child_by_name(state->u.f1.reg.crh, "SECIE"); + state->u.f1.fld.crh.alrie = cm_object_get_child_by_name(state->u.f1.reg.crh, "ALRIE"); + state->u.f1.fld.crh.owie = cm_object_get_child_by_name(state->u.f1.reg.crh, "OWIE"); + + // CRL bitfields. + state->u.f1.fld.crl.secf = cm_object_get_child_by_name(state->u.f1.reg.crl, "SECF"); + state->u.f1.fld.crl.alrf = cm_object_get_child_by_name(state->u.f1.reg.crl, "ALRF"); + state->u.f1.fld.crl.owf = cm_object_get_child_by_name(state->u.f1.reg.crl, "OWF"); + state->u.f1.fld.crl.rsf = cm_object_get_child_by_name(state->u.f1.reg.crl, "RSF"); + state->u.f1.fld.crl.cnf = cm_object_get_child_by_name(state->u.f1.reg.crl, "CNF"); + state->u.f1.fld.crl.rtoff = cm_object_get_child_by_name(state->u.f1.reg.crl, "RTOFF"); + + // PRLH bitfields. + state->u.f1.fld.prlh.prlh = cm_object_get_child_by_name(state->u.f1.reg.prlh, "PRLH"); + + // PRLL bitfields. + state->u.f1.fld.prll.prll = cm_object_get_child_by_name(state->u.f1.reg.prll, "PRLL"); + + // DIVH bitfields. + state->u.f1.fld.divh.divh = cm_object_get_child_by_name(state->u.f1.reg.divh, "DIVH"); + + // DIVL bitfields. + state->u.f1.fld.divl.divl = cm_object_get_child_by_name(state->u.f1.reg.divl, "DIVL"); + + // CNTH bitfields. + state->u.f1.fld.cnth.cnth = cm_object_get_child_by_name(state->u.f1.reg.cnth, "CNTH"); + + // CNTL bitfields. + state->u.f1.fld.cntl.cntl = cm_object_get_child_by_name(state->u.f1.reg.cntl, "CNTL"); + + // ALRH bitfields. + state->u.f1.fld.alrh.alrh = cm_object_get_child_by_name(state->u.f1.reg.alrh, "ALRH"); + + // ALRL bitfields. + state->u.f1.fld.alrl.alrl = cm_object_get_child_by_name(state->u.f1.reg.alrl, "ALRL"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rtc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rtc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rtc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rtc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rtc_is_enabled(Object *obj) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rtc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RTCState *state = STM32_RTC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rtc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RTC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RTCState *state = STM32_RTC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RTC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_rtc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rtc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_rtc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_rtc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_rtc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RTCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rtc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RTC); +} + +static void stm32_rtc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rtc_reset_callback; + dc->realize = stm32_rtc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rtc_is_enabled; +} + +static const TypeInfo stm32_rtc_type_info = { + .name = TYPE_STM32_RTC, + .parent = TYPE_STM32_RTC_PARENT, + .instance_init = stm32_rtc_instance_init_callback, + .instance_size = sizeof(STM32RTCState), + .class_init = stm32_rtc_class_init_callback, + .class_size = sizeof(STM32RTCClass) }; + +static void stm32_rtc_register_types(void) +{ + type_register_static(&stm32_rtc_type_info); +} + +type_init(stm32_rtc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/rtc.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/rtc.h new file mode 100644 index 0000000000..36b03457b1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/rtc.h @@ -0,0 +1,166 @@ +/* + * STM32 - RTC (Real time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RTC_H_ +#define STM32_RTC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RTC DEVICE_PATH_STM32 "RTC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RTC TYPE_STM32_PREFIX "rtc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RTC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RTCParentClass; +typedef PeripheralState STM32RTCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RTCClass, (obj), TYPE_STM32_RTC) +#define STM32_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RTCClass, (klass), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentClass parent_class; + // public: + + // None, so far. +} STM32RTCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RTC_STATE(obj) \ + OBJECT_CHECK(STM32RTCState, (obj), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 RTC (Real time clock) registers. + struct { + Object *crh; // 0x0 (RTC Control Register High) + Object *crl; // 0x4 (RTC Control Register Low) + Object *prlh; // 0x8 (RTC Prescaler Load Register High) + Object *prll; // 0xC (RTC Prescaler Load Register Low) + Object *divh; // 0x10 (RTC Prescaler Divider Register High) + Object *divl; // 0x14 (RTC Prescaler Divider Register Low) + Object *cnth; // 0x18 (RTC Counter Register High) + Object *cntl; // 0x1C (RTC Counter Register Low) + Object *alrh; // 0x20 (RTC Alarm Register High) + Object *alrl; // 0x24 (RTC Alarm Register Low) + } reg; + + struct { + + // CRH (RTC Control Register High) bitfields. + struct { + Object *secie; // [0:0] Second interrupt Enable + Object *alrie; // [1:1] Alarm interrupt Enable + Object *owie; // [2:2] Overflow interrupt Enable + } crh; + + // CRL (RTC Control Register Low) bitfields. + struct { + Object *secf; // [0:0] Second Flag + Object *alrf; // [1:1] Alarm Flag + Object *owf; // [2:2] Overflow Flag + Object *rsf; // [3:3] Registers Synchronized Flag + Object *cnf; // [4:4] Configuration Flag + Object *rtoff; // [5:5] RTC operation OFF + } crl; + + // PRLH (RTC Prescaler Load Register High) bitfields. + struct { + Object *prlh; // [0:3] RTC Prescaler Load Register High + } prlh; + + // PRLL (RTC Prescaler Load Register Low) bitfields. + struct { + Object *prll; // [0:15] RTC Prescaler Divider Register Low + } prll; + + // DIVH (RTC Prescaler Divider Register High) bitfields. + struct { + Object *divh; // [0:3] RTC prescaler divider register high + } divh; + + // DIVL (RTC Prescaler Divider Register Low) bitfields. + struct { + Object *divl; // [0:15] RTC prescaler divider register Low + } divl; + + // CNTH (RTC Counter Register High) bitfields. + struct { + Object *cnth; // [0:15] RTC counter register high + } cnth; + + // CNTL (RTC Counter Register Low) bitfields. + struct { + Object *cntl; // [0:15] RTC counter register Low + } cntl; + + // ALRH (RTC Alarm Register High) bitfields. + struct { + Object *alrh; // [0:15] RTC alarm register high + } alrh; + + // ALRL (RTC Alarm Register Low) bitfields. + struct { + Object *alrl; // [0:15] RTC alarm register low + } alrl; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RTCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RTC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/spi1.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/spi1.c new file mode 100644 index 0000000000..32e90b9bb6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/spi1.c @@ -0,0 +1,309 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_spi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.crcpr = cm_object_get_child_by_name(obj, "CRCPR"); + state->u.f1.reg.rxcrcr = cm_object_get_child_by_name(obj, "RXCRCR"); + state->u.f1.reg.txcrcr = cm_object_get_child_by_name(obj, "TXCRCR"); + state->u.f1.reg.i2scfgr = cm_object_get_child_by_name(obj, "I2SCFGR"); + state->u.f1.reg.i2spr = cm_object_get_child_by_name(obj, "I2SPR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cpha = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CPHA"); + state->u.f1.fld.cr1.cpol = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CPOL"); + state->u.f1.fld.cr1.mstr = cm_object_get_child_by_name(state->u.f1.reg.cr1, "MSTR"); + state->u.f1.fld.cr1.br = cm_object_get_child_by_name(state->u.f1.reg.cr1, "BR"); + state->u.f1.fld.cr1.spe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SPE"); + state->u.f1.fld.cr1.lsbfirst = cm_object_get_child_by_name(state->u.f1.reg.cr1, "LSBFIRST"); + state->u.f1.fld.cr1.ssi = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SSI"); + state->u.f1.fld.cr1.ssm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SSM"); + state->u.f1.fld.cr1.rxonly = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXONLY"); + state->u.f1.fld.cr1.dff = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DFF"); + state->u.f1.fld.cr1.crcnext = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CRCNEXT"); + state->u.f1.fld.cr1.crcen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CRCEN"); + state->u.f1.fld.cr1.bidioe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "BIDIOE"); + state->u.f1.fld.cr1.bidimode = cm_object_get_child_by_name(state->u.f1.reg.cr1, "BIDIMODE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.rxdmaen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RXDMAEN"); + state->u.f1.fld.cr2.txdmaen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TXDMAEN"); + state->u.f1.fld.cr2.ssoe = cm_object_get_child_by_name(state->u.f1.reg.cr2, "SSOE"); + state->u.f1.fld.cr2.errie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ERRIE"); + state->u.f1.fld.cr2.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "RXNEIE"); + state->u.f1.fld.cr2.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TXEIE"); + + // SR bitfields. + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.chside = cm_object_get_child_by_name(state->u.f1.reg.sr, "CHSIDE"); + state->u.f1.fld.sr.udr = cm_object_get_child_by_name(state->u.f1.reg.sr, "UDR"); + state->u.f1.fld.sr.crcerr = cm_object_get_child_by_name(state->u.f1.reg.sr, "CRCERR"); + state->u.f1.fld.sr.modf = cm_object_get_child_by_name(state->u.f1.reg.sr, "MODF"); + state->u.f1.fld.sr.ovr = cm_object_get_child_by_name(state->u.f1.reg.sr, "OVR"); + state->u.f1.fld.sr.bsy = cm_object_get_child_by_name(state->u.f1.reg.sr, "BSY"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // CRCPR bitfields. + state->u.f1.fld.crcpr.crcpoly = cm_object_get_child_by_name(state->u.f1.reg.crcpr, "CRCPOLY"); + + // RXCRCR bitfields. + state->u.f1.fld.rxcrcr.rxcrc = cm_object_get_child_by_name(state->u.f1.reg.rxcrcr, "RxCRC"); + + // TXCRCR bitfields. + state->u.f1.fld.txcrcr.txcrc = cm_object_get_child_by_name(state->u.f1.reg.txcrcr, "TxCRC"); + + // I2SCFGR bitfields. + state->u.f1.fld.i2scfgr.chlen = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "CHLEN"); + state->u.f1.fld.i2scfgr.datlen = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "DATLEN"); + state->u.f1.fld.i2scfgr.ckpol = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "CKPOL"); + state->u.f1.fld.i2scfgr.i2sstd = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SSTD"); + state->u.f1.fld.i2scfgr.pcmsync = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "PCMSYNC"); + state->u.f1.fld.i2scfgr.i2scfg = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SCFG"); + state->u.f1.fld.i2scfgr.i2se = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SE"); + state->u.f1.fld.i2scfgr.i2smod = cm_object_get_child_by_name(state->u.f1.reg.i2scfgr, "I2SMOD"); + + // I2SPR bitfields. + state->u.f1.fld.i2spr.i2sdiv = cm_object_get_child_by_name(state->u.f1.reg.i2spr, "I2SDIV"); + state->u.f1.fld.i2spr.odd = cm_object_get_child_by_name(state->u.f1.reg.i2spr, "ODD"); + state->u.f1.fld.i2spr.mckoe = cm_object_get_child_by_name(state->u.f1.reg.i2spr, "MCKOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_spi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_spi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_spi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_spi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_spi_is_enabled(Object *obj) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_spi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SPIState *state = STM32_SPI_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_SPI_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_spi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SPI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SPIState *state = STM32_SPI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SPI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_spi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_spi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_spi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_spi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_spi_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SPI%dEN", + 1 + state->port_index - STM32_PORT_SPI1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_spi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SPI); +} + +static void stm32_spi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_spi_reset_callback; + dc->realize = stm32_spi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_spi_is_enabled; +} + +static const TypeInfo stm32_spi_type_info = { + .name = TYPE_STM32_SPI, + .parent = TYPE_STM32_SPI_PARENT, + .instance_init = stm32_spi_instance_init_callback, + .instance_size = sizeof(STM32SPIState), + .class_init = stm32_spi_class_init_callback, + .class_size = sizeof(STM32SPIClass) }; + +static void stm32_spi_register_types(void) +{ + type_register_static(&stm32_spi_type_info); +} + +type_init(stm32_spi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/spi1.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/spi1.h new file mode 100644 index 0000000000..e31c614200 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/spi1.h @@ -0,0 +1,199 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SPI_H_ +#define STM32_SPI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SPI DEVICE_PATH_STM32 "SPI" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_SPI1, + STM32_PORT_SPI2, + STM32_PORT_SPI3, + STM32_PORT_SPI_UNDEFINED = 0xFF, +} stm32_spi_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SPI TYPE_STM32_PREFIX "spi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SPI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SPIParentClass; +typedef PeripheralState STM32SPIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SPI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SPIClass, (obj), TYPE_STM32_SPI) +#define STM32_SPI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SPIClass, (klass), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentClass parent_class; + // public: + + // None, so far. +} STM32SPIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SPI_STATE(obj) \ + OBJECT_CHECK(STM32SPIState, (obj), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_spi_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 SPI (Serial peripheral interface) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *sr; // 0x8 (Status register) + Object *dr; // 0xC (Data register) + Object *crcpr; // 0x10 (CRC polynomial register) + Object *rxcrcr; // 0x14 (RX CRC register) + Object *txcrcr; // 0x18 (TX CRC register) + Object *i2scfgr; // 0x1C (I2S configuration register) + Object *i2spr; // 0x20 (I2S prescaler register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cpha; // [0:0] Clock phase + Object *cpol; // [1:1] Clock polarity + Object *mstr; // [2:2] Master selection + Object *br; // [3:5] Baud rate control + Object *spe; // [6:6] SPI enable + Object *lsbfirst; // [7:7] Frame format + Object *ssi; // [8:8] Internal slave select + Object *ssm; // [9:9] Software slave management + Object *rxonly; // [10:10] Receive only + Object *dff; // [11:11] Data frame format + Object *crcnext; // [12:12] CRC transfer next + Object *crcen; // [13:13] Hardware CRC calculation enable + Object *bidioe; // [14:14] Output enable in bidirectional mode + Object *bidimode; // [15:15] Bidirectional data mode enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *rxdmaen; // [0:0] Rx buffer DMA enable + Object *txdmaen; // [1:1] Tx buffer DMA enable + Object *ssoe; // [2:2] SS output enable + Object *errie; // [5:5] Error interrupt enable + Object *rxneie; // [6:6] RX buffer not empty interrupt enable + Object *txeie; // [7:7] Tx buffer empty interrupt enable + } cr2; + + // SR (Status register) bitfields. + struct { + Object *rxne; // [0:0] Receive buffer not empty + Object *txe; // [1:1] Transmit buffer empty + Object *chside; // [2:2] Channel side + Object *udr; // [3:3] Underrun flag + Object *crcerr; // [4:4] CRC error flag + Object *modf; // [5:5] Mode fault + Object *ovr; // [6:6] Overrun flag + Object *bsy; // [7:7] Busy flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:15] Data register + } dr; + + // CRCPR (CRC polynomial register) bitfields. + struct { + Object *crcpoly; // [0:15] CRC polynomial register + } crcpr; + + // RXCRCR (RX CRC register) bitfields. + struct { + Object *rxcrc; // [0:15] Rx CRC register + } rxcrcr; + + // TXCRCR (TX CRC register) bitfields. + struct { + Object *txcrc; // [0:15] Tx CRC register + } txcrcr; + + // I2SCFGR (I2S configuration register) bitfields. + struct { + Object *chlen; // [0:0] Channel length (number of bits per audio channel) + Object *datlen; // [1:2] Data length to be transferred + Object *ckpol; // [3:3] Steady state clock polarity + Object *i2sstd; // [4:5] I2S standard selection + Object *pcmsync; // [7:7] PCM frame synchronization + Object *i2scfg; // [8:9] I2S configuration mode + Object *i2se; // [10:10] I2S Enable + Object *i2smod; // [11:11] I2S mode selection + } i2scfgr; + + // I2SPR (I2S prescaler register) bitfields. + struct { + Object *i2sdiv; // [0:7] I2S Linear prescaler + Object *odd; // [8:8] Odd factor for the prescaler + Object *mckoe; // [9:9] Master clock output enable + } i2spr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SPIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SPI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/tim1.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim1.c new file mode 100644 index 0000000000..553c7fc9ec --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim1.c @@ -0,0 +1,427 @@ +/* + * STM32 - TIM1 (Advanced timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_tim1_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f1.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f1.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f1.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f1.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f1.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f1.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f1.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f1.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f1.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f1.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f1.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.opm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "OPM"); + state->u.f1.fld.cr1.dir = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DIR"); + state->u.f1.fld.cr1.cms = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CMS"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + state->u.f1.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f1.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCPC"); + state->u.f1.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCUS"); + state->u.f1.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCDS"); + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + state->u.f1.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TI1S"); + state->u.f1.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS1"); + state->u.f1.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS1N"); + state->u.f1.fld.cr2.ois2 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS2"); + state->u.f1.fld.cr2.ois2n = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS2N"); + state->u.f1.fld.cr2.ois3 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS3"); + state->u.f1.fld.cr2.ois3n = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS3N"); + state->u.f1.fld.cr2.ois4 = cm_object_get_child_by_name(state->u.f1.reg.cr2, "OIS4"); + + // SMCR bitfields. + state->u.f1.fld.smcr.sms = cm_object_get_child_by_name(state->u.f1.reg.smcr, "SMS"); + state->u.f1.fld.smcr.ts = cm_object_get_child_by_name(state->u.f1.reg.smcr, "TS"); + state->u.f1.fld.smcr.msm = cm_object_get_child_by_name(state->u.f1.reg.smcr, "MSM"); + state->u.f1.fld.smcr.etf = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETF"); + state->u.f1.fld.smcr.etps = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETPS"); + state->u.f1.fld.smcr.ece = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ECE"); + state->u.f1.fld.smcr.etp = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1IE"); + state->u.f1.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2IE"); + state->u.f1.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3IE"); + state->u.f1.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4IE"); + state->u.f1.fld.dier.comie = cm_object_get_child_by_name(state->u.f1.reg.dier, "COMIE"); + state->u.f1.fld.dier.tie = cm_object_get_child_by_name(state->u.f1.reg.dier, "TIE"); + state->u.f1.fld.dier.bie = cm_object_get_child_by_name(state->u.f1.reg.dier, "BIE"); + state->u.f1.fld.dier.ude = cm_object_get_child_by_name(state->u.f1.reg.dier, "UDE"); + state->u.f1.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1DE"); + state->u.f1.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2DE"); + state->u.f1.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3DE"); + state->u.f1.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4DE"); + state->u.f1.fld.dier.comde = cm_object_get_child_by_name(state->u.f1.reg.dier, "COMDE"); + state->u.f1.fld.dier.tde = cm_object_get_child_by_name(state->u.f1.reg.dier, "TDE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + state->u.f1.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1IF"); + state->u.f1.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2IF"); + state->u.f1.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3IF"); + state->u.f1.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4IF"); + state->u.f1.fld.sr.comif = cm_object_get_child_by_name(state->u.f1.reg.sr, "COMIF"); + state->u.f1.fld.sr.tif = cm_object_get_child_by_name(state->u.f1.reg.sr, "TIF"); + state->u.f1.fld.sr.bif = cm_object_get_child_by_name(state->u.f1.reg.sr, "BIF"); + state->u.f1.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1OF"); + state->u.f1.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2OF"); + state->u.f1.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3OF"); + state->u.f1.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + state->u.f1.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC1G"); + state->u.f1.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC2G"); + state->u.f1.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC3G"); + state->u.f1.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC4G"); + state->u.f1.fld.egr.comg = cm_object_get_child_by_name(state->u.f1.reg.egr, "COMG"); + state->u.f1.fld.egr.tg = cm_object_get_child_by_name(state->u.f1.reg.egr, "TG"); + state->u.f1.fld.egr.bg = cm_object_get_child_by_name(state->u.f1.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f1.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC1S"); + state->u.f1.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1FE"); + state->u.f1.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1PE"); + state->u.f1.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1M"); + state->u.f1.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1CE"); + state->u.f1.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC2S"); + state->u.f1.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2FE"); + state->u.f1.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2PE"); + state->u.f1.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2M"); + state->u.f1.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f1.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC1S"); + state->u.f1.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "ICPCS"); + state->u.f1.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1F"); + state->u.f1.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC2S"); + state->u.f1.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2PCS"); + state->u.f1.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f1.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC3S"); + state->u.f1.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3FE"); + state->u.f1.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3PE"); + state->u.f1.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3M"); + state->u.f1.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3CE"); + state->u.f1.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC4S"); + state->u.f1.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4FE"); + state->u.f1.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4PE"); + state->u.f1.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4M"); + state->u.f1.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f1.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC3S"); + state->u.f1.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3PSC"); + state->u.f1.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3F"); + state->u.f1.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC4S"); + state->u.f1.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4PSC"); + state->u.f1.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f1.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1E"); + state->u.f1.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1P"); + state->u.f1.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1NE"); + state->u.f1.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1NP"); + state->u.f1.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2E"); + state->u.f1.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2P"); + state->u.f1.fld.ccer.cc2ne = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2NE"); + state->u.f1.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2NP"); + state->u.f1.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3E"); + state->u.f1.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3P"); + state->u.f1.fld.ccer.cc3ne = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3NE"); + state->u.f1.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3NP"); + state->u.f1.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4E"); + state->u.f1.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f1.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f1.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f1.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "CCR4"); + + // DCR bitfields. + state->u.f1.fld.dcr.dba = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBA"); + state->u.f1.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f1.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f1.reg.dmar, "DMAB"); + + // RCR bitfields. + state->u.f1.fld.rcr.rep = cm_object_get_child_by_name(state->u.f1.reg.rcr, "REP"); + + // BDTR bitfields. + state->u.f1.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "DTG"); + state->u.f1.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "LOCK"); + state->u.f1.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "OSSI"); + state->u.f1.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "OSSR"); + state->u.f1.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "BKE"); + state->u.f1.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "BKP"); + state->u.f1.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "AOE"); + state->u.f1.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f1.reg.bdtr, "MOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim1_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim1_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim1_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim1_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim1_is_enabled(Object *obj) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim1_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim1_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM1)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM1State *state = STM32_TIM1_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM1"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_tim1_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim1_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim1_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim1_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim1_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM1EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim1_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM1); +} + +static void stm32_tim1_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim1_reset_callback; + dc->realize = stm32_tim1_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim1_is_enabled; +} + +static const TypeInfo stm32_tim1_type_info = { + .name = TYPE_STM32_TIM1, + .parent = TYPE_STM32_TIM1_PARENT, + .instance_init = stm32_tim1_instance_init_callback, + .instance_size = sizeof(STM32TIM1State), + .class_init = stm32_tim1_class_init_callback, + .class_size = sizeof(STM32TIM1Class) }; + +static void stm32_tim1_register_types(void) +{ + type_register_static(&stm32_tim1_type_info); +} + +type_init(stm32_tim1_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/tim1.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim1.h new file mode 100644 index 0000000000..8d7109ff8e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim1.h @@ -0,0 +1,336 @@ +/* + * STM32 - TIM1 (Advanced timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM1_H_ +#define STM32_TIM1_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM1 DEVICE_PATH_STM32 "TIM1" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM1 TYPE_STM32_PREFIX "tim1" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM1_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM1ParentClass; +typedef PeripheralState STM32TIM1ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM1_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM1Class, (obj), TYPE_STM32_TIM1) +#define STM32_TIM1_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM1Class, (klass), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM1Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM1_STATE(obj) \ + OBJECT_CHECK(STM32TIM1State, (obj), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM1 (Advanced timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *rcr; // 0x30 (Repetition counter register) + Object *bdtr; // 0x44 (Break and dead-time register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + Object *ois2; // [10:10] Output Idle state 2 + Object *ois2n; // [11:11] Output Idle state 2 + Object *ois3; // [12:12] Output Idle state 3 + Object *ois3n; // [13:13] Output Idle state 3 + Object *ois4; // [14:14] Output Idle state 4 + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *comde; // [13:13] COM DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *oc1ce; // [7:7] Output Compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + Object *oc2ce; // [15:15] Output Compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2ne; // [6:6] Capture/Compare 2 complementary output enable + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3ne; // [10:10] Capture/Compare 3 complementary output enable + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM1State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM1_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/tim2.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim2.c new file mode 100644 index 0000000000..23499de260 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim2.c @@ -0,0 +1,390 @@ +/* + * STM32 - TIM2 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_tim2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f1.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f1.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f1.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f1.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f1.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f1.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f1.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f1.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f1.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f1.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.opm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "OPM"); + state->u.f1.fld.cr1.dir = cm_object_get_child_by_name(state->u.f1.reg.cr1, "DIR"); + state->u.f1.fld.cr1.cms = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CMS"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + state->u.f1.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f1.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CCDS"); + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + state->u.f1.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f1.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f1.fld.smcr.sms = cm_object_get_child_by_name(state->u.f1.reg.smcr, "SMS"); + state->u.f1.fld.smcr.ts = cm_object_get_child_by_name(state->u.f1.reg.smcr, "TS"); + state->u.f1.fld.smcr.msm = cm_object_get_child_by_name(state->u.f1.reg.smcr, "MSM"); + state->u.f1.fld.smcr.etf = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETF"); + state->u.f1.fld.smcr.etps = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETPS"); + state->u.f1.fld.smcr.ece = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ECE"); + state->u.f1.fld.smcr.etp = cm_object_get_child_by_name(state->u.f1.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1IE"); + state->u.f1.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2IE"); + state->u.f1.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3IE"); + state->u.f1.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4IE"); + state->u.f1.fld.dier.tie = cm_object_get_child_by_name(state->u.f1.reg.dier, "TIE"); + state->u.f1.fld.dier.ude = cm_object_get_child_by_name(state->u.f1.reg.dier, "UDE"); + state->u.f1.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC1DE"); + state->u.f1.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC2DE"); + state->u.f1.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC3DE"); + state->u.f1.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f1.reg.dier, "CC4DE"); + state->u.f1.fld.dier.tde = cm_object_get_child_by_name(state->u.f1.reg.dier, "TDE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + state->u.f1.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1IF"); + state->u.f1.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2IF"); + state->u.f1.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3IF"); + state->u.f1.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4IF"); + state->u.f1.fld.sr.tif = cm_object_get_child_by_name(state->u.f1.reg.sr, "TIF"); + state->u.f1.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC1OF"); + state->u.f1.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC2OF"); + state->u.f1.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC3OF"); + state->u.f1.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f1.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + state->u.f1.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC1G"); + state->u.f1.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC2G"); + state->u.f1.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC3G"); + state->u.f1.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f1.reg.egr, "CC4G"); + state->u.f1.fld.egr.tg = cm_object_get_child_by_name(state->u.f1.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f1.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC1S"); + state->u.f1.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1FE"); + state->u.f1.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1PE"); + state->u.f1.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1M"); + state->u.f1.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC1CE"); + state->u.f1.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "CC2S"); + state->u.f1.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2FE"); + state->u.f1.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2PE"); + state->u.f1.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2M"); + state->u.f1.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f1.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC1S"); + state->u.f1.fld.ccmr1_input.ic1psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1PSC"); + state->u.f1.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC1F"); + state->u.f1.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "CC2S"); + state->u.f1.fld.ccmr1_input.ic2psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2PSC"); + state->u.f1.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f1.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f1.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC3S"); + state->u.f1.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3FE"); + state->u.f1.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3PE"); + state->u.f1.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3M"); + state->u.f1.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC3CE"); + state->u.f1.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "CC4S"); + state->u.f1.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4FE"); + state->u.f1.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4PE"); + state->u.f1.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4M"); + state->u.f1.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f1.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC3S"); + state->u.f1.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3PSC"); + state->u.f1.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC3F"); + state->u.f1.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "CC4S"); + state->u.f1.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4PSC"); + state->u.f1.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f1.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f1.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1E"); + state->u.f1.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC1P"); + state->u.f1.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2E"); + state->u.f1.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC2P"); + state->u.f1.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3E"); + state->u.f1.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC3P"); + state->u.f1.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4E"); + state->u.f1.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f1.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f1.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f1.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f1.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f1.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f1.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f1.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f1.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f1.reg.ccr4, "CCR4"); + + // DCR bitfields. + state->u.f1.fld.dcr.dba = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBA"); + state->u.f1.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f1.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f1.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f1.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim2_is_enabled(Object *obj) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM2State *state = STM32_TIM2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_tim2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim2_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM2EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM2); +} + +static void stm32_tim2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim2_reset_callback; + dc->realize = stm32_tim2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim2_is_enabled; +} + +static const TypeInfo stm32_tim2_type_info = { + .name = TYPE_STM32_TIM2, + .parent = TYPE_STM32_TIM2_PARENT, + .instance_init = stm32_tim2_instance_init_callback, + .instance_size = sizeof(STM32TIM2State), + .class_init = stm32_tim2_class_init_callback, + .class_size = sizeof(STM32TIM2Class) }; + +static void stm32_tim2_register_types(void) +{ + type_register_static(&stm32_tim2_type_info); +} + +type_init(stm32_tim2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/tim2.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim2.h new file mode 100644 index 0000000000..50bb151aec --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim2.h @@ -0,0 +1,295 @@ +/* + * STM32 - TIM2 (General purpose timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM2_H_ +#define STM32_TIM2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM2 DEVICE_PATH_STM32 "TIM2" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM2 TYPE_STM32_PREFIX "tim2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM2ParentClass; +typedef PeripheralState STM32TIM2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM2Class, (obj), TYPE_STM32_TIM2) +#define STM32_TIM2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM2Class, (klass), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM2_STATE(obj) \ + OBJECT_CHECK(STM32TIM2State, (obj), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM2 (General purpose timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output compare 1 fast enable + Object *oc1pe; // [3:3] Output compare 1 preload enable + Object *oc1m; // [4:6] Output compare 1 mode + Object *oc1ce; // [7:7] Output compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output compare 2 fast enable + Object *oc2pe; // [11:11] Output compare 2 preload enable + Object *oc2m; // [12:14] Output compare 2 mode + Object *oc2ce; // [15:15] Output compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *ic1psc; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/compare 2 selection + Object *ic2psc; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/tim6.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim6.c new file mode 100644 index 0000000000..10cb136fbc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim6.c @@ -0,0 +1,271 @@ +/* + * STM32 - TIM6 (Basic timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_tim6_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f1.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f1.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f1.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + + + // CR1 bitfields. + state->u.f1.fld.cr1.cen = cm_object_get_child_by_name(state->u.f1.reg.cr1, "CEN"); + state->u.f1.fld.cr1.udis = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UDIS"); + state->u.f1.fld.cr1.urs = cm_object_get_child_by_name(state->u.f1.reg.cr1, "URS"); + state->u.f1.fld.cr1.opm = cm_object_get_child_by_name(state->u.f1.reg.cr1, "OPM"); + state->u.f1.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f1.reg.cr1, "ARPE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.mms = cm_object_get_child_by_name(state->u.f1.reg.cr2, "MMS"); + + // DIER bitfields. + state->u.f1.fld.dier.uie = cm_object_get_child_by_name(state->u.f1.reg.dier, "UIE"); + state->u.f1.fld.dier.ude = cm_object_get_child_by_name(state->u.f1.reg.dier, "UDE"); + + // SR bitfields. + state->u.f1.fld.sr.uif = cm_object_get_child_by_name(state->u.f1.reg.sr, "UIF"); + + // EGR bitfields. + state->u.f1.fld.egr.ug = cm_object_get_child_by_name(state->u.f1.reg.egr, "UG"); + + // CNT bitfields. + state->u.f1.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f1.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f1.fld.psc.psc = cm_object_get_child_by_name(state->u.f1.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f1.fld.arr.arr = cm_object_get_child_by_name(state->u.f1.reg.arr, "ARR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim6_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim6_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim6_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim6_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim6_is_enabled(Object *obj) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim6_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim6_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM6)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM6State *state = STM32_TIM6_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM6"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_tim6_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim6_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_tim6_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_tim6_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_tim6_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM6EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim6_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM6); +} + +static void stm32_tim6_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim6_reset_callback; + dc->realize = stm32_tim6_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim6_is_enabled; +} + +static const TypeInfo stm32_tim6_type_info = { + .name = TYPE_STM32_TIM6, + .parent = TYPE_STM32_TIM6_PARENT, + .instance_init = stm32_tim6_instance_init_callback, + .instance_size = sizeof(STM32TIM6State), + .class_init = stm32_tim6_class_init_callback, + .class_size = sizeof(STM32TIM6Class) }; + +static void stm32_tim6_register_types(void) +{ + type_register_static(&stm32_tim6_type_info); +} + +type_init(stm32_tim6_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/tim6.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim6.h new file mode 100644 index 0000000000..2370d39c78 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/tim6.h @@ -0,0 +1,152 @@ +/* + * STM32 - TIM6 (Basic timer) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM6_H_ +#define STM32_TIM6_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM6 DEVICE_PATH_STM32 "TIM6" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM6 TYPE_STM32_PREFIX "tim6" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM6_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM6ParentClass; +typedef PeripheralState STM32TIM6ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM6_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM6Class, (obj), TYPE_STM32_TIM6) +#define STM32_TIM6_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM6Class, (klass), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM6Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM6_STATE(obj) \ + OBJECT_CHECK(STM32TIM6State, (obj), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 TIM6 (Basic timer) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *ude; // [8:8] Update DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + } egr; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Low counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Low Auto-reload value + } arr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM6State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM6_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/uart4.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart4.c new file mode 100644 index 0000000000..73996dd75d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart4.c @@ -0,0 +1,294 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_uart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + + + // SR bitfields. + state->u.f1.fld.sr.pe = cm_object_get_child_by_name(state->u.f1.reg.sr, "PE"); + state->u.f1.fld.sr.fe = cm_object_get_child_by_name(state->u.f1.reg.sr, "FE"); + state->u.f1.fld.sr.ne = cm_object_get_child_by_name(state->u.f1.reg.sr, "NE"); + state->u.f1.fld.sr.ore = cm_object_get_child_by_name(state->u.f1.reg.sr, "ORE"); + state->u.f1.fld.sr.idle = cm_object_get_child_by_name(state->u.f1.reg.sr, "IDLE"); + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.tc = cm_object_get_child_by_name(state->u.f1.reg.sr, "TC"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.lbd = cm_object_get_child_by_name(state->u.f1.reg.sr, "LBD"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // BRR bitfields. + state->u.f1.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Fraction"); + state->u.f1.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f1.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SBK"); + state->u.f1.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RWU"); + state->u.f1.fld.cr1.re = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RE"); + state->u.f1.fld.cr1.te = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TE"); + state->u.f1.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "IDLEIE"); + state->u.f1.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXNEIE"); + state->u.f1.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TCIE"); + state->u.f1.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TXEIE"); + state->u.f1.fld.cr1.peie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEIE"); + state->u.f1.fld.cr1.ps = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PS"); + state->u.f1.fld.cr1.pce = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PCE"); + state->u.f1.fld.cr1.wake = cm_object_get_child_by_name(state->u.f1.reg.cr1, "WAKE"); + state->u.f1.fld.cr1.m = cm_object_get_child_by_name(state->u.f1.reg.cr1, "M"); + state->u.f1.fld.cr1.ue = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.add = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADD"); + state->u.f1.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDL"); + state->u.f1.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDIE"); + state->u.f1.fld.cr2.stop = cm_object_get_child_by_name(state->u.f1.reg.cr2, "STOP"); + state->u.f1.fld.cr2.linen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f1.fld.cr3.eie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "EIE"); + state->u.f1.fld.cr3.iren = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IREN"); + state->u.f1.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IRLP"); + state->u.f1.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f1.reg.cr3, "HDSEL"); + state->u.f1.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAR"); + state->u.f1.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_uart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_uart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_uart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_uart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_uart_is_enabled(Object *obj) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_uart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32UARTState *state = STM32_UART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_UART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_uart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_UART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32UARTState *state = STM32_UART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "UART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_uart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_uart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_uart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/UART%dEN", + 1 + state->port_index - STM32_PORT_UART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_uart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_UART); +} + +static void stm32_uart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_uart_reset_callback; + dc->realize = stm32_uart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_uart_is_enabled; +} + +static const TypeInfo stm32_uart_type_info = { + .name = TYPE_STM32_UART, + .parent = TYPE_STM32_UART_PARENT, + .instance_init = stm32_uart_instance_init_callback, + .instance_size = sizeof(STM32UARTState), + .class_init = stm32_uart_class_init_callback, + .class_size = sizeof(STM32UARTClass) }; + +static void stm32_uart_register_types(void) +{ + type_register_static(&stm32_uart_type_info); +} + +type_init(stm32_uart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/uart4.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart4.h new file mode 100644 index 0000000000..342ef10dbe --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart4.h @@ -0,0 +1,177 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_UART_H_ +#define STM32_UART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_UART DEVICE_PATH_STM32 "UART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_UART4, + STM32_PORT_UART5, + STM32_PORT_UART_UNDEFINED = 0xFF, +} stm32_uart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_UART TYPE_STM32_PREFIX "uart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_UART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32UARTParentClass; +typedef PeripheralState STM32UARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32UARTClass, (obj), TYPE_STM32_UART) +#define STM32_UART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32UARTClass, (klass), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentClass parent_class; + // public: + + // None, so far. +} STM32UARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_UART_STATE(obj) \ + OBJECT_CHECK(STM32UARTState, (obj), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_uart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 UART (Universal asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (UART4 SR) + Object *dr; // 0x4 (UART4 DR) + Object *brr; // 0x8 (UART4 BRR) + Object *cr1; // 0xC (UART4 CR1) + Object *cr2; // 0x10 (UART4 CR2) + Object *cr3; // 0x14 (UART4 CR3) + } reg; + + struct { + + // SR (UART4 SR) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *ne; // [2:2] Noise error flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + } sr; + + // DR (UART4 DR) bitfields. + struct { + Object *dr; // [0:8] DR + } dr; + + // BRR (UART4 BRR) bitfields. + struct { + Object *div_fraction; // [0:3] DIV_Fraction + Object *div_mantissa; // [4:15] DIV_Mantissa + } brr; + + // CR1 (UART4 CR1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + } cr1; + + // CR2 (UART4 CR2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (UART4 CR3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + } cr3; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32UARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_UART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/uart5.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart5.c new file mode 100644 index 0000000000..bc02722516 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart5.c @@ -0,0 +1,293 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_uart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + + + // SR bitfields. + state->u.f1.fld.sr.pe = cm_object_get_child_by_name(state->u.f1.reg.sr, "PE"); + state->u.f1.fld.sr.fe = cm_object_get_child_by_name(state->u.f1.reg.sr, "FE"); + state->u.f1.fld.sr.ne = cm_object_get_child_by_name(state->u.f1.reg.sr, "NE"); + state->u.f1.fld.sr.ore = cm_object_get_child_by_name(state->u.f1.reg.sr, "ORE"); + state->u.f1.fld.sr.idle = cm_object_get_child_by_name(state->u.f1.reg.sr, "IDLE"); + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.tc = cm_object_get_child_by_name(state->u.f1.reg.sr, "TC"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.lbd = cm_object_get_child_by_name(state->u.f1.reg.sr, "LBD"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // BRR bitfields. + state->u.f1.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Fraction"); + state->u.f1.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f1.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SBK"); + state->u.f1.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RWU"); + state->u.f1.fld.cr1.re = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RE"); + state->u.f1.fld.cr1.te = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TE"); + state->u.f1.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "IDLEIE"); + state->u.f1.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXNEIE"); + state->u.f1.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TCIE"); + state->u.f1.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TXEIE"); + state->u.f1.fld.cr1.peie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEIE"); + state->u.f1.fld.cr1.ps = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PS"); + state->u.f1.fld.cr1.pce = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PCE"); + state->u.f1.fld.cr1.wake = cm_object_get_child_by_name(state->u.f1.reg.cr1, "WAKE"); + state->u.f1.fld.cr1.m = cm_object_get_child_by_name(state->u.f1.reg.cr1, "M"); + state->u.f1.fld.cr1.ue = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.add = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADD"); + state->u.f1.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDL"); + state->u.f1.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDIE"); + state->u.f1.fld.cr2.stop = cm_object_get_child_by_name(state->u.f1.reg.cr2, "STOP"); + state->u.f1.fld.cr2.linen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f1.fld.cr3.eie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "EIE"); + state->u.f1.fld.cr3.iren = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IREN"); + state->u.f1.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IRLP"); + state->u.f1.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f1.reg.cr3, "HDSEL"); + state->u.f1.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_uart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_uart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_uart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_uart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_uart_is_enabled(Object *obj) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_uart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32UARTState *state = STM32_UART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_UART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_uart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_UART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32UARTState *state = STM32_UART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "UART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_uart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_uart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_uart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_uart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/UART%dEN", + 1 + state->port_index - STM32_PORT_UART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_uart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_UART); +} + +static void stm32_uart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_uart_reset_callback; + dc->realize = stm32_uart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_uart_is_enabled; +} + +static const TypeInfo stm32_uart_type_info = { + .name = TYPE_STM32_UART, + .parent = TYPE_STM32_UART_PARENT, + .instance_init = stm32_uart_instance_init_callback, + .instance_size = sizeof(STM32UARTState), + .class_init = stm32_uart_class_init_callback, + .class_size = sizeof(STM32UARTClass) }; + +static void stm32_uart_register_types(void) +{ + type_register_static(&stm32_uart_type_info); +} + +type_init(stm32_uart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/uart5.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart5.h new file mode 100644 index 0000000000..f6a970706f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/uart5.h @@ -0,0 +1,176 @@ +/* + * STM32 - UART (Universal asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_UART_H_ +#define STM32_UART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_UART DEVICE_PATH_STM32 "UART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_UART4, + STM32_PORT_UART5, + STM32_PORT_UART_UNDEFINED = 0xFF, +} stm32_uart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_UART TYPE_STM32_PREFIX "uart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_UART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32UARTParentClass; +typedef PeripheralState STM32UARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32UARTClass, (obj), TYPE_STM32_UART) +#define STM32_UART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32UARTClass, (klass), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentClass parent_class; + // public: + + // None, so far. +} STM32UARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_UART_STATE(obj) \ + OBJECT_CHECK(STM32UARTState, (obj), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_uart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 UART (Universal asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (UART5 SR) + Object *dr; // 0x4 (UART5 DR) + Object *brr; // 0x8 (UART5 BRR) + Object *cr1; // 0xC (UART5 CR1) + Object *cr2; // 0x10 (UART5 CR2) + Object *cr3; // 0x14 (UART5 CR3) + } reg; + + struct { + + // SR (UART5 SR) bitfields. + struct { + Object *pe; // [0:0] PE + Object *fe; // [1:1] FE + Object *ne; // [2:2] NE + Object *ore; // [3:3] ORE + Object *idle; // [4:4] IDLE + Object *rxne; // [5:5] RXNE + Object *tc; // [6:6] TC + Object *txe; // [7:7] TXE + Object *lbd; // [8:8] LBD + } sr; + + // DR (UART5 DR) bitfields. + struct { + Object *dr; // [0:8] DR + } dr; + + // BRR (UART5 BRR) bitfields. + struct { + Object *div_fraction; // [0:3] DIV_Fraction + Object *div_mantissa; // [4:15] DIV_Mantissa + } brr; + + // CR1 (UART5 CR1) bitfields. + struct { + Object *sbk; // [0:0] SBK + Object *rwu; // [1:1] RWU + Object *re; // [2:2] RE + Object *te; // [3:3] TE + Object *idleie; // [4:4] IDLEIE + Object *rxneie; // [5:5] RXNEIE + Object *tcie; // [6:6] TCIE + Object *txeie; // [7:7] TXEIE + Object *peie; // [8:8] PEIE + Object *ps; // [9:9] PS + Object *pce; // [10:10] PCE + Object *wake; // [11:11] WAKE + Object *m; // [12:12] M + Object *ue; // [13:13] UE + } cr1; + + // CR2 (UART5 CR2) bitfields. + struct { + Object *add; // [0:3] ADD + Object *lbdl; // [5:5] LBDL + Object *lbdie; // [6:6] LBDIE + Object *stop; // [12:13] STOP + Object *linen; // [14:14] LINEN + } cr2; + + // CR3 (UART5 CR3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *dmat; // [7:7] DMA enable transmitter + } cr3; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32UARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_UART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usart1.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/usart1.c new file mode 100644 index 0000000000..1e894cf487 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usart1.c @@ -0,0 +1,309 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_usart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f1.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f1.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f1.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f1.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f1.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + state->u.f1.reg.gtpr = cm_object_get_child_by_name(obj, "GTPR"); + + + // SR bitfields. + state->u.f1.fld.sr.pe = cm_object_get_child_by_name(state->u.f1.reg.sr, "PE"); + state->u.f1.fld.sr.fe = cm_object_get_child_by_name(state->u.f1.reg.sr, "FE"); + state->u.f1.fld.sr.ne = cm_object_get_child_by_name(state->u.f1.reg.sr, "NE"); + state->u.f1.fld.sr.ore = cm_object_get_child_by_name(state->u.f1.reg.sr, "ORE"); + state->u.f1.fld.sr.idle = cm_object_get_child_by_name(state->u.f1.reg.sr, "IDLE"); + state->u.f1.fld.sr.rxne = cm_object_get_child_by_name(state->u.f1.reg.sr, "RXNE"); + state->u.f1.fld.sr.tc = cm_object_get_child_by_name(state->u.f1.reg.sr, "TC"); + state->u.f1.fld.sr.txe = cm_object_get_child_by_name(state->u.f1.reg.sr, "TXE"); + state->u.f1.fld.sr.lbd = cm_object_get_child_by_name(state->u.f1.reg.sr, "LBD"); + state->u.f1.fld.sr.cts = cm_object_get_child_by_name(state->u.f1.reg.sr, "CTS"); + + // DR bitfields. + state->u.f1.fld.dr.dr = cm_object_get_child_by_name(state->u.f1.reg.dr, "DR"); + + // BRR bitfields. + state->u.f1.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Fraction"); + state->u.f1.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f1.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f1.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f1.reg.cr1, "SBK"); + state->u.f1.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RWU"); + state->u.f1.fld.cr1.re = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RE"); + state->u.f1.fld.cr1.te = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TE"); + state->u.f1.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "IDLEIE"); + state->u.f1.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "RXNEIE"); + state->u.f1.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TCIE"); + state->u.f1.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "TXEIE"); + state->u.f1.fld.cr1.peie = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PEIE"); + state->u.f1.fld.cr1.ps = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PS"); + state->u.f1.fld.cr1.pce = cm_object_get_child_by_name(state->u.f1.reg.cr1, "PCE"); + state->u.f1.fld.cr1.wake = cm_object_get_child_by_name(state->u.f1.reg.cr1, "WAKE"); + state->u.f1.fld.cr1.m = cm_object_get_child_by_name(state->u.f1.reg.cr1, "M"); + state->u.f1.fld.cr1.ue = cm_object_get_child_by_name(state->u.f1.reg.cr1, "UE"); + + // CR2 bitfields. + state->u.f1.fld.cr2.add = cm_object_get_child_by_name(state->u.f1.reg.cr2, "ADD"); + state->u.f1.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDL"); + state->u.f1.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBDIE"); + state->u.f1.fld.cr2.lbcl = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LBCL"); + state->u.f1.fld.cr2.cpha = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CPHA"); + state->u.f1.fld.cr2.cpol = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CPOL"); + state->u.f1.fld.cr2.clken = cm_object_get_child_by_name(state->u.f1.reg.cr2, "CLKEN"); + state->u.f1.fld.cr2.stop = cm_object_get_child_by_name(state->u.f1.reg.cr2, "STOP"); + state->u.f1.fld.cr2.linen = cm_object_get_child_by_name(state->u.f1.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f1.fld.cr3.eie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "EIE"); + state->u.f1.fld.cr3.iren = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IREN"); + state->u.f1.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f1.reg.cr3, "IRLP"); + state->u.f1.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f1.reg.cr3, "HDSEL"); + state->u.f1.fld.cr3.nack = cm_object_get_child_by_name(state->u.f1.reg.cr3, "NACK"); + state->u.f1.fld.cr3.scen = cm_object_get_child_by_name(state->u.f1.reg.cr3, "SCEN"); + state->u.f1.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAR"); + state->u.f1.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f1.reg.cr3, "DMAT"); + state->u.f1.fld.cr3.rtse = cm_object_get_child_by_name(state->u.f1.reg.cr3, "RTSE"); + state->u.f1.fld.cr3.ctse = cm_object_get_child_by_name(state->u.f1.reg.cr3, "CTSE"); + state->u.f1.fld.cr3.ctsie = cm_object_get_child_by_name(state->u.f1.reg.cr3, "CTSIE"); + + // GTPR bitfields. + state->u.f1.fld.gtpr.psc = cm_object_get_child_by_name(state->u.f1.reg.gtpr, "PSC"); + state->u.f1.fld.gtpr.gt = cm_object_get_child_by_name(state->u.f1.reg.gtpr, "GT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usart_is_enabled(Object *obj) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USARTState *state = STM32_USART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_USART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USARTState *state = STM32_USART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_usart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_usart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_usart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USART%dEN", + 1 + state->port_index - STM32_PORT_USART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USART); +} + +static void stm32_usart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usart_reset_callback; + dc->realize = stm32_usart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usart_is_enabled; +} + +static const TypeInfo stm32_usart_type_info = { + .name = TYPE_STM32_USART, + .parent = TYPE_STM32_USART_PARENT, + .instance_init = stm32_usart_instance_init_callback, + .instance_size = sizeof(STM32USARTState), + .class_init = stm32_usart_class_init_callback, + .class_size = sizeof(STM32USARTClass) }; + +static void stm32_usart_register_types(void) +{ + type_register_static(&stm32_usart_type_info); +} + +type_init(stm32_usart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usart1.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/usart1.h new file mode 100644 index 0000000000..10629eb585 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usart1.h @@ -0,0 +1,195 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USART_H_ +#define STM32_USART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USART DEVICE_PATH_STM32 "USART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_USART1, + STM32_PORT_USART2, + STM32_PORT_USART3, + STM32_PORT_USART_UNDEFINED = 0xFF, +} stm32_usart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USART TYPE_STM32_PREFIX "usart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USARTParentClass; +typedef PeripheralState STM32USARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USARTClass, (obj), TYPE_STM32_USART) +#define STM32_USART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USARTClass, (klass), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentClass parent_class; + // public: + + // None, so far. +} STM32USARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USART_STATE(obj) \ + OBJECT_CHECK(STM32USARTState, (obj), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_usart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 USART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *dr; // 0x4 (Data register) + Object *brr; // 0x8 (Baud rate register) + Object *cr1; // 0xC (Control register 1) + Object *cr2; // 0x10 (Control register 2) + Object *cr3; // 0x14 (Control register 3) + Object *gtpr; // 0x18 (Guard time and prescaler register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *ne; // [2:2] Noise error flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + Object *cts; // [9:9] CTS flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:8] Data value + } dr; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // CR1 (Control register 1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *lbcl; // [8:8] Last bit clock pulse + Object *cpha; // [9:9] Clock phase + Object *cpol; // [10:10] Clock polarity + Object *clken; // [11:11] Clock enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *nack; // [4:4] Smartcard NACK enable + Object *scen; // [5:5] Smartcard mode enable + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *rtse; // [8:8] RTS enable + Object *ctse; // [9:9] CTS enable + Object *ctsie; // [10:10] CTS interrupt enable + } cr3; + + // GTPR (Guard time and prescaler register) bitfields. + struct { + Object *psc; // [0:7] Prescaler value + Object *gt; // [8:15] Guard time value + } gtpr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_device.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_device.c new file mode 100644 index 0000000000..218f23e201 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_device.c @@ -0,0 +1,552 @@ +/* + * STM32 - USB_OTG_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_usb_otg_device_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.fs_dcfg = cm_object_get_child_by_name(obj, "FS_DCFG"); + state->u.f1.reg.fs_dctl = cm_object_get_child_by_name(obj, "FS_DCTL"); + state->u.f1.reg.fs_dsts = cm_object_get_child_by_name(obj, "FS_DSTS"); + state->u.f1.reg.fs_diepmsk = cm_object_get_child_by_name(obj, "FS_DIEPMSK"); + state->u.f1.reg.fs_doepmsk = cm_object_get_child_by_name(obj, "FS_DOEPMSK"); + state->u.f1.reg.fs_daint = cm_object_get_child_by_name(obj, "FS_DAINT"); + state->u.f1.reg.fs_daintmsk = cm_object_get_child_by_name(obj, "FS_DAINTMSK"); + state->u.f1.reg.dvbusdis = cm_object_get_child_by_name(obj, "DVBUSDIS"); + state->u.f1.reg.dvbuspulse = cm_object_get_child_by_name(obj, "DVBUSPULSE"); + state->u.f1.reg.diepempmsk = cm_object_get_child_by_name(obj, "DIEPEMPMSK"); + state->u.f1.reg.fs_diepctl0 = cm_object_get_child_by_name(obj, "FS_DIEPCTL0"); + state->u.f1.reg.diepctl1 = cm_object_get_child_by_name(obj, "DIEPCTL1"); + state->u.f1.reg.diepctl2 = cm_object_get_child_by_name(obj, "DIEPCTL2"); + state->u.f1.reg.diepctl3 = cm_object_get_child_by_name(obj, "DIEPCTL3"); + state->u.f1.reg.doepctl0 = cm_object_get_child_by_name(obj, "DOEPCTL0"); + state->u.f1.reg.doepctl1 = cm_object_get_child_by_name(obj, "DOEPCTL1"); + state->u.f1.reg.doepctl2 = cm_object_get_child_by_name(obj, "DOEPCTL2"); + state->u.f1.reg.doepctl3 = cm_object_get_child_by_name(obj, "DOEPCTL3"); + state->u.f1.reg.diepint0 = cm_object_get_child_by_name(obj, "DIEPINT0"); + state->u.f1.reg.diepint1 = cm_object_get_child_by_name(obj, "DIEPINT1"); + state->u.f1.reg.diepint2 = cm_object_get_child_by_name(obj, "DIEPINT2"); + state->u.f1.reg.diepint3 = cm_object_get_child_by_name(obj, "DIEPINT3"); + state->u.f1.reg.doepint0 = cm_object_get_child_by_name(obj, "DOEPINT0"); + state->u.f1.reg.doepint1 = cm_object_get_child_by_name(obj, "DOEPINT1"); + state->u.f1.reg.doepint2 = cm_object_get_child_by_name(obj, "DOEPINT2"); + state->u.f1.reg.doepint3 = cm_object_get_child_by_name(obj, "DOEPINT3"); + state->u.f1.reg.dieptsiz0 = cm_object_get_child_by_name(obj, "DIEPTSIZ0"); + state->u.f1.reg.doeptsiz0 = cm_object_get_child_by_name(obj, "DOEPTSIZ0"); + state->u.f1.reg.dieptsiz1 = cm_object_get_child_by_name(obj, "DIEPTSIZ1"); + state->u.f1.reg.dieptsiz2 = cm_object_get_child_by_name(obj, "DIEPTSIZ2"); + state->u.f1.reg.dieptsiz3 = cm_object_get_child_by_name(obj, "DIEPTSIZ3"); + state->u.f1.reg.dtxfsts0 = cm_object_get_child_by_name(obj, "DTXFSTS0"); + state->u.f1.reg.dtxfsts1 = cm_object_get_child_by_name(obj, "DTXFSTS1"); + state->u.f1.reg.dtxfsts2 = cm_object_get_child_by_name(obj, "DTXFSTS2"); + state->u.f1.reg.dtxfsts3 = cm_object_get_child_by_name(obj, "DTXFSTS3"); + state->u.f1.reg.doeptsiz1 = cm_object_get_child_by_name(obj, "DOEPTSIZ1"); + state->u.f1.reg.doeptsiz2 = cm_object_get_child_by_name(obj, "DOEPTSIZ2"); + state->u.f1.reg.doeptsiz3 = cm_object_get_child_by_name(obj, "DOEPTSIZ3"); + + + // FS_DCFG bitfields. + state->u.f1.fld.fs_dcfg.dspd = cm_object_get_child_by_name(state->u.f1.reg.fs_dcfg, "DSPD"); + state->u.f1.fld.fs_dcfg.nzlsohsk = cm_object_get_child_by_name(state->u.f1.reg.fs_dcfg, "NZLSOHSK"); + state->u.f1.fld.fs_dcfg.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_dcfg, "DAD"); + state->u.f1.fld.fs_dcfg.pfivl = cm_object_get_child_by_name(state->u.f1.reg.fs_dcfg, "PFIVL"); + + // FS_DCTL bitfields. + state->u.f1.fld.fs_dctl.rwusig = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "RWUSIG"); + state->u.f1.fld.fs_dctl.sdis = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "SDIS"); + state->u.f1.fld.fs_dctl.ginsts = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "GINSTS"); + state->u.f1.fld.fs_dctl.gonsts = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "GONSTS"); + state->u.f1.fld.fs_dctl.tctl = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "TCTL"); + state->u.f1.fld.fs_dctl.sginak = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "SGINAK"); + state->u.f1.fld.fs_dctl.cginak = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "CGINAK"); + state->u.f1.fld.fs_dctl.sgonak = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "SGONAK"); + state->u.f1.fld.fs_dctl.cgonak = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "CGONAK"); + state->u.f1.fld.fs_dctl.poprgdne = cm_object_get_child_by_name(state->u.f1.reg.fs_dctl, "POPRGDNE"); + + // FS_DSTS bitfields. + state->u.f1.fld.fs_dsts.suspsts = cm_object_get_child_by_name(state->u.f1.reg.fs_dsts, "SUSPSTS"); + state->u.f1.fld.fs_dsts.enumspd = cm_object_get_child_by_name(state->u.f1.reg.fs_dsts, "ENUMSPD"); + state->u.f1.fld.fs_dsts.eerr = cm_object_get_child_by_name(state->u.f1.reg.fs_dsts, "EERR"); + state->u.f1.fld.fs_dsts.fnsof = cm_object_get_child_by_name(state->u.f1.reg.fs_dsts, "FNSOF"); + + // FS_DIEPMSK bitfields. + state->u.f1.fld.fs_diepmsk.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_diepmsk, "XFRCM"); + state->u.f1.fld.fs_diepmsk.epdm = cm_object_get_child_by_name(state->u.f1.reg.fs_diepmsk, "EPDM"); + state->u.f1.fld.fs_diepmsk.tom = cm_object_get_child_by_name(state->u.f1.reg.fs_diepmsk, "TOM"); + state->u.f1.fld.fs_diepmsk.ittxfemsk = cm_object_get_child_by_name(state->u.f1.reg.fs_diepmsk, "ITTXFEMSK"); + state->u.f1.fld.fs_diepmsk.inepnmm = cm_object_get_child_by_name(state->u.f1.reg.fs_diepmsk, "INEPNMM"); + state->u.f1.fld.fs_diepmsk.inepnem = cm_object_get_child_by_name(state->u.f1.reg.fs_diepmsk, "INEPNEM"); + + // FS_DOEPMSK bitfields. + state->u.f1.fld.fs_doepmsk.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_doepmsk, "XFRCM"); + state->u.f1.fld.fs_doepmsk.epdm = cm_object_get_child_by_name(state->u.f1.reg.fs_doepmsk, "EPDM"); + state->u.f1.fld.fs_doepmsk.stupm = cm_object_get_child_by_name(state->u.f1.reg.fs_doepmsk, "STUPM"); + state->u.f1.fld.fs_doepmsk.otepdm = cm_object_get_child_by_name(state->u.f1.reg.fs_doepmsk, "OTEPDM"); + + // FS_DAINT bitfields. + state->u.f1.fld.fs_daint.iepint = cm_object_get_child_by_name(state->u.f1.reg.fs_daint, "IEPINT"); + state->u.f1.fld.fs_daint.oepint = cm_object_get_child_by_name(state->u.f1.reg.fs_daint, "OEPINT"); + + // FS_DAINTMSK bitfields. + state->u.f1.fld.fs_daintmsk.iepm = cm_object_get_child_by_name(state->u.f1.reg.fs_daintmsk, "IEPM"); + state->u.f1.fld.fs_daintmsk.oepint = cm_object_get_child_by_name(state->u.f1.reg.fs_daintmsk, "OEPINT"); + + // DVBUSDIS bitfields. + state->u.f1.fld.dvbusdis.vbusdt = cm_object_get_child_by_name(state->u.f1.reg.dvbusdis, "VBUSDT"); + + // DVBUSPULSE bitfields. + state->u.f1.fld.dvbuspulse.dvbusp = cm_object_get_child_by_name(state->u.f1.reg.dvbuspulse, "DVBUSP"); + + // DIEPEMPMSK bitfields. + state->u.f1.fld.diepempmsk.ineptxfem = cm_object_get_child_by_name(state->u.f1.reg.diepempmsk, "INEPTXFEM"); + + // FS_DIEPCTL0 bitfields. + state->u.f1.fld.fs_diepctl0.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "MPSIZ"); + state->u.f1.fld.fs_diepctl0.usbaep = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "USBAEP"); + state->u.f1.fld.fs_diepctl0.naksts = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "NAKSTS"); + state->u.f1.fld.fs_diepctl0.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "EPTYP"); + state->u.f1.fld.fs_diepctl0.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "STALL"); + state->u.f1.fld.fs_diepctl0.txfnum = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "TXFNUM"); + state->u.f1.fld.fs_diepctl0.cnak = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "CNAK"); + state->u.f1.fld.fs_diepctl0.snak = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "SNAK"); + state->u.f1.fld.fs_diepctl0.epdis = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "EPDIS"); + state->u.f1.fld.fs_diepctl0.epena = cm_object_get_child_by_name(state->u.f1.reg.fs_diepctl0, "EPENA"); + + // DIEPCTL1 bitfields. + state->u.f1.fld.diepctl1.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "MPSIZ"); + state->u.f1.fld.diepctl1.usbaep = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "USBAEP"); + state->u.f1.fld.diepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "EONUM_DPID"); + state->u.f1.fld.diepctl1.naksts = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "NAKSTS"); + state->u.f1.fld.diepctl1.eptyp = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "EPTYP"); + state->u.f1.fld.diepctl1.stall = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "Stall"); + state->u.f1.fld.diepctl1.txfnum = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "TXFNUM"); + state->u.f1.fld.diepctl1.cnak = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "CNAK"); + state->u.f1.fld.diepctl1.snak = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "SNAK"); + state->u.f1.fld.diepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "SD0PID_SEVNFRM"); + state->u.f1.fld.diepctl1.soddfrm_sd1pid = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "SODDFRM_SD1PID"); + state->u.f1.fld.diepctl1.epdis = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "EPDIS"); + state->u.f1.fld.diepctl1.epena = cm_object_get_child_by_name(state->u.f1.reg.diepctl1, "EPENA"); + + // DIEPCTL2 bitfields. + state->u.f1.fld.diepctl2.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "MPSIZ"); + state->u.f1.fld.diepctl2.usbaep = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "USBAEP"); + state->u.f1.fld.diepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "EONUM_DPID"); + state->u.f1.fld.diepctl2.naksts = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "NAKSTS"); + state->u.f1.fld.diepctl2.eptyp = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "EPTYP"); + state->u.f1.fld.diepctl2.stall = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "Stall"); + state->u.f1.fld.diepctl2.txfnum = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "TXFNUM"); + state->u.f1.fld.diepctl2.cnak = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "CNAK"); + state->u.f1.fld.diepctl2.snak = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "SNAK"); + state->u.f1.fld.diepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "SD0PID_SEVNFRM"); + state->u.f1.fld.diepctl2.soddfrm = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "SODDFRM"); + state->u.f1.fld.diepctl2.epdis = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "EPDIS"); + state->u.f1.fld.diepctl2.epena = cm_object_get_child_by_name(state->u.f1.reg.diepctl2, "EPENA"); + + // DIEPCTL3 bitfields. + state->u.f1.fld.diepctl3.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "MPSIZ"); + state->u.f1.fld.diepctl3.usbaep = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "USBAEP"); + state->u.f1.fld.diepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "EONUM_DPID"); + state->u.f1.fld.diepctl3.naksts = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "NAKSTS"); + state->u.f1.fld.diepctl3.eptyp = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "EPTYP"); + state->u.f1.fld.diepctl3.stall = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "Stall"); + state->u.f1.fld.diepctl3.txfnum = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "TXFNUM"); + state->u.f1.fld.diepctl3.cnak = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "CNAK"); + state->u.f1.fld.diepctl3.snak = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "SNAK"); + state->u.f1.fld.diepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "SD0PID_SEVNFRM"); + state->u.f1.fld.diepctl3.soddfrm = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "SODDFRM"); + state->u.f1.fld.diepctl3.epdis = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "EPDIS"); + state->u.f1.fld.diepctl3.epena = cm_object_get_child_by_name(state->u.f1.reg.diepctl3, "EPENA"); + + // DOEPCTL0 bitfields. + state->u.f1.fld.doepctl0.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "MPSIZ"); + state->u.f1.fld.doepctl0.usbaep = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "USBAEP"); + state->u.f1.fld.doepctl0.naksts = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "NAKSTS"); + state->u.f1.fld.doepctl0.eptyp = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "EPTYP"); + state->u.f1.fld.doepctl0.snpm = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "SNPM"); + state->u.f1.fld.doepctl0.stall = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "Stall"); + state->u.f1.fld.doepctl0.cnak = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "CNAK"); + state->u.f1.fld.doepctl0.snak = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "SNAK"); + state->u.f1.fld.doepctl0.epdis = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "EPDIS"); + state->u.f1.fld.doepctl0.epena = cm_object_get_child_by_name(state->u.f1.reg.doepctl0, "EPENA"); + + // DOEPCTL1 bitfields. + state->u.f1.fld.doepctl1.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "MPSIZ"); + state->u.f1.fld.doepctl1.usbaep = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "USBAEP"); + state->u.f1.fld.doepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "EONUM_DPID"); + state->u.f1.fld.doepctl1.naksts = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "NAKSTS"); + state->u.f1.fld.doepctl1.eptyp = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "EPTYP"); + state->u.f1.fld.doepctl1.snpm = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "SNPM"); + state->u.f1.fld.doepctl1.stall = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "Stall"); + state->u.f1.fld.doepctl1.cnak = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "CNAK"); + state->u.f1.fld.doepctl1.snak = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "SNAK"); + state->u.f1.fld.doepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "SD0PID_SEVNFRM"); + state->u.f1.fld.doepctl1.soddfrm = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "SODDFRM"); + state->u.f1.fld.doepctl1.epdis = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "EPDIS"); + state->u.f1.fld.doepctl1.epena = cm_object_get_child_by_name(state->u.f1.reg.doepctl1, "EPENA"); + + // DOEPCTL2 bitfields. + state->u.f1.fld.doepctl2.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "MPSIZ"); + state->u.f1.fld.doepctl2.usbaep = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "USBAEP"); + state->u.f1.fld.doepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "EONUM_DPID"); + state->u.f1.fld.doepctl2.naksts = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "NAKSTS"); + state->u.f1.fld.doepctl2.eptyp = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "EPTYP"); + state->u.f1.fld.doepctl2.snpm = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "SNPM"); + state->u.f1.fld.doepctl2.stall = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "Stall"); + state->u.f1.fld.doepctl2.cnak = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "CNAK"); + state->u.f1.fld.doepctl2.snak = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "SNAK"); + state->u.f1.fld.doepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "SD0PID_SEVNFRM"); + state->u.f1.fld.doepctl2.soddfrm = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "SODDFRM"); + state->u.f1.fld.doepctl2.epdis = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "EPDIS"); + state->u.f1.fld.doepctl2.epena = cm_object_get_child_by_name(state->u.f1.reg.doepctl2, "EPENA"); + + // DOEPCTL3 bitfields. + state->u.f1.fld.doepctl3.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "MPSIZ"); + state->u.f1.fld.doepctl3.usbaep = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "USBAEP"); + state->u.f1.fld.doepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "EONUM_DPID"); + state->u.f1.fld.doepctl3.naksts = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "NAKSTS"); + state->u.f1.fld.doepctl3.eptyp = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "EPTYP"); + state->u.f1.fld.doepctl3.snpm = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "SNPM"); + state->u.f1.fld.doepctl3.stall = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "Stall"); + state->u.f1.fld.doepctl3.cnak = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "CNAK"); + state->u.f1.fld.doepctl3.snak = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "SNAK"); + state->u.f1.fld.doepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "SD0PID_SEVNFRM"); + state->u.f1.fld.doepctl3.soddfrm = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "SODDFRM"); + state->u.f1.fld.doepctl3.epdis = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "EPDIS"); + state->u.f1.fld.doepctl3.epena = cm_object_get_child_by_name(state->u.f1.reg.doepctl3, "EPENA"); + + // DIEPINT0 bitfields. + state->u.f1.fld.diepint0.xfrc = cm_object_get_child_by_name(state->u.f1.reg.diepint0, "XFRC"); + state->u.f1.fld.diepint0.epdisd = cm_object_get_child_by_name(state->u.f1.reg.diepint0, "EPDISD"); + state->u.f1.fld.diepint0.toc = cm_object_get_child_by_name(state->u.f1.reg.diepint0, "TOC"); + state->u.f1.fld.diepint0.ittxfe = cm_object_get_child_by_name(state->u.f1.reg.diepint0, "ITTXFE"); + state->u.f1.fld.diepint0.inepne = cm_object_get_child_by_name(state->u.f1.reg.diepint0, "INEPNE"); + state->u.f1.fld.diepint0.txfe = cm_object_get_child_by_name(state->u.f1.reg.diepint0, "TXFE"); + + // DIEPINT1 bitfields. + state->u.f1.fld.diepint1.xfrc = cm_object_get_child_by_name(state->u.f1.reg.diepint1, "XFRC"); + state->u.f1.fld.diepint1.epdisd = cm_object_get_child_by_name(state->u.f1.reg.diepint1, "EPDISD"); + state->u.f1.fld.diepint1.toc = cm_object_get_child_by_name(state->u.f1.reg.diepint1, "TOC"); + state->u.f1.fld.diepint1.ittxfe = cm_object_get_child_by_name(state->u.f1.reg.diepint1, "ITTXFE"); + state->u.f1.fld.diepint1.inepne = cm_object_get_child_by_name(state->u.f1.reg.diepint1, "INEPNE"); + state->u.f1.fld.diepint1.txfe = cm_object_get_child_by_name(state->u.f1.reg.diepint1, "TXFE"); + + // DIEPINT2 bitfields. + state->u.f1.fld.diepint2.xfrc = cm_object_get_child_by_name(state->u.f1.reg.diepint2, "XFRC"); + state->u.f1.fld.diepint2.epdisd = cm_object_get_child_by_name(state->u.f1.reg.diepint2, "EPDISD"); + state->u.f1.fld.diepint2.toc = cm_object_get_child_by_name(state->u.f1.reg.diepint2, "TOC"); + state->u.f1.fld.diepint2.ittxfe = cm_object_get_child_by_name(state->u.f1.reg.diepint2, "ITTXFE"); + state->u.f1.fld.diepint2.inepne = cm_object_get_child_by_name(state->u.f1.reg.diepint2, "INEPNE"); + state->u.f1.fld.diepint2.txfe = cm_object_get_child_by_name(state->u.f1.reg.diepint2, "TXFE"); + + // DIEPINT3 bitfields. + state->u.f1.fld.diepint3.xfrc = cm_object_get_child_by_name(state->u.f1.reg.diepint3, "XFRC"); + state->u.f1.fld.diepint3.epdisd = cm_object_get_child_by_name(state->u.f1.reg.diepint3, "EPDISD"); + state->u.f1.fld.diepint3.toc = cm_object_get_child_by_name(state->u.f1.reg.diepint3, "TOC"); + state->u.f1.fld.diepint3.ittxfe = cm_object_get_child_by_name(state->u.f1.reg.diepint3, "ITTXFE"); + state->u.f1.fld.diepint3.inepne = cm_object_get_child_by_name(state->u.f1.reg.diepint3, "INEPNE"); + state->u.f1.fld.diepint3.txfe = cm_object_get_child_by_name(state->u.f1.reg.diepint3, "TXFE"); + + // DOEPINT0 bitfields. + state->u.f1.fld.doepint0.xfrc = cm_object_get_child_by_name(state->u.f1.reg.doepint0, "XFRC"); + state->u.f1.fld.doepint0.epdisd = cm_object_get_child_by_name(state->u.f1.reg.doepint0, "EPDISD"); + state->u.f1.fld.doepint0.stup = cm_object_get_child_by_name(state->u.f1.reg.doepint0, "STUP"); + state->u.f1.fld.doepint0.otepdis = cm_object_get_child_by_name(state->u.f1.reg.doepint0, "OTEPDIS"); + state->u.f1.fld.doepint0.b2bstup = cm_object_get_child_by_name(state->u.f1.reg.doepint0, "B2BSTUP"); + + // DOEPINT1 bitfields. + state->u.f1.fld.doepint1.xfrc = cm_object_get_child_by_name(state->u.f1.reg.doepint1, "XFRC"); + state->u.f1.fld.doepint1.epdisd = cm_object_get_child_by_name(state->u.f1.reg.doepint1, "EPDISD"); + state->u.f1.fld.doepint1.stup = cm_object_get_child_by_name(state->u.f1.reg.doepint1, "STUP"); + state->u.f1.fld.doepint1.otepdis = cm_object_get_child_by_name(state->u.f1.reg.doepint1, "OTEPDIS"); + state->u.f1.fld.doepint1.b2bstup = cm_object_get_child_by_name(state->u.f1.reg.doepint1, "B2BSTUP"); + + // DOEPINT2 bitfields. + state->u.f1.fld.doepint2.xfrc = cm_object_get_child_by_name(state->u.f1.reg.doepint2, "XFRC"); + state->u.f1.fld.doepint2.epdisd = cm_object_get_child_by_name(state->u.f1.reg.doepint2, "EPDISD"); + state->u.f1.fld.doepint2.stup = cm_object_get_child_by_name(state->u.f1.reg.doepint2, "STUP"); + state->u.f1.fld.doepint2.otepdis = cm_object_get_child_by_name(state->u.f1.reg.doepint2, "OTEPDIS"); + state->u.f1.fld.doepint2.b2bstup = cm_object_get_child_by_name(state->u.f1.reg.doepint2, "B2BSTUP"); + + // DOEPINT3 bitfields. + state->u.f1.fld.doepint3.xfrc = cm_object_get_child_by_name(state->u.f1.reg.doepint3, "XFRC"); + state->u.f1.fld.doepint3.epdisd = cm_object_get_child_by_name(state->u.f1.reg.doepint3, "EPDISD"); + state->u.f1.fld.doepint3.stup = cm_object_get_child_by_name(state->u.f1.reg.doepint3, "STUP"); + state->u.f1.fld.doepint3.otepdis = cm_object_get_child_by_name(state->u.f1.reg.doepint3, "OTEPDIS"); + state->u.f1.fld.doepint3.b2bstup = cm_object_get_child_by_name(state->u.f1.reg.doepint3, "B2BSTUP"); + + // DIEPTSIZ0 bitfields. + state->u.f1.fld.dieptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz0, "XFRSIZ"); + state->u.f1.fld.dieptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz0, "PKTCNT"); + + // DOEPTSIZ0 bitfields. + state->u.f1.fld.doeptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz0, "XFRSIZ"); + state->u.f1.fld.doeptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz0, "PKTCNT"); + state->u.f1.fld.doeptsiz0.stupcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz0, "STUPCNT"); + + // DIEPTSIZ1 bitfields. + state->u.f1.fld.dieptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz1, "XFRSIZ"); + state->u.f1.fld.dieptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz1, "PKTCNT"); + state->u.f1.fld.dieptsiz1.mcnt = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz1, "MCNT"); + + // DIEPTSIZ2 bitfields. + state->u.f1.fld.dieptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz2, "XFRSIZ"); + state->u.f1.fld.dieptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz2, "PKTCNT"); + state->u.f1.fld.dieptsiz2.mcnt = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz2, "MCNT"); + + // DIEPTSIZ3 bitfields. + state->u.f1.fld.dieptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz3, "XFRSIZ"); + state->u.f1.fld.dieptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz3, "PKTCNT"); + state->u.f1.fld.dieptsiz3.mcnt = cm_object_get_child_by_name(state->u.f1.reg.dieptsiz3, "MCNT"); + + // DTXFSTS0 bitfields. + state->u.f1.fld.dtxfsts0.ineptfsav = cm_object_get_child_by_name(state->u.f1.reg.dtxfsts0, "INEPTFSAV"); + + // DTXFSTS1 bitfields. + state->u.f1.fld.dtxfsts1.ineptfsav = cm_object_get_child_by_name(state->u.f1.reg.dtxfsts1, "INEPTFSAV"); + + // DTXFSTS2 bitfields. + state->u.f1.fld.dtxfsts2.ineptfsav = cm_object_get_child_by_name(state->u.f1.reg.dtxfsts2, "INEPTFSAV"); + + // DTXFSTS3 bitfields. + state->u.f1.fld.dtxfsts3.ineptfsav = cm_object_get_child_by_name(state->u.f1.reg.dtxfsts3, "INEPTFSAV"); + + // DOEPTSIZ1 bitfields. + state->u.f1.fld.doeptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz1, "XFRSIZ"); + state->u.f1.fld.doeptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz1, "PKTCNT"); + state->u.f1.fld.doeptsiz1.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz1, "RXDPID_STUPCNT"); + + // DOEPTSIZ2 bitfields. + state->u.f1.fld.doeptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz2, "XFRSIZ"); + state->u.f1.fld.doeptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz2, "PKTCNT"); + state->u.f1.fld.doeptsiz2.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz2, "RXDPID_STUPCNT"); + + // DOEPTSIZ3 bitfields. + state->u.f1.fld.doeptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz3, "XFRSIZ"); + state->u.f1.fld.doeptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz3, "PKTCNT"); + state->u.f1.fld.doeptsiz3.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f1.reg.doeptsiz3, "RXDPID_STUPCNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usb_otg_device_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usb_otg_device_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usb_otg_device_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usb_otg_device_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usb_otg_device_is_enabled(Object *obj) +{ + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usb_otg_device_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usb_otg_device_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USB_OTG_DEVICE)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USB_OTG_DEVICEState *state = STM32_USB_OTG_DEVICE_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USB_OTG_DEVICE"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_usb_otg_device_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_device_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_usb_otg_device_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_device_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_usb_otg_device_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USB_OTG_DEVICEEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usb_otg_device_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USB_OTG_DEVICE); +} + +static void stm32_usb_otg_device_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usb_otg_device_reset_callback; + dc->realize = stm32_usb_otg_device_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usb_otg_device_is_enabled; +} + +static const TypeInfo stm32_usb_otg_device_type_info = { + .name = TYPE_STM32_USB_OTG_DEVICE, + .parent = TYPE_STM32_USB_OTG_DEVICE_PARENT, + .instance_init = stm32_usb_otg_device_instance_init_callback, + .instance_size = sizeof(STM32USB_OTG_DEVICEState), + .class_init = stm32_usb_otg_device_class_init_callback, + .class_size = sizeof(STM32USB_OTG_DEVICEClass) }; + +static void stm32_usb_otg_device_register_types(void) +{ + type_register_static(&stm32_usb_otg_device_type_info); +} + +type_init(stm32_usb_otg_device_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_device.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_device.h new file mode 100644 index 0000000000..cbb5f23050 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_device.h @@ -0,0 +1,493 @@ +/* + * STM32 - USB_OTG_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USB_OTG_DEVICE_H_ +#define STM32_USB_OTG_DEVICE_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USB_OTG_DEVICE DEVICE_PATH_STM32 "USB_OTG_DEVICE" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USB_OTG_DEVICE TYPE_STM32_PREFIX "usb_otg_device" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USB_OTG_DEVICE_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USB_OTG_DEVICEParentClass; +typedef PeripheralState STM32USB_OTG_DEVICEParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USB_OTG_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USB_OTG_DEVICEClass, (obj), TYPE_STM32_USB_OTG_DEVICE) +#define STM32_USB_OTG_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USB_OTG_DEVICEClass, (klass), TYPE_STM32_USB_OTG_DEVICE) + +typedef struct { + // private: + STM32USB_OTG_DEVICEParentClass parent_class; + // public: + + // None, so far. +} STM32USB_OTG_DEVICEClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USB_OTG_DEVICE_STATE(obj) \ + OBJECT_CHECK(STM32USB_OTG_DEVICEState, (obj), TYPE_STM32_USB_OTG_DEVICE) + +typedef struct { + // private: + STM32USB_OTG_DEVICEParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 USB_OTG_DEVICE (USB on the go full speed) registers. + struct { + Object *fs_dcfg; // 0x0 (OTG_FS device configuration register (OTG_FS_DCFG)) + Object *fs_dctl; // 0x4 (OTG_FS device control register (OTG_FS_DCTL)) + Object *fs_dsts; // 0x8 (OTG_FS device status register (OTG_FS_DSTS)) + Object *fs_diepmsk; // 0x10 (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) + Object *fs_doepmsk; // 0x14 (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) + Object *fs_daint; // 0x18 (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) + Object *fs_daintmsk; // 0x1C (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) + Object *dvbusdis; // 0x28 (OTG_FS device VBUS discharge time register) + Object *dvbuspulse; // 0x2C (OTG_FS device VBUS pulsing time register) + Object *diepempmsk; // 0x34 (OTG_FS device IN endpoint FIFO empty interrupt mask register) + Object *fs_diepctl0; // 0x100 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) + Object *diepctl1; // 0x120 (OTG device endpoint-1 control register) + Object *diepctl2; // 0x140 (OTG device endpoint-2 control register) + Object *diepctl3; // 0x160 (OTG device endpoint-3 control register) + Object *doepctl0; // 0x300 (Device endpoint-0 control register) + Object *doepctl1; // 0x320 (Device endpoint-1 control register) + Object *doepctl2; // 0x340 (Device endpoint-2 control register) + Object *doepctl3; // 0x360 (Device endpoint-3 control register) + Object *diepint0; // 0x108 (Device endpoint-x interrupt register) + Object *diepint1; // 0x128 (Device endpoint-1 interrupt register) + Object *diepint2; // 0x148 (Device endpoint-2 interrupt register) + Object *diepint3; // 0x168 (Device endpoint-3 interrupt register) + Object *doepint0; // 0x308 (Device endpoint-0 interrupt register) + Object *doepint1; // 0x328 (Device endpoint-1 interrupt register) + Object *doepint2; // 0x348 (Device endpoint-2 interrupt register) + Object *doepint3; // 0x368 (Device endpoint-3 interrupt register) + Object *dieptsiz0; // 0x110 (Device endpoint-0 transfer size register) + Object *doeptsiz0; // 0x310 (Device OUT endpoint-0 transfer size register) + Object *dieptsiz1; // 0x130 (Device endpoint-1 transfer size register) + Object *dieptsiz2; // 0x150 (Device endpoint-2 transfer size register) + Object *dieptsiz3; // 0x170 (Device endpoint-3 transfer size register) + Object *dtxfsts0; // 0x118 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts1; // 0x138 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts2; // 0x158 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts3; // 0x178 (OTG_FS device IN endpoint transmit FIFO status register) + Object *doeptsiz1; // 0x330 (Device OUT endpoint-1 transfer size register) + Object *doeptsiz2; // 0x350 (Device OUT endpoint-2 transfer size register) + Object *doeptsiz3; // 0x370 (Device OUT endpoint-3 transfer size register) + } reg; + + struct { + + // FS_DCFG (OTG_FS device configuration register (OTG_FS_DCFG)) bitfields. + struct { + Object *dspd; // [0:1] Device speed + Object *nzlsohsk; // [2:2] Non-zero-length status OUT handshake + Object *dad; // [4:10] Device address + Object *pfivl; // [11:12] Periodic frame interval + } fs_dcfg; + + // FS_DCTL (OTG_FS device control register (OTG_FS_DCTL)) bitfields. + struct { + Object *rwusig; // [0:0] Remote wakeup signaling + Object *sdis; // [1:1] Soft disconnect + Object *ginsts; // [2:2] Global IN NAK status + Object *gonsts; // [3:3] Global OUT NAK status + Object *tctl; // [4:6] Test control + Object *sginak; // [7:7] Set global IN NAK + Object *cginak; // [8:8] Clear global IN NAK + Object *sgonak; // [9:9] Set global OUT NAK + Object *cgonak; // [10:10] Clear global OUT NAK + Object *poprgdne; // [11:11] Power-on programming done + } fs_dctl; + + // FS_DSTS (OTG_FS device status register (OTG_FS_DSTS)) bitfields. + struct { + Object *suspsts; // [0:0] Suspend status + Object *enumspd; // [1:2] Enumerated speed + Object *eerr; // [3:3] Erratic error + Object *fnsof; // [8:21] Frame number of the received SOF + } fs_dsts; + + // FS_DIEPMSK (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (Non-isochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + } fs_diepmsk; + + // FS_DOEPMSK (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *stupm; // [3:3] SETUP phase done mask + Object *otepdm; // [4:4] OUT token received when endpoint disabled mask + } fs_doepmsk; + + // FS_DAINT (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) bitfields. + struct { + Object *iepint; // [0:15] IN endpoint interrupt bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daint; + + // FS_DAINTMSK (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) bitfields. + struct { + Object *iepm; // [0:15] IN EP interrupt mask bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daintmsk; + + // DVBUSDIS (OTG_FS device VBUS discharge time register) bitfields. + struct { + Object *vbusdt; // [0:15] Device VBUS discharge time + } dvbusdis; + + // DVBUSPULSE (OTG_FS device VBUS pulsing time register) bitfields. + struct { + Object *dvbusp; // [0:11] Device VBUS pulsing time + } dvbuspulse; + + // DIEPEMPMSK (OTG_FS device IN endpoint FIFO empty interrupt mask register) bitfields. + struct { + Object *ineptxfem; // [0:15] IN EP Tx FIFO empty interrupt mask bits + } diepempmsk; + + // FS_DIEPCTL0 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) bitfields. + struct { + Object *mpsiz; // [0:1] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } fs_diepctl0; + + // DIEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm_sd1pid; // [29:29] SODDFRM/SD1PID + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl1; + + // DIEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl2; + + // DIEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl3; + + // DOEPCTL0 (Device endpoint-0 control register) bitfields. + struct { + Object *mpsiz; // [0:1] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl0; + + // DOEPCTL1 (Device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl1; + + // DOEPCTL2 (Device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl2; + + // DOEPCTL3 (Device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl3; + + // DIEPINT0 (Device endpoint-x interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint0; + + // DIEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint1; + + // DIEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint2; + + // DIEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint3; + + // DOEPINT0 (Device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint0; + + // DOEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint1; + + // DOEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint2; + + // DOEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint3; + + // DIEPTSIZ0 (Device endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:20] Packet count + } dieptsiz0; + + // DOEPTSIZ0 (Device OUT endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:19] Packet count + Object *stupcnt; // [29:30] SETUP packet count + } doeptsiz0; + + // DIEPTSIZ1 (Device endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz1; + + // DIEPTSIZ2 (Device endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz2; + + // DIEPTSIZ3 (Device endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz3; + + // DTXFSTS0 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts0; + + // DTXFSTS1 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts1; + + // DTXFSTS2 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts2; + + // DTXFSTS3 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts3; + + // DOEPTSIZ1 (Device OUT endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz1; + + // DOEPTSIZ2 (Device OUT endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz2; + + // DOEPTSIZ3 (Device OUT endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz3; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USB_OTG_DEVICEState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USB_OTG_DEVICE_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_global.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_global.c new file mode 100644 index 0000000000..d4b966e9d1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_global.c @@ -0,0 +1,406 @@ +/* + * STM32 - USB_OTG_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_usb_otg_global_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.fs_gotgctl = cm_object_get_child_by_name(obj, "FS_GOTGCTL"); + state->u.f1.reg.fs_gotgint = cm_object_get_child_by_name(obj, "FS_GOTGINT"); + state->u.f1.reg.fs_gahbcfg = cm_object_get_child_by_name(obj, "FS_GAHBCFG"); + state->u.f1.reg.fs_gusbcfg = cm_object_get_child_by_name(obj, "FS_GUSBCFG"); + state->u.f1.reg.fs_grstctl = cm_object_get_child_by_name(obj, "FS_GRSTCTL"); + state->u.f1.reg.fs_gintsts = cm_object_get_child_by_name(obj, "FS_GINTSTS"); + state->u.f1.reg.fs_gintmsk = cm_object_get_child_by_name(obj, "FS_GINTMSK"); + state->u.f1.reg.fs_grxstsr_device = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Device"); + state->u.f1.reg.fs_grxstsr_host = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Host"); + state->u.f1.reg.fs_grxfsiz = cm_object_get_child_by_name(obj, "FS_GRXFSIZ"); + state->u.f1.reg.fs_gnptxfsiz_device = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Device"); + state->u.f1.reg.fs_gnptxfsiz_host = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Host"); + state->u.f1.reg.fs_gnptxsts = cm_object_get_child_by_name(obj, "FS_GNPTXSTS"); + state->u.f1.reg.fs_gccfg = cm_object_get_child_by_name(obj, "FS_GCCFG"); + state->u.f1.reg.fs_cid = cm_object_get_child_by_name(obj, "FS_CID"); + state->u.f1.reg.fs_hptxfsiz = cm_object_get_child_by_name(obj, "FS_HPTXFSIZ"); + state->u.f1.reg.fs_dieptxf1 = cm_object_get_child_by_name(obj, "FS_DIEPTXF1"); + state->u.f1.reg.fs_dieptxf2 = cm_object_get_child_by_name(obj, "FS_DIEPTXF2"); + state->u.f1.reg.fs_dieptxf3 = cm_object_get_child_by_name(obj, "FS_DIEPTXF3"); + + + // FS_GOTGCTL bitfields. + state->u.f1.fld.fs_gotgctl.srqscs = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "SRQSCS"); + state->u.f1.fld.fs_gotgctl.srq = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "SRQ"); + state->u.f1.fld.fs_gotgctl.hngscs = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "HNGSCS"); + state->u.f1.fld.fs_gotgctl.hnprq = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "HNPRQ"); + state->u.f1.fld.fs_gotgctl.hshnpen = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "HSHNPEN"); + state->u.f1.fld.fs_gotgctl.dhnpen = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "DHNPEN"); + state->u.f1.fld.fs_gotgctl.cidsts = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "CIDSTS"); + state->u.f1.fld.fs_gotgctl.dbct = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "DBCT"); + state->u.f1.fld.fs_gotgctl.asvld = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "ASVLD"); + state->u.f1.fld.fs_gotgctl.bsvld = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgctl, "BSVLD"); + + // FS_GOTGINT bitfields. + state->u.f1.fld.fs_gotgint.sedet = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgint, "SEDET"); + state->u.f1.fld.fs_gotgint.srsschg = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgint, "SRSSCHG"); + state->u.f1.fld.fs_gotgint.hnsschg = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgint, "HNSSCHG"); + state->u.f1.fld.fs_gotgint.hngdet = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgint, "HNGDET"); + state->u.f1.fld.fs_gotgint.adtochg = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgint, "ADTOCHG"); + state->u.f1.fld.fs_gotgint.dbcdne = cm_object_get_child_by_name(state->u.f1.reg.fs_gotgint, "DBCDNE"); + + // FS_GAHBCFG bitfields. + state->u.f1.fld.fs_gahbcfg.gint = cm_object_get_child_by_name(state->u.f1.reg.fs_gahbcfg, "GINT"); + state->u.f1.fld.fs_gahbcfg.txfelvl = cm_object_get_child_by_name(state->u.f1.reg.fs_gahbcfg, "TXFELVL"); + state->u.f1.fld.fs_gahbcfg.ptxfelvl = cm_object_get_child_by_name(state->u.f1.reg.fs_gahbcfg, "PTXFELVL"); + + // FS_GUSBCFG bitfields. + state->u.f1.fld.fs_gusbcfg.tocal = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "TOCAL"); + state->u.f1.fld.fs_gusbcfg.physel = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "PHYSEL"); + state->u.f1.fld.fs_gusbcfg.srpcap = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "SRPCAP"); + state->u.f1.fld.fs_gusbcfg.hnpcap = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "HNPCAP"); + state->u.f1.fld.fs_gusbcfg.trdt = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "TRDT"); + state->u.f1.fld.fs_gusbcfg.fhmod = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "FHMOD"); + state->u.f1.fld.fs_gusbcfg.fdmod = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "FDMOD"); + state->u.f1.fld.fs_gusbcfg.ctxpkt = cm_object_get_child_by_name(state->u.f1.reg.fs_gusbcfg, "CTXPKT"); + + // FS_GRSTCTL bitfields. + state->u.f1.fld.fs_grstctl.csrst = cm_object_get_child_by_name(state->u.f1.reg.fs_grstctl, "CSRST"); + state->u.f1.fld.fs_grstctl.hsrst = cm_object_get_child_by_name(state->u.f1.reg.fs_grstctl, "HSRST"); + state->u.f1.fld.fs_grstctl.fcrst = cm_object_get_child_by_name(state->u.f1.reg.fs_grstctl, "FCRST"); + state->u.f1.fld.fs_grstctl.rxfflsh = cm_object_get_child_by_name(state->u.f1.reg.fs_grstctl, "RXFFLSH"); + state->u.f1.fld.fs_grstctl.txfflsh = cm_object_get_child_by_name(state->u.f1.reg.fs_grstctl, "TXFFLSH"); + state->u.f1.fld.fs_grstctl.txfnum = cm_object_get_child_by_name(state->u.f1.reg.fs_grstctl, "TXFNUM"); + state->u.f1.fld.fs_grstctl.ahbidl = cm_object_get_child_by_name(state->u.f1.reg.fs_grstctl, "AHBIDL"); + + // FS_GINTSTS bitfields. + state->u.f1.fld.fs_gintsts.cmod = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "CMOD"); + state->u.f1.fld.fs_gintsts.mmis = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "MMIS"); + state->u.f1.fld.fs_gintsts.otgint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "OTGINT"); + state->u.f1.fld.fs_gintsts.sof = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "SOF"); + state->u.f1.fld.fs_gintsts.rxflvl = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "RXFLVL"); + state->u.f1.fld.fs_gintsts.nptxfe = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "NPTXFE"); + state->u.f1.fld.fs_gintsts.ginakeff = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "GINAKEFF"); + state->u.f1.fld.fs_gintsts.goutnakeff = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "GOUTNAKEFF"); + state->u.f1.fld.fs_gintsts.esusp = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "ESUSP"); + state->u.f1.fld.fs_gintsts.usbsusp = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "USBSUSP"); + state->u.f1.fld.fs_gintsts.usbrst = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "USBRST"); + state->u.f1.fld.fs_gintsts.enumdne = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "ENUMDNE"); + state->u.f1.fld.fs_gintsts.isoodrp = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "ISOODRP"); + state->u.f1.fld.fs_gintsts.eopf = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "EOPF"); + state->u.f1.fld.fs_gintsts.iepint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "IEPINT"); + state->u.f1.fld.fs_gintsts.oepint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "OEPINT"); + state->u.f1.fld.fs_gintsts.iisoixfr = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "IISOIXFR"); + state->u.f1.fld.fs_gintsts.ipxfr_incompisoout = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "IPXFR_INCOMPISOOUT"); + state->u.f1.fld.fs_gintsts.hprtint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "HPRTINT"); + state->u.f1.fld.fs_gintsts.hcint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "HCINT"); + state->u.f1.fld.fs_gintsts.ptxfe = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "PTXFE"); + state->u.f1.fld.fs_gintsts.cidschg = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "CIDSCHG"); + state->u.f1.fld.fs_gintsts.discint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "DISCINT"); + state->u.f1.fld.fs_gintsts.srqint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "SRQINT"); + state->u.f1.fld.fs_gintsts.wkupint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintsts, "WKUPINT"); + + // FS_GINTMSK bitfields. + state->u.f1.fld.fs_gintmsk.mmism = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "MMISM"); + state->u.f1.fld.fs_gintmsk.otgint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "OTGINT"); + state->u.f1.fld.fs_gintmsk.sofm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "SOFM"); + state->u.f1.fld.fs_gintmsk.rxflvlm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "RXFLVLM"); + state->u.f1.fld.fs_gintmsk.nptxfem = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "NPTXFEM"); + state->u.f1.fld.fs_gintmsk.ginakeffm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "GINAKEFFM"); + state->u.f1.fld.fs_gintmsk.gonakeffm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "GONAKEFFM"); + state->u.f1.fld.fs_gintmsk.esuspm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "ESUSPM"); + state->u.f1.fld.fs_gintmsk.usbsuspm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "USBSUSPM"); + state->u.f1.fld.fs_gintmsk.usbrst = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "USBRST"); + state->u.f1.fld.fs_gintmsk.enumdnem = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "ENUMDNEM"); + state->u.f1.fld.fs_gintmsk.isoodrpm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "ISOODRPM"); + state->u.f1.fld.fs_gintmsk.eopfm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "EOPFM"); + state->u.f1.fld.fs_gintmsk.epmism = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "EPMISM"); + state->u.f1.fld.fs_gintmsk.iepint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "IEPINT"); + state->u.f1.fld.fs_gintmsk.oepint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "OEPINT"); + state->u.f1.fld.fs_gintmsk.iisoixfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "IISOIXFRM"); + state->u.f1.fld.fs_gintmsk.ipxfrm_iisooxfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "IPXFRM_IISOOXFRM"); + state->u.f1.fld.fs_gintmsk.prtim = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "PRTIM"); + state->u.f1.fld.fs_gintmsk.hcim = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "HCIM"); + state->u.f1.fld.fs_gintmsk.ptxfem = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "PTXFEM"); + state->u.f1.fld.fs_gintmsk.cidschgm = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "CIDSCHGM"); + state->u.f1.fld.fs_gintmsk.discint = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "DISCINT"); + state->u.f1.fld.fs_gintmsk.srqim = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "SRQIM"); + state->u.f1.fld.fs_gintmsk.wuim = cm_object_get_child_by_name(state->u.f1.reg.fs_gintmsk, "WUIM"); + + // FS_GRXSTSR_Device bitfields. + state->u.f1.fld.fs_grxstsr_device.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_device, "EPNUM"); + state->u.f1.fld.fs_grxstsr_device.bcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_device, "BCNT"); + state->u.f1.fld.fs_grxstsr_device.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_device, "DPID"); + state->u.f1.fld.fs_grxstsr_device.pktsts = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_device, "PKTSTS"); + state->u.f1.fld.fs_grxstsr_device.frmnum = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_device, "FRMNUM"); + + // FS_GRXSTSR_Host bitfields. + state->u.f1.fld.fs_grxstsr_host.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_host, "EPNUM"); + state->u.f1.fld.fs_grxstsr_host.bcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_host, "BCNT"); + state->u.f1.fld.fs_grxstsr_host.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_host, "DPID"); + state->u.f1.fld.fs_grxstsr_host.pktsts = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_host, "PKTSTS"); + state->u.f1.fld.fs_grxstsr_host.frmnum = cm_object_get_child_by_name(state->u.f1.reg.fs_grxstsr_host, "FRMNUM"); + + // FS_GRXFSIZ bitfields. + state->u.f1.fld.fs_grxfsiz.rxfd = cm_object_get_child_by_name(state->u.f1.reg.fs_grxfsiz, "RXFD"); + + // FS_GNPTXFSIZ_Device bitfields. + state->u.f1.fld.fs_gnptxfsiz_device.tx0fsa = cm_object_get_child_by_name(state->u.f1.reg.fs_gnptxfsiz_device, "TX0FSA"); + state->u.f1.fld.fs_gnptxfsiz_device.tx0fd = cm_object_get_child_by_name(state->u.f1.reg.fs_gnptxfsiz_device, "TX0FD"); + + // FS_GNPTXFSIZ_Host bitfields. + state->u.f1.fld.fs_gnptxfsiz_host.nptxfsa = cm_object_get_child_by_name(state->u.f1.reg.fs_gnptxfsiz_host, "NPTXFSA"); + state->u.f1.fld.fs_gnptxfsiz_host.nptxfd = cm_object_get_child_by_name(state->u.f1.reg.fs_gnptxfsiz_host, "NPTXFD"); + + // FS_GNPTXSTS bitfields. + state->u.f1.fld.fs_gnptxsts.nptxfsav = cm_object_get_child_by_name(state->u.f1.reg.fs_gnptxsts, "NPTXFSAV"); + state->u.f1.fld.fs_gnptxsts.nptqxsav = cm_object_get_child_by_name(state->u.f1.reg.fs_gnptxsts, "NPTQXSAV"); + state->u.f1.fld.fs_gnptxsts.nptxqtop = cm_object_get_child_by_name(state->u.f1.reg.fs_gnptxsts, "NPTXQTOP"); + + // FS_GCCFG bitfields. + state->u.f1.fld.fs_gccfg.pwrdwn = cm_object_get_child_by_name(state->u.f1.reg.fs_gccfg, "PWRDWN"); + state->u.f1.fld.fs_gccfg.vbusasen = cm_object_get_child_by_name(state->u.f1.reg.fs_gccfg, "VBUSASEN"); + state->u.f1.fld.fs_gccfg.vbusbsen = cm_object_get_child_by_name(state->u.f1.reg.fs_gccfg, "VBUSBSEN"); + state->u.f1.fld.fs_gccfg.sofouten = cm_object_get_child_by_name(state->u.f1.reg.fs_gccfg, "SOFOUTEN"); + + // FS_CID bitfields. + state->u.f1.fld.fs_cid.product_id = cm_object_get_child_by_name(state->u.f1.reg.fs_cid, "PRODUCT_ID"); + + // FS_HPTXFSIZ bitfields. + state->u.f1.fld.fs_hptxfsiz.ptxsa = cm_object_get_child_by_name(state->u.f1.reg.fs_hptxfsiz, "PTXSA"); + state->u.f1.fld.fs_hptxfsiz.ptxfsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hptxfsiz, "PTXFSIZ"); + + // FS_DIEPTXF1 bitfields. + state->u.f1.fld.fs_dieptxf1.ineptxsa = cm_object_get_child_by_name(state->u.f1.reg.fs_dieptxf1, "INEPTXSA"); + state->u.f1.fld.fs_dieptxf1.ineptxfd = cm_object_get_child_by_name(state->u.f1.reg.fs_dieptxf1, "INEPTXFD"); + + // FS_DIEPTXF2 bitfields. + state->u.f1.fld.fs_dieptxf2.ineptxsa = cm_object_get_child_by_name(state->u.f1.reg.fs_dieptxf2, "INEPTXSA"); + state->u.f1.fld.fs_dieptxf2.ineptxfd = cm_object_get_child_by_name(state->u.f1.reg.fs_dieptxf2, "INEPTXFD"); + + // FS_DIEPTXF3 bitfields. + state->u.f1.fld.fs_dieptxf3.ineptxsa = cm_object_get_child_by_name(state->u.f1.reg.fs_dieptxf3, "INEPTXSA"); + state->u.f1.fld.fs_dieptxf3.ineptxfd = cm_object_get_child_by_name(state->u.f1.reg.fs_dieptxf3, "INEPTXFD"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usb_otg_global_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usb_otg_global_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usb_otg_global_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usb_otg_global_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usb_otg_global_is_enabled(Object *obj) +{ + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usb_otg_global_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usb_otg_global_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USB_OTG_GLOBAL)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USB_OTG_GLOBALState *state = STM32_USB_OTG_GLOBAL_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USB_OTG_GLOBAL"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_usb_otg_global_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_global_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_usb_otg_global_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_global_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_usb_otg_global_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USB_OTG_GLOBALEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usb_otg_global_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USB_OTG_GLOBAL); +} + +static void stm32_usb_otg_global_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usb_otg_global_reset_callback; + dc->realize = stm32_usb_otg_global_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usb_otg_global_is_enabled; +} + +static const TypeInfo stm32_usb_otg_global_type_info = { + .name = TYPE_STM32_USB_OTG_GLOBAL, + .parent = TYPE_STM32_USB_OTG_GLOBAL_PARENT, + .instance_init = stm32_usb_otg_global_instance_init_callback, + .instance_size = sizeof(STM32USB_OTG_GLOBALState), + .class_init = stm32_usb_otg_global_class_init_callback, + .class_size = sizeof(STM32USB_OTG_GLOBALClass) }; + +static void stm32_usb_otg_global_register_types(void) +{ + type_register_static(&stm32_usb_otg_global_type_info); +} + +type_init(stm32_usb_otg_global_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_global.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_global.h new file mode 100644 index 0000000000..006e527e56 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_global.h @@ -0,0 +1,309 @@ +/* + * STM32 - USB_OTG_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USB_OTG_GLOBAL_H_ +#define STM32_USB_OTG_GLOBAL_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USB_OTG_GLOBAL DEVICE_PATH_STM32 "USB_OTG_GLOBAL" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USB_OTG_GLOBAL TYPE_STM32_PREFIX "usb_otg_global" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USB_OTG_GLOBAL_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USB_OTG_GLOBALParentClass; +typedef PeripheralState STM32USB_OTG_GLOBALParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USB_OTG_GLOBAL_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USB_OTG_GLOBALClass, (obj), TYPE_STM32_USB_OTG_GLOBAL) +#define STM32_USB_OTG_GLOBAL_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USB_OTG_GLOBALClass, (klass), TYPE_STM32_USB_OTG_GLOBAL) + +typedef struct { + // private: + STM32USB_OTG_GLOBALParentClass parent_class; + // public: + + // None, so far. +} STM32USB_OTG_GLOBALClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USB_OTG_GLOBAL_STATE(obj) \ + OBJECT_CHECK(STM32USB_OTG_GLOBALState, (obj), TYPE_STM32_USB_OTG_GLOBAL) + +typedef struct { + // private: + STM32USB_OTG_GLOBALParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 USB_OTG_GLOBAL (USB on the go full speed) registers. + struct { + Object *fs_gotgctl; // 0x0 (OTG_FS control and status register (OTG_FS_GOTGCTL)) + Object *fs_gotgint; // 0x4 (OTG_FS interrupt register (OTG_FS_GOTGINT)) + Object *fs_gahbcfg; // 0x8 (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) + Object *fs_gusbcfg; // 0xC (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) + Object *fs_grstctl; // 0x10 (OTG_FS reset register (OTG_FS_GRSTCTL)) + Object *fs_gintsts; // 0x14 (OTG_FS core interrupt register (OTG_FS_GINTSTS)) + Object *fs_gintmsk; // 0x18 (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) + Object *fs_grxstsr_device; // 0x1C (OTG_FS Receive status debug read(Device mode)) + Object *fs_grxstsr_host; // 0x1C (OTG_FS Receive status debug read(Host mode)) + Object *fs_grxfsiz; // 0x24 (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) + Object *fs_gnptxfsiz_device; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Device mode)) + Object *fs_gnptxfsiz_host; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Host mode)) + Object *fs_gnptxsts; // 0x2C (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) + Object *fs_gccfg; // 0x38 (OTG_FS general core configuration register (OTG_FS_GCCFG)) + Object *fs_cid; // 0x3C (Core ID register) + Object *fs_hptxfsiz; // 0x100 (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) + Object *fs_dieptxf1; // 0x104 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) + Object *fs_dieptxf2; // 0x108 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) + Object *fs_dieptxf3; // 0x10C (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) + } reg; + + struct { + + // FS_GOTGCTL (OTG_FS control and status register (OTG_FS_GOTGCTL)) bitfields. + struct { + Object *srqscs; // [0:0] Session request success + Object *srq; // [1:1] Session request + Object *hngscs; // [8:8] Host negotiation success + Object *hnprq; // [9:9] HNP request + Object *hshnpen; // [10:10] Host set HNP enable + Object *dhnpen; // [11:11] Device HNP enabled + Object *cidsts; // [16:16] Connector ID status + Object *dbct; // [17:17] Long/short debounce time + Object *asvld; // [18:18] A-session valid + Object *bsvld; // [19:19] B-session valid + } fs_gotgctl; + + // FS_GOTGINT (OTG_FS interrupt register (OTG_FS_GOTGINT)) bitfields. + struct { + Object *sedet; // [2:2] Session end detected + Object *srsschg; // [8:8] Session request success status change + Object *hnsschg; // [9:9] Host negotiation success status change + Object *hngdet; // [17:17] Host negotiation detected + Object *adtochg; // [18:18] A-device timeout change + Object *dbcdne; // [19:19] Debounce done + } fs_gotgint; + + // FS_GAHBCFG (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) bitfields. + struct { + Object *gint; // [0:0] Global interrupt mask + Object *txfelvl; // [7:7] TxFIFO empty level + Object *ptxfelvl; // [8:8] Periodic TxFIFO empty level + } fs_gahbcfg; + + // FS_GUSBCFG (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) bitfields. + struct { + Object *tocal; // [0:2] FS timeout calibration + Object *physel; // [7:7] Full Speed serial transceiver select + Object *srpcap; // [8:8] SRP-capable + Object *hnpcap; // [9:9] HNP-capable + Object *trdt; // [10:13] USB turnaround time + Object *fhmod; // [29:29] Force host mode + Object *fdmod; // [30:30] Force device mode + Object *ctxpkt; // [31:31] Corrupt Tx packet + } fs_gusbcfg; + + // FS_GRSTCTL (OTG_FS reset register (OTG_FS_GRSTCTL)) bitfields. + struct { + Object *csrst; // [0:0] Core soft reset + Object *hsrst; // [1:1] HCLK soft reset + Object *fcrst; // [2:2] Host frame counter reset + Object *rxfflsh; // [4:4] RxFIFO flush + Object *txfflsh; // [5:5] TxFIFO flush + Object *txfnum; // [6:10] TxFIFO number + Object *ahbidl; // [31:31] AHB master idle + } fs_grstctl; + + // FS_GINTSTS (OTG_FS core interrupt register (OTG_FS_GINTSTS)) bitfields. + struct { + Object *cmod; // [0:0] Current mode of operation + Object *mmis; // [1:1] Mode mismatch interrupt + Object *otgint; // [2:2] OTG interrupt + Object *sof; // [3:3] Start of frame + Object *rxflvl; // [4:4] RxFIFO non-empty + Object *nptxfe; // [5:5] Non-periodic TxFIFO empty + Object *ginakeff; // [6:6] Global IN non-periodic NAK effective + Object *goutnakeff; // [7:7] Global OUT NAK effective + Object *esusp; // [10:10] Early suspend + Object *usbsusp; // [11:11] USB suspend + Object *usbrst; // [12:12] USB reset + Object *enumdne; // [13:13] Enumeration done + Object *isoodrp; // [14:14] Isochronous OUT packet dropped interrupt + Object *eopf; // [15:15] End of periodic frame interrupt + Object *iepint; // [18:18] IN endpoint interrupt + Object *oepint; // [19:19] OUT endpoint interrupt + Object *iisoixfr; // [20:20] Incomplete isochronous IN transfer + Object *ipxfr_incompisoout; // [21:21] Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + Object *hprtint; // [24:24] Host port interrupt + Object *hcint; // [25:25] Host channels interrupt + Object *ptxfe; // [26:26] Periodic TxFIFO empty + Object *cidschg; // [28:28] Connector ID status change + Object *discint; // [29:29] Disconnect detected interrupt + Object *srqint; // [30:30] Session request/new session detected interrupt + Object *wkupint; // [31:31] Resume/remote wakeup detected interrupt + } fs_gintsts; + + // FS_GINTMSK (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) bitfields. + struct { + Object *mmism; // [1:1] Mode mismatch interrupt mask + Object *otgint; // [2:2] OTG interrupt mask + Object *sofm; // [3:3] Start of frame mask + Object *rxflvlm; // [4:4] Receive FIFO non-empty mask + Object *nptxfem; // [5:5] Non-periodic TxFIFO empty mask + Object *ginakeffm; // [6:6] Global non-periodic IN NAK effective mask + Object *gonakeffm; // [7:7] Global OUT NAK effective mask + Object *esuspm; // [10:10] Early suspend mask + Object *usbsuspm; // [11:11] USB suspend mask + Object *usbrst; // [12:12] USB reset mask + Object *enumdnem; // [13:13] Enumeration done mask + Object *isoodrpm; // [14:14] Isochronous OUT packet dropped interrupt mask + Object *eopfm; // [15:15] End of periodic frame interrupt mask + Object *epmism; // [17:17] Endpoint mismatch interrupt mask + Object *iepint; // [18:18] IN endpoints interrupt mask + Object *oepint; // [19:19] OUT endpoints interrupt mask + Object *iisoixfrm; // [20:20] Incomplete isochronous IN transfer mask + Object *ipxfrm_iisooxfrm; // [21:21] Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + Object *prtim; // [24:24] Host port interrupt mask + Object *hcim; // [25:25] Host channels interrupt mask + Object *ptxfem; // [26:26] Periodic TxFIFO empty mask + Object *cidschgm; // [28:28] Connector ID status change mask + Object *discint; // [29:29] Disconnect detected interrupt mask + Object *srqim; // [30:30] Session request/new session detected interrupt mask + Object *wuim; // [31:31] Resume/remote wakeup detected interrupt mask + } fs_gintmsk; + + // FS_GRXSTSR_Device (OTG_FS Receive status debug read(Device mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_device; + + // FS_GRXSTSR_Host (OTG_FS Receive status debug read(Host mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_host; + + // FS_GRXFSIZ (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) bitfields. + struct { + Object *rxfd; // [0:15] RxFIFO depth + } fs_grxfsiz; + + // FS_GNPTXFSIZ_Device (OTG_FS non-periodic transmit FIFO size register (Device mode)) bitfields. + struct { + Object *tx0fsa; // [0:15] Endpoint 0 transmit RAM start address + Object *tx0fd; // [16:31] Endpoint 0 TxFIFO depth + } fs_gnptxfsiz_device; + + // FS_GNPTXFSIZ_Host (OTG_FS non-periodic transmit FIFO size register (Host mode)) bitfields. + struct { + Object *nptxfsa; // [0:15] Non-periodic transmit RAM start address + Object *nptxfd; // [16:31] Non-periodic TxFIFO depth + } fs_gnptxfsiz_host; + + // FS_GNPTXSTS (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) bitfields. + struct { + Object *nptxfsav; // [0:15] Non-periodic TxFIFO space available + Object *nptqxsav; // [16:23] Non-periodic transmit request queue space available + Object *nptxqtop; // [24:30] Top of the non-periodic transmit request queue + } fs_gnptxsts; + + // FS_GCCFG (OTG_FS general core configuration register (OTG_FS_GCCFG)) bitfields. + struct { + Object *pwrdwn; // [16:16] Power down + Object *vbusasen; // [18:18] Enable the VBUS sensing device + Object *vbusbsen; // [19:19] Enable the VBUS sensing device + Object *sofouten; // [20:20] SOF output enable + } fs_gccfg; + + // FS_CID (Core ID register) bitfields. + struct { + Object *product_id; // [0:31] Product ID field + } fs_cid; + + // FS_HPTXFSIZ (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) bitfields. + struct { + Object *ptxsa; // [0:15] Host periodic TxFIFO start address + Object *ptxfsiz; // [16:31] Host periodic TxFIFO depth + } fs_hptxfsiz; + + // FS_DIEPTXF1 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO2 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf1; + + // FS_DIEPTXF2 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO3 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf2; + + // FS_DIEPTXF3 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO4 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf3; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USB_OTG_GLOBALState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USB_OTG_GLOBAL_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_host.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_host.c new file mode 100644 index 0000000000..8f00004dc7 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_host.c @@ -0,0 +1,630 @@ +/* + * STM32 - USB_OTG_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_usb_otg_host_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.fs_hcfg = cm_object_get_child_by_name(obj, "FS_HCFG"); + state->u.f1.reg.hfir = cm_object_get_child_by_name(obj, "HFIR"); + state->u.f1.reg.fs_hfnum = cm_object_get_child_by_name(obj, "FS_HFNUM"); + state->u.f1.reg.fs_hptxsts = cm_object_get_child_by_name(obj, "FS_HPTXSTS"); + state->u.f1.reg.haint = cm_object_get_child_by_name(obj, "HAINT"); + state->u.f1.reg.haintmsk = cm_object_get_child_by_name(obj, "HAINTMSK"); + state->u.f1.reg.fs_hprt = cm_object_get_child_by_name(obj, "FS_HPRT"); + state->u.f1.reg.fs_hcchar0 = cm_object_get_child_by_name(obj, "FS_HCCHAR0"); + state->u.f1.reg.fs_hcchar1 = cm_object_get_child_by_name(obj, "FS_HCCHAR1"); + state->u.f1.reg.fs_hcchar2 = cm_object_get_child_by_name(obj, "FS_HCCHAR2"); + state->u.f1.reg.fs_hcchar3 = cm_object_get_child_by_name(obj, "FS_HCCHAR3"); + state->u.f1.reg.fs_hcchar4 = cm_object_get_child_by_name(obj, "FS_HCCHAR4"); + state->u.f1.reg.fs_hcchar5 = cm_object_get_child_by_name(obj, "FS_HCCHAR5"); + state->u.f1.reg.fs_hcchar6 = cm_object_get_child_by_name(obj, "FS_HCCHAR6"); + state->u.f1.reg.fs_hcchar7 = cm_object_get_child_by_name(obj, "FS_HCCHAR7"); + state->u.f1.reg.fs_hcint0 = cm_object_get_child_by_name(obj, "FS_HCINT0"); + state->u.f1.reg.fs_hcint1 = cm_object_get_child_by_name(obj, "FS_HCINT1"); + state->u.f1.reg.fs_hcint2 = cm_object_get_child_by_name(obj, "FS_HCINT2"); + state->u.f1.reg.fs_hcint3 = cm_object_get_child_by_name(obj, "FS_HCINT3"); + state->u.f1.reg.fs_hcint4 = cm_object_get_child_by_name(obj, "FS_HCINT4"); + state->u.f1.reg.fs_hcint5 = cm_object_get_child_by_name(obj, "FS_HCINT5"); + state->u.f1.reg.fs_hcint6 = cm_object_get_child_by_name(obj, "FS_HCINT6"); + state->u.f1.reg.fs_hcint7 = cm_object_get_child_by_name(obj, "FS_HCINT7"); + state->u.f1.reg.fs_hcintmsk0 = cm_object_get_child_by_name(obj, "FS_HCINTMSK0"); + state->u.f1.reg.fs_hcintmsk1 = cm_object_get_child_by_name(obj, "FS_HCINTMSK1"); + state->u.f1.reg.fs_hcintmsk2 = cm_object_get_child_by_name(obj, "FS_HCINTMSK2"); + state->u.f1.reg.fs_hcintmsk3 = cm_object_get_child_by_name(obj, "FS_HCINTMSK3"); + state->u.f1.reg.fs_hcintmsk4 = cm_object_get_child_by_name(obj, "FS_HCINTMSK4"); + state->u.f1.reg.fs_hcintmsk5 = cm_object_get_child_by_name(obj, "FS_HCINTMSK5"); + state->u.f1.reg.fs_hcintmsk6 = cm_object_get_child_by_name(obj, "FS_HCINTMSK6"); + state->u.f1.reg.fs_hcintmsk7 = cm_object_get_child_by_name(obj, "FS_HCINTMSK7"); + state->u.f1.reg.fs_hctsiz0 = cm_object_get_child_by_name(obj, "FS_HCTSIZ0"); + state->u.f1.reg.fs_hctsiz1 = cm_object_get_child_by_name(obj, "FS_HCTSIZ1"); + state->u.f1.reg.fs_hctsiz2 = cm_object_get_child_by_name(obj, "FS_HCTSIZ2"); + state->u.f1.reg.fs_hctsiz3 = cm_object_get_child_by_name(obj, "FS_HCTSIZ3"); + state->u.f1.reg.fs_hctsiz4 = cm_object_get_child_by_name(obj, "FS_HCTSIZ4"); + state->u.f1.reg.fs_hctsiz5 = cm_object_get_child_by_name(obj, "FS_HCTSIZ5"); + state->u.f1.reg.fs_hctsiz6 = cm_object_get_child_by_name(obj, "FS_HCTSIZ6"); + state->u.f1.reg.fs_hctsiz7 = cm_object_get_child_by_name(obj, "FS_HCTSIZ7"); + + + // FS_HCFG bitfields. + state->u.f1.fld.fs_hcfg.fslspcs = cm_object_get_child_by_name(state->u.f1.reg.fs_hcfg, "FSLSPCS"); + state->u.f1.fld.fs_hcfg.fslss = cm_object_get_child_by_name(state->u.f1.reg.fs_hcfg, "FSLSS"); + + // HFIR bitfields. + state->u.f1.fld.hfir.frivl = cm_object_get_child_by_name(state->u.f1.reg.hfir, "FRIVL"); + + // FS_HFNUM bitfields. + state->u.f1.fld.fs_hfnum.frnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hfnum, "FRNUM"); + state->u.f1.fld.fs_hfnum.ftrem = cm_object_get_child_by_name(state->u.f1.reg.fs_hfnum, "FTREM"); + + // FS_HPTXSTS bitfields. + state->u.f1.fld.fs_hptxsts.ptxfsavl = cm_object_get_child_by_name(state->u.f1.reg.fs_hptxsts, "PTXFSAVL"); + state->u.f1.fld.fs_hptxsts.ptxqsav = cm_object_get_child_by_name(state->u.f1.reg.fs_hptxsts, "PTXQSAV"); + state->u.f1.fld.fs_hptxsts.ptxqtop = cm_object_get_child_by_name(state->u.f1.reg.fs_hptxsts, "PTXQTOP"); + + // HAINT bitfields. + state->u.f1.fld.haint.haint = cm_object_get_child_by_name(state->u.f1.reg.haint, "HAINT"); + + // HAINTMSK bitfields. + state->u.f1.fld.haintmsk.haintm = cm_object_get_child_by_name(state->u.f1.reg.haintmsk, "HAINTM"); + + // FS_HPRT bitfields. + state->u.f1.fld.fs_hprt.pcsts = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PCSTS"); + state->u.f1.fld.fs_hprt.pcdet = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PCDET"); + state->u.f1.fld.fs_hprt.pena = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PENA"); + state->u.f1.fld.fs_hprt.penchng = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PENCHNG"); + state->u.f1.fld.fs_hprt.poca = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "POCA"); + state->u.f1.fld.fs_hprt.pocchng = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "POCCHNG"); + state->u.f1.fld.fs_hprt.pres = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PRES"); + state->u.f1.fld.fs_hprt.psusp = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PSUSP"); + state->u.f1.fld.fs_hprt.prst = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PRST"); + state->u.f1.fld.fs_hprt.plsts = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PLSTS"); + state->u.f1.fld.fs_hprt.ppwr = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PPWR"); + state->u.f1.fld.fs_hprt.ptctl = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PTCTL"); + state->u.f1.fld.fs_hprt.pspd = cm_object_get_child_by_name(state->u.f1.reg.fs_hprt, "PSPD"); + + // FS_HCCHAR0 bitfields. + state->u.f1.fld.fs_hcchar0.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "MPSIZ"); + state->u.f1.fld.fs_hcchar0.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "EPNUM"); + state->u.f1.fld.fs_hcchar0.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "EPDIR"); + state->u.f1.fld.fs_hcchar0.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "LSDEV"); + state->u.f1.fld.fs_hcchar0.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "EPTYP"); + state->u.f1.fld.fs_hcchar0.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "MCNT"); + state->u.f1.fld.fs_hcchar0.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "DAD"); + state->u.f1.fld.fs_hcchar0.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "ODDFRM"); + state->u.f1.fld.fs_hcchar0.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "CHDIS"); + state->u.f1.fld.fs_hcchar0.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar0, "CHENA"); + + // FS_HCCHAR1 bitfields. + state->u.f1.fld.fs_hcchar1.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "MPSIZ"); + state->u.f1.fld.fs_hcchar1.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "EPNUM"); + state->u.f1.fld.fs_hcchar1.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "EPDIR"); + state->u.f1.fld.fs_hcchar1.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "LSDEV"); + state->u.f1.fld.fs_hcchar1.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "EPTYP"); + state->u.f1.fld.fs_hcchar1.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "MCNT"); + state->u.f1.fld.fs_hcchar1.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "DAD"); + state->u.f1.fld.fs_hcchar1.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "ODDFRM"); + state->u.f1.fld.fs_hcchar1.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "CHDIS"); + state->u.f1.fld.fs_hcchar1.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar1, "CHENA"); + + // FS_HCCHAR2 bitfields. + state->u.f1.fld.fs_hcchar2.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "MPSIZ"); + state->u.f1.fld.fs_hcchar2.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "EPNUM"); + state->u.f1.fld.fs_hcchar2.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "EPDIR"); + state->u.f1.fld.fs_hcchar2.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "LSDEV"); + state->u.f1.fld.fs_hcchar2.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "EPTYP"); + state->u.f1.fld.fs_hcchar2.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "MCNT"); + state->u.f1.fld.fs_hcchar2.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "DAD"); + state->u.f1.fld.fs_hcchar2.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "ODDFRM"); + state->u.f1.fld.fs_hcchar2.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "CHDIS"); + state->u.f1.fld.fs_hcchar2.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar2, "CHENA"); + + // FS_HCCHAR3 bitfields. + state->u.f1.fld.fs_hcchar3.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "MPSIZ"); + state->u.f1.fld.fs_hcchar3.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "EPNUM"); + state->u.f1.fld.fs_hcchar3.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "EPDIR"); + state->u.f1.fld.fs_hcchar3.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "LSDEV"); + state->u.f1.fld.fs_hcchar3.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "EPTYP"); + state->u.f1.fld.fs_hcchar3.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "MCNT"); + state->u.f1.fld.fs_hcchar3.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "DAD"); + state->u.f1.fld.fs_hcchar3.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "ODDFRM"); + state->u.f1.fld.fs_hcchar3.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "CHDIS"); + state->u.f1.fld.fs_hcchar3.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar3, "CHENA"); + + // FS_HCCHAR4 bitfields. + state->u.f1.fld.fs_hcchar4.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "MPSIZ"); + state->u.f1.fld.fs_hcchar4.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "EPNUM"); + state->u.f1.fld.fs_hcchar4.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "EPDIR"); + state->u.f1.fld.fs_hcchar4.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "LSDEV"); + state->u.f1.fld.fs_hcchar4.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "EPTYP"); + state->u.f1.fld.fs_hcchar4.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "MCNT"); + state->u.f1.fld.fs_hcchar4.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "DAD"); + state->u.f1.fld.fs_hcchar4.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "ODDFRM"); + state->u.f1.fld.fs_hcchar4.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "CHDIS"); + state->u.f1.fld.fs_hcchar4.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar4, "CHENA"); + + // FS_HCCHAR5 bitfields. + state->u.f1.fld.fs_hcchar5.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "MPSIZ"); + state->u.f1.fld.fs_hcchar5.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "EPNUM"); + state->u.f1.fld.fs_hcchar5.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "EPDIR"); + state->u.f1.fld.fs_hcchar5.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "LSDEV"); + state->u.f1.fld.fs_hcchar5.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "EPTYP"); + state->u.f1.fld.fs_hcchar5.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "MCNT"); + state->u.f1.fld.fs_hcchar5.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "DAD"); + state->u.f1.fld.fs_hcchar5.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "ODDFRM"); + state->u.f1.fld.fs_hcchar5.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "CHDIS"); + state->u.f1.fld.fs_hcchar5.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar5, "CHENA"); + + // FS_HCCHAR6 bitfields. + state->u.f1.fld.fs_hcchar6.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "MPSIZ"); + state->u.f1.fld.fs_hcchar6.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "EPNUM"); + state->u.f1.fld.fs_hcchar6.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "EPDIR"); + state->u.f1.fld.fs_hcchar6.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "LSDEV"); + state->u.f1.fld.fs_hcchar6.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "EPTYP"); + state->u.f1.fld.fs_hcchar6.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "MCNT"); + state->u.f1.fld.fs_hcchar6.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "DAD"); + state->u.f1.fld.fs_hcchar6.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "ODDFRM"); + state->u.f1.fld.fs_hcchar6.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "CHDIS"); + state->u.f1.fld.fs_hcchar6.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar6, "CHENA"); + + // FS_HCCHAR7 bitfields. + state->u.f1.fld.fs_hcchar7.mpsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "MPSIZ"); + state->u.f1.fld.fs_hcchar7.epnum = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "EPNUM"); + state->u.f1.fld.fs_hcchar7.epdir = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "EPDIR"); + state->u.f1.fld.fs_hcchar7.lsdev = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "LSDEV"); + state->u.f1.fld.fs_hcchar7.eptyp = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "EPTYP"); + state->u.f1.fld.fs_hcchar7.mcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "MCNT"); + state->u.f1.fld.fs_hcchar7.dad = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "DAD"); + state->u.f1.fld.fs_hcchar7.oddfrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "ODDFRM"); + state->u.f1.fld.fs_hcchar7.chdis = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "CHDIS"); + state->u.f1.fld.fs_hcchar7.chena = cm_object_get_child_by_name(state->u.f1.reg.fs_hcchar7, "CHENA"); + + // FS_HCINT0 bitfields. + state->u.f1.fld.fs_hcint0.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "XFRC"); + state->u.f1.fld.fs_hcint0.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "CHH"); + state->u.f1.fld.fs_hcint0.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "STALL"); + state->u.f1.fld.fs_hcint0.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "NAK"); + state->u.f1.fld.fs_hcint0.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "ACK"); + state->u.f1.fld.fs_hcint0.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "TXERR"); + state->u.f1.fld.fs_hcint0.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "BBERR"); + state->u.f1.fld.fs_hcint0.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "FRMOR"); + state->u.f1.fld.fs_hcint0.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint0, "DTERR"); + + // FS_HCINT1 bitfields. + state->u.f1.fld.fs_hcint1.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "XFRC"); + state->u.f1.fld.fs_hcint1.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "CHH"); + state->u.f1.fld.fs_hcint1.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "STALL"); + state->u.f1.fld.fs_hcint1.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "NAK"); + state->u.f1.fld.fs_hcint1.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "ACK"); + state->u.f1.fld.fs_hcint1.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "TXERR"); + state->u.f1.fld.fs_hcint1.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "BBERR"); + state->u.f1.fld.fs_hcint1.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "FRMOR"); + state->u.f1.fld.fs_hcint1.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint1, "DTERR"); + + // FS_HCINT2 bitfields. + state->u.f1.fld.fs_hcint2.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "XFRC"); + state->u.f1.fld.fs_hcint2.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "CHH"); + state->u.f1.fld.fs_hcint2.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "STALL"); + state->u.f1.fld.fs_hcint2.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "NAK"); + state->u.f1.fld.fs_hcint2.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "ACK"); + state->u.f1.fld.fs_hcint2.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "TXERR"); + state->u.f1.fld.fs_hcint2.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "BBERR"); + state->u.f1.fld.fs_hcint2.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "FRMOR"); + state->u.f1.fld.fs_hcint2.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint2, "DTERR"); + + // FS_HCINT3 bitfields. + state->u.f1.fld.fs_hcint3.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "XFRC"); + state->u.f1.fld.fs_hcint3.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "CHH"); + state->u.f1.fld.fs_hcint3.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "STALL"); + state->u.f1.fld.fs_hcint3.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "NAK"); + state->u.f1.fld.fs_hcint3.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "ACK"); + state->u.f1.fld.fs_hcint3.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "TXERR"); + state->u.f1.fld.fs_hcint3.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "BBERR"); + state->u.f1.fld.fs_hcint3.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "FRMOR"); + state->u.f1.fld.fs_hcint3.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint3, "DTERR"); + + // FS_HCINT4 bitfields. + state->u.f1.fld.fs_hcint4.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "XFRC"); + state->u.f1.fld.fs_hcint4.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "CHH"); + state->u.f1.fld.fs_hcint4.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "STALL"); + state->u.f1.fld.fs_hcint4.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "NAK"); + state->u.f1.fld.fs_hcint4.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "ACK"); + state->u.f1.fld.fs_hcint4.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "TXERR"); + state->u.f1.fld.fs_hcint4.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "BBERR"); + state->u.f1.fld.fs_hcint4.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "FRMOR"); + state->u.f1.fld.fs_hcint4.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint4, "DTERR"); + + // FS_HCINT5 bitfields. + state->u.f1.fld.fs_hcint5.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "XFRC"); + state->u.f1.fld.fs_hcint5.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "CHH"); + state->u.f1.fld.fs_hcint5.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "STALL"); + state->u.f1.fld.fs_hcint5.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "NAK"); + state->u.f1.fld.fs_hcint5.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "ACK"); + state->u.f1.fld.fs_hcint5.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "TXERR"); + state->u.f1.fld.fs_hcint5.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "BBERR"); + state->u.f1.fld.fs_hcint5.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "FRMOR"); + state->u.f1.fld.fs_hcint5.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint5, "DTERR"); + + // FS_HCINT6 bitfields. + state->u.f1.fld.fs_hcint6.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "XFRC"); + state->u.f1.fld.fs_hcint6.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "CHH"); + state->u.f1.fld.fs_hcint6.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "STALL"); + state->u.f1.fld.fs_hcint6.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "NAK"); + state->u.f1.fld.fs_hcint6.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "ACK"); + state->u.f1.fld.fs_hcint6.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "TXERR"); + state->u.f1.fld.fs_hcint6.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "BBERR"); + state->u.f1.fld.fs_hcint6.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "FRMOR"); + state->u.f1.fld.fs_hcint6.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint6, "DTERR"); + + // FS_HCINT7 bitfields. + state->u.f1.fld.fs_hcint7.xfrc = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "XFRC"); + state->u.f1.fld.fs_hcint7.chh = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "CHH"); + state->u.f1.fld.fs_hcint7.stall = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "STALL"); + state->u.f1.fld.fs_hcint7.nak = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "NAK"); + state->u.f1.fld.fs_hcint7.ack = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "ACK"); + state->u.f1.fld.fs_hcint7.txerr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "TXERR"); + state->u.f1.fld.fs_hcint7.bberr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "BBERR"); + state->u.f1.fld.fs_hcint7.frmor = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "FRMOR"); + state->u.f1.fld.fs_hcint7.dterr = cm_object_get_child_by_name(state->u.f1.reg.fs_hcint7, "DTERR"); + + // FS_HCINTMSK0 bitfields. + state->u.f1.fld.fs_hcintmsk0.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "XFRCM"); + state->u.f1.fld.fs_hcintmsk0.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "CHHM"); + state->u.f1.fld.fs_hcintmsk0.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "STALLM"); + state->u.f1.fld.fs_hcintmsk0.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "NAKM"); + state->u.f1.fld.fs_hcintmsk0.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "ACKM"); + state->u.f1.fld.fs_hcintmsk0.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "NYET"); + state->u.f1.fld.fs_hcintmsk0.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "TXERRM"); + state->u.f1.fld.fs_hcintmsk0.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "BBERRM"); + state->u.f1.fld.fs_hcintmsk0.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "FRMORM"); + state->u.f1.fld.fs_hcintmsk0.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk0, "DTERRM"); + + // FS_HCINTMSK1 bitfields. + state->u.f1.fld.fs_hcintmsk1.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "XFRCM"); + state->u.f1.fld.fs_hcintmsk1.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "CHHM"); + state->u.f1.fld.fs_hcintmsk1.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "STALLM"); + state->u.f1.fld.fs_hcintmsk1.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "NAKM"); + state->u.f1.fld.fs_hcintmsk1.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "ACKM"); + state->u.f1.fld.fs_hcintmsk1.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "NYET"); + state->u.f1.fld.fs_hcintmsk1.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "TXERRM"); + state->u.f1.fld.fs_hcintmsk1.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "BBERRM"); + state->u.f1.fld.fs_hcintmsk1.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "FRMORM"); + state->u.f1.fld.fs_hcintmsk1.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk1, "DTERRM"); + + // FS_HCINTMSK2 bitfields. + state->u.f1.fld.fs_hcintmsk2.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "XFRCM"); + state->u.f1.fld.fs_hcintmsk2.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "CHHM"); + state->u.f1.fld.fs_hcintmsk2.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "STALLM"); + state->u.f1.fld.fs_hcintmsk2.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "NAKM"); + state->u.f1.fld.fs_hcintmsk2.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "ACKM"); + state->u.f1.fld.fs_hcintmsk2.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "NYET"); + state->u.f1.fld.fs_hcintmsk2.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "TXERRM"); + state->u.f1.fld.fs_hcintmsk2.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "BBERRM"); + state->u.f1.fld.fs_hcintmsk2.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "FRMORM"); + state->u.f1.fld.fs_hcintmsk2.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk2, "DTERRM"); + + // FS_HCINTMSK3 bitfields. + state->u.f1.fld.fs_hcintmsk3.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "XFRCM"); + state->u.f1.fld.fs_hcintmsk3.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "CHHM"); + state->u.f1.fld.fs_hcintmsk3.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "STALLM"); + state->u.f1.fld.fs_hcintmsk3.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "NAKM"); + state->u.f1.fld.fs_hcintmsk3.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "ACKM"); + state->u.f1.fld.fs_hcintmsk3.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "NYET"); + state->u.f1.fld.fs_hcintmsk3.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "TXERRM"); + state->u.f1.fld.fs_hcintmsk3.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "BBERRM"); + state->u.f1.fld.fs_hcintmsk3.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "FRMORM"); + state->u.f1.fld.fs_hcintmsk3.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk3, "DTERRM"); + + // FS_HCINTMSK4 bitfields. + state->u.f1.fld.fs_hcintmsk4.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "XFRCM"); + state->u.f1.fld.fs_hcintmsk4.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "CHHM"); + state->u.f1.fld.fs_hcintmsk4.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "STALLM"); + state->u.f1.fld.fs_hcintmsk4.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "NAKM"); + state->u.f1.fld.fs_hcintmsk4.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "ACKM"); + state->u.f1.fld.fs_hcintmsk4.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "NYET"); + state->u.f1.fld.fs_hcintmsk4.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "TXERRM"); + state->u.f1.fld.fs_hcintmsk4.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "BBERRM"); + state->u.f1.fld.fs_hcintmsk4.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "FRMORM"); + state->u.f1.fld.fs_hcintmsk4.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk4, "DTERRM"); + + // FS_HCINTMSK5 bitfields. + state->u.f1.fld.fs_hcintmsk5.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "XFRCM"); + state->u.f1.fld.fs_hcintmsk5.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "CHHM"); + state->u.f1.fld.fs_hcintmsk5.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "STALLM"); + state->u.f1.fld.fs_hcintmsk5.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "NAKM"); + state->u.f1.fld.fs_hcintmsk5.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "ACKM"); + state->u.f1.fld.fs_hcintmsk5.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "NYET"); + state->u.f1.fld.fs_hcintmsk5.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "TXERRM"); + state->u.f1.fld.fs_hcintmsk5.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "BBERRM"); + state->u.f1.fld.fs_hcintmsk5.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "FRMORM"); + state->u.f1.fld.fs_hcintmsk5.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk5, "DTERRM"); + + // FS_HCINTMSK6 bitfields. + state->u.f1.fld.fs_hcintmsk6.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "XFRCM"); + state->u.f1.fld.fs_hcintmsk6.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "CHHM"); + state->u.f1.fld.fs_hcintmsk6.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "STALLM"); + state->u.f1.fld.fs_hcintmsk6.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "NAKM"); + state->u.f1.fld.fs_hcintmsk6.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "ACKM"); + state->u.f1.fld.fs_hcintmsk6.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "NYET"); + state->u.f1.fld.fs_hcintmsk6.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "TXERRM"); + state->u.f1.fld.fs_hcintmsk6.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "BBERRM"); + state->u.f1.fld.fs_hcintmsk6.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "FRMORM"); + state->u.f1.fld.fs_hcintmsk6.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk6, "DTERRM"); + + // FS_HCINTMSK7 bitfields. + state->u.f1.fld.fs_hcintmsk7.xfrcm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "XFRCM"); + state->u.f1.fld.fs_hcintmsk7.chhm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "CHHM"); + state->u.f1.fld.fs_hcintmsk7.stallm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "STALLM"); + state->u.f1.fld.fs_hcintmsk7.nakm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "NAKM"); + state->u.f1.fld.fs_hcintmsk7.ackm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "ACKM"); + state->u.f1.fld.fs_hcintmsk7.nyet = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "NYET"); + state->u.f1.fld.fs_hcintmsk7.txerrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "TXERRM"); + state->u.f1.fld.fs_hcintmsk7.bberrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "BBERRM"); + state->u.f1.fld.fs_hcintmsk7.frmorm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "FRMORM"); + state->u.f1.fld.fs_hcintmsk7.dterrm = cm_object_get_child_by_name(state->u.f1.reg.fs_hcintmsk7, "DTERRM"); + + // FS_HCTSIZ0 bitfields. + state->u.f1.fld.fs_hctsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz0, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz0.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz0, "PKTCNT"); + state->u.f1.fld.fs_hctsiz0.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz0, "DPID"); + + // FS_HCTSIZ1 bitfields. + state->u.f1.fld.fs_hctsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz1, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz1.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz1, "PKTCNT"); + state->u.f1.fld.fs_hctsiz1.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz1, "DPID"); + + // FS_HCTSIZ2 bitfields. + state->u.f1.fld.fs_hctsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz2, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz2.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz2, "PKTCNT"); + state->u.f1.fld.fs_hctsiz2.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz2, "DPID"); + + // FS_HCTSIZ3 bitfields. + state->u.f1.fld.fs_hctsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz3, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz3.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz3, "PKTCNT"); + state->u.f1.fld.fs_hctsiz3.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz3, "DPID"); + + // FS_HCTSIZ4 bitfields. + state->u.f1.fld.fs_hctsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz4, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz4.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz4, "PKTCNT"); + state->u.f1.fld.fs_hctsiz4.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz4, "DPID"); + + // FS_HCTSIZ5 bitfields. + state->u.f1.fld.fs_hctsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz5, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz5.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz5, "PKTCNT"); + state->u.f1.fld.fs_hctsiz5.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz5, "DPID"); + + // FS_HCTSIZ6 bitfields. + state->u.f1.fld.fs_hctsiz6.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz6, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz6.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz6, "PKTCNT"); + state->u.f1.fld.fs_hctsiz6.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz6, "DPID"); + + // FS_HCTSIZ7 bitfields. + state->u.f1.fld.fs_hctsiz7.xfrsiz = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz7, "XFRSIZ"); + state->u.f1.fld.fs_hctsiz7.pktcnt = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz7, "PKTCNT"); + state->u.f1.fld.fs_hctsiz7.dpid = cm_object_get_child_by_name(state->u.f1.reg.fs_hctsiz7, "DPID"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usb_otg_host_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usb_otg_host_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usb_otg_host_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usb_otg_host_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usb_otg_host_is_enabled(Object *obj) +{ + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usb_otg_host_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usb_otg_host_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USB_OTG_HOST)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USB_OTG_HOSTState *state = STM32_USB_OTG_HOST_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USB_OTG_HOST"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_usb_otg_host_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_host_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_usb_otg_host_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_host_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_usb_otg_host_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USB_OTG_HOSTEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usb_otg_host_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USB_OTG_HOST); +} + +static void stm32_usb_otg_host_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usb_otg_host_reset_callback; + dc->realize = stm32_usb_otg_host_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usb_otg_host_is_enabled; +} + +static const TypeInfo stm32_usb_otg_host_type_info = { + .name = TYPE_STM32_USB_OTG_HOST, + .parent = TYPE_STM32_USB_OTG_HOST_PARENT, + .instance_init = stm32_usb_otg_host_instance_init_callback, + .instance_size = sizeof(STM32USB_OTG_HOSTState), + .class_init = stm32_usb_otg_host_class_init_callback, + .class_size = sizeof(STM32USB_OTG_HOSTClass) }; + +static void stm32_usb_otg_host_register_types(void) +{ + type_register_static(&stm32_usb_otg_host_type_info); +} + +type_init(stm32_usb_otg_host_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_host.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_host.h new file mode 100644 index 0000000000..67f34b7cba --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_host.h @@ -0,0 +1,573 @@ +/* + * STM32 - USB_OTG_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USB_OTG_HOST_H_ +#define STM32_USB_OTG_HOST_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USB_OTG_HOST DEVICE_PATH_STM32 "USB_OTG_HOST" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USB_OTG_HOST TYPE_STM32_PREFIX "usb_otg_host" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USB_OTG_HOST_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USB_OTG_HOSTParentClass; +typedef PeripheralState STM32USB_OTG_HOSTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USB_OTG_HOST_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USB_OTG_HOSTClass, (obj), TYPE_STM32_USB_OTG_HOST) +#define STM32_USB_OTG_HOST_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USB_OTG_HOSTClass, (klass), TYPE_STM32_USB_OTG_HOST) + +typedef struct { + // private: + STM32USB_OTG_HOSTParentClass parent_class; + // public: + + // None, so far. +} STM32USB_OTG_HOSTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USB_OTG_HOST_STATE(obj) \ + OBJECT_CHECK(STM32USB_OTG_HOSTState, (obj), TYPE_STM32_USB_OTG_HOST) + +typedef struct { + // private: + STM32USB_OTG_HOSTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 USB_OTG_HOST (USB on the go full speed) registers. + struct { + Object *fs_hcfg; // 0x0 (OTG_FS host configuration register (OTG_FS_HCFG)) + Object *hfir; // 0x4 (OTG_FS Host frame interval register) + Object *fs_hfnum; // 0x8 (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) + Object *fs_hptxsts; // 0x10 (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) + Object *haint; // 0x14 (OTG_FS Host all channels interrupt register) + Object *haintmsk; // 0x18 (OTG_FS host all channels interrupt mask register) + Object *fs_hprt; // 0x40 (OTG_FS host port control and status register (OTG_FS_HPRT)) + Object *fs_hcchar0; // 0x100 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) + Object *fs_hcchar1; // 0x120 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) + Object *fs_hcchar2; // 0x140 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) + Object *fs_hcchar3; // 0x160 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) + Object *fs_hcchar4; // 0x180 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) + Object *fs_hcchar5; // 0x1A0 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) + Object *fs_hcchar6; // 0x1C0 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) + Object *fs_hcchar7; // 0x1E0 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) + Object *fs_hcint0; // 0x108 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) + Object *fs_hcint1; // 0x128 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) + Object *fs_hcint2; // 0x148 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) + Object *fs_hcint3; // 0x168 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) + Object *fs_hcint4; // 0x188 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) + Object *fs_hcint5; // 0x1A8 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) + Object *fs_hcint6; // 0x1C8 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) + Object *fs_hcint7; // 0x1E8 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) + Object *fs_hcintmsk0; // 0x10C (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) + Object *fs_hcintmsk1; // 0x12C (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) + Object *fs_hcintmsk2; // 0x14C (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) + Object *fs_hcintmsk3; // 0x16C (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) + Object *fs_hcintmsk4; // 0x18C (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) + Object *fs_hcintmsk5; // 0x1AC (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) + Object *fs_hcintmsk6; // 0x1CC (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) + Object *fs_hcintmsk7; // 0x1EC (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) + Object *fs_hctsiz0; // 0x110 (OTG_FS host channel-0 transfer size register) + Object *fs_hctsiz1; // 0x130 (OTG_FS host channel-1 transfer size register) + Object *fs_hctsiz2; // 0x150 (OTG_FS host channel-2 transfer size register) + Object *fs_hctsiz3; // 0x170 (OTG_FS host channel-3 transfer size register) + Object *fs_hctsiz4; // 0x190 (OTG_FS host channel-x transfer size register) + Object *fs_hctsiz5; // 0x1B0 (OTG_FS host channel-5 transfer size register) + Object *fs_hctsiz6; // 0x1D0 (OTG_FS host channel-6 transfer size register) + Object *fs_hctsiz7; // 0x1F0 (OTG_FS host channel-7 transfer size register) + } reg; + + struct { + + // FS_HCFG (OTG_FS host configuration register (OTG_FS_HCFG)) bitfields. + struct { + Object *fslspcs; // [0:1] FS/LS PHY clock select + Object *fslss; // [2:2] FS- and LS-only support + } fs_hcfg; + + // HFIR (OTG_FS Host frame interval register) bitfields. + struct { + Object *frivl; // [0:15] Frame interval + } hfir; + + // FS_HFNUM (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) bitfields. + struct { + Object *frnum; // [0:15] Frame number + Object *ftrem; // [16:31] Frame time remaining + } fs_hfnum; + + // FS_HPTXSTS (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) bitfields. + struct { + Object *ptxfsavl; // [0:15] Periodic transmit data FIFO space available + Object *ptxqsav; // [16:23] Periodic transmit request queue space available + Object *ptxqtop; // [24:31] Top of the periodic transmit request queue + } fs_hptxsts; + + // HAINT (OTG_FS Host all channels interrupt register) bitfields. + struct { + Object *haint; // [0:15] Channel interrupts + } haint; + + // HAINTMSK (OTG_FS host all channels interrupt mask register) bitfields. + struct { + Object *haintm; // [0:15] Channel interrupt mask + } haintmsk; + + // FS_HPRT (OTG_FS host port control and status register (OTG_FS_HPRT)) bitfields. + struct { + Object *pcsts; // [0:0] Port connect status + Object *pcdet; // [1:1] Port connect detected + Object *pena; // [2:2] Port enable + Object *penchng; // [3:3] Port enable/disable change + Object *poca; // [4:4] Port overcurrent active + Object *pocchng; // [5:5] Port overcurrent change + Object *pres; // [6:6] Port resume + Object *psusp; // [7:7] Port suspend + Object *prst; // [8:8] Port reset + Object *plsts; // [10:11] Port line status + Object *ppwr; // [12:12] Port power + Object *ptctl; // [13:16] Port test control + Object *pspd; // [17:18] Port speed + } fs_hprt; + + // FS_HCCHAR0 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar0; + + // FS_HCCHAR1 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar1; + + // FS_HCCHAR2 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar2; + + // FS_HCCHAR3 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar3; + + // FS_HCCHAR4 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar4; + + // FS_HCCHAR5 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar5; + + // FS_HCCHAR6 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar6; + + // FS_HCCHAR7 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar7; + + // FS_HCINT0 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint0; + + // FS_HCINT1 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint1; + + // FS_HCINT2 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint2; + + // FS_HCINT3 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint3; + + // FS_HCINT4 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint4; + + // FS_HCINT5 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint5; + + // FS_HCINT6 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint6; + + // FS_HCINT7 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint7; + + // FS_HCINTMSK0 (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk0; + + // FS_HCINTMSK1 (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk1; + + // FS_HCINTMSK2 (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk2; + + // FS_HCINTMSK3 (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk3; + + // FS_HCINTMSK4 (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk4; + + // FS_HCINTMSK5 (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk5; + + // FS_HCINTMSK6 (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk6; + + // FS_HCINTMSK7 (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk7; + + // FS_HCTSIZ0 (OTG_FS host channel-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz0; + + // FS_HCTSIZ1 (OTG_FS host channel-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz1; + + // FS_HCTSIZ2 (OTG_FS host channel-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz2; + + // FS_HCTSIZ3 (OTG_FS host channel-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz3; + + // FS_HCTSIZ4 (OTG_FS host channel-x transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz4; + + // FS_HCTSIZ5 (OTG_FS host channel-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz5; + + // FS_HCTSIZ6 (OTG_FS host channel-6 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz6; + + // FS_HCTSIZ7 (OTG_FS host channel-7 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz7; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USB_OTG_HOSTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USB_OTG_HOST_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_pwrclk.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_pwrclk.c new file mode 100644 index 0000000000..77e8494ade --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_pwrclk.c @@ -0,0 +1,240 @@ +/* + * STM32 - USB_OTG_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_usb_otg_pwrclk_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.fs_pcgcctl = cm_object_get_child_by_name(obj, "FS_PCGCCTL"); + + + // FS_PCGCCTL bitfields. + state->u.f1.fld.fs_pcgcctl.stppclk = cm_object_get_child_by_name(state->u.f1.reg.fs_pcgcctl, "STPPCLK"); + state->u.f1.fld.fs_pcgcctl.gatehclk = cm_object_get_child_by_name(state->u.f1.reg.fs_pcgcctl, "GATEHCLK"); + state->u.f1.fld.fs_pcgcctl.physusp = cm_object_get_child_by_name(state->u.f1.reg.fs_pcgcctl, "PHYSUSP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usb_otg_pwrclk_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usb_otg_pwrclk_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usb_otg_pwrclk_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usb_otg_pwrclk_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usb_otg_pwrclk_is_enabled(Object *obj) +{ + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usb_otg_pwrclk_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usb_otg_pwrclk_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USB_OTG_PWRCLK)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USB_OTG_PWRCLKState *state = STM32_USB_OTG_PWRCLK_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USB_OTG_PWRCLK"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_usb_otg_pwrclk_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_pwrclk_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_usb_otg_pwrclk_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_usb_otg_pwrclk_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_usb_otg_pwrclk_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USB_OTG_PWRCLKEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usb_otg_pwrclk_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USB_OTG_PWRCLK); +} + +static void stm32_usb_otg_pwrclk_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usb_otg_pwrclk_reset_callback; + dc->realize = stm32_usb_otg_pwrclk_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usb_otg_pwrclk_is_enabled; +} + +static const TypeInfo stm32_usb_otg_pwrclk_type_info = { + .name = TYPE_STM32_USB_OTG_PWRCLK, + .parent = TYPE_STM32_USB_OTG_PWRCLK_PARENT, + .instance_init = stm32_usb_otg_pwrclk_instance_init_callback, + .instance_size = sizeof(STM32USB_OTG_PWRCLKState), + .class_init = stm32_usb_otg_pwrclk_class_init_callback, + .class_size = sizeof(STM32USB_OTG_PWRCLKClass) }; + +static void stm32_usb_otg_pwrclk_register_types(void) +{ + type_register_static(&stm32_usb_otg_pwrclk_type_info); +} + +type_init(stm32_usb_otg_pwrclk_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_pwrclk.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_pwrclk.h new file mode 100644 index 0000000000..64943b1ef4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/usb_otg_pwrclk.h @@ -0,0 +1,107 @@ +/* + * STM32 - USB_OTG_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USB_OTG_PWRCLK_H_ +#define STM32_USB_OTG_PWRCLK_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USB_OTG_PWRCLK DEVICE_PATH_STM32 "USB_OTG_PWRCLK" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USB_OTG_PWRCLK TYPE_STM32_PREFIX "usb_otg_pwrclk" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USB_OTG_PWRCLK_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USB_OTG_PWRCLKParentClass; +typedef PeripheralState STM32USB_OTG_PWRCLKParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USB_OTG_PWRCLK_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USB_OTG_PWRCLKClass, (obj), TYPE_STM32_USB_OTG_PWRCLK) +#define STM32_USB_OTG_PWRCLK_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USB_OTG_PWRCLKClass, (klass), TYPE_STM32_USB_OTG_PWRCLK) + +typedef struct { + // private: + STM32USB_OTG_PWRCLKParentClass parent_class; + // public: + + // None, so far. +} STM32USB_OTG_PWRCLKClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USB_OTG_PWRCLK_STATE(obj) \ + OBJECT_CHECK(STM32USB_OTG_PWRCLKState, (obj), TYPE_STM32_USB_OTG_PWRCLK) + +typedef struct { + // private: + STM32USB_OTG_PWRCLKParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 USB_OTG_PWRCLK (USB on the go full speed) registers. + struct { + Object *fs_pcgcctl; // 0x0 (OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)) + } reg; + + struct { + + // FS_PCGCCTL (OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)) bitfields. + struct { + Object *stppclk; // [0:0] Stop PHY clock + Object *gatehclk; // [1:1] Gate HCLK + Object *physusp; // [4:4] PHY Suspended + } fs_pcgcctl; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USB_OTG_PWRCLKState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USB_OTG_PWRCLK_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/wwdg.c b/gnu-mcu-eclipse/devices/support/STM32F107xx/wwdg.c new file mode 100644 index 0000000000..1a93b4f11b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/wwdg.c @@ -0,0 +1,249 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f107xx_wwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f1.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f1.reg.cfr = cm_object_get_child_by_name(obj, "CFR"); + state->u.f1.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f1.fld.cr.t = cm_object_get_child_by_name(state->u.f1.reg.cr, "T"); + state->u.f1.fld.cr.wdga = cm_object_get_child_by_name(state->u.f1.reg.cr, "WDGA"); + + // CFR bitfields. + state->u.f1.fld.cfr.w = cm_object_get_child_by_name(state->u.f1.reg.cfr, "W"); + state->u.f1.fld.cfr.wdgtb = cm_object_get_child_by_name(state->u.f1.reg.cfr, "WDGTB"); + state->u.f1.fld.cfr.ewi = cm_object_get_child_by_name(state->u.f1.reg.cfr, "EWI"); + + // SR bitfields. + state->u.f1.fld.sr.ewi = cm_object_get_child_by_name(state->u.f1.reg.sr, "EWI"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_wwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_wwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_wwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_wwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_wwdg_is_enabled(Object *obj) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_wwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_wwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_WWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32WWDGState *state = STM32_WWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "WWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F1: + + if (capabilities->f1.is_107xx ) { + + stm32f107xx_wwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f1.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_wwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f1.reg.xxx, &stm32_wwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f1.reg.xxx, &stm32_wwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f1.reg.xxx, &stm32_wwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/WWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_wwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_WWDG); +} + +static void stm32_wwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_wwdg_reset_callback; + dc->realize = stm32_wwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_wwdg_is_enabled; +} + +static const TypeInfo stm32_wwdg_type_info = { + .name = TYPE_STM32_WWDG, + .parent = TYPE_STM32_WWDG_PARENT, + .instance_init = stm32_wwdg_instance_init_callback, + .instance_size = sizeof(STM32WWDGState), + .class_init = stm32_wwdg_class_init_callback, + .class_size = sizeof(STM32WWDGClass) }; + +static void stm32_wwdg_register_types(void) +{ + type_register_static(&stm32_wwdg_type_info); +} + +type_init(stm32_wwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F107xx/wwdg.h b/gnu-mcu-eclipse/devices/support/STM32F107xx/wwdg.h new file mode 100644 index 0000000000..7b0bc72dab --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F107xx/wwdg.h @@ -0,0 +1,120 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_WWDG_H_ +#define STM32_WWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_WWDG DEVICE_PATH_STM32 "WWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_WWDG TYPE_STM32_PREFIX "wwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_WWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32WWDGParentClass; +typedef PeripheralState STM32WWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_WWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32WWDGClass, (obj), TYPE_STM32_WWDG) +#define STM32_WWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32WWDGClass, (klass), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentClass parent_class; + // public: + + // None, so far. +} STM32WWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_WWDG_STATE(obj) \ + OBJECT_CHECK(STM32WWDGState, (obj), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F1 WWDG (Window watchdog) registers. + struct { + Object *cr; // 0x0 (Control register (WWDG_CR)) + Object *cfr; // 0x4 (Configuration register (WWDG_CFR)) + Object *sr; // 0x8 (Status register (WWDG_SR)) + } reg; + + struct { + + // CR (Control register (WWDG_CR)) bitfields. + struct { + Object *t; // [0:6] 7-bit counter (MSB to LSB) + Object *wdga; // [7:7] Activation bit + } cr; + + // CFR (Configuration register (WWDG_CFR)) bitfields. + struct { + Object *w; // [0:6] 7-bit window value + Object *wdgtb; // [7:8] Timer Base + Object *ewi; // [9:9] Early Wakeup Interrupt + } cfr; + + // SR (Status register (WWDG_SR)) bitfields. + struct { + Object *ewi; // [0:0] Early Wakeup Interrupt + } sr; + } fld; + } f1; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32WWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_WWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x-patch.json b/gnu-mcu-eclipse/devices/support/STM32F40x-patch.json new file mode 100644 index 0000000000..0344cfe7bb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x-patch.json @@ -0,0 +1,139 @@ +{ + "comment": "Patch for QEMU use.", + "device": { + "name": "STM32F40x", + "cpu": { + "name": "CM4", + "revision": "r0p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "true", + "nvicPrioBits": "4", + "deviceNumInterrupts": "82", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "access": "read-write", + "qemuAlignment": "any", + "peripherals": [ + { + "name": "GPIOA", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOG", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOH", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOI", + "qemuGroupName": "GPIO" + }, + { + "name": "USART1", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART2", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART3", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART6", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART4", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART5", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "ADC1", + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "qemuGroupName": "ADC" + }, + { + "name": "I2C1", + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "qemuGroupName": "I2C" + }, + { + "name": "I2C3", + "qemuGroupName": "I2C" + }, + { + "name": "CAN1", + "qemuGroupName": "CAN" + }, + { + "name": "CAN2", + "qemuGroupName": "CAN" + }, + { + "name": "DMA1", + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "qemuGroupName": "DMA" + }, + { + "name": "SPI1", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "qemuGroupName": "SPI" + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x-xsvd.json b/gnu-mcu-eclipse/devices/support/STM32F40x-xsvd.json new file mode 100644 index 0000000000..cdacf20e00 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x-xsvd.json @@ -0,0 +1,52083 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F40x.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.2", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F40x.svd", + "--output", + "STM32F40x-xsvd.json" + ], + "date": "2016-12-14T22:50:52.397Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F40x", + "version": "1.5", + "description": "STM32F40x", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "RNG", + "description": "Random number generator", + "groupName": "RNG", + "baseAddress": "0x50060800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FPU", + "description": "FPU interrupt", + "value": "81" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IE", + "description": "Interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RNGEN", + "description": "Random number generator enable", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEIS", + "description": "Seed error interrupt status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CEIS", + "description": "Clock error interrupt status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SECS", + "description": "Seed error current status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CECS", + "description": "Clock error current status", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DRDY", + "description": "Data ready", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RNDATA", + "description": "Random data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DCMI", + "description": "Digital camera interface", + "groupName": "DCMI", + "baseAddress": "0x50050000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DCMI", + "description": "DCMI global interrupt", + "value": "78" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ENABLE", + "description": "DCMI enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "EDM", + "description": "Extended data mode", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "FCRC", + "description": "Frame capture rate control", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "VSPOL", + "description": "Vertical synchronization polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "HSPOL", + "description": "Horizontal synchronization polarity", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PCKPOL", + "description": "Pixel clock polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ESS", + "description": "Embedded synchronization select", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JPEG", + "description": "JPEG format", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CROP", + "description": "Crop feature", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CM", + "description": "Capture mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CAPTURE", + "description": "Capture enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FNE", + "description": "FIFO not empty", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC", + "description": "VSYNC", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HSYNC", + "description": "HSYNC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "RIS", + "displayName": "RIS", + "description": "Raw interrupt status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_RIS", + "description": "Line raw interrupt status", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_RIS", + "description": "VSYNC raw interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_RIS", + "description": "Synchronization error raw interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_RIS", + "description": "Overrun raw interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_RIS", + "description": "Capture complete raw interrupt status", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_IE", + "description": "Line interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_IE", + "description": "VSYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_IE", + "description": "Synchronization error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_IE", + "description": "Overrun interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_IE", + "description": "Capture complete interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "MIS", + "displayName": "MIS", + "description": "Masked interrupt status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_MIS", + "description": "Line masked interrupt status", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_MIS", + "description": "VSYNC masked interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_MIS", + "description": "Synchronization error masked interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_MIS", + "description": "Overrun masked interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_MIS", + "description": "Capture complete masked interrupt status", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_ISC", + "description": "Line interrupt status clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_ISC", + "description": "Vertical synch interrupt status clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_ISC", + "description": "Synchronization error interrupt status clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_ISC", + "description": "Overrun interrupt status clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_ISC", + "description": "Capture complete interrupt status clear", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ESCR", + "displayName": "ESCR", + "description": "Embedded synchronization code register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FEC", + "description": "Frame end delimiter code", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "LEC", + "description": "Line end delimiter code", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "LSC", + "description": "Line start delimiter code", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "FSC", + "description": "Frame start delimiter code", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ESUR", + "displayName": "ESUR", + "description": "Embedded synchronization unmask register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FEU", + "description": "Frame end delimiter unmask", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "LEU", + "description": "Line end delimiter unmask", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "LSU", + "description": "Line start delimiter unmask", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "FSU", + "description": "Frame start delimiter unmask", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CWSTRT", + "displayName": "CWSTRT", + "description": "Crop window start", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "VST", + "description": "Vertical start line count", + "bitOffset": "16", + "bitWidth": "13" + }, + { + "name": "HOFFCNT", + "description": "Horizontal offset count", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "CWSIZE", + "displayName": "CWSIZE", + "description": "Crop window size", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "VLINE", + "description": "Vertical line count", + "bitOffset": "16", + "bitWidth": "14" + }, + { + "name": "CAPCNT", + "description": "Capture count", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "Byte3", + "description": "Data byte 3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "Byte2", + "description": "Data byte 2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "Byte1", + "description": "Data byte 1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "Byte0", + "description": "Data byte 0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "FSMC", + "description": "Flexible static memory controller", + "groupName": "FSMC", + "baseAddress": "0xA0000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FSMC", + "description": "FSMC global interrupt", + "value": "48" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "SRAM/NOR-Flash chip-select control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR1", + "displayName": "BTR1", + "description": "SRAM/NOR-Flash chip-select timing register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "SRAM/NOR-Flash chip-select control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR2", + "displayName": "BTR2", + "description": "SRAM/NOR-Flash chip-select timing register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR3", + "displayName": "BCR3", + "description": "SRAM/NOR-Flash chip-select control register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR3", + "displayName": "BTR3", + "description": "SRAM/NOR-Flash chip-select timing register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR4", + "displayName": "BCR4", + "description": "SRAM/NOR-Flash chip-select control register 4", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR4", + "displayName": "BTR4", + "description": "SRAM/NOR-Flash chip-select timing register 4", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "PCR2", + "displayName": "PCR2", + "description": "PC Card/NAND Flash control register 2", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "FIFO status and interrupt register 2", + "addressOffset": "0x64", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM2", + "displayName": "PMEM2", + "description": "Common memory space timing register 2", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT2", + "displayName": "PATT2", + "description": "Attribute memory space timing register 2", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR2", + "displayName": "ECCR2", + "description": "ECC result register 2", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR3", + "displayName": "PCR3", + "description": "PC Card/NAND Flash control register 3", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR3", + "displayName": "SR3", + "description": "FIFO status and interrupt register 3", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM3", + "displayName": "PMEM3", + "description": "Common memory space timing register 3", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT3", + "displayName": "PATT3", + "description": "Attribute memory space timing register 3", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR3", + "displayName": "ECCR3", + "description": "ECC result register 3", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR4", + "displayName": "PCR4", + "description": "PC Card/NAND Flash control register 4", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR4", + "displayName": "SR4", + "description": "FIFO status and interrupt register 4", + "addressOffset": "0xA4", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM4", + "displayName": "PMEM4", + "description": "Common memory space timing register 4", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT4", + "displayName": "PATT4", + "description": "Attribute memory space timing register 4", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PIO4", + "displayName": "PIO4", + "description": "I/O space timing register 4", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "IOHIZx", + "description": "IOHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "IOHOLDx", + "description": "IOHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IOWAITx", + "description": "IOWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IOSETx", + "description": "IOSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BWTR1", + "displayName": "BWTR1", + "description": "SRAM/NOR-Flash write timing registers 1", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR2", + "displayName": "BWTR2", + "description": "SRAM/NOR-Flash write timing registers 2", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR3", + "displayName": "BWTR3", + "description": "SRAM/NOR-Flash write timing registers 3", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR4", + "displayName": "BWTR4", + "description": "SRAM/NOR-Flash write timing registers 4", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DBGMCU_IDCODE", + "displayName": "DBGMCU_IDCODE", + "description": "IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x10006411", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DBGMCU_CR", + "displayName": "DBGMCU_CR", + "description": "Control Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "DBG_TIM8_STOP", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB1_FZ", + "displayName": "DBGMCU_APB1_FZ", + "description": "Debug MCU APB1 Freeze registe", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3 _STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DBG_TIM12_STOP", + "description": "DBG_TIM12_STOP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DBG_TIM13_STOP", + "description": "DBG_TIM13_STOP", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DBG_TIM14_STOP", + "description": "DBG_TIM14_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDEG_STOP", + "description": "DBG_IWDEG_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_J2C1_SMBUS_TIMEOUT", + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DBG_J2C2_SMBUS_TIMEOUT", + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBG_J2C3SMBUS_TIMEOUT", + "description": "DBG_J2C3SMBUS_TIMEOUT", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB2_FZ", + "displayName": "DBGMCU_APB2_FZ", + "description": "Debug MCU APB2 Freeze registe", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM1_STOP", + "description": "TIM1 counter stopped when core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "TIM8 counter stopped when core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM9_STOP", + "description": "TIM9 counter stopped when core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM10_STOP", + "description": "TIM10 counter stopped when core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM11_STOP", + "description": "TIM11 counter stopped when core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA2", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40026400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA2_Stream0", + "description": "DMA2 Stream0 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Stream1", + "description": "DMA2 Stream1 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Stream2", + "description": "DMA2 Stream2 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Stream3", + "description": "DMA2 Stream3 global interrupt", + "value": "59" + }, + { + "name": "DMA2_Stream4", + "description": "DMA2 Stream4 global interrupt", + "value": "60" + }, + { + "name": "DMA2_Stream5", + "description": "DMA2 Stream5 global interrupt", + "value": "68" + }, + { + "name": "DMA2_Stream6", + "description": "DMA2 Stream6 global interrupt", + "value": "69" + }, + { + "name": "DMA2_Stream7", + "description": "DMA2 Stream7 global interrupt", + "value": "70" + } + ], + "registers": [ + { + "name": "LISR", + "displayName": "LISR", + "description": "Low interrupt status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TCIF3", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMEIF3", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FEIF3", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMEIF2", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FEIF2", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMEIF1", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FEIF1", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCIF0", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF0", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TEIF0", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMEIF0", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FEIF0", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "HISR", + "displayName": "HISR", + "description": "High interrupt status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TCIF7", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMEIF7", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FEIF7", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMEIF6", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FEIF6", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMEIF5", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FEIF5", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMEIF4", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FEIF4", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LIFCR", + "displayName": "LIFCR", + "description": "Low interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTCIF3", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CDMEIF3", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CFEIF3", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CDMEIF2", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CFEIF2", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CDMEIF1", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CFEIF1", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTCIF0", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF0", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTEIF0", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CDMEIF0", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CFEIF0", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "HIFCR", + "displayName": "HIFCR", + "description": "High interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTCIF7", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CDMEIF7", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CFEIF7", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CDMEIF6", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CFEIF6", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CDMEIF5", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CFEIF5", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CDMEIF4", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CFEIF4", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S0CR", + "displayName": "S0CR", + "description": "Stream x configuration register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S0NDTR", + "displayName": "S0NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S0PAR", + "displayName": "S0PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M0AR", + "displayName": "S0M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M1AR", + "displayName": "S0M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0FCR", + "displayName": "S0FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S1CR", + "displayName": "S1CR", + "description": "Stream x configuration register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S1NDTR", + "displayName": "S1NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S1PAR", + "displayName": "S1PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M0AR", + "displayName": "S1M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M1AR", + "displayName": "S1M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1FCR", + "displayName": "S1FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x3C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S2CR", + "displayName": "S2CR", + "description": "Stream x configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S2NDTR", + "displayName": "S2NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S2PAR", + "displayName": "S2PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M0AR", + "displayName": "S2M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M1AR", + "displayName": "S2M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2FCR", + "displayName": "S2FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S3CR", + "displayName": "S3CR", + "description": "Stream x configuration register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S3NDTR", + "displayName": "S3NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S3PAR", + "displayName": "S3PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M0AR", + "displayName": "S3M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M1AR", + "displayName": "S3M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3FCR", + "displayName": "S3FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x6C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S4CR", + "displayName": "S4CR", + "description": "Stream x configuration register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S4NDTR", + "displayName": "S4NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S4PAR", + "displayName": "S4PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M0AR", + "displayName": "S4M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M1AR", + "displayName": "S4M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4FCR", + "displayName": "S4FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S5CR", + "displayName": "S5CR", + "description": "Stream x configuration register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S5NDTR", + "displayName": "S5NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S5PAR", + "displayName": "S5PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M0AR", + "displayName": "S5M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M1AR", + "displayName": "S5M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5FCR", + "displayName": "S5FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x9C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S6CR", + "displayName": "S6CR", + "description": "Stream x configuration register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S6NDTR", + "displayName": "S6NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S6PAR", + "displayName": "S6PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M0AR", + "displayName": "S6M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M1AR", + "displayName": "S6M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6FCR", + "displayName": "S6FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xB4", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S7CR", + "displayName": "S7CR", + "description": "Stream x configuration register", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S7NDTR", + "displayName": "S7NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xBC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S7PAR", + "displayName": "S7PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xC0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M0AR", + "displayName": "S7M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M1AR", + "displayName": "S7M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xC8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7FCR", + "displayName": "S7FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xCC", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "DMA1", + "derivedFrom": "DMA2", + "baseAddress": "0x40026000", + "interrupts": [ + { + "name": "DMA1_Stream0", + "description": "DMA1 Stream0 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Stream1", + "description": "DMA1 Stream1 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Stream2", + "description": "DMA1 Stream2 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Stream3", + "description": "DMA1 Stream3 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Stream4", + "description": "DMA1 Stream4 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Stream5", + "description": "DMA1 Stream5 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Stream6", + "description": "DMA1 Stream6 global interrupt", + "value": "17" + }, + { + "name": "DMA1_Stream7", + "description": "DMA1 Stream7 global interrupt", + "value": "47" + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40023800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "PLLI2SRDY", + "description": "PLLI2S clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SON", + "description": "PLLI2S enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "Main PLL (PLL) clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLON", + "description": "Main PLL (PLL) enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock security system enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSEBYP", + "description": "HSE clock bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "HSE clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "HSE clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal high-speed clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal high-speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal high-speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSION", + "description": "Internal high-speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PLLCFGR", + "displayName": "PLLCFGR", + "description": "PLL configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003010", + "fields": [ + { + "name": "PLLQ3", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PLLQ2", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PLLQ1", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "PLLQ0", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "PLLSRC", + "description": "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PLLP1", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PLLP0", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PLLN8", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PLLN7", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PLLN6", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PLLN5", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PLLN4", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PLLN3", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PLLN2", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLLN1", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PLLN0", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PLLM5", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PLLM4", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLLM3", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLLM2", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PLLM1", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PLLM0", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCO2", + "description": "Microcontroller clock output 2", + "bitOffset": "30", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "MCO2PRE", + "description": "MCO2 prescaler", + "bitOffset": "27", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO1PRE", + "description": "MCO1 prescaler", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "I2SSRC", + "description": "I2S clock selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO1", + "description": "Microcontroller clock output 1", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCPRE", + "description": "HSE division factor for RTC clock", + "bitOffset": "16", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB high-speed prescaler (APB2)", + "bitOffset": "13", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "10", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "SWS1", + "description": "System clock switch status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SWS0", + "description": "System clock switch status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SW1", + "description": "System clock switch", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SW0", + "description": "System clock switch", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYC", + "description": "PLLI2S ready interrupt clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "Main PLL(PLL) ready interrupt clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE ready interrupt clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI ready interrupt clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE ready interrupt clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSIRDYC", + "description": "LSI ready interrupt clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYIE", + "description": "PLLI2S ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "Main PLL (PLL) ready interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE ready interrupt enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI ready interrupt enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE ready interrupt enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYIE", + "description": "LSI ready interrupt enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSF", + "description": "Clock security system interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SRDYF", + "description": "PLLI2S ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "Main PLL (PLL) ready interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE ready interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI ready interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE ready interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYF", + "description": "LSI ready interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "AHB1RSTR", + "displayName": "AHB1RSTR", + "description": "AHB1 peripheral reset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGHSRST", + "description": "USB OTG HS module reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "ETHMACRST", + "description": "Ethernet MAC reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMA2RST", + "description": "DMA2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1RST", + "description": "DMA2 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CRCRST", + "description": "CRC reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOIRST", + "description": "IO port I reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOHRST", + "description": "IO port H reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOGRST", + "description": "IO port G reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOFRST", + "description": "IO port F reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOERST", + "description": "IO port E reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODRST", + "description": "IO port D reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCRST", + "description": "IO port C reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBRST", + "description": "IO port B reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOARST", + "description": "IO port A reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2RSTR", + "displayName": "AHB2RSTR", + "description": "AHB2 peripheral reset register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSRST", + "description": "USB OTG FS module reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RNGRST", + "description": "Random number generator module reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCMIRST", + "description": "Camera interface reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3RSTR", + "displayName": "AHB3RSTR", + "description": "AHB3 peripheral reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSMCRST", + "description": "Flexible static memory controller module reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACRST", + "description": "DAC reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "CAN2RST", + "description": "CAN2 reset", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CAN1RST", + "description": "CAN1 reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "I2C3RST", + "description": "I2C3 reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C 2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C 1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "UART5RST", + "description": "USART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "UART4RST", + "description": "USART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI 3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI 2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "TIM14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIM13RST", + "description": "TIM13 reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM12RST", + "description": "TIM12 reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "TIM6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "TIM5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "TIM4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "TIM3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM2RST", + "description": "TIM2 reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM11RST", + "description": "TIM11 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SYSCFGRST", + "description": "System configuration controller reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SDIORST", + "description": "SDIO reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset (common to all ADCs)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART6RST", + "description": "USART6 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM8RST", + "description": "TIM8 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1ENR", + "displayName": "AHB1ENR", + "description": "AHB1 peripheral clock register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00100000", + "fields": [ + { + "name": "OTGHSULPIEN", + "description": "USB OTG HSULPI clock enable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "OTGHSEN", + "description": "USB OTG HS clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPEN", + "description": "Ethernet PTP clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "ETHMACRXEN", + "description": "Ethernet Reception clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACTXEN", + "description": "Ethernet Transmission clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACEN", + "description": "Ethernet MAC clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BKPSRAMEN", + "description": "Backup SRAM interface clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOIEN", + "description": "IO port I clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOHEN", + "description": "IO port H clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOGEN", + "description": "IO port G clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOFEN", + "description": "IO port F clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOEEN", + "description": "IO port E clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODEN", + "description": "IO port D clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCEN", + "description": "IO port C clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBEN", + "description": "IO port B clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOAEN", + "description": "IO port A clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2ENR", + "displayName": "AHB2ENR", + "description": "AHB2 peripheral clock enable register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RNGEN", + "description": "Random number generator clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCMIEN", + "description": "Camera interface enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3ENR", + "displayName": "AHB3ENR", + "description": "AHB3 peripheral clock enable register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSMCEN", + "description": "Flexible static memory controller module clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "CAN2EN", + "description": "CAN 2 clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CAN1EN", + "description": "CAN 1 clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "I2C3EN", + "description": "I2C3 clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "TIM14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIM13EN", + "description": "TIM13 clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM12EN", + "description": "TIM12 clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "TIM6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "TIM5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "TIM4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "TIM3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM2EN", + "description": "TIM2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM11EN", + "description": "TIM11 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SYSCFGEN", + "description": "System configuration controller clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ADC3EN", + "description": "ADC3 clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC2 clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC1 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART6EN", + "description": "USART6 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM8EN", + "description": "TIM8 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM1EN", + "description": "TIM1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1LPENR", + "displayName": "AHB1LPENR", + "description": "AHB1 peripheral clock enable in low power mode register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7E6791FF", + "fields": [ + { + "name": "OTGHSULPILPEN", + "description": "USB OTG HS ULPI clock enable during Sleep mode", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "OTGHSLPEN", + "description": "USB OTG HS clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPLPEN", + "description": "Ethernet PTP clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "ETHMACRXLPEN", + "description": "Ethernet reception clock enable during Sleep mode", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACTXLPEN", + "description": "Ethernet transmission clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACLPEN", + "description": "Ethernet MAC clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMA2LPEN", + "description": "DMA2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1LPEN", + "description": "DMA1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BKPSRAMLPEN", + "description": "Backup SRAM interface clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SRAM2LPEN", + "description": "SRAM 2 interface clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SRAM1LPEN", + "description": "SRAM 1interface clock enable during Sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FLITFLPEN", + "description": "Flash interface clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CRCLPEN", + "description": "CRC clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOILPEN", + "description": "IO port I clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOHLPEN", + "description": "IO port H clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOGLPEN", + "description": "IO port G clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOFLPEN", + "description": "IO port F clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOELPEN", + "description": "IO port E clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODLPEN", + "description": "IO port D clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCLPEN", + "description": "IO port C clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBLPEN", + "description": "IO port B clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOALPEN", + "description": "IO port A clock enable during sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2LPENR", + "displayName": "AHB2LPENR", + "description": "AHB2 peripheral clock enable in low power mode register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000F1", + "fields": [ + { + "name": "OTGFSLPEN", + "description": "USB OTG FS clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RNGLPEN", + "description": "Random number generator clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCMILPEN", + "description": "Camera interface enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3LPENR", + "displayName": "AHB3LPENR", + "description": "AHB3 peripheral clock enable in low power mode register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000001", + "fields": [ + { + "name": "FSMCLPEN", + "description": "Flexible static memory controller module clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1LPENR", + "displayName": "APB1LPENR", + "description": "APB1 peripheral clock enable in low power mode register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x36FEC9FF", + "fields": [ + { + "name": "DACLPEN", + "description": "DAC interface clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "PWRLPEN", + "description": "Power interface clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "CAN2LPEN", + "description": "CAN 2 clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CAN1LPEN", + "description": "CAN 1 clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "I2C3LPEN", + "description": "I2C3 clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "I2C2LPEN", + "description": "I2C2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C1LPEN", + "description": "I2C1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "UART5LPEN", + "description": "UART5 clock enable during Sleep mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "UART4LPEN", + "description": "UART4 clock enable during Sleep mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "USART3LPEN", + "description": "USART3 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "USART2LPEN", + "description": "USART2 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SPI3LPEN", + "description": "SPI3 clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SPI2LPEN", + "description": "SPI2 clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WWDGLPEN", + "description": "Window watchdog clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM14LPEN", + "description": "TIM14 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIM13LPEN", + "description": "TIM13 clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM12LPEN", + "description": "TIM12 clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM7LPEN", + "description": "TIM7 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM6LPEN", + "description": "TIM6 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM5LPEN", + "description": "TIM5 clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM4LPEN", + "description": "TIM4 clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM3LPEN", + "description": "TIM3 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM2LPEN", + "description": "TIM2 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2LPENR", + "displayName": "APB2LPENR", + "description": "APB2 peripheral clock enabled in low power mode register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00075F33", + "fields": [ + { + "name": "TIM11LPEN", + "description": "TIM11 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TIM10LPEN", + "description": "TIM10 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM9LPEN", + "description": "TIM9 clock enable during sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SYSCFGLPEN", + "description": "System configuration controller clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI1LPEN", + "description": "SPI 1 clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SDIOLPEN", + "description": "SDIO clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ADC3LPEN", + "description": "ADC 3 clock enable during Sleep mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ADC2LPEN", + "description": "ADC2 clock enable during Sleep mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC1LPEN", + "description": "ADC1 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART6LPEN", + "description": "USART6 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "USART1LPEN", + "description": "USART1 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM8LPEN", + "description": "TIM8 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM1LPEN", + "description": "TIM1 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register", + "addressOffset": "0x70", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL1", + "description": "RTC clock source selection", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL0", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSEBYP", + "description": "External low-speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEON", + "description": "External low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Clock control & status register", + "addressOffset": "0x74", + "size": "0x20", + "resetValue": "0x0E000000", + "fields": [ + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PADRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BORRSTF", + "description": "BOR reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSION", + "description": "Internal low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SSCGR", + "displayName": "SSCGR", + "description": "Spread spectrum clock generation register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SSCGEN", + "description": "Spread spectrum modulation enable", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SPREADSEL", + "description": "Spread Select", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "INCSTEP", + "description": "Incrementation step", + "bitOffset": "13", + "bitWidth": "15" + }, + { + "name": "MODPER", + "description": "Modulation period", + "bitOffset": "0", + "bitWidth": "13" + } + ] + }, + { + "name": "PLLI2SCFGR", + "displayName": "PLLI2SCFGR", + "description": "PLLI2S configuration register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20003000", + "fields": [ + { + "name": "PLLI2SRx", + "description": "PLLI2S division factor for I2S clocks", + "bitOffset": "28", + "bitWidth": "3" + }, + { + "name": "PLLI2SNx", + "description": "PLLI2S multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + } + ] + } + ] + }, + { + "name": "GPIOI", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40022000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "GPIOH", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021C00" + }, + { + "name": "GPIOG", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021800" + }, + { + "name": "GPIOF", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021400" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOI", + "baseAddress": "0x40021000" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOI", + "baseAddress": "0X40020C00" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOI", + "baseAddress": "0x40020800" + }, + { + "name": "GPIOB", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000280", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000C0", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000100", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xA8000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x64000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MEMRM", + "displayName": "MEMRM", + "description": "Memory remap register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "MEM_MODE", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PMC", + "displayName": "PMC", + "description": "Peripheral mode configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MII_RMII_SEL", + "description": "Ethernet PHY interface selection", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI3", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI0", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI7", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI4", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI11", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI8", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI15", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI12", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CMPCR", + "displayName": "CMPCR", + "description": "Compensation cell control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "READY", + "description": "READY", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMP_PD", + "description": "Compensation cell power-down", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ] + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ] + }, + { + "name": "I2S2ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40003400" + }, + { + "name": "I2S3ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40004000" + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Argument register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "Command register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CE_ATACMD", + "description": "CE-ATA command", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "Not Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "Enable CMD completion", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SD I/O suspend command", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "Command path state machine (CPSM) Enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "CPSM Waits for ends of data transfer (CmdPend internal signal).", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WAITINT", + "description": "CPSM waits for interrupt request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITRESP", + "description": "Wait for response bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CMDINDEX", + "description": "Command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "Command response register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "Response command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESP1", + "displayName": "RESP1", + "description": "Response 1..4 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Response 1..4 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Response 1..4 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Response 1..4 register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Data timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Data length register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "Data control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SDIOEN", + "description": "SD I/O enable functions", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "Read wait mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "RWSTOP", + "description": "Read wait stop", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWSTART", + "description": "Read wait start", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "Data block size", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DMAEN", + "description": "DMA enable bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "Data transfer mode selection 1: Stream or SDIO multibyte data transfer.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "Data transfer direction selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Data counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAEND", + "description": "CE-ATA command completion signal received for CMD61", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIO interrupt received", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "Data available in receive FIFO", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "Data available in transmit FIFO", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "Receive FIFO empty", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "Transmit FIFO empty", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "Receive FIFO full", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "Transmit FIFO full", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "Receive FIFO half full: there are at least 8 words in the FIFO", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "Transmit FIFO half empty: at least 8 words can be written into the FIFO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "Data receive in progress", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "Data transmit in progress", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "Command transfer in progress", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "Data block sent/received (CRC check passed)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "Start bit not detected on all data signals in wide bus mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "Data end (data counter, SDIDCOUNT, is zero)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "Command sent (no response required)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "Command response received (CRC check passed)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "Received FIFO overrun error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "Transmit FIFO underrun error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "Data timeout", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "Command response timeout", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "Data block sent/received (CRC check failed)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAIL", + "description": "Command response received (CRC check failed)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAENDC", + "description": "CEATAEND flag clear bit", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOIT flag clear bit", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKEND flag clear bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERR flag clear bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAEND flag clear bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENT flag clear bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDREND flag clear bit", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERR flag clear bit", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERR flag clear bit", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUT flag clear bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUT flag clear bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAIL flag clear bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAILC", + "description": "CCRCFAIL flag clear bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "Mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAENDIE", + "description": "CE-ATA command completion signal received interrupt enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIO mode interrupt received interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "Data available in Rx FIFO interrupt enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "Data available in Tx FIFO interrupt enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "Rx FIFO empty interrupt enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "Tx FIFO empty interrupt enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "Rx FIFO full interrupt enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "Tx FIFO full interrupt enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "Rx FIFO half full interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "Tx FIFO half empty interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "Data receive acting interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "Data transmit acting interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "Command acting interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBCKENDIE", + "description": "Data block end interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "Start bit error interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "Data end interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "Command sent interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "Command response received interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "Rx FIFO overrun error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "Tx FIFO underrun error interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "Data timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "Command timeout interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "Data CRC fail interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAILIE", + "description": "Command CRC fail interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "FIFO counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOCOUNT", + "description": "Remaining number of words to be written to or read from the FIFO.", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Data FIFO register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "Receive and transmit FIFO data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ADC1", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVR", + "description": "Overrun", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Resolution", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "EXTEN", + "description": "External trigger enable for regular channels", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "JEXTEN", + "description": "External trigger enable for injected channels", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "EOCS", + "description": "End of conversion selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DDS", + "description": "DMA disable selection (for single ADC mode)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode (for single ADC mode)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADON", + "description": "A/D Converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "ADC2", + "derivedFrom": "ADC1", + "baseAddress": "0x40012100", + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupts", + "value": "18" + } + ] + }, + { + "name": "ADC3", + "derivedFrom": "ADC1", + "baseAddress": "0x40012200", + "interrupts": [ + { + "name": "ADC", + "description": "ADC3 global interrupts", + "value": "18" + } + ] + }, + { + "name": "USART6", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40011400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART6", + "description": "USART6 global interrupt", + "value": "71" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "USART1", + "derivedFrom": "USART6", + "baseAddress": "0x40011000", + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ] + }, + { + "name": "USART2", + "derivedFrom": "USART6", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ] + }, + { + "name": "USART3", + "derivedFrom": "USART6", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDRIE2", + "description": "DAC channel2 DMA underrun interrupt enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMAUDRIE1", + "description": "DAC channel1 DMA Underrun Interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "Channel2 12-bit right aligned data holding register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "Channel2 12-bit left aligned data holding register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "Channel2 8-bit right-aligned data holding register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "20", + "bitWidth": "12" + }, + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "Channel2 data output register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FPDS", + "description": "Flash power down in Stop mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BRR", + "description": "Backup regulator ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BRE", + "description": "Backup regulator enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VOSRDY", + "description": "Regulator voltage scaling output selection ready bit", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "I2C3", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ] + }, + { + "name": "I2C2", + "derivedFrom": "I2C3", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ] + }, + { + "name": "I2C1", + "derivedFrom": "I2C3", + "baseAddress": "0x40005400", + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ] + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value (write only, read 0000h)", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WDGTB1", + "description": "Timer base", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WDGTB0", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC_WKUP", + "description": "RTC Wakeup interrupt through the EXTI line", + "value": "3" + }, + { + "name": "RTC_Alarm", + "description": "RTC Alarms (A and B) through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WUTIE", + "description": "Wakeup timer interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ALRBIE", + "description": "Alarm B interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WUTE", + "description": "Wakeup timer enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ALRBE", + "description": "Alarm B enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DCE", + "description": "Coarse digital calibration enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "REFCKON", + "description": "Reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WCKSEL", + "description": "Wakeup clock selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALRBWF", + "description": "Alarm B write flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "WUTWF", + "description": "Wakeup timer write flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRBF", + "description": "Alarm B flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUTF", + "description": "Wakeup timer flag", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "Tamper detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "TAMPER2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + }, + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "WUTR", + "displayName": "WUTR", + "description": "Wakeup timer register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "WUT", + "description": "Wakeup auto-reload value bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALIBR", + "displayName": "CALIBR", + "description": "Calibration register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCS", + "description": "Digital calibration sign", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "Digital calibration", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "ALRMBR", + "displayName": "ALRMBR", + "description": "Alarm B register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm B date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm B hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm B minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm B seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADD1S", + "description": "Add one second", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Time stamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Time stamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Timestamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALP", + "description": "Increase frequency of RTC by 488.5 ppm", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALW16", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TAMPPUDIS", + "description": "TAMPER pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMPPRCH", + "description": "Tamper precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPFLT", + "description": "Tamper filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMP2TRG", + "description": "Active level for tamper 2", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "Tamper 2 detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "ALRMBSSR", + "displayName": "ALRMBSSR", + "description": "Alarm B sub second register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP5R", + "displayName": "BKP5R", + "description": "Backup register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP6R", + "displayName": "BKP6R", + "description": "Backup register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP7R", + "displayName": "BKP7R", + "description": "Backup register", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP8R", + "displayName": "BKP8R", + "description": "Backup register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP9R", + "displayName": "BKP9R", + "description": "Backup register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP10R", + "displayName": "BKP10R", + "description": "Backup register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP11R", + "displayName": "BKP11R", + "description": "Backup register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP12R", + "displayName": "BKP12R", + "description": "Backup register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP13R", + "displayName": "BKP13R", + "description": "Backup register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP14R", + "displayName": "BKP14R", + "description": "Backup register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP15R", + "displayName": "BKP15R", + "description": "Backup register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP16R", + "displayName": "BKP16R", + "description": "Backup register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP17R", + "displayName": "BKP17R", + "description": "Backup register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP18R", + "displayName": "BKP18R", + "description": "Backup register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP19R", + "displayName": "BKP19R", + "description": "Backup register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "UART4", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "UART5", + "derivedFrom": "UART4", + "baseAddress": "0x40005000", + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ] + }, + { + "name": "C_ADC", + "description": "Common ADC registers", + "groupName": "ADC", + "baseAddress": "0x40012300", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "ADC Common status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVR3", + "description": "Overrun flag of ADC3", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "STRT3", + "description": "Regular channel Start flag of ADC 3", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "JSTRT3", + "description": "Injected channel Start flag of ADC 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "JEOC3", + "description": "Injected channel end of conversion of ADC 3", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "EOC3", + "description": "End of conversion of ADC 3", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "AWD3", + "description": "Analog watchdog flag of ADC 3", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "OVR2", + "description": "Overrun flag of ADC 2", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "STRT2", + "description": "Regular channel Start flag of ADC 2", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "JSTRT2", + "description": "Injected channel Start flag of ADC 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEOC2", + "description": "Injected channel end of conversion of ADC 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOC2", + "description": "End of conversion of ADC 2", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "AWD2", + "description": "Analog watchdog flag of ADC 2", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OVR1", + "description": "Overrun flag of ADC 1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT1", + "description": "Regular channel Start flag of ADC 1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT1", + "description": "Injected channel Start flag of ADC 1", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC1", + "description": "Injected channel end of conversion of ADC 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC1", + "description": "End of conversion of ADC 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD1", + "description": "Analog watchdog flag of ADC 1", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "ADC common control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "VBATE", + "description": "VBAT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DMA", + "description": "Direct memory access mode for multi ADC mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "DDS", + "description": "DMA disable selection for multi-ADC mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DELAY", + "description": "Delay between 2 sampling phases", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MULT", + "description": "Multi ADC mode selection", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CDR", + "displayName": "CDR", + "description": "ADC common regular data register for dual and triple modes", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA2", + "description": "2nd data item of a pair of regular conversions", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "DATA1", + "description": "1st data item of a pair of regular conversions", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40010400", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + }, + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + }, + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + }, + { + "name": "TIM8_CC", + "description": "TIM8 Capture Compare interrupt", + "value": "46" + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ITR1_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM3", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM3", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "IT4_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "6", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM9", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM12", + "derivedFrom": "TIM9", + "baseAddress": "0x40001800", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + } + ] + }, + { + "name": "TIM10", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM13", + "derivedFrom": "TIM10", + "baseAddress": "0x40001C00", + "interrupts": [ + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + } + ] + }, + { + "name": "TIM14", + "derivedFrom": "TIM10", + "baseAddress": "0x40002000", + "interrupts": [ + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + } + ] + }, + { + "name": "TIM11", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Input 1 remapping capability", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM6", + "description": "Basic timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "Ethernet_MAC", + "description": "Ethernet: media access control (MAC)", + "groupName": "Ethernet", + "baseAddress": "0x40028000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ETH", + "description": "Ethernet global interrupt", + "value": "61" + }, + { + "name": "ETH_WKUP", + "description": "Ethernet Wakeup through EXTI line interrupt", + "value": "62" + } + ], + "registers": [ + { + "name": "MACCR", + "displayName": "MACCR", + "description": "Ethernet MAC configuration register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0008000", + "fields": [ + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "DC", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BL", + "description": "BL", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "APCS", + "description": "APCS", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RD", + "description": "RD", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IPCO", + "description": "IPCO", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DM", + "description": "DM", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LM", + "description": "LM", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ROD", + "description": "ROD", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FES", + "description": "FES", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CSD", + "description": "CSD", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "IFG", + "description": "IFG", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JD", + "description": "JD", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WD", + "description": "WD", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CSTF", + "description": "CSTF", + "bitOffset": "25", + "bitWidth": "1" + } + ] + }, + { + "name": "MACFFR", + "displayName": "MACFFR", + "description": "Ethernet MAC frame filter register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HM", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAIF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RAM", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BFD", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PCF", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SAIF", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SAF", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HPF", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RA", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACHTHR", + "displayName": "MACHTHR", + "description": "Ethernet MAC hash table high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACHTLR", + "displayName": "MACHTLR", + "description": "Ethernet MAC hash table low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACMIIAR", + "displayName": "MACMIIAR", + "description": "Ethernet MAC MII address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MW", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "3" + }, + { + "name": "MR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "5" + }, + { + "name": "PA", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "5" + } + ] + }, + { + "name": "MACMIIDR", + "displayName": "MACMIIDR", + "description": "Ethernet MAC MII data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "MACFCR", + "displayName": "MACFCR", + "description": "Ethernet MAC flow control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FCB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TFCE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RFCE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UPFD", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLT", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ZQPD", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "MACVLANTR", + "displayName": "MACVLANTR", + "description": "Ethernet MAC VLAN tag register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VLANTI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "VLANTC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MACPMTCSR", + "displayName": "MACPMTCSR", + "description": "Ethernet MAC PMT control and status register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MPE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WFE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MPR", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WFR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GU", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WFFRPR", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACDBGR", + "displayName": "MACDBGR", + "description": "Ethernet MAC debug register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "CR", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "CSR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "ROR", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "MCF", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "MCP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "MCFHP", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MACSR", + "displayName": "MACSR", + "description": "Ethernet MAC interrupt status register", + "addressOffset": "0x38", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCRS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCTS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "MACIMR", + "displayName": "MACIMR", + "description": "Ethernet MAC interrupt mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTIM", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSTIM", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA0HR", + "displayName": "MACA0HR", + "description": "Ethernet MAC address 0 high register", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x0010FFFF", + "fields": [ + { + "name": "MACA0H", + "description": "MAC address0 high", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "MO", + "description": "Always 1", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "MACA0LR", + "displayName": "MACA0LR", + "description": "Ethernet MAC address 0 low register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA0L", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA1HR", + "displayName": "MACA1HR", + "description": "Ethernet MAC address 1 high register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA1H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA1LR", + "displayName": "MACA1LR", + "description": "Ethernet MAC address1 low register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA1LR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA2HR", + "displayName": "MACA2HR", + "description": "Ethernet MAC address 2 high register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MAC2AH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA2LR", + "displayName": "MACA2LR", + "description": "Ethernet MAC address 2 low register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA2L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + } + ] + }, + { + "name": "MACA3HR", + "displayName": "MACA3HR", + "description": "Ethernet MAC address 3 high register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA3H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA3LR", + "displayName": "MACA3LR", + "description": "Ethernet MAC address 3 low register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MBCA3L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_MMC", + "description": "Ethernet: MAC management counters", + "groupName": "Ethernet", + "baseAddress": "0x40028100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MMCCR", + "displayName": "MMCCR", + "description": "Ethernet MMC control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIR", + "displayName": "MMCRIR", + "description": "Ethernet MMC receive interrupt register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCES", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAES", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIR", + "displayName": "MMCTIR", + "description": "Ethernet MMC transmit interrupt register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFS", + "description": "No description available", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIMR", + "displayName": "MMCRIMR", + "description": "Ethernet MMC receive interrupt mask register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCEM", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAEM", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFM", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIMR", + "displayName": "MMCTIMR", + "description": "Ethernet MMC transmit interrupt mask register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCM", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCM", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFM", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTGFSCCR", + "displayName": "MMCTGFSCCR", + "description": "Ethernet MMC transmitted good frames after a single collision counter", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFMSCCR", + "displayName": "MMCTGFMSCCR", + "description": "Ethernet MMC transmitted good frames after more than a single collision", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFMSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFCR", + "displayName": "MMCTGFCR", + "description": "Ethernet MMC transmitted good frames counter register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFC", + "description": "HTL", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFCECR", + "displayName": "MMCRFCECR", + "description": "Ethernet MMC received frames with CRC error counter register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFAECR", + "displayName": "MMCRFAECR", + "description": "Ethernet MMC received frames with alignment error counter register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFAEC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRGUFCR", + "displayName": "MMCRGUFCR", + "description": "MMC received good unicast frames counter register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RGUFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_PTP", + "description": "Ethernet: Precision time protocol", + "groupName": "Ethernet", + "baseAddress": "0x40028700", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "PTPTSCR", + "displayName": "PTPTSCR", + "description": "Ethernet PTP time stamp control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "TSE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSFCU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSPTPPSV2E", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TSSPTPOEFE", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TSSIPV6FE", + "description": "No description available", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TSSIPV4FE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TSSEME", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TSSMRME", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TSCNT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "TSPFFMAE", + "description": "No description available", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSSTI", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSSTU", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSITE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TTSARU", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TSSARFE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TSSSR", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPSSIR", + "displayName": "PTPSSIR", + "description": "Ethernet PTP subsecond increment register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSSI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PTPTSHR", + "displayName": "PTPTSHR", + "description": "Ethernet PTP time stamp high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLR", + "displayName": "PTPTSLR", + "description": "Ethernet PTP time stamp low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "STPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSHUR", + "displayName": "PTPTSHUR", + "description": "Ethernet PTP time stamp high update register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLUR", + "displayName": "PTPTSLUR", + "description": "Ethernet PTP time stamp low update register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "TSUPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSAR", + "displayName": "PTPTSAR", + "description": "Ethernet PTP time stamp addend register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSA", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTHR", + "displayName": "PTPTTHR", + "description": "Ethernet PTP target time high register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSH", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTLR", + "displayName": "PTPTTLR", + "description": "Ethernet PTP target time low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSSR", + "displayName": "PTPTSSR", + "description": "Ethernet PTP time stamp status register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPPPSCR", + "displayName": "PTPPPSCR", + "description": "Ethernet PTP PPS control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "TSSO", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "TSTTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "Ethernet_DMA", + "description": "Ethernet: DMA controller operation", + "groupName": "Ethernet", + "baseAddress": "0x40029000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DMABMR", + "displayName": "DMABMR", + "description": "Ethernet DMA bus mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "SR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DA", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DSL", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "5" + }, + { + "name": "EDFE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PBL", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "RTPR", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "FB", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "6" + }, + { + "name": "USP", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FPM", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AAB", + "description": "No description available", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MB", + "description": "No description available", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMATPDR", + "displayName": "DMATPDR", + "description": "Ethernet DMA transmit poll demand register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARPDR", + "displayName": "DMARPDR", + "description": "EHERNET DMA receive poll demand register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RPD", + "description": "RPD", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARDLAR", + "displayName": "DMARDLAR", + "description": "Ethernet DMA receive descriptor list address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SRL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMATDLAR", + "displayName": "DMATDLAR", + "description": "Ethernet DMA transmit descriptor list address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMASR", + "displayName": "DMASR", + "description": "Ethernet DMA status register", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TPSS", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TBUS", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TJTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ROS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TUS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RBUS", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPSS", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PWTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETS", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FBES", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AIS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NIS", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "TPS", + "description": "No description available", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "EBS", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DMAOMR", + "displayName": "DMAOMR", + "description": "Ethernet DMA operation mode register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SR", + "description": "SR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OSF", + "description": "OSF", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTC", + "description": "RTC", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "FUGF", + "description": "FUGF", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FEF", + "description": "FEF", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "ST", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TTC", + "description": "TTC", + "bitOffset": "14", + "bitWidth": "3" + }, + { + "name": "FTF", + "description": "FTF", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TSF", + "description": "TSF", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DFRF", + "description": "DFRF", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "RSF", + "description": "RSF", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DTCEFD", + "description": "DTCEFD", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAIER", + "displayName": "DMAIER", + "description": "Ethernet DMA interrupt enable register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPSIE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TBUIE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TJTIE", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ROIE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TUIE", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RIE", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RBUIE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RPSIE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWTIE", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ETIE", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBEIE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ERIE", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AISE", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NISE", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAMFBOCR", + "displayName": "DMAMFBOCR", + "description": "Ethernet DMA missed frame and buffer overflow counter register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OMFC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MFA", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "11" + }, + { + "name": "OFOC", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "DMARSWTR", + "displayName": "DMARSWTR", + "description": "Ethernet DMA receive status watchdog timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RSWTC", + "description": "RSWTC", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DMACHTDR", + "displayName": "DMACHTDR", + "description": "Ethernet DMA current host transmit descriptor register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTDAP", + "description": "HTDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRDR", + "displayName": "DMACHRDR", + "description": "Ethernet DMA current host receive descriptor register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRDAP", + "description": "HRDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHTBAR", + "displayName": "DMACHTBAR", + "description": "Ethernet DMA current host transmit buffer address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRBAR", + "displayName": "DMACHRBAR", + "description": "Ethernet DMA current host receive buffer address register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "Cryptographic processor", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Control regidter", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_FS_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS_WKUP", + "description": "USB On-The-Go FS Wakeup through EXTI line interrupt", + "value": "42" + }, + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "OTG_FS_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + } + ] + }, + { + "name": "OTG_FS_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN1", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupts", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ], + "registers": [ + { + "name": "MCR", + "displayName": "MCR", + "description": "Master control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00010002", + "fields": [ + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "MSR", + "displayName": "MSR", + "description": "Master status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000C02", + "fields": [ + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "TSR", + "displayName": "TSR", + "description": "Transmit status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x1C000000", + "fields": [ + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "RF0R", + "displayName": "RF0R", + "description": "Receive FIFO 0 register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "RF1R", + "displayName": "RF1R", + "description": "Receive FIFO 1 register", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ESR", + "displayName": "ESR", + "description": "Interrupt enable register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "BTR", + "displayName": "BTR", + "description": "Bit timing register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + } + ] + }, + { + "name": "TI0R", + "displayName": "TI0R", + "description": "TX mailbox identifier register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TDT0R", + "displayName": "TDT0R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TDL0R", + "displayName": "TDL0R", + "description": "Mailbox data low register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH0R", + "displayName": "TDH0R", + "description": "Mailbox data high register", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TI1R", + "displayName": "TI1R", + "description": "Mailbox identifier register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TDT1R", + "displayName": "TDT1R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TDL1R", + "displayName": "TDL1R", + "description": "Mailbox data low register", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH1R", + "displayName": "TDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TI2R", + "displayName": "TI2R", + "description": "Mailbox identifier register", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TDT2R", + "displayName": "TDT2R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TDL2R", + "displayName": "TDL2R", + "description": "Mailbox data low register", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH2R", + "displayName": "TDH2R", + "description": "Mailbox data high register", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RI0R", + "displayName": "RI0R", + "description": "Receive FIFO mailbox identifier register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "RDT0R", + "displayName": "RDT0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "RDL0R", + "displayName": "RDL0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH0R", + "displayName": "RDH0R", + "description": "Receive FIFO mailbox data high register", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RI1R", + "displayName": "RI1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "RDT1R", + "displayName": "RDT1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "RDL1R", + "displayName": "RDL1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH1R", + "displayName": "RDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "FMR", + "displayName": "FMR", + "description": "Filter master register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2A1C0E01", + "fields": [ + { + "name": "CAN2SB", + "description": "CAN2SB", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "FM1R", + "displayName": "FM1R", + "description": "Filter mode register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FBM14", + "description": "Filter mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FS1R", + "displayName": "FS1R", + "description": "Filter scale register", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FFA1R", + "displayName": "FFA1R", + "description": "Filter FIFO assignment register", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FA1R", + "displayName": "FA1R", + "description": "Filter activation register", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN2", + "derivedFrom": "CAN1", + "baseAddress": "0x40006800", + "interrupts": [ + { + "name": "CAN2_TX", + "description": "CAN2 TX interrupts", + "value": "63" + }, + { + "name": "CAN2_RX0", + "description": "CAN2 RX0 interrupts", + "value": "64" + }, + { + "name": "CAN2_RX1", + "description": "CAN2 RX1 interrupts", + "value": "65" + }, + { + "name": "CAN2_SCE", + "description": "CAN2 SCE interrupt", + "value": "66" + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40023C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bitOffset": "11", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OPERR", + "description": "Operation error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGPERR", + "description": "Programming parallelism error", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x80000000", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SER", + "description": "Sector Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SNB", + "description": "Sector number", + "bitOffset": "3", + "bitWidth": "4" + }, + { + "name": "PSIZE", + "description": "Program size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OPTCR", + "displayName": "OPTCR", + "description": "Flash option control register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "OPTLOCK", + "description": "Option lock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OPTSTRT", + "description": "Option start", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "WDG_SW", + "description": "WDG_SW User option bytes", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP User option bytes", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY User option bytes", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Read protect", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40013C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMP_STAMP", + "description": "Tamper and TimeStamp interrupts through the EXTI line", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Rising trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Rising trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Rising trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Falling trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Falling trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Falling trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SWIER20", + "description": "Software Interrupt on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SWIER21", + "description": "Software Interrupt on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWIER22", + "description": "Software Interrupt on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PR20", + "description": "Pending bit 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PR21", + "description": "Pending bit 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PR22", + "description": "Pending bit 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_HS_GLOBAL", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0xFFFC0400", + "usage": "registers" + }, + { + "offset": "0xFFFC0400", + "size": "0x40000", + "usage": "reserved" + } + ], + "interrupts": [ + { + "name": "OTG_HS_EP1_OUT", + "description": "USB On The Go HS End Point 1 Out global interrupt", + "value": "74" + }, + { + "name": "OTG_HS_EP1_IN", + "description": "USB On The Go HS End Point 1 In global interrupt", + "value": "75" + }, + { + "name": "OTG_HS_WKUP", + "description": "USB On The Go HS Wakeup through EXTI interrupt", + "value": "76" + }, + { + "name": "OTG_HS", + "description": "USB On The Go HS global interrupt", + "value": "77" + } + ], + "registers": [ + { + "name": "OTG_HS_GOTGCTL", + "displayName": "OTG_HS_GOTGCTL", + "description": "OTG_HS control and status register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GOTGINT", + "displayName": "OTG_HS_GOTGINT", + "description": "OTG_HS interrupt register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GAHBCFG", + "displayName": "OTG_HS_GAHBCFG", + "description": "OTG_HS AHB configuration register", + "addressOffset": "0x8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HBSTLEN", + "description": "Burst length/type", + "bitOffset": "1", + "bitWidth": "4" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GUSBCFG", + "displayName": "OTG_HS_GUSBCFG", + "description": "OTG_HS USB configuration register", + "addressOffset": "0xC", + "size": "32", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PHYLPCS", + "description": "PHY Low-power clock select", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIFSLS", + "description": "ULPI FS/LS select", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIAR", + "description": "ULPI Auto-resume", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPICSM", + "description": "ULPI Clock SuspendM", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSD", + "description": "ULPI External VBUS Drive", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSI", + "description": "ULPI external VBUS indicator", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSDPS", + "description": "TermSel DLine pulsing selection", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PCCI", + "description": "Indicator complement", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCI", + "description": "Indicator pass through", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIIPD", + "description": "ULPI interface protect disable", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Forced host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Forced peripheral mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRSTCTL", + "displayName": "OTG_HS_GRSTCTL", + "description": "OTG_HS reset register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "DMAREQ", + "description": "DMA request signal", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GINTSTS", + "displayName": "OTG_HS_GINTSTS", + "description": "OTG_HS core interrupt register", + "addressOffset": "0x14", + "size": "32", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO nonempty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Nonperiodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN nonperiodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DATAFSUSP", + "description": "Data fetch suspended", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GINTMSK", + "displayName": "OTG_HS_GINTMSK", + "description": "OTG_HS interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO nonempty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Nonperiodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global nonperiodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FSUSPM", + "description": "Data fetch suspended mask", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Host", + "displayName": "OTG_HS_GRXSTSR_Host", + "description": "OTG_HS Receive status debug read register (host mode)", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Host", + "displayName": "OTG_HS_GRXSTSP_Host", + "description": "OTG_HS status read and pop register (host mode)", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXFSIZ", + "displayName": "OTG_HS_GRXFSIZ", + "description": "OTG_HS Receive FIFO size register", + "addressOffset": "0x24", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXFSIZ_Host", + "displayName": "OTG_HS_GNPTXFSIZ_Host", + "description": "OTG_HS nonperiodic transmit FIFO size register (host mode)", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Nonperiodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Nonperiodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_TX0FSIZ_Peripheral", + "displayName": "OTG_HS_TX0FSIZ_Peripheral", + "description": "Endpoint 0 transmit FIFO size (peripheral mode)", + "headerStructName": "OTG_HS_GNPTXFSIZ_Host", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXSTS", + "displayName": "OTG_HS_GNPTXSTS", + "description": "OTG_HS nonperiodic transmit FIFO/queue status register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Nonperiodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Nonperiodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the nonperiodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "OTG_HS_GCCFG", + "displayName": "OTG_HS_GCCFG", + "description": "OTG_HS general core configuration register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2CPADEN", + "description": "Enable I2C bus connection for the external I2C PHY interface", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "NOVBUSSENS", + "description": "VBUS sensing disable option", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_CID", + "displayName": "OTG_HS_CID", + "description": "OTG_HS core ID register", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x00001200", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HPTXFSIZ", + "displayName": "OTG_HS_HPTXFSIZ", + "description": "OTG_HS Host periodic transmit FIFO size register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFD", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF1", + "displayName": "OTG_HS_DIEPTXF1", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF2", + "displayName": "OTG_HS_DIEPTXF2", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF3", + "displayName": "OTG_HS_DIEPTXF3", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x11C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF4", + "displayName": "OTG_HS_DIEPTXF4", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF5", + "displayName": "OTG_HS_DIEPTXF5", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF6", + "displayName": "OTG_HS_DIEPTXF6", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF7", + "displayName": "OTG_HS_DIEPTXF7", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Peripheral", + "displayName": "OTG_HS_GRXSTSR_Peripheral", + "description": "OTG_HS Receive status debug read register (peripheral mode mode)", + "headerStructName": "OTG_HS_GRXSTSR_Host", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Peripheral", + "displayName": "OTG_HS_GRXSTSP_Peripheral", + "description": "OTG_HS status read and pop register (peripheral mode)", + "headerStructName": "OTG_HS_GRXSTSP_Host", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "OTG_HS_HOST", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_HCFG", + "displayName": "OTG_HS_HCFG", + "description": "OTG_HS host configuration register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HFIR", + "displayName": "OTG_HS_HFIR", + "description": "OTG_HS Host frame interval register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HFNUM", + "displayName": "OTG_HS_HFNUM", + "description": "OTG_HS host frame number/frame time remaining register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPTXSTS", + "displayName": "OTG_HS_HPTXSTS", + "description": "OTG_HS_Host periodic transmit FIFO/queue status register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HAINT", + "displayName": "OTG_HS_HAINT", + "description": "OTG_HS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HAINTMSK", + "displayName": "OTG_HS_HAINTMSK", + "description": "OTG_HS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPRT", + "displayName": "OTG_HS_HPRT", + "description": "OTG_HS host port control and status register", + "addressOffset": "0x40", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HCCHAR0", + "displayName": "OTG_HS_HCCHAR0", + "description": "OTG_HS host channel-0 characteristics register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR1", + "displayName": "OTG_HS_HCCHAR1", + "description": "OTG_HS host channel-1 characteristics register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR2", + "displayName": "OTG_HS_HCCHAR2", + "description": "OTG_HS host channel-2 characteristics register", + "addressOffset": "0x140", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR3", + "displayName": "OTG_HS_HCCHAR3", + "description": "OTG_HS host channel-3 characteristics register", + "addressOffset": "0x160", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR4", + "displayName": "OTG_HS_HCCHAR4", + "description": "OTG_HS host channel-4 characteristics register", + "addressOffset": "0x180", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR5", + "displayName": "OTG_HS_HCCHAR5", + "description": "OTG_HS host channel-5 characteristics register", + "addressOffset": "0x1A0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR6", + "displayName": "OTG_HS_HCCHAR6", + "description": "OTG_HS host channel-6 characteristics register", + "addressOffset": "0x1C0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR7", + "displayName": "OTG_HS_HCCHAR7", + "description": "OTG_HS host channel-7 characteristics register", + "addressOffset": "0x1E0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR8", + "displayName": "OTG_HS_HCCHAR8", + "description": "OTG_HS host channel-8 characteristics register", + "addressOffset": "0x200", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR9", + "displayName": "OTG_HS_HCCHAR9", + "description": "OTG_HS host channel-9 characteristics register", + "addressOffset": "0x220", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR10", + "displayName": "OTG_HS_HCCHAR10", + "description": "OTG_HS host channel-10 characteristics register", + "addressOffset": "0x240", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR11", + "displayName": "OTG_HS_HCCHAR11", + "description": "OTG_HS host channel-11 characteristics register", + "addressOffset": "0x260", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT0", + "displayName": "OTG_HS_HCSPLT0", + "description": "OTG_HS host channel-0 split control register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT1", + "displayName": "OTG_HS_HCSPLT1", + "description": "OTG_HS host channel-1 split control register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT2", + "displayName": "OTG_HS_HCSPLT2", + "description": "OTG_HS host channel-2 split control register", + "addressOffset": "0x144", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT3", + "displayName": "OTG_HS_HCSPLT3", + "description": "OTG_HS host channel-3 split control register", + "addressOffset": "0x164", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT4", + "displayName": "OTG_HS_HCSPLT4", + "description": "OTG_HS host channel-4 split control register", + "addressOffset": "0x184", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT5", + "displayName": "OTG_HS_HCSPLT5", + "description": "OTG_HS host channel-5 split control register", + "addressOffset": "0x1A4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT6", + "displayName": "OTG_HS_HCSPLT6", + "description": "OTG_HS host channel-6 split control register", + "addressOffset": "0x1C4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT7", + "displayName": "OTG_HS_HCSPLT7", + "description": "OTG_HS host channel-7 split control register", + "addressOffset": "0x1E4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT8", + "displayName": "OTG_HS_HCSPLT8", + "description": "OTG_HS host channel-8 split control register", + "addressOffset": "0x204", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT9", + "displayName": "OTG_HS_HCSPLT9", + "description": "OTG_HS host channel-9 split control register", + "addressOffset": "0x224", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT10", + "displayName": "OTG_HS_HCSPLT10", + "description": "OTG_HS host channel-10 split control register", + "addressOffset": "0x244", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT11", + "displayName": "OTG_HS_HCSPLT11", + "description": "OTG_HS host channel-11 split control register", + "addressOffset": "0x264", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT0", + "displayName": "OTG_HS_HCINT0", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT1", + "displayName": "OTG_HS_HCINT1", + "description": "OTG_HS host channel-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT2", + "displayName": "OTG_HS_HCINT2", + "description": "OTG_HS host channel-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT3", + "displayName": "OTG_HS_HCINT3", + "description": "OTG_HS host channel-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT4", + "displayName": "OTG_HS_HCINT4", + "description": "OTG_HS host channel-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT5", + "displayName": "OTG_HS_HCINT5", + "description": "OTG_HS host channel-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT6", + "displayName": "OTG_HS_HCINT6", + "description": "OTG_HS host channel-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT7", + "displayName": "OTG_HS_HCINT7", + "description": "OTG_HS host channel-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT8", + "displayName": "OTG_HS_HCINT8", + "description": "OTG_HS host channel-8 interrupt register", + "addressOffset": "0x208", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT9", + "displayName": "OTG_HS_HCINT9", + "description": "OTG_HS host channel-9 interrupt register", + "addressOffset": "0x228", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT10", + "displayName": "OTG_HS_HCINT10", + "description": "OTG_HS host channel-10 interrupt register", + "addressOffset": "0x248", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT11", + "displayName": "OTG_HS_HCINT11", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x268", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK0", + "displayName": "OTG_HS_HCINTMSK0", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x10C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK1", + "displayName": "OTG_HS_HCINTMSK1", + "description": "OTG_HS host channel-1 interrupt mask register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK2", + "displayName": "OTG_HS_HCINTMSK2", + "description": "OTG_HS host channel-2 interrupt mask register", + "addressOffset": "0x14C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK3", + "displayName": "OTG_HS_HCINTMSK3", + "description": "OTG_HS host channel-3 interrupt mask register", + "addressOffset": "0x16C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK4", + "displayName": "OTG_HS_HCINTMSK4", + "description": "OTG_HS host channel-4 interrupt mask register", + "addressOffset": "0x18C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK5", + "displayName": "OTG_HS_HCINTMSK5", + "description": "OTG_HS host channel-5 interrupt mask register", + "addressOffset": "0x1AC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK6", + "displayName": "OTG_HS_HCINTMSK6", + "description": "OTG_HS host channel-6 interrupt mask register", + "addressOffset": "0x1CC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK7", + "displayName": "OTG_HS_HCINTMSK7", + "description": "OTG_HS host channel-7 interrupt mask register", + "addressOffset": "0x1EC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK8", + "displayName": "OTG_HS_HCINTMSK8", + "description": "OTG_HS host channel-8 interrupt mask register", + "addressOffset": "0x20C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK9", + "displayName": "OTG_HS_HCINTMSK9", + "description": "OTG_HS host channel-9 interrupt mask register", + "addressOffset": "0x22C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK10", + "displayName": "OTG_HS_HCINTMSK10", + "description": "OTG_HS host channel-10 interrupt mask register", + "addressOffset": "0x24C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK11", + "displayName": "OTG_HS_HCINTMSK11", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x26C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ0", + "displayName": "OTG_HS_HCTSIZ0", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ1", + "displayName": "OTG_HS_HCTSIZ1", + "description": "OTG_HS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ2", + "displayName": "OTG_HS_HCTSIZ2", + "description": "OTG_HS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ3", + "displayName": "OTG_HS_HCTSIZ3", + "description": "OTG_HS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ4", + "displayName": "OTG_HS_HCTSIZ4", + "description": "OTG_HS host channel-4 transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ5", + "displayName": "OTG_HS_HCTSIZ5", + "description": "OTG_HS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ6", + "displayName": "OTG_HS_HCTSIZ6", + "description": "OTG_HS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ7", + "displayName": "OTG_HS_HCTSIZ7", + "description": "OTG_HS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ8", + "displayName": "OTG_HS_HCTSIZ8", + "description": "OTG_HS host channel-8 transfer size register", + "addressOffset": "0x210", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ9", + "displayName": "OTG_HS_HCTSIZ9", + "description": "OTG_HS host channel-9 transfer size register", + "addressOffset": "0x230", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ10", + "displayName": "OTG_HS_HCTSIZ10", + "description": "OTG_HS host channel-10 transfer size register", + "addressOffset": "0x250", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ11", + "displayName": "OTG_HS_HCTSIZ11", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x270", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCDMA0", + "displayName": "OTG_HS_HCDMA0", + "description": "OTG_HS host channel-0 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA1", + "displayName": "OTG_HS_HCDMA1", + "description": "OTG_HS host channel-1 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA2", + "displayName": "OTG_HS_HCDMA2", + "description": "OTG_HS host channel-2 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA3", + "displayName": "OTG_HS_HCDMA3", + "description": "OTG_HS host channel-3 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA4", + "displayName": "OTG_HS_HCDMA4", + "description": "OTG_HS host channel-4 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA5", + "displayName": "OTG_HS_HCDMA5", + "description": "OTG_HS host channel-5 DMA address register", + "addressOffset": "0x1B4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA6", + "displayName": "OTG_HS_HCDMA6", + "description": "OTG_HS host channel-6 DMA address register", + "addressOffset": "0x1D4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA7", + "displayName": "OTG_HS_HCDMA7", + "description": "OTG_HS host channel-7 DMA address register", + "addressOffset": "0x1F4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA8", + "displayName": "OTG_HS_HCDMA8", + "description": "OTG_HS host channel-8 DMA address register", + "addressOffset": "0x214", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA9", + "displayName": "OTG_HS_HCDMA9", + "description": "OTG_HS host channel-9 DMA address register", + "addressOffset": "0x234", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA10", + "displayName": "OTG_HS_HCDMA10", + "description": "OTG_HS host channel-10 DMA address register", + "addressOffset": "0x254", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA11", + "displayName": "OTG_HS_HCDMA11", + "description": "OTG_HS host channel-11 DMA address register", + "addressOffset": "0x274", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "OTG_HS_DEVICE", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_DCFG", + "displayName": "OTG_HS_DCFG", + "description": "OTG_HS device configuration register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Nonzero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic (micro)frame interval", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "PERSCHIVL", + "description": "Periodic scheduling interval", + "bitOffset": "24", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DCTL", + "displayName": "OTG_HS_DCTL", + "description": "OTG_HS device control register", + "addressOffset": "0x4", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DSTS", + "displayName": "OTG_HS_DSTS", + "description": "OTG_HS device status register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "OTG_HS_DIEPMSK", + "displayName": "OTG_HS_DIEPMSK", + "description": "OTG_HS device IN endpoint common interrupt mask register", + "addressOffset": "0x10", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPMSK", + "displayName": "OTG_HS_DOEPMSK", + "description": "OTG_HS device OUT endpoint common interrupt mask register", + "addressOffset": "0x14", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OPEM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BOIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DAINT", + "displayName": "OTG_HS_DAINT", + "description": "OTG_HS device all endpoints interrupt register", + "addressOffset": "0x18", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DAINTMSK", + "displayName": "OTG_HS_DAINTMSK", + "description": "OTG_HS all endpoints interrupt mask register", + "addressOffset": "0x1C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPM", + "description": "OUT EP interrupt mask bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSDIS", + "displayName": "OTG_HS_DVBUSDIS", + "description": "OTG_HS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSPULSE", + "displayName": "OTG_HS_DVBUSPULSE", + "description": "OTG_HS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "OTG_HS_DTHRCTL", + "displayName": "OTG_HS_DTHRCTL", + "description": "OTG_HS Device threshold control register", + "addressOffset": "0x30", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "NONISOTHREN", + "description": "Nonisochronous IN endpoints threshold enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ISOTHREN", + "description": "ISO IN endpoint threshold enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXTHRLEN", + "description": "Transmit threshold length", + "bitOffset": "2", + "bitWidth": "9" + }, + { + "name": "RXTHREN", + "description": "Receive threshold enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXTHRLEN", + "description": "Receive threshold length", + "bitOffset": "17", + "bitWidth": "9" + }, + { + "name": "ARPEN", + "description": "Arbiter parking enable", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEMPMSK", + "displayName": "OTG_HS_DIEPEMPMSK", + "description": "OTG_HS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DEACHINT", + "displayName": "OTG_HS_DEACHINT", + "description": "OTG_HS device each endpoint interrupt register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INT", + "description": "IN endpoint 1interrupt bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INT", + "description": "OUT endpoint 1 interrupt bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DEACHINTMSK", + "displayName": "OTG_HS_DEACHINTMSK", + "description": "OTG_HS device each endpoint interrupt register mask", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INTM", + "description": "IN Endpoint 1 interrupt mask bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INTM", + "description": "OUT Endpoint 1 interrupt mask bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEACHMSK1", + "displayName": "OTG_HS_DIEPEACHMSK1", + "description": "OTG_HS device each in endpoint-1 interrupt register", + "addressOffset": "0x40", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPEACHMSK1", + "displayName": "OTG_HS_DOEPEACHMSK1", + "description": "OTG_HS device each OUT endpoint-1 interrupt register", + "addressOffset": "0x80", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BERRM", + "description": "Bubble error interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "NYETM", + "description": "NYET interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL0", + "displayName": "OTG_HS_DIEPCTL0", + "description": "OTG device endpoint-0 control register", + "addressOffset": "0x100", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL1", + "displayName": "OTG_HS_DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL2", + "displayName": "OTG_HS_DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL3", + "displayName": "OTG_HS_DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL4", + "displayName": "OTG_HS_DIEPCTL4", + "description": "OTG device endpoint-4 control register", + "addressOffset": "0x180", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL5", + "displayName": "OTG_HS_DIEPCTL5", + "description": "OTG device endpoint-5 control register", + "addressOffset": "0x1A0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL6", + "displayName": "OTG_HS_DIEPCTL6", + "description": "OTG device endpoint-6 control register", + "addressOffset": "0x1C0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL7", + "displayName": "OTG_HS_DIEPCTL7", + "description": "OTG device endpoint-7 control register", + "addressOffset": "0x1E0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT0", + "displayName": "OTG_HS_DIEPINT0", + "description": "OTG device endpoint-0 interrupt register", + "addressOffset": "0x108", + "size": "32", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT1", + "displayName": "OTG_HS_DIEPINT1", + "description": "OTG device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT2", + "displayName": "OTG_HS_DIEPINT2", + "description": "OTG device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT3", + "displayName": "OTG_HS_DIEPINT3", + "description": "OTG device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT4", + "displayName": "OTG_HS_DIEPINT4", + "description": "OTG device endpoint-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT5", + "displayName": "OTG_HS_DIEPINT5", + "description": "OTG device endpoint-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT6", + "displayName": "OTG_HS_DIEPINT6", + "description": "OTG device endpoint-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT7", + "displayName": "OTG_HS_DIEPINT7", + "description": "OTG device endpoint-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ0", + "displayName": "OTG_HS_DIEPTSIZ0", + "description": "OTG_HS device IN endpoint 0 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA1", + "displayName": "OTG_HS_DIEPDMA1", + "description": "OTG_HS device endpoint-1 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA2", + "displayName": "OTG_HS_DIEPDMA2", + "description": "OTG_HS device endpoint-2 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA3", + "displayName": "OTG_HS_DIEPDMA3", + "description": "OTG_HS device endpoint-3 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA4", + "displayName": "OTG_HS_DIEPDMA4", + "description": "OTG_HS device endpoint-4 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA5", + "displayName": "OTG_HS_DIEPDMA5", + "description": "OTG_HS device endpoint-5 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS0", + "displayName": "OTG_HS_DTXFSTS0", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS1", + "displayName": "OTG_HS_DTXFSTS1", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS2", + "displayName": "OTG_HS_DTXFSTS2", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS3", + "displayName": "OTG_HS_DTXFSTS3", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS4", + "displayName": "OTG_HS_DTXFSTS4", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x198", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS5", + "displayName": "OTG_HS_DTXFSTS5", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x1B8", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ1", + "displayName": "OTG_HS_DIEPTSIZ1", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ2", + "displayName": "OTG_HS_DIEPTSIZ2", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ3", + "displayName": "OTG_HS_DIEPTSIZ3", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ4", + "displayName": "OTG_HS_DIEPTSIZ4", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ5", + "displayName": "OTG_HS_DIEPTSIZ5", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL0", + "displayName": "OTG_HS_DOEPCTL0", + "description": "OTG_HS device control OUT endpoint 0 control register", + "addressOffset": "0x300", + "size": "32", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL1", + "displayName": "OTG_HS_DOEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x320", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL2", + "displayName": "OTG_HS_DOEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x340", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL3", + "displayName": "OTG_HS_DOEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x360", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPINT0", + "displayName": "OTG_HS_DOEPINT0", + "description": "OTG_HS device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "32", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT1", + "displayName": "OTG_HS_DOEPINT1", + "description": "OTG_HS device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT2", + "displayName": "OTG_HS_DOEPINT2", + "description": "OTG_HS device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT3", + "displayName": "OTG_HS_DOEPINT3", + "description": "OTG_HS device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT4", + "displayName": "OTG_HS_DOEPINT4", + "description": "OTG_HS device endpoint-4 interrupt register", + "addressOffset": "0x388", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT5", + "displayName": "OTG_HS_DOEPINT5", + "description": "OTG_HS device endpoint-5 interrupt register", + "addressOffset": "0x3A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT6", + "displayName": "OTG_HS_DOEPINT6", + "description": "OTG_HS device endpoint-6 interrupt register", + "addressOffset": "0x3C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT7", + "displayName": "OTG_HS_DOEPINT7", + "description": "OTG_HS device endpoint-7 interrupt register", + "addressOffset": "0x3E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ0", + "displayName": "OTG_HS_DOEPTSIZ0", + "description": "OTG_HS device endpoint-1 transfer size register", + "addressOffset": "0x310", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ1", + "displayName": "OTG_HS_DOEPTSIZ1", + "description": "OTG_HS device endpoint-2 transfer size register", + "addressOffset": "0x330", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ2", + "displayName": "OTG_HS_DOEPTSIZ2", + "description": "OTG_HS device endpoint-3 transfer size register", + "addressOffset": "0x350", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ3", + "displayName": "OTG_HS_DOEPTSIZ3", + "description": "OTG_HS device endpoint-4 transfer size register", + "addressOffset": "0x370", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ4", + "displayName": "OTG_HS_DOEPTSIZ4", + "description": "OTG_HS device endpoint-5 transfer size register", + "addressOffset": "0x390", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_HS_PWRCLK", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x3F200", + "usage": "registers" + }, + { + "offset": "0x3F200", + "size": "0xFFFC1200", + "usage": "reserved" + } + ], + "registers": [ + { + "name": "OTG_HS_PCGCR", + "displayName": "OTG_HS_PCGCR", + "description": "Power and clock gating control register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1001", + "usage": "registers" + }, + { + "offset": "0x1001", + "size": "0xFFFFF3FF", + "usage": "reserved" + } + ], + "registers": [ + { + "name": "ICTR", + "displayName": "ICTR", + "description": "Interrupt Controller Type Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTLINESNUM", + "description": "Total number of interrupt lines in groups", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "STIR", + "displayName": "STIR", + "description": "Software Triggered Interrupt Register", + "addressOffset": "0xF00", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTID", + "description": "Interrupt to be triggered", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "ISER0", + "displayName": "ISER0", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER1", + "displayName": "ISER1", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER2", + "displayName": "ISER2", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER0", + "displayName": "ICER0", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER1", + "displayName": "ICER1", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER2", + "displayName": "ICER2", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR0", + "displayName": "ISPR0", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR1", + "displayName": "ISPR1", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR2", + "displayName": "ISPR2", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x208", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR0", + "displayName": "ICPR0", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR1", + "displayName": "ICPR1", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR2", + "displayName": "ICPR2", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR0", + "displayName": "IABR0", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR1", + "displayName": "IABR1", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR2", + "displayName": "IABR2", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register", + "addressOffset": "0x404", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register", + "addressOffset": "0x408", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register", + "addressOffset": "0x40C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register", + "addressOffset": "0x410", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register", + "addressOffset": "0x414", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register", + "addressOffset": "0x418", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register", + "addressOffset": "0x41C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR8", + "displayName": "IPR8", + "description": "Interrupt Priority Register", + "addressOffset": "0x420", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR9", + "displayName": "IPR9", + "description": "Interrupt Priority Register", + "addressOffset": "0x424", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR10", + "displayName": "IPR10", + "description": "Interrupt Priority Register", + "addressOffset": "0x428", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR11", + "displayName": "IPR11", + "description": "Interrupt Priority Register", + "addressOffset": "0x42C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR12", + "displayName": "IPR12", + "description": "Interrupt Priority Register", + "addressOffset": "0x430", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR13", + "displayName": "IPR13", + "description": "Interrupt Priority Register", + "addressOffset": "0x434", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR14", + "displayName": "IPR14", + "description": "Interrupt Priority Register", + "addressOffset": "0x438", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR15", + "displayName": "IPR15", + "description": "Interrupt Priority Register", + "addressOffset": "0x43C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR16", + "displayName": "IPR16", + "description": "Interrupt Priority Register", + "addressOffset": "0x440", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR17", + "displayName": "IPR17", + "description": "Interrupt Priority Register", + "addressOffset": "0x444", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR18", + "displayName": "IPR18", + "description": "Interrupt Priority Register", + "addressOffset": "0x448", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR19", + "displayName": "IPR19", + "description": "Interrupt Priority Register", + "addressOffset": "0x44C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/adc1.c b/gnu-mcu-eclipse/devices/support/STM32F40x/adc1.c new file mode 100644 index 0000000000..193cf76928 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/adc1.c @@ -0,0 +1,366 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smpr1 = cm_object_get_child_by_name(obj, "SMPR1"); + state->u.f4.reg.smpr2 = cm_object_get_child_by_name(obj, "SMPR2"); + state->u.f4.reg.jofr1 = cm_object_get_child_by_name(obj, "JOFR1"); + state->u.f4.reg.jofr2 = cm_object_get_child_by_name(obj, "JOFR2"); + state->u.f4.reg.jofr3 = cm_object_get_child_by_name(obj, "JOFR3"); + state->u.f4.reg.jofr4 = cm_object_get_child_by_name(obj, "JOFR4"); + state->u.f4.reg.htr = cm_object_get_child_by_name(obj, "HTR"); + state->u.f4.reg.ltr = cm_object_get_child_by_name(obj, "LTR"); + state->u.f4.reg.sqr1 = cm_object_get_child_by_name(obj, "SQR1"); + state->u.f4.reg.sqr2 = cm_object_get_child_by_name(obj, "SQR2"); + state->u.f4.reg.sqr3 = cm_object_get_child_by_name(obj, "SQR3"); + state->u.f4.reg.jsqr = cm_object_get_child_by_name(obj, "JSQR"); + state->u.f4.reg.jdr1 = cm_object_get_child_by_name(obj, "JDR1"); + state->u.f4.reg.jdr2 = cm_object_get_child_by_name(obj, "JDR2"); + state->u.f4.reg.jdr3 = cm_object_get_child_by_name(obj, "JDR3"); + state->u.f4.reg.jdr4 = cm_object_get_child_by_name(obj, "JDR4"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // SR bitfields. + state->u.f4.fld.sr.awd = cm_object_get_child_by_name(state->u.f4.reg.sr, "AWD"); + state->u.f4.fld.sr.eoc = cm_object_get_child_by_name(state->u.f4.reg.sr, "EOC"); + state->u.f4.fld.sr.jeoc = cm_object_get_child_by_name(state->u.f4.reg.sr, "JEOC"); + state->u.f4.fld.sr.jstrt = cm_object_get_child_by_name(state->u.f4.reg.sr, "JSTRT"); + state->u.f4.fld.sr.strt = cm_object_get_child_by_name(state->u.f4.reg.sr, "STRT"); + state->u.f4.fld.sr.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OVR"); + + // CR1 bitfields. + state->u.f4.fld.cr1.awdch = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDCH"); + state->u.f4.fld.cr1.eocie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "EOCIE"); + state->u.f4.fld.cr1.awdie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDIE"); + state->u.f4.fld.cr1.jeocie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JEOCIE"); + state->u.f4.fld.cr1.scan = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SCAN"); + state->u.f4.fld.cr1.awdsgl = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDSGL"); + state->u.f4.fld.cr1.jauto = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JAUTO"); + state->u.f4.fld.cr1.discen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DISCEN"); + state->u.f4.fld.cr1.jdiscen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JDISCEN"); + state->u.f4.fld.cr1.discnum = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DISCNUM"); + state->u.f4.fld.cr1.jawden = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JAWDEN"); + state->u.f4.fld.cr1.awden = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDEN"); + state->u.f4.fld.cr1.res = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RES"); + state->u.f4.fld.cr1.ovrie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVRIE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.adon = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADON"); + state->u.f4.fld.cr2.cont = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CONT"); + state->u.f4.fld.cr2.dma = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DMA"); + state->u.f4.fld.cr2.dds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DDS"); + state->u.f4.fld.cr2.eocs = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EOCS"); + state->u.f4.fld.cr2.align = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ALIGN"); + state->u.f4.fld.cr2.jextsel = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JEXTSEL"); + state->u.f4.fld.cr2.jexten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JEXTEN"); + state->u.f4.fld.cr2.jswstart = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JSWSTART"); + state->u.f4.fld.cr2.extsel = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EXTSEL"); + state->u.f4.fld.cr2.exten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EXTEN"); + state->u.f4.fld.cr2.swstart = cm_object_get_child_by_name(state->u.f4.reg.cr2, "SWSTART"); + + // SMPR1 bitfields. + state->u.f4.fld.smpr1.smpx_x = cm_object_get_child_by_name(state->u.f4.reg.smpr1, "SMPx_x"); + + // SMPR2 bitfields. + state->u.f4.fld.smpr2.smpx_x = cm_object_get_child_by_name(state->u.f4.reg.smpr2, "SMPx_x"); + + // JOFR1 bitfields. + state->u.f4.fld.jofr1.joffset1 = cm_object_get_child_by_name(state->u.f4.reg.jofr1, "JOFFSET1"); + + // JOFR2 bitfields. + state->u.f4.fld.jofr2.joffset2 = cm_object_get_child_by_name(state->u.f4.reg.jofr2, "JOFFSET2"); + + // JOFR3 bitfields. + state->u.f4.fld.jofr3.joffset3 = cm_object_get_child_by_name(state->u.f4.reg.jofr3, "JOFFSET3"); + + // JOFR4 bitfields. + state->u.f4.fld.jofr4.joffset4 = cm_object_get_child_by_name(state->u.f4.reg.jofr4, "JOFFSET4"); + + // HTR bitfields. + state->u.f4.fld.htr.ht = cm_object_get_child_by_name(state->u.f4.reg.htr, "HT"); + + // LTR bitfields. + state->u.f4.fld.ltr.lt = cm_object_get_child_by_name(state->u.f4.reg.ltr, "LT"); + + // SQR1 bitfields. + state->u.f4.fld.sqr1.sq13 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ13"); + state->u.f4.fld.sqr1.sq14 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ14"); + state->u.f4.fld.sqr1.sq15 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ15"); + state->u.f4.fld.sqr1.sq16 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ16"); + state->u.f4.fld.sqr1.l = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "L"); + + // SQR2 bitfields. + state->u.f4.fld.sqr2.sq7 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ7"); + state->u.f4.fld.sqr2.sq8 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ8"); + state->u.f4.fld.sqr2.sq9 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ9"); + state->u.f4.fld.sqr2.sq10 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ10"); + state->u.f4.fld.sqr2.sq11 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ11"); + state->u.f4.fld.sqr2.sq12 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ12"); + + // SQR3 bitfields. + state->u.f4.fld.sqr3.sq1 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ1"); + state->u.f4.fld.sqr3.sq2 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ2"); + state->u.f4.fld.sqr3.sq3 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ3"); + state->u.f4.fld.sqr3.sq4 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ4"); + state->u.f4.fld.sqr3.sq5 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ5"); + state->u.f4.fld.sqr3.sq6 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ6"); + + // JSQR bitfields. + state->u.f4.fld.jsqr.jsq1 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ1"); + state->u.f4.fld.jsqr.jsq2 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ2"); + state->u.f4.fld.jsqr.jsq3 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ3"); + state->u.f4.fld.jsqr.jsq4 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ4"); + state->u.f4.fld.jsqr.jl = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JL"); + + // JDR1 bitfields. + state->u.f4.fld.jdr1.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr1, "JDATA"); + + // JDR2 bitfields. + state->u.f4.fld.jdr2.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr2, "JDATA"); + + // JDR3 bitfields. + state->u.f4.fld.jdr3.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr3, "JDATA"); + + // JDR4 bitfields. + state->u.f4.fld.jdr4.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr4, "JDATA"); + + // DR bitfields. + state->u.f4.fld.dr.data = cm_object_get_child_by_name(state->u.f4.reg.dr, "DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_ADC_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC%dEN", + 1 + state->port_index - STM32_PORT_ADC1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/adc1.h b/gnu-mcu-eclipse/devices/support/STM32F40x/adc1.h new file mode 100644 index 0000000000..29cf7373ae --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/adc1.h @@ -0,0 +1,278 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_ADC1, + STM32_PORT_ADC2, + STM32_PORT_ADC3, + STM32_PORT_ADC_UNDEFINED = 0xFF, +} stm32_adc_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_adc_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 ADC (Analog-to-digital converter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *cr1; // 0x4 (Control register 1) + Object *cr2; // 0x8 (Control register 2) + Object *smpr1; // 0xC (Sample time register 1) + Object *smpr2; // 0x10 (Sample time register 2) + Object *jofr1; // 0x14 (Injected channel data offset register x) + Object *jofr2; // 0x18 (Injected channel data offset register x) + Object *jofr3; // 0x1C (Injected channel data offset register x) + Object *jofr4; // 0x20 (Injected channel data offset register x) + Object *htr; // 0x24 (Watchdog higher threshold register) + Object *ltr; // 0x28 (Watchdog lower threshold register) + Object *sqr1; // 0x2C (Regular sequence register 1) + Object *sqr2; // 0x30 (Regular sequence register 2) + Object *sqr3; // 0x34 (Regular sequence register 3) + Object *jsqr; // 0x38 (Injected sequence register) + Object *jdr1; // 0x3C (Injected data register x) + Object *jdr2; // 0x40 (Injected data register x) + Object *jdr3; // 0x44 (Injected data register x) + Object *jdr4; // 0x48 (Injected data register x) + Object *dr; // 0x4C (Regular data register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *awd; // [0:0] Analog watchdog flag + Object *eoc; // [1:1] Regular channel end of conversion + Object *jeoc; // [2:2] Injected channel end of conversion + Object *jstrt; // [3:3] Injected channel start flag + Object *strt; // [4:4] Regular channel start flag + Object *ovr; // [5:5] Overrun + } sr; + + // CR1 (Control register 1) bitfields. + struct { + Object *awdch; // [0:4] Analog watchdog channel select bits + Object *eocie; // [5:5] Interrupt enable for EOC + Object *awdie; // [6:6] Analog watchdog interrupt enable + Object *jeocie; // [7:7] Interrupt enable for injected channels + Object *scan; // [8:8] Scan mode + Object *awdsgl; // [9:9] Enable the watchdog on a single channel in scan mode + Object *jauto; // [10:10] Automatic injected group conversion + Object *discen; // [11:11] Discontinuous mode on regular channels + Object *jdiscen; // [12:12] Discontinuous mode on injected channels + Object *discnum; // [13:15] Discontinuous mode channel count + Object *jawden; // [22:22] Analog watchdog enable on injected channels + Object *awden; // [23:23] Analog watchdog enable on regular channels + Object *res; // [24:25] Resolution + Object *ovrie; // [26:26] Overrun interrupt enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *adon; // [0:0] A/D Converter ON / OFF + Object *cont; // [1:1] Continuous conversion + Object *dma; // [8:8] Direct memory access mode (for single ADC mode) + Object *dds; // [9:9] DMA disable selection (for single ADC mode) + Object *eocs; // [10:10] End of conversion selection + Object *align; // [11:11] Data alignment + Object *jextsel; // [16:19] External event select for injected group + Object *jexten; // [20:21] External trigger enable for injected channels + Object *jswstart; // [22:22] Start conversion of injected channels + Object *extsel; // [24:27] External event select for regular group + Object *exten; // [28:29] External trigger enable for regular channels + Object *swstart; // [30:30] Start conversion of regular channels + } cr2; + + // SMPR1 (Sample time register 1) bitfields. + struct { + Object *smpx_x; // [0:31] Sample time bits + } smpr1; + + // SMPR2 (Sample time register 2) bitfields. + struct { + Object *smpx_x; // [0:31] Sample time bits + } smpr2; + + // JOFR1 (Injected channel data offset register x) bitfields. + struct { + Object *joffset1; // [0:11] Data offset for injected channel x + } jofr1; + + // JOFR2 (Injected channel data offset register x) bitfields. + struct { + Object *joffset2; // [0:11] Data offset for injected channel x + } jofr2; + + // JOFR3 (Injected channel data offset register x) bitfields. + struct { + Object *joffset3; // [0:11] Data offset for injected channel x + } jofr3; + + // JOFR4 (Injected channel data offset register x) bitfields. + struct { + Object *joffset4; // [0:11] Data offset for injected channel x + } jofr4; + + // HTR (Watchdog higher threshold register) bitfields. + struct { + Object *ht; // [0:11] Analog watchdog higher threshold + } htr; + + // LTR (Watchdog lower threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + } ltr; + + // SQR1 (Regular sequence register 1) bitfields. + struct { + Object *sq13; // [0:4] 13th conversion in regular sequence + Object *sq14; // [5:9] 14th conversion in regular sequence + Object *sq15; // [10:14] 15th conversion in regular sequence + Object *sq16; // [15:19] 16th conversion in regular sequence + Object *l; // [20:23] Regular channel sequence length + } sqr1; + + // SQR2 (Regular sequence register 2) bitfields. + struct { + Object *sq7; // [0:4] 7th conversion in regular sequence + Object *sq8; // [5:9] 8th conversion in regular sequence + Object *sq9; // [10:14] 9th conversion in regular sequence + Object *sq10; // [15:19] 10th conversion in regular sequence + Object *sq11; // [20:24] 11th conversion in regular sequence + Object *sq12; // [25:29] 12th conversion in regular sequence + } sqr2; + + // SQR3 (Regular sequence register 3) bitfields. + struct { + Object *sq1; // [0:4] 1st conversion in regular sequence + Object *sq2; // [5:9] 2nd conversion in regular sequence + Object *sq3; // [10:14] 3rd conversion in regular sequence + Object *sq4; // [15:19] 4th conversion in regular sequence + Object *sq5; // [20:24] 5th conversion in regular sequence + Object *sq6; // [25:29] 6th conversion in regular sequence + } sqr3; + + // JSQR (Injected sequence register) bitfields. + struct { + Object *jsq1; // [0:4] 1st conversion in injected sequence + Object *jsq2; // [5:9] 2nd conversion in injected sequence + Object *jsq3; // [10:14] 3rd conversion in injected sequence + Object *jsq4; // [15:19] 4th conversion in injected sequence + Object *jl; // [20:21] Injected sequence length + } jsqr; + + // JDR1 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr1; + + // JDR2 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr2; + + // JDR3 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr3; + + // JDR4 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr4; + + // DR (Regular data register) bitfields. + struct { + Object *data; // [0:15] Regular data + } dr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/c_adc.c b/gnu-mcu-eclipse/devices/support/STM32F40x/c_adc.c new file mode 100644 index 0000000000..83f4f1a289 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/c_adc.c @@ -0,0 +1,270 @@ +/* + * STM32 - C_ADC (Common ADC registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_c_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f4.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + state->u.f4.reg.cdr = cm_object_get_child_by_name(obj, "CDR"); + + + // CSR bitfields. + state->u.f4.fld.csr.awd1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD1"); + state->u.f4.fld.csr.eoc1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC1"); + state->u.f4.fld.csr.jeoc1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC1"); + state->u.f4.fld.csr.jstrt1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT1"); + state->u.f4.fld.csr.strt1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT1"); + state->u.f4.fld.csr.ovr1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR1"); + state->u.f4.fld.csr.awd2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD2"); + state->u.f4.fld.csr.eoc2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC2"); + state->u.f4.fld.csr.jeoc2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC2"); + state->u.f4.fld.csr.jstrt2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT2"); + state->u.f4.fld.csr.strt2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT2"); + state->u.f4.fld.csr.ovr2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR2"); + state->u.f4.fld.csr.awd3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD3"); + state->u.f4.fld.csr.eoc3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC3"); + state->u.f4.fld.csr.jeoc3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC3"); + state->u.f4.fld.csr.jstrt3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT3"); + state->u.f4.fld.csr.strt3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT3"); + state->u.f4.fld.csr.ovr3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR3"); + + // CCR bitfields. + state->u.f4.fld.ccr.mult = cm_object_get_child_by_name(state->u.f4.reg.ccr, "MULT"); + state->u.f4.fld.ccr.delay = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DELAY"); + state->u.f4.fld.ccr.dds = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DDS"); + state->u.f4.fld.ccr.dma = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DMA"); + state->u.f4.fld.ccr.adcpre = cm_object_get_child_by_name(state->u.f4.reg.ccr, "ADCPRE"); + state->u.f4.fld.ccr.vbate = cm_object_get_child_by_name(state->u.f4.reg.ccr, "VBATE"); + state->u.f4.fld.ccr.tsvrefe = cm_object_get_child_by_name(state->u.f4.reg.ccr, "TSVREFE"); + + // CDR bitfields. + state->u.f4.fld.cdr.data1 = cm_object_get_child_by_name(state->u.f4.reg.cdr, "DATA1"); + state->u.f4.fld.cdr.data2 = cm_object_get_child_by_name(state->u.f4.reg.cdr, "DATA2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_c_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_c_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_c_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_c_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_c_adc_is_enabled(Object *obj) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_c_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32C_ADCState *state = STM32_C_ADC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_c_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_C_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32C_ADCState *state = STM32_C_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "C_ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_c_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_c_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_c_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_c_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_c_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/C_ADCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_c_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_C_ADC); +} + +static void stm32_c_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_c_adc_reset_callback; + dc->realize = stm32_c_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_c_adc_is_enabled; +} + +static const TypeInfo stm32_c_adc_type_info = { + .name = TYPE_STM32_C_ADC, + .parent = TYPE_STM32_C_ADC_PARENT, + .instance_init = stm32_c_adc_instance_init_callback, + .instance_size = sizeof(STM32C_ADCState), + .class_init = stm32_c_adc_class_init_callback, + .class_size = sizeof(STM32C_ADCClass) }; + +static void stm32_c_adc_register_types(void) +{ + type_register_static(&stm32_c_adc_type_info); +} + +type_init(stm32_c_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/c_adc.h b/gnu-mcu-eclipse/devices/support/STM32F40x/c_adc.h new file mode 100644 index 0000000000..deae314e3a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/c_adc.h @@ -0,0 +1,141 @@ +/* + * STM32 - C_ADC (Common ADC registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_C_ADC_H_ +#define STM32_C_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_C_ADC DEVICE_PATH_STM32 "C_ADC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_C_ADC TYPE_STM32_PREFIX "c_adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_C_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32C_ADCParentClass; +typedef PeripheralState STM32C_ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_C_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32C_ADCClass, (obj), TYPE_STM32_C_ADC) +#define STM32_C_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32C_ADCClass, (klass), TYPE_STM32_C_ADC) + +typedef struct { + // private: + STM32C_ADCParentClass parent_class; + // public: + + // None, so far. +} STM32C_ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_C_ADC_STATE(obj) \ + OBJECT_CHECK(STM32C_ADCState, (obj), TYPE_STM32_C_ADC) + +typedef struct { + // private: + STM32C_ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 C_ADC (Common ADC registers) registers. + struct { + Object *csr; // 0x0 (ADC Common status register) + Object *ccr; // 0x4 (ADC common control register) + Object *cdr; // 0x8 (ADC common regular data register for dual and triple modes) + } reg; + + struct { + + // CSR (ADC Common status register) bitfields. + struct { + Object *awd1; // [0:0] Analog watchdog flag of ADC 1 + Object *eoc1; // [1:1] End of conversion of ADC 1 + Object *jeoc1; // [2:2] Injected channel end of conversion of ADC 1 + Object *jstrt1; // [3:3] Injected channel Start flag of ADC 1 + Object *strt1; // [4:4] Regular channel Start flag of ADC 1 + Object *ovr1; // [5:5] Overrun flag of ADC 1 + Object *awd2; // [8:8] Analog watchdog flag of ADC 2 + Object *eoc2; // [9:9] End of conversion of ADC 2 + Object *jeoc2; // [10:10] Injected channel end of conversion of ADC 2 + Object *jstrt2; // [11:11] Injected channel Start flag of ADC 2 + Object *strt2; // [12:12] Regular channel Start flag of ADC 2 + Object *ovr2; // [13:13] Overrun flag of ADC 2 + Object *awd3; // [16:16] Analog watchdog flag of ADC 3 + Object *eoc3; // [17:17] End of conversion of ADC 3 + Object *jeoc3; // [18:18] Injected channel end of conversion of ADC 3 + Object *jstrt3; // [19:19] Injected channel Start flag of ADC 3 + Object *strt3; // [20:20] Regular channel Start flag of ADC 3 + Object *ovr3; // [21:21] Overrun flag of ADC3 + } csr; + + // CCR (ADC common control register) bitfields. + struct { + Object *mult; // [0:4] Multi ADC mode selection + Object *delay; // [8:11] Delay between 2 sampling phases + Object *dds; // [13:13] DMA disable selection for multi-ADC mode + Object *dma; // [14:15] Direct memory access mode for multi ADC mode + Object *adcpre; // [16:17] ADC prescaler + Object *vbate; // [22:22] VBAT enable + Object *tsvrefe; // [23:23] Temperature sensor and VREFINT enable + } ccr; + + // CDR (ADC common regular data register for dual and triple modes) bitfields. + struct { + Object *data1; // [0:15] 1st data item of a pair of regular conversions + Object *data2; // [16:31] 2nd data item of a pair of regular conversions + } cdr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32C_ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_C_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/can1.c b/gnu-mcu-eclipse/devices/support/STM32F40x/can1.c new file mode 100644 index 0000000000..e2d8bf5ff8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/can1.c @@ -0,0 +1,2565 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_can_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.mcr = cm_object_get_child_by_name(obj, "MCR"); + state->u.f4.reg.msr = cm_object_get_child_by_name(obj, "MSR"); + state->u.f4.reg.tsr = cm_object_get_child_by_name(obj, "TSR"); + state->u.f4.reg.rf0r = cm_object_get_child_by_name(obj, "RF0R"); + state->u.f4.reg.rf1r = cm_object_get_child_by_name(obj, "RF1R"); + state->u.f4.reg.ier = cm_object_get_child_by_name(obj, "IER"); + state->u.f4.reg.esr = cm_object_get_child_by_name(obj, "ESR"); + state->u.f4.reg.btr = cm_object_get_child_by_name(obj, "BTR"); + state->u.f4.reg.ti0r = cm_object_get_child_by_name(obj, "TI0R"); + state->u.f4.reg.tdt0r = cm_object_get_child_by_name(obj, "TDT0R"); + state->u.f4.reg.tdl0r = cm_object_get_child_by_name(obj, "TDL0R"); + state->u.f4.reg.tdh0r = cm_object_get_child_by_name(obj, "TDH0R"); + state->u.f4.reg.ti1r = cm_object_get_child_by_name(obj, "TI1R"); + state->u.f4.reg.tdt1r = cm_object_get_child_by_name(obj, "TDT1R"); + state->u.f4.reg.tdl1r = cm_object_get_child_by_name(obj, "TDL1R"); + state->u.f4.reg.tdh1r = cm_object_get_child_by_name(obj, "TDH1R"); + state->u.f4.reg.ti2r = cm_object_get_child_by_name(obj, "TI2R"); + state->u.f4.reg.tdt2r = cm_object_get_child_by_name(obj, "TDT2R"); + state->u.f4.reg.tdl2r = cm_object_get_child_by_name(obj, "TDL2R"); + state->u.f4.reg.tdh2r = cm_object_get_child_by_name(obj, "TDH2R"); + state->u.f4.reg.ri0r = cm_object_get_child_by_name(obj, "RI0R"); + state->u.f4.reg.rdt0r = cm_object_get_child_by_name(obj, "RDT0R"); + state->u.f4.reg.rdl0r = cm_object_get_child_by_name(obj, "RDL0R"); + state->u.f4.reg.rdh0r = cm_object_get_child_by_name(obj, "RDH0R"); + state->u.f4.reg.ri1r = cm_object_get_child_by_name(obj, "RI1R"); + state->u.f4.reg.rdt1r = cm_object_get_child_by_name(obj, "RDT1R"); + state->u.f4.reg.rdl1r = cm_object_get_child_by_name(obj, "RDL1R"); + state->u.f4.reg.rdh1r = cm_object_get_child_by_name(obj, "RDH1R"); + state->u.f4.reg.fmr = cm_object_get_child_by_name(obj, "FMR"); + state->u.f4.reg.fm1r = cm_object_get_child_by_name(obj, "FM1R"); + state->u.f4.reg.fs1r = cm_object_get_child_by_name(obj, "FS1R"); + state->u.f4.reg.ffa1r = cm_object_get_child_by_name(obj, "FFA1R"); + state->u.f4.reg.fa1r = cm_object_get_child_by_name(obj, "FA1R"); + state->u.f4.reg.f0r1 = cm_object_get_child_by_name(obj, "F0R1"); + state->u.f4.reg.f0r2 = cm_object_get_child_by_name(obj, "F0R2"); + state->u.f4.reg.f1r1 = cm_object_get_child_by_name(obj, "F1R1"); + state->u.f4.reg.f1r2 = cm_object_get_child_by_name(obj, "F1R2"); + state->u.f4.reg.f2r1 = cm_object_get_child_by_name(obj, "F2R1"); + state->u.f4.reg.f2r2 = cm_object_get_child_by_name(obj, "F2R2"); + state->u.f4.reg.f3r1 = cm_object_get_child_by_name(obj, "F3R1"); + state->u.f4.reg.f3r2 = cm_object_get_child_by_name(obj, "F3R2"); + state->u.f4.reg.f4r1 = cm_object_get_child_by_name(obj, "F4R1"); + state->u.f4.reg.f4r2 = cm_object_get_child_by_name(obj, "F4R2"); + state->u.f4.reg.f5r1 = cm_object_get_child_by_name(obj, "F5R1"); + state->u.f4.reg.f5r2 = cm_object_get_child_by_name(obj, "F5R2"); + state->u.f4.reg.f6r1 = cm_object_get_child_by_name(obj, "F6R1"); + state->u.f4.reg.f6r2 = cm_object_get_child_by_name(obj, "F6R2"); + state->u.f4.reg.f7r1 = cm_object_get_child_by_name(obj, "F7R1"); + state->u.f4.reg.f7r2 = cm_object_get_child_by_name(obj, "F7R2"); + state->u.f4.reg.f8r1 = cm_object_get_child_by_name(obj, "F8R1"); + state->u.f4.reg.f8r2 = cm_object_get_child_by_name(obj, "F8R2"); + state->u.f4.reg.f9r1 = cm_object_get_child_by_name(obj, "F9R1"); + state->u.f4.reg.f9r2 = cm_object_get_child_by_name(obj, "F9R2"); + state->u.f4.reg.f10r1 = cm_object_get_child_by_name(obj, "F10R1"); + state->u.f4.reg.f10r2 = cm_object_get_child_by_name(obj, "F10R2"); + state->u.f4.reg.f11r1 = cm_object_get_child_by_name(obj, "F11R1"); + state->u.f4.reg.f11r2 = cm_object_get_child_by_name(obj, "F11R2"); + state->u.f4.reg.f12r1 = cm_object_get_child_by_name(obj, "F12R1"); + state->u.f4.reg.f12r2 = cm_object_get_child_by_name(obj, "F12R2"); + state->u.f4.reg.f13r1 = cm_object_get_child_by_name(obj, "F13R1"); + state->u.f4.reg.f13r2 = cm_object_get_child_by_name(obj, "F13R2"); + state->u.f4.reg.f14r1 = cm_object_get_child_by_name(obj, "F14R1"); + state->u.f4.reg.f14r2 = cm_object_get_child_by_name(obj, "F14R2"); + state->u.f4.reg.f15r1 = cm_object_get_child_by_name(obj, "F15R1"); + state->u.f4.reg.f15r2 = cm_object_get_child_by_name(obj, "F15R2"); + state->u.f4.reg.f16r1 = cm_object_get_child_by_name(obj, "F16R1"); + state->u.f4.reg.f16r2 = cm_object_get_child_by_name(obj, "F16R2"); + state->u.f4.reg.f17r1 = cm_object_get_child_by_name(obj, "F17R1"); + state->u.f4.reg.f17r2 = cm_object_get_child_by_name(obj, "F17R2"); + state->u.f4.reg.f18r1 = cm_object_get_child_by_name(obj, "F18R1"); + state->u.f4.reg.f18r2 = cm_object_get_child_by_name(obj, "F18R2"); + state->u.f4.reg.f19r1 = cm_object_get_child_by_name(obj, "F19R1"); + state->u.f4.reg.f19r2 = cm_object_get_child_by_name(obj, "F19R2"); + state->u.f4.reg.f20r1 = cm_object_get_child_by_name(obj, "F20R1"); + state->u.f4.reg.f20r2 = cm_object_get_child_by_name(obj, "F20R2"); + state->u.f4.reg.f21r1 = cm_object_get_child_by_name(obj, "F21R1"); + state->u.f4.reg.f21r2 = cm_object_get_child_by_name(obj, "F21R2"); + state->u.f4.reg.f22r1 = cm_object_get_child_by_name(obj, "F22R1"); + state->u.f4.reg.f22r2 = cm_object_get_child_by_name(obj, "F22R2"); + state->u.f4.reg.f23r1 = cm_object_get_child_by_name(obj, "F23R1"); + state->u.f4.reg.f23r2 = cm_object_get_child_by_name(obj, "F23R2"); + state->u.f4.reg.f24r1 = cm_object_get_child_by_name(obj, "F24R1"); + state->u.f4.reg.f24r2 = cm_object_get_child_by_name(obj, "F24R2"); + state->u.f4.reg.f25r1 = cm_object_get_child_by_name(obj, "F25R1"); + state->u.f4.reg.f25r2 = cm_object_get_child_by_name(obj, "F25R2"); + state->u.f4.reg.f26r1 = cm_object_get_child_by_name(obj, "F26R1"); + state->u.f4.reg.f26r2 = cm_object_get_child_by_name(obj, "F26R2"); + state->u.f4.reg.f27r1 = cm_object_get_child_by_name(obj, "F27R1"); + state->u.f4.reg.f27r2 = cm_object_get_child_by_name(obj, "F27R2"); + + + // MCR bitfields. + state->u.f4.fld.mcr.inrq = cm_object_get_child_by_name(state->u.f4.reg.mcr, "INRQ"); + state->u.f4.fld.mcr.sleep = cm_object_get_child_by_name(state->u.f4.reg.mcr, "SLEEP"); + state->u.f4.fld.mcr.txfp = cm_object_get_child_by_name(state->u.f4.reg.mcr, "TXFP"); + state->u.f4.fld.mcr.rflm = cm_object_get_child_by_name(state->u.f4.reg.mcr, "RFLM"); + state->u.f4.fld.mcr.nart = cm_object_get_child_by_name(state->u.f4.reg.mcr, "NART"); + state->u.f4.fld.mcr.awum = cm_object_get_child_by_name(state->u.f4.reg.mcr, "AWUM"); + state->u.f4.fld.mcr.abom = cm_object_get_child_by_name(state->u.f4.reg.mcr, "ABOM"); + state->u.f4.fld.mcr.ttcm = cm_object_get_child_by_name(state->u.f4.reg.mcr, "TTCM"); + state->u.f4.fld.mcr.reset = cm_object_get_child_by_name(state->u.f4.reg.mcr, "RESET"); + state->u.f4.fld.mcr.dbf = cm_object_get_child_by_name(state->u.f4.reg.mcr, "DBF"); + + // MSR bitfields. + state->u.f4.fld.msr.inak = cm_object_get_child_by_name(state->u.f4.reg.msr, "INAK"); + state->u.f4.fld.msr.slak = cm_object_get_child_by_name(state->u.f4.reg.msr, "SLAK"); + state->u.f4.fld.msr.erri = cm_object_get_child_by_name(state->u.f4.reg.msr, "ERRI"); + state->u.f4.fld.msr.wkui = cm_object_get_child_by_name(state->u.f4.reg.msr, "WKUI"); + state->u.f4.fld.msr.slaki = cm_object_get_child_by_name(state->u.f4.reg.msr, "SLAKI"); + state->u.f4.fld.msr.txm = cm_object_get_child_by_name(state->u.f4.reg.msr, "TXM"); + state->u.f4.fld.msr.rxm = cm_object_get_child_by_name(state->u.f4.reg.msr, "RXM"); + state->u.f4.fld.msr.samp = cm_object_get_child_by_name(state->u.f4.reg.msr, "SAMP"); + state->u.f4.fld.msr.rx = cm_object_get_child_by_name(state->u.f4.reg.msr, "RX"); + + // TSR bitfields. + state->u.f4.fld.tsr.rqcp0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "RQCP0"); + state->u.f4.fld.tsr.txok0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TXOK0"); + state->u.f4.fld.tsr.alst0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ALST0"); + state->u.f4.fld.tsr.terr0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TERR0"); + state->u.f4.fld.tsr.abrq0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ABRQ0"); + state->u.f4.fld.tsr.rqcp1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "RQCP1"); + state->u.f4.fld.tsr.txok1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TXOK1"); + state->u.f4.fld.tsr.alst1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ALST1"); + state->u.f4.fld.tsr.terr1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TERR1"); + state->u.f4.fld.tsr.abrq1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ABRQ1"); + state->u.f4.fld.tsr.rqcp2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "RQCP2"); + state->u.f4.fld.tsr.txok2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TXOK2"); + state->u.f4.fld.tsr.alst2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ALST2"); + state->u.f4.fld.tsr.terr2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TERR2"); + state->u.f4.fld.tsr.abrq2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ABRQ2"); + state->u.f4.fld.tsr.code = cm_object_get_child_by_name(state->u.f4.reg.tsr, "CODE"); + state->u.f4.fld.tsr.tme0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TME0"); + state->u.f4.fld.tsr.tme1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TME1"); + state->u.f4.fld.tsr.tme2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TME2"); + state->u.f4.fld.tsr.low0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "LOW0"); + state->u.f4.fld.tsr.low1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "LOW1"); + state->u.f4.fld.tsr.low2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "LOW2"); + + // RF0R bitfields. + state->u.f4.fld.rf0r.fmp0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "FMP0"); + state->u.f4.fld.rf0r.full0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "FULL0"); + state->u.f4.fld.rf0r.fovr0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "FOVR0"); + state->u.f4.fld.rf0r.rfom0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "RFOM0"); + + // RF1R bitfields. + state->u.f4.fld.rf1r.fmp1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "FMP1"); + state->u.f4.fld.rf1r.full1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "FULL1"); + state->u.f4.fld.rf1r.fovr1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "FOVR1"); + state->u.f4.fld.rf1r.rfom1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "RFOM1"); + + // IER bitfields. + state->u.f4.fld.ier.tmeie = cm_object_get_child_by_name(state->u.f4.reg.ier, "TMEIE"); + state->u.f4.fld.ier.fmpie0 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FMPIE0"); + state->u.f4.fld.ier.ffie0 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FFIE0"); + state->u.f4.fld.ier.fovie0 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FOVIE0"); + state->u.f4.fld.ier.fmpie1 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FMPIE1"); + state->u.f4.fld.ier.ffie1 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FFIE1"); + state->u.f4.fld.ier.fovie1 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FOVIE1"); + state->u.f4.fld.ier.ewgie = cm_object_get_child_by_name(state->u.f4.reg.ier, "EWGIE"); + state->u.f4.fld.ier.epvie = cm_object_get_child_by_name(state->u.f4.reg.ier, "EPVIE"); + state->u.f4.fld.ier.bofie = cm_object_get_child_by_name(state->u.f4.reg.ier, "BOFIE"); + state->u.f4.fld.ier.lecie = cm_object_get_child_by_name(state->u.f4.reg.ier, "LECIE"); + state->u.f4.fld.ier.errie = cm_object_get_child_by_name(state->u.f4.reg.ier, "ERRIE"); + state->u.f4.fld.ier.wkuie = cm_object_get_child_by_name(state->u.f4.reg.ier, "WKUIE"); + state->u.f4.fld.ier.slkie = cm_object_get_child_by_name(state->u.f4.reg.ier, "SLKIE"); + + // ESR bitfields. + state->u.f4.fld.esr.ewgf = cm_object_get_child_by_name(state->u.f4.reg.esr, "EWGF"); + state->u.f4.fld.esr.epvf = cm_object_get_child_by_name(state->u.f4.reg.esr, "EPVF"); + state->u.f4.fld.esr.boff = cm_object_get_child_by_name(state->u.f4.reg.esr, "BOFF"); + state->u.f4.fld.esr.lec = cm_object_get_child_by_name(state->u.f4.reg.esr, "LEC"); + state->u.f4.fld.esr.tec = cm_object_get_child_by_name(state->u.f4.reg.esr, "TEC"); + state->u.f4.fld.esr.rec = cm_object_get_child_by_name(state->u.f4.reg.esr, "REC"); + + // BTR bitfields. + state->u.f4.fld.btr.brp = cm_object_get_child_by_name(state->u.f4.reg.btr, "BRP"); + state->u.f4.fld.btr.ts1 = cm_object_get_child_by_name(state->u.f4.reg.btr, "TS1"); + state->u.f4.fld.btr.ts2 = cm_object_get_child_by_name(state->u.f4.reg.btr, "TS2"); + state->u.f4.fld.btr.sjw = cm_object_get_child_by_name(state->u.f4.reg.btr, "SJW"); + state->u.f4.fld.btr.lbkm = cm_object_get_child_by_name(state->u.f4.reg.btr, "LBKM"); + state->u.f4.fld.btr.silm = cm_object_get_child_by_name(state->u.f4.reg.btr, "SILM"); + + // TI0R bitfields. + state->u.f4.fld.ti0r.txrq = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "TXRQ"); + state->u.f4.fld.ti0r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "RTR"); + state->u.f4.fld.ti0r.ide = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "IDE"); + state->u.f4.fld.ti0r.exid = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "EXID"); + state->u.f4.fld.ti0r.stid = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "STID"); + + // TDT0R bitfields. + state->u.f4.fld.tdt0r.dlc = cm_object_get_child_by_name(state->u.f4.reg.tdt0r, "DLC"); + state->u.f4.fld.tdt0r.tgt = cm_object_get_child_by_name(state->u.f4.reg.tdt0r, "TGT"); + state->u.f4.fld.tdt0r.time = cm_object_get_child_by_name(state->u.f4.reg.tdt0r, "TIME"); + + // TDL0R bitfields. + state->u.f4.fld.tdl0r.data0 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA0"); + state->u.f4.fld.tdl0r.data1 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA1"); + state->u.f4.fld.tdl0r.data2 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA2"); + state->u.f4.fld.tdl0r.data3 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA3"); + + // TDH0R bitfields. + state->u.f4.fld.tdh0r.data4 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA4"); + state->u.f4.fld.tdh0r.data5 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA5"); + state->u.f4.fld.tdh0r.data6 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA6"); + state->u.f4.fld.tdh0r.data7 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA7"); + + // TI1R bitfields. + state->u.f4.fld.ti1r.txrq = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "TXRQ"); + state->u.f4.fld.ti1r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "RTR"); + state->u.f4.fld.ti1r.ide = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "IDE"); + state->u.f4.fld.ti1r.exid = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "EXID"); + state->u.f4.fld.ti1r.stid = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "STID"); + + // TDT1R bitfields. + state->u.f4.fld.tdt1r.dlc = cm_object_get_child_by_name(state->u.f4.reg.tdt1r, "DLC"); + state->u.f4.fld.tdt1r.tgt = cm_object_get_child_by_name(state->u.f4.reg.tdt1r, "TGT"); + state->u.f4.fld.tdt1r.time = cm_object_get_child_by_name(state->u.f4.reg.tdt1r, "TIME"); + + // TDL1R bitfields. + state->u.f4.fld.tdl1r.data0 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA0"); + state->u.f4.fld.tdl1r.data1 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA1"); + state->u.f4.fld.tdl1r.data2 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA2"); + state->u.f4.fld.tdl1r.data3 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA3"); + + // TDH1R bitfields. + state->u.f4.fld.tdh1r.data4 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA4"); + state->u.f4.fld.tdh1r.data5 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA5"); + state->u.f4.fld.tdh1r.data6 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA6"); + state->u.f4.fld.tdh1r.data7 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA7"); + + // TI2R bitfields. + state->u.f4.fld.ti2r.txrq = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "TXRQ"); + state->u.f4.fld.ti2r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "RTR"); + state->u.f4.fld.ti2r.ide = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "IDE"); + state->u.f4.fld.ti2r.exid = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "EXID"); + state->u.f4.fld.ti2r.stid = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "STID"); + + // TDT2R bitfields. + state->u.f4.fld.tdt2r.dlc = cm_object_get_child_by_name(state->u.f4.reg.tdt2r, "DLC"); + state->u.f4.fld.tdt2r.tgt = cm_object_get_child_by_name(state->u.f4.reg.tdt2r, "TGT"); + state->u.f4.fld.tdt2r.time = cm_object_get_child_by_name(state->u.f4.reg.tdt2r, "TIME"); + + // TDL2R bitfields. + state->u.f4.fld.tdl2r.data0 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA0"); + state->u.f4.fld.tdl2r.data1 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA1"); + state->u.f4.fld.tdl2r.data2 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA2"); + state->u.f4.fld.tdl2r.data3 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA3"); + + // TDH2R bitfields. + state->u.f4.fld.tdh2r.data4 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA4"); + state->u.f4.fld.tdh2r.data5 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA5"); + state->u.f4.fld.tdh2r.data6 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA6"); + state->u.f4.fld.tdh2r.data7 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA7"); + + // RI0R bitfields. + state->u.f4.fld.ri0r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "RTR"); + state->u.f4.fld.ri0r.ide = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "IDE"); + state->u.f4.fld.ri0r.exid = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "EXID"); + state->u.f4.fld.ri0r.stid = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "STID"); + + // RDT0R bitfields. + state->u.f4.fld.rdt0r.dlc = cm_object_get_child_by_name(state->u.f4.reg.rdt0r, "DLC"); + state->u.f4.fld.rdt0r.fmi = cm_object_get_child_by_name(state->u.f4.reg.rdt0r, "FMI"); + state->u.f4.fld.rdt0r.time = cm_object_get_child_by_name(state->u.f4.reg.rdt0r, "TIME"); + + // RDL0R bitfields. + state->u.f4.fld.rdl0r.data0 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA0"); + state->u.f4.fld.rdl0r.data1 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA1"); + state->u.f4.fld.rdl0r.data2 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA2"); + state->u.f4.fld.rdl0r.data3 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA3"); + + // RDH0R bitfields. + state->u.f4.fld.rdh0r.data4 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA4"); + state->u.f4.fld.rdh0r.data5 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA5"); + state->u.f4.fld.rdh0r.data6 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA6"); + state->u.f4.fld.rdh0r.data7 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA7"); + + // RI1R bitfields. + state->u.f4.fld.ri1r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "RTR"); + state->u.f4.fld.ri1r.ide = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "IDE"); + state->u.f4.fld.ri1r.exid = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "EXID"); + state->u.f4.fld.ri1r.stid = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "STID"); + + // RDT1R bitfields. + state->u.f4.fld.rdt1r.dlc = cm_object_get_child_by_name(state->u.f4.reg.rdt1r, "DLC"); + state->u.f4.fld.rdt1r.fmi = cm_object_get_child_by_name(state->u.f4.reg.rdt1r, "FMI"); + state->u.f4.fld.rdt1r.time = cm_object_get_child_by_name(state->u.f4.reg.rdt1r, "TIME"); + + // RDL1R bitfields. + state->u.f4.fld.rdl1r.data0 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA0"); + state->u.f4.fld.rdl1r.data1 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA1"); + state->u.f4.fld.rdl1r.data2 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA2"); + state->u.f4.fld.rdl1r.data3 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA3"); + + // RDH1R bitfields. + state->u.f4.fld.rdh1r.data4 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA4"); + state->u.f4.fld.rdh1r.data5 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA5"); + state->u.f4.fld.rdh1r.data6 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA6"); + state->u.f4.fld.rdh1r.data7 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA7"); + + // FMR bitfields. + state->u.f4.fld.fmr.finit = cm_object_get_child_by_name(state->u.f4.reg.fmr, "FINIT"); + state->u.f4.fld.fmr.can2sb = cm_object_get_child_by_name(state->u.f4.reg.fmr, "CAN2SB"); + + // FM1R bitfields. + state->u.f4.fld.fm1r.fbm0 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM0"); + state->u.f4.fld.fm1r.fbm1 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM1"); + state->u.f4.fld.fm1r.fbm2 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM2"); + state->u.f4.fld.fm1r.fbm3 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM3"); + state->u.f4.fld.fm1r.fbm4 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM4"); + state->u.f4.fld.fm1r.fbm5 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM5"); + state->u.f4.fld.fm1r.fbm6 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM6"); + state->u.f4.fld.fm1r.fbm7 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM7"); + state->u.f4.fld.fm1r.fbm8 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM8"); + state->u.f4.fld.fm1r.fbm9 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM9"); + state->u.f4.fld.fm1r.fbm10 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM10"); + state->u.f4.fld.fm1r.fbm11 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM11"); + state->u.f4.fld.fm1r.fbm12 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM12"); + state->u.f4.fld.fm1r.fbm13 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM13"); + state->u.f4.fld.fm1r.fbm14 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM14"); + state->u.f4.fld.fm1r.fbm15 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM15"); + state->u.f4.fld.fm1r.fbm16 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM16"); + state->u.f4.fld.fm1r.fbm17 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM17"); + state->u.f4.fld.fm1r.fbm18 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM18"); + state->u.f4.fld.fm1r.fbm19 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM19"); + state->u.f4.fld.fm1r.fbm20 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM20"); + state->u.f4.fld.fm1r.fbm21 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM21"); + state->u.f4.fld.fm1r.fbm22 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM22"); + state->u.f4.fld.fm1r.fbm23 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM23"); + state->u.f4.fld.fm1r.fbm24 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM24"); + state->u.f4.fld.fm1r.fbm25 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM25"); + state->u.f4.fld.fm1r.fbm26 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM26"); + state->u.f4.fld.fm1r.fbm27 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM27"); + + // FS1R bitfields. + state->u.f4.fld.fs1r.fsc0 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC0"); + state->u.f4.fld.fs1r.fsc1 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC1"); + state->u.f4.fld.fs1r.fsc2 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC2"); + state->u.f4.fld.fs1r.fsc3 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC3"); + state->u.f4.fld.fs1r.fsc4 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC4"); + state->u.f4.fld.fs1r.fsc5 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC5"); + state->u.f4.fld.fs1r.fsc6 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC6"); + state->u.f4.fld.fs1r.fsc7 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC7"); + state->u.f4.fld.fs1r.fsc8 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC8"); + state->u.f4.fld.fs1r.fsc9 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC9"); + state->u.f4.fld.fs1r.fsc10 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC10"); + state->u.f4.fld.fs1r.fsc11 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC11"); + state->u.f4.fld.fs1r.fsc12 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC12"); + state->u.f4.fld.fs1r.fsc13 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC13"); + state->u.f4.fld.fs1r.fsc14 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC14"); + state->u.f4.fld.fs1r.fsc15 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC15"); + state->u.f4.fld.fs1r.fsc16 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC16"); + state->u.f4.fld.fs1r.fsc17 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC17"); + state->u.f4.fld.fs1r.fsc18 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC18"); + state->u.f4.fld.fs1r.fsc19 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC19"); + state->u.f4.fld.fs1r.fsc20 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC20"); + state->u.f4.fld.fs1r.fsc21 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC21"); + state->u.f4.fld.fs1r.fsc22 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC22"); + state->u.f4.fld.fs1r.fsc23 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC23"); + state->u.f4.fld.fs1r.fsc24 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC24"); + state->u.f4.fld.fs1r.fsc25 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC25"); + state->u.f4.fld.fs1r.fsc26 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC26"); + state->u.f4.fld.fs1r.fsc27 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC27"); + + // FFA1R bitfields. + state->u.f4.fld.ffa1r.ffa0 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA0"); + state->u.f4.fld.ffa1r.ffa1 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA1"); + state->u.f4.fld.ffa1r.ffa2 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA2"); + state->u.f4.fld.ffa1r.ffa3 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA3"); + state->u.f4.fld.ffa1r.ffa4 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA4"); + state->u.f4.fld.ffa1r.ffa5 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA5"); + state->u.f4.fld.ffa1r.ffa6 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA6"); + state->u.f4.fld.ffa1r.ffa7 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA7"); + state->u.f4.fld.ffa1r.ffa8 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA8"); + state->u.f4.fld.ffa1r.ffa9 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA9"); + state->u.f4.fld.ffa1r.ffa10 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA10"); + state->u.f4.fld.ffa1r.ffa11 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA11"); + state->u.f4.fld.ffa1r.ffa12 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA12"); + state->u.f4.fld.ffa1r.ffa13 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA13"); + state->u.f4.fld.ffa1r.ffa14 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA14"); + state->u.f4.fld.ffa1r.ffa15 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA15"); + state->u.f4.fld.ffa1r.ffa16 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA16"); + state->u.f4.fld.ffa1r.ffa17 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA17"); + state->u.f4.fld.ffa1r.ffa18 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA18"); + state->u.f4.fld.ffa1r.ffa19 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA19"); + state->u.f4.fld.ffa1r.ffa20 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA20"); + state->u.f4.fld.ffa1r.ffa21 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA21"); + state->u.f4.fld.ffa1r.ffa22 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA22"); + state->u.f4.fld.ffa1r.ffa23 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA23"); + state->u.f4.fld.ffa1r.ffa24 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA24"); + state->u.f4.fld.ffa1r.ffa25 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA25"); + state->u.f4.fld.ffa1r.ffa26 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA26"); + state->u.f4.fld.ffa1r.ffa27 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA27"); + + // FA1R bitfields. + state->u.f4.fld.fa1r.fact0 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT0"); + state->u.f4.fld.fa1r.fact1 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT1"); + state->u.f4.fld.fa1r.fact2 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT2"); + state->u.f4.fld.fa1r.fact3 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT3"); + state->u.f4.fld.fa1r.fact4 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT4"); + state->u.f4.fld.fa1r.fact5 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT5"); + state->u.f4.fld.fa1r.fact6 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT6"); + state->u.f4.fld.fa1r.fact7 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT7"); + state->u.f4.fld.fa1r.fact8 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT8"); + state->u.f4.fld.fa1r.fact9 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT9"); + state->u.f4.fld.fa1r.fact10 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT10"); + state->u.f4.fld.fa1r.fact11 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT11"); + state->u.f4.fld.fa1r.fact12 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT12"); + state->u.f4.fld.fa1r.fact13 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT13"); + state->u.f4.fld.fa1r.fact14 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT14"); + state->u.f4.fld.fa1r.fact15 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT15"); + state->u.f4.fld.fa1r.fact16 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT16"); + state->u.f4.fld.fa1r.fact17 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT17"); + state->u.f4.fld.fa1r.fact18 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT18"); + state->u.f4.fld.fa1r.fact19 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT19"); + state->u.f4.fld.fa1r.fact20 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT20"); + state->u.f4.fld.fa1r.fact21 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT21"); + state->u.f4.fld.fa1r.fact22 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT22"); + state->u.f4.fld.fa1r.fact23 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT23"); + state->u.f4.fld.fa1r.fact24 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT24"); + state->u.f4.fld.fa1r.fact25 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT25"); + state->u.f4.fld.fa1r.fact26 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT26"); + state->u.f4.fld.fa1r.fact27 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT27"); + + // F0R1 bitfields. + state->u.f4.fld.f0r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB0"); + state->u.f4.fld.f0r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB1"); + state->u.f4.fld.f0r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB2"); + state->u.f4.fld.f0r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB3"); + state->u.f4.fld.f0r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB4"); + state->u.f4.fld.f0r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB5"); + state->u.f4.fld.f0r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB6"); + state->u.f4.fld.f0r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB7"); + state->u.f4.fld.f0r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB8"); + state->u.f4.fld.f0r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB9"); + state->u.f4.fld.f0r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB10"); + state->u.f4.fld.f0r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB11"); + state->u.f4.fld.f0r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB12"); + state->u.f4.fld.f0r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB13"); + state->u.f4.fld.f0r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB14"); + state->u.f4.fld.f0r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB15"); + state->u.f4.fld.f0r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB16"); + state->u.f4.fld.f0r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB17"); + state->u.f4.fld.f0r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB18"); + state->u.f4.fld.f0r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB19"); + state->u.f4.fld.f0r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB20"); + state->u.f4.fld.f0r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB21"); + state->u.f4.fld.f0r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB22"); + state->u.f4.fld.f0r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB23"); + state->u.f4.fld.f0r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB24"); + state->u.f4.fld.f0r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB25"); + state->u.f4.fld.f0r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB26"); + state->u.f4.fld.f0r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB27"); + state->u.f4.fld.f0r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB28"); + state->u.f4.fld.f0r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB29"); + state->u.f4.fld.f0r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB30"); + state->u.f4.fld.f0r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB31"); + + // F0R2 bitfields. + state->u.f4.fld.f0r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB0"); + state->u.f4.fld.f0r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB1"); + state->u.f4.fld.f0r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB2"); + state->u.f4.fld.f0r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB3"); + state->u.f4.fld.f0r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB4"); + state->u.f4.fld.f0r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB5"); + state->u.f4.fld.f0r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB6"); + state->u.f4.fld.f0r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB7"); + state->u.f4.fld.f0r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB8"); + state->u.f4.fld.f0r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB9"); + state->u.f4.fld.f0r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB10"); + state->u.f4.fld.f0r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB11"); + state->u.f4.fld.f0r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB12"); + state->u.f4.fld.f0r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB13"); + state->u.f4.fld.f0r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB14"); + state->u.f4.fld.f0r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB15"); + state->u.f4.fld.f0r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB16"); + state->u.f4.fld.f0r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB17"); + state->u.f4.fld.f0r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB18"); + state->u.f4.fld.f0r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB19"); + state->u.f4.fld.f0r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB20"); + state->u.f4.fld.f0r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB21"); + state->u.f4.fld.f0r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB22"); + state->u.f4.fld.f0r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB23"); + state->u.f4.fld.f0r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB24"); + state->u.f4.fld.f0r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB25"); + state->u.f4.fld.f0r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB26"); + state->u.f4.fld.f0r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB27"); + state->u.f4.fld.f0r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB28"); + state->u.f4.fld.f0r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB29"); + state->u.f4.fld.f0r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB30"); + state->u.f4.fld.f0r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB31"); + + // F1R1 bitfields. + state->u.f4.fld.f1r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB0"); + state->u.f4.fld.f1r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB1"); + state->u.f4.fld.f1r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB2"); + state->u.f4.fld.f1r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB3"); + state->u.f4.fld.f1r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB4"); + state->u.f4.fld.f1r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB5"); + state->u.f4.fld.f1r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB6"); + state->u.f4.fld.f1r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB7"); + state->u.f4.fld.f1r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB8"); + state->u.f4.fld.f1r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB9"); + state->u.f4.fld.f1r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB10"); + state->u.f4.fld.f1r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB11"); + state->u.f4.fld.f1r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB12"); + state->u.f4.fld.f1r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB13"); + state->u.f4.fld.f1r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB14"); + state->u.f4.fld.f1r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB15"); + state->u.f4.fld.f1r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB16"); + state->u.f4.fld.f1r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB17"); + state->u.f4.fld.f1r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB18"); + state->u.f4.fld.f1r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB19"); + state->u.f4.fld.f1r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB20"); + state->u.f4.fld.f1r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB21"); + state->u.f4.fld.f1r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB22"); + state->u.f4.fld.f1r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB23"); + state->u.f4.fld.f1r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB24"); + state->u.f4.fld.f1r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB25"); + state->u.f4.fld.f1r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB26"); + state->u.f4.fld.f1r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB27"); + state->u.f4.fld.f1r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB28"); + state->u.f4.fld.f1r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB29"); + state->u.f4.fld.f1r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB30"); + state->u.f4.fld.f1r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB31"); + + // F1R2 bitfields. + state->u.f4.fld.f1r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB0"); + state->u.f4.fld.f1r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB1"); + state->u.f4.fld.f1r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB2"); + state->u.f4.fld.f1r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB3"); + state->u.f4.fld.f1r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB4"); + state->u.f4.fld.f1r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB5"); + state->u.f4.fld.f1r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB6"); + state->u.f4.fld.f1r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB7"); + state->u.f4.fld.f1r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB8"); + state->u.f4.fld.f1r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB9"); + state->u.f4.fld.f1r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB10"); + state->u.f4.fld.f1r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB11"); + state->u.f4.fld.f1r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB12"); + state->u.f4.fld.f1r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB13"); + state->u.f4.fld.f1r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB14"); + state->u.f4.fld.f1r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB15"); + state->u.f4.fld.f1r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB16"); + state->u.f4.fld.f1r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB17"); + state->u.f4.fld.f1r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB18"); + state->u.f4.fld.f1r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB19"); + state->u.f4.fld.f1r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB20"); + state->u.f4.fld.f1r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB21"); + state->u.f4.fld.f1r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB22"); + state->u.f4.fld.f1r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB23"); + state->u.f4.fld.f1r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB24"); + state->u.f4.fld.f1r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB25"); + state->u.f4.fld.f1r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB26"); + state->u.f4.fld.f1r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB27"); + state->u.f4.fld.f1r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB28"); + state->u.f4.fld.f1r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB29"); + state->u.f4.fld.f1r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB30"); + state->u.f4.fld.f1r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB31"); + + // F2R1 bitfields. + state->u.f4.fld.f2r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB0"); + state->u.f4.fld.f2r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB1"); + state->u.f4.fld.f2r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB2"); + state->u.f4.fld.f2r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB3"); + state->u.f4.fld.f2r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB4"); + state->u.f4.fld.f2r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB5"); + state->u.f4.fld.f2r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB6"); + state->u.f4.fld.f2r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB7"); + state->u.f4.fld.f2r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB8"); + state->u.f4.fld.f2r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB9"); + state->u.f4.fld.f2r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB10"); + state->u.f4.fld.f2r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB11"); + state->u.f4.fld.f2r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB12"); + state->u.f4.fld.f2r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB13"); + state->u.f4.fld.f2r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB14"); + state->u.f4.fld.f2r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB15"); + state->u.f4.fld.f2r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB16"); + state->u.f4.fld.f2r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB17"); + state->u.f4.fld.f2r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB18"); + state->u.f4.fld.f2r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB19"); + state->u.f4.fld.f2r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB20"); + state->u.f4.fld.f2r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB21"); + state->u.f4.fld.f2r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB22"); + state->u.f4.fld.f2r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB23"); + state->u.f4.fld.f2r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB24"); + state->u.f4.fld.f2r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB25"); + state->u.f4.fld.f2r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB26"); + state->u.f4.fld.f2r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB27"); + state->u.f4.fld.f2r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB28"); + state->u.f4.fld.f2r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB29"); + state->u.f4.fld.f2r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB30"); + state->u.f4.fld.f2r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB31"); + + // F2R2 bitfields. + state->u.f4.fld.f2r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB0"); + state->u.f4.fld.f2r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB1"); + state->u.f4.fld.f2r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB2"); + state->u.f4.fld.f2r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB3"); + state->u.f4.fld.f2r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB4"); + state->u.f4.fld.f2r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB5"); + state->u.f4.fld.f2r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB6"); + state->u.f4.fld.f2r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB7"); + state->u.f4.fld.f2r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB8"); + state->u.f4.fld.f2r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB9"); + state->u.f4.fld.f2r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB10"); + state->u.f4.fld.f2r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB11"); + state->u.f4.fld.f2r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB12"); + state->u.f4.fld.f2r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB13"); + state->u.f4.fld.f2r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB14"); + state->u.f4.fld.f2r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB15"); + state->u.f4.fld.f2r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB16"); + state->u.f4.fld.f2r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB17"); + state->u.f4.fld.f2r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB18"); + state->u.f4.fld.f2r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB19"); + state->u.f4.fld.f2r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB20"); + state->u.f4.fld.f2r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB21"); + state->u.f4.fld.f2r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB22"); + state->u.f4.fld.f2r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB23"); + state->u.f4.fld.f2r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB24"); + state->u.f4.fld.f2r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB25"); + state->u.f4.fld.f2r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB26"); + state->u.f4.fld.f2r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB27"); + state->u.f4.fld.f2r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB28"); + state->u.f4.fld.f2r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB29"); + state->u.f4.fld.f2r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB30"); + state->u.f4.fld.f2r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB31"); + + // F3R1 bitfields. + state->u.f4.fld.f3r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB0"); + state->u.f4.fld.f3r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB1"); + state->u.f4.fld.f3r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB2"); + state->u.f4.fld.f3r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB3"); + state->u.f4.fld.f3r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB4"); + state->u.f4.fld.f3r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB5"); + state->u.f4.fld.f3r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB6"); + state->u.f4.fld.f3r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB7"); + state->u.f4.fld.f3r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB8"); + state->u.f4.fld.f3r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB9"); + state->u.f4.fld.f3r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB10"); + state->u.f4.fld.f3r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB11"); + state->u.f4.fld.f3r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB12"); + state->u.f4.fld.f3r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB13"); + state->u.f4.fld.f3r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB14"); + state->u.f4.fld.f3r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB15"); + state->u.f4.fld.f3r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB16"); + state->u.f4.fld.f3r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB17"); + state->u.f4.fld.f3r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB18"); + state->u.f4.fld.f3r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB19"); + state->u.f4.fld.f3r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB20"); + state->u.f4.fld.f3r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB21"); + state->u.f4.fld.f3r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB22"); + state->u.f4.fld.f3r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB23"); + state->u.f4.fld.f3r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB24"); + state->u.f4.fld.f3r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB25"); + state->u.f4.fld.f3r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB26"); + state->u.f4.fld.f3r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB27"); + state->u.f4.fld.f3r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB28"); + state->u.f4.fld.f3r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB29"); + state->u.f4.fld.f3r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB30"); + state->u.f4.fld.f3r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB31"); + + // F3R2 bitfields. + state->u.f4.fld.f3r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB0"); + state->u.f4.fld.f3r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB1"); + state->u.f4.fld.f3r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB2"); + state->u.f4.fld.f3r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB3"); + state->u.f4.fld.f3r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB4"); + state->u.f4.fld.f3r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB5"); + state->u.f4.fld.f3r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB6"); + state->u.f4.fld.f3r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB7"); + state->u.f4.fld.f3r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB8"); + state->u.f4.fld.f3r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB9"); + state->u.f4.fld.f3r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB10"); + state->u.f4.fld.f3r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB11"); + state->u.f4.fld.f3r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB12"); + state->u.f4.fld.f3r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB13"); + state->u.f4.fld.f3r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB14"); + state->u.f4.fld.f3r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB15"); + state->u.f4.fld.f3r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB16"); + state->u.f4.fld.f3r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB17"); + state->u.f4.fld.f3r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB18"); + state->u.f4.fld.f3r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB19"); + state->u.f4.fld.f3r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB20"); + state->u.f4.fld.f3r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB21"); + state->u.f4.fld.f3r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB22"); + state->u.f4.fld.f3r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB23"); + state->u.f4.fld.f3r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB24"); + state->u.f4.fld.f3r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB25"); + state->u.f4.fld.f3r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB26"); + state->u.f4.fld.f3r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB27"); + state->u.f4.fld.f3r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB28"); + state->u.f4.fld.f3r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB29"); + state->u.f4.fld.f3r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB30"); + state->u.f4.fld.f3r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB31"); + + // F4R1 bitfields. + state->u.f4.fld.f4r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB0"); + state->u.f4.fld.f4r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB1"); + state->u.f4.fld.f4r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB2"); + state->u.f4.fld.f4r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB3"); + state->u.f4.fld.f4r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB4"); + state->u.f4.fld.f4r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB5"); + state->u.f4.fld.f4r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB6"); + state->u.f4.fld.f4r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB7"); + state->u.f4.fld.f4r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB8"); + state->u.f4.fld.f4r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB9"); + state->u.f4.fld.f4r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB10"); + state->u.f4.fld.f4r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB11"); + state->u.f4.fld.f4r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB12"); + state->u.f4.fld.f4r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB13"); + state->u.f4.fld.f4r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB14"); + state->u.f4.fld.f4r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB15"); + state->u.f4.fld.f4r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB16"); + state->u.f4.fld.f4r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB17"); + state->u.f4.fld.f4r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB18"); + state->u.f4.fld.f4r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB19"); + state->u.f4.fld.f4r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB20"); + state->u.f4.fld.f4r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB21"); + state->u.f4.fld.f4r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB22"); + state->u.f4.fld.f4r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB23"); + state->u.f4.fld.f4r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB24"); + state->u.f4.fld.f4r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB25"); + state->u.f4.fld.f4r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB26"); + state->u.f4.fld.f4r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB27"); + state->u.f4.fld.f4r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB28"); + state->u.f4.fld.f4r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB29"); + state->u.f4.fld.f4r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB30"); + state->u.f4.fld.f4r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB31"); + + // F4R2 bitfields. + state->u.f4.fld.f4r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB0"); + state->u.f4.fld.f4r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB1"); + state->u.f4.fld.f4r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB2"); + state->u.f4.fld.f4r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB3"); + state->u.f4.fld.f4r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB4"); + state->u.f4.fld.f4r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB5"); + state->u.f4.fld.f4r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB6"); + state->u.f4.fld.f4r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB7"); + state->u.f4.fld.f4r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB8"); + state->u.f4.fld.f4r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB9"); + state->u.f4.fld.f4r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB10"); + state->u.f4.fld.f4r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB11"); + state->u.f4.fld.f4r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB12"); + state->u.f4.fld.f4r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB13"); + state->u.f4.fld.f4r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB14"); + state->u.f4.fld.f4r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB15"); + state->u.f4.fld.f4r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB16"); + state->u.f4.fld.f4r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB17"); + state->u.f4.fld.f4r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB18"); + state->u.f4.fld.f4r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB19"); + state->u.f4.fld.f4r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB20"); + state->u.f4.fld.f4r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB21"); + state->u.f4.fld.f4r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB22"); + state->u.f4.fld.f4r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB23"); + state->u.f4.fld.f4r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB24"); + state->u.f4.fld.f4r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB25"); + state->u.f4.fld.f4r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB26"); + state->u.f4.fld.f4r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB27"); + state->u.f4.fld.f4r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB28"); + state->u.f4.fld.f4r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB29"); + state->u.f4.fld.f4r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB30"); + state->u.f4.fld.f4r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB31"); + + // F5R1 bitfields. + state->u.f4.fld.f5r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB0"); + state->u.f4.fld.f5r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB1"); + state->u.f4.fld.f5r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB2"); + state->u.f4.fld.f5r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB3"); + state->u.f4.fld.f5r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB4"); + state->u.f4.fld.f5r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB5"); + state->u.f4.fld.f5r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB6"); + state->u.f4.fld.f5r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB7"); + state->u.f4.fld.f5r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB8"); + state->u.f4.fld.f5r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB9"); + state->u.f4.fld.f5r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB10"); + state->u.f4.fld.f5r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB11"); + state->u.f4.fld.f5r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB12"); + state->u.f4.fld.f5r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB13"); + state->u.f4.fld.f5r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB14"); + state->u.f4.fld.f5r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB15"); + state->u.f4.fld.f5r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB16"); + state->u.f4.fld.f5r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB17"); + state->u.f4.fld.f5r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB18"); + state->u.f4.fld.f5r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB19"); + state->u.f4.fld.f5r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB20"); + state->u.f4.fld.f5r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB21"); + state->u.f4.fld.f5r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB22"); + state->u.f4.fld.f5r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB23"); + state->u.f4.fld.f5r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB24"); + state->u.f4.fld.f5r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB25"); + state->u.f4.fld.f5r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB26"); + state->u.f4.fld.f5r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB27"); + state->u.f4.fld.f5r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB28"); + state->u.f4.fld.f5r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB29"); + state->u.f4.fld.f5r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB30"); + state->u.f4.fld.f5r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB31"); + + // F5R2 bitfields. + state->u.f4.fld.f5r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB0"); + state->u.f4.fld.f5r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB1"); + state->u.f4.fld.f5r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB2"); + state->u.f4.fld.f5r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB3"); + state->u.f4.fld.f5r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB4"); + state->u.f4.fld.f5r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB5"); + state->u.f4.fld.f5r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB6"); + state->u.f4.fld.f5r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB7"); + state->u.f4.fld.f5r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB8"); + state->u.f4.fld.f5r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB9"); + state->u.f4.fld.f5r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB10"); + state->u.f4.fld.f5r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB11"); + state->u.f4.fld.f5r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB12"); + state->u.f4.fld.f5r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB13"); + state->u.f4.fld.f5r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB14"); + state->u.f4.fld.f5r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB15"); + state->u.f4.fld.f5r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB16"); + state->u.f4.fld.f5r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB17"); + state->u.f4.fld.f5r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB18"); + state->u.f4.fld.f5r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB19"); + state->u.f4.fld.f5r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB20"); + state->u.f4.fld.f5r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB21"); + state->u.f4.fld.f5r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB22"); + state->u.f4.fld.f5r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB23"); + state->u.f4.fld.f5r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB24"); + state->u.f4.fld.f5r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB25"); + state->u.f4.fld.f5r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB26"); + state->u.f4.fld.f5r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB27"); + state->u.f4.fld.f5r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB28"); + state->u.f4.fld.f5r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB29"); + state->u.f4.fld.f5r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB30"); + state->u.f4.fld.f5r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB31"); + + // F6R1 bitfields. + state->u.f4.fld.f6r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB0"); + state->u.f4.fld.f6r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB1"); + state->u.f4.fld.f6r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB2"); + state->u.f4.fld.f6r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB3"); + state->u.f4.fld.f6r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB4"); + state->u.f4.fld.f6r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB5"); + state->u.f4.fld.f6r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB6"); + state->u.f4.fld.f6r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB7"); + state->u.f4.fld.f6r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB8"); + state->u.f4.fld.f6r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB9"); + state->u.f4.fld.f6r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB10"); + state->u.f4.fld.f6r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB11"); + state->u.f4.fld.f6r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB12"); + state->u.f4.fld.f6r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB13"); + state->u.f4.fld.f6r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB14"); + state->u.f4.fld.f6r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB15"); + state->u.f4.fld.f6r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB16"); + state->u.f4.fld.f6r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB17"); + state->u.f4.fld.f6r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB18"); + state->u.f4.fld.f6r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB19"); + state->u.f4.fld.f6r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB20"); + state->u.f4.fld.f6r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB21"); + state->u.f4.fld.f6r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB22"); + state->u.f4.fld.f6r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB23"); + state->u.f4.fld.f6r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB24"); + state->u.f4.fld.f6r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB25"); + state->u.f4.fld.f6r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB26"); + state->u.f4.fld.f6r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB27"); + state->u.f4.fld.f6r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB28"); + state->u.f4.fld.f6r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB29"); + state->u.f4.fld.f6r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB30"); + state->u.f4.fld.f6r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB31"); + + // F6R2 bitfields. + state->u.f4.fld.f6r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB0"); + state->u.f4.fld.f6r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB1"); + state->u.f4.fld.f6r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB2"); + state->u.f4.fld.f6r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB3"); + state->u.f4.fld.f6r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB4"); + state->u.f4.fld.f6r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB5"); + state->u.f4.fld.f6r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB6"); + state->u.f4.fld.f6r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB7"); + state->u.f4.fld.f6r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB8"); + state->u.f4.fld.f6r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB9"); + state->u.f4.fld.f6r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB10"); + state->u.f4.fld.f6r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB11"); + state->u.f4.fld.f6r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB12"); + state->u.f4.fld.f6r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB13"); + state->u.f4.fld.f6r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB14"); + state->u.f4.fld.f6r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB15"); + state->u.f4.fld.f6r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB16"); + state->u.f4.fld.f6r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB17"); + state->u.f4.fld.f6r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB18"); + state->u.f4.fld.f6r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB19"); + state->u.f4.fld.f6r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB20"); + state->u.f4.fld.f6r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB21"); + state->u.f4.fld.f6r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB22"); + state->u.f4.fld.f6r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB23"); + state->u.f4.fld.f6r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB24"); + state->u.f4.fld.f6r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB25"); + state->u.f4.fld.f6r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB26"); + state->u.f4.fld.f6r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB27"); + state->u.f4.fld.f6r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB28"); + state->u.f4.fld.f6r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB29"); + state->u.f4.fld.f6r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB30"); + state->u.f4.fld.f6r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB31"); + + // F7R1 bitfields. + state->u.f4.fld.f7r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB0"); + state->u.f4.fld.f7r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB1"); + state->u.f4.fld.f7r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB2"); + state->u.f4.fld.f7r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB3"); + state->u.f4.fld.f7r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB4"); + state->u.f4.fld.f7r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB5"); + state->u.f4.fld.f7r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB6"); + state->u.f4.fld.f7r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB7"); + state->u.f4.fld.f7r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB8"); + state->u.f4.fld.f7r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB9"); + state->u.f4.fld.f7r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB10"); + state->u.f4.fld.f7r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB11"); + state->u.f4.fld.f7r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB12"); + state->u.f4.fld.f7r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB13"); + state->u.f4.fld.f7r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB14"); + state->u.f4.fld.f7r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB15"); + state->u.f4.fld.f7r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB16"); + state->u.f4.fld.f7r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB17"); + state->u.f4.fld.f7r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB18"); + state->u.f4.fld.f7r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB19"); + state->u.f4.fld.f7r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB20"); + state->u.f4.fld.f7r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB21"); + state->u.f4.fld.f7r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB22"); + state->u.f4.fld.f7r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB23"); + state->u.f4.fld.f7r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB24"); + state->u.f4.fld.f7r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB25"); + state->u.f4.fld.f7r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB26"); + state->u.f4.fld.f7r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB27"); + state->u.f4.fld.f7r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB28"); + state->u.f4.fld.f7r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB29"); + state->u.f4.fld.f7r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB30"); + state->u.f4.fld.f7r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB31"); + + // F7R2 bitfields. + state->u.f4.fld.f7r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB0"); + state->u.f4.fld.f7r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB1"); + state->u.f4.fld.f7r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB2"); + state->u.f4.fld.f7r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB3"); + state->u.f4.fld.f7r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB4"); + state->u.f4.fld.f7r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB5"); + state->u.f4.fld.f7r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB6"); + state->u.f4.fld.f7r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB7"); + state->u.f4.fld.f7r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB8"); + state->u.f4.fld.f7r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB9"); + state->u.f4.fld.f7r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB10"); + state->u.f4.fld.f7r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB11"); + state->u.f4.fld.f7r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB12"); + state->u.f4.fld.f7r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB13"); + state->u.f4.fld.f7r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB14"); + state->u.f4.fld.f7r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB15"); + state->u.f4.fld.f7r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB16"); + state->u.f4.fld.f7r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB17"); + state->u.f4.fld.f7r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB18"); + state->u.f4.fld.f7r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB19"); + state->u.f4.fld.f7r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB20"); + state->u.f4.fld.f7r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB21"); + state->u.f4.fld.f7r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB22"); + state->u.f4.fld.f7r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB23"); + state->u.f4.fld.f7r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB24"); + state->u.f4.fld.f7r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB25"); + state->u.f4.fld.f7r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB26"); + state->u.f4.fld.f7r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB27"); + state->u.f4.fld.f7r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB28"); + state->u.f4.fld.f7r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB29"); + state->u.f4.fld.f7r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB30"); + state->u.f4.fld.f7r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB31"); + + // F8R1 bitfields. + state->u.f4.fld.f8r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB0"); + state->u.f4.fld.f8r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB1"); + state->u.f4.fld.f8r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB2"); + state->u.f4.fld.f8r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB3"); + state->u.f4.fld.f8r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB4"); + state->u.f4.fld.f8r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB5"); + state->u.f4.fld.f8r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB6"); + state->u.f4.fld.f8r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB7"); + state->u.f4.fld.f8r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB8"); + state->u.f4.fld.f8r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB9"); + state->u.f4.fld.f8r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB10"); + state->u.f4.fld.f8r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB11"); + state->u.f4.fld.f8r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB12"); + state->u.f4.fld.f8r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB13"); + state->u.f4.fld.f8r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB14"); + state->u.f4.fld.f8r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB15"); + state->u.f4.fld.f8r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB16"); + state->u.f4.fld.f8r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB17"); + state->u.f4.fld.f8r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB18"); + state->u.f4.fld.f8r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB19"); + state->u.f4.fld.f8r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB20"); + state->u.f4.fld.f8r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB21"); + state->u.f4.fld.f8r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB22"); + state->u.f4.fld.f8r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB23"); + state->u.f4.fld.f8r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB24"); + state->u.f4.fld.f8r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB25"); + state->u.f4.fld.f8r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB26"); + state->u.f4.fld.f8r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB27"); + state->u.f4.fld.f8r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB28"); + state->u.f4.fld.f8r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB29"); + state->u.f4.fld.f8r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB30"); + state->u.f4.fld.f8r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB31"); + + // F8R2 bitfields. + state->u.f4.fld.f8r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB0"); + state->u.f4.fld.f8r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB1"); + state->u.f4.fld.f8r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB2"); + state->u.f4.fld.f8r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB3"); + state->u.f4.fld.f8r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB4"); + state->u.f4.fld.f8r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB5"); + state->u.f4.fld.f8r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB6"); + state->u.f4.fld.f8r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB7"); + state->u.f4.fld.f8r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB8"); + state->u.f4.fld.f8r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB9"); + state->u.f4.fld.f8r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB10"); + state->u.f4.fld.f8r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB11"); + state->u.f4.fld.f8r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB12"); + state->u.f4.fld.f8r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB13"); + state->u.f4.fld.f8r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB14"); + state->u.f4.fld.f8r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB15"); + state->u.f4.fld.f8r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB16"); + state->u.f4.fld.f8r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB17"); + state->u.f4.fld.f8r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB18"); + state->u.f4.fld.f8r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB19"); + state->u.f4.fld.f8r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB20"); + state->u.f4.fld.f8r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB21"); + state->u.f4.fld.f8r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB22"); + state->u.f4.fld.f8r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB23"); + state->u.f4.fld.f8r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB24"); + state->u.f4.fld.f8r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB25"); + state->u.f4.fld.f8r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB26"); + state->u.f4.fld.f8r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB27"); + state->u.f4.fld.f8r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB28"); + state->u.f4.fld.f8r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB29"); + state->u.f4.fld.f8r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB30"); + state->u.f4.fld.f8r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB31"); + + // F9R1 bitfields. + state->u.f4.fld.f9r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB0"); + state->u.f4.fld.f9r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB1"); + state->u.f4.fld.f9r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB2"); + state->u.f4.fld.f9r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB3"); + state->u.f4.fld.f9r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB4"); + state->u.f4.fld.f9r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB5"); + state->u.f4.fld.f9r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB6"); + state->u.f4.fld.f9r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB7"); + state->u.f4.fld.f9r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB8"); + state->u.f4.fld.f9r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB9"); + state->u.f4.fld.f9r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB10"); + state->u.f4.fld.f9r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB11"); + state->u.f4.fld.f9r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB12"); + state->u.f4.fld.f9r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB13"); + state->u.f4.fld.f9r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB14"); + state->u.f4.fld.f9r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB15"); + state->u.f4.fld.f9r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB16"); + state->u.f4.fld.f9r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB17"); + state->u.f4.fld.f9r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB18"); + state->u.f4.fld.f9r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB19"); + state->u.f4.fld.f9r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB20"); + state->u.f4.fld.f9r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB21"); + state->u.f4.fld.f9r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB22"); + state->u.f4.fld.f9r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB23"); + state->u.f4.fld.f9r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB24"); + state->u.f4.fld.f9r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB25"); + state->u.f4.fld.f9r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB26"); + state->u.f4.fld.f9r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB27"); + state->u.f4.fld.f9r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB28"); + state->u.f4.fld.f9r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB29"); + state->u.f4.fld.f9r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB30"); + state->u.f4.fld.f9r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB31"); + + // F9R2 bitfields. + state->u.f4.fld.f9r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB0"); + state->u.f4.fld.f9r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB1"); + state->u.f4.fld.f9r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB2"); + state->u.f4.fld.f9r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB3"); + state->u.f4.fld.f9r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB4"); + state->u.f4.fld.f9r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB5"); + state->u.f4.fld.f9r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB6"); + state->u.f4.fld.f9r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB7"); + state->u.f4.fld.f9r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB8"); + state->u.f4.fld.f9r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB9"); + state->u.f4.fld.f9r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB10"); + state->u.f4.fld.f9r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB11"); + state->u.f4.fld.f9r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB12"); + state->u.f4.fld.f9r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB13"); + state->u.f4.fld.f9r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB14"); + state->u.f4.fld.f9r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB15"); + state->u.f4.fld.f9r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB16"); + state->u.f4.fld.f9r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB17"); + state->u.f4.fld.f9r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB18"); + state->u.f4.fld.f9r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB19"); + state->u.f4.fld.f9r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB20"); + state->u.f4.fld.f9r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB21"); + state->u.f4.fld.f9r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB22"); + state->u.f4.fld.f9r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB23"); + state->u.f4.fld.f9r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB24"); + state->u.f4.fld.f9r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB25"); + state->u.f4.fld.f9r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB26"); + state->u.f4.fld.f9r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB27"); + state->u.f4.fld.f9r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB28"); + state->u.f4.fld.f9r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB29"); + state->u.f4.fld.f9r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB30"); + state->u.f4.fld.f9r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB31"); + + // F10R1 bitfields. + state->u.f4.fld.f10r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB0"); + state->u.f4.fld.f10r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB1"); + state->u.f4.fld.f10r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB2"); + state->u.f4.fld.f10r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB3"); + state->u.f4.fld.f10r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB4"); + state->u.f4.fld.f10r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB5"); + state->u.f4.fld.f10r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB6"); + state->u.f4.fld.f10r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB7"); + state->u.f4.fld.f10r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB8"); + state->u.f4.fld.f10r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB9"); + state->u.f4.fld.f10r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB10"); + state->u.f4.fld.f10r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB11"); + state->u.f4.fld.f10r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB12"); + state->u.f4.fld.f10r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB13"); + state->u.f4.fld.f10r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB14"); + state->u.f4.fld.f10r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB15"); + state->u.f4.fld.f10r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB16"); + state->u.f4.fld.f10r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB17"); + state->u.f4.fld.f10r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB18"); + state->u.f4.fld.f10r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB19"); + state->u.f4.fld.f10r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB20"); + state->u.f4.fld.f10r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB21"); + state->u.f4.fld.f10r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB22"); + state->u.f4.fld.f10r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB23"); + state->u.f4.fld.f10r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB24"); + state->u.f4.fld.f10r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB25"); + state->u.f4.fld.f10r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB26"); + state->u.f4.fld.f10r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB27"); + state->u.f4.fld.f10r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB28"); + state->u.f4.fld.f10r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB29"); + state->u.f4.fld.f10r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB30"); + state->u.f4.fld.f10r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB31"); + + // F10R2 bitfields. + state->u.f4.fld.f10r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB0"); + state->u.f4.fld.f10r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB1"); + state->u.f4.fld.f10r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB2"); + state->u.f4.fld.f10r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB3"); + state->u.f4.fld.f10r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB4"); + state->u.f4.fld.f10r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB5"); + state->u.f4.fld.f10r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB6"); + state->u.f4.fld.f10r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB7"); + state->u.f4.fld.f10r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB8"); + state->u.f4.fld.f10r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB9"); + state->u.f4.fld.f10r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB10"); + state->u.f4.fld.f10r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB11"); + state->u.f4.fld.f10r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB12"); + state->u.f4.fld.f10r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB13"); + state->u.f4.fld.f10r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB14"); + state->u.f4.fld.f10r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB15"); + state->u.f4.fld.f10r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB16"); + state->u.f4.fld.f10r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB17"); + state->u.f4.fld.f10r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB18"); + state->u.f4.fld.f10r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB19"); + state->u.f4.fld.f10r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB20"); + state->u.f4.fld.f10r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB21"); + state->u.f4.fld.f10r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB22"); + state->u.f4.fld.f10r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB23"); + state->u.f4.fld.f10r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB24"); + state->u.f4.fld.f10r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB25"); + state->u.f4.fld.f10r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB26"); + state->u.f4.fld.f10r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB27"); + state->u.f4.fld.f10r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB28"); + state->u.f4.fld.f10r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB29"); + state->u.f4.fld.f10r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB30"); + state->u.f4.fld.f10r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB31"); + + // F11R1 bitfields. + state->u.f4.fld.f11r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB0"); + state->u.f4.fld.f11r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB1"); + state->u.f4.fld.f11r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB2"); + state->u.f4.fld.f11r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB3"); + state->u.f4.fld.f11r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB4"); + state->u.f4.fld.f11r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB5"); + state->u.f4.fld.f11r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB6"); + state->u.f4.fld.f11r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB7"); + state->u.f4.fld.f11r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB8"); + state->u.f4.fld.f11r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB9"); + state->u.f4.fld.f11r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB10"); + state->u.f4.fld.f11r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB11"); + state->u.f4.fld.f11r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB12"); + state->u.f4.fld.f11r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB13"); + state->u.f4.fld.f11r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB14"); + state->u.f4.fld.f11r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB15"); + state->u.f4.fld.f11r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB16"); + state->u.f4.fld.f11r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB17"); + state->u.f4.fld.f11r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB18"); + state->u.f4.fld.f11r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB19"); + state->u.f4.fld.f11r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB20"); + state->u.f4.fld.f11r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB21"); + state->u.f4.fld.f11r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB22"); + state->u.f4.fld.f11r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB23"); + state->u.f4.fld.f11r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB24"); + state->u.f4.fld.f11r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB25"); + state->u.f4.fld.f11r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB26"); + state->u.f4.fld.f11r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB27"); + state->u.f4.fld.f11r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB28"); + state->u.f4.fld.f11r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB29"); + state->u.f4.fld.f11r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB30"); + state->u.f4.fld.f11r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB31"); + + // F11R2 bitfields. + state->u.f4.fld.f11r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB0"); + state->u.f4.fld.f11r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB1"); + state->u.f4.fld.f11r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB2"); + state->u.f4.fld.f11r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB3"); + state->u.f4.fld.f11r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB4"); + state->u.f4.fld.f11r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB5"); + state->u.f4.fld.f11r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB6"); + state->u.f4.fld.f11r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB7"); + state->u.f4.fld.f11r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB8"); + state->u.f4.fld.f11r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB9"); + state->u.f4.fld.f11r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB10"); + state->u.f4.fld.f11r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB11"); + state->u.f4.fld.f11r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB12"); + state->u.f4.fld.f11r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB13"); + state->u.f4.fld.f11r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB14"); + state->u.f4.fld.f11r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB15"); + state->u.f4.fld.f11r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB16"); + state->u.f4.fld.f11r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB17"); + state->u.f4.fld.f11r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB18"); + state->u.f4.fld.f11r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB19"); + state->u.f4.fld.f11r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB20"); + state->u.f4.fld.f11r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB21"); + state->u.f4.fld.f11r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB22"); + state->u.f4.fld.f11r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB23"); + state->u.f4.fld.f11r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB24"); + state->u.f4.fld.f11r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB25"); + state->u.f4.fld.f11r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB26"); + state->u.f4.fld.f11r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB27"); + state->u.f4.fld.f11r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB28"); + state->u.f4.fld.f11r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB29"); + state->u.f4.fld.f11r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB30"); + state->u.f4.fld.f11r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB31"); + + // F12R1 bitfields. + state->u.f4.fld.f12r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB0"); + state->u.f4.fld.f12r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB1"); + state->u.f4.fld.f12r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB2"); + state->u.f4.fld.f12r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB3"); + state->u.f4.fld.f12r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB4"); + state->u.f4.fld.f12r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB5"); + state->u.f4.fld.f12r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB6"); + state->u.f4.fld.f12r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB7"); + state->u.f4.fld.f12r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB8"); + state->u.f4.fld.f12r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB9"); + state->u.f4.fld.f12r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB10"); + state->u.f4.fld.f12r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB11"); + state->u.f4.fld.f12r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB12"); + state->u.f4.fld.f12r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB13"); + state->u.f4.fld.f12r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB14"); + state->u.f4.fld.f12r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB15"); + state->u.f4.fld.f12r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB16"); + state->u.f4.fld.f12r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB17"); + state->u.f4.fld.f12r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB18"); + state->u.f4.fld.f12r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB19"); + state->u.f4.fld.f12r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB20"); + state->u.f4.fld.f12r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB21"); + state->u.f4.fld.f12r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB22"); + state->u.f4.fld.f12r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB23"); + state->u.f4.fld.f12r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB24"); + state->u.f4.fld.f12r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB25"); + state->u.f4.fld.f12r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB26"); + state->u.f4.fld.f12r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB27"); + state->u.f4.fld.f12r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB28"); + state->u.f4.fld.f12r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB29"); + state->u.f4.fld.f12r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB30"); + state->u.f4.fld.f12r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB31"); + + // F12R2 bitfields. + state->u.f4.fld.f12r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB0"); + state->u.f4.fld.f12r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB1"); + state->u.f4.fld.f12r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB2"); + state->u.f4.fld.f12r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB3"); + state->u.f4.fld.f12r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB4"); + state->u.f4.fld.f12r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB5"); + state->u.f4.fld.f12r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB6"); + state->u.f4.fld.f12r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB7"); + state->u.f4.fld.f12r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB8"); + state->u.f4.fld.f12r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB9"); + state->u.f4.fld.f12r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB10"); + state->u.f4.fld.f12r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB11"); + state->u.f4.fld.f12r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB12"); + state->u.f4.fld.f12r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB13"); + state->u.f4.fld.f12r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB14"); + state->u.f4.fld.f12r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB15"); + state->u.f4.fld.f12r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB16"); + state->u.f4.fld.f12r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB17"); + state->u.f4.fld.f12r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB18"); + state->u.f4.fld.f12r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB19"); + state->u.f4.fld.f12r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB20"); + state->u.f4.fld.f12r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB21"); + state->u.f4.fld.f12r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB22"); + state->u.f4.fld.f12r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB23"); + state->u.f4.fld.f12r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB24"); + state->u.f4.fld.f12r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB25"); + state->u.f4.fld.f12r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB26"); + state->u.f4.fld.f12r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB27"); + state->u.f4.fld.f12r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB28"); + state->u.f4.fld.f12r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB29"); + state->u.f4.fld.f12r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB30"); + state->u.f4.fld.f12r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB31"); + + // F13R1 bitfields. + state->u.f4.fld.f13r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB0"); + state->u.f4.fld.f13r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB1"); + state->u.f4.fld.f13r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB2"); + state->u.f4.fld.f13r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB3"); + state->u.f4.fld.f13r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB4"); + state->u.f4.fld.f13r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB5"); + state->u.f4.fld.f13r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB6"); + state->u.f4.fld.f13r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB7"); + state->u.f4.fld.f13r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB8"); + state->u.f4.fld.f13r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB9"); + state->u.f4.fld.f13r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB10"); + state->u.f4.fld.f13r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB11"); + state->u.f4.fld.f13r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB12"); + state->u.f4.fld.f13r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB13"); + state->u.f4.fld.f13r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB14"); + state->u.f4.fld.f13r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB15"); + state->u.f4.fld.f13r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB16"); + state->u.f4.fld.f13r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB17"); + state->u.f4.fld.f13r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB18"); + state->u.f4.fld.f13r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB19"); + state->u.f4.fld.f13r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB20"); + state->u.f4.fld.f13r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB21"); + state->u.f4.fld.f13r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB22"); + state->u.f4.fld.f13r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB23"); + state->u.f4.fld.f13r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB24"); + state->u.f4.fld.f13r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB25"); + state->u.f4.fld.f13r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB26"); + state->u.f4.fld.f13r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB27"); + state->u.f4.fld.f13r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB28"); + state->u.f4.fld.f13r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB29"); + state->u.f4.fld.f13r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB30"); + state->u.f4.fld.f13r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB31"); + + // F13R2 bitfields. + state->u.f4.fld.f13r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB0"); + state->u.f4.fld.f13r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB1"); + state->u.f4.fld.f13r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB2"); + state->u.f4.fld.f13r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB3"); + state->u.f4.fld.f13r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB4"); + state->u.f4.fld.f13r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB5"); + state->u.f4.fld.f13r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB6"); + state->u.f4.fld.f13r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB7"); + state->u.f4.fld.f13r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB8"); + state->u.f4.fld.f13r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB9"); + state->u.f4.fld.f13r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB10"); + state->u.f4.fld.f13r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB11"); + state->u.f4.fld.f13r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB12"); + state->u.f4.fld.f13r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB13"); + state->u.f4.fld.f13r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB14"); + state->u.f4.fld.f13r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB15"); + state->u.f4.fld.f13r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB16"); + state->u.f4.fld.f13r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB17"); + state->u.f4.fld.f13r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB18"); + state->u.f4.fld.f13r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB19"); + state->u.f4.fld.f13r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB20"); + state->u.f4.fld.f13r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB21"); + state->u.f4.fld.f13r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB22"); + state->u.f4.fld.f13r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB23"); + state->u.f4.fld.f13r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB24"); + state->u.f4.fld.f13r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB25"); + state->u.f4.fld.f13r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB26"); + state->u.f4.fld.f13r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB27"); + state->u.f4.fld.f13r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB28"); + state->u.f4.fld.f13r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB29"); + state->u.f4.fld.f13r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB30"); + state->u.f4.fld.f13r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB31"); + + // F14R1 bitfields. + state->u.f4.fld.f14r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB0"); + state->u.f4.fld.f14r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB1"); + state->u.f4.fld.f14r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB2"); + state->u.f4.fld.f14r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB3"); + state->u.f4.fld.f14r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB4"); + state->u.f4.fld.f14r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB5"); + state->u.f4.fld.f14r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB6"); + state->u.f4.fld.f14r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB7"); + state->u.f4.fld.f14r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB8"); + state->u.f4.fld.f14r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB9"); + state->u.f4.fld.f14r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB10"); + state->u.f4.fld.f14r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB11"); + state->u.f4.fld.f14r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB12"); + state->u.f4.fld.f14r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB13"); + state->u.f4.fld.f14r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB14"); + state->u.f4.fld.f14r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB15"); + state->u.f4.fld.f14r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB16"); + state->u.f4.fld.f14r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB17"); + state->u.f4.fld.f14r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB18"); + state->u.f4.fld.f14r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB19"); + state->u.f4.fld.f14r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB20"); + state->u.f4.fld.f14r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB21"); + state->u.f4.fld.f14r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB22"); + state->u.f4.fld.f14r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB23"); + state->u.f4.fld.f14r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB24"); + state->u.f4.fld.f14r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB25"); + state->u.f4.fld.f14r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB26"); + state->u.f4.fld.f14r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB27"); + state->u.f4.fld.f14r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB28"); + state->u.f4.fld.f14r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB29"); + state->u.f4.fld.f14r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB30"); + state->u.f4.fld.f14r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB31"); + + // F14R2 bitfields. + state->u.f4.fld.f14r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB0"); + state->u.f4.fld.f14r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB1"); + state->u.f4.fld.f14r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB2"); + state->u.f4.fld.f14r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB3"); + state->u.f4.fld.f14r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB4"); + state->u.f4.fld.f14r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB5"); + state->u.f4.fld.f14r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB6"); + state->u.f4.fld.f14r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB7"); + state->u.f4.fld.f14r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB8"); + state->u.f4.fld.f14r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB9"); + state->u.f4.fld.f14r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB10"); + state->u.f4.fld.f14r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB11"); + state->u.f4.fld.f14r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB12"); + state->u.f4.fld.f14r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB13"); + state->u.f4.fld.f14r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB14"); + state->u.f4.fld.f14r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB15"); + state->u.f4.fld.f14r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB16"); + state->u.f4.fld.f14r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB17"); + state->u.f4.fld.f14r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB18"); + state->u.f4.fld.f14r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB19"); + state->u.f4.fld.f14r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB20"); + state->u.f4.fld.f14r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB21"); + state->u.f4.fld.f14r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB22"); + state->u.f4.fld.f14r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB23"); + state->u.f4.fld.f14r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB24"); + state->u.f4.fld.f14r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB25"); + state->u.f4.fld.f14r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB26"); + state->u.f4.fld.f14r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB27"); + state->u.f4.fld.f14r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB28"); + state->u.f4.fld.f14r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB29"); + state->u.f4.fld.f14r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB30"); + state->u.f4.fld.f14r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB31"); + + // F15R1 bitfields. + state->u.f4.fld.f15r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB0"); + state->u.f4.fld.f15r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB1"); + state->u.f4.fld.f15r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB2"); + state->u.f4.fld.f15r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB3"); + state->u.f4.fld.f15r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB4"); + state->u.f4.fld.f15r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB5"); + state->u.f4.fld.f15r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB6"); + state->u.f4.fld.f15r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB7"); + state->u.f4.fld.f15r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB8"); + state->u.f4.fld.f15r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB9"); + state->u.f4.fld.f15r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB10"); + state->u.f4.fld.f15r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB11"); + state->u.f4.fld.f15r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB12"); + state->u.f4.fld.f15r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB13"); + state->u.f4.fld.f15r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB14"); + state->u.f4.fld.f15r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB15"); + state->u.f4.fld.f15r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB16"); + state->u.f4.fld.f15r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB17"); + state->u.f4.fld.f15r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB18"); + state->u.f4.fld.f15r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB19"); + state->u.f4.fld.f15r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB20"); + state->u.f4.fld.f15r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB21"); + state->u.f4.fld.f15r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB22"); + state->u.f4.fld.f15r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB23"); + state->u.f4.fld.f15r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB24"); + state->u.f4.fld.f15r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB25"); + state->u.f4.fld.f15r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB26"); + state->u.f4.fld.f15r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB27"); + state->u.f4.fld.f15r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB28"); + state->u.f4.fld.f15r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB29"); + state->u.f4.fld.f15r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB30"); + state->u.f4.fld.f15r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB31"); + + // F15R2 bitfields. + state->u.f4.fld.f15r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB0"); + state->u.f4.fld.f15r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB1"); + state->u.f4.fld.f15r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB2"); + state->u.f4.fld.f15r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB3"); + state->u.f4.fld.f15r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB4"); + state->u.f4.fld.f15r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB5"); + state->u.f4.fld.f15r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB6"); + state->u.f4.fld.f15r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB7"); + state->u.f4.fld.f15r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB8"); + state->u.f4.fld.f15r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB9"); + state->u.f4.fld.f15r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB10"); + state->u.f4.fld.f15r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB11"); + state->u.f4.fld.f15r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB12"); + state->u.f4.fld.f15r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB13"); + state->u.f4.fld.f15r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB14"); + state->u.f4.fld.f15r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB15"); + state->u.f4.fld.f15r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB16"); + state->u.f4.fld.f15r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB17"); + state->u.f4.fld.f15r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB18"); + state->u.f4.fld.f15r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB19"); + state->u.f4.fld.f15r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB20"); + state->u.f4.fld.f15r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB21"); + state->u.f4.fld.f15r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB22"); + state->u.f4.fld.f15r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB23"); + state->u.f4.fld.f15r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB24"); + state->u.f4.fld.f15r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB25"); + state->u.f4.fld.f15r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB26"); + state->u.f4.fld.f15r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB27"); + state->u.f4.fld.f15r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB28"); + state->u.f4.fld.f15r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB29"); + state->u.f4.fld.f15r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB30"); + state->u.f4.fld.f15r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB31"); + + // F16R1 bitfields. + state->u.f4.fld.f16r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB0"); + state->u.f4.fld.f16r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB1"); + state->u.f4.fld.f16r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB2"); + state->u.f4.fld.f16r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB3"); + state->u.f4.fld.f16r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB4"); + state->u.f4.fld.f16r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB5"); + state->u.f4.fld.f16r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB6"); + state->u.f4.fld.f16r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB7"); + state->u.f4.fld.f16r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB8"); + state->u.f4.fld.f16r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB9"); + state->u.f4.fld.f16r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB10"); + state->u.f4.fld.f16r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB11"); + state->u.f4.fld.f16r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB12"); + state->u.f4.fld.f16r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB13"); + state->u.f4.fld.f16r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB14"); + state->u.f4.fld.f16r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB15"); + state->u.f4.fld.f16r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB16"); + state->u.f4.fld.f16r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB17"); + state->u.f4.fld.f16r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB18"); + state->u.f4.fld.f16r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB19"); + state->u.f4.fld.f16r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB20"); + state->u.f4.fld.f16r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB21"); + state->u.f4.fld.f16r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB22"); + state->u.f4.fld.f16r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB23"); + state->u.f4.fld.f16r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB24"); + state->u.f4.fld.f16r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB25"); + state->u.f4.fld.f16r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB26"); + state->u.f4.fld.f16r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB27"); + state->u.f4.fld.f16r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB28"); + state->u.f4.fld.f16r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB29"); + state->u.f4.fld.f16r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB30"); + state->u.f4.fld.f16r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB31"); + + // F16R2 bitfields. + state->u.f4.fld.f16r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB0"); + state->u.f4.fld.f16r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB1"); + state->u.f4.fld.f16r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB2"); + state->u.f4.fld.f16r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB3"); + state->u.f4.fld.f16r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB4"); + state->u.f4.fld.f16r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB5"); + state->u.f4.fld.f16r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB6"); + state->u.f4.fld.f16r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB7"); + state->u.f4.fld.f16r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB8"); + state->u.f4.fld.f16r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB9"); + state->u.f4.fld.f16r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB10"); + state->u.f4.fld.f16r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB11"); + state->u.f4.fld.f16r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB12"); + state->u.f4.fld.f16r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB13"); + state->u.f4.fld.f16r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB14"); + state->u.f4.fld.f16r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB15"); + state->u.f4.fld.f16r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB16"); + state->u.f4.fld.f16r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB17"); + state->u.f4.fld.f16r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB18"); + state->u.f4.fld.f16r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB19"); + state->u.f4.fld.f16r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB20"); + state->u.f4.fld.f16r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB21"); + state->u.f4.fld.f16r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB22"); + state->u.f4.fld.f16r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB23"); + state->u.f4.fld.f16r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB24"); + state->u.f4.fld.f16r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB25"); + state->u.f4.fld.f16r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB26"); + state->u.f4.fld.f16r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB27"); + state->u.f4.fld.f16r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB28"); + state->u.f4.fld.f16r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB29"); + state->u.f4.fld.f16r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB30"); + state->u.f4.fld.f16r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB31"); + + // F17R1 bitfields. + state->u.f4.fld.f17r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB0"); + state->u.f4.fld.f17r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB1"); + state->u.f4.fld.f17r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB2"); + state->u.f4.fld.f17r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB3"); + state->u.f4.fld.f17r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB4"); + state->u.f4.fld.f17r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB5"); + state->u.f4.fld.f17r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB6"); + state->u.f4.fld.f17r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB7"); + state->u.f4.fld.f17r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB8"); + state->u.f4.fld.f17r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB9"); + state->u.f4.fld.f17r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB10"); + state->u.f4.fld.f17r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB11"); + state->u.f4.fld.f17r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB12"); + state->u.f4.fld.f17r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB13"); + state->u.f4.fld.f17r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB14"); + state->u.f4.fld.f17r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB15"); + state->u.f4.fld.f17r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB16"); + state->u.f4.fld.f17r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB17"); + state->u.f4.fld.f17r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB18"); + state->u.f4.fld.f17r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB19"); + state->u.f4.fld.f17r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB20"); + state->u.f4.fld.f17r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB21"); + state->u.f4.fld.f17r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB22"); + state->u.f4.fld.f17r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB23"); + state->u.f4.fld.f17r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB24"); + state->u.f4.fld.f17r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB25"); + state->u.f4.fld.f17r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB26"); + state->u.f4.fld.f17r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB27"); + state->u.f4.fld.f17r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB28"); + state->u.f4.fld.f17r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB29"); + state->u.f4.fld.f17r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB30"); + state->u.f4.fld.f17r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB31"); + + // F17R2 bitfields. + state->u.f4.fld.f17r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB0"); + state->u.f4.fld.f17r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB1"); + state->u.f4.fld.f17r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB2"); + state->u.f4.fld.f17r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB3"); + state->u.f4.fld.f17r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB4"); + state->u.f4.fld.f17r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB5"); + state->u.f4.fld.f17r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB6"); + state->u.f4.fld.f17r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB7"); + state->u.f4.fld.f17r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB8"); + state->u.f4.fld.f17r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB9"); + state->u.f4.fld.f17r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB10"); + state->u.f4.fld.f17r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB11"); + state->u.f4.fld.f17r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB12"); + state->u.f4.fld.f17r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB13"); + state->u.f4.fld.f17r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB14"); + state->u.f4.fld.f17r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB15"); + state->u.f4.fld.f17r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB16"); + state->u.f4.fld.f17r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB17"); + state->u.f4.fld.f17r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB18"); + state->u.f4.fld.f17r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB19"); + state->u.f4.fld.f17r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB20"); + state->u.f4.fld.f17r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB21"); + state->u.f4.fld.f17r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB22"); + state->u.f4.fld.f17r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB23"); + state->u.f4.fld.f17r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB24"); + state->u.f4.fld.f17r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB25"); + state->u.f4.fld.f17r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB26"); + state->u.f4.fld.f17r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB27"); + state->u.f4.fld.f17r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB28"); + state->u.f4.fld.f17r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB29"); + state->u.f4.fld.f17r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB30"); + state->u.f4.fld.f17r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB31"); + + // F18R1 bitfields. + state->u.f4.fld.f18r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB0"); + state->u.f4.fld.f18r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB1"); + state->u.f4.fld.f18r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB2"); + state->u.f4.fld.f18r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB3"); + state->u.f4.fld.f18r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB4"); + state->u.f4.fld.f18r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB5"); + state->u.f4.fld.f18r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB6"); + state->u.f4.fld.f18r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB7"); + state->u.f4.fld.f18r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB8"); + state->u.f4.fld.f18r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB9"); + state->u.f4.fld.f18r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB10"); + state->u.f4.fld.f18r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB11"); + state->u.f4.fld.f18r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB12"); + state->u.f4.fld.f18r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB13"); + state->u.f4.fld.f18r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB14"); + state->u.f4.fld.f18r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB15"); + state->u.f4.fld.f18r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB16"); + state->u.f4.fld.f18r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB17"); + state->u.f4.fld.f18r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB18"); + state->u.f4.fld.f18r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB19"); + state->u.f4.fld.f18r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB20"); + state->u.f4.fld.f18r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB21"); + state->u.f4.fld.f18r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB22"); + state->u.f4.fld.f18r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB23"); + state->u.f4.fld.f18r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB24"); + state->u.f4.fld.f18r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB25"); + state->u.f4.fld.f18r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB26"); + state->u.f4.fld.f18r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB27"); + state->u.f4.fld.f18r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB28"); + state->u.f4.fld.f18r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB29"); + state->u.f4.fld.f18r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB30"); + state->u.f4.fld.f18r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB31"); + + // F18R2 bitfields. + state->u.f4.fld.f18r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB0"); + state->u.f4.fld.f18r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB1"); + state->u.f4.fld.f18r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB2"); + state->u.f4.fld.f18r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB3"); + state->u.f4.fld.f18r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB4"); + state->u.f4.fld.f18r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB5"); + state->u.f4.fld.f18r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB6"); + state->u.f4.fld.f18r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB7"); + state->u.f4.fld.f18r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB8"); + state->u.f4.fld.f18r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB9"); + state->u.f4.fld.f18r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB10"); + state->u.f4.fld.f18r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB11"); + state->u.f4.fld.f18r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB12"); + state->u.f4.fld.f18r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB13"); + state->u.f4.fld.f18r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB14"); + state->u.f4.fld.f18r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB15"); + state->u.f4.fld.f18r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB16"); + state->u.f4.fld.f18r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB17"); + state->u.f4.fld.f18r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB18"); + state->u.f4.fld.f18r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB19"); + state->u.f4.fld.f18r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB20"); + state->u.f4.fld.f18r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB21"); + state->u.f4.fld.f18r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB22"); + state->u.f4.fld.f18r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB23"); + state->u.f4.fld.f18r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB24"); + state->u.f4.fld.f18r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB25"); + state->u.f4.fld.f18r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB26"); + state->u.f4.fld.f18r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB27"); + state->u.f4.fld.f18r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB28"); + state->u.f4.fld.f18r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB29"); + state->u.f4.fld.f18r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB30"); + state->u.f4.fld.f18r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB31"); + + // F19R1 bitfields. + state->u.f4.fld.f19r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB0"); + state->u.f4.fld.f19r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB1"); + state->u.f4.fld.f19r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB2"); + state->u.f4.fld.f19r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB3"); + state->u.f4.fld.f19r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB4"); + state->u.f4.fld.f19r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB5"); + state->u.f4.fld.f19r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB6"); + state->u.f4.fld.f19r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB7"); + state->u.f4.fld.f19r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB8"); + state->u.f4.fld.f19r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB9"); + state->u.f4.fld.f19r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB10"); + state->u.f4.fld.f19r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB11"); + state->u.f4.fld.f19r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB12"); + state->u.f4.fld.f19r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB13"); + state->u.f4.fld.f19r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB14"); + state->u.f4.fld.f19r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB15"); + state->u.f4.fld.f19r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB16"); + state->u.f4.fld.f19r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB17"); + state->u.f4.fld.f19r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB18"); + state->u.f4.fld.f19r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB19"); + state->u.f4.fld.f19r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB20"); + state->u.f4.fld.f19r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB21"); + state->u.f4.fld.f19r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB22"); + state->u.f4.fld.f19r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB23"); + state->u.f4.fld.f19r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB24"); + state->u.f4.fld.f19r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB25"); + state->u.f4.fld.f19r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB26"); + state->u.f4.fld.f19r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB27"); + state->u.f4.fld.f19r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB28"); + state->u.f4.fld.f19r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB29"); + state->u.f4.fld.f19r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB30"); + state->u.f4.fld.f19r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB31"); + + // F19R2 bitfields. + state->u.f4.fld.f19r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB0"); + state->u.f4.fld.f19r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB1"); + state->u.f4.fld.f19r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB2"); + state->u.f4.fld.f19r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB3"); + state->u.f4.fld.f19r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB4"); + state->u.f4.fld.f19r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB5"); + state->u.f4.fld.f19r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB6"); + state->u.f4.fld.f19r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB7"); + state->u.f4.fld.f19r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB8"); + state->u.f4.fld.f19r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB9"); + state->u.f4.fld.f19r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB10"); + state->u.f4.fld.f19r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB11"); + state->u.f4.fld.f19r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB12"); + state->u.f4.fld.f19r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB13"); + state->u.f4.fld.f19r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB14"); + state->u.f4.fld.f19r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB15"); + state->u.f4.fld.f19r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB16"); + state->u.f4.fld.f19r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB17"); + state->u.f4.fld.f19r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB18"); + state->u.f4.fld.f19r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB19"); + state->u.f4.fld.f19r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB20"); + state->u.f4.fld.f19r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB21"); + state->u.f4.fld.f19r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB22"); + state->u.f4.fld.f19r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB23"); + state->u.f4.fld.f19r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB24"); + state->u.f4.fld.f19r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB25"); + state->u.f4.fld.f19r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB26"); + state->u.f4.fld.f19r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB27"); + state->u.f4.fld.f19r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB28"); + state->u.f4.fld.f19r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB29"); + state->u.f4.fld.f19r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB30"); + state->u.f4.fld.f19r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB31"); + + // F20R1 bitfields. + state->u.f4.fld.f20r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB0"); + state->u.f4.fld.f20r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB1"); + state->u.f4.fld.f20r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB2"); + state->u.f4.fld.f20r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB3"); + state->u.f4.fld.f20r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB4"); + state->u.f4.fld.f20r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB5"); + state->u.f4.fld.f20r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB6"); + state->u.f4.fld.f20r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB7"); + state->u.f4.fld.f20r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB8"); + state->u.f4.fld.f20r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB9"); + state->u.f4.fld.f20r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB10"); + state->u.f4.fld.f20r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB11"); + state->u.f4.fld.f20r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB12"); + state->u.f4.fld.f20r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB13"); + state->u.f4.fld.f20r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB14"); + state->u.f4.fld.f20r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB15"); + state->u.f4.fld.f20r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB16"); + state->u.f4.fld.f20r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB17"); + state->u.f4.fld.f20r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB18"); + state->u.f4.fld.f20r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB19"); + state->u.f4.fld.f20r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB20"); + state->u.f4.fld.f20r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB21"); + state->u.f4.fld.f20r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB22"); + state->u.f4.fld.f20r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB23"); + state->u.f4.fld.f20r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB24"); + state->u.f4.fld.f20r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB25"); + state->u.f4.fld.f20r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB26"); + state->u.f4.fld.f20r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB27"); + state->u.f4.fld.f20r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB28"); + state->u.f4.fld.f20r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB29"); + state->u.f4.fld.f20r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB30"); + state->u.f4.fld.f20r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB31"); + + // F20R2 bitfields. + state->u.f4.fld.f20r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB0"); + state->u.f4.fld.f20r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB1"); + state->u.f4.fld.f20r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB2"); + state->u.f4.fld.f20r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB3"); + state->u.f4.fld.f20r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB4"); + state->u.f4.fld.f20r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB5"); + state->u.f4.fld.f20r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB6"); + state->u.f4.fld.f20r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB7"); + state->u.f4.fld.f20r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB8"); + state->u.f4.fld.f20r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB9"); + state->u.f4.fld.f20r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB10"); + state->u.f4.fld.f20r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB11"); + state->u.f4.fld.f20r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB12"); + state->u.f4.fld.f20r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB13"); + state->u.f4.fld.f20r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB14"); + state->u.f4.fld.f20r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB15"); + state->u.f4.fld.f20r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB16"); + state->u.f4.fld.f20r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB17"); + state->u.f4.fld.f20r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB18"); + state->u.f4.fld.f20r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB19"); + state->u.f4.fld.f20r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB20"); + state->u.f4.fld.f20r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB21"); + state->u.f4.fld.f20r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB22"); + state->u.f4.fld.f20r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB23"); + state->u.f4.fld.f20r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB24"); + state->u.f4.fld.f20r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB25"); + state->u.f4.fld.f20r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB26"); + state->u.f4.fld.f20r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB27"); + state->u.f4.fld.f20r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB28"); + state->u.f4.fld.f20r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB29"); + state->u.f4.fld.f20r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB30"); + state->u.f4.fld.f20r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB31"); + + // F21R1 bitfields. + state->u.f4.fld.f21r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB0"); + state->u.f4.fld.f21r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB1"); + state->u.f4.fld.f21r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB2"); + state->u.f4.fld.f21r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB3"); + state->u.f4.fld.f21r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB4"); + state->u.f4.fld.f21r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB5"); + state->u.f4.fld.f21r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB6"); + state->u.f4.fld.f21r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB7"); + state->u.f4.fld.f21r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB8"); + state->u.f4.fld.f21r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB9"); + state->u.f4.fld.f21r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB10"); + state->u.f4.fld.f21r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB11"); + state->u.f4.fld.f21r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB12"); + state->u.f4.fld.f21r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB13"); + state->u.f4.fld.f21r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB14"); + state->u.f4.fld.f21r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB15"); + state->u.f4.fld.f21r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB16"); + state->u.f4.fld.f21r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB17"); + state->u.f4.fld.f21r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB18"); + state->u.f4.fld.f21r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB19"); + state->u.f4.fld.f21r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB20"); + state->u.f4.fld.f21r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB21"); + state->u.f4.fld.f21r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB22"); + state->u.f4.fld.f21r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB23"); + state->u.f4.fld.f21r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB24"); + state->u.f4.fld.f21r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB25"); + state->u.f4.fld.f21r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB26"); + state->u.f4.fld.f21r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB27"); + state->u.f4.fld.f21r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB28"); + state->u.f4.fld.f21r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB29"); + state->u.f4.fld.f21r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB30"); + state->u.f4.fld.f21r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB31"); + + // F21R2 bitfields. + state->u.f4.fld.f21r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB0"); + state->u.f4.fld.f21r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB1"); + state->u.f4.fld.f21r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB2"); + state->u.f4.fld.f21r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB3"); + state->u.f4.fld.f21r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB4"); + state->u.f4.fld.f21r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB5"); + state->u.f4.fld.f21r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB6"); + state->u.f4.fld.f21r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB7"); + state->u.f4.fld.f21r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB8"); + state->u.f4.fld.f21r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB9"); + state->u.f4.fld.f21r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB10"); + state->u.f4.fld.f21r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB11"); + state->u.f4.fld.f21r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB12"); + state->u.f4.fld.f21r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB13"); + state->u.f4.fld.f21r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB14"); + state->u.f4.fld.f21r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB15"); + state->u.f4.fld.f21r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB16"); + state->u.f4.fld.f21r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB17"); + state->u.f4.fld.f21r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB18"); + state->u.f4.fld.f21r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB19"); + state->u.f4.fld.f21r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB20"); + state->u.f4.fld.f21r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB21"); + state->u.f4.fld.f21r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB22"); + state->u.f4.fld.f21r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB23"); + state->u.f4.fld.f21r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB24"); + state->u.f4.fld.f21r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB25"); + state->u.f4.fld.f21r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB26"); + state->u.f4.fld.f21r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB27"); + state->u.f4.fld.f21r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB28"); + state->u.f4.fld.f21r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB29"); + state->u.f4.fld.f21r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB30"); + state->u.f4.fld.f21r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB31"); + + // F22R1 bitfields. + state->u.f4.fld.f22r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB0"); + state->u.f4.fld.f22r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB1"); + state->u.f4.fld.f22r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB2"); + state->u.f4.fld.f22r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB3"); + state->u.f4.fld.f22r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB4"); + state->u.f4.fld.f22r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB5"); + state->u.f4.fld.f22r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB6"); + state->u.f4.fld.f22r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB7"); + state->u.f4.fld.f22r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB8"); + state->u.f4.fld.f22r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB9"); + state->u.f4.fld.f22r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB10"); + state->u.f4.fld.f22r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB11"); + state->u.f4.fld.f22r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB12"); + state->u.f4.fld.f22r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB13"); + state->u.f4.fld.f22r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB14"); + state->u.f4.fld.f22r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB15"); + state->u.f4.fld.f22r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB16"); + state->u.f4.fld.f22r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB17"); + state->u.f4.fld.f22r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB18"); + state->u.f4.fld.f22r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB19"); + state->u.f4.fld.f22r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB20"); + state->u.f4.fld.f22r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB21"); + state->u.f4.fld.f22r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB22"); + state->u.f4.fld.f22r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB23"); + state->u.f4.fld.f22r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB24"); + state->u.f4.fld.f22r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB25"); + state->u.f4.fld.f22r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB26"); + state->u.f4.fld.f22r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB27"); + state->u.f4.fld.f22r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB28"); + state->u.f4.fld.f22r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB29"); + state->u.f4.fld.f22r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB30"); + state->u.f4.fld.f22r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB31"); + + // F22R2 bitfields. + state->u.f4.fld.f22r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB0"); + state->u.f4.fld.f22r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB1"); + state->u.f4.fld.f22r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB2"); + state->u.f4.fld.f22r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB3"); + state->u.f4.fld.f22r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB4"); + state->u.f4.fld.f22r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB5"); + state->u.f4.fld.f22r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB6"); + state->u.f4.fld.f22r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB7"); + state->u.f4.fld.f22r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB8"); + state->u.f4.fld.f22r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB9"); + state->u.f4.fld.f22r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB10"); + state->u.f4.fld.f22r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB11"); + state->u.f4.fld.f22r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB12"); + state->u.f4.fld.f22r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB13"); + state->u.f4.fld.f22r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB14"); + state->u.f4.fld.f22r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB15"); + state->u.f4.fld.f22r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB16"); + state->u.f4.fld.f22r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB17"); + state->u.f4.fld.f22r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB18"); + state->u.f4.fld.f22r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB19"); + state->u.f4.fld.f22r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB20"); + state->u.f4.fld.f22r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB21"); + state->u.f4.fld.f22r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB22"); + state->u.f4.fld.f22r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB23"); + state->u.f4.fld.f22r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB24"); + state->u.f4.fld.f22r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB25"); + state->u.f4.fld.f22r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB26"); + state->u.f4.fld.f22r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB27"); + state->u.f4.fld.f22r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB28"); + state->u.f4.fld.f22r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB29"); + state->u.f4.fld.f22r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB30"); + state->u.f4.fld.f22r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB31"); + + // F23R1 bitfields. + state->u.f4.fld.f23r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB0"); + state->u.f4.fld.f23r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB1"); + state->u.f4.fld.f23r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB2"); + state->u.f4.fld.f23r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB3"); + state->u.f4.fld.f23r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB4"); + state->u.f4.fld.f23r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB5"); + state->u.f4.fld.f23r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB6"); + state->u.f4.fld.f23r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB7"); + state->u.f4.fld.f23r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB8"); + state->u.f4.fld.f23r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB9"); + state->u.f4.fld.f23r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB10"); + state->u.f4.fld.f23r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB11"); + state->u.f4.fld.f23r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB12"); + state->u.f4.fld.f23r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB13"); + state->u.f4.fld.f23r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB14"); + state->u.f4.fld.f23r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB15"); + state->u.f4.fld.f23r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB16"); + state->u.f4.fld.f23r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB17"); + state->u.f4.fld.f23r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB18"); + state->u.f4.fld.f23r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB19"); + state->u.f4.fld.f23r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB20"); + state->u.f4.fld.f23r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB21"); + state->u.f4.fld.f23r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB22"); + state->u.f4.fld.f23r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB23"); + state->u.f4.fld.f23r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB24"); + state->u.f4.fld.f23r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB25"); + state->u.f4.fld.f23r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB26"); + state->u.f4.fld.f23r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB27"); + state->u.f4.fld.f23r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB28"); + state->u.f4.fld.f23r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB29"); + state->u.f4.fld.f23r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB30"); + state->u.f4.fld.f23r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB31"); + + // F23R2 bitfields. + state->u.f4.fld.f23r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB0"); + state->u.f4.fld.f23r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB1"); + state->u.f4.fld.f23r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB2"); + state->u.f4.fld.f23r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB3"); + state->u.f4.fld.f23r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB4"); + state->u.f4.fld.f23r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB5"); + state->u.f4.fld.f23r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB6"); + state->u.f4.fld.f23r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB7"); + state->u.f4.fld.f23r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB8"); + state->u.f4.fld.f23r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB9"); + state->u.f4.fld.f23r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB10"); + state->u.f4.fld.f23r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB11"); + state->u.f4.fld.f23r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB12"); + state->u.f4.fld.f23r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB13"); + state->u.f4.fld.f23r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB14"); + state->u.f4.fld.f23r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB15"); + state->u.f4.fld.f23r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB16"); + state->u.f4.fld.f23r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB17"); + state->u.f4.fld.f23r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB18"); + state->u.f4.fld.f23r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB19"); + state->u.f4.fld.f23r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB20"); + state->u.f4.fld.f23r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB21"); + state->u.f4.fld.f23r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB22"); + state->u.f4.fld.f23r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB23"); + state->u.f4.fld.f23r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB24"); + state->u.f4.fld.f23r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB25"); + state->u.f4.fld.f23r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB26"); + state->u.f4.fld.f23r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB27"); + state->u.f4.fld.f23r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB28"); + state->u.f4.fld.f23r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB29"); + state->u.f4.fld.f23r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB30"); + state->u.f4.fld.f23r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB31"); + + // F24R1 bitfields. + state->u.f4.fld.f24r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB0"); + state->u.f4.fld.f24r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB1"); + state->u.f4.fld.f24r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB2"); + state->u.f4.fld.f24r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB3"); + state->u.f4.fld.f24r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB4"); + state->u.f4.fld.f24r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB5"); + state->u.f4.fld.f24r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB6"); + state->u.f4.fld.f24r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB7"); + state->u.f4.fld.f24r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB8"); + state->u.f4.fld.f24r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB9"); + state->u.f4.fld.f24r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB10"); + state->u.f4.fld.f24r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB11"); + state->u.f4.fld.f24r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB12"); + state->u.f4.fld.f24r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB13"); + state->u.f4.fld.f24r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB14"); + state->u.f4.fld.f24r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB15"); + state->u.f4.fld.f24r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB16"); + state->u.f4.fld.f24r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB17"); + state->u.f4.fld.f24r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB18"); + state->u.f4.fld.f24r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB19"); + state->u.f4.fld.f24r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB20"); + state->u.f4.fld.f24r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB21"); + state->u.f4.fld.f24r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB22"); + state->u.f4.fld.f24r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB23"); + state->u.f4.fld.f24r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB24"); + state->u.f4.fld.f24r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB25"); + state->u.f4.fld.f24r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB26"); + state->u.f4.fld.f24r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB27"); + state->u.f4.fld.f24r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB28"); + state->u.f4.fld.f24r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB29"); + state->u.f4.fld.f24r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB30"); + state->u.f4.fld.f24r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB31"); + + // F24R2 bitfields. + state->u.f4.fld.f24r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB0"); + state->u.f4.fld.f24r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB1"); + state->u.f4.fld.f24r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB2"); + state->u.f4.fld.f24r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB3"); + state->u.f4.fld.f24r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB4"); + state->u.f4.fld.f24r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB5"); + state->u.f4.fld.f24r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB6"); + state->u.f4.fld.f24r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB7"); + state->u.f4.fld.f24r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB8"); + state->u.f4.fld.f24r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB9"); + state->u.f4.fld.f24r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB10"); + state->u.f4.fld.f24r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB11"); + state->u.f4.fld.f24r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB12"); + state->u.f4.fld.f24r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB13"); + state->u.f4.fld.f24r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB14"); + state->u.f4.fld.f24r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB15"); + state->u.f4.fld.f24r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB16"); + state->u.f4.fld.f24r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB17"); + state->u.f4.fld.f24r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB18"); + state->u.f4.fld.f24r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB19"); + state->u.f4.fld.f24r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB20"); + state->u.f4.fld.f24r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB21"); + state->u.f4.fld.f24r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB22"); + state->u.f4.fld.f24r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB23"); + state->u.f4.fld.f24r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB24"); + state->u.f4.fld.f24r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB25"); + state->u.f4.fld.f24r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB26"); + state->u.f4.fld.f24r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB27"); + state->u.f4.fld.f24r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB28"); + state->u.f4.fld.f24r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB29"); + state->u.f4.fld.f24r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB30"); + state->u.f4.fld.f24r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB31"); + + // F25R1 bitfields. + state->u.f4.fld.f25r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB0"); + state->u.f4.fld.f25r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB1"); + state->u.f4.fld.f25r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB2"); + state->u.f4.fld.f25r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB3"); + state->u.f4.fld.f25r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB4"); + state->u.f4.fld.f25r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB5"); + state->u.f4.fld.f25r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB6"); + state->u.f4.fld.f25r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB7"); + state->u.f4.fld.f25r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB8"); + state->u.f4.fld.f25r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB9"); + state->u.f4.fld.f25r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB10"); + state->u.f4.fld.f25r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB11"); + state->u.f4.fld.f25r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB12"); + state->u.f4.fld.f25r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB13"); + state->u.f4.fld.f25r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB14"); + state->u.f4.fld.f25r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB15"); + state->u.f4.fld.f25r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB16"); + state->u.f4.fld.f25r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB17"); + state->u.f4.fld.f25r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB18"); + state->u.f4.fld.f25r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB19"); + state->u.f4.fld.f25r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB20"); + state->u.f4.fld.f25r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB21"); + state->u.f4.fld.f25r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB22"); + state->u.f4.fld.f25r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB23"); + state->u.f4.fld.f25r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB24"); + state->u.f4.fld.f25r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB25"); + state->u.f4.fld.f25r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB26"); + state->u.f4.fld.f25r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB27"); + state->u.f4.fld.f25r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB28"); + state->u.f4.fld.f25r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB29"); + state->u.f4.fld.f25r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB30"); + state->u.f4.fld.f25r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB31"); + + // F25R2 bitfields. + state->u.f4.fld.f25r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB0"); + state->u.f4.fld.f25r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB1"); + state->u.f4.fld.f25r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB2"); + state->u.f4.fld.f25r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB3"); + state->u.f4.fld.f25r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB4"); + state->u.f4.fld.f25r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB5"); + state->u.f4.fld.f25r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB6"); + state->u.f4.fld.f25r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB7"); + state->u.f4.fld.f25r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB8"); + state->u.f4.fld.f25r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB9"); + state->u.f4.fld.f25r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB10"); + state->u.f4.fld.f25r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB11"); + state->u.f4.fld.f25r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB12"); + state->u.f4.fld.f25r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB13"); + state->u.f4.fld.f25r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB14"); + state->u.f4.fld.f25r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB15"); + state->u.f4.fld.f25r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB16"); + state->u.f4.fld.f25r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB17"); + state->u.f4.fld.f25r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB18"); + state->u.f4.fld.f25r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB19"); + state->u.f4.fld.f25r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB20"); + state->u.f4.fld.f25r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB21"); + state->u.f4.fld.f25r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB22"); + state->u.f4.fld.f25r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB23"); + state->u.f4.fld.f25r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB24"); + state->u.f4.fld.f25r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB25"); + state->u.f4.fld.f25r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB26"); + state->u.f4.fld.f25r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB27"); + state->u.f4.fld.f25r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB28"); + state->u.f4.fld.f25r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB29"); + state->u.f4.fld.f25r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB30"); + state->u.f4.fld.f25r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB31"); + + // F26R1 bitfields. + state->u.f4.fld.f26r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB0"); + state->u.f4.fld.f26r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB1"); + state->u.f4.fld.f26r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB2"); + state->u.f4.fld.f26r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB3"); + state->u.f4.fld.f26r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB4"); + state->u.f4.fld.f26r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB5"); + state->u.f4.fld.f26r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB6"); + state->u.f4.fld.f26r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB7"); + state->u.f4.fld.f26r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB8"); + state->u.f4.fld.f26r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB9"); + state->u.f4.fld.f26r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB10"); + state->u.f4.fld.f26r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB11"); + state->u.f4.fld.f26r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB12"); + state->u.f4.fld.f26r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB13"); + state->u.f4.fld.f26r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB14"); + state->u.f4.fld.f26r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB15"); + state->u.f4.fld.f26r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB16"); + state->u.f4.fld.f26r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB17"); + state->u.f4.fld.f26r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB18"); + state->u.f4.fld.f26r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB19"); + state->u.f4.fld.f26r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB20"); + state->u.f4.fld.f26r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB21"); + state->u.f4.fld.f26r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB22"); + state->u.f4.fld.f26r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB23"); + state->u.f4.fld.f26r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB24"); + state->u.f4.fld.f26r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB25"); + state->u.f4.fld.f26r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB26"); + state->u.f4.fld.f26r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB27"); + state->u.f4.fld.f26r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB28"); + state->u.f4.fld.f26r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB29"); + state->u.f4.fld.f26r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB30"); + state->u.f4.fld.f26r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB31"); + + // F26R2 bitfields. + state->u.f4.fld.f26r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB0"); + state->u.f4.fld.f26r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB1"); + state->u.f4.fld.f26r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB2"); + state->u.f4.fld.f26r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB3"); + state->u.f4.fld.f26r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB4"); + state->u.f4.fld.f26r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB5"); + state->u.f4.fld.f26r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB6"); + state->u.f4.fld.f26r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB7"); + state->u.f4.fld.f26r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB8"); + state->u.f4.fld.f26r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB9"); + state->u.f4.fld.f26r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB10"); + state->u.f4.fld.f26r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB11"); + state->u.f4.fld.f26r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB12"); + state->u.f4.fld.f26r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB13"); + state->u.f4.fld.f26r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB14"); + state->u.f4.fld.f26r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB15"); + state->u.f4.fld.f26r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB16"); + state->u.f4.fld.f26r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB17"); + state->u.f4.fld.f26r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB18"); + state->u.f4.fld.f26r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB19"); + state->u.f4.fld.f26r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB20"); + state->u.f4.fld.f26r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB21"); + state->u.f4.fld.f26r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB22"); + state->u.f4.fld.f26r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB23"); + state->u.f4.fld.f26r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB24"); + state->u.f4.fld.f26r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB25"); + state->u.f4.fld.f26r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB26"); + state->u.f4.fld.f26r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB27"); + state->u.f4.fld.f26r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB28"); + state->u.f4.fld.f26r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB29"); + state->u.f4.fld.f26r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB30"); + state->u.f4.fld.f26r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB31"); + + // F27R1 bitfields. + state->u.f4.fld.f27r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB0"); + state->u.f4.fld.f27r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB1"); + state->u.f4.fld.f27r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB2"); + state->u.f4.fld.f27r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB3"); + state->u.f4.fld.f27r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB4"); + state->u.f4.fld.f27r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB5"); + state->u.f4.fld.f27r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB6"); + state->u.f4.fld.f27r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB7"); + state->u.f4.fld.f27r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB8"); + state->u.f4.fld.f27r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB9"); + state->u.f4.fld.f27r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB10"); + state->u.f4.fld.f27r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB11"); + state->u.f4.fld.f27r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB12"); + state->u.f4.fld.f27r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB13"); + state->u.f4.fld.f27r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB14"); + state->u.f4.fld.f27r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB15"); + state->u.f4.fld.f27r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB16"); + state->u.f4.fld.f27r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB17"); + state->u.f4.fld.f27r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB18"); + state->u.f4.fld.f27r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB19"); + state->u.f4.fld.f27r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB20"); + state->u.f4.fld.f27r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB21"); + state->u.f4.fld.f27r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB22"); + state->u.f4.fld.f27r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB23"); + state->u.f4.fld.f27r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB24"); + state->u.f4.fld.f27r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB25"); + state->u.f4.fld.f27r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB26"); + state->u.f4.fld.f27r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB27"); + state->u.f4.fld.f27r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB28"); + state->u.f4.fld.f27r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB29"); + state->u.f4.fld.f27r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB30"); + state->u.f4.fld.f27r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB31"); + + // F27R2 bitfields. + state->u.f4.fld.f27r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB0"); + state->u.f4.fld.f27r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB1"); + state->u.f4.fld.f27r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB2"); + state->u.f4.fld.f27r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB3"); + state->u.f4.fld.f27r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB4"); + state->u.f4.fld.f27r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB5"); + state->u.f4.fld.f27r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB6"); + state->u.f4.fld.f27r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB7"); + state->u.f4.fld.f27r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB8"); + state->u.f4.fld.f27r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB9"); + state->u.f4.fld.f27r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB10"); + state->u.f4.fld.f27r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB11"); + state->u.f4.fld.f27r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB12"); + state->u.f4.fld.f27r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB13"); + state->u.f4.fld.f27r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB14"); + state->u.f4.fld.f27r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB15"); + state->u.f4.fld.f27r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB16"); + state->u.f4.fld.f27r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB17"); + state->u.f4.fld.f27r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB18"); + state->u.f4.fld.f27r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB19"); + state->u.f4.fld.f27r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB20"); + state->u.f4.fld.f27r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB21"); + state->u.f4.fld.f27r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB22"); + state->u.f4.fld.f27r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB23"); + state->u.f4.fld.f27r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB24"); + state->u.f4.fld.f27r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB25"); + state->u.f4.fld.f27r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB26"); + state->u.f4.fld.f27r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB27"); + state->u.f4.fld.f27r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB28"); + state->u.f4.fld.f27r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB29"); + state->u.f4.fld.f27r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB30"); + state->u.f4.fld.f27r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB31"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_can_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_can_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_can_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_can_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_can_is_enabled(Object *obj) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_can_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CANState *state = STM32_CAN_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_CAN_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_can_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CAN)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CANState *state = STM32_CAN_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CAN"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_can_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_can_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_can_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_can_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_can_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CAN%dEN", + 1 + state->port_index - STM32_PORT_CAN1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_can_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CAN); +} + +static void stm32_can_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_can_reset_callback; + dc->realize = stm32_can_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_can_is_enabled; +} + +static const TypeInfo stm32_can_type_info = { + .name = TYPE_STM32_CAN, + .parent = TYPE_STM32_CAN_PARENT, + .instance_init = stm32_can_instance_init_callback, + .instance_size = sizeof(STM32CANState), + .class_init = stm32_can_class_init_callback, + .class_size = sizeof(STM32CANClass) }; + +static void stm32_can_register_types(void) +{ + type_register_static(&stm32_can_type_info); +} + +type_init(stm32_can_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/can1.h b/gnu-mcu-eclipse/devices/support/STM32F40x/can1.h new file mode 100644 index 0000000000..01b284b8d6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/can1.h @@ -0,0 +1,2614 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CAN_H_ +#define STM32_CAN_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CAN DEVICE_PATH_STM32 "CAN" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_CAN1, + STM32_PORT_CAN2, + STM32_PORT_CAN_UNDEFINED = 0xFF, +} stm32_can_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CAN TYPE_STM32_PREFIX "can" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CAN_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CANParentClass; +typedef PeripheralState STM32CANParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CAN_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CANClass, (obj), TYPE_STM32_CAN) +#define STM32_CAN_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CANClass, (klass), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentClass parent_class; + // public: + + // None, so far. +} STM32CANClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CAN_STATE(obj) \ + OBJECT_CHECK(STM32CANState, (obj), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_can_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 CAN (Controller area network) registers. + struct { + Object *mcr; // 0x0 (Master control register) + Object *msr; // 0x4 (Master status register) + Object *tsr; // 0x8 (Transmit status register) + Object *rf0r; // 0xC (Receive FIFO 0 register) + Object *rf1r; // 0x10 (Receive FIFO 1 register) + Object *ier; // 0x14 (Interrupt enable register) + Object *esr; // 0x18 (Interrupt enable register) + Object *btr; // 0x1C (Bit timing register) + Object *ti0r; // 0x180 (TX mailbox identifier register) + Object *tdt0r; // 0x184 (Mailbox data length control and time stamp register) + Object *tdl0r; // 0x188 (Mailbox data low register) + Object *tdh0r; // 0x18C (Mailbox data high register) + Object *ti1r; // 0x190 (Mailbox identifier register) + Object *tdt1r; // 0x194 (Mailbox data length control and time stamp register) + Object *tdl1r; // 0x198 (Mailbox data low register) + Object *tdh1r; // 0x19C (Mailbox data high register) + Object *ti2r; // 0x1A0 (Mailbox identifier register) + Object *tdt2r; // 0x1A4 (Mailbox data length control and time stamp register) + Object *tdl2r; // 0x1A8 (Mailbox data low register) + Object *tdh2r; // 0x1AC (Mailbox data high register) + Object *ri0r; // 0x1B0 (Receive FIFO mailbox identifier register) + Object *rdt0r; // 0x1B4 (Mailbox data high register) + Object *rdl0r; // 0x1B8 (Mailbox data high register) + Object *rdh0r; // 0x1BC (Receive FIFO mailbox data high register) + Object *ri1r; // 0x1C0 (Mailbox data high register) + Object *rdt1r; // 0x1C4 (Mailbox data high register) + Object *rdl1r; // 0x1C8 (Mailbox data high register) + Object *rdh1r; // 0x1CC (Mailbox data high register) + Object *fmr; // 0x200 (Filter master register) + Object *fm1r; // 0x204 (Filter mode register) + Object *fs1r; // 0x20C (Filter scale register) + Object *ffa1r; // 0x214 (Filter FIFO assignment register) + Object *fa1r; // 0x21C (Filter activation register) + Object *f0r1; // 0x240 (Filter bank 0 register 1) + Object *f0r2; // 0x244 (Filter bank 0 register 2) + Object *f1r1; // 0x248 (Filter bank 1 register 1) + Object *f1r2; // 0x24C (Filter bank 1 register 2) + Object *f2r1; // 0x250 (Filter bank 2 register 1) + Object *f2r2; // 0x254 (Filter bank 2 register 2) + Object *f3r1; // 0x258 (Filter bank 3 register 1) + Object *f3r2; // 0x25C (Filter bank 3 register 2) + Object *f4r1; // 0x260 (Filter bank 4 register 1) + Object *f4r2; // 0x264 (Filter bank 4 register 2) + Object *f5r1; // 0x268 (Filter bank 5 register 1) + Object *f5r2; // 0x26C (Filter bank 5 register 2) + Object *f6r1; // 0x270 (Filter bank 6 register 1) + Object *f6r2; // 0x274 (Filter bank 6 register 2) + Object *f7r1; // 0x278 (Filter bank 7 register 1) + Object *f7r2; // 0x27C (Filter bank 7 register 2) + Object *f8r1; // 0x280 (Filter bank 8 register 1) + Object *f8r2; // 0x284 (Filter bank 8 register 2) + Object *f9r1; // 0x288 (Filter bank 9 register 1) + Object *f9r2; // 0x28C (Filter bank 9 register 2) + Object *f10r1; // 0x290 (Filter bank 10 register 1) + Object *f10r2; // 0x294 (Filter bank 10 register 2) + Object *f11r1; // 0x298 (Filter bank 11 register 1) + Object *f11r2; // 0x29C (Filter bank 11 register 2) + Object *f12r1; // 0x2A0 (Filter bank 4 register 1) + Object *f12r2; // 0x2A4 (Filter bank 12 register 2) + Object *f13r1; // 0x2A8 (Filter bank 13 register 1) + Object *f13r2; // 0x2AC (Filter bank 13 register 2) + Object *f14r1; // 0x2B0 (Filter bank 14 register 1) + Object *f14r2; // 0x2B4 (Filter bank 14 register 2) + Object *f15r1; // 0x2B8 (Filter bank 15 register 1) + Object *f15r2; // 0x2BC (Filter bank 15 register 2) + Object *f16r1; // 0x2C0 (Filter bank 16 register 1) + Object *f16r2; // 0x2C4 (Filter bank 16 register 2) + Object *f17r1; // 0x2C8 (Filter bank 17 register 1) + Object *f17r2; // 0x2CC (Filter bank 17 register 2) + Object *f18r1; // 0x2D0 (Filter bank 18 register 1) + Object *f18r2; // 0x2D4 (Filter bank 18 register 2) + Object *f19r1; // 0x2D8 (Filter bank 19 register 1) + Object *f19r2; // 0x2DC (Filter bank 19 register 2) + Object *f20r1; // 0x2E0 (Filter bank 20 register 1) + Object *f20r2; // 0x2E4 (Filter bank 20 register 2) + Object *f21r1; // 0x2E8 (Filter bank 21 register 1) + Object *f21r2; // 0x2EC (Filter bank 21 register 2) + Object *f22r1; // 0x2F0 (Filter bank 22 register 1) + Object *f22r2; // 0x2F4 (Filter bank 22 register 2) + Object *f23r1; // 0x2F8 (Filter bank 23 register 1) + Object *f23r2; // 0x2FC (Filter bank 23 register 2) + Object *f24r1; // 0x300 (Filter bank 24 register 1) + Object *f24r2; // 0x304 (Filter bank 24 register 2) + Object *f25r1; // 0x308 (Filter bank 25 register 1) + Object *f25r2; // 0x30C (Filter bank 25 register 2) + Object *f26r1; // 0x310 (Filter bank 26 register 1) + Object *f26r2; // 0x314 (Filter bank 26 register 2) + Object *f27r1; // 0x318 (Filter bank 27 register 1) + Object *f27r2; // 0x31C (Filter bank 27 register 2) + } reg; + + struct { + + // MCR (Master control register) bitfields. + struct { + Object *inrq; // [0:0] INRQ + Object *sleep; // [1:1] SLEEP + Object *txfp; // [2:2] TXFP + Object *rflm; // [3:3] RFLM + Object *nart; // [4:4] NART + Object *awum; // [5:5] AWUM + Object *abom; // [6:6] ABOM + Object *ttcm; // [7:7] TTCM + Object *reset; // [15:15] RESET + Object *dbf; // [16:16] DBF + } mcr; + + // MSR (Master status register) bitfields. + struct { + Object *inak; // [0:0] INAK + Object *slak; // [1:1] SLAK + Object *erri; // [2:2] ERRI + Object *wkui; // [3:3] WKUI + Object *slaki; // [4:4] SLAKI + Object *txm; // [8:8] TXM + Object *rxm; // [9:9] RXM + Object *samp; // [10:10] SAMP + Object *rx; // [11:11] RX + } msr; + + // TSR (Transmit status register) bitfields. + struct { + Object *rqcp0; // [0:0] RQCP0 + Object *txok0; // [1:1] TXOK0 + Object *alst0; // [2:2] ALST0 + Object *terr0; // [3:3] TERR0 + Object *abrq0; // [7:7] ABRQ0 + Object *rqcp1; // [8:8] RQCP1 + Object *txok1; // [9:9] TXOK1 + Object *alst1; // [10:10] ALST1 + Object *terr1; // [11:11] TERR1 + Object *abrq1; // [15:15] ABRQ1 + Object *rqcp2; // [16:16] RQCP2 + Object *txok2; // [17:17] TXOK2 + Object *alst2; // [18:18] ALST2 + Object *terr2; // [19:19] TERR2 + Object *abrq2; // [23:23] ABRQ2 + Object *code; // [24:25] CODE + Object *tme0; // [26:26] Lowest priority flag for mailbox 0 + Object *tme1; // [27:27] Lowest priority flag for mailbox 1 + Object *tme2; // [28:28] Lowest priority flag for mailbox 2 + Object *low0; // [29:29] Lowest priority flag for mailbox 0 + Object *low1; // [30:30] Lowest priority flag for mailbox 1 + Object *low2; // [31:31] Lowest priority flag for mailbox 2 + } tsr; + + // RF0R (Receive FIFO 0 register) bitfields. + struct { + Object *fmp0; // [0:1] FMP0 + Object *full0; // [3:3] FULL0 + Object *fovr0; // [4:4] FOVR0 + Object *rfom0; // [5:5] RFOM0 + } rf0r; + + // RF1R (Receive FIFO 1 register) bitfields. + struct { + Object *fmp1; // [0:1] FMP1 + Object *full1; // [3:3] FULL1 + Object *fovr1; // [4:4] FOVR1 + Object *rfom1; // [5:5] RFOM1 + } rf1r; + + // IER (Interrupt enable register) bitfields. + struct { + Object *tmeie; // [0:0] TMEIE + Object *fmpie0; // [1:1] FMPIE0 + Object *ffie0; // [2:2] FFIE0 + Object *fovie0; // [3:3] FOVIE0 + Object *fmpie1; // [4:4] FMPIE1 + Object *ffie1; // [5:5] FFIE1 + Object *fovie1; // [6:6] FOVIE1 + Object *ewgie; // [8:8] EWGIE + Object *epvie; // [9:9] EPVIE + Object *bofie; // [10:10] BOFIE + Object *lecie; // [11:11] LECIE + Object *errie; // [15:15] ERRIE + Object *wkuie; // [16:16] WKUIE + Object *slkie; // [17:17] SLKIE + } ier; + + // ESR (Interrupt enable register) bitfields. + struct { + Object *ewgf; // [0:0] EWGF + Object *epvf; // [1:1] EPVF + Object *boff; // [2:2] BOFF + Object *lec; // [4:6] LEC + Object *tec; // [16:23] TEC + Object *rec; // [24:31] REC + } esr; + + // BTR (Bit timing register) bitfields. + struct { + Object *brp; // [0:9] BRP + Object *ts1; // [16:19] TS1 + Object *ts2; // [20:22] TS2 + Object *sjw; // [24:25] SJW + Object *lbkm; // [30:30] LBKM + Object *silm; // [31:31] SILM + } btr; + + // TI0R (TX mailbox identifier register) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ti0r; + + // TDT0R (Mailbox data length control and time stamp register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } tdt0r; + + // TDL0R (Mailbox data low register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } tdl0r; + + // TDH0R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } tdh0r; + + // TI1R (Mailbox identifier register) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ti1r; + + // TDT1R (Mailbox data length control and time stamp register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } tdt1r; + + // TDL1R (Mailbox data low register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } tdl1r; + + // TDH1R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } tdh1r; + + // TI2R (Mailbox identifier register) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ti2r; + + // TDT2R (Mailbox data length control and time stamp register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } tdt2r; + + // TDL2R (Mailbox data low register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } tdl2r; + + // TDH2R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } tdh2r; + + // RI0R (Receive FIFO mailbox identifier register) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ri0r; + + // RDT0R (Mailbox data high register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } rdt0r; + + // RDL0R (Mailbox data high register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } rdl0r; + + // RDH0R (Receive FIFO mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } rdh0r; + + // RI1R (Mailbox data high register) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ri1r; + + // RDT1R (Mailbox data high register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } rdt1r; + + // RDL1R (Mailbox data high register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } rdl1r; + + // RDH1R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } rdh1r; + + // FMR (Filter master register) bitfields. + struct { + Object *finit; // [0:0] FINIT + Object *can2sb; // [8:13] CAN2SB + } fmr; + + // FM1R (Filter mode register) bitfields. + struct { + Object *fbm0; // [0:0] Filter mode + Object *fbm1; // [1:1] Filter mode + Object *fbm2; // [2:2] Filter mode + Object *fbm3; // [3:3] Filter mode + Object *fbm4; // [4:4] Filter mode + Object *fbm5; // [5:5] Filter mode + Object *fbm6; // [6:6] Filter mode + Object *fbm7; // [7:7] Filter mode + Object *fbm8; // [8:8] Filter mode + Object *fbm9; // [9:9] Filter mode + Object *fbm10; // [10:10] Filter mode + Object *fbm11; // [11:11] Filter mode + Object *fbm12; // [12:12] Filter mode + Object *fbm13; // [13:13] Filter mode + Object *fbm14; // [14:14] Filter mode + Object *fbm15; // [15:15] Filter mode + Object *fbm16; // [16:16] Filter mode + Object *fbm17; // [17:17] Filter mode + Object *fbm18; // [18:18] Filter mode + Object *fbm19; // [19:19] Filter mode + Object *fbm20; // [20:20] Filter mode + Object *fbm21; // [21:21] Filter mode + Object *fbm22; // [22:22] Filter mode + Object *fbm23; // [23:23] Filter mode + Object *fbm24; // [24:24] Filter mode + Object *fbm25; // [25:25] Filter mode + Object *fbm26; // [26:26] Filter mode + Object *fbm27; // [27:27] Filter mode + } fm1r; + + // FS1R (Filter scale register) bitfields. + struct { + Object *fsc0; // [0:0] Filter scale configuration + Object *fsc1; // [1:1] Filter scale configuration + Object *fsc2; // [2:2] Filter scale configuration + Object *fsc3; // [3:3] Filter scale configuration + Object *fsc4; // [4:4] Filter scale configuration + Object *fsc5; // [5:5] Filter scale configuration + Object *fsc6; // [6:6] Filter scale configuration + Object *fsc7; // [7:7] Filter scale configuration + Object *fsc8; // [8:8] Filter scale configuration + Object *fsc9; // [9:9] Filter scale configuration + Object *fsc10; // [10:10] Filter scale configuration + Object *fsc11; // [11:11] Filter scale configuration + Object *fsc12; // [12:12] Filter scale configuration + Object *fsc13; // [13:13] Filter scale configuration + Object *fsc14; // [14:14] Filter scale configuration + Object *fsc15; // [15:15] Filter scale configuration + Object *fsc16; // [16:16] Filter scale configuration + Object *fsc17; // [17:17] Filter scale configuration + Object *fsc18; // [18:18] Filter scale configuration + Object *fsc19; // [19:19] Filter scale configuration + Object *fsc20; // [20:20] Filter scale configuration + Object *fsc21; // [21:21] Filter scale configuration + Object *fsc22; // [22:22] Filter scale configuration + Object *fsc23; // [23:23] Filter scale configuration + Object *fsc24; // [24:24] Filter scale configuration + Object *fsc25; // [25:25] Filter scale configuration + Object *fsc26; // [26:26] Filter scale configuration + Object *fsc27; // [27:27] Filter scale configuration + } fs1r; + + // FFA1R (Filter FIFO assignment register) bitfields. + struct { + Object *ffa0; // [0:0] Filter FIFO assignment for filter 0 + Object *ffa1; // [1:1] Filter FIFO assignment for filter 1 + Object *ffa2; // [2:2] Filter FIFO assignment for filter 2 + Object *ffa3; // [3:3] Filter FIFO assignment for filter 3 + Object *ffa4; // [4:4] Filter FIFO assignment for filter 4 + Object *ffa5; // [5:5] Filter FIFO assignment for filter 5 + Object *ffa6; // [6:6] Filter FIFO assignment for filter 6 + Object *ffa7; // [7:7] Filter FIFO assignment for filter 7 + Object *ffa8; // [8:8] Filter FIFO assignment for filter 8 + Object *ffa9; // [9:9] Filter FIFO assignment for filter 9 + Object *ffa10; // [10:10] Filter FIFO assignment for filter 10 + Object *ffa11; // [11:11] Filter FIFO assignment for filter 11 + Object *ffa12; // [12:12] Filter FIFO assignment for filter 12 + Object *ffa13; // [13:13] Filter FIFO assignment for filter 13 + Object *ffa14; // [14:14] Filter FIFO assignment for filter 14 + Object *ffa15; // [15:15] Filter FIFO assignment for filter 15 + Object *ffa16; // [16:16] Filter FIFO assignment for filter 16 + Object *ffa17; // [17:17] Filter FIFO assignment for filter 17 + Object *ffa18; // [18:18] Filter FIFO assignment for filter 18 + Object *ffa19; // [19:19] Filter FIFO assignment for filter 19 + Object *ffa20; // [20:20] Filter FIFO assignment for filter 20 + Object *ffa21; // [21:21] Filter FIFO assignment for filter 21 + Object *ffa22; // [22:22] Filter FIFO assignment for filter 22 + Object *ffa23; // [23:23] Filter FIFO assignment for filter 23 + Object *ffa24; // [24:24] Filter FIFO assignment for filter 24 + Object *ffa25; // [25:25] Filter FIFO assignment for filter 25 + Object *ffa26; // [26:26] Filter FIFO assignment for filter 26 + Object *ffa27; // [27:27] Filter FIFO assignment for filter 27 + } ffa1r; + + // FA1R (Filter activation register) bitfields. + struct { + Object *fact0; // [0:0] Filter active + Object *fact1; // [1:1] Filter active + Object *fact2; // [2:2] Filter active + Object *fact3; // [3:3] Filter active + Object *fact4; // [4:4] Filter active + Object *fact5; // [5:5] Filter active + Object *fact6; // [6:6] Filter active + Object *fact7; // [7:7] Filter active + Object *fact8; // [8:8] Filter active + Object *fact9; // [9:9] Filter active + Object *fact10; // [10:10] Filter active + Object *fact11; // [11:11] Filter active + Object *fact12; // [12:12] Filter active + Object *fact13; // [13:13] Filter active + Object *fact14; // [14:14] Filter active + Object *fact15; // [15:15] Filter active + Object *fact16; // [16:16] Filter active + Object *fact17; // [17:17] Filter active + Object *fact18; // [18:18] Filter active + Object *fact19; // [19:19] Filter active + Object *fact20; // [20:20] Filter active + Object *fact21; // [21:21] Filter active + Object *fact22; // [22:22] Filter active + Object *fact23; // [23:23] Filter active + Object *fact24; // [24:24] Filter active + Object *fact25; // [25:25] Filter active + Object *fact26; // [26:26] Filter active + Object *fact27; // [27:27] Filter active + } fa1r; + + // F0R1 (Filter bank 0 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r1; + + // F0R2 (Filter bank 0 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r2; + + // F1R1 (Filter bank 1 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r1; + + // F1R2 (Filter bank 1 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r2; + + // F2R1 (Filter bank 2 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r1; + + // F2R2 (Filter bank 2 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r2; + + // F3R1 (Filter bank 3 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r1; + + // F3R2 (Filter bank 3 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r2; + + // F4R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r1; + + // F4R2 (Filter bank 4 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r2; + + // F5R1 (Filter bank 5 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r1; + + // F5R2 (Filter bank 5 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r2; + + // F6R1 (Filter bank 6 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r1; + + // F6R2 (Filter bank 6 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r2; + + // F7R1 (Filter bank 7 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r1; + + // F7R2 (Filter bank 7 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r2; + + // F8R1 (Filter bank 8 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r1; + + // F8R2 (Filter bank 8 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r2; + + // F9R1 (Filter bank 9 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r1; + + // F9R2 (Filter bank 9 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r2; + + // F10R1 (Filter bank 10 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r1; + + // F10R2 (Filter bank 10 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r2; + + // F11R1 (Filter bank 11 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r1; + + // F11R2 (Filter bank 11 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r2; + + // F12R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r1; + + // F12R2 (Filter bank 12 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r2; + + // F13R1 (Filter bank 13 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r1; + + // F13R2 (Filter bank 13 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r2; + + // F14R1 (Filter bank 14 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r1; + + // F14R2 (Filter bank 14 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r2; + + // F15R1 (Filter bank 15 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r1; + + // F15R2 (Filter bank 15 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r2; + + // F16R1 (Filter bank 16 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r1; + + // F16R2 (Filter bank 16 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r2; + + // F17R1 (Filter bank 17 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r1; + + // F17R2 (Filter bank 17 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r2; + + // F18R1 (Filter bank 18 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r1; + + // F18R2 (Filter bank 18 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r2; + + // F19R1 (Filter bank 19 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r1; + + // F19R2 (Filter bank 19 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r2; + + // F20R1 (Filter bank 20 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r1; + + // F20R2 (Filter bank 20 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r2; + + // F21R1 (Filter bank 21 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r1; + + // F21R2 (Filter bank 21 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r2; + + // F22R1 (Filter bank 22 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r1; + + // F22R2 (Filter bank 22 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r2; + + // F23R1 (Filter bank 23 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r1; + + // F23R2 (Filter bank 23 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r2; + + // F24R1 (Filter bank 24 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r1; + + // F24R2 (Filter bank 24 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r2; + + // F25R1 (Filter bank 25 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r1; + + // F25R2 (Filter bank 25 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r2; + + // F26R1 (Filter bank 26 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r1; + + // F26R2 (Filter bank 26 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r2; + + // F27R1 (Filter bank 27 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r1; + + // F27R2 (Filter bank 27 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r2; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CANState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CAN_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/crc.c b/gnu-mcu-eclipse/devices/support/STM32F40x/crc.c new file mode 100644 index 0000000000..4597895ee6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/crc.c @@ -0,0 +1,246 @@ +/* + * STM32 - CRC (Cryptographic processor) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_crc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // IDR bitfields. + state->u.f4.fld.idr.idr = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR"); + + // CR bitfields. + state->u.f4.fld.cr.cr = cm_object_get_child_by_name(state->u.f4.reg.cr, "CR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crc_is_enabled(Object *obj) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRCState *state = STM32_CRC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRCState *state = STM32_CRC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_crc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_crc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_crc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_crc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_crc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRC); +} + +static void stm32_crc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crc_reset_callback; + dc->realize = stm32_crc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crc_is_enabled; +} + +static const TypeInfo stm32_crc_type_info = { + .name = TYPE_STM32_CRC, + .parent = TYPE_STM32_CRC_PARENT, + .instance_init = stm32_crc_instance_init_callback, + .instance_size = sizeof(STM32CRCState), + .class_init = stm32_crc_class_init_callback, + .class_size = sizeof(STM32CRCClass) }; + +static void stm32_crc_register_types(void) +{ + type_register_static(&stm32_crc_type_info); +} + +type_init(stm32_crc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/crc.h b/gnu-mcu-eclipse/devices/support/STM32F40x/crc.h new file mode 100644 index 0000000000..10e5fff9cc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/crc.h @@ -0,0 +1,117 @@ +/* + * STM32 - CRC (Cryptographic processor) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRC_H_ +#define STM32_CRC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRC DEVICE_PATH_STM32 "CRC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRC TYPE_STM32_PREFIX "crc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRCParentClass; +typedef PeripheralState STM32CRCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRCClass, (obj), TYPE_STM32_CRC) +#define STM32_CRC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRCClass, (klass), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentClass parent_class; + // public: + + // None, so far. +} STM32CRCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRC_STATE(obj) \ + OBJECT_CHECK(STM32CRCState, (obj), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 CRC (Cryptographic processor) registers. + struct { + Object *dr; // 0x0 (Data register) + Object *idr; // 0x4 (Independent Data register) + Object *cr; // 0x8 (Control register) + } reg; + + struct { + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:31] Data Register + } dr; + + // IDR (Independent Data register) bitfields. + struct { + Object *idr; // [0:7] Independent Data register + } idr; + + // CR (Control register) bitfields. + struct { + Object *cr; // [0:0] Control regidter + } cr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dac.c b/gnu-mcu-eclipse/devices/support/STM32F40x/dac.c new file mode 100644 index 0000000000..f0010714d2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dac.c @@ -0,0 +1,310 @@ +/* + * STM32 - DAC (Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_dac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.swtrigr = cm_object_get_child_by_name(obj, "SWTRIGR"); + state->u.f4.reg.dhr12r1 = cm_object_get_child_by_name(obj, "DHR12R1"); + state->u.f4.reg.dhr12l1 = cm_object_get_child_by_name(obj, "DHR12L1"); + state->u.f4.reg.dhr8r1 = cm_object_get_child_by_name(obj, "DHR8R1"); + state->u.f4.reg.dhr12r2 = cm_object_get_child_by_name(obj, "DHR12R2"); + state->u.f4.reg.dhr12l2 = cm_object_get_child_by_name(obj, "DHR12L2"); + state->u.f4.reg.dhr8r2 = cm_object_get_child_by_name(obj, "DHR8R2"); + state->u.f4.reg.dhr12rd = cm_object_get_child_by_name(obj, "DHR12RD"); + state->u.f4.reg.dhr12ld = cm_object_get_child_by_name(obj, "DHR12LD"); + state->u.f4.reg.dhr8rd = cm_object_get_child_by_name(obj, "DHR8RD"); + state->u.f4.reg.dor1 = cm_object_get_child_by_name(obj, "DOR1"); + state->u.f4.reg.dor2 = cm_object_get_child_by_name(obj, "DOR2"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f4.fld.cr.en1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "EN1"); + state->u.f4.fld.cr.boff1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "BOFF1"); + state->u.f4.fld.cr.ten1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TEN1"); + state->u.f4.fld.cr.tsel1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSEL1"); + state->u.f4.fld.cr.wave1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "WAVE1"); + state->u.f4.fld.cr.mamp1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "MAMP1"); + state->u.f4.fld.cr.dmaen1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAEN1"); + state->u.f4.fld.cr.dmaudrie1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAUDRIE1"); + state->u.f4.fld.cr.en2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "EN2"); + state->u.f4.fld.cr.boff2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "BOFF2"); + state->u.f4.fld.cr.ten2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TEN2"); + state->u.f4.fld.cr.tsel2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSEL2"); + state->u.f4.fld.cr.wave2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "WAVE2"); + state->u.f4.fld.cr.mamp2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "MAMP2"); + state->u.f4.fld.cr.dmaen2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAEN2"); + state->u.f4.fld.cr.dmaudrie2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAUDRIE2"); + + // SWTRIGR bitfields. + state->u.f4.fld.swtrigr.swtrig1 = cm_object_get_child_by_name(state->u.f4.reg.swtrigr, "SWTRIG1"); + state->u.f4.fld.swtrigr.swtrig2 = cm_object_get_child_by_name(state->u.f4.reg.swtrigr, "SWTRIG2"); + + // DHR12R1 bitfields. + state->u.f4.fld.dhr12r1.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12r1, "DACC1DHR"); + + // DHR12L1 bitfields. + state->u.f4.fld.dhr12l1.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12l1, "DACC1DHR"); + + // DHR8R1 bitfields. + state->u.f4.fld.dhr8r1.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8r1, "DACC1DHR"); + + // DHR12R2 bitfields. + state->u.f4.fld.dhr12r2.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12r2, "DACC2DHR"); + + // DHR12L2 bitfields. + state->u.f4.fld.dhr12l2.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12l2, "DACC2DHR"); + + // DHR8R2 bitfields. + state->u.f4.fld.dhr8r2.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8r2, "DACC2DHR"); + + // DHR12RD bitfields. + state->u.f4.fld.dhr12rd.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12rd, "DACC1DHR"); + state->u.f4.fld.dhr12rd.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12rd, "DACC2DHR"); + + // DHR12LD bitfields. + state->u.f4.fld.dhr12ld.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12ld, "DACC1DHR"); + state->u.f4.fld.dhr12ld.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12ld, "DACC2DHR"); + + // DHR8RD bitfields. + state->u.f4.fld.dhr8rd.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8rd, "DACC1DHR"); + state->u.f4.fld.dhr8rd.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8rd, "DACC2DHR"); + + // DOR1 bitfields. + state->u.f4.fld.dor1.dacc1dor = cm_object_get_child_by_name(state->u.f4.reg.dor1, "DACC1DOR"); + + // DOR2 bitfields. + state->u.f4.fld.dor2.dacc2dor = cm_object_get_child_by_name(state->u.f4.reg.dor2, "DACC2DOR"); + + // SR bitfields. + state->u.f4.fld.sr.dmaudr1 = cm_object_get_child_by_name(state->u.f4.reg.sr, "DMAUDR1"); + state->u.f4.fld.sr.dmaudr2 = cm_object_get_child_by_name(state->u.f4.reg.sr, "DMAUDR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dac_is_enabled(Object *obj) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DACState *state = STM32_DAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DACState *state = STM32_DAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_dac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DAC); +} + +static void stm32_dac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dac_reset_callback; + dc->realize = stm32_dac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dac_is_enabled; +} + +static const TypeInfo stm32_dac_type_info = { + .name = TYPE_STM32_DAC, + .parent = TYPE_STM32_DAC_PARENT, + .instance_init = stm32_dac_instance_init_callback, + .instance_size = sizeof(STM32DACState), + .class_init = stm32_dac_class_init_callback, + .class_size = sizeof(STM32DACClass) }; + +static void stm32_dac_register_types(void) +{ + type_register_static(&stm32_dac_type_info); +} + +type_init(stm32_dac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dac.h b/gnu-mcu-eclipse/devices/support/STM32F40x/dac.h new file mode 100644 index 0000000000..2193be3f32 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dac.h @@ -0,0 +1,203 @@ +/* + * STM32 - DAC (Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DAC_H_ +#define STM32_DAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DAC DEVICE_PATH_STM32 "DAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DAC TYPE_STM32_PREFIX "dac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DACParentClass; +typedef PeripheralState STM32DACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DACClass, (obj), TYPE_STM32_DAC) +#define STM32_DAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DACClass, (klass), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentClass parent_class; + // public: + + // None, so far. +} STM32DACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DAC_STATE(obj) \ + OBJECT_CHECK(STM32DACState, (obj), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DAC (Digital-to-analog converter) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *swtrigr; // 0x4 (Software trigger register) + Object *dhr12r1; // 0x8 (Channel1 12-bit right-aligned data holding register) + Object *dhr12l1; // 0xC (Channel1 12-bit left aligned data holding register) + Object *dhr8r1; // 0x10 (Channel1 8-bit right aligned data holding register) + Object *dhr12r2; // 0x14 (Channel2 12-bit right aligned data holding register) + Object *dhr12l2; // 0x18 (Channel2 12-bit left aligned data holding register) + Object *dhr8r2; // 0x1C (Channel2 8-bit right-aligned data holding register) + Object *dhr12rd; // 0x20 (Dual DAC 12-bit right-aligned data holding register) + Object *dhr12ld; // 0x24 (DUAL DAC 12-bit left aligned data holding register) + Object *dhr8rd; // 0x28 (DUAL DAC 8-bit right aligned data holding register) + Object *dor1; // 0x2C (Channel1 data output register) + Object *dor2; // 0x30 (Channel2 data output register) + Object *sr; // 0x34 (Status register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *en1; // [0:0] DAC channel1 enable + Object *boff1; // [1:1] DAC channel1 output buffer disable + Object *ten1; // [2:2] DAC channel1 trigger enable + Object *tsel1; // [3:5] DAC channel1 trigger selection + Object *wave1; // [6:7] DAC channel1 noise/triangle wave generation enable + Object *mamp1; // [8:11] DAC channel1 mask/amplitude selector + Object *dmaen1; // [12:12] DAC channel1 DMA enable + Object *dmaudrie1; // [13:13] DAC channel1 DMA Underrun Interrupt enable + Object *en2; // [16:16] DAC channel2 enable + Object *boff2; // [17:17] DAC channel2 output buffer disable + Object *ten2; // [18:18] DAC channel2 trigger enable + Object *tsel2; // [19:21] DAC channel2 trigger selection + Object *wave2; // [22:23] DAC channel2 noise/triangle wave generation enable + Object *mamp2; // [24:27] DAC channel2 mask/amplitude selector + Object *dmaen2; // [28:28] DAC channel2 DMA enable + Object *dmaudrie2; // [29:29] DAC channel2 DMA underrun interrupt enable + } cr; + + // SWTRIGR (Software trigger register) bitfields. + struct { + Object *swtrig1; // [0:0] DAC channel1 software trigger + Object *swtrig2; // [1:1] DAC channel2 software trigger + } swtrigr; + + // DHR12R1 (Channel1 12-bit right-aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + } dhr12r1; + + // DHR12L1 (Channel1 12-bit left aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + } dhr12l1; + + // DHR8R1 (Channel1 8-bit right aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + } dhr8r1; + + // DHR12R2 (Channel2 12-bit right aligned data holding register) bitfields. + struct { + Object *dacc2dhr; // [0:11] DAC channel2 12-bit right-aligned data + } dhr12r2; + + // DHR12L2 (Channel2 12-bit left aligned data holding register) bitfields. + struct { + Object *dacc2dhr; // [4:15] DAC channel2 12-bit left-aligned data + } dhr12l2; + + // DHR8R2 (Channel2 8-bit right-aligned data holding register) bitfields. + struct { + Object *dacc2dhr; // [0:7] DAC channel2 8-bit right-aligned data + } dhr8r2; + + // DHR12RD (Dual DAC 12-bit right-aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + Object *dacc2dhr; // [16:27] DAC channel2 12-bit right-aligned data + } dhr12rd; + + // DHR12LD (DUAL DAC 12-bit left aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + Object *dacc2dhr; // [20:31] DAC channel2 12-bit left-aligned data + } dhr12ld; + + // DHR8RD (DUAL DAC 8-bit right aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + Object *dacc2dhr; // [8:15] DAC channel2 8-bit right-aligned data + } dhr8rd; + + // DOR1 (Channel1 data output register) bitfields. + struct { + Object *dacc1dor; // [0:11] DAC channel1 data output + } dor1; + + // DOR2 (Channel2 data output register) bitfields. + struct { + Object *dacc2dor; // [0:11] DAC channel2 data output + } dor2; + + // SR (Status register) bitfields. + struct { + Object *dmaudr1; // [13:13] DAC channel1 DMA underrun flag + Object *dmaudr2; // [29:29] DAC channel2 DMA underrun flag + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dbg.c b/gnu-mcu-eclipse/devices/support/STM32F40x/dbg.c new file mode 100644 index 0000000000..dcf67a6c65 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dbg.c @@ -0,0 +1,279 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_dbg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dbgmcu_idcode = cm_object_get_child_by_name(obj, "DBGMCU_IDCODE"); + state->u.f4.reg.dbgmcu_cr = cm_object_get_child_by_name(obj, "DBGMCU_CR"); + state->u.f4.reg.dbgmcu_apb1_fz = cm_object_get_child_by_name(obj, "DBGMCU_APB1_FZ"); + state->u.f4.reg.dbgmcu_apb2_fz = cm_object_get_child_by_name(obj, "DBGMCU_APB2_FZ"); + + + // DBGMCU_IDCODE bitfields. + state->u.f4.fld.dbgmcu_idcode.dev_id = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_idcode, "DEV_ID"); + state->u.f4.fld.dbgmcu_idcode.rev_id = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_idcode, "REV_ID"); + + // DBGMCU_CR bitfields. + state->u.f4.fld.dbgmcu_cr.dbg_sleep = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_SLEEP"); + state->u.f4.fld.dbgmcu_cr.dbg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_STOP"); + state->u.f4.fld.dbgmcu_cr.dbg_standby = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_STANDBY"); + state->u.f4.fld.dbgmcu_cr.trace_ioen = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "TRACE_IOEN"); + state->u.f4.fld.dbgmcu_cr.trace_mode = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "TRACE_MODE"); + state->u.f4.fld.dbgmcu_cr.dbg_i2c2_smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_I2C2_SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_cr.dbg_tim8_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_TIM8_STOP"); + state->u.f4.fld.dbgmcu_cr.dbg_tim5_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_TIM5_STOP"); + state->u.f4.fld.dbgmcu_cr.dbg_tim6_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_TIM6_STOP"); + state->u.f4.fld.dbgmcu_cr.dbg_tim7_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_TIM7_STOP"); + + // DBGMCU_APB1_FZ bitfields. + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim2_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM2_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim3_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM3_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim4_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM4_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim5_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM5_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim6_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM6_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim7_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM7_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim12_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM12_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim13_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM13_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim14_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM14_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_wwdg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_WWDG_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_iwdeg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_IWDEG_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_j2c1_smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_J2C1_SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_j2c2_smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_J2C2_SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_j2c3smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_J2C3SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_can1_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_CAN1_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_can2_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_CAN2_STOP"); + + // DBGMCU_APB2_FZ bitfields. + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim1_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM1_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim8_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM8_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim9_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM9_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim10_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM10_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim11_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM11_STOP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dbg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dbg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dbg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dbg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dbg_is_enabled(Object *obj) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dbg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DBGState *state = STM32_DBG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dbg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DBG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DBGState *state = STM32_DBG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DBG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_dbg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dbg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dbg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dbg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dbg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DBGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dbg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DBG); +} + +static void stm32_dbg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dbg_reset_callback; + dc->realize = stm32_dbg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dbg_is_enabled; +} + +static const TypeInfo stm32_dbg_type_info = { + .name = TYPE_STM32_DBG, + .parent = TYPE_STM32_DBG_PARENT, + .instance_init = stm32_dbg_instance_init_callback, + .instance_size = sizeof(STM32DBGState), + .class_init = stm32_dbg_class_init_callback, + .class_size = sizeof(STM32DBGClass) }; + +static void stm32_dbg_register_types(void) +{ + type_register_static(&stm32_dbg_type_info); +} + +type_init(stm32_dbg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dbg.h b/gnu-mcu-eclipse/devices/support/STM32F40x/dbg.h new file mode 100644 index 0000000000..0a1805683a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dbg.h @@ -0,0 +1,152 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DBG_H_ +#define STM32_DBG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DBG DEVICE_PATH_STM32 "DBG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DBG TYPE_STM32_PREFIX "dbg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DBG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DBGParentClass; +typedef PeripheralState STM32DBGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DBG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DBGClass, (obj), TYPE_STM32_DBG) +#define STM32_DBG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DBGClass, (klass), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentClass parent_class; + // public: + + // None, so far. +} STM32DBGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DBG_STATE(obj) \ + OBJECT_CHECK(STM32DBGState, (obj), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DBG (Debug support) registers. + struct { + Object *dbgmcu_idcode; // 0x0 (IDCODE) + Object *dbgmcu_cr; // 0x4 (Control Register) + Object *dbgmcu_apb1_fz; // 0x8 (Debug MCU APB1 Freeze registe) + Object *dbgmcu_apb2_fz; // 0xC (Debug MCU APB2 Freeze registe) + } reg; + + struct { + + // DBGMCU_IDCODE (IDCODE) bitfields. + struct { + Object *dev_id; // [0:11] DEV_ID + Object *rev_id; // [16:31] REV_ID + } dbgmcu_idcode; + + // DBGMCU_CR (Control Register) bitfields. + struct { + Object *dbg_sleep; // [0:0] DBG_SLEEP + Object *dbg_stop; // [1:1] DBG_STOP + Object *dbg_standby; // [2:2] DBG_STANDBY + Object *trace_ioen; // [5:5] TRACE_IOEN + Object *trace_mode; // [6:7] TRACE_MODE + Object *dbg_i2c2_smbus_timeout; // [16:16] DBG_I2C2_SMBUS_TIMEOUT + Object *dbg_tim8_stop; // [17:17] DBG_TIM8_STOP + Object *dbg_tim5_stop; // [18:18] DBG_TIM5_STOP + Object *dbg_tim6_stop; // [19:19] DBG_TIM6_STOP + Object *dbg_tim7_stop; // [20:20] DBG_TIM7_STOP + } dbgmcu_cr; + + // DBGMCU_APB1_FZ (Debug MCU APB1 Freeze registe) bitfields. + struct { + Object *dbg_tim2_stop; // [0:0] DBG_TIM2_STOP + Object *dbg_tim3_stop; // [1:1] DBG_TIM3 _STOP + Object *dbg_tim4_stop; // [2:2] DBG_TIM4_STOP + Object *dbg_tim5_stop; // [3:3] DBG_TIM5_STOP + Object *dbg_tim6_stop; // [4:4] DBG_TIM6_STOP + Object *dbg_tim7_stop; // [5:5] DBG_TIM7_STOP + Object *dbg_tim12_stop; // [6:6] DBG_TIM12_STOP + Object *dbg_tim13_stop; // [7:7] DBG_TIM13_STOP + Object *dbg_tim14_stop; // [8:8] DBG_TIM14_STOP + Object *dbg_wwdg_stop; // [11:11] DBG_WWDG_STOP + Object *dbg_iwdeg_stop; // [12:12] DBG_IWDEG_STOP + Object *dbg_j2c1_smbus_timeout; // [21:21] DBG_J2C1_SMBUS_TIMEOUT + Object *dbg_j2c2_smbus_timeout; // [22:22] DBG_J2C2_SMBUS_TIMEOUT + Object *dbg_j2c3smbus_timeout; // [23:23] DBG_J2C3SMBUS_TIMEOUT + Object *dbg_can1_stop; // [25:25] DBG_CAN1_STOP + Object *dbg_can2_stop; // [26:26] DBG_CAN2_STOP + } dbgmcu_apb1_fz; + + // DBGMCU_APB2_FZ (Debug MCU APB2 Freeze registe) bitfields. + struct { + Object *dbg_tim1_stop; // [0:0] TIM1 counter stopped when core is halted + Object *dbg_tim8_stop; // [1:1] TIM8 counter stopped when core is halted + Object *dbg_tim9_stop; // [16:16] TIM9 counter stopped when core is halted + Object *dbg_tim10_stop; // [17:17] TIM10 counter stopped when core is halted + Object *dbg_tim11_stop; // [18:18] TIM11 counter stopped when core is halted + } dbgmcu_apb2_fz; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DBGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DBG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dcmi.c b/gnu-mcu-eclipse/devices/support/STM32F40x/dcmi.c new file mode 100644 index 0000000000..c9a3099958 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dcmi.c @@ -0,0 +1,317 @@ +/* + * STM32 - DCMI (Digital camera interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_dcmi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DCMIState *state = STM32_DCMI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.ris = cm_object_get_child_by_name(obj, "RIS"); + state->u.f4.reg.ier = cm_object_get_child_by_name(obj, "IER"); + state->u.f4.reg.mis = cm_object_get_child_by_name(obj, "MIS"); + state->u.f4.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f4.reg.escr = cm_object_get_child_by_name(obj, "ESCR"); + state->u.f4.reg.esur = cm_object_get_child_by_name(obj, "ESUR"); + state->u.f4.reg.cwstrt = cm_object_get_child_by_name(obj, "CWSTRT"); + state->u.f4.reg.cwsize = cm_object_get_child_by_name(obj, "CWSIZE"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // CR bitfields. + state->u.f4.fld.cr.capture = cm_object_get_child_by_name(state->u.f4.reg.cr, "CAPTURE"); + state->u.f4.fld.cr.cm = cm_object_get_child_by_name(state->u.f4.reg.cr, "CM"); + state->u.f4.fld.cr.crop = cm_object_get_child_by_name(state->u.f4.reg.cr, "CROP"); + state->u.f4.fld.cr.jpeg = cm_object_get_child_by_name(state->u.f4.reg.cr, "JPEG"); + state->u.f4.fld.cr.ess = cm_object_get_child_by_name(state->u.f4.reg.cr, "ESS"); + state->u.f4.fld.cr.pckpol = cm_object_get_child_by_name(state->u.f4.reg.cr, "PCKPOL"); + state->u.f4.fld.cr.hspol = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSPOL"); + state->u.f4.fld.cr.vspol = cm_object_get_child_by_name(state->u.f4.reg.cr, "VSPOL"); + state->u.f4.fld.cr.fcrc = cm_object_get_child_by_name(state->u.f4.reg.cr, "FCRC"); + state->u.f4.fld.cr.edm = cm_object_get_child_by_name(state->u.f4.reg.cr, "EDM"); + state->u.f4.fld.cr.enable = cm_object_get_child_by_name(state->u.f4.reg.cr, "ENABLE"); + + // SR bitfields. + state->u.f4.fld.sr.hsync = cm_object_get_child_by_name(state->u.f4.reg.sr, "HSYNC"); + state->u.f4.fld.sr.vsync = cm_object_get_child_by_name(state->u.f4.reg.sr, "VSYNC"); + state->u.f4.fld.sr.fne = cm_object_get_child_by_name(state->u.f4.reg.sr, "FNE"); + + // RIS bitfields. + state->u.f4.fld.ris.frame_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "FRAME_RIS"); + state->u.f4.fld.ris.ovr_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "OVR_RIS"); + state->u.f4.fld.ris.err_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "ERR_RIS"); + state->u.f4.fld.ris.vsync_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "VSYNC_RIS"); + state->u.f4.fld.ris.line_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "LINE_RIS"); + + // IER bitfields. + state->u.f4.fld.ier.frame_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "FRAME_IE"); + state->u.f4.fld.ier.ovr_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "OVR_IE"); + state->u.f4.fld.ier.err_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "ERR_IE"); + state->u.f4.fld.ier.vsync_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "VSYNC_IE"); + state->u.f4.fld.ier.line_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "LINE_IE"); + + // MIS bitfields. + state->u.f4.fld.mis.frame_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "FRAME_MIS"); + state->u.f4.fld.mis.ovr_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "OVR_MIS"); + state->u.f4.fld.mis.err_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "ERR_MIS"); + state->u.f4.fld.mis.vsync_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "VSYNC_MIS"); + state->u.f4.fld.mis.line_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "LINE_MIS"); + + // ICR bitfields. + state->u.f4.fld.icr.frame_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "FRAME_ISC"); + state->u.f4.fld.icr.ovr_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "OVR_ISC"); + state->u.f4.fld.icr.err_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "ERR_ISC"); + state->u.f4.fld.icr.vsync_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "VSYNC_ISC"); + state->u.f4.fld.icr.line_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "LINE_ISC"); + + // ESCR bitfields. + state->u.f4.fld.escr.fsc = cm_object_get_child_by_name(state->u.f4.reg.escr, "FSC"); + state->u.f4.fld.escr.lsc = cm_object_get_child_by_name(state->u.f4.reg.escr, "LSC"); + state->u.f4.fld.escr.lec = cm_object_get_child_by_name(state->u.f4.reg.escr, "LEC"); + state->u.f4.fld.escr.fec = cm_object_get_child_by_name(state->u.f4.reg.escr, "FEC"); + + // ESUR bitfields. + state->u.f4.fld.esur.fsu = cm_object_get_child_by_name(state->u.f4.reg.esur, "FSU"); + state->u.f4.fld.esur.lsu = cm_object_get_child_by_name(state->u.f4.reg.esur, "LSU"); + state->u.f4.fld.esur.leu = cm_object_get_child_by_name(state->u.f4.reg.esur, "LEU"); + state->u.f4.fld.esur.feu = cm_object_get_child_by_name(state->u.f4.reg.esur, "FEU"); + + // CWSTRT bitfields. + state->u.f4.fld.cwstrt.hoffcnt = cm_object_get_child_by_name(state->u.f4.reg.cwstrt, "HOFFCNT"); + state->u.f4.fld.cwstrt.vst = cm_object_get_child_by_name(state->u.f4.reg.cwstrt, "VST"); + + // CWSIZE bitfields. + state->u.f4.fld.cwsize.capcnt = cm_object_get_child_by_name(state->u.f4.reg.cwsize, "CAPCNT"); + state->u.f4.fld.cwsize.vline = cm_object_get_child_by_name(state->u.f4.reg.cwsize, "VLINE"); + + // DR bitfields. + state->u.f4.fld.dr.byte0 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte0"); + state->u.f4.fld.dr.byte1 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte1"); + state->u.f4.fld.dr.byte2 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte2"); + state->u.f4.fld.dr.byte3 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte3"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dcmi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dcmi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dcmi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dcmi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dcmi_is_enabled(Object *obj) +{ + STM32DCMIState *state = STM32_DCMI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dcmi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DCMIState *state = STM32_DCMI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dcmi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DCMI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DCMIState *state = STM32_DCMI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DCMI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_dcmi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dcmi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dcmi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dcmi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dcmi_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DCMIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dcmi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DCMI); +} + +static void stm32_dcmi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dcmi_reset_callback; + dc->realize = stm32_dcmi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dcmi_is_enabled; +} + +static const TypeInfo stm32_dcmi_type_info = { + .name = TYPE_STM32_DCMI, + .parent = TYPE_STM32_DCMI_PARENT, + .instance_init = stm32_dcmi_instance_init_callback, + .instance_size = sizeof(STM32DCMIState), + .class_init = stm32_dcmi_class_init_callback, + .class_size = sizeof(STM32DCMIClass) }; + +static void stm32_dcmi_register_types(void) +{ + type_register_static(&stm32_dcmi_type_info); +} + +type_init(stm32_dcmi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dcmi.h b/gnu-mcu-eclipse/devices/support/STM32F40x/dcmi.h new file mode 100644 index 0000000000..e42585bb2d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dcmi.h @@ -0,0 +1,204 @@ +/* + * STM32 - DCMI (Digital camera interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DCMI_H_ +#define STM32_DCMI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DCMI DEVICE_PATH_STM32 "DCMI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DCMI TYPE_STM32_PREFIX "dcmi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DCMI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DCMIParentClass; +typedef PeripheralState STM32DCMIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DCMI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DCMIClass, (obj), TYPE_STM32_DCMI) +#define STM32_DCMI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DCMIClass, (klass), TYPE_STM32_DCMI) + +typedef struct { + // private: + STM32DCMIParentClass parent_class; + // public: + + // None, so far. +} STM32DCMIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DCMI_STATE(obj) \ + OBJECT_CHECK(STM32DCMIState, (obj), TYPE_STM32_DCMI) + +typedef struct { + // private: + STM32DCMIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DCMI (Digital camera interface) registers. + struct { + Object *cr; // 0x0 (Control register 1) + Object *sr; // 0x4 (Status register) + Object *ris; // 0x8 (Raw interrupt status register) + Object *ier; // 0xC (Interrupt enable register) + Object *mis; // 0x10 (Masked interrupt status register) + Object *icr; // 0x14 (Interrupt clear register) + Object *escr; // 0x18 (Embedded synchronization code register) + Object *esur; // 0x1C (Embedded synchronization unmask register) + Object *cwstrt; // 0x20 (Crop window start) + Object *cwsize; // 0x24 (Crop window size) + Object *dr; // 0x28 (Data register) + } reg; + + struct { + + // CR (Control register 1) bitfields. + struct { + Object *capture; // [0:0] Capture enable + Object *cm; // [1:1] Capture mode + Object *crop; // [2:2] Crop feature + Object *jpeg; // [3:3] JPEG format + Object *ess; // [4:4] Embedded synchronization select + Object *pckpol; // [5:5] Pixel clock polarity + Object *hspol; // [6:6] Horizontal synchronization polarity + Object *vspol; // [7:7] Vertical synchronization polarity + Object *fcrc; // [8:9] Frame capture rate control + Object *edm; // [10:11] Extended data mode + Object *enable; // [14:14] DCMI enable + } cr; + + // SR (Status register) bitfields. + struct { + Object *hsync; // [0:0] HSYNC + Object *vsync; // [1:1] VSYNC + Object *fne; // [2:2] FIFO not empty + } sr; + + // RIS (Raw interrupt status register) bitfields. + struct { + Object *frame_ris; // [0:0] Capture complete raw interrupt status + Object *ovr_ris; // [1:1] Overrun raw interrupt status + Object *err_ris; // [2:2] Synchronization error raw interrupt status + Object *vsync_ris; // [3:3] VSYNC raw interrupt status + Object *line_ris; // [4:4] Line raw interrupt status + } ris; + + // IER (Interrupt enable register) bitfields. + struct { + Object *frame_ie; // [0:0] Capture complete interrupt enable + Object *ovr_ie; // [1:1] Overrun interrupt enable + Object *err_ie; // [2:2] Synchronization error interrupt enable + Object *vsync_ie; // [3:3] VSYNC interrupt enable + Object *line_ie; // [4:4] Line interrupt enable + } ier; + + // MIS (Masked interrupt status register) bitfields. + struct { + Object *frame_mis; // [0:0] Capture complete masked interrupt status + Object *ovr_mis; // [1:1] Overrun masked interrupt status + Object *err_mis; // [2:2] Synchronization error masked interrupt status + Object *vsync_mis; // [3:3] VSYNC masked interrupt status + Object *line_mis; // [4:4] Line masked interrupt status + } mis; + + // ICR (Interrupt clear register) bitfields. + struct { + Object *frame_isc; // [0:0] Capture complete interrupt status clear + Object *ovr_isc; // [1:1] Overrun interrupt status clear + Object *err_isc; // [2:2] Synchronization error interrupt status clear + Object *vsync_isc; // [3:3] Vertical synch interrupt status clear + Object *line_isc; // [4:4] Line interrupt status clear + } icr; + + // ESCR (Embedded synchronization code register) bitfields. + struct { + Object *fsc; // [0:7] Frame start delimiter code + Object *lsc; // [8:15] Line start delimiter code + Object *lec; // [16:23] Line end delimiter code + Object *fec; // [24:31] Frame end delimiter code + } escr; + + // ESUR (Embedded synchronization unmask register) bitfields. + struct { + Object *fsu; // [0:7] Frame start delimiter unmask + Object *lsu; // [8:15] Line start delimiter unmask + Object *leu; // [16:23] Line end delimiter unmask + Object *feu; // [24:31] Frame end delimiter unmask + } esur; + + // CWSTRT (Crop window start) bitfields. + struct { + Object *hoffcnt; // [0:13] Horizontal offset count + Object *vst; // [16:28] Vertical start line count + } cwstrt; + + // CWSIZE (Crop window size) bitfields. + struct { + Object *capcnt; // [0:13] Capture count + Object *vline; // [16:29] Vertical line count + } cwsize; + + // DR (Data register) bitfields. + struct { + Object *byte0; // [0:7] Data byte 0 + Object *byte1; // [8:15] Data byte 1 + Object *byte2; // [16:23] Data byte 2 + Object *byte3; // [24:31] Data byte 3 + } dr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DCMIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DCMI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dma2.c b/gnu-mcu-eclipse/devices/support/STM32F40x/dma2.c new file mode 100644 index 0000000000..29a8b08c1d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dma2.c @@ -0,0 +1,698 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.lisr = cm_object_get_child_by_name(obj, "LISR"); + state->u.f4.reg.hisr = cm_object_get_child_by_name(obj, "HISR"); + state->u.f4.reg.lifcr = cm_object_get_child_by_name(obj, "LIFCR"); + state->u.f4.reg.hifcr = cm_object_get_child_by_name(obj, "HIFCR"); + state->u.f4.reg.s0cr = cm_object_get_child_by_name(obj, "S0CR"); + state->u.f4.reg.s0ndtr = cm_object_get_child_by_name(obj, "S0NDTR"); + state->u.f4.reg.s0par = cm_object_get_child_by_name(obj, "S0PAR"); + state->u.f4.reg.s0m0ar = cm_object_get_child_by_name(obj, "S0M0AR"); + state->u.f4.reg.s0m1ar = cm_object_get_child_by_name(obj, "S0M1AR"); + state->u.f4.reg.s0fcr = cm_object_get_child_by_name(obj, "S0FCR"); + state->u.f4.reg.s1cr = cm_object_get_child_by_name(obj, "S1CR"); + state->u.f4.reg.s1ndtr = cm_object_get_child_by_name(obj, "S1NDTR"); + state->u.f4.reg.s1par = cm_object_get_child_by_name(obj, "S1PAR"); + state->u.f4.reg.s1m0ar = cm_object_get_child_by_name(obj, "S1M0AR"); + state->u.f4.reg.s1m1ar = cm_object_get_child_by_name(obj, "S1M1AR"); + state->u.f4.reg.s1fcr = cm_object_get_child_by_name(obj, "S1FCR"); + state->u.f4.reg.s2cr = cm_object_get_child_by_name(obj, "S2CR"); + state->u.f4.reg.s2ndtr = cm_object_get_child_by_name(obj, "S2NDTR"); + state->u.f4.reg.s2par = cm_object_get_child_by_name(obj, "S2PAR"); + state->u.f4.reg.s2m0ar = cm_object_get_child_by_name(obj, "S2M0AR"); + state->u.f4.reg.s2m1ar = cm_object_get_child_by_name(obj, "S2M1AR"); + state->u.f4.reg.s2fcr = cm_object_get_child_by_name(obj, "S2FCR"); + state->u.f4.reg.s3cr = cm_object_get_child_by_name(obj, "S3CR"); + state->u.f4.reg.s3ndtr = cm_object_get_child_by_name(obj, "S3NDTR"); + state->u.f4.reg.s3par = cm_object_get_child_by_name(obj, "S3PAR"); + state->u.f4.reg.s3m0ar = cm_object_get_child_by_name(obj, "S3M0AR"); + state->u.f4.reg.s3m1ar = cm_object_get_child_by_name(obj, "S3M1AR"); + state->u.f4.reg.s3fcr = cm_object_get_child_by_name(obj, "S3FCR"); + state->u.f4.reg.s4cr = cm_object_get_child_by_name(obj, "S4CR"); + state->u.f4.reg.s4ndtr = cm_object_get_child_by_name(obj, "S4NDTR"); + state->u.f4.reg.s4par = cm_object_get_child_by_name(obj, "S4PAR"); + state->u.f4.reg.s4m0ar = cm_object_get_child_by_name(obj, "S4M0AR"); + state->u.f4.reg.s4m1ar = cm_object_get_child_by_name(obj, "S4M1AR"); + state->u.f4.reg.s4fcr = cm_object_get_child_by_name(obj, "S4FCR"); + state->u.f4.reg.s5cr = cm_object_get_child_by_name(obj, "S5CR"); + state->u.f4.reg.s5ndtr = cm_object_get_child_by_name(obj, "S5NDTR"); + state->u.f4.reg.s5par = cm_object_get_child_by_name(obj, "S5PAR"); + state->u.f4.reg.s5m0ar = cm_object_get_child_by_name(obj, "S5M0AR"); + state->u.f4.reg.s5m1ar = cm_object_get_child_by_name(obj, "S5M1AR"); + state->u.f4.reg.s5fcr = cm_object_get_child_by_name(obj, "S5FCR"); + state->u.f4.reg.s6cr = cm_object_get_child_by_name(obj, "S6CR"); + state->u.f4.reg.s6ndtr = cm_object_get_child_by_name(obj, "S6NDTR"); + state->u.f4.reg.s6par = cm_object_get_child_by_name(obj, "S6PAR"); + state->u.f4.reg.s6m0ar = cm_object_get_child_by_name(obj, "S6M0AR"); + state->u.f4.reg.s6m1ar = cm_object_get_child_by_name(obj, "S6M1AR"); + state->u.f4.reg.s6fcr = cm_object_get_child_by_name(obj, "S6FCR"); + state->u.f4.reg.s7cr = cm_object_get_child_by_name(obj, "S7CR"); + state->u.f4.reg.s7ndtr = cm_object_get_child_by_name(obj, "S7NDTR"); + state->u.f4.reg.s7par = cm_object_get_child_by_name(obj, "S7PAR"); + state->u.f4.reg.s7m0ar = cm_object_get_child_by_name(obj, "S7M0AR"); + state->u.f4.reg.s7m1ar = cm_object_get_child_by_name(obj, "S7M1AR"); + state->u.f4.reg.s7fcr = cm_object_get_child_by_name(obj, "S7FCR"); + + + // LISR bitfields. + state->u.f4.fld.lisr.feif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF0"); + state->u.f4.fld.lisr.dmeif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF0"); + state->u.f4.fld.lisr.teif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF0"); + state->u.f4.fld.lisr.htif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF0"); + state->u.f4.fld.lisr.tcif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF0"); + state->u.f4.fld.lisr.feif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF1"); + state->u.f4.fld.lisr.dmeif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF1"); + state->u.f4.fld.lisr.teif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF1"); + state->u.f4.fld.lisr.htif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF1"); + state->u.f4.fld.lisr.tcif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF1"); + state->u.f4.fld.lisr.feif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF2"); + state->u.f4.fld.lisr.dmeif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF2"); + state->u.f4.fld.lisr.teif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF2"); + state->u.f4.fld.lisr.htif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF2"); + state->u.f4.fld.lisr.tcif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF2"); + state->u.f4.fld.lisr.feif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF3"); + state->u.f4.fld.lisr.dmeif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF3"); + state->u.f4.fld.lisr.teif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF3"); + state->u.f4.fld.lisr.htif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF3"); + state->u.f4.fld.lisr.tcif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF3"); + + // HISR bitfields. + state->u.f4.fld.hisr.feif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF4"); + state->u.f4.fld.hisr.dmeif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF4"); + state->u.f4.fld.hisr.teif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF4"); + state->u.f4.fld.hisr.htif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF4"); + state->u.f4.fld.hisr.tcif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF4"); + state->u.f4.fld.hisr.feif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF5"); + state->u.f4.fld.hisr.dmeif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF5"); + state->u.f4.fld.hisr.teif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF5"); + state->u.f4.fld.hisr.htif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF5"); + state->u.f4.fld.hisr.tcif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF5"); + state->u.f4.fld.hisr.feif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF6"); + state->u.f4.fld.hisr.dmeif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF6"); + state->u.f4.fld.hisr.teif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF6"); + state->u.f4.fld.hisr.htif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF6"); + state->u.f4.fld.hisr.tcif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF6"); + state->u.f4.fld.hisr.feif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF7"); + state->u.f4.fld.hisr.dmeif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF7"); + state->u.f4.fld.hisr.teif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF7"); + state->u.f4.fld.hisr.htif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF7"); + state->u.f4.fld.hisr.tcif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF7"); + + // LIFCR bitfields. + state->u.f4.fld.lifcr.cfeif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF0"); + state->u.f4.fld.lifcr.cdmeif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF0"); + state->u.f4.fld.lifcr.cteif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF0"); + state->u.f4.fld.lifcr.chtif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF0"); + state->u.f4.fld.lifcr.ctcif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF0"); + state->u.f4.fld.lifcr.cfeif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF1"); + state->u.f4.fld.lifcr.cdmeif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF1"); + state->u.f4.fld.lifcr.cteif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF1"); + state->u.f4.fld.lifcr.chtif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF1"); + state->u.f4.fld.lifcr.ctcif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF1"); + state->u.f4.fld.lifcr.cfeif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF2"); + state->u.f4.fld.lifcr.cdmeif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF2"); + state->u.f4.fld.lifcr.cteif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF2"); + state->u.f4.fld.lifcr.chtif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF2"); + state->u.f4.fld.lifcr.ctcif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF2"); + state->u.f4.fld.lifcr.cfeif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF3"); + state->u.f4.fld.lifcr.cdmeif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF3"); + state->u.f4.fld.lifcr.cteif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF3"); + state->u.f4.fld.lifcr.chtif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF3"); + state->u.f4.fld.lifcr.ctcif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF3"); + + // HIFCR bitfields. + state->u.f4.fld.hifcr.cfeif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF4"); + state->u.f4.fld.hifcr.cdmeif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF4"); + state->u.f4.fld.hifcr.cteif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF4"); + state->u.f4.fld.hifcr.chtif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF4"); + state->u.f4.fld.hifcr.ctcif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF4"); + state->u.f4.fld.hifcr.cfeif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF5"); + state->u.f4.fld.hifcr.cdmeif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF5"); + state->u.f4.fld.hifcr.cteif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF5"); + state->u.f4.fld.hifcr.chtif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF5"); + state->u.f4.fld.hifcr.ctcif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF5"); + state->u.f4.fld.hifcr.cfeif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF6"); + state->u.f4.fld.hifcr.cdmeif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF6"); + state->u.f4.fld.hifcr.cteif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF6"); + state->u.f4.fld.hifcr.chtif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF6"); + state->u.f4.fld.hifcr.ctcif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF6"); + state->u.f4.fld.hifcr.cfeif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF7"); + state->u.f4.fld.hifcr.cdmeif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF7"); + state->u.f4.fld.hifcr.cteif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF7"); + state->u.f4.fld.hifcr.chtif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF7"); + state->u.f4.fld.hifcr.ctcif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF7"); + + // S0CR bitfields. + state->u.f4.fld.s0cr.en = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "EN"); + state->u.f4.fld.s0cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DMEIE"); + state->u.f4.fld.s0cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "TEIE"); + state->u.f4.fld.s0cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "HTIE"); + state->u.f4.fld.s0cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "TCIE"); + state->u.f4.fld.s0cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PFCTRL"); + state->u.f4.fld.s0cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DIR"); + state->u.f4.fld.s0cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CIRC"); + state->u.f4.fld.s0cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PINC"); + state->u.f4.fld.s0cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MINC"); + state->u.f4.fld.s0cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PSIZE"); + state->u.f4.fld.s0cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MSIZE"); + state->u.f4.fld.s0cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PINCOS"); + state->u.f4.fld.s0cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PL"); + state->u.f4.fld.s0cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DBM"); + state->u.f4.fld.s0cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CT"); + state->u.f4.fld.s0cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PBURST"); + state->u.f4.fld.s0cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MBURST"); + state->u.f4.fld.s0cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CHSEL"); + + // S0NDTR bitfields. + state->u.f4.fld.s0ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s0ndtr, "NDT"); + + // S0PAR bitfields. + state->u.f4.fld.s0par.pa = cm_object_get_child_by_name(state->u.f4.reg.s0par, "PA"); + + // S0M0AR bitfields. + state->u.f4.fld.s0m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s0m0ar, "M0A"); + + // S0M1AR bitfields. + state->u.f4.fld.s0m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s0m1ar, "M1A"); + + // S0FCR bitfields. + state->u.f4.fld.s0fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FTH"); + state->u.f4.fld.s0fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "DMDIS"); + state->u.f4.fld.s0fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FS"); + state->u.f4.fld.s0fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FEIE"); + + // S1CR bitfields. + state->u.f4.fld.s1cr.en = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "EN"); + state->u.f4.fld.s1cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DMEIE"); + state->u.f4.fld.s1cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "TEIE"); + state->u.f4.fld.s1cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "HTIE"); + state->u.f4.fld.s1cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "TCIE"); + state->u.f4.fld.s1cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PFCTRL"); + state->u.f4.fld.s1cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DIR"); + state->u.f4.fld.s1cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CIRC"); + state->u.f4.fld.s1cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PINC"); + state->u.f4.fld.s1cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MINC"); + state->u.f4.fld.s1cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PSIZE"); + state->u.f4.fld.s1cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MSIZE"); + state->u.f4.fld.s1cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PINCOS"); + state->u.f4.fld.s1cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PL"); + state->u.f4.fld.s1cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DBM"); + state->u.f4.fld.s1cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CT"); + state->u.f4.fld.s1cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "ACK"); + state->u.f4.fld.s1cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PBURST"); + state->u.f4.fld.s1cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MBURST"); + state->u.f4.fld.s1cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CHSEL"); + + // S1NDTR bitfields. + state->u.f4.fld.s1ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s1ndtr, "NDT"); + + // S1PAR bitfields. + state->u.f4.fld.s1par.pa = cm_object_get_child_by_name(state->u.f4.reg.s1par, "PA"); + + // S1M0AR bitfields. + state->u.f4.fld.s1m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s1m0ar, "M0A"); + + // S1M1AR bitfields. + state->u.f4.fld.s1m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s1m1ar, "M1A"); + + // S1FCR bitfields. + state->u.f4.fld.s1fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FTH"); + state->u.f4.fld.s1fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "DMDIS"); + state->u.f4.fld.s1fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FS"); + state->u.f4.fld.s1fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FEIE"); + + // S2CR bitfields. + state->u.f4.fld.s2cr.en = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "EN"); + state->u.f4.fld.s2cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DMEIE"); + state->u.f4.fld.s2cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "TEIE"); + state->u.f4.fld.s2cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "HTIE"); + state->u.f4.fld.s2cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "TCIE"); + state->u.f4.fld.s2cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PFCTRL"); + state->u.f4.fld.s2cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DIR"); + state->u.f4.fld.s2cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CIRC"); + state->u.f4.fld.s2cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PINC"); + state->u.f4.fld.s2cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MINC"); + state->u.f4.fld.s2cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PSIZE"); + state->u.f4.fld.s2cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MSIZE"); + state->u.f4.fld.s2cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PINCOS"); + state->u.f4.fld.s2cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PL"); + state->u.f4.fld.s2cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DBM"); + state->u.f4.fld.s2cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CT"); + state->u.f4.fld.s2cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "ACK"); + state->u.f4.fld.s2cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PBURST"); + state->u.f4.fld.s2cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MBURST"); + state->u.f4.fld.s2cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CHSEL"); + + // S2NDTR bitfields. + state->u.f4.fld.s2ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s2ndtr, "NDT"); + + // S2PAR bitfields. + state->u.f4.fld.s2par.pa = cm_object_get_child_by_name(state->u.f4.reg.s2par, "PA"); + + // S2M0AR bitfields. + state->u.f4.fld.s2m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s2m0ar, "M0A"); + + // S2M1AR bitfields. + state->u.f4.fld.s2m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s2m1ar, "M1A"); + + // S2FCR bitfields. + state->u.f4.fld.s2fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FTH"); + state->u.f4.fld.s2fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "DMDIS"); + state->u.f4.fld.s2fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FS"); + state->u.f4.fld.s2fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FEIE"); + + // S3CR bitfields. + state->u.f4.fld.s3cr.en = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "EN"); + state->u.f4.fld.s3cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DMEIE"); + state->u.f4.fld.s3cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "TEIE"); + state->u.f4.fld.s3cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "HTIE"); + state->u.f4.fld.s3cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "TCIE"); + state->u.f4.fld.s3cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PFCTRL"); + state->u.f4.fld.s3cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DIR"); + state->u.f4.fld.s3cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CIRC"); + state->u.f4.fld.s3cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PINC"); + state->u.f4.fld.s3cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MINC"); + state->u.f4.fld.s3cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PSIZE"); + state->u.f4.fld.s3cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MSIZE"); + state->u.f4.fld.s3cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PINCOS"); + state->u.f4.fld.s3cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PL"); + state->u.f4.fld.s3cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DBM"); + state->u.f4.fld.s3cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CT"); + state->u.f4.fld.s3cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "ACK"); + state->u.f4.fld.s3cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PBURST"); + state->u.f4.fld.s3cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MBURST"); + state->u.f4.fld.s3cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CHSEL"); + + // S3NDTR bitfields. + state->u.f4.fld.s3ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s3ndtr, "NDT"); + + // S3PAR bitfields. + state->u.f4.fld.s3par.pa = cm_object_get_child_by_name(state->u.f4.reg.s3par, "PA"); + + // S3M0AR bitfields. + state->u.f4.fld.s3m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s3m0ar, "M0A"); + + // S3M1AR bitfields. + state->u.f4.fld.s3m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s3m1ar, "M1A"); + + // S3FCR bitfields. + state->u.f4.fld.s3fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FTH"); + state->u.f4.fld.s3fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "DMDIS"); + state->u.f4.fld.s3fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FS"); + state->u.f4.fld.s3fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FEIE"); + + // S4CR bitfields. + state->u.f4.fld.s4cr.en = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "EN"); + state->u.f4.fld.s4cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DMEIE"); + state->u.f4.fld.s4cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "TEIE"); + state->u.f4.fld.s4cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "HTIE"); + state->u.f4.fld.s4cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "TCIE"); + state->u.f4.fld.s4cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PFCTRL"); + state->u.f4.fld.s4cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DIR"); + state->u.f4.fld.s4cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CIRC"); + state->u.f4.fld.s4cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PINC"); + state->u.f4.fld.s4cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MINC"); + state->u.f4.fld.s4cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PSIZE"); + state->u.f4.fld.s4cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MSIZE"); + state->u.f4.fld.s4cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PINCOS"); + state->u.f4.fld.s4cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PL"); + state->u.f4.fld.s4cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DBM"); + state->u.f4.fld.s4cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CT"); + state->u.f4.fld.s4cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "ACK"); + state->u.f4.fld.s4cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PBURST"); + state->u.f4.fld.s4cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MBURST"); + state->u.f4.fld.s4cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CHSEL"); + + // S4NDTR bitfields. + state->u.f4.fld.s4ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s4ndtr, "NDT"); + + // S4PAR bitfields. + state->u.f4.fld.s4par.pa = cm_object_get_child_by_name(state->u.f4.reg.s4par, "PA"); + + // S4M0AR bitfields. + state->u.f4.fld.s4m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s4m0ar, "M0A"); + + // S4M1AR bitfields. + state->u.f4.fld.s4m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s4m1ar, "M1A"); + + // S4FCR bitfields. + state->u.f4.fld.s4fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FTH"); + state->u.f4.fld.s4fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "DMDIS"); + state->u.f4.fld.s4fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FS"); + state->u.f4.fld.s4fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FEIE"); + + // S5CR bitfields. + state->u.f4.fld.s5cr.en = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "EN"); + state->u.f4.fld.s5cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DMEIE"); + state->u.f4.fld.s5cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "TEIE"); + state->u.f4.fld.s5cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "HTIE"); + state->u.f4.fld.s5cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "TCIE"); + state->u.f4.fld.s5cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PFCTRL"); + state->u.f4.fld.s5cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DIR"); + state->u.f4.fld.s5cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CIRC"); + state->u.f4.fld.s5cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PINC"); + state->u.f4.fld.s5cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MINC"); + state->u.f4.fld.s5cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PSIZE"); + state->u.f4.fld.s5cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MSIZE"); + state->u.f4.fld.s5cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PINCOS"); + state->u.f4.fld.s5cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PL"); + state->u.f4.fld.s5cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DBM"); + state->u.f4.fld.s5cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CT"); + state->u.f4.fld.s5cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "ACK"); + state->u.f4.fld.s5cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PBURST"); + state->u.f4.fld.s5cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MBURST"); + state->u.f4.fld.s5cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CHSEL"); + + // S5NDTR bitfields. + state->u.f4.fld.s5ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s5ndtr, "NDT"); + + // S5PAR bitfields. + state->u.f4.fld.s5par.pa = cm_object_get_child_by_name(state->u.f4.reg.s5par, "PA"); + + // S5M0AR bitfields. + state->u.f4.fld.s5m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s5m0ar, "M0A"); + + // S5M1AR bitfields. + state->u.f4.fld.s5m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s5m1ar, "M1A"); + + // S5FCR bitfields. + state->u.f4.fld.s5fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FTH"); + state->u.f4.fld.s5fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "DMDIS"); + state->u.f4.fld.s5fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FS"); + state->u.f4.fld.s5fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FEIE"); + + // S6CR bitfields. + state->u.f4.fld.s6cr.en = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "EN"); + state->u.f4.fld.s6cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DMEIE"); + state->u.f4.fld.s6cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "TEIE"); + state->u.f4.fld.s6cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "HTIE"); + state->u.f4.fld.s6cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "TCIE"); + state->u.f4.fld.s6cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PFCTRL"); + state->u.f4.fld.s6cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DIR"); + state->u.f4.fld.s6cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CIRC"); + state->u.f4.fld.s6cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PINC"); + state->u.f4.fld.s6cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MINC"); + state->u.f4.fld.s6cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PSIZE"); + state->u.f4.fld.s6cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MSIZE"); + state->u.f4.fld.s6cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PINCOS"); + state->u.f4.fld.s6cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PL"); + state->u.f4.fld.s6cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DBM"); + state->u.f4.fld.s6cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CT"); + state->u.f4.fld.s6cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "ACK"); + state->u.f4.fld.s6cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PBURST"); + state->u.f4.fld.s6cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MBURST"); + state->u.f4.fld.s6cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CHSEL"); + + // S6NDTR bitfields. + state->u.f4.fld.s6ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s6ndtr, "NDT"); + + // S6PAR bitfields. + state->u.f4.fld.s6par.pa = cm_object_get_child_by_name(state->u.f4.reg.s6par, "PA"); + + // S6M0AR bitfields. + state->u.f4.fld.s6m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s6m0ar, "M0A"); + + // S6M1AR bitfields. + state->u.f4.fld.s6m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s6m1ar, "M1A"); + + // S6FCR bitfields. + state->u.f4.fld.s6fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FTH"); + state->u.f4.fld.s6fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "DMDIS"); + state->u.f4.fld.s6fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FS"); + state->u.f4.fld.s6fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FEIE"); + + // S7CR bitfields. + state->u.f4.fld.s7cr.en = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "EN"); + state->u.f4.fld.s7cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DMEIE"); + state->u.f4.fld.s7cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "TEIE"); + state->u.f4.fld.s7cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "HTIE"); + state->u.f4.fld.s7cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "TCIE"); + state->u.f4.fld.s7cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PFCTRL"); + state->u.f4.fld.s7cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DIR"); + state->u.f4.fld.s7cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CIRC"); + state->u.f4.fld.s7cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PINC"); + state->u.f4.fld.s7cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MINC"); + state->u.f4.fld.s7cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PSIZE"); + state->u.f4.fld.s7cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MSIZE"); + state->u.f4.fld.s7cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PINCOS"); + state->u.f4.fld.s7cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PL"); + state->u.f4.fld.s7cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DBM"); + state->u.f4.fld.s7cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CT"); + state->u.f4.fld.s7cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "ACK"); + state->u.f4.fld.s7cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PBURST"); + state->u.f4.fld.s7cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MBURST"); + state->u.f4.fld.s7cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CHSEL"); + + // S7NDTR bitfields. + state->u.f4.fld.s7ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s7ndtr, "NDT"); + + // S7PAR bitfields. + state->u.f4.fld.s7par.pa = cm_object_get_child_by_name(state->u.f4.reg.s7par, "PA"); + + // S7M0AR bitfields. + state->u.f4.fld.s7m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s7m0ar, "M0A"); + + // S7M1AR bitfields. + state->u.f4.fld.s7m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s7m1ar, "M1A"); + + // S7FCR bitfields. + state->u.f4.fld.s7fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FTH"); + state->u.f4.fld.s7fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "DMDIS"); + state->u.f4.fld.s7fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FS"); + state->u.f4.fld.s7fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FEIE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma_is_enabled(Object *obj) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMAState *state = STM32_DMA_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_DMA_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMAState *state = STM32_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA%dEN", + 1 + state->port_index - STM32_PORT_DMA1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA); +} + +static void stm32_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma_reset_callback; + dc->realize = stm32_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma_is_enabled; +} + +static const TypeInfo stm32_dma_type_info = { + .name = TYPE_STM32_DMA, + .parent = TYPE_STM32_DMA_PARENT, + .instance_init = stm32_dma_instance_init_callback, + .instance_size = sizeof(STM32DMAState), + .class_init = stm32_dma_class_init_callback, + .class_size = sizeof(STM32DMAClass) }; + +static void stm32_dma_register_types(void) +{ + type_register_static(&stm32_dma_type_info); +} + +type_init(stm32_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/dma2.h b/gnu-mcu-eclipse/devices/support/STM32F40x/dma2.h new file mode 100644 index 0000000000..b8356b45c9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/dma2.h @@ -0,0 +1,673 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA_H_ +#define STM32_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMA DEVICE_PATH_STM32 "DMA" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_DMA1, + STM32_PORT_DMA2, + STM32_PORT_DMA_UNDEFINED = 0xFF, +} stm32_dma_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMA TYPE_STM32_PREFIX "dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMAParentClass; +typedef PeripheralState STM32DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMAClass, (obj), TYPE_STM32_DMA) +#define STM32_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMAClass, (klass), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentClass parent_class; + // public: + + // None, so far. +} STM32DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA_STATE(obj) \ + OBJECT_CHECK(STM32DMAState, (obj), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_dma_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DMA (DMA controller) registers. + struct { + Object *lisr; // 0x0 (Low interrupt status register) + Object *hisr; // 0x4 (High interrupt status register) + Object *lifcr; // 0x8 (Low interrupt flag clear register) + Object *hifcr; // 0xC (High interrupt flag clear register) + Object *s0cr; // 0x10 (Stream x configuration register) + Object *s0ndtr; // 0x14 (Stream x number of data register) + Object *s0par; // 0x18 (Stream x peripheral address register) + Object *s0m0ar; // 0x1C (Stream x memory 0 address register) + Object *s0m1ar; // 0x20 (Stream x memory 1 address register) + Object *s0fcr; // 0x24 (Stream x FIFO control register) + Object *s1cr; // 0x28 (Stream x configuration register) + Object *s1ndtr; // 0x2C (Stream x number of data register) + Object *s1par; // 0x30 (Stream x peripheral address register) + Object *s1m0ar; // 0x34 (Stream x memory 0 address register) + Object *s1m1ar; // 0x38 (Stream x memory 1 address register) + Object *s1fcr; // 0x3C (Stream x FIFO control register) + Object *s2cr; // 0x40 (Stream x configuration register) + Object *s2ndtr; // 0x44 (Stream x number of data register) + Object *s2par; // 0x48 (Stream x peripheral address register) + Object *s2m0ar; // 0x4C (Stream x memory 0 address register) + Object *s2m1ar; // 0x50 (Stream x memory 1 address register) + Object *s2fcr; // 0x54 (Stream x FIFO control register) + Object *s3cr; // 0x58 (Stream x configuration register) + Object *s3ndtr; // 0x5C (Stream x number of data register) + Object *s3par; // 0x60 (Stream x peripheral address register) + Object *s3m0ar; // 0x64 (Stream x memory 0 address register) + Object *s3m1ar; // 0x68 (Stream x memory 1 address register) + Object *s3fcr; // 0x6C (Stream x FIFO control register) + Object *s4cr; // 0x70 (Stream x configuration register) + Object *s4ndtr; // 0x74 (Stream x number of data register) + Object *s4par; // 0x78 (Stream x peripheral address register) + Object *s4m0ar; // 0x7C (Stream x memory 0 address register) + Object *s4m1ar; // 0x80 (Stream x memory 1 address register) + Object *s4fcr; // 0x84 (Stream x FIFO control register) + Object *s5cr; // 0x88 (Stream x configuration register) + Object *s5ndtr; // 0x8C (Stream x number of data register) + Object *s5par; // 0x90 (Stream x peripheral address register) + Object *s5m0ar; // 0x94 (Stream x memory 0 address register) + Object *s5m1ar; // 0x98 (Stream x memory 1 address register) + Object *s5fcr; // 0x9C (Stream x FIFO control register) + Object *s6cr; // 0xA0 (Stream x configuration register) + Object *s6ndtr; // 0xA4 (Stream x number of data register) + Object *s6par; // 0xA8 (Stream x peripheral address register) + Object *s6m0ar; // 0xAC (Stream x memory 0 address register) + Object *s6m1ar; // 0xB0 (Stream x memory 1 address register) + Object *s6fcr; // 0xB4 (Stream x FIFO control register) + Object *s7cr; // 0xB8 (Stream x configuration register) + Object *s7ndtr; // 0xBC (Stream x number of data register) + Object *s7par; // 0xC0 (Stream x peripheral address register) + Object *s7m0ar; // 0xC4 (Stream x memory 0 address register) + Object *s7m1ar; // 0xC8 (Stream x memory 1 address register) + Object *s7fcr; // 0xCC (Stream x FIFO control register) + } reg; + + struct { + + // LISR (Low interrupt status register) bitfields. + struct { + Object *feif0; // [0:0] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif0; // [2:2] Stream x direct mode error interrupt flag (x=3..0) + Object *teif0; // [3:3] Stream x transfer error interrupt flag (x=3..0) + Object *htif0; // [4:4] Stream x half transfer interrupt flag (x=3..0) + Object *tcif0; // [5:5] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif1; // [6:6] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif1; // [8:8] Stream x direct mode error interrupt flag (x=3..0) + Object *teif1; // [9:9] Stream x transfer error interrupt flag (x=3..0) + Object *htif1; // [10:10] Stream x half transfer interrupt flag (x=3..0) + Object *tcif1; // [11:11] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif2; // [16:16] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif2; // [18:18] Stream x direct mode error interrupt flag (x=3..0) + Object *teif2; // [19:19] Stream x transfer error interrupt flag (x=3..0) + Object *htif2; // [20:20] Stream x half transfer interrupt flag (x=3..0) + Object *tcif2; // [21:21] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif3; // [22:22] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif3; // [24:24] Stream x direct mode error interrupt flag (x=3..0) + Object *teif3; // [25:25] Stream x transfer error interrupt flag (x=3..0) + Object *htif3; // [26:26] Stream x half transfer interrupt flag (x=3..0) + Object *tcif3; // [27:27] Stream x transfer complete interrupt flag (x = 3..0) + } lisr; + + // HISR (High interrupt status register) bitfields. + struct { + Object *feif4; // [0:0] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif4; // [2:2] Stream x direct mode error interrupt flag (x=7..4) + Object *teif4; // [3:3] Stream x transfer error interrupt flag (x=7..4) + Object *htif4; // [4:4] Stream x half transfer interrupt flag (x=7..4) + Object *tcif4; // [5:5] Stream x transfer complete interrupt flag (x=7..4) + Object *feif5; // [6:6] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif5; // [8:8] Stream x direct mode error interrupt flag (x=7..4) + Object *teif5; // [9:9] Stream x transfer error interrupt flag (x=7..4) + Object *htif5; // [10:10] Stream x half transfer interrupt flag (x=7..4) + Object *tcif5; // [11:11] Stream x transfer complete interrupt flag (x=7..4) + Object *feif6; // [16:16] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif6; // [18:18] Stream x direct mode error interrupt flag (x=7..4) + Object *teif6; // [19:19] Stream x transfer error interrupt flag (x=7..4) + Object *htif6; // [20:20] Stream x half transfer interrupt flag (x=7..4) + Object *tcif6; // [21:21] Stream x transfer complete interrupt flag (x=7..4) + Object *feif7; // [22:22] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif7; // [24:24] Stream x direct mode error interrupt flag (x=7..4) + Object *teif7; // [25:25] Stream x transfer error interrupt flag (x=7..4) + Object *htif7; // [26:26] Stream x half transfer interrupt flag (x=7..4) + Object *tcif7; // [27:27] Stream x transfer complete interrupt flag (x=7..4) + } hisr; + + // LIFCR (Low interrupt flag clear register) bitfields. + struct { + Object *cfeif0; // [0:0] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif0; // [2:2] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif0; // [3:3] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif0; // [4:4] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif0; // [5:5] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif1; // [6:6] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif1; // [8:8] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif1; // [9:9] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif1; // [10:10] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif1; // [11:11] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif2; // [16:16] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif2; // [18:18] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif2; // [19:19] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif2; // [20:20] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif2; // [21:21] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif3; // [22:22] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif3; // [24:24] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif3; // [25:25] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif3; // [26:26] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif3; // [27:27] Stream x clear transfer complete interrupt flag (x = 3..0) + } lifcr; + + // HIFCR (High interrupt flag clear register) bitfields. + struct { + Object *cfeif4; // [0:0] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif4; // [2:2] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif4; // [3:3] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif4; // [4:4] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif4; // [5:5] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif5; // [6:6] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif5; // [8:8] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif5; // [9:9] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif5; // [10:10] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif5; // [11:11] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif6; // [16:16] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif6; // [18:18] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif6; // [19:19] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif6; // [20:20] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif6; // [21:21] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif7; // [22:22] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif7; // [24:24] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif7; // [25:25] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif7; // [26:26] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif7; // [27:27] Stream x clear transfer complete interrupt flag (x = 7..4) + } hifcr; + + // S0CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s0cr; + + // S0NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s0ndtr; + + // S0PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s0par; + + // S0M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s0m0ar; + + // S0M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s0m1ar; + + // S0FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s0fcr; + + // S1CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s1cr; + + // S1NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s1ndtr; + + // S1PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s1par; + + // S1M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s1m0ar; + + // S1M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s1m1ar; + + // S1FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s1fcr; + + // S2CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s2cr; + + // S2NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s2ndtr; + + // S2PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s2par; + + // S2M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s2m0ar; + + // S2M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s2m1ar; + + // S2FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s2fcr; + + // S3CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s3cr; + + // S3NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s3ndtr; + + // S3PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s3par; + + // S3M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s3m0ar; + + // S3M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s3m1ar; + + // S3FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s3fcr; + + // S4CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s4cr; + + // S4NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s4ndtr; + + // S4PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s4par; + + // S4M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s4m0ar; + + // S4M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s4m1ar; + + // S4FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s4fcr; + + // S5CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s5cr; + + // S5NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s5ndtr; + + // S5PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s5par; + + // S5M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s5m0ar; + + // S5M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s5m1ar; + + // S5FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s5fcr; + + // S6CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s6cr; + + // S6NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s6ndtr; + + // S6PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s6par; + + // S6M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s6m0ar; + + // S6M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s6m1ar; + + // S6FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s6fcr; + + // S7CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s7cr; + + // S7NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s7ndtr; + + // S7PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s7par; + + // S7M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s7m0ar; + + // S7M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s7m1ar; + + // S7FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s7fcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_dma.c b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_dma.c new file mode 100644 index 0000000000..a2ffee8042 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_dma.c @@ -0,0 +1,349 @@ +/* + * STM32 - Ethernet_DMA (Ethernet: DMA controller operation) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_ethernet_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dmabmr = cm_object_get_child_by_name(obj, "DMABMR"); + state->u.f4.reg.dmatpdr = cm_object_get_child_by_name(obj, "DMATPDR"); + state->u.f4.reg.dmarpdr = cm_object_get_child_by_name(obj, "DMARPDR"); + state->u.f4.reg.dmardlar = cm_object_get_child_by_name(obj, "DMARDLAR"); + state->u.f4.reg.dmatdlar = cm_object_get_child_by_name(obj, "DMATDLAR"); + state->u.f4.reg.dmasr = cm_object_get_child_by_name(obj, "DMASR"); + state->u.f4.reg.dmaomr = cm_object_get_child_by_name(obj, "DMAOMR"); + state->u.f4.reg.dmaier = cm_object_get_child_by_name(obj, "DMAIER"); + state->u.f4.reg.dmamfbocr = cm_object_get_child_by_name(obj, "DMAMFBOCR"); + state->u.f4.reg.dmarswtr = cm_object_get_child_by_name(obj, "DMARSWTR"); + state->u.f4.reg.dmachtdr = cm_object_get_child_by_name(obj, "DMACHTDR"); + state->u.f4.reg.dmachrdr = cm_object_get_child_by_name(obj, "DMACHRDR"); + state->u.f4.reg.dmachtbar = cm_object_get_child_by_name(obj, "DMACHTBAR"); + state->u.f4.reg.dmachrbar = cm_object_get_child_by_name(obj, "DMACHRBAR"); + + + // DMABMR bitfields. + state->u.f4.fld.dmabmr.sr = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "SR"); + state->u.f4.fld.dmabmr.da = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "DA"); + state->u.f4.fld.dmabmr.dsl = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "DSL"); + state->u.f4.fld.dmabmr.edfe = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "EDFE"); + state->u.f4.fld.dmabmr.pbl = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "PBL"); + state->u.f4.fld.dmabmr.rtpr = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "RTPR"); + state->u.f4.fld.dmabmr.fb = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "FB"); + state->u.f4.fld.dmabmr.rdp = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "RDP"); + state->u.f4.fld.dmabmr.usp = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "USP"); + state->u.f4.fld.dmabmr.fpm = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "FPM"); + state->u.f4.fld.dmabmr.aab = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "AAB"); + state->u.f4.fld.dmabmr.mb = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "MB"); + + // DMATPDR bitfields. + state->u.f4.fld.dmatpdr.tpd = cm_object_get_child_by_name(state->u.f4.reg.dmatpdr, "TPD"); + + // DMARPDR bitfields. + state->u.f4.fld.dmarpdr.rpd = cm_object_get_child_by_name(state->u.f4.reg.dmarpdr, "RPD"); + + // DMARDLAR bitfields. + state->u.f4.fld.dmardlar.srl = cm_object_get_child_by_name(state->u.f4.reg.dmardlar, "SRL"); + + // DMATDLAR bitfields. + state->u.f4.fld.dmatdlar.stl = cm_object_get_child_by_name(state->u.f4.reg.dmatdlar, "STL"); + + // DMASR bitfields. + state->u.f4.fld.dmasr.ts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TS"); + state->u.f4.fld.dmasr.tpss = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TPSS"); + state->u.f4.fld.dmasr.tbus = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TBUS"); + state->u.f4.fld.dmasr.tjts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TJTS"); + state->u.f4.fld.dmasr.ros = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "ROS"); + state->u.f4.fld.dmasr.tus = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TUS"); + state->u.f4.fld.dmasr.rs = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RS"); + state->u.f4.fld.dmasr.rbus = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RBUS"); + state->u.f4.fld.dmasr.rpss = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RPSS"); + state->u.f4.fld.dmasr.pwts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "PWTS"); + state->u.f4.fld.dmasr.ets = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "ETS"); + state->u.f4.fld.dmasr.fbes = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "FBES"); + state->u.f4.fld.dmasr.ers = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "ERS"); + state->u.f4.fld.dmasr.ais = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "AIS"); + state->u.f4.fld.dmasr.nis = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "NIS"); + state->u.f4.fld.dmasr.rps = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RPS"); + state->u.f4.fld.dmasr.tps = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TPS"); + state->u.f4.fld.dmasr.ebs = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "EBS"); + state->u.f4.fld.dmasr.mmcs = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "MMCS"); + state->u.f4.fld.dmasr.pmts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "PMTS"); + state->u.f4.fld.dmasr.tsts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TSTS"); + + // DMAOMR bitfields. + state->u.f4.fld.dmaomr.sr = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "SR"); + state->u.f4.fld.dmaomr.osf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "OSF"); + state->u.f4.fld.dmaomr.rtc = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "RTC"); + state->u.f4.fld.dmaomr.fugf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "FUGF"); + state->u.f4.fld.dmaomr.fef = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "FEF"); + state->u.f4.fld.dmaomr.st = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "ST"); + state->u.f4.fld.dmaomr.ttc = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "TTC"); + state->u.f4.fld.dmaomr.ftf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "FTF"); + state->u.f4.fld.dmaomr.tsf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "TSF"); + state->u.f4.fld.dmaomr.dfrf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "DFRF"); + state->u.f4.fld.dmaomr.rsf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "RSF"); + state->u.f4.fld.dmaomr.dtcefd = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "DTCEFD"); + + // DMAIER bitfields. + state->u.f4.fld.dmaier.tie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TIE"); + state->u.f4.fld.dmaier.tpsie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TPSIE"); + state->u.f4.fld.dmaier.tbuie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TBUIE"); + state->u.f4.fld.dmaier.tjtie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TJTIE"); + state->u.f4.fld.dmaier.roie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "ROIE"); + state->u.f4.fld.dmaier.tuie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TUIE"); + state->u.f4.fld.dmaier.rie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RIE"); + state->u.f4.fld.dmaier.rbuie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RBUIE"); + state->u.f4.fld.dmaier.rpsie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RPSIE"); + state->u.f4.fld.dmaier.rwtie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RWTIE"); + state->u.f4.fld.dmaier.etie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "ETIE"); + state->u.f4.fld.dmaier.fbeie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "FBEIE"); + state->u.f4.fld.dmaier.erie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "ERIE"); + state->u.f4.fld.dmaier.aise = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "AISE"); + state->u.f4.fld.dmaier.nise = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "NISE"); + + // DMAMFBOCR bitfields. + state->u.f4.fld.dmamfbocr.mfc = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "MFC"); + state->u.f4.fld.dmamfbocr.omfc = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "OMFC"); + state->u.f4.fld.dmamfbocr.mfa = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "MFA"); + state->u.f4.fld.dmamfbocr.ofoc = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "OFOC"); + + // DMARSWTR bitfields. + state->u.f4.fld.dmarswtr.rswtc = cm_object_get_child_by_name(state->u.f4.reg.dmarswtr, "RSWTC"); + + // DMACHTDR bitfields. + state->u.f4.fld.dmachtdr.htdap = cm_object_get_child_by_name(state->u.f4.reg.dmachtdr, "HTDAP"); + + // DMACHRDR bitfields. + state->u.f4.fld.dmachrdr.hrdap = cm_object_get_child_by_name(state->u.f4.reg.dmachrdr, "HRDAP"); + + // DMACHTBAR bitfields. + state->u.f4.fld.dmachtbar.htbap = cm_object_get_child_by_name(state->u.f4.reg.dmachtbar, "HTBAP"); + + // DMACHRBAR bitfields. + state->u.f4.fld.dmachrbar.hrbap = cm_object_get_child_by_name(state->u.f4.reg.dmachrbar, "HRBAP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_dma_is_enabled(Object *obj) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_ethernet_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_DMAEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_DMA); +} + +static void stm32_ethernet_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_dma_reset_callback; + dc->realize = stm32_ethernet_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_dma_is_enabled; +} + +static const TypeInfo stm32_ethernet_dma_type_info = { + .name = TYPE_STM32_Ethernet_DMA, + .parent = TYPE_STM32_Ethernet_DMA_PARENT, + .instance_init = stm32_ethernet_dma_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_DMAState), + .class_init = stm32_ethernet_dma_class_init_callback, + .class_size = sizeof(STM32Ethernet_DMAClass) }; + +static void stm32_ethernet_dma_register_types(void) +{ + type_register_static(&stm32_ethernet_dma_type_info); +} + +type_init(stm32_ethernet_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_dma.h b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_dma.h new file mode 100644 index 0000000000..51d3403ed8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_dma.h @@ -0,0 +1,242 @@ +/* + * STM32 - Ethernet_DMA (Ethernet: DMA controller operation) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_DMA_H_ +#define STM32_Ethernet_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_DMA DEVICE_PATH_STM32 "Ethernet_DMA" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_DMA TYPE_STM32_PREFIX "ethernet_dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_DMAParentClass; +typedef PeripheralState STM32Ethernet_DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_DMAClass, (obj), TYPE_STM32_Ethernet_DMA) +#define STM32_Ethernet_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_DMAClass, (klass), TYPE_STM32_Ethernet_DMA) + +typedef struct { + // private: + STM32Ethernet_DMAParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_DMA_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_DMAState, (obj), TYPE_STM32_Ethernet_DMA) + +typedef struct { + // private: + STM32Ethernet_DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_DMA (Ethernet: DMA controller operation) registers. + struct { + Object *dmabmr; // 0x0 (Ethernet DMA bus mode register) + Object *dmatpdr; // 0x4 (Ethernet DMA transmit poll demand register) + Object *dmarpdr; // 0x8 (EHERNET DMA receive poll demand register) + Object *dmardlar; // 0xC (Ethernet DMA receive descriptor list address register) + Object *dmatdlar; // 0x10 (Ethernet DMA transmit descriptor list address register) + Object *dmasr; // 0x14 (Ethernet DMA status register) + Object *dmaomr; // 0x18 (Ethernet DMA operation mode register) + Object *dmaier; // 0x1C (Ethernet DMA interrupt enable register) + Object *dmamfbocr; // 0x20 (Ethernet DMA missed frame and buffer overflow counter register) + Object *dmarswtr; // 0x24 (Ethernet DMA receive status watchdog timer register) + Object *dmachtdr; // 0x48 (Ethernet DMA current host transmit descriptor register) + Object *dmachrdr; // 0x4C (Ethernet DMA current host receive descriptor register) + Object *dmachtbar; // 0x50 (Ethernet DMA current host transmit buffer address register) + Object *dmachrbar; // 0x54 (Ethernet DMA current host receive buffer address register) + } reg; + + struct { + + // DMABMR (Ethernet DMA bus mode register) bitfields. + struct { + Object *sr; // [0:0] No description available + Object *da; // [1:1] No description available + Object *dsl; // [2:6] No description available + Object *edfe; // [7:7] No description available + Object *pbl; // [8:13] No description available + Object *rtpr; // [14:15] No description available + Object *fb; // [16:16] No description available + Object *rdp; // [17:22] No description available + Object *usp; // [23:23] No description available + Object *fpm; // [24:24] No description available + Object *aab; // [25:25] No description available + Object *mb; // [26:26] No description available + } dmabmr; + + // DMATPDR (Ethernet DMA transmit poll demand register) bitfields. + struct { + Object *tpd; // [0:31] No description available + } dmatpdr; + + // DMARPDR (EHERNET DMA receive poll demand register) bitfields. + struct { + Object *rpd; // [0:31] RPD + } dmarpdr; + + // DMARDLAR (Ethernet DMA receive descriptor list address register) bitfields. + struct { + Object *srl; // [0:31] No description available + } dmardlar; + + // DMATDLAR (Ethernet DMA transmit descriptor list address register) bitfields. + struct { + Object *stl; // [0:31] No description available + } dmatdlar; + + // DMASR (Ethernet DMA status register) bitfields. + struct { + Object *ts; // [0:0] No description available + Object *tpss; // [1:1] No description available + Object *tbus; // [2:2] No description available + Object *tjts; // [3:3] No description available + Object *ros; // [4:4] No description available + Object *tus; // [5:5] No description available + Object *rs; // [6:6] No description available + Object *rbus; // [7:7] No description available + Object *rpss; // [8:8] No description available + Object *pwts; // [9:9] No description available + Object *ets; // [10:10] No description available + Object *fbes; // [13:13] No description available + Object *ers; // [14:14] No description available + Object *ais; // [15:15] No description available + Object *nis; // [16:16] No description available + Object *rps; // [17:19] No description available + Object *tps; // [20:22] No description available + Object *ebs; // [23:25] No description available + Object *mmcs; // [27:27] No description available + Object *pmts; // [28:28] No description available + Object *tsts; // [29:29] No description available + } dmasr; + + // DMAOMR (Ethernet DMA operation mode register) bitfields. + struct { + Object *sr; // [1:1] SR + Object *osf; // [2:2] OSF + Object *rtc; // [3:4] RTC + Object *fugf; // [6:6] FUGF + Object *fef; // [7:7] FEF + Object *st; // [13:13] ST + Object *ttc; // [14:16] TTC + Object *ftf; // [20:20] FTF + Object *tsf; // [21:21] TSF + Object *dfrf; // [24:24] DFRF + Object *rsf; // [25:25] RSF + Object *dtcefd; // [26:26] DTCEFD + } dmaomr; + + // DMAIER (Ethernet DMA interrupt enable register) bitfields. + struct { + Object *tie; // [0:0] No description available + Object *tpsie; // [1:1] No description available + Object *tbuie; // [2:2] No description available + Object *tjtie; // [3:3] No description available + Object *roie; // [4:4] No description available + Object *tuie; // [5:5] No description available + Object *rie; // [6:6] No description available + Object *rbuie; // [7:7] No description available + Object *rpsie; // [8:8] No description available + Object *rwtie; // [9:9] No description available + Object *etie; // [10:10] No description available + Object *fbeie; // [13:13] No description available + Object *erie; // [14:14] No description available + Object *aise; // [15:15] No description available + Object *nise; // [16:16] No description available + } dmaier; + + // DMAMFBOCR (Ethernet DMA missed frame and buffer overflow counter register) bitfields. + struct { + Object *mfc; // [0:15] No description available + Object *omfc; // [16:16] No description available + Object *mfa; // [17:27] No description available + Object *ofoc; // [28:28] No description available + } dmamfbocr; + + // DMARSWTR (Ethernet DMA receive status watchdog timer register) bitfields. + struct { + Object *rswtc; // [0:7] RSWTC + } dmarswtr; + + // DMACHTDR (Ethernet DMA current host transmit descriptor register) bitfields. + struct { + Object *htdap; // [0:31] HTDAP + } dmachtdr; + + // DMACHRDR (Ethernet DMA current host receive descriptor register) bitfields. + struct { + Object *hrdap; // [0:31] HRDAP + } dmachrdr; + + // DMACHTBAR (Ethernet DMA current host transmit buffer address register) bitfields. + struct { + Object *htbap; // [0:31] No description available + } dmachtbar; + + // DMACHRBAR (Ethernet DMA current host receive buffer address register) bitfields. + struct { + Object *hrbap; // [0:31] No description available + } dmachrbar; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mac.c b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mac.c new file mode 100644 index 0000000000..b9947c6977 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mac.c @@ -0,0 +1,376 @@ +/* + * STM32 - Ethernet_MAC (Ethernet: media access control (MAC)) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_ethernet_mac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.maccr = cm_object_get_child_by_name(obj, "MACCR"); + state->u.f4.reg.macffr = cm_object_get_child_by_name(obj, "MACFFR"); + state->u.f4.reg.machthr = cm_object_get_child_by_name(obj, "MACHTHR"); + state->u.f4.reg.machtlr = cm_object_get_child_by_name(obj, "MACHTLR"); + state->u.f4.reg.macmiiar = cm_object_get_child_by_name(obj, "MACMIIAR"); + state->u.f4.reg.macmiidr = cm_object_get_child_by_name(obj, "MACMIIDR"); + state->u.f4.reg.macfcr = cm_object_get_child_by_name(obj, "MACFCR"); + state->u.f4.reg.macvlantr = cm_object_get_child_by_name(obj, "MACVLANTR"); + state->u.f4.reg.macpmtcsr = cm_object_get_child_by_name(obj, "MACPMTCSR"); + state->u.f4.reg.macdbgr = cm_object_get_child_by_name(obj, "MACDBGR"); + state->u.f4.reg.macsr = cm_object_get_child_by_name(obj, "MACSR"); + state->u.f4.reg.macimr = cm_object_get_child_by_name(obj, "MACIMR"); + state->u.f4.reg.maca0hr = cm_object_get_child_by_name(obj, "MACA0HR"); + state->u.f4.reg.maca0lr = cm_object_get_child_by_name(obj, "MACA0LR"); + state->u.f4.reg.maca1hr = cm_object_get_child_by_name(obj, "MACA1HR"); + state->u.f4.reg.maca1lr = cm_object_get_child_by_name(obj, "MACA1LR"); + state->u.f4.reg.maca2hr = cm_object_get_child_by_name(obj, "MACA2HR"); + state->u.f4.reg.maca2lr = cm_object_get_child_by_name(obj, "MACA2LR"); + state->u.f4.reg.maca3hr = cm_object_get_child_by_name(obj, "MACA3HR"); + state->u.f4.reg.maca3lr = cm_object_get_child_by_name(obj, "MACA3LR"); + + + // MACCR bitfields. + state->u.f4.fld.maccr.re = cm_object_get_child_by_name(state->u.f4.reg.maccr, "RE"); + state->u.f4.fld.maccr.te = cm_object_get_child_by_name(state->u.f4.reg.maccr, "TE"); + state->u.f4.fld.maccr.dc = cm_object_get_child_by_name(state->u.f4.reg.maccr, "DC"); + state->u.f4.fld.maccr.bl = cm_object_get_child_by_name(state->u.f4.reg.maccr, "BL"); + state->u.f4.fld.maccr.apcs = cm_object_get_child_by_name(state->u.f4.reg.maccr, "APCS"); + state->u.f4.fld.maccr.rd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "RD"); + state->u.f4.fld.maccr.ipco = cm_object_get_child_by_name(state->u.f4.reg.maccr, "IPCO"); + state->u.f4.fld.maccr.dm = cm_object_get_child_by_name(state->u.f4.reg.maccr, "DM"); + state->u.f4.fld.maccr.lm = cm_object_get_child_by_name(state->u.f4.reg.maccr, "LM"); + state->u.f4.fld.maccr.rod = cm_object_get_child_by_name(state->u.f4.reg.maccr, "ROD"); + state->u.f4.fld.maccr.fes = cm_object_get_child_by_name(state->u.f4.reg.maccr, "FES"); + state->u.f4.fld.maccr.csd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "CSD"); + state->u.f4.fld.maccr.ifg = cm_object_get_child_by_name(state->u.f4.reg.maccr, "IFG"); + state->u.f4.fld.maccr.jd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "JD"); + state->u.f4.fld.maccr.wd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "WD"); + state->u.f4.fld.maccr.cstf = cm_object_get_child_by_name(state->u.f4.reg.maccr, "CSTF"); + + // MACFFR bitfields. + state->u.f4.fld.macffr.pm = cm_object_get_child_by_name(state->u.f4.reg.macffr, "PM"); + state->u.f4.fld.macffr.hu = cm_object_get_child_by_name(state->u.f4.reg.macffr, "HU"); + state->u.f4.fld.macffr.hm = cm_object_get_child_by_name(state->u.f4.reg.macffr, "HM"); + state->u.f4.fld.macffr.daif = cm_object_get_child_by_name(state->u.f4.reg.macffr, "DAIF"); + state->u.f4.fld.macffr.ram = cm_object_get_child_by_name(state->u.f4.reg.macffr, "RAM"); + state->u.f4.fld.macffr.bfd = cm_object_get_child_by_name(state->u.f4.reg.macffr, "BFD"); + state->u.f4.fld.macffr.pcf = cm_object_get_child_by_name(state->u.f4.reg.macffr, "PCF"); + state->u.f4.fld.macffr.saif = cm_object_get_child_by_name(state->u.f4.reg.macffr, "SAIF"); + state->u.f4.fld.macffr.saf = cm_object_get_child_by_name(state->u.f4.reg.macffr, "SAF"); + state->u.f4.fld.macffr.hpf = cm_object_get_child_by_name(state->u.f4.reg.macffr, "HPF"); + state->u.f4.fld.macffr.ra = cm_object_get_child_by_name(state->u.f4.reg.macffr, "RA"); + + // MACHTHR bitfields. + state->u.f4.fld.machthr.hth = cm_object_get_child_by_name(state->u.f4.reg.machthr, "HTH"); + + // MACHTLR bitfields. + state->u.f4.fld.machtlr.htl = cm_object_get_child_by_name(state->u.f4.reg.machtlr, "HTL"); + + // MACMIIAR bitfields. + state->u.f4.fld.macmiiar.mb = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "MB"); + state->u.f4.fld.macmiiar.mw = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "MW"); + state->u.f4.fld.macmiiar.cr = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "CR"); + state->u.f4.fld.macmiiar.mr = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "MR"); + state->u.f4.fld.macmiiar.pa = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "PA"); + + // MACMIIDR bitfields. + state->u.f4.fld.macmiidr.td = cm_object_get_child_by_name(state->u.f4.reg.macmiidr, "TD"); + + // MACFCR bitfields. + state->u.f4.fld.macfcr.fcb = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "FCB"); + state->u.f4.fld.macfcr.tfce = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "TFCE"); + state->u.f4.fld.macfcr.rfce = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "RFCE"); + state->u.f4.fld.macfcr.upfd = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "UPFD"); + state->u.f4.fld.macfcr.plt = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "PLT"); + state->u.f4.fld.macfcr.zqpd = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "ZQPD"); + state->u.f4.fld.macfcr.pt = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "PT"); + + // MACVLANTR bitfields. + state->u.f4.fld.macvlantr.vlanti = cm_object_get_child_by_name(state->u.f4.reg.macvlantr, "VLANTI"); + state->u.f4.fld.macvlantr.vlantc = cm_object_get_child_by_name(state->u.f4.reg.macvlantr, "VLANTC"); + + // MACPMTCSR bitfields. + state->u.f4.fld.macpmtcsr.pd = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "PD"); + state->u.f4.fld.macpmtcsr.mpe = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "MPE"); + state->u.f4.fld.macpmtcsr.wfe = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "WFE"); + state->u.f4.fld.macpmtcsr.mpr = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "MPR"); + state->u.f4.fld.macpmtcsr.wfr = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "WFR"); + state->u.f4.fld.macpmtcsr.gu = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "GU"); + state->u.f4.fld.macpmtcsr.wffrpr = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "WFFRPR"); + + // MACDBGR bitfields. + state->u.f4.fld.macdbgr.cr = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "CR"); + state->u.f4.fld.macdbgr.csr = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "CSR"); + state->u.f4.fld.macdbgr.ror = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "ROR"); + state->u.f4.fld.macdbgr.mcf = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "MCF"); + state->u.f4.fld.macdbgr.mcp = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "MCP"); + state->u.f4.fld.macdbgr.mcfhp = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "MCFHP"); + + // MACSR bitfields. + state->u.f4.fld.macsr.pmts = cm_object_get_child_by_name(state->u.f4.reg.macsr, "PMTS"); + state->u.f4.fld.macsr.mmcs = cm_object_get_child_by_name(state->u.f4.reg.macsr, "MMCS"); + state->u.f4.fld.macsr.mmcrs = cm_object_get_child_by_name(state->u.f4.reg.macsr, "MMCRS"); + state->u.f4.fld.macsr.mmcts = cm_object_get_child_by_name(state->u.f4.reg.macsr, "MMCTS"); + state->u.f4.fld.macsr.tsts = cm_object_get_child_by_name(state->u.f4.reg.macsr, "TSTS"); + + // MACIMR bitfields. + state->u.f4.fld.macimr.pmtim = cm_object_get_child_by_name(state->u.f4.reg.macimr, "PMTIM"); + state->u.f4.fld.macimr.tstim = cm_object_get_child_by_name(state->u.f4.reg.macimr, "TSTIM"); + + // MACA0HR bitfields. + state->u.f4.fld.maca0hr.maca0h = cm_object_get_child_by_name(state->u.f4.reg.maca0hr, "MACA0H"); + state->u.f4.fld.maca0hr.mo = cm_object_get_child_by_name(state->u.f4.reg.maca0hr, "MO"); + + // MACA0LR bitfields. + state->u.f4.fld.maca0lr.maca0l = cm_object_get_child_by_name(state->u.f4.reg.maca0lr, "MACA0L"); + + // MACA1HR bitfields. + state->u.f4.fld.maca1hr.maca1h = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "MACA1H"); + state->u.f4.fld.maca1hr.mbc = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "MBC"); + state->u.f4.fld.maca1hr.sa = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "SA"); + state->u.f4.fld.maca1hr.ae = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "AE"); + + // MACA1LR bitfields. + state->u.f4.fld.maca1lr.maca1lr = cm_object_get_child_by_name(state->u.f4.reg.maca1lr, "MACA1LR"); + + // MACA2HR bitfields. + state->u.f4.fld.maca2hr.mac2ah = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "MAC2AH"); + state->u.f4.fld.maca2hr.mbc = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "MBC"); + state->u.f4.fld.maca2hr.sa = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "SA"); + state->u.f4.fld.maca2hr.ae = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "AE"); + + // MACA2LR bitfields. + state->u.f4.fld.maca2lr.maca2l = cm_object_get_child_by_name(state->u.f4.reg.maca2lr, "MACA2L"); + + // MACA3HR bitfields. + state->u.f4.fld.maca3hr.maca3h = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "MACA3H"); + state->u.f4.fld.maca3hr.mbc = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "MBC"); + state->u.f4.fld.maca3hr.sa = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "SA"); + state->u.f4.fld.maca3hr.ae = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "AE"); + + // MACA3LR bitfields. + state->u.f4.fld.maca3lr.mbca3l = cm_object_get_child_by_name(state->u.f4.reg.maca3lr, "MBCA3L"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_mac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_mac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_mac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_mac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_mac_is_enabled(Object *obj) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_mac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_mac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_MAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_MAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_ethernet_mac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_MACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_mac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_MAC); +} + +static void stm32_ethernet_mac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_mac_reset_callback; + dc->realize = stm32_ethernet_mac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_mac_is_enabled; +} + +static const TypeInfo stm32_ethernet_mac_type_info = { + .name = TYPE_STM32_Ethernet_MAC, + .parent = TYPE_STM32_Ethernet_MAC_PARENT, + .instance_init = stm32_ethernet_mac_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_MACState), + .class_init = stm32_ethernet_mac_class_init_callback, + .class_size = sizeof(STM32Ethernet_MACClass) }; + +static void stm32_ethernet_mac_register_types(void) +{ + type_register_static(&stm32_ethernet_mac_type_info); +} + +type_init(stm32_ethernet_mac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mac.h b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mac.h new file mode 100644 index 0000000000..87220e3fdc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mac.h @@ -0,0 +1,281 @@ +/* + * STM32 - Ethernet_MAC (Ethernet: media access control (MAC)) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_MAC_H_ +#define STM32_Ethernet_MAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_MAC DEVICE_PATH_STM32 "Ethernet_MAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_MAC TYPE_STM32_PREFIX "ethernet_mac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_MAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_MACParentClass; +typedef PeripheralState STM32Ethernet_MACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_MAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_MACClass, (obj), TYPE_STM32_Ethernet_MAC) +#define STM32_Ethernet_MAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_MACClass, (klass), TYPE_STM32_Ethernet_MAC) + +typedef struct { + // private: + STM32Ethernet_MACParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_MACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_MAC_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_MACState, (obj), TYPE_STM32_Ethernet_MAC) + +typedef struct { + // private: + STM32Ethernet_MACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_MAC (Ethernet: media access control (MAC)) registers. + struct { + Object *maccr; // 0x0 (Ethernet MAC configuration register) + Object *macffr; // 0x4 (Ethernet MAC frame filter register) + Object *machthr; // 0x8 (Ethernet MAC hash table high register) + Object *machtlr; // 0xC (Ethernet MAC hash table low register) + Object *macmiiar; // 0x10 (Ethernet MAC MII address register) + Object *macmiidr; // 0x14 (Ethernet MAC MII data register) + Object *macfcr; // 0x18 (Ethernet MAC flow control register) + Object *macvlantr; // 0x1C (Ethernet MAC VLAN tag register) + Object *macpmtcsr; // 0x2C (Ethernet MAC PMT control and status register) + Object *macdbgr; // 0x34 (Ethernet MAC debug register) + Object *macsr; // 0x38 (Ethernet MAC interrupt status register) + Object *macimr; // 0x3C (Ethernet MAC interrupt mask register) + Object *maca0hr; // 0x40 (Ethernet MAC address 0 high register) + Object *maca0lr; // 0x44 (Ethernet MAC address 0 low register) + Object *maca1hr; // 0x48 (Ethernet MAC address 1 high register) + Object *maca1lr; // 0x4C (Ethernet MAC address1 low register) + Object *maca2hr; // 0x50 (Ethernet MAC address 2 high register) + Object *maca2lr; // 0x54 (Ethernet MAC address 2 low register) + Object *maca3hr; // 0x58 (Ethernet MAC address 3 high register) + Object *maca3lr; // 0x5C (Ethernet MAC address 3 low register) + } reg; + + struct { + + // MACCR (Ethernet MAC configuration register) bitfields. + struct { + Object *re; // [2:2] RE + Object *te; // [3:3] TE + Object *dc; // [4:4] DC + Object *bl; // [5:6] BL + Object *apcs; // [7:7] APCS + Object *rd; // [9:9] RD + Object *ipco; // [10:10] IPCO + Object *dm; // [11:11] DM + Object *lm; // [12:12] LM + Object *rod; // [13:13] ROD + Object *fes; // [14:14] FES + Object *csd; // [16:16] CSD + Object *ifg; // [17:19] IFG + Object *jd; // [22:22] JD + Object *wd; // [23:23] WD + Object *cstf; // [25:25] CSTF + } maccr; + + // MACFFR (Ethernet MAC frame filter register) bitfields. + struct { + Object *pm; // [0:0] No description available + Object *hu; // [1:1] No description available + Object *hm; // [2:2] No description available + Object *daif; // [3:3] No description available + Object *ram; // [4:4] No description available + Object *bfd; // [5:5] No description available + Object *pcf; // [6:6] No description available + Object *saif; // [7:7] No description available + Object *saf; // [8:8] No description available + Object *hpf; // [9:9] No description available + Object *ra; // [31:31] No description available + } macffr; + + // MACHTHR (Ethernet MAC hash table high register) bitfields. + struct { + Object *hth; // [0:31] No description available + } machthr; + + // MACHTLR (Ethernet MAC hash table low register) bitfields. + struct { + Object *htl; // [0:31] No description available + } machtlr; + + // MACMIIAR (Ethernet MAC MII address register) bitfields. + struct { + Object *mb; // [0:0] No description available + Object *mw; // [1:1] No description available + Object *cr; // [2:4] No description available + Object *mr; // [6:10] No description available + Object *pa; // [11:15] No description available + } macmiiar; + + // MACMIIDR (Ethernet MAC MII data register) bitfields. + struct { + Object *td; // [0:15] No description available + } macmiidr; + + // MACFCR (Ethernet MAC flow control register) bitfields. + struct { + Object *fcb; // [0:0] No description available + Object *tfce; // [1:1] No description available + Object *rfce; // [2:2] No description available + Object *upfd; // [3:3] No description available + Object *plt; // [4:5] No description available + Object *zqpd; // [7:7] No description available + Object *pt; // [16:31] No description available + } macfcr; + + // MACVLANTR (Ethernet MAC VLAN tag register) bitfields. + struct { + Object *vlanti; // [0:15] No description available + Object *vlantc; // [16:16] No description available + } macvlantr; + + // MACPMTCSR (Ethernet MAC PMT control and status register) bitfields. + struct { + Object *pd; // [0:0] No description available + Object *mpe; // [1:1] No description available + Object *wfe; // [2:2] No description available + Object *mpr; // [5:5] No description available + Object *wfr; // [6:6] No description available + Object *gu; // [9:9] No description available + Object *wffrpr; // [31:31] No description available + } macpmtcsr; + + // MACDBGR (Ethernet MAC debug register) bitfields. + struct { + Object *cr; // [0:0] CR + Object *csr; // [1:1] CSR + Object *ror; // [2:2] ROR + Object *mcf; // [3:3] MCF + Object *mcp; // [4:4] MCP + Object *mcfhp; // [5:5] MCFHP + } macdbgr; + + // MACSR (Ethernet MAC interrupt status register) bitfields. + struct { + Object *pmts; // [3:3] No description available + Object *mmcs; // [4:4] No description available + Object *mmcrs; // [5:5] No description available + Object *mmcts; // [6:6] No description available + Object *tsts; // [9:9] No description available + } macsr; + + // MACIMR (Ethernet MAC interrupt mask register) bitfields. + struct { + Object *pmtim; // [3:3] No description available + Object *tstim; // [9:9] No description available + } macimr; + + // MACA0HR (Ethernet MAC address 0 high register) bitfields. + struct { + Object *maca0h; // [0:15] MAC address0 high + Object *mo; // [31:31] Always 1 + } maca0hr; + + // MACA0LR (Ethernet MAC address 0 low register) bitfields. + struct { + Object *maca0l; // [0:31] 0 + } maca0lr; + + // MACA1HR (Ethernet MAC address 1 high register) bitfields. + struct { + Object *maca1h; // [0:15] No description available + Object *mbc; // [24:29] No description available + Object *sa; // [30:30] No description available + Object *ae; // [31:31] No description available + } maca1hr; + + // MACA1LR (Ethernet MAC address1 low register) bitfields. + struct { + Object *maca1lr; // [0:31] No description available + } maca1lr; + + // MACA2HR (Ethernet MAC address 2 high register) bitfields. + struct { + Object *mac2ah; // [0:15] No description available + Object *mbc; // [24:29] No description available + Object *sa; // [30:30] No description available + Object *ae; // [31:31] No description available + } maca2hr; + + // MACA2LR (Ethernet MAC address 2 low register) bitfields. + struct { + Object *maca2l; // [0:30] No description available + } maca2lr; + + // MACA3HR (Ethernet MAC address 3 high register) bitfields. + struct { + Object *maca3h; // [0:15] No description available + Object *mbc; // [24:29] No description available + Object *sa; // [30:30] No description available + Object *ae; // [31:31] No description available + } maca3hr; + + // MACA3LR (Ethernet MAC address 3 low register) bitfields. + struct { + Object *mbca3l; // [0:31] No description available + } maca3lr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_MACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_MAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mmc.c b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mmc.c new file mode 100644 index 0000000000..02733a9e0c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mmc.c @@ -0,0 +1,291 @@ +/* + * STM32 - Ethernet_MMC (Ethernet: MAC management counters) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_ethernet_mmc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.mmccr = cm_object_get_child_by_name(obj, "MMCCR"); + state->u.f4.reg.mmcrir = cm_object_get_child_by_name(obj, "MMCRIR"); + state->u.f4.reg.mmctir = cm_object_get_child_by_name(obj, "MMCTIR"); + state->u.f4.reg.mmcrimr = cm_object_get_child_by_name(obj, "MMCRIMR"); + state->u.f4.reg.mmctimr = cm_object_get_child_by_name(obj, "MMCTIMR"); + state->u.f4.reg.mmctgfsccr = cm_object_get_child_by_name(obj, "MMCTGFSCCR"); + state->u.f4.reg.mmctgfmsccr = cm_object_get_child_by_name(obj, "MMCTGFMSCCR"); + state->u.f4.reg.mmctgfcr = cm_object_get_child_by_name(obj, "MMCTGFCR"); + state->u.f4.reg.mmcrfcecr = cm_object_get_child_by_name(obj, "MMCRFCECR"); + state->u.f4.reg.mmcrfaecr = cm_object_get_child_by_name(obj, "MMCRFAECR"); + state->u.f4.reg.mmcrgufcr = cm_object_get_child_by_name(obj, "MMCRGUFCR"); + + + // MMCCR bitfields. + state->u.f4.fld.mmccr.cr = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "CR"); + state->u.f4.fld.mmccr.csr = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "CSR"); + state->u.f4.fld.mmccr.ror = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "ROR"); + state->u.f4.fld.mmccr.mcf = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "MCF"); + state->u.f4.fld.mmccr.mcp = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "MCP"); + state->u.f4.fld.mmccr.mcfhp = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "MCFHP"); + + // MMCRIR bitfields. + state->u.f4.fld.mmcrir.rfces = cm_object_get_child_by_name(state->u.f4.reg.mmcrir, "RFCES"); + state->u.f4.fld.mmcrir.rfaes = cm_object_get_child_by_name(state->u.f4.reg.mmcrir, "RFAES"); + state->u.f4.fld.mmcrir.rgufs = cm_object_get_child_by_name(state->u.f4.reg.mmcrir, "RGUFS"); + + // MMCTIR bitfields. + state->u.f4.fld.mmctir.tgfscs = cm_object_get_child_by_name(state->u.f4.reg.mmctir, "TGFSCS"); + state->u.f4.fld.mmctir.tgfmscs = cm_object_get_child_by_name(state->u.f4.reg.mmctir, "TGFMSCS"); + state->u.f4.fld.mmctir.tgfs = cm_object_get_child_by_name(state->u.f4.reg.mmctir, "TGFS"); + + // MMCRIMR bitfields. + state->u.f4.fld.mmcrimr.rfcem = cm_object_get_child_by_name(state->u.f4.reg.mmcrimr, "RFCEM"); + state->u.f4.fld.mmcrimr.rfaem = cm_object_get_child_by_name(state->u.f4.reg.mmcrimr, "RFAEM"); + state->u.f4.fld.mmcrimr.rgufm = cm_object_get_child_by_name(state->u.f4.reg.mmcrimr, "RGUFM"); + + // MMCTIMR bitfields. + state->u.f4.fld.mmctimr.tgfscm = cm_object_get_child_by_name(state->u.f4.reg.mmctimr, "TGFSCM"); + state->u.f4.fld.mmctimr.tgfmscm = cm_object_get_child_by_name(state->u.f4.reg.mmctimr, "TGFMSCM"); + state->u.f4.fld.mmctimr.tgfm = cm_object_get_child_by_name(state->u.f4.reg.mmctimr, "TGFM"); + + // MMCTGFSCCR bitfields. + state->u.f4.fld.mmctgfsccr.tgfscc = cm_object_get_child_by_name(state->u.f4.reg.mmctgfsccr, "TGFSCC"); + + // MMCTGFMSCCR bitfields. + state->u.f4.fld.mmctgfmsccr.tgfmscc = cm_object_get_child_by_name(state->u.f4.reg.mmctgfmsccr, "TGFMSCC"); + + // MMCTGFCR bitfields. + state->u.f4.fld.mmctgfcr.tgfc = cm_object_get_child_by_name(state->u.f4.reg.mmctgfcr, "TGFC"); + + // MMCRFCECR bitfields. + state->u.f4.fld.mmcrfcecr.rfcfc = cm_object_get_child_by_name(state->u.f4.reg.mmcrfcecr, "RFCFC"); + + // MMCRFAECR bitfields. + state->u.f4.fld.mmcrfaecr.rfaec = cm_object_get_child_by_name(state->u.f4.reg.mmcrfaecr, "RFAEC"); + + // MMCRGUFCR bitfields. + state->u.f4.fld.mmcrgufcr.rgufc = cm_object_get_child_by_name(state->u.f4.reg.mmcrgufcr, "RGUFC"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_mmc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_mmc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_mmc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_mmc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_mmc_is_enabled(Object *obj) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_mmc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_mmc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_MMC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_MMC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_ethernet_mmc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_MMCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_mmc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_MMC); +} + +static void stm32_ethernet_mmc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_mmc_reset_callback; + dc->realize = stm32_ethernet_mmc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_mmc_is_enabled; +} + +static const TypeInfo stm32_ethernet_mmc_type_info = { + .name = TYPE_STM32_Ethernet_MMC, + .parent = TYPE_STM32_Ethernet_MMC_PARENT, + .instance_init = stm32_ethernet_mmc_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_MMCState), + .class_init = stm32_ethernet_mmc_class_init_callback, + .class_size = sizeof(STM32Ethernet_MMCClass) }; + +static void stm32_ethernet_mmc_register_types(void) +{ + type_register_static(&stm32_ethernet_mmc_type_info); +} + +type_init(stm32_ethernet_mmc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mmc.h b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mmc.h new file mode 100644 index 0000000000..cf85a7daf5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_mmc.h @@ -0,0 +1,178 @@ +/* + * STM32 - Ethernet_MMC (Ethernet: MAC management counters) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_MMC_H_ +#define STM32_Ethernet_MMC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_MMC DEVICE_PATH_STM32 "Ethernet_MMC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_MMC TYPE_STM32_PREFIX "ethernet_mmc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_MMC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_MMCParentClass; +typedef PeripheralState STM32Ethernet_MMCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_MMC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_MMCClass, (obj), TYPE_STM32_Ethernet_MMC) +#define STM32_Ethernet_MMC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_MMCClass, (klass), TYPE_STM32_Ethernet_MMC) + +typedef struct { + // private: + STM32Ethernet_MMCParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_MMCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_MMC_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_MMCState, (obj), TYPE_STM32_Ethernet_MMC) + +typedef struct { + // private: + STM32Ethernet_MMCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_MMC (Ethernet: MAC management counters) registers. + struct { + Object *mmccr; // 0x0 (Ethernet MMC control register) + Object *mmcrir; // 0x4 (Ethernet MMC receive interrupt register) + Object *mmctir; // 0x8 (Ethernet MMC transmit interrupt register) + Object *mmcrimr; // 0xC (Ethernet MMC receive interrupt mask register) + Object *mmctimr; // 0x10 (Ethernet MMC transmit interrupt mask register) + Object *mmctgfsccr; // 0x4C (Ethernet MMC transmitted good frames after a single collision counter) + Object *mmctgfmsccr; // 0x50 (Ethernet MMC transmitted good frames after more than a single collision) + Object *mmctgfcr; // 0x68 (Ethernet MMC transmitted good frames counter register) + Object *mmcrfcecr; // 0x94 (Ethernet MMC received frames with CRC error counter register) + Object *mmcrfaecr; // 0x98 (Ethernet MMC received frames with alignment error counter register) + Object *mmcrgufcr; // 0xC4 (MMC received good unicast frames counter register) + } reg; + + struct { + + // MMCCR (Ethernet MMC control register) bitfields. + struct { + Object *cr; // [0:0] No description available + Object *csr; // [1:1] No description available + Object *ror; // [2:2] No description available + Object *mcf; // [3:3] No description available + Object *mcp; // [4:4] No description available + Object *mcfhp; // [5:5] No description available + } mmccr; + + // MMCRIR (Ethernet MMC receive interrupt register) bitfields. + struct { + Object *rfces; // [5:5] No description available + Object *rfaes; // [6:6] No description available + Object *rgufs; // [17:17] No description available + } mmcrir; + + // MMCTIR (Ethernet MMC transmit interrupt register) bitfields. + struct { + Object *tgfscs; // [14:14] No description available + Object *tgfmscs; // [15:15] No description available + Object *tgfs; // [21:21] No description available + } mmctir; + + // MMCRIMR (Ethernet MMC receive interrupt mask register) bitfields. + struct { + Object *rfcem; // [5:5] No description available + Object *rfaem; // [6:6] No description available + Object *rgufm; // [17:17] No description available + } mmcrimr; + + // MMCTIMR (Ethernet MMC transmit interrupt mask register) bitfields. + struct { + Object *tgfscm; // [14:14] No description available + Object *tgfmscm; // [15:15] No description available + Object *tgfm; // [16:16] No description available + } mmctimr; + + // MMCTGFSCCR (Ethernet MMC transmitted good frames after a single collision counter) bitfields. + struct { + Object *tgfscc; // [0:31] No description available + } mmctgfsccr; + + // MMCTGFMSCCR (Ethernet MMC transmitted good frames after more than a single collision) bitfields. + struct { + Object *tgfmscc; // [0:31] No description available + } mmctgfmsccr; + + // MMCTGFCR (Ethernet MMC transmitted good frames counter register) bitfields. + struct { + Object *tgfc; // [0:31] HTL + } mmctgfcr; + + // MMCRFCECR (Ethernet MMC received frames with CRC error counter register) bitfields. + struct { + Object *rfcfc; // [0:31] No description available + } mmcrfcecr; + + // MMCRFAECR (Ethernet MMC received frames with alignment error counter register) bitfields. + struct { + Object *rfaec; // [0:31] No description available + } mmcrfaecr; + + // MMCRGUFCR (MMC received good unicast frames counter register) bitfields. + struct { + Object *rgufc; // [0:31] No description available + } mmcrgufcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_MMCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_MMC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_ptp.c b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_ptp.c new file mode 100644 index 0000000000..786c527725 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_ptp.c @@ -0,0 +1,297 @@ +/* + * STM32 - Ethernet_PTP (Ethernet: Precision time protocol) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_ethernet_ptp_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.ptptscr = cm_object_get_child_by_name(obj, "PTPTSCR"); + state->u.f4.reg.ptpssir = cm_object_get_child_by_name(obj, "PTPSSIR"); + state->u.f4.reg.ptptshr = cm_object_get_child_by_name(obj, "PTPTSHR"); + state->u.f4.reg.ptptslr = cm_object_get_child_by_name(obj, "PTPTSLR"); + state->u.f4.reg.ptptshur = cm_object_get_child_by_name(obj, "PTPTSHUR"); + state->u.f4.reg.ptptslur = cm_object_get_child_by_name(obj, "PTPTSLUR"); + state->u.f4.reg.ptptsar = cm_object_get_child_by_name(obj, "PTPTSAR"); + state->u.f4.reg.ptptthr = cm_object_get_child_by_name(obj, "PTPTTHR"); + state->u.f4.reg.ptpttlr = cm_object_get_child_by_name(obj, "PTPTTLR"); + state->u.f4.reg.ptptssr = cm_object_get_child_by_name(obj, "PTPTSSR"); + state->u.f4.reg.ptpppscr = cm_object_get_child_by_name(obj, "PTPPPSCR"); + + + // PTPTSCR bitfields. + state->u.f4.fld.ptptscr.tse = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSE"); + state->u.f4.fld.ptptscr.tsfcu = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSFCU"); + state->u.f4.fld.ptptscr.tssti = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSTI"); + state->u.f4.fld.ptptscr.tsstu = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSTU"); + state->u.f4.fld.ptptscr.tsite = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSITE"); + state->u.f4.fld.ptptscr.ttsaru = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TTSARU"); + state->u.f4.fld.ptptscr.tssarfe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSARFE"); + state->u.f4.fld.ptptscr.tsssr = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSSR"); + state->u.f4.fld.ptptscr.tsptppsv2e = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSPTPPSV2E"); + state->u.f4.fld.ptptscr.tssptpoefe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSPTPOEFE"); + state->u.f4.fld.ptptscr.tssipv6fe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSIPV6FE"); + state->u.f4.fld.ptptscr.tssipv4fe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSIPV4FE"); + state->u.f4.fld.ptptscr.tsseme = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSEME"); + state->u.f4.fld.ptptscr.tssmrme = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSMRME"); + state->u.f4.fld.ptptscr.tscnt = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSCNT"); + state->u.f4.fld.ptptscr.tspffmae = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSPFFMAE"); + + // PTPSSIR bitfields. + state->u.f4.fld.ptpssir.stssi = cm_object_get_child_by_name(state->u.f4.reg.ptpssir, "STSSI"); + + // PTPTSHR bitfields. + state->u.f4.fld.ptptshr.sts = cm_object_get_child_by_name(state->u.f4.reg.ptptshr, "STS"); + + // PTPTSLR bitfields. + state->u.f4.fld.ptptslr.stss = cm_object_get_child_by_name(state->u.f4.reg.ptptslr, "STSS"); + state->u.f4.fld.ptptslr.stpns = cm_object_get_child_by_name(state->u.f4.reg.ptptslr, "STPNS"); + + // PTPTSHUR bitfields. + state->u.f4.fld.ptptshur.tsus = cm_object_get_child_by_name(state->u.f4.reg.ptptshur, "TSUS"); + + // PTPTSLUR bitfields. + state->u.f4.fld.ptptslur.tsuss = cm_object_get_child_by_name(state->u.f4.reg.ptptslur, "TSUSS"); + state->u.f4.fld.ptptslur.tsupns = cm_object_get_child_by_name(state->u.f4.reg.ptptslur, "TSUPNS"); + + // PTPTSAR bitfields. + state->u.f4.fld.ptptsar.tsa = cm_object_get_child_by_name(state->u.f4.reg.ptptsar, "TSA"); + + // PTPTTHR bitfields. + state->u.f4.fld.ptptthr.ttsh = cm_object_get_child_by_name(state->u.f4.reg.ptptthr, "TTSH"); + + // PTPTTLR bitfields. + state->u.f4.fld.ptpttlr.ttsl = cm_object_get_child_by_name(state->u.f4.reg.ptpttlr, "TTSL"); + + // PTPTSSR bitfields. + state->u.f4.fld.ptptssr.tsso = cm_object_get_child_by_name(state->u.f4.reg.ptptssr, "TSSO"); + state->u.f4.fld.ptptssr.tsttr = cm_object_get_child_by_name(state->u.f4.reg.ptptssr, "TSTTR"); + + // PTPPPSCR bitfields. + state->u.f4.fld.ptpppscr.tsso = cm_object_get_child_by_name(state->u.f4.reg.ptpppscr, "TSSO"); + state->u.f4.fld.ptpppscr.tsttr = cm_object_get_child_by_name(state->u.f4.reg.ptpppscr, "TSTTR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_ptp_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_ptp_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_ptp_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_ptp_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_ptp_is_enabled(Object *obj) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_ptp_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_ptp_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_PTP)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_PTP"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_ethernet_ptp_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_PTPEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_ptp_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_PTP); +} + +static void stm32_ethernet_ptp_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_ptp_reset_callback; + dc->realize = stm32_ethernet_ptp_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_ptp_is_enabled; +} + +static const TypeInfo stm32_ethernet_ptp_type_info = { + .name = TYPE_STM32_Ethernet_PTP, + .parent = TYPE_STM32_Ethernet_PTP_PARENT, + .instance_init = stm32_ethernet_ptp_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_PTPState), + .class_init = stm32_ethernet_ptp_class_init_callback, + .class_size = sizeof(STM32Ethernet_PTPClass) }; + +static void stm32_ethernet_ptp_register_types(void) +{ + type_register_static(&stm32_ethernet_ptp_type_info); +} + +type_init(stm32_ethernet_ptp_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_ptp.h b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_ptp.h new file mode 100644 index 0000000000..ae192297f5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/ethernet_ptp.h @@ -0,0 +1,184 @@ +/* + * STM32 - Ethernet_PTP (Ethernet: Precision time protocol) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_PTP_H_ +#define STM32_Ethernet_PTP_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_PTP DEVICE_PATH_STM32 "Ethernet_PTP" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_PTP TYPE_STM32_PREFIX "ethernet_ptp" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_PTP_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_PTPParentClass; +typedef PeripheralState STM32Ethernet_PTPParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_PTP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_PTPClass, (obj), TYPE_STM32_Ethernet_PTP) +#define STM32_Ethernet_PTP_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_PTPClass, (klass), TYPE_STM32_Ethernet_PTP) + +typedef struct { + // private: + STM32Ethernet_PTPParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_PTPClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_PTP_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_PTPState, (obj), TYPE_STM32_Ethernet_PTP) + +typedef struct { + // private: + STM32Ethernet_PTPParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_PTP (Ethernet: Precision time protocol) registers. + struct { + Object *ptptscr; // 0x0 (Ethernet PTP time stamp control register) + Object *ptpssir; // 0x4 (Ethernet PTP subsecond increment register) + Object *ptptshr; // 0x8 (Ethernet PTP time stamp high register) + Object *ptptslr; // 0xC (Ethernet PTP time stamp low register) + Object *ptptshur; // 0x10 (Ethernet PTP time stamp high update register) + Object *ptptslur; // 0x14 (Ethernet PTP time stamp low update register) + Object *ptptsar; // 0x18 (Ethernet PTP time stamp addend register) + Object *ptptthr; // 0x1C (Ethernet PTP target time high register) + Object *ptpttlr; // 0x20 (Ethernet PTP target time low register) + Object *ptptssr; // 0x28 (Ethernet PTP time stamp status register) + Object *ptpppscr; // 0x2C (Ethernet PTP PPS control register) + } reg; + + struct { + + // PTPTSCR (Ethernet PTP time stamp control register) bitfields. + struct { + Object *tse; // [0:0] No description available + Object *tsfcu; // [1:1] No description available + Object *tssti; // [2:2] No description available + Object *tsstu; // [3:3] No description available + Object *tsite; // [4:4] No description available + Object *ttsaru; // [5:5] No description available + Object *tssarfe; // [8:8] No description available + Object *tsssr; // [9:9] No description available + Object *tsptppsv2e; // [10:10] No description available + Object *tssptpoefe; // [11:11] No description available + Object *tssipv6fe; // [12:12] No description available + Object *tssipv4fe; // [13:13] No description available + Object *tsseme; // [14:14] No description available + Object *tssmrme; // [15:15] No description available + Object *tscnt; // [16:17] No description available + Object *tspffmae; // [18:18] No description available + } ptptscr; + + // PTPSSIR (Ethernet PTP subsecond increment register) bitfields. + struct { + Object *stssi; // [0:7] No description available + } ptpssir; + + // PTPTSHR (Ethernet PTP time stamp high register) bitfields. + struct { + Object *sts; // [0:31] No description available + } ptptshr; + + // PTPTSLR (Ethernet PTP time stamp low register) bitfields. + struct { + Object *stss; // [0:30] No description available + Object *stpns; // [31:31] No description available + } ptptslr; + + // PTPTSHUR (Ethernet PTP time stamp high update register) bitfields. + struct { + Object *tsus; // [0:31] No description available + } ptptshur; + + // PTPTSLUR (Ethernet PTP time stamp low update register) bitfields. + struct { + Object *tsuss; // [0:30] No description available + Object *tsupns; // [31:31] No description available + } ptptslur; + + // PTPTSAR (Ethernet PTP time stamp addend register) bitfields. + struct { + Object *tsa; // [0:31] No description available + } ptptsar; + + // PTPTTHR (Ethernet PTP target time high register) bitfields. + struct { + Object *ttsh; // [0:31] 0 + } ptptthr; + + // PTPTTLR (Ethernet PTP target time low register) bitfields. + struct { + Object *ttsl; // [0:31] No description available + } ptpttlr; + + // PTPTSSR (Ethernet PTP time stamp status register) bitfields. + struct { + Object *tsso; // [0:0] No description available + Object *tsttr; // [1:1] No description available + } ptptssr; + + // PTPPPSCR (Ethernet PTP PPS control register) bitfields. + struct { + Object *tsso; // [0:0] TSSO + Object *tsttr; // [1:1] TSTTR + } ptpppscr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_PTPState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_PTP_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/exti.c b/gnu-mcu-eclipse/devices/support/STM32F40x/exti.c new file mode 100644 index 0000000000..dd36378a48 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/exti.c @@ -0,0 +1,390 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_exti_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.imr = cm_object_get_child_by_name(obj, "IMR"); + state->u.f4.reg.emr = cm_object_get_child_by_name(obj, "EMR"); + state->u.f4.reg.rtsr = cm_object_get_child_by_name(obj, "RTSR"); + state->u.f4.reg.ftsr = cm_object_get_child_by_name(obj, "FTSR"); + state->u.f4.reg.swier = cm_object_get_child_by_name(obj, "SWIER"); + state->u.f4.reg.pr = cm_object_get_child_by_name(obj, "PR"); + + + // IMR bitfields. + state->u.f4.fld.imr.mr0 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR0"); + state->u.f4.fld.imr.mr1 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR1"); + state->u.f4.fld.imr.mr2 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR2"); + state->u.f4.fld.imr.mr3 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR3"); + state->u.f4.fld.imr.mr4 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR4"); + state->u.f4.fld.imr.mr5 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR5"); + state->u.f4.fld.imr.mr6 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR6"); + state->u.f4.fld.imr.mr7 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR7"); + state->u.f4.fld.imr.mr8 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR8"); + state->u.f4.fld.imr.mr9 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR9"); + state->u.f4.fld.imr.mr10 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR10"); + state->u.f4.fld.imr.mr11 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR11"); + state->u.f4.fld.imr.mr12 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR12"); + state->u.f4.fld.imr.mr13 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR13"); + state->u.f4.fld.imr.mr14 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR14"); + state->u.f4.fld.imr.mr15 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR15"); + state->u.f4.fld.imr.mr16 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR16"); + state->u.f4.fld.imr.mr17 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR17"); + state->u.f4.fld.imr.mr18 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR18"); + state->u.f4.fld.imr.mr19 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR19"); + state->u.f4.fld.imr.mr20 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR20"); + state->u.f4.fld.imr.mr21 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR21"); + state->u.f4.fld.imr.mr22 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR22"); + + // EMR bitfields. + state->u.f4.fld.emr.mr0 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR0"); + state->u.f4.fld.emr.mr1 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR1"); + state->u.f4.fld.emr.mr2 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR2"); + state->u.f4.fld.emr.mr3 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR3"); + state->u.f4.fld.emr.mr4 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR4"); + state->u.f4.fld.emr.mr5 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR5"); + state->u.f4.fld.emr.mr6 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR6"); + state->u.f4.fld.emr.mr7 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR7"); + state->u.f4.fld.emr.mr8 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR8"); + state->u.f4.fld.emr.mr9 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR9"); + state->u.f4.fld.emr.mr10 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR10"); + state->u.f4.fld.emr.mr11 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR11"); + state->u.f4.fld.emr.mr12 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR12"); + state->u.f4.fld.emr.mr13 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR13"); + state->u.f4.fld.emr.mr14 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR14"); + state->u.f4.fld.emr.mr15 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR15"); + state->u.f4.fld.emr.mr16 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR16"); + state->u.f4.fld.emr.mr17 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR17"); + state->u.f4.fld.emr.mr18 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR18"); + state->u.f4.fld.emr.mr19 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR19"); + state->u.f4.fld.emr.mr20 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR20"); + state->u.f4.fld.emr.mr21 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR21"); + state->u.f4.fld.emr.mr22 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR22"); + + // RTSR bitfields. + state->u.f4.fld.rtsr.tr0 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR0"); + state->u.f4.fld.rtsr.tr1 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR1"); + state->u.f4.fld.rtsr.tr2 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR2"); + state->u.f4.fld.rtsr.tr3 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR3"); + state->u.f4.fld.rtsr.tr4 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR4"); + state->u.f4.fld.rtsr.tr5 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR5"); + state->u.f4.fld.rtsr.tr6 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR6"); + state->u.f4.fld.rtsr.tr7 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR7"); + state->u.f4.fld.rtsr.tr8 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR8"); + state->u.f4.fld.rtsr.tr9 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR9"); + state->u.f4.fld.rtsr.tr10 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR10"); + state->u.f4.fld.rtsr.tr11 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR11"); + state->u.f4.fld.rtsr.tr12 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR12"); + state->u.f4.fld.rtsr.tr13 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR13"); + state->u.f4.fld.rtsr.tr14 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR14"); + state->u.f4.fld.rtsr.tr15 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR15"); + state->u.f4.fld.rtsr.tr16 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR16"); + state->u.f4.fld.rtsr.tr17 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR17"); + state->u.f4.fld.rtsr.tr18 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR18"); + state->u.f4.fld.rtsr.tr19 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR19"); + state->u.f4.fld.rtsr.tr20 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR20"); + state->u.f4.fld.rtsr.tr21 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR21"); + state->u.f4.fld.rtsr.tr22 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR22"); + + // FTSR bitfields. + state->u.f4.fld.ftsr.tr0 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR0"); + state->u.f4.fld.ftsr.tr1 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR1"); + state->u.f4.fld.ftsr.tr2 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR2"); + state->u.f4.fld.ftsr.tr3 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR3"); + state->u.f4.fld.ftsr.tr4 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR4"); + state->u.f4.fld.ftsr.tr5 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR5"); + state->u.f4.fld.ftsr.tr6 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR6"); + state->u.f4.fld.ftsr.tr7 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR7"); + state->u.f4.fld.ftsr.tr8 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR8"); + state->u.f4.fld.ftsr.tr9 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR9"); + state->u.f4.fld.ftsr.tr10 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR10"); + state->u.f4.fld.ftsr.tr11 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR11"); + state->u.f4.fld.ftsr.tr12 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR12"); + state->u.f4.fld.ftsr.tr13 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR13"); + state->u.f4.fld.ftsr.tr14 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR14"); + state->u.f4.fld.ftsr.tr15 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR15"); + state->u.f4.fld.ftsr.tr16 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR16"); + state->u.f4.fld.ftsr.tr17 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR17"); + state->u.f4.fld.ftsr.tr18 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR18"); + state->u.f4.fld.ftsr.tr19 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR19"); + state->u.f4.fld.ftsr.tr20 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR20"); + state->u.f4.fld.ftsr.tr21 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR21"); + state->u.f4.fld.ftsr.tr22 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR22"); + + // SWIER bitfields. + state->u.f4.fld.swier.swier0 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER0"); + state->u.f4.fld.swier.swier1 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER1"); + state->u.f4.fld.swier.swier2 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER2"); + state->u.f4.fld.swier.swier3 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER3"); + state->u.f4.fld.swier.swier4 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER4"); + state->u.f4.fld.swier.swier5 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER5"); + state->u.f4.fld.swier.swier6 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER6"); + state->u.f4.fld.swier.swier7 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER7"); + state->u.f4.fld.swier.swier8 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER8"); + state->u.f4.fld.swier.swier9 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER9"); + state->u.f4.fld.swier.swier10 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER10"); + state->u.f4.fld.swier.swier11 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER11"); + state->u.f4.fld.swier.swier12 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER12"); + state->u.f4.fld.swier.swier13 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER13"); + state->u.f4.fld.swier.swier14 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER14"); + state->u.f4.fld.swier.swier15 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER15"); + state->u.f4.fld.swier.swier16 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER16"); + state->u.f4.fld.swier.swier17 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER17"); + state->u.f4.fld.swier.swier18 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER18"); + state->u.f4.fld.swier.swier19 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER19"); + state->u.f4.fld.swier.swier20 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER20"); + state->u.f4.fld.swier.swier21 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER21"); + state->u.f4.fld.swier.swier22 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER22"); + + // PR bitfields. + state->u.f4.fld.pr.pr0 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR0"); + state->u.f4.fld.pr.pr1 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR1"); + state->u.f4.fld.pr.pr2 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR2"); + state->u.f4.fld.pr.pr3 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR3"); + state->u.f4.fld.pr.pr4 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR4"); + state->u.f4.fld.pr.pr5 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR5"); + state->u.f4.fld.pr.pr6 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR6"); + state->u.f4.fld.pr.pr7 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR7"); + state->u.f4.fld.pr.pr8 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR8"); + state->u.f4.fld.pr.pr9 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR9"); + state->u.f4.fld.pr.pr10 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR10"); + state->u.f4.fld.pr.pr11 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR11"); + state->u.f4.fld.pr.pr12 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR12"); + state->u.f4.fld.pr.pr13 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR13"); + state->u.f4.fld.pr.pr14 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR14"); + state->u.f4.fld.pr.pr15 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR15"); + state->u.f4.fld.pr.pr16 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR16"); + state->u.f4.fld.pr.pr17 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR17"); + state->u.f4.fld.pr.pr18 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR18"); + state->u.f4.fld.pr.pr19 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR19"); + state->u.f4.fld.pr.pr20 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR20"); + state->u.f4.fld.pr.pr21 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR21"); + state->u.f4.fld.pr.pr22 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR22"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_exti_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_exti_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_exti_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_exti_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_exti_is_enabled(Object *obj) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_exti_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_exti_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_EXTI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32EXTIState *state = STM32_EXTI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "EXTI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_exti_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_exti_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_exti_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_exti_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_exti_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/EXTIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_exti_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_EXTI); +} + +static void stm32_exti_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_exti_reset_callback; + dc->realize = stm32_exti_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_exti_is_enabled; +} + +static const TypeInfo stm32_exti_type_info = { + .name = TYPE_STM32_EXTI, + .parent = TYPE_STM32_EXTI_PARENT, + .instance_init = stm32_exti_instance_init_callback, + .instance_size = sizeof(STM32EXTIState), + .class_init = stm32_exti_class_init_callback, + .class_size = sizeof(STM32EXTIClass) }; + +static void stm32_exti_register_types(void) +{ + type_register_static(&stm32_exti_type_info); +} + +type_init(stm32_exti_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/exti.h b/gnu-mcu-eclipse/devices/support/STM32F40x/exti.h new file mode 100644 index 0000000000..c60df55b50 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/exti.h @@ -0,0 +1,267 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_EXTI_H_ +#define STM32_EXTI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_EXTI DEVICE_PATH_STM32 "EXTI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_EXTI TYPE_STM32_PREFIX "exti" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_EXTI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32EXTIParentClass; +typedef PeripheralState STM32EXTIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_EXTI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32EXTIClass, (obj), TYPE_STM32_EXTI) +#define STM32_EXTI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32EXTIClass, (klass), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentClass parent_class; + // public: + + // None, so far. +} STM32EXTIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_EXTI_STATE(obj) \ + OBJECT_CHECK(STM32EXTIState, (obj), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 EXTI (External interrupt/event controller) registers. + struct { + Object *imr; // 0x0 (Interrupt mask register (EXTI_IMR)) + Object *emr; // 0x4 (Event mask register (EXTI_EMR)) + Object *rtsr; // 0x8 (Rising Trigger selection register (EXTI_RTSR)) + Object *ftsr; // 0xC (Falling Trigger selection register (EXTI_FTSR)) + Object *swier; // 0x10 (Software interrupt event register (EXTI_SWIER)) + Object *pr; // 0x14 (Pending register (EXTI_PR)) + } reg; + + struct { + + // IMR (Interrupt mask register (EXTI_IMR)) bitfields. + struct { + Object *mr0; // [0:0] Interrupt Mask on line 0 + Object *mr1; // [1:1] Interrupt Mask on line 1 + Object *mr2; // [2:2] Interrupt Mask on line 2 + Object *mr3; // [3:3] Interrupt Mask on line 3 + Object *mr4; // [4:4] Interrupt Mask on line 4 + Object *mr5; // [5:5] Interrupt Mask on line 5 + Object *mr6; // [6:6] Interrupt Mask on line 6 + Object *mr7; // [7:7] Interrupt Mask on line 7 + Object *mr8; // [8:8] Interrupt Mask on line 8 + Object *mr9; // [9:9] Interrupt Mask on line 9 + Object *mr10; // [10:10] Interrupt Mask on line 10 + Object *mr11; // [11:11] Interrupt Mask on line 11 + Object *mr12; // [12:12] Interrupt Mask on line 12 + Object *mr13; // [13:13] Interrupt Mask on line 13 + Object *mr14; // [14:14] Interrupt Mask on line 14 + Object *mr15; // [15:15] Interrupt Mask on line 15 + Object *mr16; // [16:16] Interrupt Mask on line 16 + Object *mr17; // [17:17] Interrupt Mask on line 17 + Object *mr18; // [18:18] Interrupt Mask on line 18 + Object *mr19; // [19:19] Interrupt Mask on line 19 + Object *mr20; // [20:20] Interrupt Mask on line 20 + Object *mr21; // [21:21] Interrupt Mask on line 21 + Object *mr22; // [22:22] Interrupt Mask on line 22 + } imr; + + // EMR (Event mask register (EXTI_EMR)) bitfields. + struct { + Object *mr0; // [0:0] Event Mask on line 0 + Object *mr1; // [1:1] Event Mask on line 1 + Object *mr2; // [2:2] Event Mask on line 2 + Object *mr3; // [3:3] Event Mask on line 3 + Object *mr4; // [4:4] Event Mask on line 4 + Object *mr5; // [5:5] Event Mask on line 5 + Object *mr6; // [6:6] Event Mask on line 6 + Object *mr7; // [7:7] Event Mask on line 7 + Object *mr8; // [8:8] Event Mask on line 8 + Object *mr9; // [9:9] Event Mask on line 9 + Object *mr10; // [10:10] Event Mask on line 10 + Object *mr11; // [11:11] Event Mask on line 11 + Object *mr12; // [12:12] Event Mask on line 12 + Object *mr13; // [13:13] Event Mask on line 13 + Object *mr14; // [14:14] Event Mask on line 14 + Object *mr15; // [15:15] Event Mask on line 15 + Object *mr16; // [16:16] Event Mask on line 16 + Object *mr17; // [17:17] Event Mask on line 17 + Object *mr18; // [18:18] Event Mask on line 18 + Object *mr19; // [19:19] Event Mask on line 19 + Object *mr20; // [20:20] Event Mask on line 20 + Object *mr21; // [21:21] Event Mask on line 21 + Object *mr22; // [22:22] Event Mask on line 22 + } emr; + + // RTSR (Rising Trigger selection register (EXTI_RTSR)) bitfields. + struct { + Object *tr0; // [0:0] Rising trigger event configuration of line 0 + Object *tr1; // [1:1] Rising trigger event configuration of line 1 + Object *tr2; // [2:2] Rising trigger event configuration of line 2 + Object *tr3; // [3:3] Rising trigger event configuration of line 3 + Object *tr4; // [4:4] Rising trigger event configuration of line 4 + Object *tr5; // [5:5] Rising trigger event configuration of line 5 + Object *tr6; // [6:6] Rising trigger event configuration of line 6 + Object *tr7; // [7:7] Rising trigger event configuration of line 7 + Object *tr8; // [8:8] Rising trigger event configuration of line 8 + Object *tr9; // [9:9] Rising trigger event configuration of line 9 + Object *tr10; // [10:10] Rising trigger event configuration of line 10 + Object *tr11; // [11:11] Rising trigger event configuration of line 11 + Object *tr12; // [12:12] Rising trigger event configuration of line 12 + Object *tr13; // [13:13] Rising trigger event configuration of line 13 + Object *tr14; // [14:14] Rising trigger event configuration of line 14 + Object *tr15; // [15:15] Rising trigger event configuration of line 15 + Object *tr16; // [16:16] Rising trigger event configuration of line 16 + Object *tr17; // [17:17] Rising trigger event configuration of line 17 + Object *tr18; // [18:18] Rising trigger event configuration of line 18 + Object *tr19; // [19:19] Rising trigger event configuration of line 19 + Object *tr20; // [20:20] Rising trigger event configuration of line 20 + Object *tr21; // [21:21] Rising trigger event configuration of line 21 + Object *tr22; // [22:22] Rising trigger event configuration of line 22 + } rtsr; + + // FTSR (Falling Trigger selection register (EXTI_FTSR)) bitfields. + struct { + Object *tr0; // [0:0] Falling trigger event configuration of line 0 + Object *tr1; // [1:1] Falling trigger event configuration of line 1 + Object *tr2; // [2:2] Falling trigger event configuration of line 2 + Object *tr3; // [3:3] Falling trigger event configuration of line 3 + Object *tr4; // [4:4] Falling trigger event configuration of line 4 + Object *tr5; // [5:5] Falling trigger event configuration of line 5 + Object *tr6; // [6:6] Falling trigger event configuration of line 6 + Object *tr7; // [7:7] Falling trigger event configuration of line 7 + Object *tr8; // [8:8] Falling trigger event configuration of line 8 + Object *tr9; // [9:9] Falling trigger event configuration of line 9 + Object *tr10; // [10:10] Falling trigger event configuration of line 10 + Object *tr11; // [11:11] Falling trigger event configuration of line 11 + Object *tr12; // [12:12] Falling trigger event configuration of line 12 + Object *tr13; // [13:13] Falling trigger event configuration of line 13 + Object *tr14; // [14:14] Falling trigger event configuration of line 14 + Object *tr15; // [15:15] Falling trigger event configuration of line 15 + Object *tr16; // [16:16] Falling trigger event configuration of line 16 + Object *tr17; // [17:17] Falling trigger event configuration of line 17 + Object *tr18; // [18:18] Falling trigger event configuration of line 18 + Object *tr19; // [19:19] Falling trigger event configuration of line 19 + Object *tr20; // [20:20] Falling trigger event configuration of line 20 + Object *tr21; // [21:21] Falling trigger event configuration of line 21 + Object *tr22; // [22:22] Falling trigger event configuration of line 22 + } ftsr; + + // SWIER (Software interrupt event register (EXTI_SWIER)) bitfields. + struct { + Object *swier0; // [0:0] Software Interrupt on line 0 + Object *swier1; // [1:1] Software Interrupt on line 1 + Object *swier2; // [2:2] Software Interrupt on line 2 + Object *swier3; // [3:3] Software Interrupt on line 3 + Object *swier4; // [4:4] Software Interrupt on line 4 + Object *swier5; // [5:5] Software Interrupt on line 5 + Object *swier6; // [6:6] Software Interrupt on line 6 + Object *swier7; // [7:7] Software Interrupt on line 7 + Object *swier8; // [8:8] Software Interrupt on line 8 + Object *swier9; // [9:9] Software Interrupt on line 9 + Object *swier10; // [10:10] Software Interrupt on line 10 + Object *swier11; // [11:11] Software Interrupt on line 11 + Object *swier12; // [12:12] Software Interrupt on line 12 + Object *swier13; // [13:13] Software Interrupt on line 13 + Object *swier14; // [14:14] Software Interrupt on line 14 + Object *swier15; // [15:15] Software Interrupt on line 15 + Object *swier16; // [16:16] Software Interrupt on line 16 + Object *swier17; // [17:17] Software Interrupt on line 17 + Object *swier18; // [18:18] Software Interrupt on line 18 + Object *swier19; // [19:19] Software Interrupt on line 19 + Object *swier20; // [20:20] Software Interrupt on line 20 + Object *swier21; // [21:21] Software Interrupt on line 21 + Object *swier22; // [22:22] Software Interrupt on line 22 + } swier; + + // PR (Pending register (EXTI_PR)) bitfields. + struct { + Object *pr0; // [0:0] Pending bit 0 + Object *pr1; // [1:1] Pending bit 1 + Object *pr2; // [2:2] Pending bit 2 + Object *pr3; // [3:3] Pending bit 3 + Object *pr4; // [4:4] Pending bit 4 + Object *pr5; // [5:5] Pending bit 5 + Object *pr6; // [6:6] Pending bit 6 + Object *pr7; // [7:7] Pending bit 7 + Object *pr8; // [8:8] Pending bit 8 + Object *pr9; // [9:9] Pending bit 9 + Object *pr10; // [10:10] Pending bit 10 + Object *pr11; // [11:11] Pending bit 11 + Object *pr12; // [12:12] Pending bit 12 + Object *pr13; // [13:13] Pending bit 13 + Object *pr14; // [14:14] Pending bit 14 + Object *pr15; // [15:15] Pending bit 15 + Object *pr16; // [16:16] Pending bit 16 + Object *pr17; // [17:17] Pending bit 17 + Object *pr18; // [18:18] Pending bit 18 + Object *pr19; // [19:19] Pending bit 19 + Object *pr20; // [20:20] Pending bit 20 + Object *pr21; // [21:21] Pending bit 21 + Object *pr22; // [22:22] Pending bit 22 + } pr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32EXTIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_EXTI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/flash.c b/gnu-mcu-eclipse/devices/support/STM32F40x/flash.c new file mode 100644 index 0000000000..a219286946 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/flash.c @@ -0,0 +1,284 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_flash_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.acr = cm_object_get_child_by_name(obj, "ACR"); + state->u.f4.reg.keyr = cm_object_get_child_by_name(obj, "KEYR"); + state->u.f4.reg.optkeyr = cm_object_get_child_by_name(obj, "OPTKEYR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.optcr = cm_object_get_child_by_name(obj, "OPTCR"); + + + // ACR bitfields. + state->u.f4.fld.acr.latency = cm_object_get_child_by_name(state->u.f4.reg.acr, "LATENCY"); + state->u.f4.fld.acr.prften = cm_object_get_child_by_name(state->u.f4.reg.acr, "PRFTEN"); + state->u.f4.fld.acr.icen = cm_object_get_child_by_name(state->u.f4.reg.acr, "ICEN"); + state->u.f4.fld.acr.dcen = cm_object_get_child_by_name(state->u.f4.reg.acr, "DCEN"); + state->u.f4.fld.acr.icrst = cm_object_get_child_by_name(state->u.f4.reg.acr, "ICRST"); + state->u.f4.fld.acr.dcrst = cm_object_get_child_by_name(state->u.f4.reg.acr, "DCRST"); + + // KEYR bitfields. + state->u.f4.fld.keyr.key = cm_object_get_child_by_name(state->u.f4.reg.keyr, "KEY"); + + // OPTKEYR bitfields. + state->u.f4.fld.optkeyr.optkey = cm_object_get_child_by_name(state->u.f4.reg.optkeyr, "OPTKEY"); + + // SR bitfields. + state->u.f4.fld.sr.eop = cm_object_get_child_by_name(state->u.f4.reg.sr, "EOP"); + state->u.f4.fld.sr.operr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OPERR"); + state->u.f4.fld.sr.wrperr = cm_object_get_child_by_name(state->u.f4.reg.sr, "WRPERR"); + state->u.f4.fld.sr.pgaerr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGAERR"); + state->u.f4.fld.sr.pgperr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGPERR"); + state->u.f4.fld.sr.pgserr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGSERR"); + state->u.f4.fld.sr.bsy = cm_object_get_child_by_name(state->u.f4.reg.sr, "BSY"); + + // CR bitfields. + state->u.f4.fld.cr.pg = cm_object_get_child_by_name(state->u.f4.reg.cr, "PG"); + state->u.f4.fld.cr.ser = cm_object_get_child_by_name(state->u.f4.reg.cr, "SER"); + state->u.f4.fld.cr.mer = cm_object_get_child_by_name(state->u.f4.reg.cr, "MER"); + state->u.f4.fld.cr.snb = cm_object_get_child_by_name(state->u.f4.reg.cr, "SNB"); + state->u.f4.fld.cr.psize = cm_object_get_child_by_name(state->u.f4.reg.cr, "PSIZE"); + state->u.f4.fld.cr.strt = cm_object_get_child_by_name(state->u.f4.reg.cr, "STRT"); + state->u.f4.fld.cr.eopie = cm_object_get_child_by_name(state->u.f4.reg.cr, "EOPIE"); + state->u.f4.fld.cr.errie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ERRIE"); + state->u.f4.fld.cr.lock = cm_object_get_child_by_name(state->u.f4.reg.cr, "LOCK"); + + // OPTCR bitfields. + state->u.f4.fld.optcr.optlock = cm_object_get_child_by_name(state->u.f4.reg.optcr, "OPTLOCK"); + state->u.f4.fld.optcr.optstrt = cm_object_get_child_by_name(state->u.f4.reg.optcr, "OPTSTRT"); + state->u.f4.fld.optcr.bor_lev = cm_object_get_child_by_name(state->u.f4.reg.optcr, "BOR_LEV"); + state->u.f4.fld.optcr.wdg_sw = cm_object_get_child_by_name(state->u.f4.reg.optcr, "WDG_SW"); + state->u.f4.fld.optcr.nrst_stop = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nRST_STOP"); + state->u.f4.fld.optcr.nrst_stdby = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nRST_STDBY"); + state->u.f4.fld.optcr.rdp = cm_object_get_child_by_name(state->u.f4.reg.optcr, "RDP"); + state->u.f4.fld.optcr.nwrp = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nWRP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_flash_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_flash_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_flash_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_flash_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_flash_is_enabled(Object *obj) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_flash_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_flash_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FLASH)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FLASHState *state = STM32_FLASH_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FLASH"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_flash_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_flash_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_flash_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_flash_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_flash_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FLASHEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_flash_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FLASH); +} + +static void stm32_flash_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_flash_reset_callback; + dc->realize = stm32_flash_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_flash_is_enabled; +} + +static const TypeInfo stm32_flash_type_info = { + .name = TYPE_STM32_FLASH, + .parent = TYPE_STM32_FLASH_PARENT, + .instance_init = stm32_flash_instance_init_callback, + .instance_size = sizeof(STM32FLASHState), + .class_init = stm32_flash_class_init_callback, + .class_size = sizeof(STM32FLASHClass) }; + +static void stm32_flash_register_types(void) +{ + type_register_static(&stm32_flash_type_info); +} + +type_init(stm32_flash_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/flash.h b/gnu-mcu-eclipse/devices/support/STM32F40x/flash.h new file mode 100644 index 0000000000..21558b4bbe --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/flash.h @@ -0,0 +1,161 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FLASH_H_ +#define STM32_FLASH_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FLASH DEVICE_PATH_STM32 "FLASH" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FLASH TYPE_STM32_PREFIX "flash" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FLASH_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FLASHParentClass; +typedef PeripheralState STM32FLASHParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FLASH_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FLASHClass, (obj), TYPE_STM32_FLASH) +#define STM32_FLASH_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FLASHClass, (klass), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentClass parent_class; + // public: + + // None, so far. +} STM32FLASHClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FLASH_STATE(obj) \ + OBJECT_CHECK(STM32FLASHState, (obj), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 FLASH (FLASH) registers. + struct { + Object *acr; // 0x0 (Flash access control register) + Object *keyr; // 0x4 (Flash key register) + Object *optkeyr; // 0x8 (Flash option key register) + Object *sr; // 0xC (Status register) + Object *cr; // 0x10 (Control register) + Object *optcr; // 0x14 (Flash option control register) + } reg; + + struct { + + // ACR (Flash access control register) bitfields. + struct { + Object *latency; // [0:2] Latency + Object *prften; // [8:8] Prefetch enable + Object *icen; // [9:9] Instruction cache enable + Object *dcen; // [10:10] Data cache enable + Object *icrst; // [11:11] Instruction cache reset + Object *dcrst; // [12:12] Data cache reset + } acr; + + // KEYR (Flash key register) bitfields. + struct { + Object *key; // [0:31] FPEC key + } keyr; + + // OPTKEYR (Flash option key register) bitfields. + struct { + Object *optkey; // [0:31] Option byte key + } optkeyr; + + // SR (Status register) bitfields. + struct { + Object *eop; // [0:0] End of operation + Object *operr; // [1:1] Operation error + Object *wrperr; // [4:4] Write protection error + Object *pgaerr; // [5:5] Programming alignment error + Object *pgperr; // [6:6] Programming parallelism error + Object *pgserr; // [7:7] Programming sequence error + Object *bsy; // [16:16] Busy + } sr; + + // CR (Control register) bitfields. + struct { + Object *pg; // [0:0] Programming + Object *ser; // [1:1] Sector Erase + Object *mer; // [2:2] Mass Erase + Object *snb; // [3:6] Sector number + Object *psize; // [8:9] Program size + Object *strt; // [16:16] Start + Object *eopie; // [24:24] End of operation interrupt enable + Object *errie; // [25:25] Error interrupt enable + Object *lock; // [31:31] Lock + } cr; + + // OPTCR (Flash option control register) bitfields. + struct { + Object *optlock; // [0:0] Option lock + Object *optstrt; // [1:1] Option start + Object *bor_lev; // [2:3] BOR reset Level + Object *wdg_sw; // [5:5] WDG_SW User option bytes + Object *nrst_stop; // [6:6] NRST_STOP User option bytes + Object *nrst_stdby; // [7:7] NRST_STDBY User option bytes + Object *rdp; // [8:15] Read protect + Object *nwrp; // [16:27] Not write protect + } optcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FLASHState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FLASH_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/fsmc.c b/gnu-mcu-eclipse/devices/support/STM32F40x/fsmc.c new file mode 100644 index 0000000000..2eb0451193 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/fsmc.c @@ -0,0 +1,497 @@ +/* + * STM32 - FSMC (Flexible static memory controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_fsmc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FSMCState *state = STM32_FSMC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.bcr1 = cm_object_get_child_by_name(obj, "BCR1"); + state->u.f4.reg.btr1 = cm_object_get_child_by_name(obj, "BTR1"); + state->u.f4.reg.bcr2 = cm_object_get_child_by_name(obj, "BCR2"); + state->u.f4.reg.btr2 = cm_object_get_child_by_name(obj, "BTR2"); + state->u.f4.reg.bcr3 = cm_object_get_child_by_name(obj, "BCR3"); + state->u.f4.reg.btr3 = cm_object_get_child_by_name(obj, "BTR3"); + state->u.f4.reg.bcr4 = cm_object_get_child_by_name(obj, "BCR4"); + state->u.f4.reg.btr4 = cm_object_get_child_by_name(obj, "BTR4"); + state->u.f4.reg.pcr2 = cm_object_get_child_by_name(obj, "PCR2"); + state->u.f4.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f4.reg.pmem2 = cm_object_get_child_by_name(obj, "PMEM2"); + state->u.f4.reg.patt2 = cm_object_get_child_by_name(obj, "PATT2"); + state->u.f4.reg.eccr2 = cm_object_get_child_by_name(obj, "ECCR2"); + state->u.f4.reg.pcr3 = cm_object_get_child_by_name(obj, "PCR3"); + state->u.f4.reg.sr3 = cm_object_get_child_by_name(obj, "SR3"); + state->u.f4.reg.pmem3 = cm_object_get_child_by_name(obj, "PMEM3"); + state->u.f4.reg.patt3 = cm_object_get_child_by_name(obj, "PATT3"); + state->u.f4.reg.eccr3 = cm_object_get_child_by_name(obj, "ECCR3"); + state->u.f4.reg.pcr4 = cm_object_get_child_by_name(obj, "PCR4"); + state->u.f4.reg.sr4 = cm_object_get_child_by_name(obj, "SR4"); + state->u.f4.reg.pmem4 = cm_object_get_child_by_name(obj, "PMEM4"); + state->u.f4.reg.patt4 = cm_object_get_child_by_name(obj, "PATT4"); + state->u.f4.reg.pio4 = cm_object_get_child_by_name(obj, "PIO4"); + state->u.f4.reg.bwtr1 = cm_object_get_child_by_name(obj, "BWTR1"); + state->u.f4.reg.bwtr2 = cm_object_get_child_by_name(obj, "BWTR2"); + state->u.f4.reg.bwtr3 = cm_object_get_child_by_name(obj, "BWTR3"); + state->u.f4.reg.bwtr4 = cm_object_get_child_by_name(obj, "BWTR4"); + + + // BCR1 bitfields. + state->u.f4.fld.bcr1.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MBKEN"); + state->u.f4.fld.bcr1.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MUXEN"); + state->u.f4.fld.bcr1.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MTYP"); + state->u.f4.fld.bcr1.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MWID"); + state->u.f4.fld.bcr1.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "FACCEN"); + state->u.f4.fld.bcr1.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "BURSTEN"); + state->u.f4.fld.bcr1.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WAITPOL"); + state->u.f4.fld.bcr1.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WAITCFG"); + state->u.f4.fld.bcr1.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WREN"); + state->u.f4.fld.bcr1.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WAITEN"); + state->u.f4.fld.bcr1.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "EXTMOD"); + state->u.f4.fld.bcr1.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "ASYNCWAIT"); + state->u.f4.fld.bcr1.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "CBURSTRW"); + + // BTR1 bitfields. + state->u.f4.fld.btr1.addset = cm_object_get_child_by_name(state->u.f4.reg.btr1, "ADDSET"); + state->u.f4.fld.btr1.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr1, "ADDHLD"); + state->u.f4.fld.btr1.datast = cm_object_get_child_by_name(state->u.f4.reg.btr1, "DATAST"); + state->u.f4.fld.btr1.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr1, "BUSTURN"); + state->u.f4.fld.btr1.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr1, "CLKDIV"); + state->u.f4.fld.btr1.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr1, "DATLAT"); + state->u.f4.fld.btr1.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr1, "ACCMOD"); + + // BCR2 bitfields. + state->u.f4.fld.bcr2.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MBKEN"); + state->u.f4.fld.bcr2.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MUXEN"); + state->u.f4.fld.bcr2.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MTYP"); + state->u.f4.fld.bcr2.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MWID"); + state->u.f4.fld.bcr2.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "FACCEN"); + state->u.f4.fld.bcr2.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "BURSTEN"); + state->u.f4.fld.bcr2.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WAITPOL"); + state->u.f4.fld.bcr2.wrapmod = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WRAPMOD"); + state->u.f4.fld.bcr2.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WAITCFG"); + state->u.f4.fld.bcr2.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WREN"); + state->u.f4.fld.bcr2.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WAITEN"); + state->u.f4.fld.bcr2.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "EXTMOD"); + state->u.f4.fld.bcr2.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "ASYNCWAIT"); + state->u.f4.fld.bcr2.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "CBURSTRW"); + + // BTR2 bitfields. + state->u.f4.fld.btr2.addset = cm_object_get_child_by_name(state->u.f4.reg.btr2, "ADDSET"); + state->u.f4.fld.btr2.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr2, "ADDHLD"); + state->u.f4.fld.btr2.datast = cm_object_get_child_by_name(state->u.f4.reg.btr2, "DATAST"); + state->u.f4.fld.btr2.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr2, "BUSTURN"); + state->u.f4.fld.btr2.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr2, "CLKDIV"); + state->u.f4.fld.btr2.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr2, "DATLAT"); + state->u.f4.fld.btr2.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr2, "ACCMOD"); + + // BCR3 bitfields. + state->u.f4.fld.bcr3.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MBKEN"); + state->u.f4.fld.bcr3.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MUXEN"); + state->u.f4.fld.bcr3.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MTYP"); + state->u.f4.fld.bcr3.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MWID"); + state->u.f4.fld.bcr3.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "FACCEN"); + state->u.f4.fld.bcr3.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "BURSTEN"); + state->u.f4.fld.bcr3.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WAITPOL"); + state->u.f4.fld.bcr3.wrapmod = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WRAPMOD"); + state->u.f4.fld.bcr3.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WAITCFG"); + state->u.f4.fld.bcr3.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WREN"); + state->u.f4.fld.bcr3.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WAITEN"); + state->u.f4.fld.bcr3.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "EXTMOD"); + state->u.f4.fld.bcr3.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "ASYNCWAIT"); + state->u.f4.fld.bcr3.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "CBURSTRW"); + + // BTR3 bitfields. + state->u.f4.fld.btr3.addset = cm_object_get_child_by_name(state->u.f4.reg.btr3, "ADDSET"); + state->u.f4.fld.btr3.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr3, "ADDHLD"); + state->u.f4.fld.btr3.datast = cm_object_get_child_by_name(state->u.f4.reg.btr3, "DATAST"); + state->u.f4.fld.btr3.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr3, "BUSTURN"); + state->u.f4.fld.btr3.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr3, "CLKDIV"); + state->u.f4.fld.btr3.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr3, "DATLAT"); + state->u.f4.fld.btr3.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr3, "ACCMOD"); + + // BCR4 bitfields. + state->u.f4.fld.bcr4.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MBKEN"); + state->u.f4.fld.bcr4.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MUXEN"); + state->u.f4.fld.bcr4.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MTYP"); + state->u.f4.fld.bcr4.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MWID"); + state->u.f4.fld.bcr4.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "FACCEN"); + state->u.f4.fld.bcr4.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "BURSTEN"); + state->u.f4.fld.bcr4.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WAITPOL"); + state->u.f4.fld.bcr4.wrapmod = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WRAPMOD"); + state->u.f4.fld.bcr4.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WAITCFG"); + state->u.f4.fld.bcr4.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WREN"); + state->u.f4.fld.bcr4.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WAITEN"); + state->u.f4.fld.bcr4.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "EXTMOD"); + state->u.f4.fld.bcr4.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "ASYNCWAIT"); + state->u.f4.fld.bcr4.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "CBURSTRW"); + + // BTR4 bitfields. + state->u.f4.fld.btr4.addset = cm_object_get_child_by_name(state->u.f4.reg.btr4, "ADDSET"); + state->u.f4.fld.btr4.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr4, "ADDHLD"); + state->u.f4.fld.btr4.datast = cm_object_get_child_by_name(state->u.f4.reg.btr4, "DATAST"); + state->u.f4.fld.btr4.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr4, "BUSTURN"); + state->u.f4.fld.btr4.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr4, "CLKDIV"); + state->u.f4.fld.btr4.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr4, "DATLAT"); + state->u.f4.fld.btr4.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr4, "ACCMOD"); + + // PCR2 bitfields. + state->u.f4.fld.pcr2.pwaiten = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PWAITEN"); + state->u.f4.fld.pcr2.pbken = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PBKEN"); + state->u.f4.fld.pcr2.ptyp = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PTYP"); + state->u.f4.fld.pcr2.pwid = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PWID"); + state->u.f4.fld.pcr2.eccen = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "ECCEN"); + state->u.f4.fld.pcr2.tclr = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "TCLR"); + state->u.f4.fld.pcr2.tar = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "TAR"); + state->u.f4.fld.pcr2.eccps = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "ECCPS"); + + // SR2 bitfields. + state->u.f4.fld.sr2.irs = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IRS"); + state->u.f4.fld.sr2.ils = cm_object_get_child_by_name(state->u.f4.reg.sr2, "ILS"); + state->u.f4.fld.sr2.ifs = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IFS"); + state->u.f4.fld.sr2.iren = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IREN"); + state->u.f4.fld.sr2.ilen = cm_object_get_child_by_name(state->u.f4.reg.sr2, "ILEN"); + state->u.f4.fld.sr2.ifen = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IFEN"); + state->u.f4.fld.sr2.fempt = cm_object_get_child_by_name(state->u.f4.reg.sr2, "FEMPT"); + + // PMEM2 bitfields. + state->u.f4.fld.pmem2.memsetx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMSETx"); + state->u.f4.fld.pmem2.memwaitx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMWAITx"); + state->u.f4.fld.pmem2.memholdx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMHOLDx"); + state->u.f4.fld.pmem2.memhizx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMHIZx"); + + // PATT2 bitfields. + state->u.f4.fld.patt2.attsetx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTSETx"); + state->u.f4.fld.patt2.attwaitx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTWAITx"); + state->u.f4.fld.patt2.attholdx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTHOLDx"); + state->u.f4.fld.patt2.atthizx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTHIZx"); + + // ECCR2 bitfields. + state->u.f4.fld.eccr2.eccx = cm_object_get_child_by_name(state->u.f4.reg.eccr2, "ECCx"); + + // PCR3 bitfields. + state->u.f4.fld.pcr3.pwaiten = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PWAITEN"); + state->u.f4.fld.pcr3.pbken = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PBKEN"); + state->u.f4.fld.pcr3.ptyp = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PTYP"); + state->u.f4.fld.pcr3.pwid = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PWID"); + state->u.f4.fld.pcr3.eccen = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "ECCEN"); + state->u.f4.fld.pcr3.tclr = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "TCLR"); + state->u.f4.fld.pcr3.tar = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "TAR"); + state->u.f4.fld.pcr3.eccps = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "ECCPS"); + + // SR3 bitfields. + state->u.f4.fld.sr3.irs = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IRS"); + state->u.f4.fld.sr3.ils = cm_object_get_child_by_name(state->u.f4.reg.sr3, "ILS"); + state->u.f4.fld.sr3.ifs = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IFS"); + state->u.f4.fld.sr3.iren = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IREN"); + state->u.f4.fld.sr3.ilen = cm_object_get_child_by_name(state->u.f4.reg.sr3, "ILEN"); + state->u.f4.fld.sr3.ifen = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IFEN"); + state->u.f4.fld.sr3.fempt = cm_object_get_child_by_name(state->u.f4.reg.sr3, "FEMPT"); + + // PMEM3 bitfields. + state->u.f4.fld.pmem3.memsetx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMSETx"); + state->u.f4.fld.pmem3.memwaitx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMWAITx"); + state->u.f4.fld.pmem3.memholdx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMHOLDx"); + state->u.f4.fld.pmem3.memhizx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMHIZx"); + + // PATT3 bitfields. + state->u.f4.fld.patt3.attsetx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTSETx"); + state->u.f4.fld.patt3.attwaitx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTWAITx"); + state->u.f4.fld.patt3.attholdx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTHOLDx"); + state->u.f4.fld.patt3.atthizx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTHIZx"); + + // ECCR3 bitfields. + state->u.f4.fld.eccr3.eccx = cm_object_get_child_by_name(state->u.f4.reg.eccr3, "ECCx"); + + // PCR4 bitfields. + state->u.f4.fld.pcr4.pwaiten = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PWAITEN"); + state->u.f4.fld.pcr4.pbken = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PBKEN"); + state->u.f4.fld.pcr4.ptyp = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PTYP"); + state->u.f4.fld.pcr4.pwid = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PWID"); + state->u.f4.fld.pcr4.eccen = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "ECCEN"); + state->u.f4.fld.pcr4.tclr = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "TCLR"); + state->u.f4.fld.pcr4.tar = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "TAR"); + state->u.f4.fld.pcr4.eccps = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "ECCPS"); + + // SR4 bitfields. + state->u.f4.fld.sr4.irs = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IRS"); + state->u.f4.fld.sr4.ils = cm_object_get_child_by_name(state->u.f4.reg.sr4, "ILS"); + state->u.f4.fld.sr4.ifs = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IFS"); + state->u.f4.fld.sr4.iren = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IREN"); + state->u.f4.fld.sr4.ilen = cm_object_get_child_by_name(state->u.f4.reg.sr4, "ILEN"); + state->u.f4.fld.sr4.ifen = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IFEN"); + state->u.f4.fld.sr4.fempt = cm_object_get_child_by_name(state->u.f4.reg.sr4, "FEMPT"); + + // PMEM4 bitfields. + state->u.f4.fld.pmem4.memsetx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMSETx"); + state->u.f4.fld.pmem4.memwaitx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMWAITx"); + state->u.f4.fld.pmem4.memholdx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMHOLDx"); + state->u.f4.fld.pmem4.memhizx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMHIZx"); + + // PATT4 bitfields. + state->u.f4.fld.patt4.attsetx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTSETx"); + state->u.f4.fld.patt4.attwaitx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTWAITx"); + state->u.f4.fld.patt4.attholdx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTHOLDx"); + state->u.f4.fld.patt4.atthizx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTHIZx"); + + // PIO4 bitfields. + state->u.f4.fld.pio4.iosetx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOSETx"); + state->u.f4.fld.pio4.iowaitx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOWAITx"); + state->u.f4.fld.pio4.ioholdx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOHOLDx"); + state->u.f4.fld.pio4.iohizx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOHIZx"); + + // BWTR1 bitfields. + state->u.f4.fld.bwtr1.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "ADDSET"); + state->u.f4.fld.bwtr1.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "ADDHLD"); + state->u.f4.fld.bwtr1.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "DATAST"); + state->u.f4.fld.bwtr1.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "CLKDIV"); + state->u.f4.fld.bwtr1.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "DATLAT"); + state->u.f4.fld.bwtr1.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "ACCMOD"); + + // BWTR2 bitfields. + state->u.f4.fld.bwtr2.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "ADDSET"); + state->u.f4.fld.bwtr2.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "ADDHLD"); + state->u.f4.fld.bwtr2.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "DATAST"); + state->u.f4.fld.bwtr2.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "CLKDIV"); + state->u.f4.fld.bwtr2.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "DATLAT"); + state->u.f4.fld.bwtr2.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "ACCMOD"); + + // BWTR3 bitfields. + state->u.f4.fld.bwtr3.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "ADDSET"); + state->u.f4.fld.bwtr3.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "ADDHLD"); + state->u.f4.fld.bwtr3.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "DATAST"); + state->u.f4.fld.bwtr3.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "CLKDIV"); + state->u.f4.fld.bwtr3.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "DATLAT"); + state->u.f4.fld.bwtr3.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "ACCMOD"); + + // BWTR4 bitfields. + state->u.f4.fld.bwtr4.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "ADDSET"); + state->u.f4.fld.bwtr4.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "ADDHLD"); + state->u.f4.fld.bwtr4.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "DATAST"); + state->u.f4.fld.bwtr4.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "CLKDIV"); + state->u.f4.fld.bwtr4.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "DATLAT"); + state->u.f4.fld.bwtr4.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "ACCMOD"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_fsmc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_fsmc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_fsmc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_fsmc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FSMCState *state = STM32_FSMC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_fsmc_is_enabled(Object *obj) +{ + STM32FSMCState *state = STM32_FSMC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_fsmc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FSMCState *state = STM32_FSMC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_fsmc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FSMC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FSMCState *state = STM32_FSMC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FSMC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_fsmc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_fsmc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_fsmc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_fsmc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_fsmc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FSMCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_fsmc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FSMC); +} + +static void stm32_fsmc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_fsmc_reset_callback; + dc->realize = stm32_fsmc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_fsmc_is_enabled; +} + +static const TypeInfo stm32_fsmc_type_info = { + .name = TYPE_STM32_FSMC, + .parent = TYPE_STM32_FSMC_PARENT, + .instance_init = stm32_fsmc_instance_init_callback, + .instance_size = sizeof(STM32FSMCState), + .class_init = stm32_fsmc_class_init_callback, + .class_size = sizeof(STM32FSMCClass) }; + +static void stm32_fsmc_register_types(void) +{ + type_register_static(&stm32_fsmc_type_info); +} + +type_init(stm32_fsmc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/fsmc.h b/gnu-mcu-eclipse/devices/support/STM32F40x/fsmc.h new file mode 100644 index 0000000000..bb87dc8a01 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/fsmc.h @@ -0,0 +1,416 @@ +/* + * STM32 - FSMC (Flexible static memory controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FSMC_H_ +#define STM32_FSMC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FSMC DEVICE_PATH_STM32 "FSMC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FSMC TYPE_STM32_PREFIX "fsmc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FSMC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FSMCParentClass; +typedef PeripheralState STM32FSMCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FSMC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FSMCClass, (obj), TYPE_STM32_FSMC) +#define STM32_FSMC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FSMCClass, (klass), TYPE_STM32_FSMC) + +typedef struct { + // private: + STM32FSMCParentClass parent_class; + // public: + + // None, so far. +} STM32FSMCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FSMC_STATE(obj) \ + OBJECT_CHECK(STM32FSMCState, (obj), TYPE_STM32_FSMC) + +typedef struct { + // private: + STM32FSMCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 FSMC (Flexible static memory controller) registers. + struct { + Object *bcr1; // 0x0 (SRAM/NOR-Flash chip-select control register 1) + Object *btr1; // 0x4 (SRAM/NOR-Flash chip-select timing register 1) + Object *bcr2; // 0x8 (SRAM/NOR-Flash chip-select control register 2) + Object *btr2; // 0xC (SRAM/NOR-Flash chip-select timing register 2) + Object *bcr3; // 0x10 (SRAM/NOR-Flash chip-select control register 3) + Object *btr3; // 0x14 (SRAM/NOR-Flash chip-select timing register 3) + Object *bcr4; // 0x18 (SRAM/NOR-Flash chip-select control register 4) + Object *btr4; // 0x1C (SRAM/NOR-Flash chip-select timing register 4) + Object *pcr2; // 0x60 (PC Card/NAND Flash control register 2) + Object *sr2; // 0x64 (FIFO status and interrupt register 2) + Object *pmem2; // 0x68 (Common memory space timing register 2) + Object *patt2; // 0x6C (Attribute memory space timing register 2) + Object *eccr2; // 0x74 (ECC result register 2) + Object *pcr3; // 0x80 (PC Card/NAND Flash control register 3) + Object *sr3; // 0x84 (FIFO status and interrupt register 3) + Object *pmem3; // 0x88 (Common memory space timing register 3) + Object *patt3; // 0x8C (Attribute memory space timing register 3) + Object *eccr3; // 0x94 (ECC result register 3) + Object *pcr4; // 0xA0 (PC Card/NAND Flash control register 4) + Object *sr4; // 0xA4 (FIFO status and interrupt register 4) + Object *pmem4; // 0xA8 (Common memory space timing register 4) + Object *patt4; // 0xAC (Attribute memory space timing register 4) + Object *pio4; // 0xB0 (I/O space timing register 4) + Object *bwtr1; // 0x104 (SRAM/NOR-Flash write timing registers 1) + Object *bwtr2; // 0x10C (SRAM/NOR-Flash write timing registers 2) + Object *bwtr3; // 0x114 (SRAM/NOR-Flash write timing registers 3) + Object *bwtr4; // 0x11C (SRAM/NOR-Flash write timing registers 4) + } reg; + + struct { + + // BCR1 (SRAM/NOR-Flash chip-select control register 1) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr1; + + // BTR1 (SRAM/NOR-Flash chip-select timing register 1) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr1; + + // BCR2 (SRAM/NOR-Flash chip-select control register 2) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr2; + + // BTR2 (SRAM/NOR-Flash chip-select timing register 2) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr2; + + // BCR3 (SRAM/NOR-Flash chip-select control register 3) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr3; + + // BTR3 (SRAM/NOR-Flash chip-select timing register 3) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr3; + + // BCR4 (SRAM/NOR-Flash chip-select control register 4) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr4; + + // BTR4 (SRAM/NOR-Flash chip-select timing register 4) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr4; + + // PCR2 (PC Card/NAND Flash control register 2) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr2; + + // SR2 (FIFO status and interrupt register 2) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr2; + + // PMEM2 (Common memory space timing register 2) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem2; + + // PATT2 (Attribute memory space timing register 2) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt2; + + // ECCR2 (ECC result register 2) bitfields. + struct { + Object *eccx; // [0:31] ECCx + } eccr2; + + // PCR3 (PC Card/NAND Flash control register 3) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr3; + + // SR3 (FIFO status and interrupt register 3) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr3; + + // PMEM3 (Common memory space timing register 3) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem3; + + // PATT3 (Attribute memory space timing register 3) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt3; + + // ECCR3 (ECC result register 3) bitfields. + struct { + Object *eccx; // [0:31] ECCx + } eccr3; + + // PCR4 (PC Card/NAND Flash control register 4) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr4; + + // SR4 (FIFO status and interrupt register 4) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr4; + + // PMEM4 (Common memory space timing register 4) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem4; + + // PATT4 (Attribute memory space timing register 4) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt4; + + // PIO4 (I/O space timing register 4) bitfields. + struct { + Object *iosetx; // [0:7] IOSETx + Object *iowaitx; // [8:15] IOWAITx + Object *ioholdx; // [16:23] IOHOLDx + Object *iohizx; // [24:31] IOHIZx + } pio4; + + // BWTR1 (SRAM/NOR-Flash write timing registers 1) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr1; + + // BWTR2 (SRAM/NOR-Flash write timing registers 2) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr2; + + // BWTR3 (SRAM/NOR-Flash write timing registers 3) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr3; + + // BWTR4 (SRAM/NOR-Flash write timing registers 4) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr4; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FSMCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FSMC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/gpioa.c b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioa.c new file mode 100644 index 0000000000..f9cc2bb607 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioa.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/gpioa.h b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioa.h new file mode 100644 index 0000000000..82d1aef4b2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioa.h @@ -0,0 +1,328 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIOG, + STM32_PORT_GPIOH, + STM32_PORT_GPIOI, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/gpiob.c b/gnu-mcu-eclipse/devices/support/STM32F40x/gpiob.c new file mode 100644 index 0000000000..f9cc2bb607 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/gpiob.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/gpiob.h b/gnu-mcu-eclipse/devices/support/STM32F40x/gpiob.h new file mode 100644 index 0000000000..82d1aef4b2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/gpiob.h @@ -0,0 +1,328 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIOG, + STM32_PORT_GPIOH, + STM32_PORT_GPIOI, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/gpioi.c b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioi.c new file mode 100644 index 0000000000..f9cc2bb607 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioi.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/gpioi.h b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioi.h new file mode 100644 index 0000000000..82d1aef4b2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/gpioi.h @@ -0,0 +1,328 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIOG, + STM32_PORT_GPIOH, + STM32_PORT_GPIOI, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/i2c3.c b/gnu-mcu-eclipse/devices/support/STM32F40x/i2c3.c new file mode 100644 index 0000000000..54161e58e2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/i2c3.c @@ -0,0 +1,319 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_i2c_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.oar1 = cm_object_get_child_by_name(obj, "OAR1"); + state->u.f4.reg.oar2 = cm_object_get_child_by_name(obj, "OAR2"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.sr1 = cm_object_get_child_by_name(obj, "SR1"); + state->u.f4.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f4.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + state->u.f4.reg.trise = cm_object_get_child_by_name(obj, "TRISE"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.pe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PE"); + state->u.f4.fld.cr1.smbus = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SMBUS"); + state->u.f4.fld.cr1.smbtype = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SMBTYPE"); + state->u.f4.fld.cr1.enarp = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENARP"); + state->u.f4.fld.cr1.enpec = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENPEC"); + state->u.f4.fld.cr1.engc = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENGC"); + state->u.f4.fld.cr1.nostretch = cm_object_get_child_by_name(state->u.f4.reg.cr1, "NOSTRETCH"); + state->u.f4.fld.cr1.start = cm_object_get_child_by_name(state->u.f4.reg.cr1, "START"); + state->u.f4.fld.cr1.stop = cm_object_get_child_by_name(state->u.f4.reg.cr1, "STOP"); + state->u.f4.fld.cr1.ack = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ACK"); + state->u.f4.fld.cr1.pos = cm_object_get_child_by_name(state->u.f4.reg.cr1, "POS"); + state->u.f4.fld.cr1.pec = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEC"); + state->u.f4.fld.cr1.alert = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ALERT"); + state->u.f4.fld.cr1.swrst = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SWRST"); + + // CR2 bitfields. + state->u.f4.fld.cr2.freq = cm_object_get_child_by_name(state->u.f4.reg.cr2, "FREQ"); + state->u.f4.fld.cr2.iterren = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITERREN"); + state->u.f4.fld.cr2.itevten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITEVTEN"); + state->u.f4.fld.cr2.itbufen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITBUFEN"); + state->u.f4.fld.cr2.dmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DMAEN"); + state->u.f4.fld.cr2.last = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LAST"); + + // OAR1 bitfields. + state->u.f4.fld.oar1.add0 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD0"); + state->u.f4.fld.oar1.add7 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD7"); + state->u.f4.fld.oar1.add10 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD10"); + state->u.f4.fld.oar1.addmode = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADDMODE"); + + // OAR2 bitfields. + state->u.f4.fld.oar2.endual = cm_object_get_child_by_name(state->u.f4.reg.oar2, "ENDUAL"); + state->u.f4.fld.oar2.add2 = cm_object_get_child_by_name(state->u.f4.reg.oar2, "ADD2"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // SR1 bitfields. + state->u.f4.fld.sr1.sb = cm_object_get_child_by_name(state->u.f4.reg.sr1, "SB"); + state->u.f4.fld.sr1.addr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ADDR"); + state->u.f4.fld.sr1.btf = cm_object_get_child_by_name(state->u.f4.reg.sr1, "BTF"); + state->u.f4.fld.sr1.add10 = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ADD10"); + state->u.f4.fld.sr1.stopf = cm_object_get_child_by_name(state->u.f4.reg.sr1, "STOPF"); + state->u.f4.fld.sr1.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr1, "RxNE"); + state->u.f4.fld.sr1.txe = cm_object_get_child_by_name(state->u.f4.reg.sr1, "TxE"); + state->u.f4.fld.sr1.berr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "BERR"); + state->u.f4.fld.sr1.arlo = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ARLO"); + state->u.f4.fld.sr1.af = cm_object_get_child_by_name(state->u.f4.reg.sr1, "AF"); + state->u.f4.fld.sr1.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "OVR"); + state->u.f4.fld.sr1.pecerr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "PECERR"); + state->u.f4.fld.sr1.timeout = cm_object_get_child_by_name(state->u.f4.reg.sr1, "TIMEOUT"); + state->u.f4.fld.sr1.smbalert = cm_object_get_child_by_name(state->u.f4.reg.sr1, "SMBALERT"); + + // SR2 bitfields. + state->u.f4.fld.sr2.msl = cm_object_get_child_by_name(state->u.f4.reg.sr2, "MSL"); + state->u.f4.fld.sr2.busy = cm_object_get_child_by_name(state->u.f4.reg.sr2, "BUSY"); + state->u.f4.fld.sr2.tra = cm_object_get_child_by_name(state->u.f4.reg.sr2, "TRA"); + state->u.f4.fld.sr2.gencall = cm_object_get_child_by_name(state->u.f4.reg.sr2, "GENCALL"); + state->u.f4.fld.sr2.smbdefault = cm_object_get_child_by_name(state->u.f4.reg.sr2, "SMBDEFAULT"); + state->u.f4.fld.sr2.smbhost = cm_object_get_child_by_name(state->u.f4.reg.sr2, "SMBHOST"); + state->u.f4.fld.sr2.dualf = cm_object_get_child_by_name(state->u.f4.reg.sr2, "DUALF"); + state->u.f4.fld.sr2.pec = cm_object_get_child_by_name(state->u.f4.reg.sr2, "PEC"); + + // CCR bitfields. + state->u.f4.fld.ccr.ccr = cm_object_get_child_by_name(state->u.f4.reg.ccr, "CCR"); + state->u.f4.fld.ccr.duty = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DUTY"); + state->u.f4.fld.ccr.f_s = cm_object_get_child_by_name(state->u.f4.reg.ccr, "F_S"); + + // TRISE bitfields. + state->u.f4.fld.trise.trise = cm_object_get_child_by_name(state->u.f4.reg.trise, "TRISE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2c_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2c_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2c_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2c_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2c_is_enabled(Object *obj) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2c_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2CState *state = STM32_I2C_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_I2C_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2c_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2C)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2CState *state = STM32_I2C_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2C"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_i2c_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2c_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_i2c_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2c_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_i2c_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2C%dEN", + 1 + state->port_index - STM32_PORT_I2C1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2c_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2C); +} + +static void stm32_i2c_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2c_reset_callback; + dc->realize = stm32_i2c_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2c_is_enabled; +} + +static const TypeInfo stm32_i2c_type_info = { + .name = TYPE_STM32_I2C, + .parent = TYPE_STM32_I2C_PARENT, + .instance_init = stm32_i2c_instance_init_callback, + .instance_size = sizeof(STM32I2CState), + .class_init = stm32_i2c_class_init_callback, + .class_size = sizeof(STM32I2CClass) }; + +static void stm32_i2c_register_types(void) +{ + type_register_static(&stm32_i2c_type_info); +} + +type_init(stm32_i2c_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/i2c3.h b/gnu-mcu-eclipse/devices/support/STM32F40x/i2c3.h new file mode 100644 index 0000000000..a94d1f8319 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/i2c3.h @@ -0,0 +1,209 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2C_H_ +#define STM32_I2C_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2C DEVICE_PATH_STM32 "I2C" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_I2C1, + STM32_PORT_I2C2, + STM32_PORT_I2C3, + STM32_PORT_I2C_UNDEFINED = 0xFF, +} stm32_i2c_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2C TYPE_STM32_PREFIX "i2c" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2C_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2CParentClass; +typedef PeripheralState STM32I2CParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2CClass, (obj), TYPE_STM32_I2C) +#define STM32_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2CClass, (klass), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentClass parent_class; + // public: + + // None, so far. +} STM32I2CClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2C_STATE(obj) \ + OBJECT_CHECK(STM32I2CState, (obj), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_i2c_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 I2C (Inter-integrated circuit) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *oar1; // 0x8 (Own address register 1) + Object *oar2; // 0xC (Own address register 2) + Object *dr; // 0x10 (Data register) + Object *sr1; // 0x14 (Status register 1) + Object *sr2; // 0x18 (Status register 2) + Object *ccr; // 0x1C (Clock control register) + Object *trise; // 0x20 (TRISE register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *pe; // [0:0] Peripheral enable + Object *smbus; // [1:1] SMBus mode + Object *smbtype; // [3:3] SMBus type + Object *enarp; // [4:4] ARP enable + Object *enpec; // [5:5] PEC enable + Object *engc; // [6:6] General call enable + Object *nostretch; // [7:7] Clock stretching disable (Slave mode) + Object *start; // [8:8] Start generation + Object *stop; // [9:9] Stop generation + Object *ack; // [10:10] Acknowledge enable + Object *pos; // [11:11] Acknowledge/PEC Position (for data reception) + Object *pec; // [12:12] Packet error checking + Object *alert; // [13:13] SMBus alert + Object *swrst; // [15:15] Software reset + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *freq; // [0:5] Peripheral clock frequency + Object *iterren; // [8:8] Error interrupt enable + Object *itevten; // [9:9] Event interrupt enable + Object *itbufen; // [10:10] Buffer interrupt enable + Object *dmaen; // [11:11] DMA requests enable + Object *last; // [12:12] DMA last transfer + } cr2; + + // OAR1 (Own address register 1) bitfields. + struct { + Object *add0; // [0:0] Interface address + Object *add7; // [1:7] Interface address + Object *add10; // [8:9] Interface address + Object *addmode; // [15:15] Addressing mode (slave mode) + } oar1; + + // OAR2 (Own address register 2) bitfields. + struct { + Object *endual; // [0:0] Dual addressing mode enable + Object *add2; // [1:7] Interface address + } oar2; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:7] 8-bit data register + } dr; + + // SR1 (Status register 1) bitfields. + struct { + Object *sb; // [0:0] Start bit (Master mode) + Object *addr; // [1:1] Address sent (master mode)/matched (slave mode) + Object *btf; // [2:2] Byte transfer finished + Object *add10; // [3:3] 10-bit header sent (Master mode) + Object *stopf; // [4:4] Stop detection (slave mode) + Object *rxne; // [6:6] Data register not empty (receivers) + Object *txe; // [7:7] Data register empty (transmitters) + Object *berr; // [8:8] Bus error + Object *arlo; // [9:9] Arbitration lost (master mode) + Object *af; // [10:10] Acknowledge failure + Object *ovr; // [11:11] Overrun/Underrun + Object *pecerr; // [12:12] PEC Error in reception + Object *timeout; // [14:14] Timeout or Tlow error + Object *smbalert; // [15:15] SMBus alert + } sr1; + + // SR2 (Status register 2) bitfields. + struct { + Object *msl; // [0:0] Master/slave + Object *busy; // [1:1] Bus busy + Object *tra; // [2:2] Transmitter/receiver + Object *gencall; // [4:4] General call address (Slave mode) + Object *smbdefault; // [5:5] SMBus device default address (Slave mode) + Object *smbhost; // [6:6] SMBus host header (Slave mode) + Object *dualf; // [7:7] Dual flag (Slave mode) + Object *pec; // [8:15] Acket error checking register + } sr2; + + // CCR (Clock control register) bitfields. + struct { + Object *ccr; // [0:11] Clock control register in Fast/Standard mode (Master mode) + Object *duty; // [14:14] Fast mode duty cycle + Object *f_s; // [15:15] I2C master mode selection + } ccr; + + // TRISE (TRISE register) bitfields. + struct { + Object *trise; // [0:5] Maximum rise time in Fast/Standard mode (Master mode) + } trise; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2CState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2C_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/iwdg.c b/gnu-mcu-eclipse/devices/support/STM32F40x/iwdg.c new file mode 100644 index 0000000000..f5a1c56157 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/iwdg.c @@ -0,0 +1,251 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_iwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.kr = cm_object_get_child_by_name(obj, "KR"); + state->u.f4.reg.pr = cm_object_get_child_by_name(obj, "PR"); + state->u.f4.reg.rlr = cm_object_get_child_by_name(obj, "RLR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // KR bitfields. + state->u.f4.fld.kr.key = cm_object_get_child_by_name(state->u.f4.reg.kr, "KEY"); + + // PR bitfields. + state->u.f4.fld.pr.pr = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR"); + + // RLR bitfields. + state->u.f4.fld.rlr.rl = cm_object_get_child_by_name(state->u.f4.reg.rlr, "RL"); + + // SR bitfields. + state->u.f4.fld.sr.pvu = cm_object_get_child_by_name(state->u.f4.reg.sr, "PVU"); + state->u.f4.fld.sr.rvu = cm_object_get_child_by_name(state->u.f4.reg.sr, "RVU"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_iwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_iwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_iwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_iwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_iwdg_is_enabled(Object *obj) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_iwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_iwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_IWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32IWDGState *state = STM32_IWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "IWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_iwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_iwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_iwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_iwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_iwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/IWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_iwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_IWDG); +} + +static void stm32_iwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_iwdg_reset_callback; + dc->realize = stm32_iwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_iwdg_is_enabled; +} + +static const TypeInfo stm32_iwdg_type_info = { + .name = TYPE_STM32_IWDG, + .parent = TYPE_STM32_IWDG_PARENT, + .instance_init = stm32_iwdg_instance_init_callback, + .instance_size = sizeof(STM32IWDGState), + .class_init = stm32_iwdg_class_init_callback, + .class_size = sizeof(STM32IWDGClass) }; + +static void stm32_iwdg_register_types(void) +{ + type_register_static(&stm32_iwdg_type_info); +} + +type_init(stm32_iwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/iwdg.h b/gnu-mcu-eclipse/devices/support/STM32F40x/iwdg.h new file mode 100644 index 0000000000..76247aafbe --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/iwdg.h @@ -0,0 +1,124 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_IWDG_H_ +#define STM32_IWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_IWDG DEVICE_PATH_STM32 "IWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_IWDG TYPE_STM32_PREFIX "iwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_IWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32IWDGParentClass; +typedef PeripheralState STM32IWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_IWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32IWDGClass, (obj), TYPE_STM32_IWDG) +#define STM32_IWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32IWDGClass, (klass), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentClass parent_class; + // public: + + // None, so far. +} STM32IWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_IWDG_STATE(obj) \ + OBJECT_CHECK(STM32IWDGState, (obj), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 IWDG (Independent watchdog) registers. + struct { + Object *kr; // 0x0 (Key register) + Object *pr; // 0x4 (Prescaler register) + Object *rlr; // 0x8 (Reload register) + Object *sr; // 0xC (Status register) + } reg; + + struct { + + // KR (Key register) bitfields. + struct { + Object *key; // [0:15] Key value (write only, read 0000h) + } kr; + + // PR (Prescaler register) bitfields. + struct { + Object *pr; // [0:2] Prescaler divider + } pr; + + // RLR (Reload register) bitfields. + struct { + Object *rl; // [0:11] Watchdog counter reload value + } rlr; + + // SR (Status register) bitfields. + struct { + Object *pvu; // [0:0] Watchdog prescaler value update + Object *rvu; // [1:1] Watchdog counter reload value update + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32IWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_IWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_device.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_device.c new file mode 100644 index 0000000000..354c073a5c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_device.c @@ -0,0 +1,552 @@ +/* + * STM32 - OTG_FS_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_fs_device_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_dcfg = cm_object_get_child_by_name(obj, "FS_DCFG"); + state->u.f4.reg.fs_dctl = cm_object_get_child_by_name(obj, "FS_DCTL"); + state->u.f4.reg.fs_dsts = cm_object_get_child_by_name(obj, "FS_DSTS"); + state->u.f4.reg.fs_diepmsk = cm_object_get_child_by_name(obj, "FS_DIEPMSK"); + state->u.f4.reg.fs_doepmsk = cm_object_get_child_by_name(obj, "FS_DOEPMSK"); + state->u.f4.reg.fs_daint = cm_object_get_child_by_name(obj, "FS_DAINT"); + state->u.f4.reg.fs_daintmsk = cm_object_get_child_by_name(obj, "FS_DAINTMSK"); + state->u.f4.reg.dvbusdis = cm_object_get_child_by_name(obj, "DVBUSDIS"); + state->u.f4.reg.dvbuspulse = cm_object_get_child_by_name(obj, "DVBUSPULSE"); + state->u.f4.reg.diepempmsk = cm_object_get_child_by_name(obj, "DIEPEMPMSK"); + state->u.f4.reg.fs_diepctl0 = cm_object_get_child_by_name(obj, "FS_DIEPCTL0"); + state->u.f4.reg.diepctl1 = cm_object_get_child_by_name(obj, "DIEPCTL1"); + state->u.f4.reg.diepctl2 = cm_object_get_child_by_name(obj, "DIEPCTL2"); + state->u.f4.reg.diepctl3 = cm_object_get_child_by_name(obj, "DIEPCTL3"); + state->u.f4.reg.doepctl0 = cm_object_get_child_by_name(obj, "DOEPCTL0"); + state->u.f4.reg.doepctl1 = cm_object_get_child_by_name(obj, "DOEPCTL1"); + state->u.f4.reg.doepctl2 = cm_object_get_child_by_name(obj, "DOEPCTL2"); + state->u.f4.reg.doepctl3 = cm_object_get_child_by_name(obj, "DOEPCTL3"); + state->u.f4.reg.diepint0 = cm_object_get_child_by_name(obj, "DIEPINT0"); + state->u.f4.reg.diepint1 = cm_object_get_child_by_name(obj, "DIEPINT1"); + state->u.f4.reg.diepint2 = cm_object_get_child_by_name(obj, "DIEPINT2"); + state->u.f4.reg.diepint3 = cm_object_get_child_by_name(obj, "DIEPINT3"); + state->u.f4.reg.doepint0 = cm_object_get_child_by_name(obj, "DOEPINT0"); + state->u.f4.reg.doepint1 = cm_object_get_child_by_name(obj, "DOEPINT1"); + state->u.f4.reg.doepint2 = cm_object_get_child_by_name(obj, "DOEPINT2"); + state->u.f4.reg.doepint3 = cm_object_get_child_by_name(obj, "DOEPINT3"); + state->u.f4.reg.dieptsiz0 = cm_object_get_child_by_name(obj, "DIEPTSIZ0"); + state->u.f4.reg.doeptsiz0 = cm_object_get_child_by_name(obj, "DOEPTSIZ0"); + state->u.f4.reg.dieptsiz1 = cm_object_get_child_by_name(obj, "DIEPTSIZ1"); + state->u.f4.reg.dieptsiz2 = cm_object_get_child_by_name(obj, "DIEPTSIZ2"); + state->u.f4.reg.dieptsiz3 = cm_object_get_child_by_name(obj, "DIEPTSIZ3"); + state->u.f4.reg.dtxfsts0 = cm_object_get_child_by_name(obj, "DTXFSTS0"); + state->u.f4.reg.dtxfsts1 = cm_object_get_child_by_name(obj, "DTXFSTS1"); + state->u.f4.reg.dtxfsts2 = cm_object_get_child_by_name(obj, "DTXFSTS2"); + state->u.f4.reg.dtxfsts3 = cm_object_get_child_by_name(obj, "DTXFSTS3"); + state->u.f4.reg.doeptsiz1 = cm_object_get_child_by_name(obj, "DOEPTSIZ1"); + state->u.f4.reg.doeptsiz2 = cm_object_get_child_by_name(obj, "DOEPTSIZ2"); + state->u.f4.reg.doeptsiz3 = cm_object_get_child_by_name(obj, "DOEPTSIZ3"); + + + // FS_DCFG bitfields. + state->u.f4.fld.fs_dcfg.dspd = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "DSPD"); + state->u.f4.fld.fs_dcfg.nzlsohsk = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "NZLSOHSK"); + state->u.f4.fld.fs_dcfg.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "DAD"); + state->u.f4.fld.fs_dcfg.pfivl = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "PFIVL"); + + // FS_DCTL bitfields. + state->u.f4.fld.fs_dctl.rwusig = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "RWUSIG"); + state->u.f4.fld.fs_dctl.sdis = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SDIS"); + state->u.f4.fld.fs_dctl.ginsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "GINSTS"); + state->u.f4.fld.fs_dctl.gonsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "GONSTS"); + state->u.f4.fld.fs_dctl.tctl = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "TCTL"); + state->u.f4.fld.fs_dctl.sginak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SGINAK"); + state->u.f4.fld.fs_dctl.cginak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "CGINAK"); + state->u.f4.fld.fs_dctl.sgonak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SGONAK"); + state->u.f4.fld.fs_dctl.cgonak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "CGONAK"); + state->u.f4.fld.fs_dctl.poprgdne = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "POPRGDNE"); + + // FS_DSTS bitfields. + state->u.f4.fld.fs_dsts.suspsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "SUSPSTS"); + state->u.f4.fld.fs_dsts.enumspd = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "ENUMSPD"); + state->u.f4.fld.fs_dsts.eerr = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "EERR"); + state->u.f4.fld.fs_dsts.fnsof = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "FNSOF"); + + // FS_DIEPMSK bitfields. + state->u.f4.fld.fs_diepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "XFRCM"); + state->u.f4.fld.fs_diepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "EPDM"); + state->u.f4.fld.fs_diepmsk.tom = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "TOM"); + state->u.f4.fld.fs_diepmsk.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "ITTXFEMSK"); + state->u.f4.fld.fs_diepmsk.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "INEPNMM"); + state->u.f4.fld.fs_diepmsk.inepnem = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "INEPNEM"); + + // FS_DOEPMSK bitfields. + state->u.f4.fld.fs_doepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "XFRCM"); + state->u.f4.fld.fs_doepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "EPDM"); + state->u.f4.fld.fs_doepmsk.stupm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "STUPM"); + state->u.f4.fld.fs_doepmsk.otepdm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "OTEPDM"); + + // FS_DAINT bitfields. + state->u.f4.fld.fs_daint.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daint, "IEPINT"); + state->u.f4.fld.fs_daint.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daint, "OEPINT"); + + // FS_DAINTMSK bitfields. + state->u.f4.fld.fs_daintmsk.iepm = cm_object_get_child_by_name(state->u.f4.reg.fs_daintmsk, "IEPM"); + state->u.f4.fld.fs_daintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daintmsk, "OEPINT"); + + // DVBUSDIS bitfields. + state->u.f4.fld.dvbusdis.vbusdt = cm_object_get_child_by_name(state->u.f4.reg.dvbusdis, "VBUSDT"); + + // DVBUSPULSE bitfields. + state->u.f4.fld.dvbuspulse.dvbusp = cm_object_get_child_by_name(state->u.f4.reg.dvbuspulse, "DVBUSP"); + + // DIEPEMPMSK bitfields. + state->u.f4.fld.diepempmsk.ineptxfem = cm_object_get_child_by_name(state->u.f4.reg.diepempmsk, "INEPTXFEM"); + + // FS_DIEPCTL0 bitfields. + state->u.f4.fld.fs_diepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "MPSIZ"); + state->u.f4.fld.fs_diepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "USBAEP"); + state->u.f4.fld.fs_diepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "NAKSTS"); + state->u.f4.fld.fs_diepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPTYP"); + state->u.f4.fld.fs_diepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "STALL"); + state->u.f4.fld.fs_diepctl0.txfnum = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "TXFNUM"); + state->u.f4.fld.fs_diepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "CNAK"); + state->u.f4.fld.fs_diepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "SNAK"); + state->u.f4.fld.fs_diepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPDIS"); + state->u.f4.fld.fs_diepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPENA"); + + // DIEPCTL1 bitfields. + state->u.f4.fld.diepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "MPSIZ"); + state->u.f4.fld.diepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "USBAEP"); + state->u.f4.fld.diepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EONUM_DPID"); + state->u.f4.fld.diepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "NAKSTS"); + state->u.f4.fld.diepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPTYP"); + state->u.f4.fld.diepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "Stall"); + state->u.f4.fld.diepctl1.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "TXFNUM"); + state->u.f4.fld.diepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "CNAK"); + state->u.f4.fld.diepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SNAK"); + state->u.f4.fld.diepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl1.soddfrm_sd1pid = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SODDFRM_SD1PID"); + state->u.f4.fld.diepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPDIS"); + state->u.f4.fld.diepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPENA"); + + // DIEPCTL2 bitfields. + state->u.f4.fld.diepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "MPSIZ"); + state->u.f4.fld.diepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "USBAEP"); + state->u.f4.fld.diepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EONUM_DPID"); + state->u.f4.fld.diepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "NAKSTS"); + state->u.f4.fld.diepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPTYP"); + state->u.f4.fld.diepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "Stall"); + state->u.f4.fld.diepctl2.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "TXFNUM"); + state->u.f4.fld.diepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "CNAK"); + state->u.f4.fld.diepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SNAK"); + state->u.f4.fld.diepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SODDFRM"); + state->u.f4.fld.diepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPDIS"); + state->u.f4.fld.diepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPENA"); + + // DIEPCTL3 bitfields. + state->u.f4.fld.diepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "MPSIZ"); + state->u.f4.fld.diepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "USBAEP"); + state->u.f4.fld.diepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EONUM_DPID"); + state->u.f4.fld.diepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "NAKSTS"); + state->u.f4.fld.diepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPTYP"); + state->u.f4.fld.diepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "Stall"); + state->u.f4.fld.diepctl3.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "TXFNUM"); + state->u.f4.fld.diepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "CNAK"); + state->u.f4.fld.diepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SNAK"); + state->u.f4.fld.diepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SODDFRM"); + state->u.f4.fld.diepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPDIS"); + state->u.f4.fld.diepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPENA"); + + // DOEPCTL0 bitfields. + state->u.f4.fld.doepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "MPSIZ"); + state->u.f4.fld.doepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "USBAEP"); + state->u.f4.fld.doepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "NAKSTS"); + state->u.f4.fld.doepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPTYP"); + state->u.f4.fld.doepctl0.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "SNPM"); + state->u.f4.fld.doepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "Stall"); + state->u.f4.fld.doepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "CNAK"); + state->u.f4.fld.doepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "SNAK"); + state->u.f4.fld.doepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPDIS"); + state->u.f4.fld.doepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPENA"); + + // DOEPCTL1 bitfields. + state->u.f4.fld.doepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "MPSIZ"); + state->u.f4.fld.doepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "USBAEP"); + state->u.f4.fld.doepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EONUM_DPID"); + state->u.f4.fld.doepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "NAKSTS"); + state->u.f4.fld.doepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPTYP"); + state->u.f4.fld.doepctl1.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SNPM"); + state->u.f4.fld.doepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "Stall"); + state->u.f4.fld.doepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "CNAK"); + state->u.f4.fld.doepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SNAK"); + state->u.f4.fld.doepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl1.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SODDFRM"); + state->u.f4.fld.doepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPDIS"); + state->u.f4.fld.doepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPENA"); + + // DOEPCTL2 bitfields. + state->u.f4.fld.doepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "MPSIZ"); + state->u.f4.fld.doepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "USBAEP"); + state->u.f4.fld.doepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EONUM_DPID"); + state->u.f4.fld.doepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "NAKSTS"); + state->u.f4.fld.doepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPTYP"); + state->u.f4.fld.doepctl2.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SNPM"); + state->u.f4.fld.doepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "Stall"); + state->u.f4.fld.doepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "CNAK"); + state->u.f4.fld.doepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SNAK"); + state->u.f4.fld.doepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SODDFRM"); + state->u.f4.fld.doepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPDIS"); + state->u.f4.fld.doepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPENA"); + + // DOEPCTL3 bitfields. + state->u.f4.fld.doepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "MPSIZ"); + state->u.f4.fld.doepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "USBAEP"); + state->u.f4.fld.doepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EONUM_DPID"); + state->u.f4.fld.doepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "NAKSTS"); + state->u.f4.fld.doepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPTYP"); + state->u.f4.fld.doepctl3.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SNPM"); + state->u.f4.fld.doepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "Stall"); + state->u.f4.fld.doepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "CNAK"); + state->u.f4.fld.doepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SNAK"); + state->u.f4.fld.doepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SODDFRM"); + state->u.f4.fld.doepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPDIS"); + state->u.f4.fld.doepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPENA"); + + // DIEPINT0 bitfields. + state->u.f4.fld.diepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "XFRC"); + state->u.f4.fld.diepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "EPDISD"); + state->u.f4.fld.diepint0.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "TOC"); + state->u.f4.fld.diepint0.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "ITTXFE"); + state->u.f4.fld.diepint0.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "INEPNE"); + state->u.f4.fld.diepint0.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "TXFE"); + + // DIEPINT1 bitfields. + state->u.f4.fld.diepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "XFRC"); + state->u.f4.fld.diepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "EPDISD"); + state->u.f4.fld.diepint1.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "TOC"); + state->u.f4.fld.diepint1.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "ITTXFE"); + state->u.f4.fld.diepint1.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "INEPNE"); + state->u.f4.fld.diepint1.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "TXFE"); + + // DIEPINT2 bitfields. + state->u.f4.fld.diepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "XFRC"); + state->u.f4.fld.diepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "EPDISD"); + state->u.f4.fld.diepint2.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "TOC"); + state->u.f4.fld.diepint2.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "ITTXFE"); + state->u.f4.fld.diepint2.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "INEPNE"); + state->u.f4.fld.diepint2.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "TXFE"); + + // DIEPINT3 bitfields. + state->u.f4.fld.diepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "XFRC"); + state->u.f4.fld.diepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "EPDISD"); + state->u.f4.fld.diepint3.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "TOC"); + state->u.f4.fld.diepint3.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "ITTXFE"); + state->u.f4.fld.diepint3.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "INEPNE"); + state->u.f4.fld.diepint3.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "TXFE"); + + // DOEPINT0 bitfields. + state->u.f4.fld.doepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "XFRC"); + state->u.f4.fld.doepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "EPDISD"); + state->u.f4.fld.doepint0.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "STUP"); + state->u.f4.fld.doepint0.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "OTEPDIS"); + state->u.f4.fld.doepint0.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "B2BSTUP"); + + // DOEPINT1 bitfields. + state->u.f4.fld.doepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "XFRC"); + state->u.f4.fld.doepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "EPDISD"); + state->u.f4.fld.doepint1.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "STUP"); + state->u.f4.fld.doepint1.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "OTEPDIS"); + state->u.f4.fld.doepint1.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "B2BSTUP"); + + // DOEPINT2 bitfields. + state->u.f4.fld.doepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "XFRC"); + state->u.f4.fld.doepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "EPDISD"); + state->u.f4.fld.doepint2.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "STUP"); + state->u.f4.fld.doepint2.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "OTEPDIS"); + state->u.f4.fld.doepint2.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "B2BSTUP"); + + // DOEPINT3 bitfields. + state->u.f4.fld.doepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "XFRC"); + state->u.f4.fld.doepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "EPDISD"); + state->u.f4.fld.doepint3.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "STUP"); + state->u.f4.fld.doepint3.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "OTEPDIS"); + state->u.f4.fld.doepint3.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "B2BSTUP"); + + // DIEPTSIZ0 bitfields. + state->u.f4.fld.dieptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz0, "XFRSIZ"); + state->u.f4.fld.dieptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz0, "PKTCNT"); + + // DOEPTSIZ0 bitfields. + state->u.f4.fld.doeptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "XFRSIZ"); + state->u.f4.fld.doeptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "PKTCNT"); + state->u.f4.fld.doeptsiz0.stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "STUPCNT"); + + // DIEPTSIZ1 bitfields. + state->u.f4.fld.dieptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "XFRSIZ"); + state->u.f4.fld.dieptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "PKTCNT"); + state->u.f4.fld.dieptsiz1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "MCNT"); + + // DIEPTSIZ2 bitfields. + state->u.f4.fld.dieptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "XFRSIZ"); + state->u.f4.fld.dieptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "PKTCNT"); + state->u.f4.fld.dieptsiz2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "MCNT"); + + // DIEPTSIZ3 bitfields. + state->u.f4.fld.dieptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "XFRSIZ"); + state->u.f4.fld.dieptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "PKTCNT"); + state->u.f4.fld.dieptsiz3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "MCNT"); + + // DTXFSTS0 bitfields. + state->u.f4.fld.dtxfsts0.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts0, "INEPTFSAV"); + + // DTXFSTS1 bitfields. + state->u.f4.fld.dtxfsts1.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts1, "INEPTFSAV"); + + // DTXFSTS2 bitfields. + state->u.f4.fld.dtxfsts2.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts2, "INEPTFSAV"); + + // DTXFSTS3 bitfields. + state->u.f4.fld.dtxfsts3.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts3, "INEPTFSAV"); + + // DOEPTSIZ1 bitfields. + state->u.f4.fld.doeptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "XFRSIZ"); + state->u.f4.fld.doeptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "PKTCNT"); + state->u.f4.fld.doeptsiz1.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "RXDPID_STUPCNT"); + + // DOEPTSIZ2 bitfields. + state->u.f4.fld.doeptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "XFRSIZ"); + state->u.f4.fld.doeptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "PKTCNT"); + state->u.f4.fld.doeptsiz2.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "RXDPID_STUPCNT"); + + // DOEPTSIZ3 bitfields. + state->u.f4.fld.doeptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "XFRSIZ"); + state->u.f4.fld.doeptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "PKTCNT"); + state->u.f4.fld.doeptsiz3.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "RXDPID_STUPCNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_device_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_device_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_device_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_device_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_device_is_enabled(Object *obj) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_device_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_device_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_DEVICE)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_DEVICE"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_fs_device_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_DEVICEEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_device_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_DEVICE); +} + +static void stm32_otg_fs_device_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_device_reset_callback; + dc->realize = stm32_otg_fs_device_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_device_is_enabled; +} + +static const TypeInfo stm32_otg_fs_device_type_info = { + .name = TYPE_STM32_OTG_FS_DEVICE, + .parent = TYPE_STM32_OTG_FS_DEVICE_PARENT, + .instance_init = stm32_otg_fs_device_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_DEVICEState), + .class_init = stm32_otg_fs_device_class_init_callback, + .class_size = sizeof(STM32OTG_FS_DEVICEClass) }; + +static void stm32_otg_fs_device_register_types(void) +{ + type_register_static(&stm32_otg_fs_device_type_info); +} + +type_init(stm32_otg_fs_device_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_device.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_device.h new file mode 100644 index 0000000000..42475e75f6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_device.h @@ -0,0 +1,493 @@ +/* + * STM32 - OTG_FS_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_DEVICE_H_ +#define STM32_OTG_FS_DEVICE_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_DEVICE DEVICE_PATH_STM32 "OTG_FS_DEVICE" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_DEVICE TYPE_STM32_PREFIX "otg_fs_device" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_DEVICE_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_DEVICEParentClass; +typedef PeripheralState STM32OTG_FS_DEVICEParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_DEVICEClass, (obj), TYPE_STM32_OTG_FS_DEVICE) +#define STM32_OTG_FS_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_DEVICEClass, (klass), TYPE_STM32_OTG_FS_DEVICE) + +typedef struct { + // private: + STM32OTG_FS_DEVICEParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_DEVICEClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_DEVICE_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_DEVICEState, (obj), TYPE_STM32_OTG_FS_DEVICE) + +typedef struct { + // private: + STM32OTG_FS_DEVICEParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_DEVICE (USB on the go full speed) registers. + struct { + Object *fs_dcfg; // 0x0 (OTG_FS device configuration register (OTG_FS_DCFG)) + Object *fs_dctl; // 0x4 (OTG_FS device control register (OTG_FS_DCTL)) + Object *fs_dsts; // 0x8 (OTG_FS device status register (OTG_FS_DSTS)) + Object *fs_diepmsk; // 0x10 (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) + Object *fs_doepmsk; // 0x14 (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) + Object *fs_daint; // 0x18 (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) + Object *fs_daintmsk; // 0x1C (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) + Object *dvbusdis; // 0x28 (OTG_FS device VBUS discharge time register) + Object *dvbuspulse; // 0x2C (OTG_FS device VBUS pulsing time register) + Object *diepempmsk; // 0x34 (OTG_FS device IN endpoint FIFO empty interrupt mask register) + Object *fs_diepctl0; // 0x100 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) + Object *diepctl1; // 0x120 (OTG device endpoint-1 control register) + Object *diepctl2; // 0x140 (OTG device endpoint-2 control register) + Object *diepctl3; // 0x160 (OTG device endpoint-3 control register) + Object *doepctl0; // 0x300 (Device endpoint-0 control register) + Object *doepctl1; // 0x320 (Device endpoint-1 control register) + Object *doepctl2; // 0x340 (Device endpoint-2 control register) + Object *doepctl3; // 0x360 (Device endpoint-3 control register) + Object *diepint0; // 0x108 (Device endpoint-x interrupt register) + Object *diepint1; // 0x128 (Device endpoint-1 interrupt register) + Object *diepint2; // 0x148 (Device endpoint-2 interrupt register) + Object *diepint3; // 0x168 (Device endpoint-3 interrupt register) + Object *doepint0; // 0x308 (Device endpoint-0 interrupt register) + Object *doepint1; // 0x328 (Device endpoint-1 interrupt register) + Object *doepint2; // 0x348 (Device endpoint-2 interrupt register) + Object *doepint3; // 0x368 (Device endpoint-3 interrupt register) + Object *dieptsiz0; // 0x110 (Device endpoint-0 transfer size register) + Object *doeptsiz0; // 0x310 (Device OUT endpoint-0 transfer size register) + Object *dieptsiz1; // 0x130 (Device endpoint-1 transfer size register) + Object *dieptsiz2; // 0x150 (Device endpoint-2 transfer size register) + Object *dieptsiz3; // 0x170 (Device endpoint-3 transfer size register) + Object *dtxfsts0; // 0x118 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts1; // 0x138 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts2; // 0x158 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts3; // 0x178 (OTG_FS device IN endpoint transmit FIFO status register) + Object *doeptsiz1; // 0x330 (Device OUT endpoint-1 transfer size register) + Object *doeptsiz2; // 0x350 (Device OUT endpoint-2 transfer size register) + Object *doeptsiz3; // 0x370 (Device OUT endpoint-3 transfer size register) + } reg; + + struct { + + // FS_DCFG (OTG_FS device configuration register (OTG_FS_DCFG)) bitfields. + struct { + Object *dspd; // [0:1] Device speed + Object *nzlsohsk; // [2:2] Non-zero-length status OUT handshake + Object *dad; // [4:10] Device address + Object *pfivl; // [11:12] Periodic frame interval + } fs_dcfg; + + // FS_DCTL (OTG_FS device control register (OTG_FS_DCTL)) bitfields. + struct { + Object *rwusig; // [0:0] Remote wakeup signaling + Object *sdis; // [1:1] Soft disconnect + Object *ginsts; // [2:2] Global IN NAK status + Object *gonsts; // [3:3] Global OUT NAK status + Object *tctl; // [4:6] Test control + Object *sginak; // [7:7] Set global IN NAK + Object *cginak; // [8:8] Clear global IN NAK + Object *sgonak; // [9:9] Set global OUT NAK + Object *cgonak; // [10:10] Clear global OUT NAK + Object *poprgdne; // [11:11] Power-on programming done + } fs_dctl; + + // FS_DSTS (OTG_FS device status register (OTG_FS_DSTS)) bitfields. + struct { + Object *suspsts; // [0:0] Suspend status + Object *enumspd; // [1:2] Enumerated speed + Object *eerr; // [3:3] Erratic error + Object *fnsof; // [8:21] Frame number of the received SOF + } fs_dsts; + + // FS_DIEPMSK (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (Non-isochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + } fs_diepmsk; + + // FS_DOEPMSK (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *stupm; // [3:3] SETUP phase done mask + Object *otepdm; // [4:4] OUT token received when endpoint disabled mask + } fs_doepmsk; + + // FS_DAINT (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) bitfields. + struct { + Object *iepint; // [0:15] IN endpoint interrupt bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daint; + + // FS_DAINTMSK (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) bitfields. + struct { + Object *iepm; // [0:15] IN EP interrupt mask bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daintmsk; + + // DVBUSDIS (OTG_FS device VBUS discharge time register) bitfields. + struct { + Object *vbusdt; // [0:15] Device VBUS discharge time + } dvbusdis; + + // DVBUSPULSE (OTG_FS device VBUS pulsing time register) bitfields. + struct { + Object *dvbusp; // [0:11] Device VBUS pulsing time + } dvbuspulse; + + // DIEPEMPMSK (OTG_FS device IN endpoint FIFO empty interrupt mask register) bitfields. + struct { + Object *ineptxfem; // [0:15] IN EP Tx FIFO empty interrupt mask bits + } diepempmsk; + + // FS_DIEPCTL0 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) bitfields. + struct { + Object *mpsiz; // [0:1] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } fs_diepctl0; + + // DIEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm_sd1pid; // [29:29] SODDFRM/SD1PID + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl1; + + // DIEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl2; + + // DIEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl3; + + // DOEPCTL0 (Device endpoint-0 control register) bitfields. + struct { + Object *mpsiz; // [0:1] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl0; + + // DOEPCTL1 (Device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl1; + + // DOEPCTL2 (Device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl2; + + // DOEPCTL3 (Device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl3; + + // DIEPINT0 (Device endpoint-x interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint0; + + // DIEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint1; + + // DIEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint2; + + // DIEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint3; + + // DOEPINT0 (Device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint0; + + // DOEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint1; + + // DOEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint2; + + // DOEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint3; + + // DIEPTSIZ0 (Device endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:20] Packet count + } dieptsiz0; + + // DOEPTSIZ0 (Device OUT endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:19] Packet count + Object *stupcnt; // [29:30] SETUP packet count + } doeptsiz0; + + // DIEPTSIZ1 (Device endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz1; + + // DIEPTSIZ2 (Device endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz2; + + // DIEPTSIZ3 (Device endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz3; + + // DTXFSTS0 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts0; + + // DTXFSTS1 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts1; + + // DTXFSTS2 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts2; + + // DTXFSTS3 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts3; + + // DOEPTSIZ1 (Device OUT endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz1; + + // DOEPTSIZ2 (Device OUT endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz2; + + // DOEPTSIZ3 (Device OUT endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_DEVICEState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_DEVICE_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_global.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_global.c new file mode 100644 index 0000000000..41c6cf015e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_global.c @@ -0,0 +1,406 @@ +/* + * STM32 - OTG_FS_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_fs_global_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_gotgctl = cm_object_get_child_by_name(obj, "FS_GOTGCTL"); + state->u.f4.reg.fs_gotgint = cm_object_get_child_by_name(obj, "FS_GOTGINT"); + state->u.f4.reg.fs_gahbcfg = cm_object_get_child_by_name(obj, "FS_GAHBCFG"); + state->u.f4.reg.fs_gusbcfg = cm_object_get_child_by_name(obj, "FS_GUSBCFG"); + state->u.f4.reg.fs_grstctl = cm_object_get_child_by_name(obj, "FS_GRSTCTL"); + state->u.f4.reg.fs_gintsts = cm_object_get_child_by_name(obj, "FS_GINTSTS"); + state->u.f4.reg.fs_gintmsk = cm_object_get_child_by_name(obj, "FS_GINTMSK"); + state->u.f4.reg.fs_grxstsr_device = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Device"); + state->u.f4.reg.fs_grxstsr_host = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Host"); + state->u.f4.reg.fs_grxfsiz = cm_object_get_child_by_name(obj, "FS_GRXFSIZ"); + state->u.f4.reg.fs_gnptxfsiz_device = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Device"); + state->u.f4.reg.fs_gnptxfsiz_host = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Host"); + state->u.f4.reg.fs_gnptxsts = cm_object_get_child_by_name(obj, "FS_GNPTXSTS"); + state->u.f4.reg.fs_gccfg = cm_object_get_child_by_name(obj, "FS_GCCFG"); + state->u.f4.reg.fs_cid = cm_object_get_child_by_name(obj, "FS_CID"); + state->u.f4.reg.fs_hptxfsiz = cm_object_get_child_by_name(obj, "FS_HPTXFSIZ"); + state->u.f4.reg.fs_dieptxf1 = cm_object_get_child_by_name(obj, "FS_DIEPTXF1"); + state->u.f4.reg.fs_dieptxf2 = cm_object_get_child_by_name(obj, "FS_DIEPTXF2"); + state->u.f4.reg.fs_dieptxf3 = cm_object_get_child_by_name(obj, "FS_DIEPTXF3"); + + + // FS_GOTGCTL bitfields. + state->u.f4.fld.fs_gotgctl.srqscs = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "SRQSCS"); + state->u.f4.fld.fs_gotgctl.srq = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "SRQ"); + state->u.f4.fld.fs_gotgctl.hngscs = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HNGSCS"); + state->u.f4.fld.fs_gotgctl.hnprq = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HNPRQ"); + state->u.f4.fld.fs_gotgctl.hshnpen = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HSHNPEN"); + state->u.f4.fld.fs_gotgctl.dhnpen = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "DHNPEN"); + state->u.f4.fld.fs_gotgctl.cidsts = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "CIDSTS"); + state->u.f4.fld.fs_gotgctl.dbct = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "DBCT"); + state->u.f4.fld.fs_gotgctl.asvld = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "ASVLD"); + state->u.f4.fld.fs_gotgctl.bsvld = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "BSVLD"); + + // FS_GOTGINT bitfields. + state->u.f4.fld.fs_gotgint.sedet = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "SEDET"); + state->u.f4.fld.fs_gotgint.srsschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "SRSSCHG"); + state->u.f4.fld.fs_gotgint.hnsschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "HNSSCHG"); + state->u.f4.fld.fs_gotgint.hngdet = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "HNGDET"); + state->u.f4.fld.fs_gotgint.adtochg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "ADTOCHG"); + state->u.f4.fld.fs_gotgint.dbcdne = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "DBCDNE"); + + // FS_GAHBCFG bitfields. + state->u.f4.fld.fs_gahbcfg.gint = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "GINT"); + state->u.f4.fld.fs_gahbcfg.txfelvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "TXFELVL"); + state->u.f4.fld.fs_gahbcfg.ptxfelvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "PTXFELVL"); + + // FS_GUSBCFG bitfields. + state->u.f4.fld.fs_gusbcfg.tocal = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "TOCAL"); + state->u.f4.fld.fs_gusbcfg.physel = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "PHYSEL"); + state->u.f4.fld.fs_gusbcfg.srpcap = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "SRPCAP"); + state->u.f4.fld.fs_gusbcfg.hnpcap = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "HNPCAP"); + state->u.f4.fld.fs_gusbcfg.trdt = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "TRDT"); + state->u.f4.fld.fs_gusbcfg.fhmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "FHMOD"); + state->u.f4.fld.fs_gusbcfg.fdmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "FDMOD"); + state->u.f4.fld.fs_gusbcfg.ctxpkt = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "CTXPKT"); + + // FS_GRSTCTL bitfields. + state->u.f4.fld.fs_grstctl.csrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "CSRST"); + state->u.f4.fld.fs_grstctl.hsrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "HSRST"); + state->u.f4.fld.fs_grstctl.fcrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "FCRST"); + state->u.f4.fld.fs_grstctl.rxfflsh = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "RXFFLSH"); + state->u.f4.fld.fs_grstctl.txfflsh = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "TXFFLSH"); + state->u.f4.fld.fs_grstctl.txfnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "TXFNUM"); + state->u.f4.fld.fs_grstctl.ahbidl = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "AHBIDL"); + + // FS_GINTSTS bitfields. + state->u.f4.fld.fs_gintsts.cmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "CMOD"); + state->u.f4.fld.fs_gintsts.mmis = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "MMIS"); + state->u.f4.fld.fs_gintsts.otgint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "OTGINT"); + state->u.f4.fld.fs_gintsts.sof = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "SOF"); + state->u.f4.fld.fs_gintsts.rxflvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "RXFLVL"); + state->u.f4.fld.fs_gintsts.nptxfe = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "NPTXFE"); + state->u.f4.fld.fs_gintsts.ginakeff = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "GINAKEFF"); + state->u.f4.fld.fs_gintsts.goutnakeff = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "GOUTNAKEFF"); + state->u.f4.fld.fs_gintsts.esusp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ESUSP"); + state->u.f4.fld.fs_gintsts.usbsusp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "USBSUSP"); + state->u.f4.fld.fs_gintsts.usbrst = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "USBRST"); + state->u.f4.fld.fs_gintsts.enumdne = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ENUMDNE"); + state->u.f4.fld.fs_gintsts.isoodrp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ISOODRP"); + state->u.f4.fld.fs_gintsts.eopf = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "EOPF"); + state->u.f4.fld.fs_gintsts.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IEPINT"); + state->u.f4.fld.fs_gintsts.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "OEPINT"); + state->u.f4.fld.fs_gintsts.iisoixfr = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IISOIXFR"); + state->u.f4.fld.fs_gintsts.ipxfr_incompisoout = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IPXFR_INCOMPISOOUT"); + state->u.f4.fld.fs_gintsts.hprtint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "HPRTINT"); + state->u.f4.fld.fs_gintsts.hcint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "HCINT"); + state->u.f4.fld.fs_gintsts.ptxfe = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "PTXFE"); + state->u.f4.fld.fs_gintsts.cidschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "CIDSCHG"); + state->u.f4.fld.fs_gintsts.discint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "DISCINT"); + state->u.f4.fld.fs_gintsts.srqint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "SRQINT"); + state->u.f4.fld.fs_gintsts.wkupint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "WKUPINT"); + + // FS_GINTMSK bitfields. + state->u.f4.fld.fs_gintmsk.mmism = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "MMISM"); + state->u.f4.fld.fs_gintmsk.otgint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "OTGINT"); + state->u.f4.fld.fs_gintmsk.sofm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "SOFM"); + state->u.f4.fld.fs_gintmsk.rxflvlm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "RXFLVLM"); + state->u.f4.fld.fs_gintmsk.nptxfem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "NPTXFEM"); + state->u.f4.fld.fs_gintmsk.ginakeffm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "GINAKEFFM"); + state->u.f4.fld.fs_gintmsk.gonakeffm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "GONAKEFFM"); + state->u.f4.fld.fs_gintmsk.esuspm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ESUSPM"); + state->u.f4.fld.fs_gintmsk.usbsuspm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "USBSUSPM"); + state->u.f4.fld.fs_gintmsk.usbrst = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "USBRST"); + state->u.f4.fld.fs_gintmsk.enumdnem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ENUMDNEM"); + state->u.f4.fld.fs_gintmsk.isoodrpm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ISOODRPM"); + state->u.f4.fld.fs_gintmsk.eopfm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "EOPFM"); + state->u.f4.fld.fs_gintmsk.epmism = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "EPMISM"); + state->u.f4.fld.fs_gintmsk.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IEPINT"); + state->u.f4.fld.fs_gintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "OEPINT"); + state->u.f4.fld.fs_gintmsk.iisoixfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IISOIXFRM"); + state->u.f4.fld.fs_gintmsk.ipxfrm_iisooxfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IPXFRM_IISOOXFRM"); + state->u.f4.fld.fs_gintmsk.prtim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "PRTIM"); + state->u.f4.fld.fs_gintmsk.hcim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "HCIM"); + state->u.f4.fld.fs_gintmsk.ptxfem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "PTXFEM"); + state->u.f4.fld.fs_gintmsk.cidschgm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "CIDSCHGM"); + state->u.f4.fld.fs_gintmsk.discint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "DISCINT"); + state->u.f4.fld.fs_gintmsk.srqim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "SRQIM"); + state->u.f4.fld.fs_gintmsk.wuim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "WUIM"); + + // FS_GRXSTSR_Device bitfields. + state->u.f4.fld.fs_grxstsr_device.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "EPNUM"); + state->u.f4.fld.fs_grxstsr_device.bcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "BCNT"); + state->u.f4.fld.fs_grxstsr_device.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "DPID"); + state->u.f4.fld.fs_grxstsr_device.pktsts = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "PKTSTS"); + state->u.f4.fld.fs_grxstsr_device.frmnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "FRMNUM"); + + // FS_GRXSTSR_Host bitfields. + state->u.f4.fld.fs_grxstsr_host.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "EPNUM"); + state->u.f4.fld.fs_grxstsr_host.bcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "BCNT"); + state->u.f4.fld.fs_grxstsr_host.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "DPID"); + state->u.f4.fld.fs_grxstsr_host.pktsts = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "PKTSTS"); + state->u.f4.fld.fs_grxstsr_host.frmnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "FRMNUM"); + + // FS_GRXFSIZ bitfields. + state->u.f4.fld.fs_grxfsiz.rxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_grxfsiz, "RXFD"); + + // FS_GNPTXFSIZ_Device bitfields. + state->u.f4.fld.fs_gnptxfsiz_device.tx0fsa = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_device, "TX0FSA"); + state->u.f4.fld.fs_gnptxfsiz_device.tx0fd = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_device, "TX0FD"); + + // FS_GNPTXFSIZ_Host bitfields. + state->u.f4.fld.fs_gnptxfsiz_host.nptxfsa = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_host, "NPTXFSA"); + state->u.f4.fld.fs_gnptxfsiz_host.nptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_host, "NPTXFD"); + + // FS_GNPTXSTS bitfields. + state->u.f4.fld.fs_gnptxsts.nptxfsav = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTXFSAV"); + state->u.f4.fld.fs_gnptxsts.nptqxsav = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTQXSAV"); + state->u.f4.fld.fs_gnptxsts.nptxqtop = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTXQTOP"); + + // FS_GCCFG bitfields. + state->u.f4.fld.fs_gccfg.pwrdwn = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "PWRDWN"); + state->u.f4.fld.fs_gccfg.vbusasen = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "VBUSASEN"); + state->u.f4.fld.fs_gccfg.vbusbsen = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "VBUSBSEN"); + state->u.f4.fld.fs_gccfg.sofouten = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "SOFOUTEN"); + + // FS_CID bitfields. + state->u.f4.fld.fs_cid.product_id = cm_object_get_child_by_name(state->u.f4.reg.fs_cid, "PRODUCT_ID"); + + // FS_HPTXFSIZ bitfields. + state->u.f4.fld.fs_hptxfsiz.ptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxfsiz, "PTXSA"); + state->u.f4.fld.fs_hptxfsiz.ptxfsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxfsiz, "PTXFSIZ"); + + // FS_DIEPTXF1 bitfields. + state->u.f4.fld.fs_dieptxf1.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf1, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf1.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf1, "INEPTXFD"); + + // FS_DIEPTXF2 bitfields. + state->u.f4.fld.fs_dieptxf2.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf2, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf2.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf2, "INEPTXFD"); + + // FS_DIEPTXF3 bitfields. + state->u.f4.fld.fs_dieptxf3.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf3, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf3.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf3, "INEPTXFD"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_global_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_global_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_global_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_global_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_global_is_enabled(Object *obj) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_global_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_global_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_GLOBAL)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_GLOBAL"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_fs_global_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_GLOBALEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_global_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_GLOBAL); +} + +static void stm32_otg_fs_global_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_global_reset_callback; + dc->realize = stm32_otg_fs_global_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_global_is_enabled; +} + +static const TypeInfo stm32_otg_fs_global_type_info = { + .name = TYPE_STM32_OTG_FS_GLOBAL, + .parent = TYPE_STM32_OTG_FS_GLOBAL_PARENT, + .instance_init = stm32_otg_fs_global_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_GLOBALState), + .class_init = stm32_otg_fs_global_class_init_callback, + .class_size = sizeof(STM32OTG_FS_GLOBALClass) }; + +static void stm32_otg_fs_global_register_types(void) +{ + type_register_static(&stm32_otg_fs_global_type_info); +} + +type_init(stm32_otg_fs_global_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_global.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_global.h new file mode 100644 index 0000000000..5dabd26c69 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_global.h @@ -0,0 +1,309 @@ +/* + * STM32 - OTG_FS_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_GLOBAL_H_ +#define STM32_OTG_FS_GLOBAL_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_GLOBAL DEVICE_PATH_STM32 "OTG_FS_GLOBAL" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_GLOBAL TYPE_STM32_PREFIX "otg_fs_global" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_GLOBAL_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_GLOBALParentClass; +typedef PeripheralState STM32OTG_FS_GLOBALParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_GLOBAL_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_GLOBALClass, (obj), TYPE_STM32_OTG_FS_GLOBAL) +#define STM32_OTG_FS_GLOBAL_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_GLOBALClass, (klass), TYPE_STM32_OTG_FS_GLOBAL) + +typedef struct { + // private: + STM32OTG_FS_GLOBALParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_GLOBALClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_GLOBAL_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_GLOBALState, (obj), TYPE_STM32_OTG_FS_GLOBAL) + +typedef struct { + // private: + STM32OTG_FS_GLOBALParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_GLOBAL (USB on the go full speed) registers. + struct { + Object *fs_gotgctl; // 0x0 (OTG_FS control and status register (OTG_FS_GOTGCTL)) + Object *fs_gotgint; // 0x4 (OTG_FS interrupt register (OTG_FS_GOTGINT)) + Object *fs_gahbcfg; // 0x8 (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) + Object *fs_gusbcfg; // 0xC (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) + Object *fs_grstctl; // 0x10 (OTG_FS reset register (OTG_FS_GRSTCTL)) + Object *fs_gintsts; // 0x14 (OTG_FS core interrupt register (OTG_FS_GINTSTS)) + Object *fs_gintmsk; // 0x18 (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) + Object *fs_grxstsr_device; // 0x1C (OTG_FS Receive status debug read(Device mode)) + Object *fs_grxstsr_host; // 0x1C (OTG_FS Receive status debug read(Host mode)) + Object *fs_grxfsiz; // 0x24 (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) + Object *fs_gnptxfsiz_device; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Device mode)) + Object *fs_gnptxfsiz_host; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Host mode)) + Object *fs_gnptxsts; // 0x2C (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) + Object *fs_gccfg; // 0x38 (OTG_FS general core configuration register (OTG_FS_GCCFG)) + Object *fs_cid; // 0x3C (Core ID register) + Object *fs_hptxfsiz; // 0x100 (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) + Object *fs_dieptxf1; // 0x104 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) + Object *fs_dieptxf2; // 0x108 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) + Object *fs_dieptxf3; // 0x10C (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) + } reg; + + struct { + + // FS_GOTGCTL (OTG_FS control and status register (OTG_FS_GOTGCTL)) bitfields. + struct { + Object *srqscs; // [0:0] Session request success + Object *srq; // [1:1] Session request + Object *hngscs; // [8:8] Host negotiation success + Object *hnprq; // [9:9] HNP request + Object *hshnpen; // [10:10] Host set HNP enable + Object *dhnpen; // [11:11] Device HNP enabled + Object *cidsts; // [16:16] Connector ID status + Object *dbct; // [17:17] Long/short debounce time + Object *asvld; // [18:18] A-session valid + Object *bsvld; // [19:19] B-session valid + } fs_gotgctl; + + // FS_GOTGINT (OTG_FS interrupt register (OTG_FS_GOTGINT)) bitfields. + struct { + Object *sedet; // [2:2] Session end detected + Object *srsschg; // [8:8] Session request success status change + Object *hnsschg; // [9:9] Host negotiation success status change + Object *hngdet; // [17:17] Host negotiation detected + Object *adtochg; // [18:18] A-device timeout change + Object *dbcdne; // [19:19] Debounce done + } fs_gotgint; + + // FS_GAHBCFG (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) bitfields. + struct { + Object *gint; // [0:0] Global interrupt mask + Object *txfelvl; // [7:7] TxFIFO empty level + Object *ptxfelvl; // [8:8] Periodic TxFIFO empty level + } fs_gahbcfg; + + // FS_GUSBCFG (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) bitfields. + struct { + Object *tocal; // [0:2] FS timeout calibration + Object *physel; // [6:6] Full Speed serial transceiver select + Object *srpcap; // [8:8] SRP-capable + Object *hnpcap; // [9:9] HNP-capable + Object *trdt; // [10:13] USB turnaround time + Object *fhmod; // [29:29] Force host mode + Object *fdmod; // [30:30] Force device mode + Object *ctxpkt; // [31:31] Corrupt Tx packet + } fs_gusbcfg; + + // FS_GRSTCTL (OTG_FS reset register (OTG_FS_GRSTCTL)) bitfields. + struct { + Object *csrst; // [0:0] Core soft reset + Object *hsrst; // [1:1] HCLK soft reset + Object *fcrst; // [2:2] Host frame counter reset + Object *rxfflsh; // [4:4] RxFIFO flush + Object *txfflsh; // [5:5] TxFIFO flush + Object *txfnum; // [6:10] TxFIFO number + Object *ahbidl; // [31:31] AHB master idle + } fs_grstctl; + + // FS_GINTSTS (OTG_FS core interrupt register (OTG_FS_GINTSTS)) bitfields. + struct { + Object *cmod; // [0:0] Current mode of operation + Object *mmis; // [1:1] Mode mismatch interrupt + Object *otgint; // [2:2] OTG interrupt + Object *sof; // [3:3] Start of frame + Object *rxflvl; // [4:4] RxFIFO non-empty + Object *nptxfe; // [5:5] Non-periodic TxFIFO empty + Object *ginakeff; // [6:6] Global IN non-periodic NAK effective + Object *goutnakeff; // [7:7] Global OUT NAK effective + Object *esusp; // [10:10] Early suspend + Object *usbsusp; // [11:11] USB suspend + Object *usbrst; // [12:12] USB reset + Object *enumdne; // [13:13] Enumeration done + Object *isoodrp; // [14:14] Isochronous OUT packet dropped interrupt + Object *eopf; // [15:15] End of periodic frame interrupt + Object *iepint; // [18:18] IN endpoint interrupt + Object *oepint; // [19:19] OUT endpoint interrupt + Object *iisoixfr; // [20:20] Incomplete isochronous IN transfer + Object *ipxfr_incompisoout; // [21:21] Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + Object *hprtint; // [24:24] Host port interrupt + Object *hcint; // [25:25] Host channels interrupt + Object *ptxfe; // [26:26] Periodic TxFIFO empty + Object *cidschg; // [28:28] Connector ID status change + Object *discint; // [29:29] Disconnect detected interrupt + Object *srqint; // [30:30] Session request/new session detected interrupt + Object *wkupint; // [31:31] Resume/remote wakeup detected interrupt + } fs_gintsts; + + // FS_GINTMSK (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) bitfields. + struct { + Object *mmism; // [1:1] Mode mismatch interrupt mask + Object *otgint; // [2:2] OTG interrupt mask + Object *sofm; // [3:3] Start of frame mask + Object *rxflvlm; // [4:4] Receive FIFO non-empty mask + Object *nptxfem; // [5:5] Non-periodic TxFIFO empty mask + Object *ginakeffm; // [6:6] Global non-periodic IN NAK effective mask + Object *gonakeffm; // [7:7] Global OUT NAK effective mask + Object *esuspm; // [10:10] Early suspend mask + Object *usbsuspm; // [11:11] USB suspend mask + Object *usbrst; // [12:12] USB reset mask + Object *enumdnem; // [13:13] Enumeration done mask + Object *isoodrpm; // [14:14] Isochronous OUT packet dropped interrupt mask + Object *eopfm; // [15:15] End of periodic frame interrupt mask + Object *epmism; // [17:17] Endpoint mismatch interrupt mask + Object *iepint; // [18:18] IN endpoints interrupt mask + Object *oepint; // [19:19] OUT endpoints interrupt mask + Object *iisoixfrm; // [20:20] Incomplete isochronous IN transfer mask + Object *ipxfrm_iisooxfrm; // [21:21] Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + Object *prtim; // [24:24] Host port interrupt mask + Object *hcim; // [25:25] Host channels interrupt mask + Object *ptxfem; // [26:26] Periodic TxFIFO empty mask + Object *cidschgm; // [28:28] Connector ID status change mask + Object *discint; // [29:29] Disconnect detected interrupt mask + Object *srqim; // [30:30] Session request/new session detected interrupt mask + Object *wuim; // [31:31] Resume/remote wakeup detected interrupt mask + } fs_gintmsk; + + // FS_GRXSTSR_Device (OTG_FS Receive status debug read(Device mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_device; + + // FS_GRXSTSR_Host (OTG_FS Receive status debug read(Host mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_host; + + // FS_GRXFSIZ (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) bitfields. + struct { + Object *rxfd; // [0:15] RxFIFO depth + } fs_grxfsiz; + + // FS_GNPTXFSIZ_Device (OTG_FS non-periodic transmit FIFO size register (Device mode)) bitfields. + struct { + Object *tx0fsa; // [0:15] Endpoint 0 transmit RAM start address + Object *tx0fd; // [16:31] Endpoint 0 TxFIFO depth + } fs_gnptxfsiz_device; + + // FS_GNPTXFSIZ_Host (OTG_FS non-periodic transmit FIFO size register (Host mode)) bitfields. + struct { + Object *nptxfsa; // [0:15] Non-periodic transmit RAM start address + Object *nptxfd; // [16:31] Non-periodic TxFIFO depth + } fs_gnptxfsiz_host; + + // FS_GNPTXSTS (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) bitfields. + struct { + Object *nptxfsav; // [0:15] Non-periodic TxFIFO space available + Object *nptqxsav; // [16:23] Non-periodic transmit request queue space available + Object *nptxqtop; // [24:30] Top of the non-periodic transmit request queue + } fs_gnptxsts; + + // FS_GCCFG (OTG_FS general core configuration register (OTG_FS_GCCFG)) bitfields. + struct { + Object *pwrdwn; // [16:16] Power down + Object *vbusasen; // [18:18] Enable the VBUS sensing device + Object *vbusbsen; // [19:19] Enable the VBUS sensing device + Object *sofouten; // [20:20] SOF output enable + } fs_gccfg; + + // FS_CID (Core ID register) bitfields. + struct { + Object *product_id; // [0:31] Product ID field + } fs_cid; + + // FS_HPTXFSIZ (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) bitfields. + struct { + Object *ptxsa; // [0:15] Host periodic TxFIFO start address + Object *ptxfsiz; // [16:31] Host periodic TxFIFO depth + } fs_hptxfsiz; + + // FS_DIEPTXF1 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO2 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf1; + + // FS_DIEPTXF2 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO3 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf2; + + // FS_DIEPTXF3 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO4 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_GLOBALState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_GLOBAL_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_host.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_host.c new file mode 100644 index 0000000000..5be8c48c2d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_host.c @@ -0,0 +1,630 @@ +/* + * STM32 - OTG_FS_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_fs_host_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_hcfg = cm_object_get_child_by_name(obj, "FS_HCFG"); + state->u.f4.reg.hfir = cm_object_get_child_by_name(obj, "HFIR"); + state->u.f4.reg.fs_hfnum = cm_object_get_child_by_name(obj, "FS_HFNUM"); + state->u.f4.reg.fs_hptxsts = cm_object_get_child_by_name(obj, "FS_HPTXSTS"); + state->u.f4.reg.haint = cm_object_get_child_by_name(obj, "HAINT"); + state->u.f4.reg.haintmsk = cm_object_get_child_by_name(obj, "HAINTMSK"); + state->u.f4.reg.fs_hprt = cm_object_get_child_by_name(obj, "FS_HPRT"); + state->u.f4.reg.fs_hcchar0 = cm_object_get_child_by_name(obj, "FS_HCCHAR0"); + state->u.f4.reg.fs_hcchar1 = cm_object_get_child_by_name(obj, "FS_HCCHAR1"); + state->u.f4.reg.fs_hcchar2 = cm_object_get_child_by_name(obj, "FS_HCCHAR2"); + state->u.f4.reg.fs_hcchar3 = cm_object_get_child_by_name(obj, "FS_HCCHAR3"); + state->u.f4.reg.fs_hcchar4 = cm_object_get_child_by_name(obj, "FS_HCCHAR4"); + state->u.f4.reg.fs_hcchar5 = cm_object_get_child_by_name(obj, "FS_HCCHAR5"); + state->u.f4.reg.fs_hcchar6 = cm_object_get_child_by_name(obj, "FS_HCCHAR6"); + state->u.f4.reg.fs_hcchar7 = cm_object_get_child_by_name(obj, "FS_HCCHAR7"); + state->u.f4.reg.fs_hcint0 = cm_object_get_child_by_name(obj, "FS_HCINT0"); + state->u.f4.reg.fs_hcint1 = cm_object_get_child_by_name(obj, "FS_HCINT1"); + state->u.f4.reg.fs_hcint2 = cm_object_get_child_by_name(obj, "FS_HCINT2"); + state->u.f4.reg.fs_hcint3 = cm_object_get_child_by_name(obj, "FS_HCINT3"); + state->u.f4.reg.fs_hcint4 = cm_object_get_child_by_name(obj, "FS_HCINT4"); + state->u.f4.reg.fs_hcint5 = cm_object_get_child_by_name(obj, "FS_HCINT5"); + state->u.f4.reg.fs_hcint6 = cm_object_get_child_by_name(obj, "FS_HCINT6"); + state->u.f4.reg.fs_hcint7 = cm_object_get_child_by_name(obj, "FS_HCINT7"); + state->u.f4.reg.fs_hcintmsk0 = cm_object_get_child_by_name(obj, "FS_HCINTMSK0"); + state->u.f4.reg.fs_hcintmsk1 = cm_object_get_child_by_name(obj, "FS_HCINTMSK1"); + state->u.f4.reg.fs_hcintmsk2 = cm_object_get_child_by_name(obj, "FS_HCINTMSK2"); + state->u.f4.reg.fs_hcintmsk3 = cm_object_get_child_by_name(obj, "FS_HCINTMSK3"); + state->u.f4.reg.fs_hcintmsk4 = cm_object_get_child_by_name(obj, "FS_HCINTMSK4"); + state->u.f4.reg.fs_hcintmsk5 = cm_object_get_child_by_name(obj, "FS_HCINTMSK5"); + state->u.f4.reg.fs_hcintmsk6 = cm_object_get_child_by_name(obj, "FS_HCINTMSK6"); + state->u.f4.reg.fs_hcintmsk7 = cm_object_get_child_by_name(obj, "FS_HCINTMSK7"); + state->u.f4.reg.fs_hctsiz0 = cm_object_get_child_by_name(obj, "FS_HCTSIZ0"); + state->u.f4.reg.fs_hctsiz1 = cm_object_get_child_by_name(obj, "FS_HCTSIZ1"); + state->u.f4.reg.fs_hctsiz2 = cm_object_get_child_by_name(obj, "FS_HCTSIZ2"); + state->u.f4.reg.fs_hctsiz3 = cm_object_get_child_by_name(obj, "FS_HCTSIZ3"); + state->u.f4.reg.fs_hctsiz4 = cm_object_get_child_by_name(obj, "FS_HCTSIZ4"); + state->u.f4.reg.fs_hctsiz5 = cm_object_get_child_by_name(obj, "FS_HCTSIZ5"); + state->u.f4.reg.fs_hctsiz6 = cm_object_get_child_by_name(obj, "FS_HCTSIZ6"); + state->u.f4.reg.fs_hctsiz7 = cm_object_get_child_by_name(obj, "FS_HCTSIZ7"); + + + // FS_HCFG bitfields. + state->u.f4.fld.fs_hcfg.fslspcs = cm_object_get_child_by_name(state->u.f4.reg.fs_hcfg, "FSLSPCS"); + state->u.f4.fld.fs_hcfg.fslss = cm_object_get_child_by_name(state->u.f4.reg.fs_hcfg, "FSLSS"); + + // HFIR bitfields. + state->u.f4.fld.hfir.frivl = cm_object_get_child_by_name(state->u.f4.reg.hfir, "FRIVL"); + + // FS_HFNUM bitfields. + state->u.f4.fld.fs_hfnum.frnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hfnum, "FRNUM"); + state->u.f4.fld.fs_hfnum.ftrem = cm_object_get_child_by_name(state->u.f4.reg.fs_hfnum, "FTREM"); + + // FS_HPTXSTS bitfields. + state->u.f4.fld.fs_hptxsts.ptxfsavl = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXFSAVL"); + state->u.f4.fld.fs_hptxsts.ptxqsav = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXQSAV"); + state->u.f4.fld.fs_hptxsts.ptxqtop = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXQTOP"); + + // HAINT bitfields. + state->u.f4.fld.haint.haint = cm_object_get_child_by_name(state->u.f4.reg.haint, "HAINT"); + + // HAINTMSK bitfields. + state->u.f4.fld.haintmsk.haintm = cm_object_get_child_by_name(state->u.f4.reg.haintmsk, "HAINTM"); + + // FS_HPRT bitfields. + state->u.f4.fld.fs_hprt.pcsts = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PCSTS"); + state->u.f4.fld.fs_hprt.pcdet = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PCDET"); + state->u.f4.fld.fs_hprt.pena = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PENA"); + state->u.f4.fld.fs_hprt.penchng = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PENCHNG"); + state->u.f4.fld.fs_hprt.poca = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "POCA"); + state->u.f4.fld.fs_hprt.pocchng = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "POCCHNG"); + state->u.f4.fld.fs_hprt.pres = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PRES"); + state->u.f4.fld.fs_hprt.psusp = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PSUSP"); + state->u.f4.fld.fs_hprt.prst = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PRST"); + state->u.f4.fld.fs_hprt.plsts = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PLSTS"); + state->u.f4.fld.fs_hprt.ppwr = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PPWR"); + state->u.f4.fld.fs_hprt.ptctl = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PTCTL"); + state->u.f4.fld.fs_hprt.pspd = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PSPD"); + + // FS_HCCHAR0 bitfields. + state->u.f4.fld.fs_hcchar0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "MPSIZ"); + state->u.f4.fld.fs_hcchar0.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPNUM"); + state->u.f4.fld.fs_hcchar0.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPDIR"); + state->u.f4.fld.fs_hcchar0.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "LSDEV"); + state->u.f4.fld.fs_hcchar0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPTYP"); + state->u.f4.fld.fs_hcchar0.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "MCNT"); + state->u.f4.fld.fs_hcchar0.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "DAD"); + state->u.f4.fld.fs_hcchar0.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "ODDFRM"); + state->u.f4.fld.fs_hcchar0.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "CHDIS"); + state->u.f4.fld.fs_hcchar0.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "CHENA"); + + // FS_HCCHAR1 bitfields. + state->u.f4.fld.fs_hcchar1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "MPSIZ"); + state->u.f4.fld.fs_hcchar1.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPNUM"); + state->u.f4.fld.fs_hcchar1.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPDIR"); + state->u.f4.fld.fs_hcchar1.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "LSDEV"); + state->u.f4.fld.fs_hcchar1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPTYP"); + state->u.f4.fld.fs_hcchar1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "MCNT"); + state->u.f4.fld.fs_hcchar1.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "DAD"); + state->u.f4.fld.fs_hcchar1.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "ODDFRM"); + state->u.f4.fld.fs_hcchar1.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "CHDIS"); + state->u.f4.fld.fs_hcchar1.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "CHENA"); + + // FS_HCCHAR2 bitfields. + state->u.f4.fld.fs_hcchar2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "MPSIZ"); + state->u.f4.fld.fs_hcchar2.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPNUM"); + state->u.f4.fld.fs_hcchar2.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPDIR"); + state->u.f4.fld.fs_hcchar2.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "LSDEV"); + state->u.f4.fld.fs_hcchar2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPTYP"); + state->u.f4.fld.fs_hcchar2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "MCNT"); + state->u.f4.fld.fs_hcchar2.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "DAD"); + state->u.f4.fld.fs_hcchar2.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "ODDFRM"); + state->u.f4.fld.fs_hcchar2.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "CHDIS"); + state->u.f4.fld.fs_hcchar2.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "CHENA"); + + // FS_HCCHAR3 bitfields. + state->u.f4.fld.fs_hcchar3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "MPSIZ"); + state->u.f4.fld.fs_hcchar3.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPNUM"); + state->u.f4.fld.fs_hcchar3.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPDIR"); + state->u.f4.fld.fs_hcchar3.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "LSDEV"); + state->u.f4.fld.fs_hcchar3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPTYP"); + state->u.f4.fld.fs_hcchar3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "MCNT"); + state->u.f4.fld.fs_hcchar3.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "DAD"); + state->u.f4.fld.fs_hcchar3.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "ODDFRM"); + state->u.f4.fld.fs_hcchar3.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "CHDIS"); + state->u.f4.fld.fs_hcchar3.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "CHENA"); + + // FS_HCCHAR4 bitfields. + state->u.f4.fld.fs_hcchar4.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "MPSIZ"); + state->u.f4.fld.fs_hcchar4.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPNUM"); + state->u.f4.fld.fs_hcchar4.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPDIR"); + state->u.f4.fld.fs_hcchar4.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "LSDEV"); + state->u.f4.fld.fs_hcchar4.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPTYP"); + state->u.f4.fld.fs_hcchar4.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "MCNT"); + state->u.f4.fld.fs_hcchar4.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "DAD"); + state->u.f4.fld.fs_hcchar4.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "ODDFRM"); + state->u.f4.fld.fs_hcchar4.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "CHDIS"); + state->u.f4.fld.fs_hcchar4.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "CHENA"); + + // FS_HCCHAR5 bitfields. + state->u.f4.fld.fs_hcchar5.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "MPSIZ"); + state->u.f4.fld.fs_hcchar5.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPNUM"); + state->u.f4.fld.fs_hcchar5.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPDIR"); + state->u.f4.fld.fs_hcchar5.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "LSDEV"); + state->u.f4.fld.fs_hcchar5.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPTYP"); + state->u.f4.fld.fs_hcchar5.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "MCNT"); + state->u.f4.fld.fs_hcchar5.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "DAD"); + state->u.f4.fld.fs_hcchar5.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "ODDFRM"); + state->u.f4.fld.fs_hcchar5.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "CHDIS"); + state->u.f4.fld.fs_hcchar5.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "CHENA"); + + // FS_HCCHAR6 bitfields. + state->u.f4.fld.fs_hcchar6.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "MPSIZ"); + state->u.f4.fld.fs_hcchar6.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPNUM"); + state->u.f4.fld.fs_hcchar6.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPDIR"); + state->u.f4.fld.fs_hcchar6.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "LSDEV"); + state->u.f4.fld.fs_hcchar6.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPTYP"); + state->u.f4.fld.fs_hcchar6.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "MCNT"); + state->u.f4.fld.fs_hcchar6.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "DAD"); + state->u.f4.fld.fs_hcchar6.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "ODDFRM"); + state->u.f4.fld.fs_hcchar6.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "CHDIS"); + state->u.f4.fld.fs_hcchar6.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "CHENA"); + + // FS_HCCHAR7 bitfields. + state->u.f4.fld.fs_hcchar7.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "MPSIZ"); + state->u.f4.fld.fs_hcchar7.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPNUM"); + state->u.f4.fld.fs_hcchar7.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPDIR"); + state->u.f4.fld.fs_hcchar7.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "LSDEV"); + state->u.f4.fld.fs_hcchar7.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPTYP"); + state->u.f4.fld.fs_hcchar7.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "MCNT"); + state->u.f4.fld.fs_hcchar7.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "DAD"); + state->u.f4.fld.fs_hcchar7.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "ODDFRM"); + state->u.f4.fld.fs_hcchar7.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "CHDIS"); + state->u.f4.fld.fs_hcchar7.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "CHENA"); + + // FS_HCINT0 bitfields. + state->u.f4.fld.fs_hcint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "XFRC"); + state->u.f4.fld.fs_hcint0.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "CHH"); + state->u.f4.fld.fs_hcint0.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "STALL"); + state->u.f4.fld.fs_hcint0.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "NAK"); + state->u.f4.fld.fs_hcint0.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "ACK"); + state->u.f4.fld.fs_hcint0.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "TXERR"); + state->u.f4.fld.fs_hcint0.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "BBERR"); + state->u.f4.fld.fs_hcint0.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "FRMOR"); + state->u.f4.fld.fs_hcint0.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "DTERR"); + + // FS_HCINT1 bitfields. + state->u.f4.fld.fs_hcint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "XFRC"); + state->u.f4.fld.fs_hcint1.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "CHH"); + state->u.f4.fld.fs_hcint1.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "STALL"); + state->u.f4.fld.fs_hcint1.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "NAK"); + state->u.f4.fld.fs_hcint1.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "ACK"); + state->u.f4.fld.fs_hcint1.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "TXERR"); + state->u.f4.fld.fs_hcint1.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "BBERR"); + state->u.f4.fld.fs_hcint1.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "FRMOR"); + state->u.f4.fld.fs_hcint1.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "DTERR"); + + // FS_HCINT2 bitfields. + state->u.f4.fld.fs_hcint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "XFRC"); + state->u.f4.fld.fs_hcint2.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "CHH"); + state->u.f4.fld.fs_hcint2.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "STALL"); + state->u.f4.fld.fs_hcint2.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "NAK"); + state->u.f4.fld.fs_hcint2.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "ACK"); + state->u.f4.fld.fs_hcint2.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "TXERR"); + state->u.f4.fld.fs_hcint2.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "BBERR"); + state->u.f4.fld.fs_hcint2.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "FRMOR"); + state->u.f4.fld.fs_hcint2.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "DTERR"); + + // FS_HCINT3 bitfields. + state->u.f4.fld.fs_hcint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "XFRC"); + state->u.f4.fld.fs_hcint3.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "CHH"); + state->u.f4.fld.fs_hcint3.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "STALL"); + state->u.f4.fld.fs_hcint3.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "NAK"); + state->u.f4.fld.fs_hcint3.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "ACK"); + state->u.f4.fld.fs_hcint3.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "TXERR"); + state->u.f4.fld.fs_hcint3.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "BBERR"); + state->u.f4.fld.fs_hcint3.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "FRMOR"); + state->u.f4.fld.fs_hcint3.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "DTERR"); + + // FS_HCINT4 bitfields. + state->u.f4.fld.fs_hcint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "XFRC"); + state->u.f4.fld.fs_hcint4.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "CHH"); + state->u.f4.fld.fs_hcint4.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "STALL"); + state->u.f4.fld.fs_hcint4.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "NAK"); + state->u.f4.fld.fs_hcint4.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "ACK"); + state->u.f4.fld.fs_hcint4.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "TXERR"); + state->u.f4.fld.fs_hcint4.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "BBERR"); + state->u.f4.fld.fs_hcint4.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "FRMOR"); + state->u.f4.fld.fs_hcint4.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "DTERR"); + + // FS_HCINT5 bitfields. + state->u.f4.fld.fs_hcint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "XFRC"); + state->u.f4.fld.fs_hcint5.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "CHH"); + state->u.f4.fld.fs_hcint5.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "STALL"); + state->u.f4.fld.fs_hcint5.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "NAK"); + state->u.f4.fld.fs_hcint5.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "ACK"); + state->u.f4.fld.fs_hcint5.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "TXERR"); + state->u.f4.fld.fs_hcint5.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "BBERR"); + state->u.f4.fld.fs_hcint5.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "FRMOR"); + state->u.f4.fld.fs_hcint5.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "DTERR"); + + // FS_HCINT6 bitfields. + state->u.f4.fld.fs_hcint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "XFRC"); + state->u.f4.fld.fs_hcint6.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "CHH"); + state->u.f4.fld.fs_hcint6.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "STALL"); + state->u.f4.fld.fs_hcint6.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "NAK"); + state->u.f4.fld.fs_hcint6.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "ACK"); + state->u.f4.fld.fs_hcint6.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "TXERR"); + state->u.f4.fld.fs_hcint6.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "BBERR"); + state->u.f4.fld.fs_hcint6.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "FRMOR"); + state->u.f4.fld.fs_hcint6.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "DTERR"); + + // FS_HCINT7 bitfields. + state->u.f4.fld.fs_hcint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "XFRC"); + state->u.f4.fld.fs_hcint7.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "CHH"); + state->u.f4.fld.fs_hcint7.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "STALL"); + state->u.f4.fld.fs_hcint7.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "NAK"); + state->u.f4.fld.fs_hcint7.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "ACK"); + state->u.f4.fld.fs_hcint7.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "TXERR"); + state->u.f4.fld.fs_hcint7.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "BBERR"); + state->u.f4.fld.fs_hcint7.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "FRMOR"); + state->u.f4.fld.fs_hcint7.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "DTERR"); + + // FS_HCINTMSK0 bitfields. + state->u.f4.fld.fs_hcintmsk0.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "XFRCM"); + state->u.f4.fld.fs_hcintmsk0.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "CHHM"); + state->u.f4.fld.fs_hcintmsk0.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "STALLM"); + state->u.f4.fld.fs_hcintmsk0.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "NAKM"); + state->u.f4.fld.fs_hcintmsk0.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "ACKM"); + state->u.f4.fld.fs_hcintmsk0.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "NYET"); + state->u.f4.fld.fs_hcintmsk0.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "TXERRM"); + state->u.f4.fld.fs_hcintmsk0.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "BBERRM"); + state->u.f4.fld.fs_hcintmsk0.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "FRMORM"); + state->u.f4.fld.fs_hcintmsk0.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "DTERRM"); + + // FS_HCINTMSK1 bitfields. + state->u.f4.fld.fs_hcintmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "XFRCM"); + state->u.f4.fld.fs_hcintmsk1.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "CHHM"); + state->u.f4.fld.fs_hcintmsk1.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "STALLM"); + state->u.f4.fld.fs_hcintmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "NAKM"); + state->u.f4.fld.fs_hcintmsk1.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "ACKM"); + state->u.f4.fld.fs_hcintmsk1.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "NYET"); + state->u.f4.fld.fs_hcintmsk1.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "TXERRM"); + state->u.f4.fld.fs_hcintmsk1.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "BBERRM"); + state->u.f4.fld.fs_hcintmsk1.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "FRMORM"); + state->u.f4.fld.fs_hcintmsk1.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "DTERRM"); + + // FS_HCINTMSK2 bitfields. + state->u.f4.fld.fs_hcintmsk2.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "XFRCM"); + state->u.f4.fld.fs_hcintmsk2.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "CHHM"); + state->u.f4.fld.fs_hcintmsk2.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "STALLM"); + state->u.f4.fld.fs_hcintmsk2.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "NAKM"); + state->u.f4.fld.fs_hcintmsk2.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "ACKM"); + state->u.f4.fld.fs_hcintmsk2.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "NYET"); + state->u.f4.fld.fs_hcintmsk2.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "TXERRM"); + state->u.f4.fld.fs_hcintmsk2.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "BBERRM"); + state->u.f4.fld.fs_hcintmsk2.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "FRMORM"); + state->u.f4.fld.fs_hcintmsk2.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "DTERRM"); + + // FS_HCINTMSK3 bitfields. + state->u.f4.fld.fs_hcintmsk3.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "XFRCM"); + state->u.f4.fld.fs_hcintmsk3.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "CHHM"); + state->u.f4.fld.fs_hcintmsk3.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "STALLM"); + state->u.f4.fld.fs_hcintmsk3.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "NAKM"); + state->u.f4.fld.fs_hcintmsk3.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "ACKM"); + state->u.f4.fld.fs_hcintmsk3.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "NYET"); + state->u.f4.fld.fs_hcintmsk3.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "TXERRM"); + state->u.f4.fld.fs_hcintmsk3.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "BBERRM"); + state->u.f4.fld.fs_hcintmsk3.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "FRMORM"); + state->u.f4.fld.fs_hcintmsk3.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "DTERRM"); + + // FS_HCINTMSK4 bitfields. + state->u.f4.fld.fs_hcintmsk4.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "XFRCM"); + state->u.f4.fld.fs_hcintmsk4.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "CHHM"); + state->u.f4.fld.fs_hcintmsk4.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "STALLM"); + state->u.f4.fld.fs_hcintmsk4.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "NAKM"); + state->u.f4.fld.fs_hcintmsk4.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "ACKM"); + state->u.f4.fld.fs_hcintmsk4.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "NYET"); + state->u.f4.fld.fs_hcintmsk4.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "TXERRM"); + state->u.f4.fld.fs_hcintmsk4.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "BBERRM"); + state->u.f4.fld.fs_hcintmsk4.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "FRMORM"); + state->u.f4.fld.fs_hcintmsk4.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "DTERRM"); + + // FS_HCINTMSK5 bitfields. + state->u.f4.fld.fs_hcintmsk5.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "XFRCM"); + state->u.f4.fld.fs_hcintmsk5.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "CHHM"); + state->u.f4.fld.fs_hcintmsk5.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "STALLM"); + state->u.f4.fld.fs_hcintmsk5.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "NAKM"); + state->u.f4.fld.fs_hcintmsk5.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "ACKM"); + state->u.f4.fld.fs_hcintmsk5.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "NYET"); + state->u.f4.fld.fs_hcintmsk5.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "TXERRM"); + state->u.f4.fld.fs_hcintmsk5.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "BBERRM"); + state->u.f4.fld.fs_hcintmsk5.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "FRMORM"); + state->u.f4.fld.fs_hcintmsk5.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "DTERRM"); + + // FS_HCINTMSK6 bitfields. + state->u.f4.fld.fs_hcintmsk6.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "XFRCM"); + state->u.f4.fld.fs_hcintmsk6.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "CHHM"); + state->u.f4.fld.fs_hcintmsk6.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "STALLM"); + state->u.f4.fld.fs_hcintmsk6.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "NAKM"); + state->u.f4.fld.fs_hcintmsk6.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "ACKM"); + state->u.f4.fld.fs_hcintmsk6.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "NYET"); + state->u.f4.fld.fs_hcintmsk6.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "TXERRM"); + state->u.f4.fld.fs_hcintmsk6.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "BBERRM"); + state->u.f4.fld.fs_hcintmsk6.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "FRMORM"); + state->u.f4.fld.fs_hcintmsk6.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "DTERRM"); + + // FS_HCINTMSK7 bitfields. + state->u.f4.fld.fs_hcintmsk7.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "XFRCM"); + state->u.f4.fld.fs_hcintmsk7.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "CHHM"); + state->u.f4.fld.fs_hcintmsk7.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "STALLM"); + state->u.f4.fld.fs_hcintmsk7.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "NAKM"); + state->u.f4.fld.fs_hcintmsk7.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "ACKM"); + state->u.f4.fld.fs_hcintmsk7.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "NYET"); + state->u.f4.fld.fs_hcintmsk7.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "TXERRM"); + state->u.f4.fld.fs_hcintmsk7.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "BBERRM"); + state->u.f4.fld.fs_hcintmsk7.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "FRMORM"); + state->u.f4.fld.fs_hcintmsk7.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "DTERRM"); + + // FS_HCTSIZ0 bitfields. + state->u.f4.fld.fs_hctsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "PKTCNT"); + state->u.f4.fld.fs_hctsiz0.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "DPID"); + + // FS_HCTSIZ1 bitfields. + state->u.f4.fld.fs_hctsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "PKTCNT"); + state->u.f4.fld.fs_hctsiz1.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "DPID"); + + // FS_HCTSIZ2 bitfields. + state->u.f4.fld.fs_hctsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "PKTCNT"); + state->u.f4.fld.fs_hctsiz2.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "DPID"); + + // FS_HCTSIZ3 bitfields. + state->u.f4.fld.fs_hctsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "PKTCNT"); + state->u.f4.fld.fs_hctsiz3.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "DPID"); + + // FS_HCTSIZ4 bitfields. + state->u.f4.fld.fs_hctsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "PKTCNT"); + state->u.f4.fld.fs_hctsiz4.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "DPID"); + + // FS_HCTSIZ5 bitfields. + state->u.f4.fld.fs_hctsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz5.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "PKTCNT"); + state->u.f4.fld.fs_hctsiz5.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "DPID"); + + // FS_HCTSIZ6 bitfields. + state->u.f4.fld.fs_hctsiz6.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz6.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "PKTCNT"); + state->u.f4.fld.fs_hctsiz6.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "DPID"); + + // FS_HCTSIZ7 bitfields. + state->u.f4.fld.fs_hctsiz7.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz7.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "PKTCNT"); + state->u.f4.fld.fs_hctsiz7.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "DPID"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_host_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_host_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_host_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_host_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_host_is_enabled(Object *obj) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_host_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_host_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_HOST)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_HOST"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_fs_host_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_HOSTEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_host_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_HOST); +} + +static void stm32_otg_fs_host_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_host_reset_callback; + dc->realize = stm32_otg_fs_host_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_host_is_enabled; +} + +static const TypeInfo stm32_otg_fs_host_type_info = { + .name = TYPE_STM32_OTG_FS_HOST, + .parent = TYPE_STM32_OTG_FS_HOST_PARENT, + .instance_init = stm32_otg_fs_host_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_HOSTState), + .class_init = stm32_otg_fs_host_class_init_callback, + .class_size = sizeof(STM32OTG_FS_HOSTClass) }; + +static void stm32_otg_fs_host_register_types(void) +{ + type_register_static(&stm32_otg_fs_host_type_info); +} + +type_init(stm32_otg_fs_host_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_host.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_host.h new file mode 100644 index 0000000000..c08c620d0e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_host.h @@ -0,0 +1,573 @@ +/* + * STM32 - OTG_FS_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_HOST_H_ +#define STM32_OTG_FS_HOST_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_HOST DEVICE_PATH_STM32 "OTG_FS_HOST" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_HOST TYPE_STM32_PREFIX "otg_fs_host" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_HOST_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_HOSTParentClass; +typedef PeripheralState STM32OTG_FS_HOSTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_HOST_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_HOSTClass, (obj), TYPE_STM32_OTG_FS_HOST) +#define STM32_OTG_FS_HOST_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_HOSTClass, (klass), TYPE_STM32_OTG_FS_HOST) + +typedef struct { + // private: + STM32OTG_FS_HOSTParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_HOSTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_HOST_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_HOSTState, (obj), TYPE_STM32_OTG_FS_HOST) + +typedef struct { + // private: + STM32OTG_FS_HOSTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_HOST (USB on the go full speed) registers. + struct { + Object *fs_hcfg; // 0x0 (OTG_FS host configuration register (OTG_FS_HCFG)) + Object *hfir; // 0x4 (OTG_FS Host frame interval register) + Object *fs_hfnum; // 0x8 (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) + Object *fs_hptxsts; // 0x10 (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) + Object *haint; // 0x14 (OTG_FS Host all channels interrupt register) + Object *haintmsk; // 0x18 (OTG_FS host all channels interrupt mask register) + Object *fs_hprt; // 0x40 (OTG_FS host port control and status register (OTG_FS_HPRT)) + Object *fs_hcchar0; // 0x100 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) + Object *fs_hcchar1; // 0x120 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) + Object *fs_hcchar2; // 0x140 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) + Object *fs_hcchar3; // 0x160 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) + Object *fs_hcchar4; // 0x180 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) + Object *fs_hcchar5; // 0x1A0 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) + Object *fs_hcchar6; // 0x1C0 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) + Object *fs_hcchar7; // 0x1E0 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) + Object *fs_hcint0; // 0x108 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) + Object *fs_hcint1; // 0x128 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) + Object *fs_hcint2; // 0x148 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) + Object *fs_hcint3; // 0x168 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) + Object *fs_hcint4; // 0x188 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) + Object *fs_hcint5; // 0x1A8 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) + Object *fs_hcint6; // 0x1C8 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) + Object *fs_hcint7; // 0x1E8 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) + Object *fs_hcintmsk0; // 0x10C (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) + Object *fs_hcintmsk1; // 0x12C (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) + Object *fs_hcintmsk2; // 0x14C (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) + Object *fs_hcintmsk3; // 0x16C (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) + Object *fs_hcintmsk4; // 0x18C (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) + Object *fs_hcintmsk5; // 0x1AC (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) + Object *fs_hcintmsk6; // 0x1CC (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) + Object *fs_hcintmsk7; // 0x1EC (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) + Object *fs_hctsiz0; // 0x110 (OTG_FS host channel-0 transfer size register) + Object *fs_hctsiz1; // 0x130 (OTG_FS host channel-1 transfer size register) + Object *fs_hctsiz2; // 0x150 (OTG_FS host channel-2 transfer size register) + Object *fs_hctsiz3; // 0x170 (OTG_FS host channel-3 transfer size register) + Object *fs_hctsiz4; // 0x190 (OTG_FS host channel-x transfer size register) + Object *fs_hctsiz5; // 0x1B0 (OTG_FS host channel-5 transfer size register) + Object *fs_hctsiz6; // 0x1D0 (OTG_FS host channel-6 transfer size register) + Object *fs_hctsiz7; // 0x1F0 (OTG_FS host channel-7 transfer size register) + } reg; + + struct { + + // FS_HCFG (OTG_FS host configuration register (OTG_FS_HCFG)) bitfields. + struct { + Object *fslspcs; // [0:1] FS/LS PHY clock select + Object *fslss; // [2:2] FS- and LS-only support + } fs_hcfg; + + // HFIR (OTG_FS Host frame interval register) bitfields. + struct { + Object *frivl; // [0:15] Frame interval + } hfir; + + // FS_HFNUM (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) bitfields. + struct { + Object *frnum; // [0:15] Frame number + Object *ftrem; // [16:31] Frame time remaining + } fs_hfnum; + + // FS_HPTXSTS (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) bitfields. + struct { + Object *ptxfsavl; // [0:15] Periodic transmit data FIFO space available + Object *ptxqsav; // [16:23] Periodic transmit request queue space available + Object *ptxqtop; // [24:31] Top of the periodic transmit request queue + } fs_hptxsts; + + // HAINT (OTG_FS Host all channels interrupt register) bitfields. + struct { + Object *haint; // [0:15] Channel interrupts + } haint; + + // HAINTMSK (OTG_FS host all channels interrupt mask register) bitfields. + struct { + Object *haintm; // [0:15] Channel interrupt mask + } haintmsk; + + // FS_HPRT (OTG_FS host port control and status register (OTG_FS_HPRT)) bitfields. + struct { + Object *pcsts; // [0:0] Port connect status + Object *pcdet; // [1:1] Port connect detected + Object *pena; // [2:2] Port enable + Object *penchng; // [3:3] Port enable/disable change + Object *poca; // [4:4] Port overcurrent active + Object *pocchng; // [5:5] Port overcurrent change + Object *pres; // [6:6] Port resume + Object *psusp; // [7:7] Port suspend + Object *prst; // [8:8] Port reset + Object *plsts; // [10:11] Port line status + Object *ppwr; // [12:12] Port power + Object *ptctl; // [13:16] Port test control + Object *pspd; // [17:18] Port speed + } fs_hprt; + + // FS_HCCHAR0 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar0; + + // FS_HCCHAR1 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar1; + + // FS_HCCHAR2 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar2; + + // FS_HCCHAR3 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar3; + + // FS_HCCHAR4 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar4; + + // FS_HCCHAR5 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar5; + + // FS_HCCHAR6 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar6; + + // FS_HCCHAR7 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar7; + + // FS_HCINT0 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint0; + + // FS_HCINT1 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint1; + + // FS_HCINT2 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint2; + + // FS_HCINT3 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint3; + + // FS_HCINT4 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint4; + + // FS_HCINT5 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint5; + + // FS_HCINT6 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint6; + + // FS_HCINT7 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint7; + + // FS_HCINTMSK0 (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk0; + + // FS_HCINTMSK1 (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk1; + + // FS_HCINTMSK2 (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk2; + + // FS_HCINTMSK3 (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk3; + + // FS_HCINTMSK4 (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk4; + + // FS_HCINTMSK5 (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk5; + + // FS_HCINTMSK6 (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk6; + + // FS_HCINTMSK7 (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk7; + + // FS_HCTSIZ0 (OTG_FS host channel-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz0; + + // FS_HCTSIZ1 (OTG_FS host channel-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz1; + + // FS_HCTSIZ2 (OTG_FS host channel-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz2; + + // FS_HCTSIZ3 (OTG_FS host channel-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz3; + + // FS_HCTSIZ4 (OTG_FS host channel-x transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz4; + + // FS_HCTSIZ5 (OTG_FS host channel-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz5; + + // FS_HCTSIZ6 (OTG_FS host channel-6 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz6; + + // FS_HCTSIZ7 (OTG_FS host channel-7 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz7; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_HOSTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_HOST_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_pwrclk.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_pwrclk.c new file mode 100644 index 0000000000..a688859921 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_pwrclk.c @@ -0,0 +1,240 @@ +/* + * STM32 - OTG_FS_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_fs_pwrclk_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_pcgcctl = cm_object_get_child_by_name(obj, "FS_PCGCCTL"); + + + // FS_PCGCCTL bitfields. + state->u.f4.fld.fs_pcgcctl.stppclk = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "STPPCLK"); + state->u.f4.fld.fs_pcgcctl.gatehclk = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "GATEHCLK"); + state->u.f4.fld.fs_pcgcctl.physusp = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "PHYSUSP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_pwrclk_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_pwrclk_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_pwrclk_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_pwrclk_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_pwrclk_is_enabled(Object *obj) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_pwrclk_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_pwrclk_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_PWRCLK)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_PWRCLK"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_fs_pwrclk_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_PWRCLKEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_pwrclk_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_PWRCLK); +} + +static void stm32_otg_fs_pwrclk_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_pwrclk_reset_callback; + dc->realize = stm32_otg_fs_pwrclk_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_pwrclk_is_enabled; +} + +static const TypeInfo stm32_otg_fs_pwrclk_type_info = { + .name = TYPE_STM32_OTG_FS_PWRCLK, + .parent = TYPE_STM32_OTG_FS_PWRCLK_PARENT, + .instance_init = stm32_otg_fs_pwrclk_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_PWRCLKState), + .class_init = stm32_otg_fs_pwrclk_class_init_callback, + .class_size = sizeof(STM32OTG_FS_PWRCLKClass) }; + +static void stm32_otg_fs_pwrclk_register_types(void) +{ + type_register_static(&stm32_otg_fs_pwrclk_type_info); +} + +type_init(stm32_otg_fs_pwrclk_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_pwrclk.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_pwrclk.h new file mode 100644 index 0000000000..5044b8fa1b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_fs_pwrclk.h @@ -0,0 +1,107 @@ +/* + * STM32 - OTG_FS_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_PWRCLK_H_ +#define STM32_OTG_FS_PWRCLK_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_PWRCLK DEVICE_PATH_STM32 "OTG_FS_PWRCLK" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_PWRCLK TYPE_STM32_PREFIX "otg_fs_pwrclk" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_PWRCLK_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_PWRCLKParentClass; +typedef PeripheralState STM32OTG_FS_PWRCLKParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_PWRCLK_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_PWRCLKClass, (obj), TYPE_STM32_OTG_FS_PWRCLK) +#define STM32_OTG_FS_PWRCLK_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_PWRCLKClass, (klass), TYPE_STM32_OTG_FS_PWRCLK) + +typedef struct { + // private: + STM32OTG_FS_PWRCLKParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_PWRCLKClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_PWRCLK_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_PWRCLKState, (obj), TYPE_STM32_OTG_FS_PWRCLK) + +typedef struct { + // private: + STM32OTG_FS_PWRCLKParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_PWRCLK (USB on the go full speed) registers. + struct { + Object *fs_pcgcctl; // 0x0 (OTG_FS power and clock gating control register) + } reg; + + struct { + + // FS_PCGCCTL (OTG_FS power and clock gating control register) bitfields. + struct { + Object *stppclk; // [0:0] Stop PHY clock + Object *gatehclk; // [1:1] Gate HCLK + Object *physusp; // [4:4] PHY Suspended + } fs_pcgcctl; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_PWRCLKState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_PWRCLK_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_device.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_device.c new file mode 100644 index 0000000000..cb57dfd19a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_device.c @@ -0,0 +1,832 @@ +/* + * STM32 - OTG_HS_DEVICE (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_hs_device_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_dcfg = cm_object_get_child_by_name(obj, "OTG_HS_DCFG"); + state->u.f4.reg.otg_hs_dctl = cm_object_get_child_by_name(obj, "OTG_HS_DCTL"); + state->u.f4.reg.otg_hs_dsts = cm_object_get_child_by_name(obj, "OTG_HS_DSTS"); + state->u.f4.reg.otg_hs_diepmsk = cm_object_get_child_by_name(obj, "OTG_HS_DIEPMSK"); + state->u.f4.reg.otg_hs_doepmsk = cm_object_get_child_by_name(obj, "OTG_HS_DOEPMSK"); + state->u.f4.reg.otg_hs_daint = cm_object_get_child_by_name(obj, "OTG_HS_DAINT"); + state->u.f4.reg.otg_hs_daintmsk = cm_object_get_child_by_name(obj, "OTG_HS_DAINTMSK"); + state->u.f4.reg.otg_hs_dvbusdis = cm_object_get_child_by_name(obj, "OTG_HS_DVBUSDIS"); + state->u.f4.reg.otg_hs_dvbuspulse = cm_object_get_child_by_name(obj, "OTG_HS_DVBUSPULSE"); + state->u.f4.reg.otg_hs_dthrctl = cm_object_get_child_by_name(obj, "OTG_HS_DTHRCTL"); + state->u.f4.reg.otg_hs_diepempmsk = cm_object_get_child_by_name(obj, "OTG_HS_DIEPEMPMSK"); + state->u.f4.reg.otg_hs_deachint = cm_object_get_child_by_name(obj, "OTG_HS_DEACHINT"); + state->u.f4.reg.otg_hs_deachintmsk = cm_object_get_child_by_name(obj, "OTG_HS_DEACHINTMSK"); + state->u.f4.reg.otg_hs_diepeachmsk1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPEACHMSK1"); + state->u.f4.reg.otg_hs_doepeachmsk1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPEACHMSK1"); + state->u.f4.reg.otg_hs_diepctl0 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL0"); + state->u.f4.reg.otg_hs_diepctl1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL1"); + state->u.f4.reg.otg_hs_diepctl2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL2"); + state->u.f4.reg.otg_hs_diepctl3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL3"); + state->u.f4.reg.otg_hs_diepctl4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL4"); + state->u.f4.reg.otg_hs_diepctl5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL5"); + state->u.f4.reg.otg_hs_diepctl6 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL6"); + state->u.f4.reg.otg_hs_diepctl7 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL7"); + state->u.f4.reg.otg_hs_diepint0 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT0"); + state->u.f4.reg.otg_hs_diepint1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT1"); + state->u.f4.reg.otg_hs_diepint2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT2"); + state->u.f4.reg.otg_hs_diepint3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT3"); + state->u.f4.reg.otg_hs_diepint4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT4"); + state->u.f4.reg.otg_hs_diepint5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT5"); + state->u.f4.reg.otg_hs_diepint6 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT6"); + state->u.f4.reg.otg_hs_diepint7 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT7"); + state->u.f4.reg.otg_hs_dieptsiz0 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ0"); + state->u.f4.reg.otg_hs_diepdma1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA1"); + state->u.f4.reg.otg_hs_diepdma2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA2"); + state->u.f4.reg.otg_hs_diepdma3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA3"); + state->u.f4.reg.otg_hs_diepdma4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA4"); + state->u.f4.reg.otg_hs_diepdma5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA5"); + state->u.f4.reg.otg_hs_dtxfsts0 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS0"); + state->u.f4.reg.otg_hs_dtxfsts1 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS1"); + state->u.f4.reg.otg_hs_dtxfsts2 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS2"); + state->u.f4.reg.otg_hs_dtxfsts3 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS3"); + state->u.f4.reg.otg_hs_dtxfsts4 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS4"); + state->u.f4.reg.otg_hs_dtxfsts5 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS5"); + state->u.f4.reg.otg_hs_dieptsiz1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ1"); + state->u.f4.reg.otg_hs_dieptsiz2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ2"); + state->u.f4.reg.otg_hs_dieptsiz3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ3"); + state->u.f4.reg.otg_hs_dieptsiz4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ4"); + state->u.f4.reg.otg_hs_dieptsiz5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ5"); + state->u.f4.reg.otg_hs_doepctl0 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL0"); + state->u.f4.reg.otg_hs_doepctl1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL1"); + state->u.f4.reg.otg_hs_doepctl2 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL2"); + state->u.f4.reg.otg_hs_doepctl3 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL3"); + state->u.f4.reg.otg_hs_doepint0 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT0"); + state->u.f4.reg.otg_hs_doepint1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT1"); + state->u.f4.reg.otg_hs_doepint2 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT2"); + state->u.f4.reg.otg_hs_doepint3 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT3"); + state->u.f4.reg.otg_hs_doepint4 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT4"); + state->u.f4.reg.otg_hs_doepint5 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT5"); + state->u.f4.reg.otg_hs_doepint6 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT6"); + state->u.f4.reg.otg_hs_doepint7 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT7"); + state->u.f4.reg.otg_hs_doeptsiz0 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ0"); + state->u.f4.reg.otg_hs_doeptsiz1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ1"); + state->u.f4.reg.otg_hs_doeptsiz2 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ2"); + state->u.f4.reg.otg_hs_doeptsiz3 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ3"); + state->u.f4.reg.otg_hs_doeptsiz4 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ4"); + + + // OTG_HS_DCFG bitfields. + state->u.f4.fld.otg_hs_dcfg.dspd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "DSPD"); + state->u.f4.fld.otg_hs_dcfg.nzlsohsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "NZLSOHSK"); + state->u.f4.fld.otg_hs_dcfg.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "DAD"); + state->u.f4.fld.otg_hs_dcfg.pfivl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "PFIVL"); + state->u.f4.fld.otg_hs_dcfg.perschivl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "PERSCHIVL"); + + // OTG_HS_DCTL bitfields. + state->u.f4.fld.otg_hs_dctl.rwusig = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "RWUSIG"); + state->u.f4.fld.otg_hs_dctl.sdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "SDIS"); + state->u.f4.fld.otg_hs_dctl.ginsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "GINSTS"); + state->u.f4.fld.otg_hs_dctl.gonsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "GONSTS"); + state->u.f4.fld.otg_hs_dctl.tctl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "TCTL"); + state->u.f4.fld.otg_hs_dctl.sginak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "SGINAK"); + state->u.f4.fld.otg_hs_dctl.cginak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "CGINAK"); + state->u.f4.fld.otg_hs_dctl.sgonak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "SGONAK"); + state->u.f4.fld.otg_hs_dctl.cgonak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "CGONAK"); + state->u.f4.fld.otg_hs_dctl.poprgdne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "POPRGDNE"); + + // OTG_HS_DSTS bitfields. + state->u.f4.fld.otg_hs_dsts.suspsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "SUSPSTS"); + state->u.f4.fld.otg_hs_dsts.enumspd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "ENUMSPD"); + state->u.f4.fld.otg_hs_dsts.eerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "EERR"); + state->u.f4.fld.otg_hs_dsts.fnsof = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "FNSOF"); + + // OTG_HS_DIEPMSK bitfields. + state->u.f4.fld.otg_hs_diepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "XFRCM"); + state->u.f4.fld.otg_hs_diepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "EPDM"); + state->u.f4.fld.otg_hs_diepmsk.tom = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "TOM"); + state->u.f4.fld.otg_hs_diepmsk.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "ITTXFEMSK"); + state->u.f4.fld.otg_hs_diepmsk.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "INEPNMM"); + state->u.f4.fld.otg_hs_diepmsk.inepnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "INEPNEM"); + state->u.f4.fld.otg_hs_diepmsk.txfurm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "TXFURM"); + state->u.f4.fld.otg_hs_diepmsk.bim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "BIM"); + + // OTG_HS_DOEPMSK bitfields. + state->u.f4.fld.otg_hs_doepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "XFRCM"); + state->u.f4.fld.otg_hs_doepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "EPDM"); + state->u.f4.fld.otg_hs_doepmsk.stupm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "STUPM"); + state->u.f4.fld.otg_hs_doepmsk.otepdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "OTEPDM"); + state->u.f4.fld.otg_hs_doepmsk.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepmsk.opem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "OPEM"); + state->u.f4.fld.otg_hs_doepmsk.boim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "BOIM"); + + // OTG_HS_DAINT bitfields. + state->u.f4.fld.otg_hs_daint.iepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daint, "IEPINT"); + state->u.f4.fld.otg_hs_daint.oepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daint, "OEPINT"); + + // OTG_HS_DAINTMSK bitfields. + state->u.f4.fld.otg_hs_daintmsk.iepm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daintmsk, "IEPM"); + state->u.f4.fld.otg_hs_daintmsk.oepm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daintmsk, "OEPM"); + + // OTG_HS_DVBUSDIS bitfields. + state->u.f4.fld.otg_hs_dvbusdis.vbusdt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dvbusdis, "VBUSDT"); + + // OTG_HS_DVBUSPULSE bitfields. + state->u.f4.fld.otg_hs_dvbuspulse.dvbusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dvbuspulse, "DVBUSP"); + + // OTG_HS_DTHRCTL bitfields. + state->u.f4.fld.otg_hs_dthrctl.nonisothren = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "NONISOTHREN"); + state->u.f4.fld.otg_hs_dthrctl.isothren = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "ISOTHREN"); + state->u.f4.fld.otg_hs_dthrctl.txthrlen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "TXTHRLEN"); + state->u.f4.fld.otg_hs_dthrctl.rxthren = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "RXTHREN"); + state->u.f4.fld.otg_hs_dthrctl.rxthrlen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "RXTHRLEN"); + state->u.f4.fld.otg_hs_dthrctl.arpen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "ARPEN"); + + // OTG_HS_DIEPEMPMSK bitfields. + state->u.f4.fld.otg_hs_diepempmsk.ineptxfem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepempmsk, "INEPTXFEM"); + + // OTG_HS_DEACHINT bitfields. + state->u.f4.fld.otg_hs_deachint.iep1int = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachint, "IEP1INT"); + state->u.f4.fld.otg_hs_deachint.oep1int = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachint, "OEP1INT"); + + // OTG_HS_DEACHINTMSK bitfields. + state->u.f4.fld.otg_hs_deachintmsk.iep1intm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachintmsk, "IEP1INTM"); + state->u.f4.fld.otg_hs_deachintmsk.oep1intm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachintmsk, "OEP1INTM"); + + // OTG_HS_DIEPEACHMSK1 bitfields. + state->u.f4.fld.otg_hs_diepeachmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "XFRCM"); + state->u.f4.fld.otg_hs_diepeachmsk1.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "EPDM"); + state->u.f4.fld.otg_hs_diepeachmsk1.tom = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "TOM"); + state->u.f4.fld.otg_hs_diepeachmsk1.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "ITTXFEMSK"); + state->u.f4.fld.otg_hs_diepeachmsk1.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "INEPNMM"); + state->u.f4.fld.otg_hs_diepeachmsk1.inepnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "INEPNEM"); + state->u.f4.fld.otg_hs_diepeachmsk1.txfurm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "TXFURM"); + state->u.f4.fld.otg_hs_diepeachmsk1.bim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "BIM"); + state->u.f4.fld.otg_hs_diepeachmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "NAKM"); + + // OTG_HS_DOEPEACHMSK1 bitfields. + state->u.f4.fld.otg_hs_doepeachmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "XFRCM"); + state->u.f4.fld.otg_hs_doepeachmsk1.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "EPDM"); + state->u.f4.fld.otg_hs_doepeachmsk1.tom = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "TOM"); + state->u.f4.fld.otg_hs_doepeachmsk1.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "ITTXFEMSK"); + state->u.f4.fld.otg_hs_doepeachmsk1.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "INEPNMM"); + state->u.f4.fld.otg_hs_doepeachmsk1.inepnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "INEPNEM"); + state->u.f4.fld.otg_hs_doepeachmsk1.txfurm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "TXFURM"); + state->u.f4.fld.otg_hs_doepeachmsk1.bim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "BIM"); + state->u.f4.fld.otg_hs_doepeachmsk1.berrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "BERRM"); + state->u.f4.fld.otg_hs_doepeachmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "NAKM"); + state->u.f4.fld.otg_hs_doepeachmsk1.nyetm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "NYETM"); + + // OTG_HS_DIEPCTL0 bitfields. + state->u.f4.fld.otg_hs_diepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl0.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "Stall"); + state->u.f4.fld.otg_hs_diepctl0.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "CNAK"); + state->u.f4.fld.otg_hs_diepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "SNAK"); + state->u.f4.fld.otg_hs_diepctl0.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl0.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EPENA"); + + // OTG_HS_DIEPCTL1 bitfields. + state->u.f4.fld.otg_hs_diepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "Stall"); + state->u.f4.fld.otg_hs_diepctl1.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "CNAK"); + state->u.f4.fld.otg_hs_diepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "SNAK"); + state->u.f4.fld.otg_hs_diepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl1.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EPENA"); + + // OTG_HS_DIEPCTL2 bitfields. + state->u.f4.fld.otg_hs_diepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "Stall"); + state->u.f4.fld.otg_hs_diepctl2.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "CNAK"); + state->u.f4.fld.otg_hs_diepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "SNAK"); + state->u.f4.fld.otg_hs_diepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EPENA"); + + // OTG_HS_DIEPCTL3 bitfields. + state->u.f4.fld.otg_hs_diepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "Stall"); + state->u.f4.fld.otg_hs_diepctl3.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "CNAK"); + state->u.f4.fld.otg_hs_diepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "SNAK"); + state->u.f4.fld.otg_hs_diepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EPENA"); + + // OTG_HS_DIEPCTL4 bitfields. + state->u.f4.fld.otg_hs_diepctl4.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl4.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl4.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl4.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl4.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl4.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "Stall"); + state->u.f4.fld.otg_hs_diepctl4.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl4.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "CNAK"); + state->u.f4.fld.otg_hs_diepctl4.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "SNAK"); + state->u.f4.fld.otg_hs_diepctl4.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl4.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl4.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl4.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EPENA"); + + // OTG_HS_DIEPCTL5 bitfields. + state->u.f4.fld.otg_hs_diepctl5.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl5.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl5.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl5.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl5.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl5.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "Stall"); + state->u.f4.fld.otg_hs_diepctl5.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl5.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "CNAK"); + state->u.f4.fld.otg_hs_diepctl5.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "SNAK"); + state->u.f4.fld.otg_hs_diepctl5.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl5.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl5.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl5.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EPENA"); + + // OTG_HS_DIEPCTL6 bitfields. + state->u.f4.fld.otg_hs_diepctl6.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl6.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl6.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl6.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl6.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl6.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "Stall"); + state->u.f4.fld.otg_hs_diepctl6.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl6.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "CNAK"); + state->u.f4.fld.otg_hs_diepctl6.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "SNAK"); + state->u.f4.fld.otg_hs_diepctl6.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl6.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl6.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl6.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EPENA"); + + // OTG_HS_DIEPCTL7 bitfields. + state->u.f4.fld.otg_hs_diepctl7.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl7.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl7.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl7.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl7.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl7.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "Stall"); + state->u.f4.fld.otg_hs_diepctl7.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl7.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "CNAK"); + state->u.f4.fld.otg_hs_diepctl7.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "SNAK"); + state->u.f4.fld.otg_hs_diepctl7.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl7.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl7.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl7.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EPENA"); + + // OTG_HS_DIEPINT0 bitfields. + state->u.f4.fld.otg_hs_diepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "XFRC"); + state->u.f4.fld.otg_hs_diepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "EPDISD"); + state->u.f4.fld.otg_hs_diepint0.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "TOC"); + state->u.f4.fld.otg_hs_diepint0.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint0.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "INEPNE"); + state->u.f4.fld.otg_hs_diepint0.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "TXFE"); + state->u.f4.fld.otg_hs_diepint0.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint0.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "BNA"); + state->u.f4.fld.otg_hs_diepint0.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint0.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "BERR"); + state->u.f4.fld.otg_hs_diepint0.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "NAK"); + + // OTG_HS_DIEPINT1 bitfields. + state->u.f4.fld.otg_hs_diepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "XFRC"); + state->u.f4.fld.otg_hs_diepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "EPDISD"); + state->u.f4.fld.otg_hs_diepint1.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "TOC"); + state->u.f4.fld.otg_hs_diepint1.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint1.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "INEPNE"); + state->u.f4.fld.otg_hs_diepint1.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "TXFE"); + state->u.f4.fld.otg_hs_diepint1.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint1.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "BNA"); + state->u.f4.fld.otg_hs_diepint1.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint1.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "BERR"); + state->u.f4.fld.otg_hs_diepint1.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "NAK"); + + // OTG_HS_DIEPINT2 bitfields. + state->u.f4.fld.otg_hs_diepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "XFRC"); + state->u.f4.fld.otg_hs_diepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "EPDISD"); + state->u.f4.fld.otg_hs_diepint2.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "TOC"); + state->u.f4.fld.otg_hs_diepint2.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint2.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "INEPNE"); + state->u.f4.fld.otg_hs_diepint2.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "TXFE"); + state->u.f4.fld.otg_hs_diepint2.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint2.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "BNA"); + state->u.f4.fld.otg_hs_diepint2.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint2.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "BERR"); + state->u.f4.fld.otg_hs_diepint2.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "NAK"); + + // OTG_HS_DIEPINT3 bitfields. + state->u.f4.fld.otg_hs_diepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "XFRC"); + state->u.f4.fld.otg_hs_diepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "EPDISD"); + state->u.f4.fld.otg_hs_diepint3.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "TOC"); + state->u.f4.fld.otg_hs_diepint3.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint3.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "INEPNE"); + state->u.f4.fld.otg_hs_diepint3.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "TXFE"); + state->u.f4.fld.otg_hs_diepint3.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint3.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "BNA"); + state->u.f4.fld.otg_hs_diepint3.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint3.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "BERR"); + state->u.f4.fld.otg_hs_diepint3.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "NAK"); + + // OTG_HS_DIEPINT4 bitfields. + state->u.f4.fld.otg_hs_diepint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "XFRC"); + state->u.f4.fld.otg_hs_diepint4.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "EPDISD"); + state->u.f4.fld.otg_hs_diepint4.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "TOC"); + state->u.f4.fld.otg_hs_diepint4.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint4.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "INEPNE"); + state->u.f4.fld.otg_hs_diepint4.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "TXFE"); + state->u.f4.fld.otg_hs_diepint4.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint4.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "BNA"); + state->u.f4.fld.otg_hs_diepint4.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint4.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "BERR"); + state->u.f4.fld.otg_hs_diepint4.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "NAK"); + + // OTG_HS_DIEPINT5 bitfields. + state->u.f4.fld.otg_hs_diepint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "XFRC"); + state->u.f4.fld.otg_hs_diepint5.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "EPDISD"); + state->u.f4.fld.otg_hs_diepint5.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "TOC"); + state->u.f4.fld.otg_hs_diepint5.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint5.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "INEPNE"); + state->u.f4.fld.otg_hs_diepint5.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "TXFE"); + state->u.f4.fld.otg_hs_diepint5.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint5.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "BNA"); + state->u.f4.fld.otg_hs_diepint5.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint5.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "BERR"); + state->u.f4.fld.otg_hs_diepint5.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "NAK"); + + // OTG_HS_DIEPINT6 bitfields. + state->u.f4.fld.otg_hs_diepint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "XFRC"); + state->u.f4.fld.otg_hs_diepint6.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "EPDISD"); + state->u.f4.fld.otg_hs_diepint6.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "TOC"); + state->u.f4.fld.otg_hs_diepint6.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint6.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "INEPNE"); + state->u.f4.fld.otg_hs_diepint6.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "TXFE"); + state->u.f4.fld.otg_hs_diepint6.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint6.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "BNA"); + state->u.f4.fld.otg_hs_diepint6.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint6.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "BERR"); + state->u.f4.fld.otg_hs_diepint6.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "NAK"); + + // OTG_HS_DIEPINT7 bitfields. + state->u.f4.fld.otg_hs_diepint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "XFRC"); + state->u.f4.fld.otg_hs_diepint7.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "EPDISD"); + state->u.f4.fld.otg_hs_diepint7.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "TOC"); + state->u.f4.fld.otg_hs_diepint7.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint7.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "INEPNE"); + state->u.f4.fld.otg_hs_diepint7.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "TXFE"); + state->u.f4.fld.otg_hs_diepint7.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint7.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "BNA"); + state->u.f4.fld.otg_hs_diepint7.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint7.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "BERR"); + state->u.f4.fld.otg_hs_diepint7.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "NAK"); + + // OTG_HS_DIEPTSIZ0 bitfields. + state->u.f4.fld.otg_hs_dieptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz0, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz0, "PKTCNT"); + + // OTG_HS_DIEPDMA1 bitfields. + state->u.f4.fld.otg_hs_diepdma1.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma1, "DMAADDR"); + + // OTG_HS_DIEPDMA2 bitfields. + state->u.f4.fld.otg_hs_diepdma2.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma2, "DMAADDR"); + + // OTG_HS_DIEPDMA3 bitfields. + state->u.f4.fld.otg_hs_diepdma3.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma3, "DMAADDR"); + + // OTG_HS_DIEPDMA4 bitfields. + state->u.f4.fld.otg_hs_diepdma4.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma4, "DMAADDR"); + + // OTG_HS_DIEPDMA5 bitfields. + state->u.f4.fld.otg_hs_diepdma5.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma5, "DMAADDR"); + + // OTG_HS_DTXFSTS0 bitfields. + state->u.f4.fld.otg_hs_dtxfsts0.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts0, "INEPTFSAV"); + + // OTG_HS_DTXFSTS1 bitfields. + state->u.f4.fld.otg_hs_dtxfsts1.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts1, "INEPTFSAV"); + + // OTG_HS_DTXFSTS2 bitfields. + state->u.f4.fld.otg_hs_dtxfsts2.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts2, "INEPTFSAV"); + + // OTG_HS_DTXFSTS3 bitfields. + state->u.f4.fld.otg_hs_dtxfsts3.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts3, "INEPTFSAV"); + + // OTG_HS_DTXFSTS4 bitfields. + state->u.f4.fld.otg_hs_dtxfsts4.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts4, "INEPTFSAV"); + + // OTG_HS_DTXFSTS5 bitfields. + state->u.f4.fld.otg_hs_dtxfsts5.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts5, "INEPTFSAV"); + + // OTG_HS_DIEPTSIZ1 bitfields. + state->u.f4.fld.otg_hs_dieptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz1, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz1, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz1, "MCNT"); + + // OTG_HS_DIEPTSIZ2 bitfields. + state->u.f4.fld.otg_hs_dieptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz2, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz2, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz2, "MCNT"); + + // OTG_HS_DIEPTSIZ3 bitfields. + state->u.f4.fld.otg_hs_dieptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz3, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz3, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz3, "MCNT"); + + // OTG_HS_DIEPTSIZ4 bitfields. + state->u.f4.fld.otg_hs_dieptsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz4, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz4, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz4.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz4, "MCNT"); + + // OTG_HS_DIEPTSIZ5 bitfields. + state->u.f4.fld.otg_hs_dieptsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz5, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz5.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz5, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz5.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz5, "MCNT"); + + // OTG_HS_DOEPCTL0 bitfields. + state->u.f4.fld.otg_hs_doepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl0.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "SNPM"); + state->u.f4.fld.otg_hs_doepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "Stall"); + state->u.f4.fld.otg_hs_doepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "CNAK"); + state->u.f4.fld.otg_hs_doepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "SNAK"); + state->u.f4.fld.otg_hs_doepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "EPENA"); + + // OTG_HS_DOEPCTL1 bitfields. + state->u.f4.fld.otg_hs_doepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EONUM_DPID"); + state->u.f4.fld.otg_hs_doepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl1.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SNPM"); + state->u.f4.fld.otg_hs_doepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "Stall"); + state->u.f4.fld.otg_hs_doepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "CNAK"); + state->u.f4.fld.otg_hs_doepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SNAK"); + state->u.f4.fld.otg_hs_doepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_doepctl1.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SODDFRM"); + state->u.f4.fld.otg_hs_doepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EPENA"); + + // OTG_HS_DOEPCTL2 bitfields. + state->u.f4.fld.otg_hs_doepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EONUM_DPID"); + state->u.f4.fld.otg_hs_doepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl2.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SNPM"); + state->u.f4.fld.otg_hs_doepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "Stall"); + state->u.f4.fld.otg_hs_doepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "CNAK"); + state->u.f4.fld.otg_hs_doepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SNAK"); + state->u.f4.fld.otg_hs_doepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_doepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SODDFRM"); + state->u.f4.fld.otg_hs_doepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EPENA"); + + // OTG_HS_DOEPCTL3 bitfields. + state->u.f4.fld.otg_hs_doepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EONUM_DPID"); + state->u.f4.fld.otg_hs_doepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl3.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SNPM"); + state->u.f4.fld.otg_hs_doepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "Stall"); + state->u.f4.fld.otg_hs_doepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "CNAK"); + state->u.f4.fld.otg_hs_doepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SNAK"); + state->u.f4.fld.otg_hs_doepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_doepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SODDFRM"); + state->u.f4.fld.otg_hs_doepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EPENA"); + + // OTG_HS_DOEPINT0 bitfields. + state->u.f4.fld.otg_hs_doepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "XFRC"); + state->u.f4.fld.otg_hs_doepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "EPDISD"); + state->u.f4.fld.otg_hs_doepint0.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "STUP"); + state->u.f4.fld.otg_hs_doepint0.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint0.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint0.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "NYET"); + + // OTG_HS_DOEPINT1 bitfields. + state->u.f4.fld.otg_hs_doepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "XFRC"); + state->u.f4.fld.otg_hs_doepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "EPDISD"); + state->u.f4.fld.otg_hs_doepint1.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "STUP"); + state->u.f4.fld.otg_hs_doepint1.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint1.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint1.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "NYET"); + + // OTG_HS_DOEPINT2 bitfields. + state->u.f4.fld.otg_hs_doepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "XFRC"); + state->u.f4.fld.otg_hs_doepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "EPDISD"); + state->u.f4.fld.otg_hs_doepint2.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "STUP"); + state->u.f4.fld.otg_hs_doepint2.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint2.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint2.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "NYET"); + + // OTG_HS_DOEPINT3 bitfields. + state->u.f4.fld.otg_hs_doepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "XFRC"); + state->u.f4.fld.otg_hs_doepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "EPDISD"); + state->u.f4.fld.otg_hs_doepint3.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "STUP"); + state->u.f4.fld.otg_hs_doepint3.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint3.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint3.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "NYET"); + + // OTG_HS_DOEPINT4 bitfields. + state->u.f4.fld.otg_hs_doepint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "XFRC"); + state->u.f4.fld.otg_hs_doepint4.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "EPDISD"); + state->u.f4.fld.otg_hs_doepint4.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "STUP"); + state->u.f4.fld.otg_hs_doepint4.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint4.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint4.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "NYET"); + + // OTG_HS_DOEPINT5 bitfields. + state->u.f4.fld.otg_hs_doepint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "XFRC"); + state->u.f4.fld.otg_hs_doepint5.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "EPDISD"); + state->u.f4.fld.otg_hs_doepint5.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "STUP"); + state->u.f4.fld.otg_hs_doepint5.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint5.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint5.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "NYET"); + + // OTG_HS_DOEPINT6 bitfields. + state->u.f4.fld.otg_hs_doepint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "XFRC"); + state->u.f4.fld.otg_hs_doepint6.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "EPDISD"); + state->u.f4.fld.otg_hs_doepint6.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "STUP"); + state->u.f4.fld.otg_hs_doepint6.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint6.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint6.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "NYET"); + + // OTG_HS_DOEPINT7 bitfields. + state->u.f4.fld.otg_hs_doepint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "XFRC"); + state->u.f4.fld.otg_hs_doepint7.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "EPDISD"); + state->u.f4.fld.otg_hs_doepint7.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "STUP"); + state->u.f4.fld.otg_hs_doepint7.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint7.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint7.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "NYET"); + + // OTG_HS_DOEPTSIZ0 bitfields. + state->u.f4.fld.otg_hs_doeptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz0, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz0, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz0.stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz0, "STUPCNT"); + + // OTG_HS_DOEPTSIZ1 bitfields. + state->u.f4.fld.otg_hs_doeptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz1, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz1, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz1.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz1, "RXDPID_STUPCNT"); + + // OTG_HS_DOEPTSIZ2 bitfields. + state->u.f4.fld.otg_hs_doeptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz2, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz2, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz2.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz2, "RXDPID_STUPCNT"); + + // OTG_HS_DOEPTSIZ3 bitfields. + state->u.f4.fld.otg_hs_doeptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz3, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz3, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz3.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz3, "RXDPID_STUPCNT"); + + // OTG_HS_DOEPTSIZ4 bitfields. + state->u.f4.fld.otg_hs_doeptsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz4, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz4, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz4.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz4, "RXDPID_STUPCNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_device_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_device_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_device_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_device_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_device_is_enabled(Object *obj) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_device_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_device_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_DEVICE)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_DEVICE"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_hs_device_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_DEVICEEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_device_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_DEVICE); +} + +static void stm32_otg_hs_device_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_device_reset_callback; + dc->realize = stm32_otg_hs_device_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_device_is_enabled; +} + +static const TypeInfo stm32_otg_hs_device_type_info = { + .name = TYPE_STM32_OTG_HS_DEVICE, + .parent = TYPE_STM32_OTG_HS_DEVICE_PARENT, + .instance_init = stm32_otg_hs_device_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_DEVICEState), + .class_init = stm32_otg_hs_device_class_init_callback, + .class_size = sizeof(STM32OTG_HS_DEVICEClass) }; + +static void stm32_otg_hs_device_register_types(void) +{ + type_register_static(&stm32_otg_hs_device_type_info); +} + +type_init(stm32_otg_hs_device_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_device.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_device.h new file mode 100644 index 0000000000..85aae4a8a3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_device.h @@ -0,0 +1,827 @@ +/* + * STM32 - OTG_HS_DEVICE (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_DEVICE_H_ +#define STM32_OTG_HS_DEVICE_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_DEVICE DEVICE_PATH_STM32 "OTG_HS_DEVICE" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_DEVICE TYPE_STM32_PREFIX "otg_hs_device" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_DEVICE_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_DEVICEParentClass; +typedef PeripheralState STM32OTG_HS_DEVICEParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_DEVICEClass, (obj), TYPE_STM32_OTG_HS_DEVICE) +#define STM32_OTG_HS_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_DEVICEClass, (klass), TYPE_STM32_OTG_HS_DEVICE) + +typedef struct { + // private: + STM32OTG_HS_DEVICEParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_DEVICEClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_DEVICE_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_DEVICEState, (obj), TYPE_STM32_OTG_HS_DEVICE) + +typedef struct { + // private: + STM32OTG_HS_DEVICEParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_DEVICE (USB on the go high speed) registers. + struct { + Object *otg_hs_dcfg; // 0x0 (OTG_HS device configuration register) + Object *otg_hs_dctl; // 0x4 (OTG_HS device control register) + Object *otg_hs_dsts; // 0x8 (OTG_HS device status register) + Object *otg_hs_diepmsk; // 0x10 (OTG_HS device IN endpoint common interrupt mask register) + Object *otg_hs_doepmsk; // 0x14 (OTG_HS device OUT endpoint common interrupt mask register) + Object *otg_hs_daint; // 0x18 (OTG_HS device all endpoints interrupt register) + Object *otg_hs_daintmsk; // 0x1C (OTG_HS all endpoints interrupt mask register) + Object *otg_hs_dvbusdis; // 0x28 (OTG_HS device VBUS discharge time register) + Object *otg_hs_dvbuspulse; // 0x2C (OTG_HS device VBUS pulsing time register) + Object *otg_hs_dthrctl; // 0x30 (OTG_HS Device threshold control register) + Object *otg_hs_diepempmsk; // 0x34 (OTG_HS device IN endpoint FIFO empty interrupt mask register) + Object *otg_hs_deachint; // 0x38 (OTG_HS device each endpoint interrupt register) + Object *otg_hs_deachintmsk; // 0x3C (OTG_HS device each endpoint interrupt register mask) + Object *otg_hs_diepeachmsk1; // 0x40 (OTG_HS device each in endpoint-1 interrupt register) + Object *otg_hs_doepeachmsk1; // 0x80 (OTG_HS device each OUT endpoint-1 interrupt register) + Object *otg_hs_diepctl0; // 0x100 (OTG device endpoint-0 control register) + Object *otg_hs_diepctl1; // 0x120 (OTG device endpoint-1 control register) + Object *otg_hs_diepctl2; // 0x140 (OTG device endpoint-2 control register) + Object *otg_hs_diepctl3; // 0x160 (OTG device endpoint-3 control register) + Object *otg_hs_diepctl4; // 0x180 (OTG device endpoint-4 control register) + Object *otg_hs_diepctl5; // 0x1A0 (OTG device endpoint-5 control register) + Object *otg_hs_diepctl6; // 0x1C0 (OTG device endpoint-6 control register) + Object *otg_hs_diepctl7; // 0x1E0 (OTG device endpoint-7 control register) + Object *otg_hs_diepint0; // 0x108 (OTG device endpoint-0 interrupt register) + Object *otg_hs_diepint1; // 0x128 (OTG device endpoint-1 interrupt register) + Object *otg_hs_diepint2; // 0x148 (OTG device endpoint-2 interrupt register) + Object *otg_hs_diepint3; // 0x168 (OTG device endpoint-3 interrupt register) + Object *otg_hs_diepint4; // 0x188 (OTG device endpoint-4 interrupt register) + Object *otg_hs_diepint5; // 0x1A8 (OTG device endpoint-5 interrupt register) + Object *otg_hs_diepint6; // 0x1C8 (OTG device endpoint-6 interrupt register) + Object *otg_hs_diepint7; // 0x1E8 (OTG device endpoint-7 interrupt register) + Object *otg_hs_dieptsiz0; // 0x110 (OTG_HS device IN endpoint 0 transfer size register) + Object *otg_hs_diepdma1; // 0x114 (OTG_HS device endpoint-1 DMA address register) + Object *otg_hs_diepdma2; // 0x134 (OTG_HS device endpoint-2 DMA address register) + Object *otg_hs_diepdma3; // 0x154 (OTG_HS device endpoint-3 DMA address register) + Object *otg_hs_diepdma4; // 0x174 (OTG_HS device endpoint-4 DMA address register) + Object *otg_hs_diepdma5; // 0x194 (OTG_HS device endpoint-5 DMA address register) + Object *otg_hs_dtxfsts0; // 0x118 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts1; // 0x138 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts2; // 0x158 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts3; // 0x178 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts4; // 0x198 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts5; // 0x1B8 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dieptsiz1; // 0x130 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz2; // 0x150 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz3; // 0x170 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz4; // 0x190 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz5; // 0x1B0 (OTG_HS device endpoint transfer size register) + Object *otg_hs_doepctl0; // 0x300 (OTG_HS device control OUT endpoint 0 control register) + Object *otg_hs_doepctl1; // 0x320 (OTG device endpoint-1 control register) + Object *otg_hs_doepctl2; // 0x340 (OTG device endpoint-2 control register) + Object *otg_hs_doepctl3; // 0x360 (OTG device endpoint-3 control register) + Object *otg_hs_doepint0; // 0x308 (OTG_HS device endpoint-0 interrupt register) + Object *otg_hs_doepint1; // 0x328 (OTG_HS device endpoint-1 interrupt register) + Object *otg_hs_doepint2; // 0x348 (OTG_HS device endpoint-2 interrupt register) + Object *otg_hs_doepint3; // 0x368 (OTG_HS device endpoint-3 interrupt register) + Object *otg_hs_doepint4; // 0x388 (OTG_HS device endpoint-4 interrupt register) + Object *otg_hs_doepint5; // 0x3A8 (OTG_HS device endpoint-5 interrupt register) + Object *otg_hs_doepint6; // 0x3C8 (OTG_HS device endpoint-6 interrupt register) + Object *otg_hs_doepint7; // 0x3E8 (OTG_HS device endpoint-7 interrupt register) + Object *otg_hs_doeptsiz0; // 0x310 (OTG_HS device endpoint-1 transfer size register) + Object *otg_hs_doeptsiz1; // 0x330 (OTG_HS device endpoint-2 transfer size register) + Object *otg_hs_doeptsiz2; // 0x350 (OTG_HS device endpoint-3 transfer size register) + Object *otg_hs_doeptsiz3; // 0x370 (OTG_HS device endpoint-4 transfer size register) + Object *otg_hs_doeptsiz4; // 0x390 (OTG_HS device endpoint-5 transfer size register) + } reg; + + struct { + + // OTG_HS_DCFG (OTG_HS device configuration register) bitfields. + struct { + Object *dspd; // [0:1] Device speed + Object *nzlsohsk; // [2:2] Nonzero-length status OUT handshake + Object *dad; // [4:10] Device address + Object *pfivl; // [11:12] Periodic (micro)frame interval + Object *perschivl; // [24:25] Periodic scheduling interval + } otg_hs_dcfg; + + // OTG_HS_DCTL (OTG_HS device control register) bitfields. + struct { + Object *rwusig; // [0:0] Remote wakeup signaling + Object *sdis; // [1:1] Soft disconnect + Object *ginsts; // [2:2] Global IN NAK status + Object *gonsts; // [3:3] Global OUT NAK status + Object *tctl; // [4:6] Test control + Object *sginak; // [7:7] Set global IN NAK + Object *cginak; // [8:8] Clear global IN NAK + Object *sgonak; // [9:9] Set global OUT NAK + Object *cgonak; // [10:10] Clear global OUT NAK + Object *poprgdne; // [11:11] Power-on programming done + } otg_hs_dctl; + + // OTG_HS_DSTS (OTG_HS device status register) bitfields. + struct { + Object *suspsts; // [0:0] Suspend status + Object *enumspd; // [1:2] Enumerated speed + Object *eerr; // [3:3] Erratic error + Object *fnsof; // [8:21] Frame number of the received SOF + } otg_hs_dsts; + + // OTG_HS_DIEPMSK (OTG_HS device IN endpoint common interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (nonisochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + Object *txfurm; // [8:8] FIFO underrun mask + Object *bim; // [9:9] BNA interrupt mask + } otg_hs_diepmsk; + + // OTG_HS_DOEPMSK (OTG_HS device OUT endpoint common interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *stupm; // [3:3] SETUP phase done mask + Object *otepdm; // [4:4] OUT token received when endpoint disabled mask + Object *b2bstup; // [6:6] Back-to-back SETUP packets received mask + Object *opem; // [8:8] OUT packet error mask + Object *boim; // [9:9] BNA interrupt mask + } otg_hs_doepmsk; + + // OTG_HS_DAINT (OTG_HS device all endpoints interrupt register) bitfields. + struct { + Object *iepint; // [0:15] IN endpoint interrupt bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } otg_hs_daint; + + // OTG_HS_DAINTMSK (OTG_HS all endpoints interrupt mask register) bitfields. + struct { + Object *iepm; // [0:15] IN EP interrupt mask bits + Object *oepm; // [16:31] OUT EP interrupt mask bits + } otg_hs_daintmsk; + + // OTG_HS_DVBUSDIS (OTG_HS device VBUS discharge time register) bitfields. + struct { + Object *vbusdt; // [0:15] Device VBUS discharge time + } otg_hs_dvbusdis; + + // OTG_HS_DVBUSPULSE (OTG_HS device VBUS pulsing time register) bitfields. + struct { + Object *dvbusp; // [0:11] Device VBUS pulsing time + } otg_hs_dvbuspulse; + + // OTG_HS_DTHRCTL (OTG_HS Device threshold control register) bitfields. + struct { + Object *nonisothren; // [0:0] Nonisochronous IN endpoints threshold enable + Object *isothren; // [1:1] ISO IN endpoint threshold enable + Object *txthrlen; // [2:10] Transmit threshold length + Object *rxthren; // [16:16] Receive threshold enable + Object *rxthrlen; // [17:25] Receive threshold length + Object *arpen; // [27:27] Arbiter parking enable + } otg_hs_dthrctl; + + // OTG_HS_DIEPEMPMSK (OTG_HS device IN endpoint FIFO empty interrupt mask register) bitfields. + struct { + Object *ineptxfem; // [0:15] IN EP Tx FIFO empty interrupt mask bits + } otg_hs_diepempmsk; + + // OTG_HS_DEACHINT (OTG_HS device each endpoint interrupt register) bitfields. + struct { + Object *iep1int; // [1:1] IN endpoint 1interrupt bit + Object *oep1int; // [17:17] OUT endpoint 1 interrupt bit + } otg_hs_deachint; + + // OTG_HS_DEACHINTMSK (OTG_HS device each endpoint interrupt register mask) bitfields. + struct { + Object *iep1intm; // [1:1] IN Endpoint 1 interrupt mask bit + Object *oep1intm; // [17:17] OUT Endpoint 1 interrupt mask bit + } otg_hs_deachintmsk; + + // OTG_HS_DIEPEACHMSK1 (OTG_HS device each in endpoint-1 interrupt register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (nonisochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + Object *txfurm; // [8:8] FIFO underrun mask + Object *bim; // [9:9] BNA interrupt mask + Object *nakm; // [13:13] NAK interrupt mask + } otg_hs_diepeachmsk1; + + // OTG_HS_DOEPEACHMSK1 (OTG_HS device each OUT endpoint-1 interrupt register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + Object *txfurm; // [8:8] OUT packet error mask + Object *bim; // [9:9] BNA interrupt mask + Object *berrm; // [12:12] Bubble error interrupt mask + Object *nakm; // [13:13] NAK interrupt mask + Object *nyetm; // [14:14] NYET interrupt mask + } otg_hs_doepeachmsk1; + + // OTG_HS_DIEPCTL0 (OTG device endpoint-0 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl0; + + // OTG_HS_DIEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl1; + + // OTG_HS_DIEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl2; + + // OTG_HS_DIEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl3; + + // OTG_HS_DIEPCTL4 (OTG device endpoint-4 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl4; + + // OTG_HS_DIEPCTL5 (OTG device endpoint-5 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl5; + + // OTG_HS_DIEPCTL6 (OTG device endpoint-6 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl6; + + // OTG_HS_DIEPCTL7 (OTG device endpoint-7 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl7; + + // OTG_HS_DIEPINT0 (OTG device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint0; + + // OTG_HS_DIEPINT1 (OTG device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint1; + + // OTG_HS_DIEPINT2 (OTG device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint2; + + // OTG_HS_DIEPINT3 (OTG device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint3; + + // OTG_HS_DIEPINT4 (OTG device endpoint-4 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint4; + + // OTG_HS_DIEPINT5 (OTG device endpoint-5 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint5; + + // OTG_HS_DIEPINT6 (OTG device endpoint-6 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint6; + + // OTG_HS_DIEPINT7 (OTG device endpoint-7 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint7; + + // OTG_HS_DIEPTSIZ0 (OTG_HS device IN endpoint 0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:20] Packet count + } otg_hs_dieptsiz0; + + // OTG_HS_DIEPDMA1 (OTG_HS device endpoint-1 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma1; + + // OTG_HS_DIEPDMA2 (OTG_HS device endpoint-2 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma2; + + // OTG_HS_DIEPDMA3 (OTG_HS device endpoint-3 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma3; + + // OTG_HS_DIEPDMA4 (OTG_HS device endpoint-4 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma4; + + // OTG_HS_DIEPDMA5 (OTG_HS device endpoint-5 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma5; + + // OTG_HS_DTXFSTS0 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts0; + + // OTG_HS_DTXFSTS1 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts1; + + // OTG_HS_DTXFSTS2 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts2; + + // OTG_HS_DTXFSTS3 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts3; + + // OTG_HS_DTXFSTS4 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts4; + + // OTG_HS_DTXFSTS5 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts5; + + // OTG_HS_DIEPTSIZ1 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz1; + + // OTG_HS_DIEPTSIZ2 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz2; + + // OTG_HS_DIEPTSIZ3 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz3; + + // OTG_HS_DIEPTSIZ4 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz4; + + // OTG_HS_DIEPTSIZ5 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz5; + + // OTG_HS_DOEPCTL0 (OTG_HS device control OUT endpoint 0 control register) bitfields. + struct { + Object *mpsiz; // [0:1] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl0; + + // OTG_HS_DOEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even odd frame/Endpoint data PID + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID/Set even frame + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl1; + + // OTG_HS_DOEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even odd frame/Endpoint data PID + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID/Set even frame + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl2; + + // OTG_HS_DOEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even odd frame/Endpoint data PID + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID/Set even frame + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl3; + + // OTG_HS_DOEPINT0 (OTG_HS device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint0; + + // OTG_HS_DOEPINT1 (OTG_HS device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint1; + + // OTG_HS_DOEPINT2 (OTG_HS device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint2; + + // OTG_HS_DOEPINT3 (OTG_HS device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint3; + + // OTG_HS_DOEPINT4 (OTG_HS device endpoint-4 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint4; + + // OTG_HS_DOEPINT5 (OTG_HS device endpoint-5 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint5; + + // OTG_HS_DOEPINT6 (OTG_HS device endpoint-6 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint6; + + // OTG_HS_DOEPINT7 (OTG_HS device endpoint-7 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint7; + + // OTG_HS_DOEPTSIZ0 (OTG_HS device endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:19] Packet count + Object *stupcnt; // [29:30] SETUP packet count + } otg_hs_doeptsiz0; + + // OTG_HS_DOEPTSIZ1 (OTG_HS device endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz1; + + // OTG_HS_DOEPTSIZ2 (OTG_HS device endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz2; + + // OTG_HS_DOEPTSIZ3 (OTG_HS device endpoint-4 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz3; + + // OTG_HS_DOEPTSIZ4 (OTG_HS device endpoint-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz4; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_DEVICEState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_DEVICE_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_global.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_global.c new file mode 100644 index 0000000000..1cfbf9a42f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_global.c @@ -0,0 +1,457 @@ +/* + * STM32 - OTG_HS_GLOBAL (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_hs_global_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_gotgctl = cm_object_get_child_by_name(obj, "OTG_HS_GOTGCTL"); + state->u.f4.reg.otg_hs_gotgint = cm_object_get_child_by_name(obj, "OTG_HS_GOTGINT"); + state->u.f4.reg.otg_hs_gahbcfg = cm_object_get_child_by_name(obj, "OTG_HS_GAHBCFG"); + state->u.f4.reg.otg_hs_gusbcfg = cm_object_get_child_by_name(obj, "OTG_HS_GUSBCFG"); + state->u.f4.reg.otg_hs_grstctl = cm_object_get_child_by_name(obj, "OTG_HS_GRSTCTL"); + state->u.f4.reg.otg_hs_gintsts = cm_object_get_child_by_name(obj, "OTG_HS_GINTSTS"); + state->u.f4.reg.otg_hs_gintmsk = cm_object_get_child_by_name(obj, "OTG_HS_GINTMSK"); + state->u.f4.reg.otg_hs_grxstsr_host = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSR_Host"); + state->u.f4.reg.otg_hs_grxstsp_host = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSP_Host"); + state->u.f4.reg.otg_hs_grxfsiz = cm_object_get_child_by_name(obj, "OTG_HS_GRXFSIZ"); + state->u.f4.reg.otg_hs_gnptxfsiz_host = cm_object_get_child_by_name(obj, "OTG_HS_GNPTXFSIZ_Host"); + state->u.f4.reg.otg_hs_tx0fsiz_peripheral = cm_object_get_child_by_name(obj, "OTG_HS_TX0FSIZ_Peripheral"); + state->u.f4.reg.otg_hs_gnptxsts = cm_object_get_child_by_name(obj, "OTG_HS_GNPTXSTS"); + state->u.f4.reg.otg_hs_gccfg = cm_object_get_child_by_name(obj, "OTG_HS_GCCFG"); + state->u.f4.reg.otg_hs_cid = cm_object_get_child_by_name(obj, "OTG_HS_CID"); + state->u.f4.reg.otg_hs_hptxfsiz = cm_object_get_child_by_name(obj, "OTG_HS_HPTXFSIZ"); + state->u.f4.reg.otg_hs_dieptxf1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF1"); + state->u.f4.reg.otg_hs_dieptxf2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF2"); + state->u.f4.reg.otg_hs_dieptxf3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF3"); + state->u.f4.reg.otg_hs_dieptxf4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF4"); + state->u.f4.reg.otg_hs_dieptxf5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF5"); + state->u.f4.reg.otg_hs_dieptxf6 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF6"); + state->u.f4.reg.otg_hs_dieptxf7 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF7"); + state->u.f4.reg.otg_hs_grxstsr_peripheral = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSR_Peripheral"); + state->u.f4.reg.otg_hs_grxstsp_peripheral = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSP_Peripheral"); + + + // OTG_HS_GOTGCTL bitfields. + state->u.f4.fld.otg_hs_gotgctl.srqscs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "SRQSCS"); + state->u.f4.fld.otg_hs_gotgctl.srq = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "SRQ"); + state->u.f4.fld.otg_hs_gotgctl.hngscs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "HNGSCS"); + state->u.f4.fld.otg_hs_gotgctl.hnprq = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "HNPRQ"); + state->u.f4.fld.otg_hs_gotgctl.hshnpen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "HSHNPEN"); + state->u.f4.fld.otg_hs_gotgctl.dhnpen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "DHNPEN"); + state->u.f4.fld.otg_hs_gotgctl.cidsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "CIDSTS"); + state->u.f4.fld.otg_hs_gotgctl.dbct = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "DBCT"); + state->u.f4.fld.otg_hs_gotgctl.asvld = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "ASVLD"); + state->u.f4.fld.otg_hs_gotgctl.bsvld = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "BSVLD"); + + // OTG_HS_GOTGINT bitfields. + state->u.f4.fld.otg_hs_gotgint.sedet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "SEDET"); + state->u.f4.fld.otg_hs_gotgint.srsschg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "SRSSCHG"); + state->u.f4.fld.otg_hs_gotgint.hnsschg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "HNSSCHG"); + state->u.f4.fld.otg_hs_gotgint.hngdet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "HNGDET"); + state->u.f4.fld.otg_hs_gotgint.adtochg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "ADTOCHG"); + state->u.f4.fld.otg_hs_gotgint.dbcdne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "DBCDNE"); + + // OTG_HS_GAHBCFG bitfields. + state->u.f4.fld.otg_hs_gahbcfg.gint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "GINT"); + state->u.f4.fld.otg_hs_gahbcfg.hbstlen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "HBSTLEN"); + state->u.f4.fld.otg_hs_gahbcfg.dmaen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "DMAEN"); + state->u.f4.fld.otg_hs_gahbcfg.txfelvl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "TXFELVL"); + state->u.f4.fld.otg_hs_gahbcfg.ptxfelvl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "PTXFELVL"); + + // OTG_HS_GUSBCFG bitfields. + state->u.f4.fld.otg_hs_gusbcfg.tocal = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "TOCAL"); + state->u.f4.fld.otg_hs_gusbcfg.physel = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PHYSEL"); + state->u.f4.fld.otg_hs_gusbcfg.srpcap = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "SRPCAP"); + state->u.f4.fld.otg_hs_gusbcfg.hnpcap = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "HNPCAP"); + state->u.f4.fld.otg_hs_gusbcfg.trdt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "TRDT"); + state->u.f4.fld.otg_hs_gusbcfg.phylpcs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PHYLPCS"); + state->u.f4.fld.otg_hs_gusbcfg.ulpifsls = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIFSLS"); + state->u.f4.fld.otg_hs_gusbcfg.ulpiar = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIAR"); + state->u.f4.fld.otg_hs_gusbcfg.ulpicsm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPICSM"); + state->u.f4.fld.otg_hs_gusbcfg.ulpievbusd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIEVBUSD"); + state->u.f4.fld.otg_hs_gusbcfg.ulpievbusi = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIEVBUSI"); + state->u.f4.fld.otg_hs_gusbcfg.tsdps = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "TSDPS"); + state->u.f4.fld.otg_hs_gusbcfg.pcci = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PCCI"); + state->u.f4.fld.otg_hs_gusbcfg.ptci = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PTCI"); + state->u.f4.fld.otg_hs_gusbcfg.ulpiipd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIIPD"); + state->u.f4.fld.otg_hs_gusbcfg.fhmod = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "FHMOD"); + state->u.f4.fld.otg_hs_gusbcfg.fdmod = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "FDMOD"); + state->u.f4.fld.otg_hs_gusbcfg.ctxpkt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "CTXPKT"); + + // OTG_HS_GRSTCTL bitfields. + state->u.f4.fld.otg_hs_grstctl.csrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "CSRST"); + state->u.f4.fld.otg_hs_grstctl.hsrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "HSRST"); + state->u.f4.fld.otg_hs_grstctl.fcrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "FCRST"); + state->u.f4.fld.otg_hs_grstctl.rxfflsh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "RXFFLSH"); + state->u.f4.fld.otg_hs_grstctl.txfflsh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "TXFFLSH"); + state->u.f4.fld.otg_hs_grstctl.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "TXFNUM"); + state->u.f4.fld.otg_hs_grstctl.dmareq = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "DMAREQ"); + state->u.f4.fld.otg_hs_grstctl.ahbidl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "AHBIDL"); + + // OTG_HS_GINTSTS bitfields. + state->u.f4.fld.otg_hs_gintsts.cmod = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "CMOD"); + state->u.f4.fld.otg_hs_gintsts.mmis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "MMIS"); + state->u.f4.fld.otg_hs_gintsts.otgint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "OTGINT"); + state->u.f4.fld.otg_hs_gintsts.sof = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "SOF"); + state->u.f4.fld.otg_hs_gintsts.rxflvl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "RXFLVL"); + state->u.f4.fld.otg_hs_gintsts.nptxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "NPTXFE"); + state->u.f4.fld.otg_hs_gintsts.ginakeff = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "GINAKEFF"); + state->u.f4.fld.otg_hs_gintsts.boutnakeff = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "BOUTNAKEFF"); + state->u.f4.fld.otg_hs_gintsts.esusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "ESUSP"); + state->u.f4.fld.otg_hs_gintsts.usbsusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "USBSUSP"); + state->u.f4.fld.otg_hs_gintsts.usbrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "USBRST"); + state->u.f4.fld.otg_hs_gintsts.enumdne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "ENUMDNE"); + state->u.f4.fld.otg_hs_gintsts.isoodrp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "ISOODRP"); + state->u.f4.fld.otg_hs_gintsts.eopf = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "EOPF"); + state->u.f4.fld.otg_hs_gintsts.iepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "IEPINT"); + state->u.f4.fld.otg_hs_gintsts.oepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "OEPINT"); + state->u.f4.fld.otg_hs_gintsts.iisoixfr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "IISOIXFR"); + state->u.f4.fld.otg_hs_gintsts.pxfr_incompisoout = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "PXFR_INCOMPISOOUT"); + state->u.f4.fld.otg_hs_gintsts.datafsusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "DATAFSUSP"); + state->u.f4.fld.otg_hs_gintsts.hprtint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "HPRTINT"); + state->u.f4.fld.otg_hs_gintsts.hcint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "HCINT"); + state->u.f4.fld.otg_hs_gintsts.ptxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "PTXFE"); + state->u.f4.fld.otg_hs_gintsts.cidschg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "CIDSCHG"); + state->u.f4.fld.otg_hs_gintsts.discint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "DISCINT"); + state->u.f4.fld.otg_hs_gintsts.srqint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "SRQINT"); + state->u.f4.fld.otg_hs_gintsts.wkuint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "WKUINT"); + + // OTG_HS_GINTMSK bitfields. + state->u.f4.fld.otg_hs_gintmsk.mmism = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "MMISM"); + state->u.f4.fld.otg_hs_gintmsk.otgint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "OTGINT"); + state->u.f4.fld.otg_hs_gintmsk.sofm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "SOFM"); + state->u.f4.fld.otg_hs_gintmsk.rxflvlm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "RXFLVLM"); + state->u.f4.fld.otg_hs_gintmsk.nptxfem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "NPTXFEM"); + state->u.f4.fld.otg_hs_gintmsk.ginakeffm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "GINAKEFFM"); + state->u.f4.fld.otg_hs_gintmsk.gonakeffm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "GONAKEFFM"); + state->u.f4.fld.otg_hs_gintmsk.esuspm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "ESUSPM"); + state->u.f4.fld.otg_hs_gintmsk.usbsuspm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "USBSUSPM"); + state->u.f4.fld.otg_hs_gintmsk.usbrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "USBRST"); + state->u.f4.fld.otg_hs_gintmsk.enumdnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "ENUMDNEM"); + state->u.f4.fld.otg_hs_gintmsk.isoodrpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "ISOODRPM"); + state->u.f4.fld.otg_hs_gintmsk.eopfm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "EOPFM"); + state->u.f4.fld.otg_hs_gintmsk.epmism = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "EPMISM"); + state->u.f4.fld.otg_hs_gintmsk.iepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "IEPINT"); + state->u.f4.fld.otg_hs_gintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "OEPINT"); + state->u.f4.fld.otg_hs_gintmsk.iisoixfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "IISOIXFRM"); + state->u.f4.fld.otg_hs_gintmsk.pxfrm_iisooxfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "PXFRM_IISOOXFRM"); + state->u.f4.fld.otg_hs_gintmsk.fsuspm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "FSUSPM"); + state->u.f4.fld.otg_hs_gintmsk.prtim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "PRTIM"); + state->u.f4.fld.otg_hs_gintmsk.hcim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "HCIM"); + state->u.f4.fld.otg_hs_gintmsk.ptxfem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "PTXFEM"); + state->u.f4.fld.otg_hs_gintmsk.cidschgm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "CIDSCHGM"); + state->u.f4.fld.otg_hs_gintmsk.discint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "DISCINT"); + state->u.f4.fld.otg_hs_gintmsk.srqim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "SRQIM"); + state->u.f4.fld.otg_hs_gintmsk.wuim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "WUIM"); + + // OTG_HS_GRXSTSR_Host bitfields. + state->u.f4.fld.otg_hs_grxstsr_host.chnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "CHNUM"); + state->u.f4.fld.otg_hs_grxstsr_host.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "BCNT"); + state->u.f4.fld.otg_hs_grxstsr_host.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "DPID"); + state->u.f4.fld.otg_hs_grxstsr_host.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "PKTSTS"); + + // OTG_HS_GRXSTSP_Host bitfields. + state->u.f4.fld.otg_hs_grxstsp_host.chnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "CHNUM"); + state->u.f4.fld.otg_hs_grxstsp_host.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "BCNT"); + state->u.f4.fld.otg_hs_grxstsp_host.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "DPID"); + state->u.f4.fld.otg_hs_grxstsp_host.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "PKTSTS"); + + // OTG_HS_GRXFSIZ bitfields. + state->u.f4.fld.otg_hs_grxfsiz.rxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxfsiz, "RXFD"); + + // OTG_HS_GNPTXFSIZ_Host bitfields. + state->u.f4.fld.otg_hs_gnptxfsiz_host.nptxfsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxfsiz_host, "NPTXFSA"); + state->u.f4.fld.otg_hs_gnptxfsiz_host.nptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxfsiz_host, "NPTXFD"); + + // OTG_HS_TX0FSIZ_Peripheral bitfields. + state->u.f4.fld.otg_hs_tx0fsiz_peripheral.tx0fsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_tx0fsiz_peripheral, "TX0FSA"); + state->u.f4.fld.otg_hs_tx0fsiz_peripheral.tx0fd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_tx0fsiz_peripheral, "TX0FD"); + + // OTG_HS_GNPTXSTS bitfields. + state->u.f4.fld.otg_hs_gnptxsts.nptxfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxsts, "NPTXFSAV"); + state->u.f4.fld.otg_hs_gnptxsts.nptqxsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxsts, "NPTQXSAV"); + state->u.f4.fld.otg_hs_gnptxsts.nptxqtop = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxsts, "NPTXQTOP"); + + // OTG_HS_GCCFG bitfields. + state->u.f4.fld.otg_hs_gccfg.pwrdwn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "PWRDWN"); + state->u.f4.fld.otg_hs_gccfg.i2cpaden = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "I2CPADEN"); + state->u.f4.fld.otg_hs_gccfg.vbusasen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "VBUSASEN"); + state->u.f4.fld.otg_hs_gccfg.vbusbsen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "VBUSBSEN"); + state->u.f4.fld.otg_hs_gccfg.sofouten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "SOFOUTEN"); + state->u.f4.fld.otg_hs_gccfg.novbussens = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "NOVBUSSENS"); + + // OTG_HS_CID bitfields. + state->u.f4.fld.otg_hs_cid.product_id = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_cid, "PRODUCT_ID"); + + // OTG_HS_HPTXFSIZ bitfields. + state->u.f4.fld.otg_hs_hptxfsiz.ptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxfsiz, "PTXSA"); + state->u.f4.fld.otg_hs_hptxfsiz.ptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxfsiz, "PTXFD"); + + // OTG_HS_DIEPTXF1 bitfields. + state->u.f4.fld.otg_hs_dieptxf1.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf1, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf1.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf1, "INEPTXFD"); + + // OTG_HS_DIEPTXF2 bitfields. + state->u.f4.fld.otg_hs_dieptxf2.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf2, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf2.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf2, "INEPTXFD"); + + // OTG_HS_DIEPTXF3 bitfields. + state->u.f4.fld.otg_hs_dieptxf3.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf3, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf3.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf3, "INEPTXFD"); + + // OTG_HS_DIEPTXF4 bitfields. + state->u.f4.fld.otg_hs_dieptxf4.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf4, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf4.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf4, "INEPTXFD"); + + // OTG_HS_DIEPTXF5 bitfields. + state->u.f4.fld.otg_hs_dieptxf5.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf5, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf5.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf5, "INEPTXFD"); + + // OTG_HS_DIEPTXF6 bitfields. + state->u.f4.fld.otg_hs_dieptxf6.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf6, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf6.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf6, "INEPTXFD"); + + // OTG_HS_DIEPTXF7 bitfields. + state->u.f4.fld.otg_hs_dieptxf7.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf7, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf7.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf7, "INEPTXFD"); + + // OTG_HS_GRXSTSR_Peripheral bitfields. + state->u.f4.fld.otg_hs_grxstsr_peripheral.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "EPNUM"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "BCNT"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "DPID"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "PKTSTS"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.frmnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "FRMNUM"); + + // OTG_HS_GRXSTSP_Peripheral bitfields. + state->u.f4.fld.otg_hs_grxstsp_peripheral.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "EPNUM"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "BCNT"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "DPID"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "PKTSTS"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.frmnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "FRMNUM"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_global_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_global_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_global_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_global_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_global_is_enabled(Object *obj) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_global_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_global_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_GLOBAL)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_GLOBAL"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_hs_global_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_GLOBALEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_global_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_GLOBAL); +} + +static void stm32_otg_hs_global_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_global_reset_callback; + dc->realize = stm32_otg_hs_global_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_global_is_enabled; +} + +static const TypeInfo stm32_otg_hs_global_type_info = { + .name = TYPE_STM32_OTG_HS_GLOBAL, + .parent = TYPE_STM32_OTG_HS_GLOBAL_PARENT, + .instance_init = stm32_otg_hs_global_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_GLOBALState), + .class_init = stm32_otg_hs_global_class_init_callback, + .class_size = sizeof(STM32OTG_HS_GLOBALClass) }; + +static void stm32_otg_hs_global_register_types(void) +{ + type_register_static(&stm32_otg_hs_global_type_info); +} + +type_init(stm32_otg_hs_global_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_global.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_global.h new file mode 100644 index 0000000000..0af67faafd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_global.h @@ -0,0 +1,372 @@ +/* + * STM32 - OTG_HS_GLOBAL (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_GLOBAL_H_ +#define STM32_OTG_HS_GLOBAL_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_GLOBAL DEVICE_PATH_STM32 "OTG_HS_GLOBAL" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_GLOBAL TYPE_STM32_PREFIX "otg_hs_global" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_GLOBAL_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_GLOBALParentClass; +typedef PeripheralState STM32OTG_HS_GLOBALParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_GLOBAL_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_GLOBALClass, (obj), TYPE_STM32_OTG_HS_GLOBAL) +#define STM32_OTG_HS_GLOBAL_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_GLOBALClass, (klass), TYPE_STM32_OTG_HS_GLOBAL) + +typedef struct { + // private: + STM32OTG_HS_GLOBALParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_GLOBALClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_GLOBAL_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_GLOBALState, (obj), TYPE_STM32_OTG_HS_GLOBAL) + +typedef struct { + // private: + STM32OTG_HS_GLOBALParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_GLOBAL (USB on the go high speed) registers. + struct { + Object *otg_hs_gotgctl; // 0x0 (OTG_HS control and status register) + Object *otg_hs_gotgint; // 0x4 (OTG_HS interrupt register) + Object *otg_hs_gahbcfg; // 0x8 (OTG_HS AHB configuration register) + Object *otg_hs_gusbcfg; // 0xC (OTG_HS USB configuration register) + Object *otg_hs_grstctl; // 0x10 (OTG_HS reset register) + Object *otg_hs_gintsts; // 0x14 (OTG_HS core interrupt register) + Object *otg_hs_gintmsk; // 0x18 (OTG_HS interrupt mask register) + Object *otg_hs_grxstsr_host; // 0x1C (OTG_HS Receive status debug read register (host mode)) + Object *otg_hs_grxstsp_host; // 0x20 (OTG_HS status read and pop register (host mode)) + Object *otg_hs_grxfsiz; // 0x24 (OTG_HS Receive FIFO size register) + Object *otg_hs_gnptxfsiz_host; // 0x28 (OTG_HS nonperiodic transmit FIFO size register (host mode)) + Object *otg_hs_tx0fsiz_peripheral; // 0x28 (Endpoint 0 transmit FIFO size (peripheral mode)) + Object *otg_hs_gnptxsts; // 0x2C (OTG_HS nonperiodic transmit FIFO/queue status register) + Object *otg_hs_gccfg; // 0x38 (OTG_HS general core configuration register) + Object *otg_hs_cid; // 0x3C (OTG_HS core ID register) + Object *otg_hs_hptxfsiz; // 0x100 (OTG_HS Host periodic transmit FIFO size register) + Object *otg_hs_dieptxf1; // 0x104 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf2; // 0x108 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf3; // 0x11C (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf4; // 0x120 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf5; // 0x124 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf6; // 0x128 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf7; // 0x12C (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_grxstsr_peripheral; // 0x1C (OTG_HS Receive status debug read register (peripheral mode mode)) + Object *otg_hs_grxstsp_peripheral; // 0x20 (OTG_HS status read and pop register (peripheral mode)) + } reg; + + struct { + + // OTG_HS_GOTGCTL (OTG_HS control and status register) bitfields. + struct { + Object *srqscs; // [0:0] Session request success + Object *srq; // [1:1] Session request + Object *hngscs; // [8:8] Host negotiation success + Object *hnprq; // [9:9] HNP request + Object *hshnpen; // [10:10] Host set HNP enable + Object *dhnpen; // [11:11] Device HNP enabled + Object *cidsts; // [16:16] Connector ID status + Object *dbct; // [17:17] Long/short debounce time + Object *asvld; // [18:18] A-session valid + Object *bsvld; // [19:19] B-session valid + } otg_hs_gotgctl; + + // OTG_HS_GOTGINT (OTG_HS interrupt register) bitfields. + struct { + Object *sedet; // [2:2] Session end detected + Object *srsschg; // [8:8] Session request success status change + Object *hnsschg; // [9:9] Host negotiation success status change + Object *hngdet; // [17:17] Host negotiation detected + Object *adtochg; // [18:18] A-device timeout change + Object *dbcdne; // [19:19] Debounce done + } otg_hs_gotgint; + + // OTG_HS_GAHBCFG (OTG_HS AHB configuration register) bitfields. + struct { + Object *gint; // [0:0] Global interrupt mask + Object *hbstlen; // [1:4] Burst length/type + Object *dmaen; // [5:5] DMA enable + Object *txfelvl; // [7:7] TxFIFO empty level + Object *ptxfelvl; // [8:8] Periodic TxFIFO empty level + } otg_hs_gahbcfg; + + // OTG_HS_GUSBCFG (OTG_HS USB configuration register) bitfields. + struct { + Object *tocal; // [0:2] FS timeout calibration + Object *physel; // [6:6] USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select + Object *srpcap; // [8:8] SRP-capable + Object *hnpcap; // [9:9] HNP-capable + Object *trdt; // [10:13] USB turnaround time + Object *phylpcs; // [15:15] PHY Low-power clock select + Object *ulpifsls; // [17:17] ULPI FS/LS select + Object *ulpiar; // [18:18] ULPI Auto-resume + Object *ulpicsm; // [19:19] ULPI Clock SuspendM + Object *ulpievbusd; // [20:20] ULPI External VBUS Drive + Object *ulpievbusi; // [21:21] ULPI external VBUS indicator + Object *tsdps; // [22:22] TermSel DLine pulsing selection + Object *pcci; // [23:23] Indicator complement + Object *ptci; // [24:24] Indicator pass through + Object *ulpiipd; // [25:25] ULPI interface protect disable + Object *fhmod; // [29:29] Forced host mode + Object *fdmod; // [30:30] Forced peripheral mode + Object *ctxpkt; // [31:31] Corrupt Tx packet + } otg_hs_gusbcfg; + + // OTG_HS_GRSTCTL (OTG_HS reset register) bitfields. + struct { + Object *csrst; // [0:0] Core soft reset + Object *hsrst; // [1:1] HCLK soft reset + Object *fcrst; // [2:2] Host frame counter reset + Object *rxfflsh; // [4:4] RxFIFO flush + Object *txfflsh; // [5:5] TxFIFO flush + Object *txfnum; // [6:10] TxFIFO number + Object *dmareq; // [30:30] DMA request signal + Object *ahbidl; // [31:31] AHB master idle + } otg_hs_grstctl; + + // OTG_HS_GINTSTS (OTG_HS core interrupt register) bitfields. + struct { + Object *cmod; // [0:0] Current mode of operation + Object *mmis; // [1:1] Mode mismatch interrupt + Object *otgint; // [2:2] OTG interrupt + Object *sof; // [3:3] Start of frame + Object *rxflvl; // [4:4] RxFIFO nonempty + Object *nptxfe; // [5:5] Nonperiodic TxFIFO empty + Object *ginakeff; // [6:6] Global IN nonperiodic NAK effective + Object *boutnakeff; // [7:7] Global OUT NAK effective + Object *esusp; // [10:10] Early suspend + Object *usbsusp; // [11:11] USB suspend + Object *usbrst; // [12:12] USB reset + Object *enumdne; // [13:13] Enumeration done + Object *isoodrp; // [14:14] Isochronous OUT packet dropped interrupt + Object *eopf; // [15:15] End of periodic frame interrupt + Object *iepint; // [18:18] IN endpoint interrupt + Object *oepint; // [19:19] OUT endpoint interrupt + Object *iisoixfr; // [20:20] Incomplete isochronous IN transfer + Object *pxfr_incompisoout; // [21:21] Incomplete periodic transfer + Object *datafsusp; // [22:22] Data fetch suspended + Object *hprtint; // [24:24] Host port interrupt + Object *hcint; // [25:25] Host channels interrupt + Object *ptxfe; // [26:26] Periodic TxFIFO empty + Object *cidschg; // [28:28] Connector ID status change + Object *discint; // [29:29] Disconnect detected interrupt + Object *srqint; // [30:30] Session request/new session detected interrupt + Object *wkuint; // [31:31] Resume/remote wakeup detected interrupt + } otg_hs_gintsts; + + // OTG_HS_GINTMSK (OTG_HS interrupt mask register) bitfields. + struct { + Object *mmism; // [1:1] Mode mismatch interrupt mask + Object *otgint; // [2:2] OTG interrupt mask + Object *sofm; // [3:3] Start of frame mask + Object *rxflvlm; // [4:4] Receive FIFO nonempty mask + Object *nptxfem; // [5:5] Nonperiodic TxFIFO empty mask + Object *ginakeffm; // [6:6] Global nonperiodic IN NAK effective mask + Object *gonakeffm; // [7:7] Global OUT NAK effective mask + Object *esuspm; // [10:10] Early suspend mask + Object *usbsuspm; // [11:11] USB suspend mask + Object *usbrst; // [12:12] USB reset mask + Object *enumdnem; // [13:13] Enumeration done mask + Object *isoodrpm; // [14:14] Isochronous OUT packet dropped interrupt mask + Object *eopfm; // [15:15] End of periodic frame interrupt mask + Object *epmism; // [17:17] Endpoint mismatch interrupt mask + Object *iepint; // [18:18] IN endpoints interrupt mask + Object *oepint; // [19:19] OUT endpoints interrupt mask + Object *iisoixfrm; // [20:20] Incomplete isochronous IN transfer mask + Object *pxfrm_iisooxfrm; // [21:21] Incomplete periodic transfer mask + Object *fsuspm; // [22:22] Data fetch suspended mask + Object *prtim; // [24:24] Host port interrupt mask + Object *hcim; // [25:25] Host channels interrupt mask + Object *ptxfem; // [26:26] Periodic TxFIFO empty mask + Object *cidschgm; // [28:28] Connector ID status change mask + Object *discint; // [29:29] Disconnect detected interrupt mask + Object *srqim; // [30:30] Session request/new session detected interrupt mask + Object *wuim; // [31:31] Resume/remote wakeup detected interrupt mask + } otg_hs_gintmsk; + + // OTG_HS_GRXSTSR_Host (OTG_HS Receive status debug read register (host mode)) bitfields. + struct { + Object *chnum; // [0:3] Channel number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + } otg_hs_grxstsr_host; + + // OTG_HS_GRXSTSP_Host (OTG_HS status read and pop register (host mode)) bitfields. + struct { + Object *chnum; // [0:3] Channel number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + } otg_hs_grxstsp_host; + + // OTG_HS_GRXFSIZ (OTG_HS Receive FIFO size register) bitfields. + struct { + Object *rxfd; // [0:15] RxFIFO depth + } otg_hs_grxfsiz; + + // OTG_HS_GNPTXFSIZ_Host (OTG_HS nonperiodic transmit FIFO size register (host mode)) bitfields. + struct { + Object *nptxfsa; // [0:15] Nonperiodic transmit RAM start address + Object *nptxfd; // [16:31] Nonperiodic TxFIFO depth + } otg_hs_gnptxfsiz_host; + + // OTG_HS_TX0FSIZ_Peripheral (Endpoint 0 transmit FIFO size (peripheral mode)) bitfields. + struct { + Object *tx0fsa; // [0:15] Endpoint 0 transmit RAM start address + Object *tx0fd; // [16:31] Endpoint 0 TxFIFO depth + } otg_hs_tx0fsiz_peripheral; + + // OTG_HS_GNPTXSTS (OTG_HS nonperiodic transmit FIFO/queue status register) bitfields. + struct { + Object *nptxfsav; // [0:15] Nonperiodic TxFIFO space available + Object *nptqxsav; // [16:23] Nonperiodic transmit request queue space available + Object *nptxqtop; // [24:30] Top of the nonperiodic transmit request queue + } otg_hs_gnptxsts; + + // OTG_HS_GCCFG (OTG_HS general core configuration register) bitfields. + struct { + Object *pwrdwn; // [16:16] Power down + Object *i2cpaden; // [17:17] Enable I2C bus connection for the external I2C PHY interface + Object *vbusasen; // [18:18] Enable the VBUS sensing device + Object *vbusbsen; // [19:19] Enable the VBUS sensing device + Object *sofouten; // [20:20] SOF output enable + Object *novbussens; // [21:21] VBUS sensing disable option + } otg_hs_gccfg; + + // OTG_HS_CID (OTG_HS core ID register) bitfields. + struct { + Object *product_id; // [0:31] Product ID field + } otg_hs_cid; + + // OTG_HS_HPTXFSIZ (OTG_HS Host periodic transmit FIFO size register) bitfields. + struct { + Object *ptxsa; // [0:15] Host periodic TxFIFO start address + Object *ptxfd; // [16:31] Host periodic TxFIFO depth + } otg_hs_hptxfsiz; + + // OTG_HS_DIEPTXF1 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf1; + + // OTG_HS_DIEPTXF2 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf2; + + // OTG_HS_DIEPTXF3 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf3; + + // OTG_HS_DIEPTXF4 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf4; + + // OTG_HS_DIEPTXF5 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf5; + + // OTG_HS_DIEPTXF6 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf6; + + // OTG_HS_DIEPTXF7 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf7; + + // OTG_HS_GRXSTSR_Peripheral (OTG_HS Receive status debug read register (peripheral mode mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } otg_hs_grxstsr_peripheral; + + // OTG_HS_GRXSTSP_Peripheral (OTG_HS status read and pop register (peripheral mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } otg_hs_grxstsp_peripheral; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_GLOBALState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_GLOBAL_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_host.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_host.c new file mode 100644 index 0000000000..ec5987e519 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_host.c @@ -0,0 +1,986 @@ +/* + * STM32 - OTG_HS_HOST (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_hs_host_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_hcfg = cm_object_get_child_by_name(obj, "OTG_HS_HCFG"); + state->u.f4.reg.otg_hs_hfir = cm_object_get_child_by_name(obj, "OTG_HS_HFIR"); + state->u.f4.reg.otg_hs_hfnum = cm_object_get_child_by_name(obj, "OTG_HS_HFNUM"); + state->u.f4.reg.otg_hs_hptxsts = cm_object_get_child_by_name(obj, "OTG_HS_HPTXSTS"); + state->u.f4.reg.otg_hs_haint = cm_object_get_child_by_name(obj, "OTG_HS_HAINT"); + state->u.f4.reg.otg_hs_haintmsk = cm_object_get_child_by_name(obj, "OTG_HS_HAINTMSK"); + state->u.f4.reg.otg_hs_hprt = cm_object_get_child_by_name(obj, "OTG_HS_HPRT"); + state->u.f4.reg.otg_hs_hcchar0 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR0"); + state->u.f4.reg.otg_hs_hcchar1 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR1"); + state->u.f4.reg.otg_hs_hcchar2 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR2"); + state->u.f4.reg.otg_hs_hcchar3 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR3"); + state->u.f4.reg.otg_hs_hcchar4 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR4"); + state->u.f4.reg.otg_hs_hcchar5 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR5"); + state->u.f4.reg.otg_hs_hcchar6 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR6"); + state->u.f4.reg.otg_hs_hcchar7 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR7"); + state->u.f4.reg.otg_hs_hcchar8 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR8"); + state->u.f4.reg.otg_hs_hcchar9 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR9"); + state->u.f4.reg.otg_hs_hcchar10 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR10"); + state->u.f4.reg.otg_hs_hcchar11 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR11"); + state->u.f4.reg.otg_hs_hcsplt0 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT0"); + state->u.f4.reg.otg_hs_hcsplt1 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT1"); + state->u.f4.reg.otg_hs_hcsplt2 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT2"); + state->u.f4.reg.otg_hs_hcsplt3 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT3"); + state->u.f4.reg.otg_hs_hcsplt4 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT4"); + state->u.f4.reg.otg_hs_hcsplt5 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT5"); + state->u.f4.reg.otg_hs_hcsplt6 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT6"); + state->u.f4.reg.otg_hs_hcsplt7 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT7"); + state->u.f4.reg.otg_hs_hcsplt8 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT8"); + state->u.f4.reg.otg_hs_hcsplt9 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT9"); + state->u.f4.reg.otg_hs_hcsplt10 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT10"); + state->u.f4.reg.otg_hs_hcsplt11 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT11"); + state->u.f4.reg.otg_hs_hcint0 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT0"); + state->u.f4.reg.otg_hs_hcint1 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT1"); + state->u.f4.reg.otg_hs_hcint2 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT2"); + state->u.f4.reg.otg_hs_hcint3 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT3"); + state->u.f4.reg.otg_hs_hcint4 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT4"); + state->u.f4.reg.otg_hs_hcint5 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT5"); + state->u.f4.reg.otg_hs_hcint6 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT6"); + state->u.f4.reg.otg_hs_hcint7 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT7"); + state->u.f4.reg.otg_hs_hcint8 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT8"); + state->u.f4.reg.otg_hs_hcint9 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT9"); + state->u.f4.reg.otg_hs_hcint10 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT10"); + state->u.f4.reg.otg_hs_hcint11 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT11"); + state->u.f4.reg.otg_hs_hcintmsk0 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK0"); + state->u.f4.reg.otg_hs_hcintmsk1 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK1"); + state->u.f4.reg.otg_hs_hcintmsk2 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK2"); + state->u.f4.reg.otg_hs_hcintmsk3 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK3"); + state->u.f4.reg.otg_hs_hcintmsk4 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK4"); + state->u.f4.reg.otg_hs_hcintmsk5 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK5"); + state->u.f4.reg.otg_hs_hcintmsk6 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK6"); + state->u.f4.reg.otg_hs_hcintmsk7 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK7"); + state->u.f4.reg.otg_hs_hcintmsk8 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK8"); + state->u.f4.reg.otg_hs_hcintmsk9 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK9"); + state->u.f4.reg.otg_hs_hcintmsk10 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK10"); + state->u.f4.reg.otg_hs_hcintmsk11 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK11"); + state->u.f4.reg.otg_hs_hctsiz0 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ0"); + state->u.f4.reg.otg_hs_hctsiz1 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ1"); + state->u.f4.reg.otg_hs_hctsiz2 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ2"); + state->u.f4.reg.otg_hs_hctsiz3 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ3"); + state->u.f4.reg.otg_hs_hctsiz4 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ4"); + state->u.f4.reg.otg_hs_hctsiz5 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ5"); + state->u.f4.reg.otg_hs_hctsiz6 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ6"); + state->u.f4.reg.otg_hs_hctsiz7 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ7"); + state->u.f4.reg.otg_hs_hctsiz8 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ8"); + state->u.f4.reg.otg_hs_hctsiz9 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ9"); + state->u.f4.reg.otg_hs_hctsiz10 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ10"); + state->u.f4.reg.otg_hs_hctsiz11 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ11"); + state->u.f4.reg.otg_hs_hcdma0 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA0"); + state->u.f4.reg.otg_hs_hcdma1 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA1"); + state->u.f4.reg.otg_hs_hcdma2 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA2"); + state->u.f4.reg.otg_hs_hcdma3 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA3"); + state->u.f4.reg.otg_hs_hcdma4 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA4"); + state->u.f4.reg.otg_hs_hcdma5 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA5"); + state->u.f4.reg.otg_hs_hcdma6 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA6"); + state->u.f4.reg.otg_hs_hcdma7 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA7"); + state->u.f4.reg.otg_hs_hcdma8 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA8"); + state->u.f4.reg.otg_hs_hcdma9 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA9"); + state->u.f4.reg.otg_hs_hcdma10 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA10"); + state->u.f4.reg.otg_hs_hcdma11 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA11"); + + + // OTG_HS_HCFG bitfields. + state->u.f4.fld.otg_hs_hcfg.fslspcs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcfg, "FSLSPCS"); + state->u.f4.fld.otg_hs_hcfg.fslss = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcfg, "FSLSS"); + + // OTG_HS_HFIR bitfields. + state->u.f4.fld.otg_hs_hfir.frivl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hfir, "FRIVL"); + + // OTG_HS_HFNUM bitfields. + state->u.f4.fld.otg_hs_hfnum.frnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hfnum, "FRNUM"); + state->u.f4.fld.otg_hs_hfnum.ftrem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hfnum, "FTREM"); + + // OTG_HS_HPTXSTS bitfields. + state->u.f4.fld.otg_hs_hptxsts.ptxfsavl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxsts, "PTXFSAVL"); + state->u.f4.fld.otg_hs_hptxsts.ptxqsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxsts, "PTXQSAV"); + state->u.f4.fld.otg_hs_hptxsts.ptxqtop = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxsts, "PTXQTOP"); + + // OTG_HS_HAINT bitfields. + state->u.f4.fld.otg_hs_haint.haint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_haint, "HAINT"); + + // OTG_HS_HAINTMSK bitfields. + state->u.f4.fld.otg_hs_haintmsk.haintm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_haintmsk, "HAINTM"); + + // OTG_HS_HPRT bitfields. + state->u.f4.fld.otg_hs_hprt.pcsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PCSTS"); + state->u.f4.fld.otg_hs_hprt.pcdet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PCDET"); + state->u.f4.fld.otg_hs_hprt.pena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PENA"); + state->u.f4.fld.otg_hs_hprt.penchng = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PENCHNG"); + state->u.f4.fld.otg_hs_hprt.poca = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "POCA"); + state->u.f4.fld.otg_hs_hprt.pocchng = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "POCCHNG"); + state->u.f4.fld.otg_hs_hprt.pres = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PRES"); + state->u.f4.fld.otg_hs_hprt.psusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PSUSP"); + state->u.f4.fld.otg_hs_hprt.prst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PRST"); + state->u.f4.fld.otg_hs_hprt.plsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PLSTS"); + state->u.f4.fld.otg_hs_hprt.ppwr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PPWR"); + state->u.f4.fld.otg_hs_hprt.ptctl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PTCTL"); + state->u.f4.fld.otg_hs_hprt.pspd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PSPD"); + + // OTG_HS_HCCHAR0 bitfields. + state->u.f4.fld.otg_hs_hcchar0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar0.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar0.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar0.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar0.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "MC"); + state->u.f4.fld.otg_hs_hcchar0.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "DAD"); + state->u.f4.fld.otg_hs_hcchar0.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar0.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar0.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "CHENA"); + + // OTG_HS_HCCHAR1 bitfields. + state->u.f4.fld.otg_hs_hcchar1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar1.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar1.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar1.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar1.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "MC"); + state->u.f4.fld.otg_hs_hcchar1.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "DAD"); + state->u.f4.fld.otg_hs_hcchar1.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar1.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar1.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "CHENA"); + + // OTG_HS_HCCHAR2 bitfields. + state->u.f4.fld.otg_hs_hcchar2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar2.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar2.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar2.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar2.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "MC"); + state->u.f4.fld.otg_hs_hcchar2.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "DAD"); + state->u.f4.fld.otg_hs_hcchar2.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar2.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar2.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "CHENA"); + + // OTG_HS_HCCHAR3 bitfields. + state->u.f4.fld.otg_hs_hcchar3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar3.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar3.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar3.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar3.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "MC"); + state->u.f4.fld.otg_hs_hcchar3.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "DAD"); + state->u.f4.fld.otg_hs_hcchar3.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar3.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar3.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "CHENA"); + + // OTG_HS_HCCHAR4 bitfields. + state->u.f4.fld.otg_hs_hcchar4.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar4.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar4.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar4.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar4.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar4.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "MC"); + state->u.f4.fld.otg_hs_hcchar4.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "DAD"); + state->u.f4.fld.otg_hs_hcchar4.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar4.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar4.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "CHENA"); + + // OTG_HS_HCCHAR5 bitfields. + state->u.f4.fld.otg_hs_hcchar5.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar5.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar5.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar5.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar5.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar5.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "MC"); + state->u.f4.fld.otg_hs_hcchar5.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "DAD"); + state->u.f4.fld.otg_hs_hcchar5.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar5.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar5.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "CHENA"); + + // OTG_HS_HCCHAR6 bitfields. + state->u.f4.fld.otg_hs_hcchar6.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar6.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar6.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar6.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar6.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar6.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "MC"); + state->u.f4.fld.otg_hs_hcchar6.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "DAD"); + state->u.f4.fld.otg_hs_hcchar6.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar6.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar6.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "CHENA"); + + // OTG_HS_HCCHAR7 bitfields. + state->u.f4.fld.otg_hs_hcchar7.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar7.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar7.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar7.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar7.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar7.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "MC"); + state->u.f4.fld.otg_hs_hcchar7.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "DAD"); + state->u.f4.fld.otg_hs_hcchar7.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar7.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar7.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "CHENA"); + + // OTG_HS_HCCHAR8 bitfields. + state->u.f4.fld.otg_hs_hcchar8.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar8.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar8.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar8.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar8.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar8.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "MC"); + state->u.f4.fld.otg_hs_hcchar8.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "DAD"); + state->u.f4.fld.otg_hs_hcchar8.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar8.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar8.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "CHENA"); + + // OTG_HS_HCCHAR9 bitfields. + state->u.f4.fld.otg_hs_hcchar9.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar9.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar9.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar9.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar9.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar9.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "MC"); + state->u.f4.fld.otg_hs_hcchar9.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "DAD"); + state->u.f4.fld.otg_hs_hcchar9.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar9.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar9.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "CHENA"); + + // OTG_HS_HCCHAR10 bitfields. + state->u.f4.fld.otg_hs_hcchar10.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar10.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar10.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar10.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar10.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar10.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "MC"); + state->u.f4.fld.otg_hs_hcchar10.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "DAD"); + state->u.f4.fld.otg_hs_hcchar10.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar10.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar10.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "CHENA"); + + // OTG_HS_HCCHAR11 bitfields. + state->u.f4.fld.otg_hs_hcchar11.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar11.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar11.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar11.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar11.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar11.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "MC"); + state->u.f4.fld.otg_hs_hcchar11.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "DAD"); + state->u.f4.fld.otg_hs_hcchar11.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar11.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar11.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "CHENA"); + + // OTG_HS_HCSPLT0 bitfields. + state->u.f4.fld.otg_hs_hcsplt0.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt0.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt0.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt0.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt0.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "SPLITEN"); + + // OTG_HS_HCSPLT1 bitfields. + state->u.f4.fld.otg_hs_hcsplt1.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt1.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt1.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt1.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt1.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "SPLITEN"); + + // OTG_HS_HCSPLT2 bitfields. + state->u.f4.fld.otg_hs_hcsplt2.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt2.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt2.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt2.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt2.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "SPLITEN"); + + // OTG_HS_HCSPLT3 bitfields. + state->u.f4.fld.otg_hs_hcsplt3.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt3.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt3.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt3.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt3.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "SPLITEN"); + + // OTG_HS_HCSPLT4 bitfields. + state->u.f4.fld.otg_hs_hcsplt4.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt4.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt4.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt4.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt4.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "SPLITEN"); + + // OTG_HS_HCSPLT5 bitfields. + state->u.f4.fld.otg_hs_hcsplt5.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt5.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt5.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt5.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt5.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "SPLITEN"); + + // OTG_HS_HCSPLT6 bitfields. + state->u.f4.fld.otg_hs_hcsplt6.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt6.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt6.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt6.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt6.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "SPLITEN"); + + // OTG_HS_HCSPLT7 bitfields. + state->u.f4.fld.otg_hs_hcsplt7.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt7.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt7.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt7.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt7.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "SPLITEN"); + + // OTG_HS_HCSPLT8 bitfields. + state->u.f4.fld.otg_hs_hcsplt8.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt8.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt8.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt8.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt8.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "SPLITEN"); + + // OTG_HS_HCSPLT9 bitfields. + state->u.f4.fld.otg_hs_hcsplt9.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt9.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt9.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt9.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt9.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "SPLITEN"); + + // OTG_HS_HCSPLT10 bitfields. + state->u.f4.fld.otg_hs_hcsplt10.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt10.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt10.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt10.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt10.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "SPLITEN"); + + // OTG_HS_HCSPLT11 bitfields. + state->u.f4.fld.otg_hs_hcsplt11.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt11.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt11.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt11.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt11.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "SPLITEN"); + + // OTG_HS_HCINT0 bitfields. + state->u.f4.fld.otg_hs_hcint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "XFRC"); + state->u.f4.fld.otg_hs_hcint0.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "CHH"); + state->u.f4.fld.otg_hs_hcint0.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "AHBERR"); + state->u.f4.fld.otg_hs_hcint0.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "STALL"); + state->u.f4.fld.otg_hs_hcint0.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "NAK"); + state->u.f4.fld.otg_hs_hcint0.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "ACK"); + state->u.f4.fld.otg_hs_hcint0.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "NYET"); + state->u.f4.fld.otg_hs_hcint0.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "TXERR"); + state->u.f4.fld.otg_hs_hcint0.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "BBERR"); + state->u.f4.fld.otg_hs_hcint0.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "FRMOR"); + state->u.f4.fld.otg_hs_hcint0.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "DTERR"); + + // OTG_HS_HCINT1 bitfields. + state->u.f4.fld.otg_hs_hcint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "XFRC"); + state->u.f4.fld.otg_hs_hcint1.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "CHH"); + state->u.f4.fld.otg_hs_hcint1.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "AHBERR"); + state->u.f4.fld.otg_hs_hcint1.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "STALL"); + state->u.f4.fld.otg_hs_hcint1.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "NAK"); + state->u.f4.fld.otg_hs_hcint1.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "ACK"); + state->u.f4.fld.otg_hs_hcint1.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "NYET"); + state->u.f4.fld.otg_hs_hcint1.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "TXERR"); + state->u.f4.fld.otg_hs_hcint1.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "BBERR"); + state->u.f4.fld.otg_hs_hcint1.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "FRMOR"); + state->u.f4.fld.otg_hs_hcint1.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "DTERR"); + + // OTG_HS_HCINT2 bitfields. + state->u.f4.fld.otg_hs_hcint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "XFRC"); + state->u.f4.fld.otg_hs_hcint2.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "CHH"); + state->u.f4.fld.otg_hs_hcint2.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "AHBERR"); + state->u.f4.fld.otg_hs_hcint2.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "STALL"); + state->u.f4.fld.otg_hs_hcint2.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "NAK"); + state->u.f4.fld.otg_hs_hcint2.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "ACK"); + state->u.f4.fld.otg_hs_hcint2.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "NYET"); + state->u.f4.fld.otg_hs_hcint2.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "TXERR"); + state->u.f4.fld.otg_hs_hcint2.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "BBERR"); + state->u.f4.fld.otg_hs_hcint2.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "FRMOR"); + state->u.f4.fld.otg_hs_hcint2.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "DTERR"); + + // OTG_HS_HCINT3 bitfields. + state->u.f4.fld.otg_hs_hcint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "XFRC"); + state->u.f4.fld.otg_hs_hcint3.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "CHH"); + state->u.f4.fld.otg_hs_hcint3.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "AHBERR"); + state->u.f4.fld.otg_hs_hcint3.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "STALL"); + state->u.f4.fld.otg_hs_hcint3.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "NAK"); + state->u.f4.fld.otg_hs_hcint3.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "ACK"); + state->u.f4.fld.otg_hs_hcint3.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "NYET"); + state->u.f4.fld.otg_hs_hcint3.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "TXERR"); + state->u.f4.fld.otg_hs_hcint3.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "BBERR"); + state->u.f4.fld.otg_hs_hcint3.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "FRMOR"); + state->u.f4.fld.otg_hs_hcint3.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "DTERR"); + + // OTG_HS_HCINT4 bitfields. + state->u.f4.fld.otg_hs_hcint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "XFRC"); + state->u.f4.fld.otg_hs_hcint4.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "CHH"); + state->u.f4.fld.otg_hs_hcint4.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "AHBERR"); + state->u.f4.fld.otg_hs_hcint4.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "STALL"); + state->u.f4.fld.otg_hs_hcint4.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "NAK"); + state->u.f4.fld.otg_hs_hcint4.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "ACK"); + state->u.f4.fld.otg_hs_hcint4.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "NYET"); + state->u.f4.fld.otg_hs_hcint4.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "TXERR"); + state->u.f4.fld.otg_hs_hcint4.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "BBERR"); + state->u.f4.fld.otg_hs_hcint4.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "FRMOR"); + state->u.f4.fld.otg_hs_hcint4.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "DTERR"); + + // OTG_HS_HCINT5 bitfields. + state->u.f4.fld.otg_hs_hcint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "XFRC"); + state->u.f4.fld.otg_hs_hcint5.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "CHH"); + state->u.f4.fld.otg_hs_hcint5.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "AHBERR"); + state->u.f4.fld.otg_hs_hcint5.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "STALL"); + state->u.f4.fld.otg_hs_hcint5.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "NAK"); + state->u.f4.fld.otg_hs_hcint5.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "ACK"); + state->u.f4.fld.otg_hs_hcint5.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "NYET"); + state->u.f4.fld.otg_hs_hcint5.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "TXERR"); + state->u.f4.fld.otg_hs_hcint5.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "BBERR"); + state->u.f4.fld.otg_hs_hcint5.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "FRMOR"); + state->u.f4.fld.otg_hs_hcint5.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "DTERR"); + + // OTG_HS_HCINT6 bitfields. + state->u.f4.fld.otg_hs_hcint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "XFRC"); + state->u.f4.fld.otg_hs_hcint6.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "CHH"); + state->u.f4.fld.otg_hs_hcint6.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "AHBERR"); + state->u.f4.fld.otg_hs_hcint6.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "STALL"); + state->u.f4.fld.otg_hs_hcint6.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "NAK"); + state->u.f4.fld.otg_hs_hcint6.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "ACK"); + state->u.f4.fld.otg_hs_hcint6.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "NYET"); + state->u.f4.fld.otg_hs_hcint6.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "TXERR"); + state->u.f4.fld.otg_hs_hcint6.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "BBERR"); + state->u.f4.fld.otg_hs_hcint6.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "FRMOR"); + state->u.f4.fld.otg_hs_hcint6.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "DTERR"); + + // OTG_HS_HCINT7 bitfields. + state->u.f4.fld.otg_hs_hcint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "XFRC"); + state->u.f4.fld.otg_hs_hcint7.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "CHH"); + state->u.f4.fld.otg_hs_hcint7.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "AHBERR"); + state->u.f4.fld.otg_hs_hcint7.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "STALL"); + state->u.f4.fld.otg_hs_hcint7.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "NAK"); + state->u.f4.fld.otg_hs_hcint7.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "ACK"); + state->u.f4.fld.otg_hs_hcint7.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "NYET"); + state->u.f4.fld.otg_hs_hcint7.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "TXERR"); + state->u.f4.fld.otg_hs_hcint7.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "BBERR"); + state->u.f4.fld.otg_hs_hcint7.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "FRMOR"); + state->u.f4.fld.otg_hs_hcint7.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "DTERR"); + + // OTG_HS_HCINT8 bitfields. + state->u.f4.fld.otg_hs_hcint8.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "XFRC"); + state->u.f4.fld.otg_hs_hcint8.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "CHH"); + state->u.f4.fld.otg_hs_hcint8.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "AHBERR"); + state->u.f4.fld.otg_hs_hcint8.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "STALL"); + state->u.f4.fld.otg_hs_hcint8.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "NAK"); + state->u.f4.fld.otg_hs_hcint8.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "ACK"); + state->u.f4.fld.otg_hs_hcint8.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "NYET"); + state->u.f4.fld.otg_hs_hcint8.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "TXERR"); + state->u.f4.fld.otg_hs_hcint8.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "BBERR"); + state->u.f4.fld.otg_hs_hcint8.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "FRMOR"); + state->u.f4.fld.otg_hs_hcint8.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "DTERR"); + + // OTG_HS_HCINT9 bitfields. + state->u.f4.fld.otg_hs_hcint9.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "XFRC"); + state->u.f4.fld.otg_hs_hcint9.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "CHH"); + state->u.f4.fld.otg_hs_hcint9.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "AHBERR"); + state->u.f4.fld.otg_hs_hcint9.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "STALL"); + state->u.f4.fld.otg_hs_hcint9.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "NAK"); + state->u.f4.fld.otg_hs_hcint9.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "ACK"); + state->u.f4.fld.otg_hs_hcint9.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "NYET"); + state->u.f4.fld.otg_hs_hcint9.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "TXERR"); + state->u.f4.fld.otg_hs_hcint9.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "BBERR"); + state->u.f4.fld.otg_hs_hcint9.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "FRMOR"); + state->u.f4.fld.otg_hs_hcint9.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "DTERR"); + + // OTG_HS_HCINT10 bitfields. + state->u.f4.fld.otg_hs_hcint10.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "XFRC"); + state->u.f4.fld.otg_hs_hcint10.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "CHH"); + state->u.f4.fld.otg_hs_hcint10.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "AHBERR"); + state->u.f4.fld.otg_hs_hcint10.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "STALL"); + state->u.f4.fld.otg_hs_hcint10.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "NAK"); + state->u.f4.fld.otg_hs_hcint10.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "ACK"); + state->u.f4.fld.otg_hs_hcint10.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "NYET"); + state->u.f4.fld.otg_hs_hcint10.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "TXERR"); + state->u.f4.fld.otg_hs_hcint10.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "BBERR"); + state->u.f4.fld.otg_hs_hcint10.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "FRMOR"); + state->u.f4.fld.otg_hs_hcint10.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "DTERR"); + + // OTG_HS_HCINT11 bitfields. + state->u.f4.fld.otg_hs_hcint11.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "XFRC"); + state->u.f4.fld.otg_hs_hcint11.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "CHH"); + state->u.f4.fld.otg_hs_hcint11.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "AHBERR"); + state->u.f4.fld.otg_hs_hcint11.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "STALL"); + state->u.f4.fld.otg_hs_hcint11.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "NAK"); + state->u.f4.fld.otg_hs_hcint11.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "ACK"); + state->u.f4.fld.otg_hs_hcint11.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "NYET"); + state->u.f4.fld.otg_hs_hcint11.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "TXERR"); + state->u.f4.fld.otg_hs_hcint11.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "BBERR"); + state->u.f4.fld.otg_hs_hcint11.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "FRMOR"); + state->u.f4.fld.otg_hs_hcint11.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "DTERR"); + + // OTG_HS_HCINTMSK0 bitfields. + state->u.f4.fld.otg_hs_hcintmsk0.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk0.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk0.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk0.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk0.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk0.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk0.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk0.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk0.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk0.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk0.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "DTERRM"); + + // OTG_HS_HCINTMSK1 bitfields. + state->u.f4.fld.otg_hs_hcintmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk1.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk1.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk1.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk1.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk1.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk1.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk1.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk1.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk1.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "DTERRM"); + + // OTG_HS_HCINTMSK2 bitfields. + state->u.f4.fld.otg_hs_hcintmsk2.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk2.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk2.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk2.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk2.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk2.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk2.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk2.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk2.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk2.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk2.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "DTERRM"); + + // OTG_HS_HCINTMSK3 bitfields. + state->u.f4.fld.otg_hs_hcintmsk3.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk3.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk3.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk3.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk3.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk3.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk3.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk3.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk3.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk3.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk3.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "DTERRM"); + + // OTG_HS_HCINTMSK4 bitfields. + state->u.f4.fld.otg_hs_hcintmsk4.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk4.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk4.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk4.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk4.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk4.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk4.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk4.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk4.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk4.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk4.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "DTERRM"); + + // OTG_HS_HCINTMSK5 bitfields. + state->u.f4.fld.otg_hs_hcintmsk5.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk5.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk5.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk5.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk5.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk5.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk5.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk5.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk5.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk5.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk5.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "DTERRM"); + + // OTG_HS_HCINTMSK6 bitfields. + state->u.f4.fld.otg_hs_hcintmsk6.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk6.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk6.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk6.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk6.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk6.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk6.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk6.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk6.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk6.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk6.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "DTERRM"); + + // OTG_HS_HCINTMSK7 bitfields. + state->u.f4.fld.otg_hs_hcintmsk7.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk7.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk7.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk7.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk7.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk7.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk7.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk7.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk7.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk7.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk7.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "DTERRM"); + + // OTG_HS_HCINTMSK8 bitfields. + state->u.f4.fld.otg_hs_hcintmsk8.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk8.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk8.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk8.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk8.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk8.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk8.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk8.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk8.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk8.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk8.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "DTERRM"); + + // OTG_HS_HCINTMSK9 bitfields. + state->u.f4.fld.otg_hs_hcintmsk9.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk9.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk9.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk9.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk9.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk9.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk9.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk9.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk9.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk9.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk9.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "DTERRM"); + + // OTG_HS_HCINTMSK10 bitfields. + state->u.f4.fld.otg_hs_hcintmsk10.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk10.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk10.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk10.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk10.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk10.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk10.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk10.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk10.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk10.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk10.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "DTERRM"); + + // OTG_HS_HCINTMSK11 bitfields. + state->u.f4.fld.otg_hs_hcintmsk11.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk11.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk11.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk11.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk11.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk11.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk11.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk11.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk11.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk11.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk11.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "DTERRM"); + + // OTG_HS_HCTSIZ0 bitfields. + state->u.f4.fld.otg_hs_hctsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz0, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz0, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz0.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz0, "DPID"); + + // OTG_HS_HCTSIZ1 bitfields. + state->u.f4.fld.otg_hs_hctsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz1, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz1, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz1.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz1, "DPID"); + + // OTG_HS_HCTSIZ2 bitfields. + state->u.f4.fld.otg_hs_hctsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz2, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz2, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz2.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz2, "DPID"); + + // OTG_HS_HCTSIZ3 bitfields. + state->u.f4.fld.otg_hs_hctsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz3, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz3, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz3.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz3, "DPID"); + + // OTG_HS_HCTSIZ4 bitfields. + state->u.f4.fld.otg_hs_hctsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz4, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz4, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz4.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz4, "DPID"); + + // OTG_HS_HCTSIZ5 bitfields. + state->u.f4.fld.otg_hs_hctsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz5, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz5.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz5, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz5.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz5, "DPID"); + + // OTG_HS_HCTSIZ6 bitfields. + state->u.f4.fld.otg_hs_hctsiz6.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz6, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz6.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz6, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz6.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz6, "DPID"); + + // OTG_HS_HCTSIZ7 bitfields. + state->u.f4.fld.otg_hs_hctsiz7.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz7, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz7.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz7, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz7.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz7, "DPID"); + + // OTG_HS_HCTSIZ8 bitfields. + state->u.f4.fld.otg_hs_hctsiz8.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz8, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz8.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz8, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz8.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz8, "DPID"); + + // OTG_HS_HCTSIZ9 bitfields. + state->u.f4.fld.otg_hs_hctsiz9.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz9, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz9.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz9, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz9.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz9, "DPID"); + + // OTG_HS_HCTSIZ10 bitfields. + state->u.f4.fld.otg_hs_hctsiz10.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz10, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz10.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz10, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz10.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz10, "DPID"); + + // OTG_HS_HCTSIZ11 bitfields. + state->u.f4.fld.otg_hs_hctsiz11.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz11, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz11.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz11, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz11.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz11, "DPID"); + + // OTG_HS_HCDMA0 bitfields. + state->u.f4.fld.otg_hs_hcdma0.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma0, "DMAADDR"); + + // OTG_HS_HCDMA1 bitfields. + state->u.f4.fld.otg_hs_hcdma1.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma1, "DMAADDR"); + + // OTG_HS_HCDMA2 bitfields. + state->u.f4.fld.otg_hs_hcdma2.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma2, "DMAADDR"); + + // OTG_HS_HCDMA3 bitfields. + state->u.f4.fld.otg_hs_hcdma3.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma3, "DMAADDR"); + + // OTG_HS_HCDMA4 bitfields. + state->u.f4.fld.otg_hs_hcdma4.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma4, "DMAADDR"); + + // OTG_HS_HCDMA5 bitfields. + state->u.f4.fld.otg_hs_hcdma5.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma5, "DMAADDR"); + + // OTG_HS_HCDMA6 bitfields. + state->u.f4.fld.otg_hs_hcdma6.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma6, "DMAADDR"); + + // OTG_HS_HCDMA7 bitfields. + state->u.f4.fld.otg_hs_hcdma7.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma7, "DMAADDR"); + + // OTG_HS_HCDMA8 bitfields. + state->u.f4.fld.otg_hs_hcdma8.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma8, "DMAADDR"); + + // OTG_HS_HCDMA9 bitfields. + state->u.f4.fld.otg_hs_hcdma9.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma9, "DMAADDR"); + + // OTG_HS_HCDMA10 bitfields. + state->u.f4.fld.otg_hs_hcdma10.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma10, "DMAADDR"); + + // OTG_HS_HCDMA11 bitfields. + state->u.f4.fld.otg_hs_hcdma11.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma11, "DMAADDR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_host_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_host_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_host_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_host_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_host_is_enabled(Object *obj) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_host_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_host_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_HOST)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_HOST"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_hs_host_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_HOSTEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_host_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_HOST); +} + +static void stm32_otg_hs_host_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_host_reset_callback; + dc->realize = stm32_otg_hs_host_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_host_is_enabled; +} + +static const TypeInfo stm32_otg_hs_host_type_info = { + .name = TYPE_STM32_OTG_HS_HOST, + .parent = TYPE_STM32_OTG_HS_HOST_PARENT, + .instance_init = stm32_otg_hs_host_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_HOSTState), + .class_init = stm32_otg_hs_host_class_init_callback, + .class_size = sizeof(STM32OTG_HS_HOSTClass) }; + +static void stm32_otg_hs_host_register_types(void) +{ + type_register_static(&stm32_otg_hs_host_type_info); +} + +type_init(stm32_otg_hs_host_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_host.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_host.h new file mode 100644 index 0000000000..bea043abc9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_host.h @@ -0,0 +1,1009 @@ +/* + * STM32 - OTG_HS_HOST (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_HOST_H_ +#define STM32_OTG_HS_HOST_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_HOST DEVICE_PATH_STM32 "OTG_HS_HOST" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_HOST TYPE_STM32_PREFIX "otg_hs_host" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_HOST_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_HOSTParentClass; +typedef PeripheralState STM32OTG_HS_HOSTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_HOST_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_HOSTClass, (obj), TYPE_STM32_OTG_HS_HOST) +#define STM32_OTG_HS_HOST_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_HOSTClass, (klass), TYPE_STM32_OTG_HS_HOST) + +typedef struct { + // private: + STM32OTG_HS_HOSTParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_HOSTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_HOST_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_HOSTState, (obj), TYPE_STM32_OTG_HS_HOST) + +typedef struct { + // private: + STM32OTG_HS_HOSTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_HOST (USB on the go high speed) registers. + struct { + Object *otg_hs_hcfg; // 0x0 (OTG_HS host configuration register) + Object *otg_hs_hfir; // 0x4 (OTG_HS Host frame interval register) + Object *otg_hs_hfnum; // 0x8 (OTG_HS host frame number/frame time remaining register) + Object *otg_hs_hptxsts; // 0x10 (OTG_HS_Host periodic transmit FIFO/queue status register) + Object *otg_hs_haint; // 0x14 (OTG_HS Host all channels interrupt register) + Object *otg_hs_haintmsk; // 0x18 (OTG_HS host all channels interrupt mask register) + Object *otg_hs_hprt; // 0x40 (OTG_HS host port control and status register) + Object *otg_hs_hcchar0; // 0x100 (OTG_HS host channel-0 characteristics register) + Object *otg_hs_hcchar1; // 0x120 (OTG_HS host channel-1 characteristics register) + Object *otg_hs_hcchar2; // 0x140 (OTG_HS host channel-2 characteristics register) + Object *otg_hs_hcchar3; // 0x160 (OTG_HS host channel-3 characteristics register) + Object *otg_hs_hcchar4; // 0x180 (OTG_HS host channel-4 characteristics register) + Object *otg_hs_hcchar5; // 0x1A0 (OTG_HS host channel-5 characteristics register) + Object *otg_hs_hcchar6; // 0x1C0 (OTG_HS host channel-6 characteristics register) + Object *otg_hs_hcchar7; // 0x1E0 (OTG_HS host channel-7 characteristics register) + Object *otg_hs_hcchar8; // 0x200 (OTG_HS host channel-8 characteristics register) + Object *otg_hs_hcchar9; // 0x220 (OTG_HS host channel-9 characteristics register) + Object *otg_hs_hcchar10; // 0x240 (OTG_HS host channel-10 characteristics register) + Object *otg_hs_hcchar11; // 0x260 (OTG_HS host channel-11 characteristics register) + Object *otg_hs_hcsplt0; // 0x104 (OTG_HS host channel-0 split control register) + Object *otg_hs_hcsplt1; // 0x124 (OTG_HS host channel-1 split control register) + Object *otg_hs_hcsplt2; // 0x144 (OTG_HS host channel-2 split control register) + Object *otg_hs_hcsplt3; // 0x164 (OTG_HS host channel-3 split control register) + Object *otg_hs_hcsplt4; // 0x184 (OTG_HS host channel-4 split control register) + Object *otg_hs_hcsplt5; // 0x1A4 (OTG_HS host channel-5 split control register) + Object *otg_hs_hcsplt6; // 0x1C4 (OTG_HS host channel-6 split control register) + Object *otg_hs_hcsplt7; // 0x1E4 (OTG_HS host channel-7 split control register) + Object *otg_hs_hcsplt8; // 0x204 (OTG_HS host channel-8 split control register) + Object *otg_hs_hcsplt9; // 0x224 (OTG_HS host channel-9 split control register) + Object *otg_hs_hcsplt10; // 0x244 (OTG_HS host channel-10 split control register) + Object *otg_hs_hcsplt11; // 0x264 (OTG_HS host channel-11 split control register) + Object *otg_hs_hcint0; // 0x108 (OTG_HS host channel-11 interrupt register) + Object *otg_hs_hcint1; // 0x128 (OTG_HS host channel-1 interrupt register) + Object *otg_hs_hcint2; // 0x148 (OTG_HS host channel-2 interrupt register) + Object *otg_hs_hcint3; // 0x168 (OTG_HS host channel-3 interrupt register) + Object *otg_hs_hcint4; // 0x188 (OTG_HS host channel-4 interrupt register) + Object *otg_hs_hcint5; // 0x1A8 (OTG_HS host channel-5 interrupt register) + Object *otg_hs_hcint6; // 0x1C8 (OTG_HS host channel-6 interrupt register) + Object *otg_hs_hcint7; // 0x1E8 (OTG_HS host channel-7 interrupt register) + Object *otg_hs_hcint8; // 0x208 (OTG_HS host channel-8 interrupt register) + Object *otg_hs_hcint9; // 0x228 (OTG_HS host channel-9 interrupt register) + Object *otg_hs_hcint10; // 0x248 (OTG_HS host channel-10 interrupt register) + Object *otg_hs_hcint11; // 0x268 (OTG_HS host channel-11 interrupt register) + Object *otg_hs_hcintmsk0; // 0x10C (OTG_HS host channel-11 interrupt mask register) + Object *otg_hs_hcintmsk1; // 0x12C (OTG_HS host channel-1 interrupt mask register) + Object *otg_hs_hcintmsk2; // 0x14C (OTG_HS host channel-2 interrupt mask register) + Object *otg_hs_hcintmsk3; // 0x16C (OTG_HS host channel-3 interrupt mask register) + Object *otg_hs_hcintmsk4; // 0x18C (OTG_HS host channel-4 interrupt mask register) + Object *otg_hs_hcintmsk5; // 0x1AC (OTG_HS host channel-5 interrupt mask register) + Object *otg_hs_hcintmsk6; // 0x1CC (OTG_HS host channel-6 interrupt mask register) + Object *otg_hs_hcintmsk7; // 0x1EC (OTG_HS host channel-7 interrupt mask register) + Object *otg_hs_hcintmsk8; // 0x20C (OTG_HS host channel-8 interrupt mask register) + Object *otg_hs_hcintmsk9; // 0x22C (OTG_HS host channel-9 interrupt mask register) + Object *otg_hs_hcintmsk10; // 0x24C (OTG_HS host channel-10 interrupt mask register) + Object *otg_hs_hcintmsk11; // 0x26C (OTG_HS host channel-11 interrupt mask register) + Object *otg_hs_hctsiz0; // 0x110 (OTG_HS host channel-11 transfer size register) + Object *otg_hs_hctsiz1; // 0x130 (OTG_HS host channel-1 transfer size register) + Object *otg_hs_hctsiz2; // 0x150 (OTG_HS host channel-2 transfer size register) + Object *otg_hs_hctsiz3; // 0x170 (OTG_HS host channel-3 transfer size register) + Object *otg_hs_hctsiz4; // 0x190 (OTG_HS host channel-4 transfer size register) + Object *otg_hs_hctsiz5; // 0x1B0 (OTG_HS host channel-5 transfer size register) + Object *otg_hs_hctsiz6; // 0x1D0 (OTG_HS host channel-6 transfer size register) + Object *otg_hs_hctsiz7; // 0x1F0 (OTG_HS host channel-7 transfer size register) + Object *otg_hs_hctsiz8; // 0x210 (OTG_HS host channel-8 transfer size register) + Object *otg_hs_hctsiz9; // 0x230 (OTG_HS host channel-9 transfer size register) + Object *otg_hs_hctsiz10; // 0x250 (OTG_HS host channel-10 transfer size register) + Object *otg_hs_hctsiz11; // 0x270 (OTG_HS host channel-11 transfer size register) + Object *otg_hs_hcdma0; // 0x114 (OTG_HS host channel-0 DMA address register) + Object *otg_hs_hcdma1; // 0x134 (OTG_HS host channel-1 DMA address register) + Object *otg_hs_hcdma2; // 0x154 (OTG_HS host channel-2 DMA address register) + Object *otg_hs_hcdma3; // 0x174 (OTG_HS host channel-3 DMA address register) + Object *otg_hs_hcdma4; // 0x194 (OTG_HS host channel-4 DMA address register) + Object *otg_hs_hcdma5; // 0x1B4 (OTG_HS host channel-5 DMA address register) + Object *otg_hs_hcdma6; // 0x1D4 (OTG_HS host channel-6 DMA address register) + Object *otg_hs_hcdma7; // 0x1F4 (OTG_HS host channel-7 DMA address register) + Object *otg_hs_hcdma8; // 0x214 (OTG_HS host channel-8 DMA address register) + Object *otg_hs_hcdma9; // 0x234 (OTG_HS host channel-9 DMA address register) + Object *otg_hs_hcdma10; // 0x254 (OTG_HS host channel-10 DMA address register) + Object *otg_hs_hcdma11; // 0x274 (OTG_HS host channel-11 DMA address register) + } reg; + + struct { + + // OTG_HS_HCFG (OTG_HS host configuration register) bitfields. + struct { + Object *fslspcs; // [0:1] FS/LS PHY clock select + Object *fslss; // [2:2] FS- and LS-only support + } otg_hs_hcfg; + + // OTG_HS_HFIR (OTG_HS Host frame interval register) bitfields. + struct { + Object *frivl; // [0:15] Frame interval + } otg_hs_hfir; + + // OTG_HS_HFNUM (OTG_HS host frame number/frame time remaining register) bitfields. + struct { + Object *frnum; // [0:15] Frame number + Object *ftrem; // [16:31] Frame time remaining + } otg_hs_hfnum; + + // OTG_HS_HPTXSTS (OTG_HS_Host periodic transmit FIFO/queue status register) bitfields. + struct { + Object *ptxfsavl; // [0:15] Periodic transmit data FIFO space available + Object *ptxqsav; // [16:23] Periodic transmit request queue space available + Object *ptxqtop; // [24:31] Top of the periodic transmit request queue + } otg_hs_hptxsts; + + // OTG_HS_HAINT (OTG_HS Host all channels interrupt register) bitfields. + struct { + Object *haint; // [0:15] Channel interrupts + } otg_hs_haint; + + // OTG_HS_HAINTMSK (OTG_HS host all channels interrupt mask register) bitfields. + struct { + Object *haintm; // [0:15] Channel interrupt mask + } otg_hs_haintmsk; + + // OTG_HS_HPRT (OTG_HS host port control and status register) bitfields. + struct { + Object *pcsts; // [0:0] Port connect status + Object *pcdet; // [1:1] Port connect detected + Object *pena; // [2:2] Port enable + Object *penchng; // [3:3] Port enable/disable change + Object *poca; // [4:4] Port overcurrent active + Object *pocchng; // [5:5] Port overcurrent change + Object *pres; // [6:6] Port resume + Object *psusp; // [7:7] Port suspend + Object *prst; // [8:8] Port reset + Object *plsts; // [10:11] Port line status + Object *ppwr; // [12:12] Port power + Object *ptctl; // [13:16] Port test control + Object *pspd; // [17:18] Port speed + } otg_hs_hprt; + + // OTG_HS_HCCHAR0 (OTG_HS host channel-0 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar0; + + // OTG_HS_HCCHAR1 (OTG_HS host channel-1 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar1; + + // OTG_HS_HCCHAR2 (OTG_HS host channel-2 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar2; + + // OTG_HS_HCCHAR3 (OTG_HS host channel-3 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar3; + + // OTG_HS_HCCHAR4 (OTG_HS host channel-4 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar4; + + // OTG_HS_HCCHAR5 (OTG_HS host channel-5 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar5; + + // OTG_HS_HCCHAR6 (OTG_HS host channel-6 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar6; + + // OTG_HS_HCCHAR7 (OTG_HS host channel-7 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar7; + + // OTG_HS_HCCHAR8 (OTG_HS host channel-8 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar8; + + // OTG_HS_HCCHAR9 (OTG_HS host channel-9 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar9; + + // OTG_HS_HCCHAR10 (OTG_HS host channel-10 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar10; + + // OTG_HS_HCCHAR11 (OTG_HS host channel-11 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar11; + + // OTG_HS_HCSPLT0 (OTG_HS host channel-0 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt0; + + // OTG_HS_HCSPLT1 (OTG_HS host channel-1 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt1; + + // OTG_HS_HCSPLT2 (OTG_HS host channel-2 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt2; + + // OTG_HS_HCSPLT3 (OTG_HS host channel-3 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt3; + + // OTG_HS_HCSPLT4 (OTG_HS host channel-4 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt4; + + // OTG_HS_HCSPLT5 (OTG_HS host channel-5 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt5; + + // OTG_HS_HCSPLT6 (OTG_HS host channel-6 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt6; + + // OTG_HS_HCSPLT7 (OTG_HS host channel-7 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt7; + + // OTG_HS_HCSPLT8 (OTG_HS host channel-8 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt8; + + // OTG_HS_HCSPLT9 (OTG_HS host channel-9 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt9; + + // OTG_HS_HCSPLT10 (OTG_HS host channel-10 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt10; + + // OTG_HS_HCSPLT11 (OTG_HS host channel-11 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt11; + + // OTG_HS_HCINT0 (OTG_HS host channel-11 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint0; + + // OTG_HS_HCINT1 (OTG_HS host channel-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint1; + + // OTG_HS_HCINT2 (OTG_HS host channel-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint2; + + // OTG_HS_HCINT3 (OTG_HS host channel-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint3; + + // OTG_HS_HCINT4 (OTG_HS host channel-4 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint4; + + // OTG_HS_HCINT5 (OTG_HS host channel-5 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint5; + + // OTG_HS_HCINT6 (OTG_HS host channel-6 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint6; + + // OTG_HS_HCINT7 (OTG_HS host channel-7 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint7; + + // OTG_HS_HCINT8 (OTG_HS host channel-8 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint8; + + // OTG_HS_HCINT9 (OTG_HS host channel-9 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint9; + + // OTG_HS_HCINT10 (OTG_HS host channel-10 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint10; + + // OTG_HS_HCINT11 (OTG_HS host channel-11 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint11; + + // OTG_HS_HCINTMSK0 (OTG_HS host channel-11 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk0; + + // OTG_HS_HCINTMSK1 (OTG_HS host channel-1 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk1; + + // OTG_HS_HCINTMSK2 (OTG_HS host channel-2 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk2; + + // OTG_HS_HCINTMSK3 (OTG_HS host channel-3 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk3; + + // OTG_HS_HCINTMSK4 (OTG_HS host channel-4 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk4; + + // OTG_HS_HCINTMSK5 (OTG_HS host channel-5 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk5; + + // OTG_HS_HCINTMSK6 (OTG_HS host channel-6 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk6; + + // OTG_HS_HCINTMSK7 (OTG_HS host channel-7 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk7; + + // OTG_HS_HCINTMSK8 (OTG_HS host channel-8 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk8; + + // OTG_HS_HCINTMSK9 (OTG_HS host channel-9 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk9; + + // OTG_HS_HCINTMSK10 (OTG_HS host channel-10 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk10; + + // OTG_HS_HCINTMSK11 (OTG_HS host channel-11 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk11; + + // OTG_HS_HCTSIZ0 (OTG_HS host channel-11 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz0; + + // OTG_HS_HCTSIZ1 (OTG_HS host channel-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz1; + + // OTG_HS_HCTSIZ2 (OTG_HS host channel-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz2; + + // OTG_HS_HCTSIZ3 (OTG_HS host channel-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz3; + + // OTG_HS_HCTSIZ4 (OTG_HS host channel-4 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz4; + + // OTG_HS_HCTSIZ5 (OTG_HS host channel-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz5; + + // OTG_HS_HCTSIZ6 (OTG_HS host channel-6 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz6; + + // OTG_HS_HCTSIZ7 (OTG_HS host channel-7 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz7; + + // OTG_HS_HCTSIZ8 (OTG_HS host channel-8 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz8; + + // OTG_HS_HCTSIZ9 (OTG_HS host channel-9 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz9; + + // OTG_HS_HCTSIZ10 (OTG_HS host channel-10 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz10; + + // OTG_HS_HCTSIZ11 (OTG_HS host channel-11 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz11; + + // OTG_HS_HCDMA0 (OTG_HS host channel-0 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma0; + + // OTG_HS_HCDMA1 (OTG_HS host channel-1 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma1; + + // OTG_HS_HCDMA2 (OTG_HS host channel-2 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma2; + + // OTG_HS_HCDMA3 (OTG_HS host channel-3 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma3; + + // OTG_HS_HCDMA4 (OTG_HS host channel-4 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma4; + + // OTG_HS_HCDMA5 (OTG_HS host channel-5 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma5; + + // OTG_HS_HCDMA6 (OTG_HS host channel-6 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma6; + + // OTG_HS_HCDMA7 (OTG_HS host channel-7 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma7; + + // OTG_HS_HCDMA8 (OTG_HS host channel-8 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma8; + + // OTG_HS_HCDMA9 (OTG_HS host channel-9 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma9; + + // OTG_HS_HCDMA10 (OTG_HS host channel-10 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma10; + + // OTG_HS_HCDMA11 (OTG_HS host channel-11 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma11; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_HOSTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_HOST_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_pwrclk.c b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_pwrclk.c new file mode 100644 index 0000000000..3a0677db4a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_pwrclk.c @@ -0,0 +1,240 @@ +/* + * STM32 - OTG_HS_PWRCLK (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_otg_hs_pwrclk_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_pcgcr = cm_object_get_child_by_name(obj, "OTG_HS_PCGCR"); + + + // OTG_HS_PCGCR bitfields. + state->u.f4.fld.otg_hs_pcgcr.stppclk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_pcgcr, "STPPCLK"); + state->u.f4.fld.otg_hs_pcgcr.gatehclk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_pcgcr, "GATEHCLK"); + state->u.f4.fld.otg_hs_pcgcr.physusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_pcgcr, "PHYSUSP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_pwrclk_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_pwrclk_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_pwrclk_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_pwrclk_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_pwrclk_is_enabled(Object *obj) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_pwrclk_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_pwrclk_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_PWRCLK)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_PWRCLK"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_otg_hs_pwrclk_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_PWRCLKEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_pwrclk_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_PWRCLK); +} + +static void stm32_otg_hs_pwrclk_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_pwrclk_reset_callback; + dc->realize = stm32_otg_hs_pwrclk_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_pwrclk_is_enabled; +} + +static const TypeInfo stm32_otg_hs_pwrclk_type_info = { + .name = TYPE_STM32_OTG_HS_PWRCLK, + .parent = TYPE_STM32_OTG_HS_PWRCLK_PARENT, + .instance_init = stm32_otg_hs_pwrclk_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_PWRCLKState), + .class_init = stm32_otg_hs_pwrclk_class_init_callback, + .class_size = sizeof(STM32OTG_HS_PWRCLKClass) }; + +static void stm32_otg_hs_pwrclk_register_types(void) +{ + type_register_static(&stm32_otg_hs_pwrclk_type_info); +} + +type_init(stm32_otg_hs_pwrclk_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_pwrclk.h b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_pwrclk.h new file mode 100644 index 0000000000..e4920732c0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/otg_hs_pwrclk.h @@ -0,0 +1,107 @@ +/* + * STM32 - OTG_HS_PWRCLK (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_PWRCLK_H_ +#define STM32_OTG_HS_PWRCLK_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_PWRCLK DEVICE_PATH_STM32 "OTG_HS_PWRCLK" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_PWRCLK TYPE_STM32_PREFIX "otg_hs_pwrclk" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_PWRCLK_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_PWRCLKParentClass; +typedef PeripheralState STM32OTG_HS_PWRCLKParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_PWRCLK_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_PWRCLKClass, (obj), TYPE_STM32_OTG_HS_PWRCLK) +#define STM32_OTG_HS_PWRCLK_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_PWRCLKClass, (klass), TYPE_STM32_OTG_HS_PWRCLK) + +typedef struct { + // private: + STM32OTG_HS_PWRCLKParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_PWRCLKClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_PWRCLK_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_PWRCLKState, (obj), TYPE_STM32_OTG_HS_PWRCLK) + +typedef struct { + // private: + STM32OTG_HS_PWRCLKParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_PWRCLK (USB on the go high speed) registers. + struct { + Object *otg_hs_pcgcr; // 0x0 (Power and clock gating control register) + } reg; + + struct { + + // OTG_HS_PCGCR (Power and clock gating control register) bitfields. + struct { + Object *stppclk; // [0:0] Stop PHY clock + Object *gatehclk; // [1:1] Gate HCLK + Object *physusp; // [4:4] PHY suspended + } otg_hs_pcgcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_PWRCLKState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_PWRCLK_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/pwr.c b/gnu-mcu-eclipse/devices/support/STM32F40x/pwr.c new file mode 100644 index 0000000000..32da27030c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/pwr.c @@ -0,0 +1,255 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_pwr_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CR bitfields. + state->u.f4.fld.cr.lpds = cm_object_get_child_by_name(state->u.f4.reg.cr, "LPDS"); + state->u.f4.fld.cr.pdds = cm_object_get_child_by_name(state->u.f4.reg.cr, "PDDS"); + state->u.f4.fld.cr.cwuf = cm_object_get_child_by_name(state->u.f4.reg.cr, "CWUF"); + state->u.f4.fld.cr.csbf = cm_object_get_child_by_name(state->u.f4.reg.cr, "CSBF"); + state->u.f4.fld.cr.pvde = cm_object_get_child_by_name(state->u.f4.reg.cr, "PVDE"); + state->u.f4.fld.cr.pls = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLS"); + state->u.f4.fld.cr.dbp = cm_object_get_child_by_name(state->u.f4.reg.cr, "DBP"); + state->u.f4.fld.cr.fpds = cm_object_get_child_by_name(state->u.f4.reg.cr, "FPDS"); + + // CSR bitfields. + state->u.f4.fld.csr.wuf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WUF"); + state->u.f4.fld.csr.sbf = cm_object_get_child_by_name(state->u.f4.reg.csr, "SBF"); + state->u.f4.fld.csr.pvdo = cm_object_get_child_by_name(state->u.f4.reg.csr, "PVDO"); + state->u.f4.fld.csr.brr = cm_object_get_child_by_name(state->u.f4.reg.csr, "BRR"); + state->u.f4.fld.csr.ewup = cm_object_get_child_by_name(state->u.f4.reg.csr, "EWUP"); + state->u.f4.fld.csr.bre = cm_object_get_child_by_name(state->u.f4.reg.csr, "BRE"); + state->u.f4.fld.csr.vosrdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "VOSRDY"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_pwr_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_pwr_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_pwr_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_pwr_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_pwr_is_enabled(Object *obj) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_pwr_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32PWRState *state = STM32_PWR_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_pwr_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_PWR)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32PWRState *state = STM32_PWR_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "PWR"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_pwr_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_pwr_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_pwr_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_pwr_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_pwr_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/PWREN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_pwr_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_PWR); +} + +static void stm32_pwr_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_pwr_reset_callback; + dc->realize = stm32_pwr_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_pwr_is_enabled; +} + +static const TypeInfo stm32_pwr_type_info = { + .name = TYPE_STM32_PWR, + .parent = TYPE_STM32_PWR_PARENT, + .instance_init = stm32_pwr_instance_init_callback, + .instance_size = sizeof(STM32PWRState), + .class_init = stm32_pwr_class_init_callback, + .class_size = sizeof(STM32PWRClass) }; + +static void stm32_pwr_register_types(void) +{ + type_register_static(&stm32_pwr_type_info); +} + +type_init(stm32_pwr_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/pwr.h b/gnu-mcu-eclipse/devices/support/STM32F40x/pwr.h new file mode 100644 index 0000000000..f9ae08452a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/pwr.h @@ -0,0 +1,124 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_PWR_H_ +#define STM32_PWR_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_PWR DEVICE_PATH_STM32 "PWR" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_PWR TYPE_STM32_PREFIX "pwr" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_PWR_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32PWRParentClass; +typedef PeripheralState STM32PWRParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_PWR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32PWRClass, (obj), TYPE_STM32_PWR) +#define STM32_PWR_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32PWRClass, (klass), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentClass parent_class; + // public: + + // None, so far. +} STM32PWRClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_PWR_STATE(obj) \ + OBJECT_CHECK(STM32PWRState, (obj), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 PWR (Power control) registers. + struct { + Object *cr; // 0x0 (Power control register) + Object *csr; // 0x4 (Power control/status register) + } reg; + + struct { + + // CR (Power control register) bitfields. + struct { + Object *lpds; // [0:0] Low-power deep sleep + Object *pdds; // [1:1] Power down deepsleep + Object *cwuf; // [2:2] Clear wakeup flag + Object *csbf; // [3:3] Clear standby flag + Object *pvde; // [4:4] Power voltage detector enable + Object *pls; // [5:7] PVD level selection + Object *dbp; // [8:8] Disable backup domain write protection + Object *fpds; // [9:9] Flash power down in Stop mode + } cr; + + // CSR (Power control/status register) bitfields. + struct { + Object *wuf; // [0:0] Wakeup flag + Object *sbf; // [1:1] Standby flag + Object *pvdo; // [2:2] PVD output + Object *brr; // [3:3] Backup regulator ready + Object *ewup; // [8:8] Enable WKUP pin + Object *bre; // [9:9] Backup regulator enable + Object *vosrdy; // [14:14] Regulator voltage scaling output selection ready bit + } csr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32PWRState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_PWR_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/rcc.c b/gnu-mcu-eclipse/devices/support/STM32F40x/rcc.c new file mode 100644 index 0000000000..95b1794275 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/rcc.c @@ -0,0 +1,546 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_rcc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.pllcfgr = cm_object_get_child_by_name(obj, "PLLCFGR"); + state->u.f4.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f4.reg.cir = cm_object_get_child_by_name(obj, "CIR"); + state->u.f4.reg.ahb1rstr = cm_object_get_child_by_name(obj, "AHB1RSTR"); + state->u.f4.reg.ahb2rstr = cm_object_get_child_by_name(obj, "AHB2RSTR"); + state->u.f4.reg.ahb3rstr = cm_object_get_child_by_name(obj, "AHB3RSTR"); + state->u.f4.reg.apb1rstr = cm_object_get_child_by_name(obj, "APB1RSTR"); + state->u.f4.reg.apb2rstr = cm_object_get_child_by_name(obj, "APB2RSTR"); + state->u.f4.reg.ahb1enr = cm_object_get_child_by_name(obj, "AHB1ENR"); + state->u.f4.reg.ahb2enr = cm_object_get_child_by_name(obj, "AHB2ENR"); + state->u.f4.reg.ahb3enr = cm_object_get_child_by_name(obj, "AHB3ENR"); + state->u.f4.reg.apb1enr = cm_object_get_child_by_name(obj, "APB1ENR"); + state->u.f4.reg.apb2enr = cm_object_get_child_by_name(obj, "APB2ENR"); + state->u.f4.reg.ahb1lpenr = cm_object_get_child_by_name(obj, "AHB1LPENR"); + state->u.f4.reg.ahb2lpenr = cm_object_get_child_by_name(obj, "AHB2LPENR"); + state->u.f4.reg.ahb3lpenr = cm_object_get_child_by_name(obj, "AHB3LPENR"); + state->u.f4.reg.apb1lpenr = cm_object_get_child_by_name(obj, "APB1LPENR"); + state->u.f4.reg.apb2lpenr = cm_object_get_child_by_name(obj, "APB2LPENR"); + state->u.f4.reg.bdcr = cm_object_get_child_by_name(obj, "BDCR"); + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f4.reg.sscgr = cm_object_get_child_by_name(obj, "SSCGR"); + state->u.f4.reg.plli2scfgr = cm_object_get_child_by_name(obj, "PLLI2SCFGR"); + + + // CR bitfields. + state->u.f4.fld.cr.hsion = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSION"); + state->u.f4.fld.cr.hsirdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSIRDY"); + state->u.f4.fld.cr.hsitrim = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSITRIM"); + state->u.f4.fld.cr.hsical = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSICAL"); + state->u.f4.fld.cr.hseon = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSEON"); + state->u.f4.fld.cr.hserdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSERDY"); + state->u.f4.fld.cr.hsebyp = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSEBYP"); + state->u.f4.fld.cr.csson = cm_object_get_child_by_name(state->u.f4.reg.cr, "CSSON"); + state->u.f4.fld.cr.pllon = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLON"); + state->u.f4.fld.cr.pllrdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLRDY"); + state->u.f4.fld.cr.plli2son = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLI2SON"); + state->u.f4.fld.cr.plli2srdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLI2SRDY"); + + // PLLCFGR bitfields. + state->u.f4.fld.pllcfgr.pllm = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLM"); + state->u.f4.fld.pllcfgr.plln = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLN"); + state->u.f4.fld.pllcfgr.pllp = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLP"); + state->u.f4.fld.pllcfgr.pllsrc = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLSRC"); + state->u.f4.fld.pllcfgr.pllq = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLQ"); + + // CFGR bitfields. + state->u.f4.fld.cfgr.sw = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "SW"); + state->u.f4.fld.cfgr.sws = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "SWS"); + state->u.f4.fld.cfgr.hpre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "HPRE"); + state->u.f4.fld.cfgr.ppre1 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "PPRE1"); + state->u.f4.fld.cfgr.ppre2 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "PPRE2"); + state->u.f4.fld.cfgr.rtcpre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "RTCPRE"); + state->u.f4.fld.cfgr.mco1 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO1"); + state->u.f4.fld.cfgr.i2ssrc = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "I2SSRC"); + state->u.f4.fld.cfgr.mco1pre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO1PRE"); + state->u.f4.fld.cfgr.mco2pre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO2PRE"); + state->u.f4.fld.cfgr.mco2 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO2"); + + // CIR bitfields. + state->u.f4.fld.cir.lsirdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYF"); + state->u.f4.fld.cir.lserdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYF"); + state->u.f4.fld.cir.hsirdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYF"); + state->u.f4.fld.cir.hserdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYF"); + state->u.f4.fld.cir.pllrdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYF"); + state->u.f4.fld.cir.plli2srdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYF"); + state->u.f4.fld.cir.cssf = cm_object_get_child_by_name(state->u.f4.reg.cir, "CSSF"); + state->u.f4.fld.cir.lsirdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYIE"); + state->u.f4.fld.cir.lserdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYIE"); + state->u.f4.fld.cir.hsirdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYIE"); + state->u.f4.fld.cir.hserdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYIE"); + state->u.f4.fld.cir.pllrdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYIE"); + state->u.f4.fld.cir.plli2srdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYIE"); + state->u.f4.fld.cir.lsirdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYC"); + state->u.f4.fld.cir.lserdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYC"); + state->u.f4.fld.cir.hsirdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYC"); + state->u.f4.fld.cir.hserdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYC"); + state->u.f4.fld.cir.pllrdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYC"); + state->u.f4.fld.cir.plli2srdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYC"); + state->u.f4.fld.cir.cssc = cm_object_get_child_by_name(state->u.f4.reg.cir, "CSSC"); + + // AHB1RSTR bitfields. + state->u.f4.fld.ahb1rstr.gpioarst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOARST"); + state->u.f4.fld.ahb1rstr.gpiobrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOBRST"); + state->u.f4.fld.ahb1rstr.gpiocrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOCRST"); + state->u.f4.fld.ahb1rstr.gpiodrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIODRST"); + state->u.f4.fld.ahb1rstr.gpioerst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOERST"); + state->u.f4.fld.ahb1rstr.gpiofrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOFRST"); + state->u.f4.fld.ahb1rstr.gpiogrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOGRST"); + state->u.f4.fld.ahb1rstr.gpiohrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOHRST"); + state->u.f4.fld.ahb1rstr.gpioirst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOIRST"); + state->u.f4.fld.ahb1rstr.crcrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "CRCRST"); + state->u.f4.fld.ahb1rstr.dma1rst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "DMA1RST"); + state->u.f4.fld.ahb1rstr.dma2rst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "DMA2RST"); + state->u.f4.fld.ahb1rstr.ethmacrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "ETHMACRST"); + state->u.f4.fld.ahb1rstr.otghsrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "OTGHSRST"); + + // AHB2RSTR bitfields. + state->u.f4.fld.ahb2rstr.dcmirst = cm_object_get_child_by_name(state->u.f4.reg.ahb2rstr, "DCMIRST"); + state->u.f4.fld.ahb2rstr.rngrst = cm_object_get_child_by_name(state->u.f4.reg.ahb2rstr, "RNGRST"); + state->u.f4.fld.ahb2rstr.otgfsrst = cm_object_get_child_by_name(state->u.f4.reg.ahb2rstr, "OTGFSRST"); + + // AHB3RSTR bitfields. + state->u.f4.fld.ahb3rstr.fsmcrst = cm_object_get_child_by_name(state->u.f4.reg.ahb3rstr, "FSMCRST"); + + // APB1RSTR bitfields. + state->u.f4.fld.apb1rstr.tim2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM2RST"); + state->u.f4.fld.apb1rstr.tim3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM3RST"); + state->u.f4.fld.apb1rstr.tim4rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM4RST"); + state->u.f4.fld.apb1rstr.tim5rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM5RST"); + state->u.f4.fld.apb1rstr.tim6rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM6RST"); + state->u.f4.fld.apb1rstr.tim7rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM7RST"); + state->u.f4.fld.apb1rstr.tim12rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM12RST"); + state->u.f4.fld.apb1rstr.tim13rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM13RST"); + state->u.f4.fld.apb1rstr.tim14rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM14RST"); + state->u.f4.fld.apb1rstr.wwdgrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "WWDGRST"); + state->u.f4.fld.apb1rstr.spi2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "SPI2RST"); + state->u.f4.fld.apb1rstr.spi3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "SPI3RST"); + state->u.f4.fld.apb1rstr.uart2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART2RST"); + state->u.f4.fld.apb1rstr.uart3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART3RST"); + state->u.f4.fld.apb1rstr.uart4rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART4RST"); + state->u.f4.fld.apb1rstr.uart5rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART5RST"); + state->u.f4.fld.apb1rstr.i2c1rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C1RST"); + state->u.f4.fld.apb1rstr.i2c2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C2RST"); + state->u.f4.fld.apb1rstr.i2c3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C3RST"); + state->u.f4.fld.apb1rstr.can1rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "CAN1RST"); + state->u.f4.fld.apb1rstr.can2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "CAN2RST"); + state->u.f4.fld.apb1rstr.pwrrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "PWRRST"); + state->u.f4.fld.apb1rstr.dacrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "DACRST"); + + // APB2RSTR bitfields. + state->u.f4.fld.apb2rstr.tim1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM1RST"); + state->u.f4.fld.apb2rstr.tim8rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM8RST"); + state->u.f4.fld.apb2rstr.usart1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "USART1RST"); + state->u.f4.fld.apb2rstr.usart6rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "USART6RST"); + state->u.f4.fld.apb2rstr.adcrst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "ADCRST"); + state->u.f4.fld.apb2rstr.sdiorst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SDIORST"); + state->u.f4.fld.apb2rstr.spi1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SPI1RST"); + state->u.f4.fld.apb2rstr.syscfgrst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SYSCFGRST"); + state->u.f4.fld.apb2rstr.tim9rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM9RST"); + state->u.f4.fld.apb2rstr.tim10rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM10RST"); + state->u.f4.fld.apb2rstr.tim11rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM11RST"); + + // AHB1ENR bitfields. + state->u.f4.fld.ahb1enr.gpioaen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOAEN"); + state->u.f4.fld.ahb1enr.gpioben = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOBEN"); + state->u.f4.fld.ahb1enr.gpiocen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOCEN"); + state->u.f4.fld.ahb1enr.gpioden = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIODEN"); + state->u.f4.fld.ahb1enr.gpioeen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOEEN"); + state->u.f4.fld.ahb1enr.gpiofen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOFEN"); + state->u.f4.fld.ahb1enr.gpiogen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOGEN"); + state->u.f4.fld.ahb1enr.gpiohen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOHEN"); + state->u.f4.fld.ahb1enr.gpioien = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOIEN"); + state->u.f4.fld.ahb1enr.crcen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "CRCEN"); + state->u.f4.fld.ahb1enr.bkpsramen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "BKPSRAMEN"); + state->u.f4.fld.ahb1enr.dma1en = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "DMA1EN"); + state->u.f4.fld.ahb1enr.dma2en = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "DMA2EN"); + state->u.f4.fld.ahb1enr.ethmacen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACEN"); + state->u.f4.fld.ahb1enr.ethmactxen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACTXEN"); + state->u.f4.fld.ahb1enr.ethmacrxen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACRXEN"); + state->u.f4.fld.ahb1enr.ethmacptpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACPTPEN"); + state->u.f4.fld.ahb1enr.otghsen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "OTGHSEN"); + state->u.f4.fld.ahb1enr.otghsulpien = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "OTGHSULPIEN"); + + // AHB2ENR bitfields. + state->u.f4.fld.ahb2enr.dcmien = cm_object_get_child_by_name(state->u.f4.reg.ahb2enr, "DCMIEN"); + state->u.f4.fld.ahb2enr.rngen = cm_object_get_child_by_name(state->u.f4.reg.ahb2enr, "RNGEN"); + state->u.f4.fld.ahb2enr.otgfsen = cm_object_get_child_by_name(state->u.f4.reg.ahb2enr, "OTGFSEN"); + + // AHB3ENR bitfields. + state->u.f4.fld.ahb3enr.fsmcen = cm_object_get_child_by_name(state->u.f4.reg.ahb3enr, "FSMCEN"); + + // APB1ENR bitfields. + state->u.f4.fld.apb1enr.tim2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM2EN"); + state->u.f4.fld.apb1enr.tim3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM3EN"); + state->u.f4.fld.apb1enr.tim4en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM4EN"); + state->u.f4.fld.apb1enr.tim5en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM5EN"); + state->u.f4.fld.apb1enr.tim6en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM6EN"); + state->u.f4.fld.apb1enr.tim7en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM7EN"); + state->u.f4.fld.apb1enr.tim12en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM12EN"); + state->u.f4.fld.apb1enr.tim13en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM13EN"); + state->u.f4.fld.apb1enr.tim14en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM14EN"); + state->u.f4.fld.apb1enr.wwdgen = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "WWDGEN"); + state->u.f4.fld.apb1enr.spi2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "SPI2EN"); + state->u.f4.fld.apb1enr.spi3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "SPI3EN"); + state->u.f4.fld.apb1enr.usart2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "USART2EN"); + state->u.f4.fld.apb1enr.usart3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "USART3EN"); + state->u.f4.fld.apb1enr.uart4en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "UART4EN"); + state->u.f4.fld.apb1enr.uart5en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "UART5EN"); + state->u.f4.fld.apb1enr.i2c1en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C1EN"); + state->u.f4.fld.apb1enr.i2c2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C2EN"); + state->u.f4.fld.apb1enr.i2c3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C3EN"); + state->u.f4.fld.apb1enr.can1en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "CAN1EN"); + state->u.f4.fld.apb1enr.can2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "CAN2EN"); + state->u.f4.fld.apb1enr.pwren = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "PWREN"); + state->u.f4.fld.apb1enr.dacen = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "DACEN"); + + // APB2ENR bitfields. + state->u.f4.fld.apb2enr.tim1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM1EN"); + state->u.f4.fld.apb2enr.tim8en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM8EN"); + state->u.f4.fld.apb2enr.usart1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "USART1EN"); + state->u.f4.fld.apb2enr.usart6en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "USART6EN"); + state->u.f4.fld.apb2enr.adc1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "ADC1EN"); + state->u.f4.fld.apb2enr.adc2en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "ADC2EN"); + state->u.f4.fld.apb2enr.adc3en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "ADC3EN"); + state->u.f4.fld.apb2enr.sdioen = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SDIOEN"); + state->u.f4.fld.apb2enr.spi1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SPI1EN"); + state->u.f4.fld.apb2enr.syscfgen = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SYSCFGEN"); + state->u.f4.fld.apb2enr.tim9en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM9EN"); + state->u.f4.fld.apb2enr.tim10en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM10EN"); + state->u.f4.fld.apb2enr.tim11en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM11EN"); + + // AHB1LPENR bitfields. + state->u.f4.fld.ahb1lpenr.gpioalpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOALPEN"); + state->u.f4.fld.ahb1lpenr.gpioblpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOBLPEN"); + state->u.f4.fld.ahb1lpenr.gpioclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOCLPEN"); + state->u.f4.fld.ahb1lpenr.gpiodlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIODLPEN"); + state->u.f4.fld.ahb1lpenr.gpioelpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOELPEN"); + state->u.f4.fld.ahb1lpenr.gpioflpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOFLPEN"); + state->u.f4.fld.ahb1lpenr.gpioglpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOGLPEN"); + state->u.f4.fld.ahb1lpenr.gpiohlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOHLPEN"); + state->u.f4.fld.ahb1lpenr.gpioilpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOILPEN"); + state->u.f4.fld.ahb1lpenr.crclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "CRCLPEN"); + state->u.f4.fld.ahb1lpenr.flitflpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "FLITFLPEN"); + state->u.f4.fld.ahb1lpenr.sram1lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "SRAM1LPEN"); + state->u.f4.fld.ahb1lpenr.sram2lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "SRAM2LPEN"); + state->u.f4.fld.ahb1lpenr.bkpsramlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "BKPSRAMLPEN"); + state->u.f4.fld.ahb1lpenr.dma1lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "DMA1LPEN"); + state->u.f4.fld.ahb1lpenr.dma2lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "DMA2LPEN"); + state->u.f4.fld.ahb1lpenr.ethmaclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACLPEN"); + state->u.f4.fld.ahb1lpenr.ethmactxlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACTXLPEN"); + state->u.f4.fld.ahb1lpenr.ethmacrxlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACRXLPEN"); + state->u.f4.fld.ahb1lpenr.ethmacptplpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACPTPLPEN"); + state->u.f4.fld.ahb1lpenr.otghslpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "OTGHSLPEN"); + state->u.f4.fld.ahb1lpenr.otghsulpilpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "OTGHSULPILPEN"); + + // AHB2LPENR bitfields. + state->u.f4.fld.ahb2lpenr.dcmilpen = cm_object_get_child_by_name(state->u.f4.reg.ahb2lpenr, "DCMILPEN"); + state->u.f4.fld.ahb2lpenr.rnglpen = cm_object_get_child_by_name(state->u.f4.reg.ahb2lpenr, "RNGLPEN"); + state->u.f4.fld.ahb2lpenr.otgfslpen = cm_object_get_child_by_name(state->u.f4.reg.ahb2lpenr, "OTGFSLPEN"); + + // AHB3LPENR bitfields. + state->u.f4.fld.ahb3lpenr.fsmclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb3lpenr, "FSMCLPEN"); + + // APB1LPENR bitfields. + state->u.f4.fld.apb1lpenr.tim2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM2LPEN"); + state->u.f4.fld.apb1lpenr.tim3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM3LPEN"); + state->u.f4.fld.apb1lpenr.tim4lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM4LPEN"); + state->u.f4.fld.apb1lpenr.tim5lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM5LPEN"); + state->u.f4.fld.apb1lpenr.tim6lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM6LPEN"); + state->u.f4.fld.apb1lpenr.tim7lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM7LPEN"); + state->u.f4.fld.apb1lpenr.tim12lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM12LPEN"); + state->u.f4.fld.apb1lpenr.tim13lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM13LPEN"); + state->u.f4.fld.apb1lpenr.tim14lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM14LPEN"); + state->u.f4.fld.apb1lpenr.wwdglpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "WWDGLPEN"); + state->u.f4.fld.apb1lpenr.spi2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "SPI2LPEN"); + state->u.f4.fld.apb1lpenr.spi3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "SPI3LPEN"); + state->u.f4.fld.apb1lpenr.usart2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "USART2LPEN"); + state->u.f4.fld.apb1lpenr.usart3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "USART3LPEN"); + state->u.f4.fld.apb1lpenr.uart4lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "UART4LPEN"); + state->u.f4.fld.apb1lpenr.uart5lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "UART5LPEN"); + state->u.f4.fld.apb1lpenr.i2c1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C1LPEN"); + state->u.f4.fld.apb1lpenr.i2c2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C2LPEN"); + state->u.f4.fld.apb1lpenr.i2c3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C3LPEN"); + state->u.f4.fld.apb1lpenr.can1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "CAN1LPEN"); + state->u.f4.fld.apb1lpenr.can2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "CAN2LPEN"); + state->u.f4.fld.apb1lpenr.pwrlpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "PWRLPEN"); + state->u.f4.fld.apb1lpenr.daclpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "DACLPEN"); + + // APB2LPENR bitfields. + state->u.f4.fld.apb2lpenr.tim1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM1LPEN"); + state->u.f4.fld.apb2lpenr.tim8lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM8LPEN"); + state->u.f4.fld.apb2lpenr.usart1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "USART1LPEN"); + state->u.f4.fld.apb2lpenr.usart6lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "USART6LPEN"); + state->u.f4.fld.apb2lpenr.adc1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "ADC1LPEN"); + state->u.f4.fld.apb2lpenr.adc2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "ADC2LPEN"); + state->u.f4.fld.apb2lpenr.adc3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "ADC3LPEN"); + state->u.f4.fld.apb2lpenr.sdiolpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SDIOLPEN"); + state->u.f4.fld.apb2lpenr.spi1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SPI1LPEN"); + state->u.f4.fld.apb2lpenr.syscfglpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SYSCFGLPEN"); + state->u.f4.fld.apb2lpenr.tim9lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM9LPEN"); + state->u.f4.fld.apb2lpenr.tim10lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM10LPEN"); + state->u.f4.fld.apb2lpenr.tim11lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM11LPEN"); + + // BDCR bitfields. + state->u.f4.fld.bdcr.lseon = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSEON"); + state->u.f4.fld.bdcr.lserdy = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSERDY"); + state->u.f4.fld.bdcr.lsebyp = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSEBYP"); + state->u.f4.fld.bdcr.rtcsel = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "RTCSEL"); + state->u.f4.fld.bdcr.rtcen = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "RTCEN"); + state->u.f4.fld.bdcr.bdrst = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "BDRST"); + + // CSR bitfields. + state->u.f4.fld.csr.lsion = cm_object_get_child_by_name(state->u.f4.reg.csr, "LSION"); + state->u.f4.fld.csr.lsirdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "LSIRDY"); + state->u.f4.fld.csr.rmvf = cm_object_get_child_by_name(state->u.f4.reg.csr, "RMVF"); + state->u.f4.fld.csr.borrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "BORRSTF"); + state->u.f4.fld.csr.padrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "PADRSTF"); + state->u.f4.fld.csr.porrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "PORRSTF"); + state->u.f4.fld.csr.sftrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "SFTRSTF"); + state->u.f4.fld.csr.wdgrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WDGRSTF"); + state->u.f4.fld.csr.wwdgrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WWDGRSTF"); + state->u.f4.fld.csr.lpwrrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "LPWRRSTF"); + + // SSCGR bitfields. + state->u.f4.fld.sscgr.modper = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "MODPER"); + state->u.f4.fld.sscgr.incstep = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "INCSTEP"); + state->u.f4.fld.sscgr.spreadsel = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "SPREADSEL"); + state->u.f4.fld.sscgr.sscgen = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "SSCGEN"); + + // PLLI2SCFGR bitfields. + state->u.f4.fld.plli2scfgr.plli2snx = cm_object_get_child_by_name(state->u.f4.reg.plli2scfgr, "PLLI2SNx"); + state->u.f4.fld.plli2scfgr.plli2srx = cm_object_get_child_by_name(state->u.f4.reg.plli2scfgr, "PLLI2SRx"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rcc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rcc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rcc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rcc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rcc_is_enabled(Object *obj) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rcc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RCCState *state = STM32_RCC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rcc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RCC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RCCState *state = STM32_RCC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RCC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_rcc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rcc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rcc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rcc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rcc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RCCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rcc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RCC); +} + +static void stm32_rcc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rcc_reset_callback; + dc->realize = stm32_rcc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rcc_is_enabled; +} + +static const TypeInfo stm32_rcc_type_info = { + .name = TYPE_STM32_RCC, + .parent = TYPE_STM32_RCC_PARENT, + .instance_init = stm32_rcc_instance_init_callback, + .instance_size = sizeof(STM32RCCState), + .class_init = stm32_rcc_class_init_callback, + .class_size = sizeof(STM32RCCClass) }; + +static void stm32_rcc_register_types(void) +{ + type_register_static(&stm32_rcc_type_info); +} + +type_init(stm32_rcc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/rcc.h b/gnu-mcu-eclipse/devices/support/STM32F40x/rcc.h new file mode 100644 index 0000000000..3dbf243341 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/rcc.h @@ -0,0 +1,457 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RCC_H_ +#define STM32_RCC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RCC DEVICE_PATH_STM32 "RCC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RCC TYPE_STM32_PREFIX "rcc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RCC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RCCParentClass; +typedef PeripheralState STM32RCCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RCCClass, (obj), TYPE_STM32_RCC) +#define STM32_RCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RCCClass, (klass), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentClass parent_class; + // public: + + // None, so far. +} STM32RCCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RCC_STATE(obj) \ + OBJECT_CHECK(STM32RCCState, (obj), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RCC (Reset and clock control) registers. + struct { + Object *cr; // 0x0 (Clock control register) + Object *pllcfgr; // 0x4 (PLL configuration register) + Object *cfgr; // 0x8 (Clock configuration register) + Object *cir; // 0xC (Clock interrupt register) + Object *ahb1rstr; // 0x10 (AHB1 peripheral reset register) + Object *ahb2rstr; // 0x14 (AHB2 peripheral reset register) + Object *ahb3rstr; // 0x18 (AHB3 peripheral reset register) + Object *apb1rstr; // 0x20 (APB1 peripheral reset register) + Object *apb2rstr; // 0x24 (APB2 peripheral reset register) + Object *ahb1enr; // 0x30 (AHB1 peripheral clock register) + Object *ahb2enr; // 0x34 (AHB2 peripheral clock enable register) + Object *ahb3enr; // 0x38 (AHB3 peripheral clock enable register) + Object *apb1enr; // 0x40 (APB1 peripheral clock enable register) + Object *apb2enr; // 0x44 (APB2 peripheral clock enable register) + Object *ahb1lpenr; // 0x50 (AHB1 peripheral clock enable in low power mode register) + Object *ahb2lpenr; // 0x54 (AHB2 peripheral clock enable in low power mode register) + Object *ahb3lpenr; // 0x58 (AHB3 peripheral clock enable in low power mode register) + Object *apb1lpenr; // 0x60 (APB1 peripheral clock enable in low power mode register) + Object *apb2lpenr; // 0x64 (APB2 peripheral clock enabled in low power mode register) + Object *bdcr; // 0x70 (Backup domain control register) + Object *csr; // 0x74 (Clock control & status register) + Object *sscgr; // 0x80 (Spread spectrum clock generation register) + Object *plli2scfgr; // 0x84 (PLLI2S configuration register) + } reg; + + struct { + + // CR (Clock control register) bitfields. + struct { + Object *hsion; // [0:0] Internal high-speed clock enable + Object *hsirdy; // [1:1] Internal high-speed clock ready flag + Object *hsitrim; // [3:7] Internal high-speed clock trimming + Object *hsical; // [8:15] Internal high-speed clock calibration + Object *hseon; // [16:16] HSE clock enable + Object *hserdy; // [17:17] HSE clock ready flag + Object *hsebyp; // [18:18] HSE clock bypass + Object *csson; // [19:19] Clock security system enable + Object *pllon; // [24:24] Main PLL (PLL) enable + Object *pllrdy; // [25:25] Main PLL (PLL) clock ready flag + Object *plli2son; // [26:26] PLLI2S enable + Object *plli2srdy; // [27:27] PLLI2S clock ready flag + } cr; + + // PLLCFGR (PLL configuration register) bitfields. + struct { + Object *pllm; // [0:5] Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + Object *plln; // [6:14] Main PLL (PLL) multiplication factor for VCO + Object *pllp; // [16:17] Main PLL (PLL) division factor for main system clock + Object *pllsrc; // [22:22] Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + Object *pllq; // [24:27] Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + } pllcfgr; + + // CFGR (Clock configuration register) bitfields. + struct { + Object *sw; // [0:1] System clock switch + Object *sws; // [2:3] System clock switch status + Object *hpre; // [4:7] AHB prescaler + Object *ppre1; // [10:12] APB Low speed prescaler (APB1) + Object *ppre2; // [13:15] APB high-speed prescaler (APB2) + Object *rtcpre; // [16:20] HSE division factor for RTC clock + Object *mco1; // [21:22] Microcontroller clock output 1 + Object *i2ssrc; // [23:23] I2S clock selection + Object *mco1pre; // [24:26] MCO1 prescaler + Object *mco2pre; // [27:29] MCO2 prescaler + Object *mco2; // [30:31] Microcontroller clock output 2 + } cfgr; + + // CIR (Clock interrupt register) bitfields. + struct { + Object *lsirdyf; // [0:0] LSI ready interrupt flag + Object *lserdyf; // [1:1] LSE ready interrupt flag + Object *hsirdyf; // [2:2] HSI ready interrupt flag + Object *hserdyf; // [3:3] HSE ready interrupt flag + Object *pllrdyf; // [4:4] Main PLL (PLL) ready interrupt flag + Object *plli2srdyf; // [5:5] PLLI2S ready interrupt flag + Object *cssf; // [7:7] Clock security system interrupt flag + Object *lsirdyie; // [8:8] LSI ready interrupt enable + Object *lserdyie; // [9:9] LSE ready interrupt enable + Object *hsirdyie; // [10:10] HSI ready interrupt enable + Object *hserdyie; // [11:11] HSE ready interrupt enable + Object *pllrdyie; // [12:12] Main PLL (PLL) ready interrupt enable + Object *plli2srdyie; // [13:13] PLLI2S ready interrupt enable + Object *lsirdyc; // [16:16] LSI ready interrupt clear + Object *lserdyc; // [17:17] LSE ready interrupt clear + Object *hsirdyc; // [18:18] HSI ready interrupt clear + Object *hserdyc; // [19:19] HSE ready interrupt clear + Object *pllrdyc; // [20:20] Main PLL(PLL) ready interrupt clear + Object *plli2srdyc; // [21:21] PLLI2S ready interrupt clear + Object *cssc; // [23:23] Clock security system interrupt clear + } cir; + + // AHB1RSTR (AHB1 peripheral reset register) bitfields. + struct { + Object *gpioarst; // [0:0] IO port A reset + Object *gpiobrst; // [1:1] IO port B reset + Object *gpiocrst; // [2:2] IO port C reset + Object *gpiodrst; // [3:3] IO port D reset + Object *gpioerst; // [4:4] IO port E reset + Object *gpiofrst; // [5:5] IO port F reset + Object *gpiogrst; // [6:6] IO port G reset + Object *gpiohrst; // [7:7] IO port H reset + Object *gpioirst; // [8:8] IO port I reset + Object *crcrst; // [12:12] CRC reset + Object *dma1rst; // [21:21] DMA2 reset + Object *dma2rst; // [22:22] DMA2 reset + Object *ethmacrst; // [25:25] Ethernet MAC reset + Object *otghsrst; // [29:29] USB OTG HS module reset + } ahb1rstr; + + // AHB2RSTR (AHB2 peripheral reset register) bitfields. + struct { + Object *dcmirst; // [0:0] Camera interface reset + Object *rngrst; // [6:6] Random number generator module reset + Object *otgfsrst; // [7:7] USB OTG FS module reset + } ahb2rstr; + + // AHB3RSTR (AHB3 peripheral reset register) bitfields. + struct { + Object *fsmcrst; // [0:0] Flexible static memory controller module reset + } ahb3rstr; + + // APB1RSTR (APB1 peripheral reset register) bitfields. + struct { + Object *tim2rst; // [0:0] TIM2 reset + Object *tim3rst; // [1:1] TIM3 reset + Object *tim4rst; // [2:2] TIM4 reset + Object *tim5rst; // [3:3] TIM5 reset + Object *tim6rst; // [4:4] TIM6 reset + Object *tim7rst; // [5:5] TIM7 reset + Object *tim12rst; // [6:6] TIM12 reset + Object *tim13rst; // [7:7] TIM13 reset + Object *tim14rst; // [8:8] TIM14 reset + Object *wwdgrst; // [11:11] Window watchdog reset + Object *spi2rst; // [14:14] SPI 2 reset + Object *spi3rst; // [15:15] SPI 3 reset + Object *uart2rst; // [17:17] USART 2 reset + Object *uart3rst; // [18:18] USART 3 reset + Object *uart4rst; // [19:19] USART 4 reset + Object *uart5rst; // [20:20] USART 5 reset + Object *i2c1rst; // [21:21] I2C 1 reset + Object *i2c2rst; // [22:22] I2C 2 reset + Object *i2c3rst; // [23:23] I2C3 reset + Object *can1rst; // [25:25] CAN1 reset + Object *can2rst; // [26:26] CAN2 reset + Object *pwrrst; // [28:28] Power interface reset + Object *dacrst; // [29:29] DAC reset + } apb1rstr; + + // APB2RSTR (APB2 peripheral reset register) bitfields. + struct { + Object *tim1rst; // [0:0] TIM1 reset + Object *tim8rst; // [1:1] TIM8 reset + Object *usart1rst; // [4:4] USART1 reset + Object *usart6rst; // [5:5] USART6 reset + Object *adcrst; // [8:8] ADC interface reset (common to all ADCs) + Object *sdiorst; // [11:11] SDIO reset + Object *spi1rst; // [12:12] SPI 1 reset + Object *syscfgrst; // [14:14] System configuration controller reset + Object *tim9rst; // [16:16] TIM9 reset + Object *tim10rst; // [17:17] TIM10 reset + Object *tim11rst; // [18:18] TIM11 reset + } apb2rstr; + + // AHB1ENR (AHB1 peripheral clock register) bitfields. + struct { + Object *gpioaen; // [0:0] IO port A clock enable + Object *gpioben; // [1:1] IO port B clock enable + Object *gpiocen; // [2:2] IO port C clock enable + Object *gpioden; // [3:3] IO port D clock enable + Object *gpioeen; // [4:4] IO port E clock enable + Object *gpiofen; // [5:5] IO port F clock enable + Object *gpiogen; // [6:6] IO port G clock enable + Object *gpiohen; // [7:7] IO port H clock enable + Object *gpioien; // [8:8] IO port I clock enable + Object *crcen; // [12:12] CRC clock enable + Object *bkpsramen; // [18:18] Backup SRAM interface clock enable + Object *dma1en; // [21:21] DMA1 clock enable + Object *dma2en; // [22:22] DMA2 clock enable + Object *ethmacen; // [25:25] Ethernet MAC clock enable + Object *ethmactxen; // [26:26] Ethernet Transmission clock enable + Object *ethmacrxen; // [27:27] Ethernet Reception clock enable + Object *ethmacptpen; // [28:28] Ethernet PTP clock enable + Object *otghsen; // [29:29] USB OTG HS clock enable + Object *otghsulpien; // [30:30] USB OTG HSULPI clock enable + } ahb1enr; + + // AHB2ENR (AHB2 peripheral clock enable register) bitfields. + struct { + Object *dcmien; // [0:0] Camera interface enable + Object *rngen; // [6:6] Random number generator clock enable + Object *otgfsen; // [7:7] USB OTG FS clock enable + } ahb2enr; + + // AHB3ENR (AHB3 peripheral clock enable register) bitfields. + struct { + Object *fsmcen; // [0:0] Flexible static memory controller module clock enable + } ahb3enr; + + // APB1ENR (APB1 peripheral clock enable register) bitfields. + struct { + Object *tim2en; // [0:0] TIM2 clock enable + Object *tim3en; // [1:1] TIM3 clock enable + Object *tim4en; // [2:2] TIM4 clock enable + Object *tim5en; // [3:3] TIM5 clock enable + Object *tim6en; // [4:4] TIM6 clock enable + Object *tim7en; // [5:5] TIM7 clock enable + Object *tim12en; // [6:6] TIM12 clock enable + Object *tim13en; // [7:7] TIM13 clock enable + Object *tim14en; // [8:8] TIM14 clock enable + Object *wwdgen; // [11:11] Window watchdog clock enable + Object *spi2en; // [14:14] SPI2 clock enable + Object *spi3en; // [15:15] SPI3 clock enable + Object *usart2en; // [17:17] USART 2 clock enable + Object *usart3en; // [18:18] USART3 clock enable + Object *uart4en; // [19:19] UART4 clock enable + Object *uart5en; // [20:20] UART5 clock enable + Object *i2c1en; // [21:21] I2C1 clock enable + Object *i2c2en; // [22:22] I2C2 clock enable + Object *i2c3en; // [23:23] I2C3 clock enable + Object *can1en; // [25:25] CAN 1 clock enable + Object *can2en; // [26:26] CAN 2 clock enable + Object *pwren; // [28:28] Power interface clock enable + Object *dacen; // [29:29] DAC interface clock enable + } apb1enr; + + // APB2ENR (APB2 peripheral clock enable register) bitfields. + struct { + Object *tim1en; // [0:0] TIM1 clock enable + Object *tim8en; // [1:1] TIM8 clock enable + Object *usart1en; // [4:4] USART1 clock enable + Object *usart6en; // [5:5] USART6 clock enable + Object *adc1en; // [8:8] ADC1 clock enable + Object *adc2en; // [9:9] ADC2 clock enable + Object *adc3en; // [10:10] ADC3 clock enable + Object *sdioen; // [11:11] SDIO clock enable + Object *spi1en; // [12:12] SPI1 clock enable + Object *syscfgen; // [14:14] System configuration controller clock enable + Object *tim9en; // [16:16] TIM9 clock enable + Object *tim10en; // [17:17] TIM10 clock enable + Object *tim11en; // [18:18] TIM11 clock enable + } apb2enr; + + // AHB1LPENR (AHB1 peripheral clock enable in low power mode register) bitfields. + struct { + Object *gpioalpen; // [0:0] IO port A clock enable during sleep mode + Object *gpioblpen; // [1:1] IO port B clock enable during Sleep mode + Object *gpioclpen; // [2:2] IO port C clock enable during Sleep mode + Object *gpiodlpen; // [3:3] IO port D clock enable during Sleep mode + Object *gpioelpen; // [4:4] IO port E clock enable during Sleep mode + Object *gpioflpen; // [5:5] IO port F clock enable during Sleep mode + Object *gpioglpen; // [6:6] IO port G clock enable during Sleep mode + Object *gpiohlpen; // [7:7] IO port H clock enable during Sleep mode + Object *gpioilpen; // [8:8] IO port I clock enable during Sleep mode + Object *crclpen; // [12:12] CRC clock enable during Sleep mode + Object *flitflpen; // [15:15] Flash interface clock enable during Sleep mode + Object *sram1lpen; // [16:16] SRAM 1interface clock enable during Sleep mode + Object *sram2lpen; // [17:17] SRAM 2 interface clock enable during Sleep mode + Object *bkpsramlpen; // [18:18] Backup SRAM interface clock enable during Sleep mode + Object *dma1lpen; // [21:21] DMA1 clock enable during Sleep mode + Object *dma2lpen; // [22:22] DMA2 clock enable during Sleep mode + Object *ethmaclpen; // [25:25] Ethernet MAC clock enable during Sleep mode + Object *ethmactxlpen; // [26:26] Ethernet transmission clock enable during Sleep mode + Object *ethmacrxlpen; // [27:27] Ethernet reception clock enable during Sleep mode + Object *ethmacptplpen; // [28:28] Ethernet PTP clock enable during Sleep mode + Object *otghslpen; // [29:29] USB OTG HS clock enable during Sleep mode + Object *otghsulpilpen; // [30:30] USB OTG HS ULPI clock enable during Sleep mode + } ahb1lpenr; + + // AHB2LPENR (AHB2 peripheral clock enable in low power mode register) bitfields. + struct { + Object *dcmilpen; // [0:0] Camera interface enable during Sleep mode + Object *rnglpen; // [6:6] Random number generator clock enable during Sleep mode + Object *otgfslpen; // [7:7] USB OTG FS clock enable during Sleep mode + } ahb2lpenr; + + // AHB3LPENR (AHB3 peripheral clock enable in low power mode register) bitfields. + struct { + Object *fsmclpen; // [0:0] Flexible static memory controller module clock enable during Sleep mode + } ahb3lpenr; + + // APB1LPENR (APB1 peripheral clock enable in low power mode register) bitfields. + struct { + Object *tim2lpen; // [0:0] TIM2 clock enable during Sleep mode + Object *tim3lpen; // [1:1] TIM3 clock enable during Sleep mode + Object *tim4lpen; // [2:2] TIM4 clock enable during Sleep mode + Object *tim5lpen; // [3:3] TIM5 clock enable during Sleep mode + Object *tim6lpen; // [4:4] TIM6 clock enable during Sleep mode + Object *tim7lpen; // [5:5] TIM7 clock enable during Sleep mode + Object *tim12lpen; // [6:6] TIM12 clock enable during Sleep mode + Object *tim13lpen; // [7:7] TIM13 clock enable during Sleep mode + Object *tim14lpen; // [8:8] TIM14 clock enable during Sleep mode + Object *wwdglpen; // [11:11] Window watchdog clock enable during Sleep mode + Object *spi2lpen; // [14:14] SPI2 clock enable during Sleep mode + Object *spi3lpen; // [15:15] SPI3 clock enable during Sleep mode + Object *usart2lpen; // [17:17] USART2 clock enable during Sleep mode + Object *usart3lpen; // [18:18] USART3 clock enable during Sleep mode + Object *uart4lpen; // [19:19] UART4 clock enable during Sleep mode + Object *uart5lpen; // [20:20] UART5 clock enable during Sleep mode + Object *i2c1lpen; // [21:21] I2C1 clock enable during Sleep mode + Object *i2c2lpen; // [22:22] I2C2 clock enable during Sleep mode + Object *i2c3lpen; // [23:23] I2C3 clock enable during Sleep mode + Object *can1lpen; // [25:25] CAN 1 clock enable during Sleep mode + Object *can2lpen; // [26:26] CAN 2 clock enable during Sleep mode + Object *pwrlpen; // [28:28] Power interface clock enable during Sleep mode + Object *daclpen; // [29:29] DAC interface clock enable during Sleep mode + } apb1lpenr; + + // APB2LPENR (APB2 peripheral clock enabled in low power mode register) bitfields. + struct { + Object *tim1lpen; // [0:0] TIM1 clock enable during Sleep mode + Object *tim8lpen; // [1:1] TIM8 clock enable during Sleep mode + Object *usart1lpen; // [4:4] USART1 clock enable during Sleep mode + Object *usart6lpen; // [5:5] USART6 clock enable during Sleep mode + Object *adc1lpen; // [8:8] ADC1 clock enable during Sleep mode + Object *adc2lpen; // [9:9] ADC2 clock enable during Sleep mode + Object *adc3lpen; // [10:10] ADC 3 clock enable during Sleep mode + Object *sdiolpen; // [11:11] SDIO clock enable during Sleep mode + Object *spi1lpen; // [12:12] SPI 1 clock enable during Sleep mode + Object *syscfglpen; // [14:14] System configuration controller clock enable during Sleep mode + Object *tim9lpen; // [16:16] TIM9 clock enable during sleep mode + Object *tim10lpen; // [17:17] TIM10 clock enable during Sleep mode + Object *tim11lpen; // [18:18] TIM11 clock enable during Sleep mode + } apb2lpenr; + + // BDCR (Backup domain control register) bitfields. + struct { + Object *lseon; // [0:0] External low-speed oscillator enable + Object *lserdy; // [1:1] External low-speed oscillator ready + Object *lsebyp; // [2:2] External low-speed oscillator bypass + Object *rtcsel; // [8:9] RTC clock source selection + Object *rtcen; // [15:15] RTC clock enable + Object *bdrst; // [16:16] Backup domain software reset + } bdcr; + + // CSR (Clock control & status register) bitfields. + struct { + Object *lsion; // [0:0] Internal low-speed oscillator enable + Object *lsirdy; // [1:1] Internal low-speed oscillator ready + Object *rmvf; // [24:24] Remove reset flag + Object *borrstf; // [25:25] BOR reset flag + Object *padrstf; // [26:26] PIN reset flag + Object *porrstf; // [27:27] POR/PDR reset flag + Object *sftrstf; // [28:28] Software reset flag + Object *wdgrstf; // [29:29] Independent watchdog reset flag + Object *wwdgrstf; // [30:30] Window watchdog reset flag + Object *lpwrrstf; // [31:31] Low-power reset flag + } csr; + + // SSCGR (Spread spectrum clock generation register) bitfields. + struct { + Object *modper; // [0:12] Modulation period + Object *incstep; // [13:27] Incrementation step + Object *spreadsel; // [30:30] Spread Select + Object *sscgen; // [31:31] Spread spectrum modulation enable + } sscgr; + + // PLLI2SCFGR (PLLI2S configuration register) bitfields. + struct { + Object *plli2snx; // [6:14] PLLI2S multiplication factor for VCO + Object *plli2srx; // [28:30] PLLI2S division factor for I2S clocks + } plli2scfgr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RCCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RCC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/rng.c b/gnu-mcu-eclipse/devices/support/STM32F40x/rng.c new file mode 100644 index 0000000000..ce542dec9a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/rng.c @@ -0,0 +1,251 @@ +/* + * STM32 - RNG (Random number generator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_rng_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RNGState *state = STM32_RNG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // CR bitfields. + state->u.f4.fld.cr.rngen = cm_object_get_child_by_name(state->u.f4.reg.cr, "RNGEN"); + state->u.f4.fld.cr.ie = cm_object_get_child_by_name(state->u.f4.reg.cr, "IE"); + + // SR bitfields. + state->u.f4.fld.sr.drdy = cm_object_get_child_by_name(state->u.f4.reg.sr, "DRDY"); + state->u.f4.fld.sr.cecs = cm_object_get_child_by_name(state->u.f4.reg.sr, "CECS"); + state->u.f4.fld.sr.secs = cm_object_get_child_by_name(state->u.f4.reg.sr, "SECS"); + state->u.f4.fld.sr.ceis = cm_object_get_child_by_name(state->u.f4.reg.sr, "CEIS"); + state->u.f4.fld.sr.seis = cm_object_get_child_by_name(state->u.f4.reg.sr, "SEIS"); + + // DR bitfields. + state->u.f4.fld.dr.rndata = cm_object_get_child_by_name(state->u.f4.reg.dr, "RNDATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rng_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rng_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rng_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rng_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rng_is_enabled(Object *obj) +{ + STM32RNGState *state = STM32_RNG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rng_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RNGState *state = STM32_RNG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rng_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RNG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RNGState *state = STM32_RNG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RNG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_rng_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rng_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rng_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rng_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rng_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RNGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rng_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RNG); +} + +static void stm32_rng_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rng_reset_callback; + dc->realize = stm32_rng_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rng_is_enabled; +} + +static const TypeInfo stm32_rng_type_info = { + .name = TYPE_STM32_RNG, + .parent = TYPE_STM32_RNG_PARENT, + .instance_init = stm32_rng_instance_init_callback, + .instance_size = sizeof(STM32RNGState), + .class_init = stm32_rng_class_init_callback, + .class_size = sizeof(STM32RNGClass) }; + +static void stm32_rng_register_types(void) +{ + type_register_static(&stm32_rng_type_info); +} + +type_init(stm32_rng_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/rng.h b/gnu-mcu-eclipse/devices/support/STM32F40x/rng.h new file mode 100644 index 0000000000..0bbc556a66 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/rng.h @@ -0,0 +1,122 @@ +/* + * STM32 - RNG (Random number generator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RNG_H_ +#define STM32_RNG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RNG DEVICE_PATH_STM32 "RNG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RNG TYPE_STM32_PREFIX "rng" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RNG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RNGParentClass; +typedef PeripheralState STM32RNGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RNG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RNGClass, (obj), TYPE_STM32_RNG) +#define STM32_RNG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RNGClass, (klass), TYPE_STM32_RNG) + +typedef struct { + // private: + STM32RNGParentClass parent_class; + // public: + + // None, so far. +} STM32RNGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RNG_STATE(obj) \ + OBJECT_CHECK(STM32RNGState, (obj), TYPE_STM32_RNG) + +typedef struct { + // private: + STM32RNGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RNG (Random number generator) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *sr; // 0x4 (Status register) + Object *dr; // 0x8 (Data register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *rngen; // [2:2] Random number generator enable + Object *ie; // [3:3] Interrupt enable + } cr; + + // SR (Status register) bitfields. + struct { + Object *drdy; // [0:0] Data ready + Object *cecs; // [1:1] Clock error current status + Object *secs; // [2:2] Seed error current status + Object *ceis; // [5:5] Clock error interrupt status + Object *seis; // [6:6] Seed error interrupt status + } sr; + + // DR (Data register) bitfields. + struct { + Object *rndata; // [0:31] Random data + } dr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RNGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RNG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/rtc.c b/gnu-mcu-eclipse/devices/support/STM32F40x/rtc.c new file mode 100644 index 0000000000..858543b9c3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/rtc.c @@ -0,0 +1,490 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_rtc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.tr = cm_object_get_child_by_name(obj, "TR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f4.reg.prer = cm_object_get_child_by_name(obj, "PRER"); + state->u.f4.reg.wutr = cm_object_get_child_by_name(obj, "WUTR"); + state->u.f4.reg.calibr = cm_object_get_child_by_name(obj, "CALIBR"); + state->u.f4.reg.alrmar = cm_object_get_child_by_name(obj, "ALRMAR"); + state->u.f4.reg.alrmbr = cm_object_get_child_by_name(obj, "ALRMBR"); + state->u.f4.reg.wpr = cm_object_get_child_by_name(obj, "WPR"); + state->u.f4.reg.ssr = cm_object_get_child_by_name(obj, "SSR"); + state->u.f4.reg.shiftr = cm_object_get_child_by_name(obj, "SHIFTR"); + state->u.f4.reg.tstr = cm_object_get_child_by_name(obj, "TSTR"); + state->u.f4.reg.tsdr = cm_object_get_child_by_name(obj, "TSDR"); + state->u.f4.reg.tsssr = cm_object_get_child_by_name(obj, "TSSSR"); + state->u.f4.reg.calr = cm_object_get_child_by_name(obj, "CALR"); + state->u.f4.reg.tafcr = cm_object_get_child_by_name(obj, "TAFCR"); + state->u.f4.reg.alrmassr = cm_object_get_child_by_name(obj, "ALRMASSR"); + state->u.f4.reg.alrmbssr = cm_object_get_child_by_name(obj, "ALRMBSSR"); + state->u.f4.reg.bkp0r = cm_object_get_child_by_name(obj, "BKP0R"); + state->u.f4.reg.bkp1r = cm_object_get_child_by_name(obj, "BKP1R"); + state->u.f4.reg.bkp2r = cm_object_get_child_by_name(obj, "BKP2R"); + state->u.f4.reg.bkp3r = cm_object_get_child_by_name(obj, "BKP3R"); + state->u.f4.reg.bkp4r = cm_object_get_child_by_name(obj, "BKP4R"); + state->u.f4.reg.bkp5r = cm_object_get_child_by_name(obj, "BKP5R"); + state->u.f4.reg.bkp6r = cm_object_get_child_by_name(obj, "BKP6R"); + state->u.f4.reg.bkp7r = cm_object_get_child_by_name(obj, "BKP7R"); + state->u.f4.reg.bkp8r = cm_object_get_child_by_name(obj, "BKP8R"); + state->u.f4.reg.bkp9r = cm_object_get_child_by_name(obj, "BKP9R"); + state->u.f4.reg.bkp10r = cm_object_get_child_by_name(obj, "BKP10R"); + state->u.f4.reg.bkp11r = cm_object_get_child_by_name(obj, "BKP11R"); + state->u.f4.reg.bkp12r = cm_object_get_child_by_name(obj, "BKP12R"); + state->u.f4.reg.bkp13r = cm_object_get_child_by_name(obj, "BKP13R"); + state->u.f4.reg.bkp14r = cm_object_get_child_by_name(obj, "BKP14R"); + state->u.f4.reg.bkp15r = cm_object_get_child_by_name(obj, "BKP15R"); + state->u.f4.reg.bkp16r = cm_object_get_child_by_name(obj, "BKP16R"); + state->u.f4.reg.bkp17r = cm_object_get_child_by_name(obj, "BKP17R"); + state->u.f4.reg.bkp18r = cm_object_get_child_by_name(obj, "BKP18R"); + state->u.f4.reg.bkp19r = cm_object_get_child_by_name(obj, "BKP19R"); + + + // TR bitfields. + state->u.f4.fld.tr.su = cm_object_get_child_by_name(state->u.f4.reg.tr, "SU"); + state->u.f4.fld.tr.st = cm_object_get_child_by_name(state->u.f4.reg.tr, "ST"); + state->u.f4.fld.tr.mnu = cm_object_get_child_by_name(state->u.f4.reg.tr, "MNU"); + state->u.f4.fld.tr.mnt = cm_object_get_child_by_name(state->u.f4.reg.tr, "MNT"); + state->u.f4.fld.tr.hu = cm_object_get_child_by_name(state->u.f4.reg.tr, "HU"); + state->u.f4.fld.tr.ht = cm_object_get_child_by_name(state->u.f4.reg.tr, "HT"); + state->u.f4.fld.tr.pm = cm_object_get_child_by_name(state->u.f4.reg.tr, "PM"); + + // DR bitfields. + state->u.f4.fld.dr.du = cm_object_get_child_by_name(state->u.f4.reg.dr, "DU"); + state->u.f4.fld.dr.dt = cm_object_get_child_by_name(state->u.f4.reg.dr, "DT"); + state->u.f4.fld.dr.mu = cm_object_get_child_by_name(state->u.f4.reg.dr, "MU"); + state->u.f4.fld.dr.mt = cm_object_get_child_by_name(state->u.f4.reg.dr, "MT"); + state->u.f4.fld.dr.wdu = cm_object_get_child_by_name(state->u.f4.reg.dr, "WDU"); + state->u.f4.fld.dr.yu = cm_object_get_child_by_name(state->u.f4.reg.dr, "YU"); + state->u.f4.fld.dr.yt = cm_object_get_child_by_name(state->u.f4.reg.dr, "YT"); + + // CR bitfields. + state->u.f4.fld.cr.wcksel = cm_object_get_child_by_name(state->u.f4.reg.cr, "WCKSEL"); + state->u.f4.fld.cr.tsedge = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSEDGE"); + state->u.f4.fld.cr.refckon = cm_object_get_child_by_name(state->u.f4.reg.cr, "REFCKON"); + state->u.f4.fld.cr.fmt = cm_object_get_child_by_name(state->u.f4.reg.cr, "FMT"); + state->u.f4.fld.cr.dce = cm_object_get_child_by_name(state->u.f4.reg.cr, "DCE"); + state->u.f4.fld.cr.alrae = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRAE"); + state->u.f4.fld.cr.alrbe = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRBE"); + state->u.f4.fld.cr.wute = cm_object_get_child_by_name(state->u.f4.reg.cr, "WUTE"); + state->u.f4.fld.cr.tse = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSE"); + state->u.f4.fld.cr.alraie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRAIE"); + state->u.f4.fld.cr.alrbie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRBIE"); + state->u.f4.fld.cr.wutie = cm_object_get_child_by_name(state->u.f4.reg.cr, "WUTIE"); + state->u.f4.fld.cr.tsie = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSIE"); + state->u.f4.fld.cr.add1h = cm_object_get_child_by_name(state->u.f4.reg.cr, "ADD1H"); + state->u.f4.fld.cr.sub1h = cm_object_get_child_by_name(state->u.f4.reg.cr, "SUB1H"); + state->u.f4.fld.cr.bkp = cm_object_get_child_by_name(state->u.f4.reg.cr, "BKP"); + state->u.f4.fld.cr.pol = cm_object_get_child_by_name(state->u.f4.reg.cr, "POL"); + state->u.f4.fld.cr.osel = cm_object_get_child_by_name(state->u.f4.reg.cr, "OSEL"); + state->u.f4.fld.cr.coe = cm_object_get_child_by_name(state->u.f4.reg.cr, "COE"); + + // ISR bitfields. + state->u.f4.fld.isr.alrawf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRAWF"); + state->u.f4.fld.isr.alrbwf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRBWF"); + state->u.f4.fld.isr.wutwf = cm_object_get_child_by_name(state->u.f4.reg.isr, "WUTWF"); + state->u.f4.fld.isr.shpf = cm_object_get_child_by_name(state->u.f4.reg.isr, "SHPF"); + state->u.f4.fld.isr.inits = cm_object_get_child_by_name(state->u.f4.reg.isr, "INITS"); + state->u.f4.fld.isr.rsf = cm_object_get_child_by_name(state->u.f4.reg.isr, "RSF"); + state->u.f4.fld.isr.initf = cm_object_get_child_by_name(state->u.f4.reg.isr, "INITF"); + state->u.f4.fld.isr.init = cm_object_get_child_by_name(state->u.f4.reg.isr, "INIT"); + state->u.f4.fld.isr.alraf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRAF"); + state->u.f4.fld.isr.alrbf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRBF"); + state->u.f4.fld.isr.wutf = cm_object_get_child_by_name(state->u.f4.reg.isr, "WUTF"); + state->u.f4.fld.isr.tsf = cm_object_get_child_by_name(state->u.f4.reg.isr, "TSF"); + state->u.f4.fld.isr.tsovf = cm_object_get_child_by_name(state->u.f4.reg.isr, "TSOVF"); + state->u.f4.fld.isr.tamp1f = cm_object_get_child_by_name(state->u.f4.reg.isr, "TAMP1F"); + state->u.f4.fld.isr.tamp2f = cm_object_get_child_by_name(state->u.f4.reg.isr, "TAMP2F"); + state->u.f4.fld.isr.recalpf = cm_object_get_child_by_name(state->u.f4.reg.isr, "RECALPF"); + + // PRER bitfields. + state->u.f4.fld.prer.prediv_s = cm_object_get_child_by_name(state->u.f4.reg.prer, "PREDIV_S"); + state->u.f4.fld.prer.prediv_a = cm_object_get_child_by_name(state->u.f4.reg.prer, "PREDIV_A"); + + // WUTR bitfields. + state->u.f4.fld.wutr.wut = cm_object_get_child_by_name(state->u.f4.reg.wutr, "WUT"); + + // CALIBR bitfields. + state->u.f4.fld.calibr.dc = cm_object_get_child_by_name(state->u.f4.reg.calibr, "DC"); + state->u.f4.fld.calibr.dcs = cm_object_get_child_by_name(state->u.f4.reg.calibr, "DCS"); + + // ALRMAR bitfields. + state->u.f4.fld.alrmar.su = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "SU"); + state->u.f4.fld.alrmar.st = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "ST"); + state->u.f4.fld.alrmar.msk1 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK1"); + state->u.f4.fld.alrmar.mnu = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MNU"); + state->u.f4.fld.alrmar.mnt = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MNT"); + state->u.f4.fld.alrmar.msk2 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK2"); + state->u.f4.fld.alrmar.hu = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "HU"); + state->u.f4.fld.alrmar.ht = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "HT"); + state->u.f4.fld.alrmar.pm = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "PM"); + state->u.f4.fld.alrmar.msk3 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK3"); + state->u.f4.fld.alrmar.du = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "DU"); + state->u.f4.fld.alrmar.dt = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "DT"); + state->u.f4.fld.alrmar.wdsel = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "WDSEL"); + state->u.f4.fld.alrmar.msk4 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK4"); + + // ALRMBR bitfields. + state->u.f4.fld.alrmbr.su = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "SU"); + state->u.f4.fld.alrmbr.st = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "ST"); + state->u.f4.fld.alrmbr.msk1 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK1"); + state->u.f4.fld.alrmbr.mnu = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MNU"); + state->u.f4.fld.alrmbr.mnt = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MNT"); + state->u.f4.fld.alrmbr.msk2 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK2"); + state->u.f4.fld.alrmbr.hu = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "HU"); + state->u.f4.fld.alrmbr.ht = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "HT"); + state->u.f4.fld.alrmbr.pm = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "PM"); + state->u.f4.fld.alrmbr.msk3 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK3"); + state->u.f4.fld.alrmbr.du = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "DU"); + state->u.f4.fld.alrmbr.dt = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "DT"); + state->u.f4.fld.alrmbr.wdsel = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "WDSEL"); + state->u.f4.fld.alrmbr.msk4 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK4"); + + // WPR bitfields. + state->u.f4.fld.wpr.key = cm_object_get_child_by_name(state->u.f4.reg.wpr, "KEY"); + + // SSR bitfields. + state->u.f4.fld.ssr.ss = cm_object_get_child_by_name(state->u.f4.reg.ssr, "SS"); + + // SHIFTR bitfields. + state->u.f4.fld.shiftr.subfs = cm_object_get_child_by_name(state->u.f4.reg.shiftr, "SUBFS"); + state->u.f4.fld.shiftr.add1s = cm_object_get_child_by_name(state->u.f4.reg.shiftr, "ADD1S"); + + // TSTR bitfields. + state->u.f4.fld.tstr.tamp1e = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMP1E"); + state->u.f4.fld.tstr.tamp1trg = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMP1TRG"); + state->u.f4.fld.tstr.tampie = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMPIE"); + state->u.f4.fld.tstr.tamp1insel = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMP1INSEL"); + state->u.f4.fld.tstr.tsinsel = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TSINSEL"); + state->u.f4.fld.tstr.alarmouttype = cm_object_get_child_by_name(state->u.f4.reg.tstr, "ALARMOUTTYPE"); + + // TSDR bitfields. + state->u.f4.fld.tsdr.du = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "DU"); + state->u.f4.fld.tsdr.dt = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "DT"); + state->u.f4.fld.tsdr.mu = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "MU"); + state->u.f4.fld.tsdr.mt = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "MT"); + state->u.f4.fld.tsdr.wdu = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "WDU"); + + // TSSSR bitfields. + state->u.f4.fld.tsssr.ss = cm_object_get_child_by_name(state->u.f4.reg.tsssr, "SS"); + + // CALR bitfields. + state->u.f4.fld.calr.calm = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALM"); + state->u.f4.fld.calr.calw16 = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALW16"); + state->u.f4.fld.calr.calw8 = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALW8"); + state->u.f4.fld.calr.calp = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALP"); + + // TAFCR bitfields. + state->u.f4.fld.tafcr.tamp1e = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1E"); + state->u.f4.fld.tafcr.tamp1trg = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1TRG"); + state->u.f4.fld.tafcr.tampie = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPIE"); + state->u.f4.fld.tafcr.tamp2e = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP2E"); + state->u.f4.fld.tafcr.tamp2trg = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP2TRG"); + state->u.f4.fld.tafcr.tampts = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPTS"); + state->u.f4.fld.tafcr.tampfreq = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPFREQ"); + state->u.f4.fld.tafcr.tampflt = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPFLT"); + state->u.f4.fld.tafcr.tampprch = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPPRCH"); + state->u.f4.fld.tafcr.tamppudis = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPPUDIS"); + state->u.f4.fld.tafcr.tamp1insel = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1INSEL"); + state->u.f4.fld.tafcr.tsinsel = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TSINSEL"); + state->u.f4.fld.tafcr.alarmouttype = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "ALARMOUTTYPE"); + + // ALRMASSR bitfields. + state->u.f4.fld.alrmassr.ss = cm_object_get_child_by_name(state->u.f4.reg.alrmassr, "SS"); + state->u.f4.fld.alrmassr.maskss = cm_object_get_child_by_name(state->u.f4.reg.alrmassr, "MASKSS"); + + // ALRMBSSR bitfields. + state->u.f4.fld.alrmbssr.ss = cm_object_get_child_by_name(state->u.f4.reg.alrmbssr, "SS"); + state->u.f4.fld.alrmbssr.maskss = cm_object_get_child_by_name(state->u.f4.reg.alrmbssr, "MASKSS"); + + // BKP0R bitfields. + state->u.f4.fld.bkp0r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp0r, "BKP"); + + // BKP1R bitfields. + state->u.f4.fld.bkp1r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp1r, "BKP"); + + // BKP2R bitfields. + state->u.f4.fld.bkp2r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp2r, "BKP"); + + // BKP3R bitfields. + state->u.f4.fld.bkp3r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp3r, "BKP"); + + // BKP4R bitfields. + state->u.f4.fld.bkp4r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp4r, "BKP"); + + // BKP5R bitfields. + state->u.f4.fld.bkp5r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp5r, "BKP"); + + // BKP6R bitfields. + state->u.f4.fld.bkp6r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp6r, "BKP"); + + // BKP7R bitfields. + state->u.f4.fld.bkp7r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp7r, "BKP"); + + // BKP8R bitfields. + state->u.f4.fld.bkp8r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp8r, "BKP"); + + // BKP9R bitfields. + state->u.f4.fld.bkp9r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp9r, "BKP"); + + // BKP10R bitfields. + state->u.f4.fld.bkp10r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp10r, "BKP"); + + // BKP11R bitfields. + state->u.f4.fld.bkp11r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp11r, "BKP"); + + // BKP12R bitfields. + state->u.f4.fld.bkp12r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp12r, "BKP"); + + // BKP13R bitfields. + state->u.f4.fld.bkp13r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp13r, "BKP"); + + // BKP14R bitfields. + state->u.f4.fld.bkp14r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp14r, "BKP"); + + // BKP15R bitfields. + state->u.f4.fld.bkp15r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp15r, "BKP"); + + // BKP16R bitfields. + state->u.f4.fld.bkp16r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp16r, "BKP"); + + // BKP17R bitfields. + state->u.f4.fld.bkp17r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp17r, "BKP"); + + // BKP18R bitfields. + state->u.f4.fld.bkp18r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp18r, "BKP"); + + // BKP19R bitfields. + state->u.f4.fld.bkp19r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp19r, "BKP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rtc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rtc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rtc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rtc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rtc_is_enabled(Object *obj) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rtc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RTCState *state = STM32_RTC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rtc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RTC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RTCState *state = STM32_RTC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RTC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_rtc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rtc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rtc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rtc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rtc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RTCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rtc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RTC); +} + +static void stm32_rtc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rtc_reset_callback; + dc->realize = stm32_rtc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rtc_is_enabled; +} + +static const TypeInfo stm32_rtc_type_info = { + .name = TYPE_STM32_RTC, + .parent = TYPE_STM32_RTC_PARENT, + .instance_init = stm32_rtc_instance_init_callback, + .instance_size = sizeof(STM32RTCState), + .class_init = stm32_rtc_class_init_callback, + .class_size = sizeof(STM32RTCClass) }; + +static void stm32_rtc_register_types(void) +{ + type_register_static(&stm32_rtc_type_info); +} + +type_init(stm32_rtc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/rtc.h b/gnu-mcu-eclipse/devices/support/STM32F40x/rtc.h new file mode 100644 index 0000000000..a4f892896e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/rtc.h @@ -0,0 +1,433 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RTC_H_ +#define STM32_RTC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RTC DEVICE_PATH_STM32 "RTC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RTC TYPE_STM32_PREFIX "rtc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RTC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RTCParentClass; +typedef PeripheralState STM32RTCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RTCClass, (obj), TYPE_STM32_RTC) +#define STM32_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RTCClass, (klass), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentClass parent_class; + // public: + + // None, so far. +} STM32RTCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RTC_STATE(obj) \ + OBJECT_CHECK(STM32RTCState, (obj), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RTC (Real-time clock) registers. + struct { + Object *tr; // 0x0 (Time register) + Object *dr; // 0x4 (Date register) + Object *cr; // 0x8 (Control register) + Object *isr; // 0xC (Initialization and status register) + Object *prer; // 0x10 (Prescaler register) + Object *wutr; // 0x14 (Wakeup timer register) + Object *calibr; // 0x18 (Calibration register) + Object *alrmar; // 0x1C (Alarm A register) + Object *alrmbr; // 0x20 (Alarm B register) + Object *wpr; // 0x24 (Write protection register) + Object *ssr; // 0x28 (Sub second register) + Object *shiftr; // 0x2C (Shift control register) + Object *tstr; // 0x30 (Time stamp time register) + Object *tsdr; // 0x34 (Time stamp date register) + Object *tsssr; // 0x38 (Timestamp sub second register) + Object *calr; // 0x3C (Calibration register) + Object *tafcr; // 0x40 (Tamper and alternate function configuration register) + Object *alrmassr; // 0x44 (Alarm A sub second register) + Object *alrmbssr; // 0x48 (Alarm B sub second register) + Object *bkp0r; // 0x50 (Backup register) + Object *bkp1r; // 0x54 (Backup register) + Object *bkp2r; // 0x58 (Backup register) + Object *bkp3r; // 0x5C (Backup register) + Object *bkp4r; // 0x60 (Backup register) + Object *bkp5r; // 0x64 (Backup register) + Object *bkp6r; // 0x68 (Backup register) + Object *bkp7r; // 0x6C (Backup register) + Object *bkp8r; // 0x70 (Backup register) + Object *bkp9r; // 0x74 (Backup register) + Object *bkp10r; // 0x78 (Backup register) + Object *bkp11r; // 0x7C (Backup register) + Object *bkp12r; // 0x80 (Backup register) + Object *bkp13r; // 0x84 (Backup register) + Object *bkp14r; // 0x88 (Backup register) + Object *bkp15r; // 0x8C (Backup register) + Object *bkp16r; // 0x90 (Backup register) + Object *bkp17r; // 0x94 (Backup register) + Object *bkp18r; // 0x98 (Backup register) + Object *bkp19r; // 0x9C (Backup register) + } reg; + + struct { + + // TR (Time register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + } tr; + + // DR (Date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + Object *yu; // [16:19] Year units in BCD format + Object *yt; // [20:23] Year tens in BCD format + } dr; + + // CR (Control register) bitfields. + struct { + Object *wcksel; // [0:2] Wakeup clock selection + Object *tsedge; // [3:3] Time-stamp event active edge + Object *refckon; // [4:4] Reference clock detection enable (50 or 60 Hz) + Object *fmt; // [6:6] Hour format + Object *dce; // [7:7] Coarse digital calibration enable + Object *alrae; // [8:8] Alarm A enable + Object *alrbe; // [9:9] Alarm B enable + Object *wute; // [10:10] Wakeup timer enable + Object *tse; // [11:11] Time stamp enable + Object *alraie; // [12:12] Alarm A interrupt enable + Object *alrbie; // [13:13] Alarm B interrupt enable + Object *wutie; // [14:14] Wakeup timer interrupt enable + Object *tsie; // [15:15] Time-stamp interrupt enable + Object *add1h; // [16:16] Add 1 hour (summer time change) + Object *sub1h; // [17:17] Subtract 1 hour (winter time change) + Object *bkp; // [18:18] Backup + Object *pol; // [20:20] Output polarity + Object *osel; // [21:22] Output selection + Object *coe; // [23:23] Calibration output enable + } cr; + + // ISR (Initialization and status register) bitfields. + struct { + Object *alrawf; // [0:0] Alarm A write flag + Object *alrbwf; // [1:1] Alarm B write flag + Object *wutwf; // [2:2] Wakeup timer write flag + Object *shpf; // [3:3] Shift operation pending + Object *inits; // [4:4] Initialization status flag + Object *rsf; // [5:5] Registers synchronization flag + Object *initf; // [6:6] Initialization flag + Object *init; // [7:7] Initialization mode + Object *alraf; // [8:8] Alarm A flag + Object *alrbf; // [9:9] Alarm B flag + Object *wutf; // [10:10] Wakeup timer flag + Object *tsf; // [11:11] Time-stamp flag + Object *tsovf; // [12:12] Time-stamp overflow flag + Object *tamp1f; // [13:13] Tamper detection flag + Object *tamp2f; // [14:14] TAMPER2 detection flag + Object *recalpf; // [16:16] Recalibration pending Flag + } isr; + + // PRER (Prescaler register) bitfields. + struct { + Object *prediv_s; // [0:14] Synchronous prescaler factor + Object *prediv_a; // [16:22] Asynchronous prescaler factor + } prer; + + // WUTR (Wakeup timer register) bitfields. + struct { + Object *wut; // [0:15] Wakeup auto-reload value bits + } wutr; + + // CALIBR (Calibration register) bitfields. + struct { + Object *dc; // [0:4] Digital calibration + Object *dcs; // [7:7] Digital calibration sign + } calibr; + + // ALRMAR (Alarm A register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *msk1; // [7:7] Alarm A seconds mask + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *msk2; // [15:15] Alarm A minutes mask + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + Object *msk3; // [23:23] Alarm A hours mask + Object *du; // [24:27] Date units or day in BCD format + Object *dt; // [28:29] Date tens in BCD format + Object *wdsel; // [30:30] Week day selection + Object *msk4; // [31:31] Alarm A date mask + } alrmar; + + // ALRMBR (Alarm B register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *msk1; // [7:7] Alarm B seconds mask + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *msk2; // [15:15] Alarm B minutes mask + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + Object *msk3; // [23:23] Alarm B hours mask + Object *du; // [24:27] Date units or day in BCD format + Object *dt; // [28:29] Date tens in BCD format + Object *wdsel; // [30:30] Week day selection + Object *msk4; // [31:31] Alarm B date mask + } alrmbr; + + // WPR (Write protection register) bitfields. + struct { + Object *key; // [0:7] Write protection key + } wpr; + + // SSR (Sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } ssr; + + // SHIFTR (Shift control register) bitfields. + struct { + Object *subfs; // [0:14] Subtract a fraction of a second + Object *add1s; // [31:31] Add one second + } shiftr; + + // TSTR (Time stamp time register) bitfields. + struct { + Object *tamp1e; // [0:0] Tamper 1 detection enable + Object *tamp1trg; // [1:1] Active level for tamper 1 + Object *tampie; // [2:2] Tamper interrupt enable + Object *tamp1insel; // [16:16] TAMPER1 mapping + Object *tsinsel; // [17:17] TIMESTAMP mapping + Object *alarmouttype; // [18:18] AFO_ALARM output type + } tstr; + + // TSDR (Time stamp date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + } tsdr; + + // TSSSR (Timestamp sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } tsssr; + + // CALR (Calibration register) bitfields. + struct { + Object *calm; // [0:8] Calibration minus + Object *calw16; // [13:13] Use a 16-second calibration cycle period + Object *calw8; // [14:14] Use an 8-second calibration cycle period + Object *calp; // [15:15] Increase frequency of RTC by 488.5 ppm + } calr; + + // TAFCR (Tamper and alternate function configuration register) bitfields. + struct { + Object *tamp1e; // [0:0] Tamper 1 detection enable + Object *tamp1trg; // [1:1] Active level for tamper 1 + Object *tampie; // [2:2] Tamper interrupt enable + Object *tamp2e; // [3:3] Tamper 2 detection enable + Object *tamp2trg; // [4:4] Active level for tamper 2 + Object *tampts; // [7:7] Activate timestamp on tamper detection event + Object *tampfreq; // [8:10] Tamper sampling frequency + Object *tampflt; // [11:12] Tamper filter count + Object *tampprch; // [13:14] Tamper precharge duration + Object *tamppudis; // [15:15] TAMPER pull-up disable + Object *tamp1insel; // [16:16] TAMPER1 mapping + Object *tsinsel; // [17:17] TIMESTAMP mapping + Object *alarmouttype; // [18:18] AFO_ALARM output type + } tafcr; + + // ALRMASSR (Alarm A sub second register) bitfields. + struct { + Object *ss; // [0:14] Sub seconds value + Object *maskss; // [24:27] Mask the most-significant bits starting at this bit + } alrmassr; + + // ALRMBSSR (Alarm B sub second register) bitfields. + struct { + Object *ss; // [0:14] Sub seconds value + Object *maskss; // [24:27] Mask the most-significant bits starting at this bit + } alrmbssr; + + // BKP0R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp0r; + + // BKP1R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp1r; + + // BKP2R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp2r; + + // BKP3R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp3r; + + // BKP4R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp4r; + + // BKP5R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp5r; + + // BKP6R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp6r; + + // BKP7R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp7r; + + // BKP8R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp8r; + + // BKP9R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp9r; + + // BKP10R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp10r; + + // BKP11R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp11r; + + // BKP12R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp12r; + + // BKP13R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp13r; + + // BKP14R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp14r; + + // BKP15R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp15r; + + // BKP16R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp16r; + + // BKP17R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp17r; + + // BKP18R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp18r; + + // BKP19R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp19r; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RTCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RTC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/sdio.c b/gnu-mcu-eclipse/devices/support/STM32F40x/sdio.c new file mode 100644 index 0000000000..3ce255a5cf --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/sdio.c @@ -0,0 +1,386 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_sdio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.power = cm_object_get_child_by_name(obj, "POWER"); + state->u.f4.reg.clkcr = cm_object_get_child_by_name(obj, "CLKCR"); + state->u.f4.reg.arg = cm_object_get_child_by_name(obj, "ARG"); + state->u.f4.reg.cmd = cm_object_get_child_by_name(obj, "CMD"); + state->u.f4.reg.respcmd = cm_object_get_child_by_name(obj, "RESPCMD"); + state->u.f4.reg.resp1 = cm_object_get_child_by_name(obj, "RESP1"); + state->u.f4.reg.resp2 = cm_object_get_child_by_name(obj, "RESP2"); + state->u.f4.reg.resp3 = cm_object_get_child_by_name(obj, "RESP3"); + state->u.f4.reg.resp4 = cm_object_get_child_by_name(obj, "RESP4"); + state->u.f4.reg.dtimer = cm_object_get_child_by_name(obj, "DTIMER"); + state->u.f4.reg.dlen = cm_object_get_child_by_name(obj, "DLEN"); + state->u.f4.reg.dctrl = cm_object_get_child_by_name(obj, "DCTRL"); + state->u.f4.reg.dcount = cm_object_get_child_by_name(obj, "DCOUNT"); + state->u.f4.reg.sta = cm_object_get_child_by_name(obj, "STA"); + state->u.f4.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f4.reg.mask = cm_object_get_child_by_name(obj, "MASK"); + state->u.f4.reg.fifocnt = cm_object_get_child_by_name(obj, "FIFOCNT"); + state->u.f4.reg.fifo = cm_object_get_child_by_name(obj, "FIFO"); + + + // POWER bitfields. + state->u.f4.fld.power.pwrctrl = cm_object_get_child_by_name(state->u.f4.reg.power, "PWRCTRL"); + + // CLKCR bitfields. + state->u.f4.fld.clkcr.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "CLKDIV"); + state->u.f4.fld.clkcr.clken = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "CLKEN"); + state->u.f4.fld.clkcr.pwrsav = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "PWRSAV"); + state->u.f4.fld.clkcr.bypass = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "BYPASS"); + state->u.f4.fld.clkcr.widbus = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "WIDBUS"); + state->u.f4.fld.clkcr.negedge = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "NEGEDGE"); + state->u.f4.fld.clkcr.hwfc_en = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "HWFC_EN"); + + // ARG bitfields. + state->u.f4.fld.arg.cmdarg = cm_object_get_child_by_name(state->u.f4.reg.arg, "CMDARG"); + + // CMD bitfields. + state->u.f4.fld.cmd.cmdindex = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CMDINDEX"); + state->u.f4.fld.cmd.waitresp = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITRESP"); + state->u.f4.fld.cmd.waitint = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITINT"); + state->u.f4.fld.cmd.waitpend = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITPEND"); + state->u.f4.fld.cmd.cpsmen = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CPSMEN"); + state->u.f4.fld.cmd.sdiosuspend = cm_object_get_child_by_name(state->u.f4.reg.cmd, "SDIOSuspend"); + state->u.f4.fld.cmd.encmdcompl = cm_object_get_child_by_name(state->u.f4.reg.cmd, "ENCMDcompl"); + state->u.f4.fld.cmd.nien = cm_object_get_child_by_name(state->u.f4.reg.cmd, "nIEN"); + state->u.f4.fld.cmd.ce_atacmd = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CE_ATACMD"); + + // RESPCMD bitfields. + state->u.f4.fld.respcmd.respcmd = cm_object_get_child_by_name(state->u.f4.reg.respcmd, "RESPCMD"); + + // RESP1 bitfields. + state->u.f4.fld.resp1.cardstatus1 = cm_object_get_child_by_name(state->u.f4.reg.resp1, "CARDSTATUS1"); + + // RESP2 bitfields. + state->u.f4.fld.resp2.cardstatus2 = cm_object_get_child_by_name(state->u.f4.reg.resp2, "CARDSTATUS2"); + + // RESP3 bitfields. + state->u.f4.fld.resp3.cardstatus3 = cm_object_get_child_by_name(state->u.f4.reg.resp3, "CARDSTATUS3"); + + // RESP4 bitfields. + state->u.f4.fld.resp4.cardstatus4 = cm_object_get_child_by_name(state->u.f4.reg.resp4, "CARDSTATUS4"); + + // DTIMER bitfields. + state->u.f4.fld.dtimer.datatime = cm_object_get_child_by_name(state->u.f4.reg.dtimer, "DATATIME"); + + // DLEN bitfields. + state->u.f4.fld.dlen.datalength = cm_object_get_child_by_name(state->u.f4.reg.dlen, "DATALENGTH"); + + // DCTRL bitfields. + state->u.f4.fld.dctrl.dten = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTEN"); + state->u.f4.fld.dctrl.dtdir = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTDIR"); + state->u.f4.fld.dctrl.dtmode = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTMODE"); + state->u.f4.fld.dctrl.dmaen = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DMAEN"); + state->u.f4.fld.dctrl.dblocksize = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DBLOCKSIZE"); + state->u.f4.fld.dctrl.rwstart = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWSTART"); + state->u.f4.fld.dctrl.rwstop = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWSTOP"); + state->u.f4.fld.dctrl.rwmod = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWMOD"); + state->u.f4.fld.dctrl.sdioen = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "SDIOEN"); + + // DCOUNT bitfields. + state->u.f4.fld.dcount.datacount = cm_object_get_child_by_name(state->u.f4.reg.dcount, "DATACOUNT"); + + // STA bitfields. + state->u.f4.fld.sta.ccrcfail = cm_object_get_child_by_name(state->u.f4.reg.sta, "CCRCFAIL"); + state->u.f4.fld.sta.dcrcfail = cm_object_get_child_by_name(state->u.f4.reg.sta, "DCRCFAIL"); + state->u.f4.fld.sta.ctimeout = cm_object_get_child_by_name(state->u.f4.reg.sta, "CTIMEOUT"); + state->u.f4.fld.sta.dtimeout = cm_object_get_child_by_name(state->u.f4.reg.sta, "DTIMEOUT"); + state->u.f4.fld.sta.txunderr = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXUNDERR"); + state->u.f4.fld.sta.rxoverr = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXOVERR"); + state->u.f4.fld.sta.cmdrend = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDREND"); + state->u.f4.fld.sta.cmdsent = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDSENT"); + state->u.f4.fld.sta.dataend = cm_object_get_child_by_name(state->u.f4.reg.sta, "DATAEND"); + state->u.f4.fld.sta.stbiterr = cm_object_get_child_by_name(state->u.f4.reg.sta, "STBITERR"); + state->u.f4.fld.sta.dbckend = cm_object_get_child_by_name(state->u.f4.reg.sta, "DBCKEND"); + state->u.f4.fld.sta.cmdact = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDACT"); + state->u.f4.fld.sta.txact = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXACT"); + state->u.f4.fld.sta.rxact = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXACT"); + state->u.f4.fld.sta.txfifohe = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOHE"); + state->u.f4.fld.sta.rxfifohf = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOHF"); + state->u.f4.fld.sta.txfifof = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOF"); + state->u.f4.fld.sta.rxfifof = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOF"); + state->u.f4.fld.sta.txfifoe = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOE"); + state->u.f4.fld.sta.rxfifoe = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOE"); + state->u.f4.fld.sta.txdavl = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXDAVL"); + state->u.f4.fld.sta.rxdavl = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXDAVL"); + state->u.f4.fld.sta.sdioit = cm_object_get_child_by_name(state->u.f4.reg.sta, "SDIOIT"); + state->u.f4.fld.sta.ceataend = cm_object_get_child_by_name(state->u.f4.reg.sta, "CEATAEND"); + + // ICR bitfields. + state->u.f4.fld.icr.ccrcfailc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CCRCFAILC"); + state->u.f4.fld.icr.dcrcfailc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DCRCFAILC"); + state->u.f4.fld.icr.ctimeoutc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CTIMEOUTC"); + state->u.f4.fld.icr.dtimeoutc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DTIMEOUTC"); + state->u.f4.fld.icr.txunderrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "TXUNDERRC"); + state->u.f4.fld.icr.rxoverrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "RXOVERRC"); + state->u.f4.fld.icr.cmdrendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CMDRENDC"); + state->u.f4.fld.icr.cmdsentc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CMDSENTC"); + state->u.f4.fld.icr.dataendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DATAENDC"); + state->u.f4.fld.icr.stbiterrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "STBITERRC"); + state->u.f4.fld.icr.dbckendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DBCKENDC"); + state->u.f4.fld.icr.sdioitc = cm_object_get_child_by_name(state->u.f4.reg.icr, "SDIOITC"); + state->u.f4.fld.icr.ceataendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CEATAENDC"); + + // MASK bitfields. + state->u.f4.fld.mask.ccrcfailie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CCRCFAILIE"); + state->u.f4.fld.mask.dcrcfailie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DCRCFAILIE"); + state->u.f4.fld.mask.ctimeoutie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CTIMEOUTIE"); + state->u.f4.fld.mask.dtimeoutie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DTIMEOUTIE"); + state->u.f4.fld.mask.txunderrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXUNDERRIE"); + state->u.f4.fld.mask.rxoverrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXOVERRIE"); + state->u.f4.fld.mask.cmdrendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDRENDIE"); + state->u.f4.fld.mask.cmdsentie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDSENTIE"); + state->u.f4.fld.mask.dataendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DATAENDIE"); + state->u.f4.fld.mask.stbiterrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "STBITERRIE"); + state->u.f4.fld.mask.dbckendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DBCKENDIE"); + state->u.f4.fld.mask.cmdactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDACTIE"); + state->u.f4.fld.mask.txactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXACTIE"); + state->u.f4.fld.mask.rxactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXACTIE"); + state->u.f4.fld.mask.txfifoheie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOHEIE"); + state->u.f4.fld.mask.rxfifohfie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOHFIE"); + state->u.f4.fld.mask.txfifofie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOFIE"); + state->u.f4.fld.mask.rxfifofie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOFIE"); + state->u.f4.fld.mask.txfifoeie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOEIE"); + state->u.f4.fld.mask.rxfifoeie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOEIE"); + state->u.f4.fld.mask.txdavlie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXDAVLIE"); + state->u.f4.fld.mask.rxdavlie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXDAVLIE"); + state->u.f4.fld.mask.sdioitie = cm_object_get_child_by_name(state->u.f4.reg.mask, "SDIOITIE"); + state->u.f4.fld.mask.ceataendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CEATAENDIE"); + + // FIFOCNT bitfields. + state->u.f4.fld.fifocnt.fifocount = cm_object_get_child_by_name(state->u.f4.reg.fifocnt, "FIFOCOUNT"); + + // FIFO bitfields. + state->u.f4.fld.fifo.fifodata = cm_object_get_child_by_name(state->u.f4.reg.fifo, "FIFOData"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_sdio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_sdio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_sdio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_sdio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_sdio_is_enabled(Object *obj) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_sdio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_sdio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SDIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SDIOState *state = STM32_SDIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SDIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_sdio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sdio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_sdio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sdio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_sdio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SDIOEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_sdio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SDIO); +} + +static void stm32_sdio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_sdio_reset_callback; + dc->realize = stm32_sdio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_sdio_is_enabled; +} + +static const TypeInfo stm32_sdio_type_info = { + .name = TYPE_STM32_SDIO, + .parent = TYPE_STM32_SDIO_PARENT, + .instance_init = stm32_sdio_instance_init_callback, + .instance_size = sizeof(STM32SDIOState), + .class_init = stm32_sdio_class_init_callback, + .class_size = sizeof(STM32SDIOClass) }; + +static void stm32_sdio_register_types(void) +{ + type_register_static(&stm32_sdio_type_info); +} + +type_init(stm32_sdio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/sdio.h b/gnu-mcu-eclipse/devices/support/STM32F40x/sdio.h new file mode 100644 index 0000000000..b50b00c946 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/sdio.h @@ -0,0 +1,287 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SDIO_H_ +#define STM32_SDIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SDIO DEVICE_PATH_STM32 "SDIO" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SDIO TYPE_STM32_PREFIX "sdio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SDIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SDIOParentClass; +typedef PeripheralState STM32SDIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SDIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SDIOClass, (obj), TYPE_STM32_SDIO) +#define STM32_SDIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SDIOClass, (klass), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentClass parent_class; + // public: + + // None, so far. +} STM32SDIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SDIO_STATE(obj) \ + OBJECT_CHECK(STM32SDIOState, (obj), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SDIO (Secure digital input/output interface) registers. + struct { + Object *power; // 0x0 (Power control register) + Object *clkcr; // 0x4 (SDI clock control register) + Object *arg; // 0x8 (Argument register) + Object *cmd; // 0xC (Command register) + Object *respcmd; // 0x10 (Command response register) + Object *resp1; // 0x14 (Response 1..4 register) + Object *resp2; // 0x18 (Response 1..4 register) + Object *resp3; // 0x1C (Response 1..4 register) + Object *resp4; // 0x20 (Response 1..4 register) + Object *dtimer; // 0x24 (Data timer register) + Object *dlen; // 0x28 (Data length register) + Object *dctrl; // 0x2C (Data control register) + Object *dcount; // 0x30 (Data counter register) + Object *sta; // 0x34 (Status register) + Object *icr; // 0x38 (Interrupt clear register) + Object *mask; // 0x3C (Mask register) + Object *fifocnt; // 0x48 (FIFO counter register) + Object *fifo; // 0x80 (Data FIFO register) + } reg; + + struct { + + // POWER (Power control register) bitfields. + struct { + Object *pwrctrl; // [0:1] PWRCTRL + } power; + + // CLKCR (SDI clock control register) bitfields. + struct { + Object *clkdiv; // [0:7] Clock divide factor + Object *clken; // [8:8] Clock enable bit + Object *pwrsav; // [9:9] Power saving configuration bit + Object *bypass; // [10:10] Clock divider bypass enable bit + Object *widbus; // [11:12] Wide bus mode enable bit + Object *negedge; // [13:13] SDIO_CK dephasing selection bit + Object *hwfc_en; // [14:14] HW Flow Control enable + } clkcr; + + // ARG (Argument register) bitfields. + struct { + Object *cmdarg; // [0:31] Command argument + } arg; + + // CMD (Command register) bitfields. + struct { + Object *cmdindex; // [0:5] Command index + Object *waitresp; // [6:7] Wait for response bits + Object *waitint; // [8:8] CPSM waits for interrupt request + Object *waitpend; // [9:9] CPSM Waits for ends of data transfer (CmdPend internal signal). + Object *cpsmen; // [10:10] Command path state machine (CPSM) Enable bit + Object *sdiosuspend; // [11:11] SD I/O suspend command + Object *encmdcompl; // [12:12] Enable CMD completion + Object *nien; // [13:13] Not Interrupt Enable + Object *ce_atacmd; // [14:14] CE-ATA command + } cmd; + + // RESPCMD (Command response register) bitfields. + struct { + Object *respcmd; // [0:5] Response command index + } respcmd; + + // RESP1 (Response 1..4 register) bitfields. + struct { + Object *cardstatus1; // [0:31] See Table 132. + } resp1; + + // RESP2 (Response 1..4 register) bitfields. + struct { + Object *cardstatus2; // [0:31] See Table 132. + } resp2; + + // RESP3 (Response 1..4 register) bitfields. + struct { + Object *cardstatus3; // [0:31] See Table 132. + } resp3; + + // RESP4 (Response 1..4 register) bitfields. + struct { + Object *cardstatus4; // [0:31] See Table 132. + } resp4; + + // DTIMER (Data timer register) bitfields. + struct { + Object *datatime; // [0:31] Data timeout period + } dtimer; + + // DLEN (Data length register) bitfields. + struct { + Object *datalength; // [0:24] Data length value + } dlen; + + // DCTRL (Data control register) bitfields. + struct { + Object *dten; // [0:0] DTEN + Object *dtdir; // [1:1] Data transfer direction selection + Object *dtmode; // [2:2] Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + Object *dmaen; // [3:3] DMA enable bit + Object *dblocksize; // [4:7] Data block size + Object *rwstart; // [8:8] Read wait start + Object *rwstop; // [9:9] Read wait stop + Object *rwmod; // [10:10] Read wait mode + Object *sdioen; // [11:11] SD I/O enable functions + } dctrl; + + // DCOUNT (Data counter register) bitfields. + struct { + Object *datacount; // [0:24] Data count value + } dcount; + + // STA (Status register) bitfields. + struct { + Object *ccrcfail; // [0:0] Command response received (CRC check failed) + Object *dcrcfail; // [1:1] Data block sent/received (CRC check failed) + Object *ctimeout; // [2:2] Command response timeout + Object *dtimeout; // [3:3] Data timeout + Object *txunderr; // [4:4] Transmit FIFO underrun error + Object *rxoverr; // [5:5] Received FIFO overrun error + Object *cmdrend; // [6:6] Command response received (CRC check passed) + Object *cmdsent; // [7:7] Command sent (no response required) + Object *dataend; // [8:8] Data end (data counter, SDIDCOUNT, is zero) + Object *stbiterr; // [9:9] Start bit not detected on all data signals in wide bus mode + Object *dbckend; // [10:10] Data block sent/received (CRC check passed) + Object *cmdact; // [11:11] Command transfer in progress + Object *txact; // [12:12] Data transmit in progress + Object *rxact; // [13:13] Data receive in progress + Object *txfifohe; // [14:14] Transmit FIFO half empty: at least 8 words can be written into the FIFO + Object *rxfifohf; // [15:15] Receive FIFO half full: there are at least 8 words in the FIFO + Object *txfifof; // [16:16] Transmit FIFO full + Object *rxfifof; // [17:17] Receive FIFO full + Object *txfifoe; // [18:18] Transmit FIFO empty + Object *rxfifoe; // [19:19] Receive FIFO empty + Object *txdavl; // [20:20] Data available in transmit FIFO + Object *rxdavl; // [21:21] Data available in receive FIFO + Object *sdioit; // [22:22] SDIO interrupt received + Object *ceataend; // [23:23] CE-ATA command completion signal received for CMD61 + } sta; + + // ICR (Interrupt clear register) bitfields. + struct { + Object *ccrcfailc; // [0:0] CCRCFAIL flag clear bit + Object *dcrcfailc; // [1:1] DCRCFAIL flag clear bit + Object *ctimeoutc; // [2:2] CTIMEOUT flag clear bit + Object *dtimeoutc; // [3:3] DTIMEOUT flag clear bit + Object *txunderrc; // [4:4] TXUNDERR flag clear bit + Object *rxoverrc; // [5:5] RXOVERR flag clear bit + Object *cmdrendc; // [6:6] CMDREND flag clear bit + Object *cmdsentc; // [7:7] CMDSENT flag clear bit + Object *dataendc; // [8:8] DATAEND flag clear bit + Object *stbiterrc; // [9:9] STBITERR flag clear bit + Object *dbckendc; // [10:10] DBCKEND flag clear bit + Object *sdioitc; // [22:22] SDIOIT flag clear bit + Object *ceataendc; // [23:23] CEATAEND flag clear bit + } icr; + + // MASK (Mask register) bitfields. + struct { + Object *ccrcfailie; // [0:0] Command CRC fail interrupt enable + Object *dcrcfailie; // [1:1] Data CRC fail interrupt enable + Object *ctimeoutie; // [2:2] Command timeout interrupt enable + Object *dtimeoutie; // [3:3] Data timeout interrupt enable + Object *txunderrie; // [4:4] Tx FIFO underrun error interrupt enable + Object *rxoverrie; // [5:5] Rx FIFO overrun error interrupt enable + Object *cmdrendie; // [6:6] Command response received interrupt enable + Object *cmdsentie; // [7:7] Command sent interrupt enable + Object *dataendie; // [8:8] Data end interrupt enable + Object *stbiterrie; // [9:9] Start bit error interrupt enable + Object *dbckendie; // [10:10] Data block end interrupt enable + Object *cmdactie; // [11:11] Command acting interrupt enable + Object *txactie; // [12:12] Data transmit acting interrupt enable + Object *rxactie; // [13:13] Data receive acting interrupt enable + Object *txfifoheie; // [14:14] Tx FIFO half empty interrupt enable + Object *rxfifohfie; // [15:15] Rx FIFO half full interrupt enable + Object *txfifofie; // [16:16] Tx FIFO full interrupt enable + Object *rxfifofie; // [17:17] Rx FIFO full interrupt enable + Object *txfifoeie; // [18:18] Tx FIFO empty interrupt enable + Object *rxfifoeie; // [19:19] Rx FIFO empty interrupt enable + Object *txdavlie; // [20:20] Data available in Tx FIFO interrupt enable + Object *rxdavlie; // [21:21] Data available in Rx FIFO interrupt enable + Object *sdioitie; // [22:22] SDIO mode interrupt received interrupt enable + Object *ceataendie; // [23:23] CE-ATA command completion signal received interrupt enable + } mask; + + // FIFOCNT (FIFO counter register) bitfields. + struct { + Object *fifocount; // [0:23] Remaining number of words to be written to or read from the FIFO. + } fifocnt; + + // FIFO (Data FIFO register) bitfields. + struct { + Object *fifodata; // [0:31] Receive and transmit FIFO data + } fifo; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SDIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SDIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/spi1.c b/gnu-mcu-eclipse/devices/support/STM32F40x/spi1.c new file mode 100644 index 0000000000..f98691b4c8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/spi1.c @@ -0,0 +1,311 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_spi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.crcpr = cm_object_get_child_by_name(obj, "CRCPR"); + state->u.f4.reg.rxcrcr = cm_object_get_child_by_name(obj, "RXCRCR"); + state->u.f4.reg.txcrcr = cm_object_get_child_by_name(obj, "TXCRCR"); + state->u.f4.reg.i2scfgr = cm_object_get_child_by_name(obj, "I2SCFGR"); + state->u.f4.reg.i2spr = cm_object_get_child_by_name(obj, "I2SPR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cpha = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CPHA"); + state->u.f4.fld.cr1.cpol = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CPOL"); + state->u.f4.fld.cr1.mstr = cm_object_get_child_by_name(state->u.f4.reg.cr1, "MSTR"); + state->u.f4.fld.cr1.br = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BR"); + state->u.f4.fld.cr1.spe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SPE"); + state->u.f4.fld.cr1.lsbfirst = cm_object_get_child_by_name(state->u.f4.reg.cr1, "LSBFIRST"); + state->u.f4.fld.cr1.ssi = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SSI"); + state->u.f4.fld.cr1.ssm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SSM"); + state->u.f4.fld.cr1.rxonly = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXONLY"); + state->u.f4.fld.cr1.dff = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DFF"); + state->u.f4.fld.cr1.crcnext = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CRCNEXT"); + state->u.f4.fld.cr1.crcen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CRCEN"); + state->u.f4.fld.cr1.bidioe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BIDIOE"); + state->u.f4.fld.cr1.bidimode = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BIDIMODE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.rxdmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "RXDMAEN"); + state->u.f4.fld.cr2.txdmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TXDMAEN"); + state->u.f4.fld.cr2.ssoe = cm_object_get_child_by_name(state->u.f4.reg.cr2, "SSOE"); + state->u.f4.fld.cr2.frf = cm_object_get_child_by_name(state->u.f4.reg.cr2, "FRF"); + state->u.f4.fld.cr2.errie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ERRIE"); + state->u.f4.fld.cr2.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "RXNEIE"); + state->u.f4.fld.cr2.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TXEIE"); + + // SR bitfields. + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.chside = cm_object_get_child_by_name(state->u.f4.reg.sr, "CHSIDE"); + state->u.f4.fld.sr.udr = cm_object_get_child_by_name(state->u.f4.reg.sr, "UDR"); + state->u.f4.fld.sr.crcerr = cm_object_get_child_by_name(state->u.f4.reg.sr, "CRCERR"); + state->u.f4.fld.sr.modf = cm_object_get_child_by_name(state->u.f4.reg.sr, "MODF"); + state->u.f4.fld.sr.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OVR"); + state->u.f4.fld.sr.bsy = cm_object_get_child_by_name(state->u.f4.reg.sr, "BSY"); + state->u.f4.fld.sr.tifrfe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIFRFE"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // CRCPR bitfields. + state->u.f4.fld.crcpr.crcpoly = cm_object_get_child_by_name(state->u.f4.reg.crcpr, "CRCPOLY"); + + // RXCRCR bitfields. + state->u.f4.fld.rxcrcr.rxcrc = cm_object_get_child_by_name(state->u.f4.reg.rxcrcr, "RxCRC"); + + // TXCRCR bitfields. + state->u.f4.fld.txcrcr.txcrc = cm_object_get_child_by_name(state->u.f4.reg.txcrcr, "TxCRC"); + + // I2SCFGR bitfields. + state->u.f4.fld.i2scfgr.chlen = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "CHLEN"); + state->u.f4.fld.i2scfgr.datlen = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "DATLEN"); + state->u.f4.fld.i2scfgr.ckpol = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "CKPOL"); + state->u.f4.fld.i2scfgr.i2sstd = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SSTD"); + state->u.f4.fld.i2scfgr.pcmsync = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "PCMSYNC"); + state->u.f4.fld.i2scfgr.i2scfg = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SCFG"); + state->u.f4.fld.i2scfgr.i2se = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SE"); + state->u.f4.fld.i2scfgr.i2smod = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SMOD"); + + // I2SPR bitfields. + state->u.f4.fld.i2spr.i2sdiv = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "I2SDIV"); + state->u.f4.fld.i2spr.odd = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "ODD"); + state->u.f4.fld.i2spr.mckoe = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "MCKOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_spi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_spi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_spi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_spi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_spi_is_enabled(Object *obj) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_spi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SPIState *state = STM32_SPI_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_SPI_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_spi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SPI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SPIState *state = STM32_SPI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SPI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_spi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_spi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_spi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_spi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_spi_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SPI%dEN", + 1 + state->port_index - STM32_PORT_SPI1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_spi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SPI); +} + +static void stm32_spi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_spi_reset_callback; + dc->realize = stm32_spi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_spi_is_enabled; +} + +static const TypeInfo stm32_spi_type_info = { + .name = TYPE_STM32_SPI, + .parent = TYPE_STM32_SPI_PARENT, + .instance_init = stm32_spi_instance_init_callback, + .instance_size = sizeof(STM32SPIState), + .class_init = stm32_spi_class_init_callback, + .class_size = sizeof(STM32SPIClass) }; + +static void stm32_spi_register_types(void) +{ + type_register_static(&stm32_spi_type_info); +} + +type_init(stm32_spi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/spi1.h b/gnu-mcu-eclipse/devices/support/STM32F40x/spi1.h new file mode 100644 index 0000000000..29194debcd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/spi1.h @@ -0,0 +1,201 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SPI_H_ +#define STM32_SPI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SPI DEVICE_PATH_STM32 "SPI" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_SPI1, + STM32_PORT_SPI2, + STM32_PORT_SPI3, + STM32_PORT_SPI_UNDEFINED = 0xFF, +} stm32_spi_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SPI TYPE_STM32_PREFIX "spi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SPI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SPIParentClass; +typedef PeripheralState STM32SPIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SPI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SPIClass, (obj), TYPE_STM32_SPI) +#define STM32_SPI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SPIClass, (klass), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentClass parent_class; + // public: + + // None, so far. +} STM32SPIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SPI_STATE(obj) \ + OBJECT_CHECK(STM32SPIState, (obj), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_spi_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SPI (Serial peripheral interface) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *sr; // 0x8 (Status register) + Object *dr; // 0xC (Data register) + Object *crcpr; // 0x10 (CRC polynomial register) + Object *rxcrcr; // 0x14 (RX CRC register) + Object *txcrcr; // 0x18 (TX CRC register) + Object *i2scfgr; // 0x1C (I2S configuration register) + Object *i2spr; // 0x20 (I2S prescaler register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cpha; // [0:0] Clock phase + Object *cpol; // [1:1] Clock polarity + Object *mstr; // [2:2] Master selection + Object *br; // [3:5] Baud rate control + Object *spe; // [6:6] SPI enable + Object *lsbfirst; // [7:7] Frame format + Object *ssi; // [8:8] Internal slave select + Object *ssm; // [9:9] Software slave management + Object *rxonly; // [10:10] Receive only + Object *dff; // [11:11] Data frame format + Object *crcnext; // [12:12] CRC transfer next + Object *crcen; // [13:13] Hardware CRC calculation enable + Object *bidioe; // [14:14] Output enable in bidirectional mode + Object *bidimode; // [15:15] Bidirectional data mode enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *rxdmaen; // [0:0] Rx buffer DMA enable + Object *txdmaen; // [1:1] Tx buffer DMA enable + Object *ssoe; // [2:2] SS output enable + Object *frf; // [4:4] Frame format + Object *errie; // [5:5] Error interrupt enable + Object *rxneie; // [6:6] RX buffer not empty interrupt enable + Object *txeie; // [7:7] Tx buffer empty interrupt enable + } cr2; + + // SR (Status register) bitfields. + struct { + Object *rxne; // [0:0] Receive buffer not empty + Object *txe; // [1:1] Transmit buffer empty + Object *chside; // [2:2] Channel side + Object *udr; // [3:3] Underrun flag + Object *crcerr; // [4:4] CRC error flag + Object *modf; // [5:5] Mode fault + Object *ovr; // [6:6] Overrun flag + Object *bsy; // [7:7] Busy flag + Object *tifrfe; // [8:8] TI frame format error + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:15] Data register + } dr; + + // CRCPR (CRC polynomial register) bitfields. + struct { + Object *crcpoly; // [0:15] CRC polynomial register + } crcpr; + + // RXCRCR (RX CRC register) bitfields. + struct { + Object *rxcrc; // [0:15] Rx CRC register + } rxcrcr; + + // TXCRCR (TX CRC register) bitfields. + struct { + Object *txcrc; // [0:15] Tx CRC register + } txcrcr; + + // I2SCFGR (I2S configuration register) bitfields. + struct { + Object *chlen; // [0:0] Channel length (number of bits per audio channel) + Object *datlen; // [1:2] Data length to be transferred + Object *ckpol; // [3:3] Steady state clock polarity + Object *i2sstd; // [4:5] I2S standard selection + Object *pcmsync; // [7:7] PCM frame synchronization + Object *i2scfg; // [8:9] I2S configuration mode + Object *i2se; // [10:10] I2S Enable + Object *i2smod; // [11:11] I2S mode selection + } i2scfgr; + + // I2SPR (I2S prescaler register) bitfields. + struct { + Object *i2sdiv; // [0:7] I2S Linear prescaler + Object *odd; // [8:8] Odd factor for the prescaler + Object *mckoe; // [9:9] Master clock output enable + } i2spr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SPIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SPI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/syscfg.c b/gnu-mcu-eclipse/devices/support/STM32F40x/syscfg.c new file mode 100644 index 0000000000..4998972ef5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/syscfg.c @@ -0,0 +1,275 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_syscfg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.memrm = cm_object_get_child_by_name(obj, "MEMRM"); + state->u.f4.reg.pmc = cm_object_get_child_by_name(obj, "PMC"); + state->u.f4.reg.exticr1 = cm_object_get_child_by_name(obj, "EXTICR1"); + state->u.f4.reg.exticr2 = cm_object_get_child_by_name(obj, "EXTICR2"); + state->u.f4.reg.exticr3 = cm_object_get_child_by_name(obj, "EXTICR3"); + state->u.f4.reg.exticr4 = cm_object_get_child_by_name(obj, "EXTICR4"); + state->u.f4.reg.cmpcr = cm_object_get_child_by_name(obj, "CMPCR"); + + + // MEMRM bitfields. + state->u.f4.fld.memrm.mem_mode = cm_object_get_child_by_name(state->u.f4.reg.memrm, "MEM_MODE"); + + // PMC bitfields. + state->u.f4.fld.pmc.mii_rmii_sel = cm_object_get_child_by_name(state->u.f4.reg.pmc, "MII_RMII_SEL"); + + // EXTICR1 bitfields. + state->u.f4.fld.exticr1.exti0 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI0"); + state->u.f4.fld.exticr1.exti1 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI1"); + state->u.f4.fld.exticr1.exti2 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI2"); + state->u.f4.fld.exticr1.exti3 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI3"); + + // EXTICR2 bitfields. + state->u.f4.fld.exticr2.exti4 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI4"); + state->u.f4.fld.exticr2.exti5 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI5"); + state->u.f4.fld.exticr2.exti6 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI6"); + state->u.f4.fld.exticr2.exti7 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI7"); + + // EXTICR3 bitfields. + state->u.f4.fld.exticr3.exti8 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI8"); + state->u.f4.fld.exticr3.exti9 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI9"); + state->u.f4.fld.exticr3.exti10 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI10"); + state->u.f4.fld.exticr3.exti11 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI11"); + + // EXTICR4 bitfields. + state->u.f4.fld.exticr4.exti12 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI12"); + state->u.f4.fld.exticr4.exti13 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI13"); + state->u.f4.fld.exticr4.exti14 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI14"); + state->u.f4.fld.exticr4.exti15 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI15"); + + // CMPCR bitfields. + state->u.f4.fld.cmpcr.cmp_pd = cm_object_get_child_by_name(state->u.f4.reg.cmpcr, "CMP_PD"); + state->u.f4.fld.cmpcr.ready = cm_object_get_child_by_name(state->u.f4.reg.cmpcr, "READY"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_syscfg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_syscfg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_syscfg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_syscfg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_syscfg_is_enabled(Object *obj) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_syscfg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_syscfg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SYSCFG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SYSCFG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_syscfg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_syscfg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_syscfg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_syscfg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_syscfg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SYSCFGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_syscfg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SYSCFG); +} + +static void stm32_syscfg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_syscfg_reset_callback; + dc->realize = stm32_syscfg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_syscfg_is_enabled; +} + +static const TypeInfo stm32_syscfg_type_info = { + .name = TYPE_STM32_SYSCFG, + .parent = TYPE_STM32_SYSCFG_PARENT, + .instance_init = stm32_syscfg_instance_init_callback, + .instance_size = sizeof(STM32SYSCFGState), + .class_init = stm32_syscfg_class_init_callback, + .class_size = sizeof(STM32SYSCFGClass) }; + +static void stm32_syscfg_register_types(void) +{ + type_register_static(&stm32_syscfg_type_info); +} + +type_init(stm32_syscfg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/syscfg.h b/gnu-mcu-eclipse/devices/support/STM32F40x/syscfg.h new file mode 100644 index 0000000000..8e424832de --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/syscfg.h @@ -0,0 +1,154 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SYSCFG_H_ +#define STM32_SYSCFG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SYSCFG DEVICE_PATH_STM32 "SYSCFG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SYSCFG TYPE_STM32_PREFIX "syscfg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SYSCFG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SYSCFGParentClass; +typedef PeripheralState STM32SYSCFGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SYSCFG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SYSCFGClass, (obj), TYPE_STM32_SYSCFG) +#define STM32_SYSCFG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SYSCFGClass, (klass), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentClass parent_class; + // public: + + // None, so far. +} STM32SYSCFGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SYSCFG_STATE(obj) \ + OBJECT_CHECK(STM32SYSCFGState, (obj), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SYSCFG (System configuration controller) registers. + struct { + Object *memrm; // 0x0 (Memory remap register) + Object *pmc; // 0x4 (Peripheral mode configuration register) + Object *exticr1; // 0x8 (External interrupt configuration register 1) + Object *exticr2; // 0xC (External interrupt configuration register 2) + Object *exticr3; // 0x10 (External interrupt configuration register 3) + Object *exticr4; // 0x14 (External interrupt configuration register 4) + Object *cmpcr; // 0x20 (Compensation cell control register) + } reg; + + struct { + + // MEMRM (Memory remap register) bitfields. + struct { + Object *mem_mode; // [0:1] MEM_MODE + } memrm; + + // PMC (Peripheral mode configuration register) bitfields. + struct { + Object *mii_rmii_sel; // [23:23] Ethernet PHY interface selection + } pmc; + + // EXTICR1 (External interrupt configuration register 1) bitfields. + struct { + Object *exti0; // [0:3] EXTI x configuration (x = 0 to 3) + Object *exti1; // [4:7] EXTI x configuration (x = 0 to 3) + Object *exti2; // [8:11] EXTI x configuration (x = 0 to 3) + Object *exti3; // [12:15] EXTI x configuration (x = 0 to 3) + } exticr1; + + // EXTICR2 (External interrupt configuration register 2) bitfields. + struct { + Object *exti4; // [0:3] EXTI x configuration (x = 4 to 7) + Object *exti5; // [4:7] EXTI x configuration (x = 4 to 7) + Object *exti6; // [8:11] EXTI x configuration (x = 4 to 7) + Object *exti7; // [12:15] EXTI x configuration (x = 4 to 7) + } exticr2; + + // EXTICR3 (External interrupt configuration register 3) bitfields. + struct { + Object *exti8; // [0:3] EXTI x configuration (x = 8 to 11) + Object *exti9; // [4:7] EXTI x configuration (x = 8 to 11) + Object *exti10; // [8:11] EXTI10 + Object *exti11; // [12:15] EXTI x configuration (x = 8 to 11) + } exticr3; + + // EXTICR4 (External interrupt configuration register 4) bitfields. + struct { + Object *exti12; // [0:3] EXTI x configuration (x = 12 to 15) + Object *exti13; // [4:7] EXTI x configuration (x = 12 to 15) + Object *exti14; // [8:11] EXTI x configuration (x = 12 to 15) + Object *exti15; // [12:15] EXTI x configuration (x = 12 to 15) + } exticr4; + + // CMPCR (Compensation cell control register) bitfields. + struct { + Object *cmp_pd; // [0:0] Compensation cell power-down + Object *ready; // [8:8] READY + } cmpcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SYSCFGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SYSCFG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim1.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim1.c new file mode 100644 index 0000000000..0e0d0a54df --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim1.c @@ -0,0 +1,427 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim1_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f4.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCPC"); + state->u.f4.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCUS"); + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + state->u.f4.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS1"); + state->u.f4.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS1N"); + state->u.f4.fld.cr2.ois2 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS2"); + state->u.f4.fld.cr2.ois2n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS2N"); + state->u.f4.fld.cr2.ois3 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS3"); + state->u.f4.fld.cr2.ois3n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS3N"); + state->u.f4.fld.cr2.ois4 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS4"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.comie = cm_object_get_child_by_name(state->u.f4.reg.dier, "COMIE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.bie = cm_object_get_child_by_name(state->u.f4.reg.dier, "BIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.comde = cm_object_get_child_by_name(state->u.f4.reg.dier, "COMDE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.comif = cm_object_get_child_by_name(state->u.f4.reg.sr, "COMIF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.bif = cm_object_get_child_by_name(state->u.f4.reg.sr, "BIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.comg = cm_object_get_child_by_name(state->u.f4.reg.egr, "COMG"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + state->u.f4.fld.egr.bg = cm_object_get_child_by_name(state->u.f4.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NE"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NE"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NE"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // RCR bitfields. + state->u.f4.fld.rcr.rep = cm_object_get_child_by_name(state->u.f4.reg.rcr, "REP"); + + // BDTR bitfields. + state->u.f4.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "DTG"); + state->u.f4.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "LOCK"); + state->u.f4.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "OSSI"); + state->u.f4.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "OSSR"); + state->u.f4.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "BKE"); + state->u.f4.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "BKP"); + state->u.f4.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "AOE"); + state->u.f4.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "MOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim1_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim1_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim1_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim1_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim1_is_enabled(Object *obj) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim1_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim1_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM1)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM1State *state = STM32_TIM1_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM1"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim1_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim1_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim1_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim1_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim1_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM1EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim1_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM1); +} + +static void stm32_tim1_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim1_reset_callback; + dc->realize = stm32_tim1_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim1_is_enabled; +} + +static const TypeInfo stm32_tim1_type_info = { + .name = TYPE_STM32_TIM1, + .parent = TYPE_STM32_TIM1_PARENT, + .instance_init = stm32_tim1_instance_init_callback, + .instance_size = sizeof(STM32TIM1State), + .class_init = stm32_tim1_class_init_callback, + .class_size = sizeof(STM32TIM1Class) }; + +static void stm32_tim1_register_types(void) +{ + type_register_static(&stm32_tim1_type_info); +} + +type_init(stm32_tim1_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim1.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim1.h new file mode 100644 index 0000000000..de5c1bbab8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim1.h @@ -0,0 +1,336 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM1_H_ +#define STM32_TIM1_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM1 DEVICE_PATH_STM32 "TIM1" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM1 TYPE_STM32_PREFIX "tim1" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM1_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM1ParentClass; +typedef PeripheralState STM32TIM1ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM1_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM1Class, (obj), TYPE_STM32_TIM1) +#define STM32_TIM1_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM1Class, (klass), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM1Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM1_STATE(obj) \ + OBJECT_CHECK(STM32TIM1State, (obj), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM1 (Advanced-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *rcr; // 0x30 (Repetition counter register) + Object *bdtr; // 0x44 (Break and dead-time register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + Object *ois2; // [10:10] Output Idle state 2 + Object *ois2n; // [11:11] Output Idle state 2 + Object *ois3; // [12:12] Output Idle state 3 + Object *ois3n; // [13:13] Output Idle state 3 + Object *ois4; // [14:14] Output Idle state 4 + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *comde; // [13:13] COM DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *oc1ce; // [7:7] Output Compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + Object *oc2ce; // [15:15] Output Compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2ne; // [6:6] Capture/Compare 2 complementary output enable + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3ne; // [10:10] Capture/Compare 3 complementary output enable + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM1State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM1_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim10.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim10.c new file mode 100644 index 0000000000..3568afef83 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim10.c @@ -0,0 +1,293 @@ +/* + * STM32 - TIM10 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim10_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim10_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim10_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim10_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim10_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim10_is_enabled(Object *obj) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim10_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim10_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM10)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM10State *state = STM32_TIM10_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM10"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim10_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim10_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim10_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim10_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim10_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM10EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim10_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM10); +} + +static void stm32_tim10_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim10_reset_callback; + dc->realize = stm32_tim10_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim10_is_enabled; +} + +static const TypeInfo stm32_tim10_type_info = { + .name = TYPE_STM32_TIM10, + .parent = TYPE_STM32_TIM10_PARENT, + .instance_init = stm32_tim10_instance_init_callback, + .instance_size = sizeof(STM32TIM10State), + .class_init = stm32_tim10_class_init_callback, + .class_size = sizeof(STM32TIM10Class) }; + +static void stm32_tim10_register_types(void) +{ + type_register_static(&stm32_tim10_type_info); +} + +type_init(stm32_tim10_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim10.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim10.h new file mode 100644 index 0000000000..db54c1c071 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim10.h @@ -0,0 +1,180 @@ +/* + * STM32 - TIM10 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM10_H_ +#define STM32_TIM10_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM10 DEVICE_PATH_STM32 "TIM10" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM10 TYPE_STM32_PREFIX "tim10" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM10_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM10ParentClass; +typedef PeripheralState STM32TIM10ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM10_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM10Class, (obj), TYPE_STM32_TIM10) +#define STM32_TIM10_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM10Class, (klass), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM10Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM10_STATE(obj) \ + OBJECT_CHECK(STM32TIM10State, (obj), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM10 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM10State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM10_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim11.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim11.c new file mode 100644 index 0000000000..f67e519c1f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim11.c @@ -0,0 +1,297 @@ +/* + * STM32 - TIM11 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim11_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // OR bitfields. + state->u.f4.fld.or_.rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim11_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim11_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim11_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim11_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim11_is_enabled(Object *obj) +{ + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim11_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim11_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM11)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM11State *state = STM32_TIM11_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM11"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim11_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim11_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim11_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim11_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim11_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM11EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim11_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM11); +} + +static void stm32_tim11_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim11_reset_callback; + dc->realize = stm32_tim11_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim11_is_enabled; +} + +static const TypeInfo stm32_tim11_type_info = { + .name = TYPE_STM32_TIM11, + .parent = TYPE_STM32_TIM11_PARENT, + .instance_init = stm32_tim11_instance_init_callback, + .instance_size = sizeof(STM32TIM11State), + .class_init = stm32_tim11_class_init_callback, + .class_size = sizeof(STM32TIM11Class) }; + +static void stm32_tim11_register_types(void) +{ + type_register_static(&stm32_tim11_type_info); +} + +type_init(stm32_tim11_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim11.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim11.h new file mode 100644 index 0000000000..22f02a5127 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim11.h @@ -0,0 +1,186 @@ +/* + * STM32 - TIM11 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM11_H_ +#define STM32_TIM11_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM11 DEVICE_PATH_STM32 "TIM11" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM11 TYPE_STM32_PREFIX "tim11" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM11_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM11ParentClass; +typedef PeripheralState STM32TIM11ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM11_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM11Class, (obj), TYPE_STM32_TIM11) +#define STM32_TIM11_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM11Class, (klass), TYPE_STM32_TIM11) + +typedef struct { + // private: + STM32TIM11ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM11Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM11_STATE(obj) \ + OBJECT_CHECK(STM32TIM11State, (obj), TYPE_STM32_TIM11) + +typedef struct { + // private: + STM32TIM11ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM11 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *or_; // 0x50 (Option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // OR (Option register) bitfields. + struct { + Object *rmp; // [0:1] Input 1 remapping capability + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM11State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM11_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim2.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim2.c new file mode 100644 index 0000000000..9be5ba1f13 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim2.c @@ -0,0 +1,404 @@ +/* + * STM32 - TIM2 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // OR bitfields. + state->u.f4.fld.or_.itr1_rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "ITR1_RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim2_is_enabled(Object *obj) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM2State *state = STM32_TIM2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim2_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM2EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM2); +} + +static void stm32_tim2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim2_reset_callback; + dc->realize = stm32_tim2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim2_is_enabled; +} + +static const TypeInfo stm32_tim2_type_info = { + .name = TYPE_STM32_TIM2, + .parent = TYPE_STM32_TIM2_PARENT, + .instance_init = stm32_tim2_instance_init_callback, + .instance_size = sizeof(STM32TIM2State), + .class_init = stm32_tim2_class_init_callback, + .class_size = sizeof(STM32TIM2Class) }; + +static void stm32_tim2_register_types(void) +{ + type_register_static(&stm32_tim2_type_info); +} + +type_init(stm32_tim2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim2.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim2.h new file mode 100644 index 0000000000..142585db3d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim2.h @@ -0,0 +1,311 @@ +/* + * STM32 - TIM2 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM2_H_ +#define STM32_TIM2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM2 DEVICE_PATH_STM32 "TIM2" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM2 TYPE_STM32_PREFIX "tim2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM2ParentClass; +typedef PeripheralState STM32TIM2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM2Class, (obj), TYPE_STM32_TIM2) +#define STM32_TIM2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM2Class, (klass), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM2_STATE(obj) \ + OBJECT_CHECK(STM32TIM2State, (obj), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM2 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *or_; // 0x50 (TIM5 option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // OR (TIM5 option register) bitfields. + struct { + Object *itr1_rmp; // [10:11] Timer Input 4 remap + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim3.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim3.c new file mode 100644 index 0000000000..99e434c036 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim3.c @@ -0,0 +1,400 @@ +/* + * STM32 - TIM3 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim3_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim3_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim3_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim3_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim3_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim3_is_enabled(Object *obj) +{ + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim3_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim3_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM3)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM3State *state = STM32_TIM3_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM3"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim3_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim3_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim3_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim3_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim3_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM3EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim3_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM3); +} + +static void stm32_tim3_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim3_reset_callback; + dc->realize = stm32_tim3_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim3_is_enabled; +} + +static const TypeInfo stm32_tim3_type_info = { + .name = TYPE_STM32_TIM3, + .parent = TYPE_STM32_TIM3_PARENT, + .instance_init = stm32_tim3_instance_init_callback, + .instance_size = sizeof(STM32TIM3State), + .class_init = stm32_tim3_class_init_callback, + .class_size = sizeof(STM32TIM3Class) }; + +static void stm32_tim3_register_types(void) +{ + type_register_static(&stm32_tim3_type_info); +} + +type_init(stm32_tim3_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim3.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim3.h new file mode 100644 index 0000000000..7f70acd7eb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim3.h @@ -0,0 +1,305 @@ +/* + * STM32 - TIM3 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM3_H_ +#define STM32_TIM3_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM3 DEVICE_PATH_STM32 "TIM3" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM3 TYPE_STM32_PREFIX "tim3" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM3_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM3ParentClass; +typedef PeripheralState STM32TIM3ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM3_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM3Class, (obj), TYPE_STM32_TIM3) +#define STM32_TIM3_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM3Class, (klass), TYPE_STM32_TIM3) + +typedef struct { + // private: + STM32TIM3ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM3Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM3_STATE(obj) \ + OBJECT_CHECK(STM32TIM3State, (obj), TYPE_STM32_TIM3) + +typedef struct { + // private: + STM32TIM3ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM3 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM3State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM3_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim5.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim5.c new file mode 100644 index 0000000000..e51dd10e81 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim5.c @@ -0,0 +1,404 @@ +/* + * STM32 - TIM5 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim5_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // OR bitfields. + state->u.f4.fld.or_.it4_rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "IT4_RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim5_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim5_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim5_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim5_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim5_is_enabled(Object *obj) +{ + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim5_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim5_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM5)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM5State *state = STM32_TIM5_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM5"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim5_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim5_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim5_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim5_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim5_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM5EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim5_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM5); +} + +static void stm32_tim5_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim5_reset_callback; + dc->realize = stm32_tim5_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim5_is_enabled; +} + +static const TypeInfo stm32_tim5_type_info = { + .name = TYPE_STM32_TIM5, + .parent = TYPE_STM32_TIM5_PARENT, + .instance_init = stm32_tim5_instance_init_callback, + .instance_size = sizeof(STM32TIM5State), + .class_init = stm32_tim5_class_init_callback, + .class_size = sizeof(STM32TIM5Class) }; + +static void stm32_tim5_register_types(void) +{ + type_register_static(&stm32_tim5_type_info); +} + +type_init(stm32_tim5_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim5.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim5.h new file mode 100644 index 0000000000..41d6bcf531 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim5.h @@ -0,0 +1,311 @@ +/* + * STM32 - TIM5 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM5_H_ +#define STM32_TIM5_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM5 DEVICE_PATH_STM32 "TIM5" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM5 TYPE_STM32_PREFIX "tim5" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM5_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM5ParentClass; +typedef PeripheralState STM32TIM5ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM5_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM5Class, (obj), TYPE_STM32_TIM5) +#define STM32_TIM5_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM5Class, (klass), TYPE_STM32_TIM5) + +typedef struct { + // private: + STM32TIM5ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM5Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM5_STATE(obj) \ + OBJECT_CHECK(STM32TIM5State, (obj), TYPE_STM32_TIM5) + +typedef struct { + // private: + STM32TIM5ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM5 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *or_; // 0x50 (TIM5 option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // OR (TIM5 option register) bitfields. + struct { + Object *it4_rmp; // [6:7] Timer Input 4 remap + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM5State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM5_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim6.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim6.c new file mode 100644 index 0000000000..c64fa6e167 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim6.c @@ -0,0 +1,271 @@ +/* + * STM32 - TIM6 (Basic timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim6_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim6_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim6_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim6_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim6_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim6_is_enabled(Object *obj) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim6_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim6_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM6)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM6State *state = STM32_TIM6_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM6"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim6_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim6_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim6_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim6_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim6_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM6EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim6_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM6); +} + +static void stm32_tim6_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim6_reset_callback; + dc->realize = stm32_tim6_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim6_is_enabled; +} + +static const TypeInfo stm32_tim6_type_info = { + .name = TYPE_STM32_TIM6, + .parent = TYPE_STM32_TIM6_PARENT, + .instance_init = stm32_tim6_instance_init_callback, + .instance_size = sizeof(STM32TIM6State), + .class_init = stm32_tim6_class_init_callback, + .class_size = sizeof(STM32TIM6Class) }; + +static void stm32_tim6_register_types(void) +{ + type_register_static(&stm32_tim6_type_info); +} + +type_init(stm32_tim6_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim6.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim6.h new file mode 100644 index 0000000000..01ec26bc05 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim6.h @@ -0,0 +1,152 @@ +/* + * STM32 - TIM6 (Basic timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM6_H_ +#define STM32_TIM6_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM6 DEVICE_PATH_STM32 "TIM6" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM6 TYPE_STM32_PREFIX "tim6" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM6_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM6ParentClass; +typedef PeripheralState STM32TIM6ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM6_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM6Class, (obj), TYPE_STM32_TIM6) +#define STM32_TIM6_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM6Class, (klass), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM6Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM6_STATE(obj) \ + OBJECT_CHECK(STM32TIM6State, (obj), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM6 (Basic timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *ude; // [8:8] Update DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + } egr; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Low counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Low Auto-reload value + } arr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM6State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM6_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim9.c b/gnu-mcu-eclipse/devices/support/STM32F40x/tim9.c new file mode 100644 index 0000000000..4ac6346617 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim9.c @@ -0,0 +1,325 @@ +/* + * STM32 - TIM9 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_tim9_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim9_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim9_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim9_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim9_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim9_is_enabled(Object *obj) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim9_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim9_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM9)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM9State *state = STM32_TIM9_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM9"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_tim9_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim9_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim9_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim9_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim9_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM9EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim9_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM9); +} + +static void stm32_tim9_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim9_reset_callback; + dc->realize = stm32_tim9_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim9_is_enabled; +} + +static const TypeInfo stm32_tim9_type_info = { + .name = TYPE_STM32_TIM9, + .parent = TYPE_STM32_TIM9_PARENT, + .instance_init = stm32_tim9_instance_init_callback, + .instance_size = sizeof(STM32TIM9State), + .class_init = stm32_tim9_class_init_callback, + .class_size = sizeof(STM32TIM9Class) }; + +static void stm32_tim9_register_types(void) +{ + type_register_static(&stm32_tim9_type_info); +} + +type_init(stm32_tim9_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/tim9.h b/gnu-mcu-eclipse/devices/support/STM32F40x/tim9.h new file mode 100644 index 0000000000..c05086f65e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/tim9.h @@ -0,0 +1,218 @@ +/* + * STM32 - TIM9 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM9_H_ +#define STM32_TIM9_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM9 DEVICE_PATH_STM32 "TIM9" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM9 TYPE_STM32_PREFIX "tim9" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM9_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM9ParentClass; +typedef PeripheralState STM32TIM9ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM9_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM9Class, (obj), TYPE_STM32_TIM9) +#define STM32_TIM9_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM9Class, (klass), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM9Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM9_STATE(obj) \ + OBJECT_CHECK(STM32TIM9State, (obj), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM9 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:6] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:14] Input capture 2 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM9State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM9_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/uart4.c b/gnu-mcu-eclipse/devices/support/STM32F40x/uart4.c new file mode 100644 index 0000000000..af5e5f7da5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/uart4.c @@ -0,0 +1,296 @@ +/* + * STM32 - UART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_uart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + + + // SR bitfields. + state->u.f4.fld.sr.pe = cm_object_get_child_by_name(state->u.f4.reg.sr, "PE"); + state->u.f4.fld.sr.fe = cm_object_get_child_by_name(state->u.f4.reg.sr, "FE"); + state->u.f4.fld.sr.nf = cm_object_get_child_by_name(state->u.f4.reg.sr, "NF"); + state->u.f4.fld.sr.ore = cm_object_get_child_by_name(state->u.f4.reg.sr, "ORE"); + state->u.f4.fld.sr.idle = cm_object_get_child_by_name(state->u.f4.reg.sr, "IDLE"); + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.tc = cm_object_get_child_by_name(state->u.f4.reg.sr, "TC"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.lbd = cm_object_get_child_by_name(state->u.f4.reg.sr, "LBD"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // BRR bitfields. + state->u.f4.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Fraction"); + state->u.f4.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f4.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SBK"); + state->u.f4.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RWU"); + state->u.f4.fld.cr1.re = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RE"); + state->u.f4.fld.cr1.te = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TE"); + state->u.f4.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "IDLEIE"); + state->u.f4.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXNEIE"); + state->u.f4.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TCIE"); + state->u.f4.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TXEIE"); + state->u.f4.fld.cr1.peie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEIE"); + state->u.f4.fld.cr1.ps = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PS"); + state->u.f4.fld.cr1.pce = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PCE"); + state->u.f4.fld.cr1.wake = cm_object_get_child_by_name(state->u.f4.reg.cr1, "WAKE"); + state->u.f4.fld.cr1.m = cm_object_get_child_by_name(state->u.f4.reg.cr1, "M"); + state->u.f4.fld.cr1.ue = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UE"); + state->u.f4.fld.cr1.over8 = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVER8"); + + // CR2 bitfields. + state->u.f4.fld.cr2.add = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADD"); + state->u.f4.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDL"); + state->u.f4.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDIE"); + state->u.f4.fld.cr2.stop = cm_object_get_child_by_name(state->u.f4.reg.cr2, "STOP"); + state->u.f4.fld.cr2.linen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f4.fld.cr3.eie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "EIE"); + state->u.f4.fld.cr3.iren = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IREN"); + state->u.f4.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IRLP"); + state->u.f4.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f4.reg.cr3, "HDSEL"); + state->u.f4.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAR"); + state->u.f4.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAT"); + state->u.f4.fld.cr3.onebit = cm_object_get_child_by_name(state->u.f4.reg.cr3, "ONEBIT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_uart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_uart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_uart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_uart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_uart_is_enabled(Object *obj) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_uart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32UARTState *state = STM32_UART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_UART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_uart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_UART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32UARTState *state = STM32_UART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "UART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_uart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_uart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_uart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_uart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_uart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/UART%dEN", + 1 + state->port_index - STM32_PORT_UART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_uart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_UART); +} + +static void stm32_uart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_uart_reset_callback; + dc->realize = stm32_uart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_uart_is_enabled; +} + +static const TypeInfo stm32_uart_type_info = { + .name = TYPE_STM32_UART, + .parent = TYPE_STM32_UART_PARENT, + .instance_init = stm32_uart_instance_init_callback, + .instance_size = sizeof(STM32UARTState), + .class_init = stm32_uart_class_init_callback, + .class_size = sizeof(STM32UARTClass) }; + +static void stm32_uart_register_types(void) +{ + type_register_static(&stm32_uart_type_info); +} + +type_init(stm32_uart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/uart4.h b/gnu-mcu-eclipse/devices/support/STM32F40x/uart4.h new file mode 100644 index 0000000000..827b5d2935 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/uart4.h @@ -0,0 +1,179 @@ +/* + * STM32 - UART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_UART_H_ +#define STM32_UART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_UART DEVICE_PATH_STM32 "UART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_UART4, + STM32_PORT_UART5, + STM32_PORT_UART_UNDEFINED = 0xFF, +} stm32_uart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_UART TYPE_STM32_PREFIX "uart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_UART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32UARTParentClass; +typedef PeripheralState STM32UARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32UARTClass, (obj), TYPE_STM32_UART) +#define STM32_UART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32UARTClass, (klass), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentClass parent_class; + // public: + + // None, so far. +} STM32UARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_UART_STATE(obj) \ + OBJECT_CHECK(STM32UARTState, (obj), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_uart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 UART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *dr; // 0x4 (Data register) + Object *brr; // 0x8 (Baud rate register) + Object *cr1; // 0xC (Control register 1) + Object *cr2; // 0x10 (Control register 2) + Object *cr3; // 0x14 (Control register 3) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *nf; // [2:2] Noise detected flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:8] Data value + } dr; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // CR1 (Control register 1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + Object *over8; // [15:15] Oversampling mode + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *onebit; // [11:11] One sample bit method enable + } cr3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32UARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_UART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/usart6.c b/gnu-mcu-eclipse/devices/support/STM32F40x/usart6.c new file mode 100644 index 0000000000..8ae700187e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/usart6.c @@ -0,0 +1,311 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_usart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + state->u.f4.reg.gtpr = cm_object_get_child_by_name(obj, "GTPR"); + + + // SR bitfields. + state->u.f4.fld.sr.pe = cm_object_get_child_by_name(state->u.f4.reg.sr, "PE"); + state->u.f4.fld.sr.fe = cm_object_get_child_by_name(state->u.f4.reg.sr, "FE"); + state->u.f4.fld.sr.nf = cm_object_get_child_by_name(state->u.f4.reg.sr, "NF"); + state->u.f4.fld.sr.ore = cm_object_get_child_by_name(state->u.f4.reg.sr, "ORE"); + state->u.f4.fld.sr.idle = cm_object_get_child_by_name(state->u.f4.reg.sr, "IDLE"); + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.tc = cm_object_get_child_by_name(state->u.f4.reg.sr, "TC"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.lbd = cm_object_get_child_by_name(state->u.f4.reg.sr, "LBD"); + state->u.f4.fld.sr.cts = cm_object_get_child_by_name(state->u.f4.reg.sr, "CTS"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // BRR bitfields. + state->u.f4.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Fraction"); + state->u.f4.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f4.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SBK"); + state->u.f4.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RWU"); + state->u.f4.fld.cr1.re = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RE"); + state->u.f4.fld.cr1.te = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TE"); + state->u.f4.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "IDLEIE"); + state->u.f4.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXNEIE"); + state->u.f4.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TCIE"); + state->u.f4.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TXEIE"); + state->u.f4.fld.cr1.peie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEIE"); + state->u.f4.fld.cr1.ps = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PS"); + state->u.f4.fld.cr1.pce = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PCE"); + state->u.f4.fld.cr1.wake = cm_object_get_child_by_name(state->u.f4.reg.cr1, "WAKE"); + state->u.f4.fld.cr1.m = cm_object_get_child_by_name(state->u.f4.reg.cr1, "M"); + state->u.f4.fld.cr1.ue = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UE"); + state->u.f4.fld.cr1.over8 = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVER8"); + + // CR2 bitfields. + state->u.f4.fld.cr2.add = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADD"); + state->u.f4.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDL"); + state->u.f4.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDIE"); + state->u.f4.fld.cr2.lbcl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBCL"); + state->u.f4.fld.cr2.cpha = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CPHA"); + state->u.f4.fld.cr2.cpol = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CPOL"); + state->u.f4.fld.cr2.clken = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CLKEN"); + state->u.f4.fld.cr2.stop = cm_object_get_child_by_name(state->u.f4.reg.cr2, "STOP"); + state->u.f4.fld.cr2.linen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f4.fld.cr3.eie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "EIE"); + state->u.f4.fld.cr3.iren = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IREN"); + state->u.f4.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IRLP"); + state->u.f4.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f4.reg.cr3, "HDSEL"); + state->u.f4.fld.cr3.nack = cm_object_get_child_by_name(state->u.f4.reg.cr3, "NACK"); + state->u.f4.fld.cr3.scen = cm_object_get_child_by_name(state->u.f4.reg.cr3, "SCEN"); + state->u.f4.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAR"); + state->u.f4.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAT"); + state->u.f4.fld.cr3.rtse = cm_object_get_child_by_name(state->u.f4.reg.cr3, "RTSE"); + state->u.f4.fld.cr3.ctse = cm_object_get_child_by_name(state->u.f4.reg.cr3, "CTSE"); + state->u.f4.fld.cr3.ctsie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "CTSIE"); + state->u.f4.fld.cr3.onebit = cm_object_get_child_by_name(state->u.f4.reg.cr3, "ONEBIT"); + + // GTPR bitfields. + state->u.f4.fld.gtpr.psc = cm_object_get_child_by_name(state->u.f4.reg.gtpr, "PSC"); + state->u.f4.fld.gtpr.gt = cm_object_get_child_by_name(state->u.f4.reg.gtpr, "GT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usart_is_enabled(Object *obj) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USARTState *state = STM32_USART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_USART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USARTState *state = STM32_USART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_usart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_usart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_usart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_usart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_usart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USART%dEN", + 1 + state->port_index - STM32_PORT_USART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USART); +} + +static void stm32_usart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usart_reset_callback; + dc->realize = stm32_usart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usart_is_enabled; +} + +static const TypeInfo stm32_usart_type_info = { + .name = TYPE_STM32_USART, + .parent = TYPE_STM32_USART_PARENT, + .instance_init = stm32_usart_instance_init_callback, + .instance_size = sizeof(STM32USARTState), + .class_init = stm32_usart_class_init_callback, + .class_size = sizeof(STM32USARTClass) }; + +static void stm32_usart_register_types(void) +{ + type_register_static(&stm32_usart_type_info); +} + +type_init(stm32_usart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/usart6.h b/gnu-mcu-eclipse/devices/support/STM32F40x/usart6.h new file mode 100644 index 0000000000..327edc7d66 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/usart6.h @@ -0,0 +1,198 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USART_H_ +#define STM32_USART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USART DEVICE_PATH_STM32 "USART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_USART1, + STM32_PORT_USART2, + STM32_PORT_USART3, + STM32_PORT_USART6, + STM32_PORT_USART_UNDEFINED = 0xFF, +} stm32_usart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USART TYPE_STM32_PREFIX "usart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USARTParentClass; +typedef PeripheralState STM32USARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USARTClass, (obj), TYPE_STM32_USART) +#define STM32_USART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USARTClass, (klass), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentClass parent_class; + // public: + + // None, so far. +} STM32USARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USART_STATE(obj) \ + OBJECT_CHECK(STM32USARTState, (obj), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_usart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 USART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *dr; // 0x4 (Data register) + Object *brr; // 0x8 (Baud rate register) + Object *cr1; // 0xC (Control register 1) + Object *cr2; // 0x10 (Control register 2) + Object *cr3; // 0x14 (Control register 3) + Object *gtpr; // 0x18 (Guard time and prescaler register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *nf; // [2:2] Noise detected flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + Object *cts; // [9:9] CTS flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:8] Data value + } dr; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // CR1 (Control register 1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + Object *over8; // [15:15] Oversampling mode + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *lbcl; // [8:8] Last bit clock pulse + Object *cpha; // [9:9] Clock phase + Object *cpol; // [10:10] Clock polarity + Object *clken; // [11:11] Clock enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *nack; // [4:4] Smartcard NACK enable + Object *scen; // [5:5] Smartcard mode enable + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *rtse; // [8:8] RTS enable + Object *ctse; // [9:9] CTS enable + Object *ctsie; // [10:10] CTS interrupt enable + Object *onebit; // [11:11] One sample bit method enable + } cr3; + + // GTPR (Guard time and prescaler register) bitfields. + struct { + Object *psc; // [0:7] Prescaler value + Object *gt; // [8:15] Guard time value + } gtpr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/wwdg.c b/gnu-mcu-eclipse/devices/support/STM32F40x/wwdg.c new file mode 100644 index 0000000000..992056701e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/wwdg.c @@ -0,0 +1,250 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f40x_wwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.cfr = cm_object_get_child_by_name(obj, "CFR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f4.fld.cr.t = cm_object_get_child_by_name(state->u.f4.reg.cr, "T"); + state->u.f4.fld.cr.wdga = cm_object_get_child_by_name(state->u.f4.reg.cr, "WDGA"); + + // CFR bitfields. + state->u.f4.fld.cfr.w = cm_object_get_child_by_name(state->u.f4.reg.cfr, "W"); + state->u.f4.fld.cfr.wdgtb0 = cm_object_get_child_by_name(state->u.f4.reg.cfr, "WDGTB0"); + state->u.f4.fld.cfr.wdgtb1 = cm_object_get_child_by_name(state->u.f4.reg.cfr, "WDGTB1"); + state->u.f4.fld.cfr.ewi = cm_object_get_child_by_name(state->u.f4.reg.cfr, "EWI"); + + // SR bitfields. + state->u.f4.fld.sr.ewif = cm_object_get_child_by_name(state->u.f4.reg.sr, "EWIF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_wwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_wwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_wwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_wwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_wwdg_is_enabled(Object *obj) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_wwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_wwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_WWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32WWDGState *state = STM32_WWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "WWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_40x ) { + + stm32f40x_wwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_wwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_wwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_wwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_wwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/WWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_wwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_WWDG); +} + +static void stm32_wwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_wwdg_reset_callback; + dc->realize = stm32_wwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_wwdg_is_enabled; +} + +static const TypeInfo stm32_wwdg_type_info = { + .name = TYPE_STM32_WWDG, + .parent = TYPE_STM32_WWDG_PARENT, + .instance_init = stm32_wwdg_instance_init_callback, + .instance_size = sizeof(STM32WWDGState), + .class_init = stm32_wwdg_class_init_callback, + .class_size = sizeof(STM32WWDGClass) }; + +static void stm32_wwdg_register_types(void) +{ + type_register_static(&stm32_wwdg_type_info); +} + +type_init(stm32_wwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F40x/wwdg.h b/gnu-mcu-eclipse/devices/support/STM32F40x/wwdg.h new file mode 100644 index 0000000000..9e32867abb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F40x/wwdg.h @@ -0,0 +1,121 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_WWDG_H_ +#define STM32_WWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_WWDG DEVICE_PATH_STM32 "WWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_WWDG TYPE_STM32_PREFIX "wwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_WWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32WWDGParentClass; +typedef PeripheralState STM32WWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_WWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32WWDGClass, (obj), TYPE_STM32_WWDG) +#define STM32_WWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32WWDGClass, (klass), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentClass parent_class; + // public: + + // None, so far. +} STM32WWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_WWDG_STATE(obj) \ + OBJECT_CHECK(STM32WWDGState, (obj), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 WWDG (Window watchdog) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *cfr; // 0x4 (Configuration register) + Object *sr; // 0x8 (Status register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *t; // [0:6] 7-bit counter (MSB to LSB) + Object *wdga; // [7:7] Activation bit + } cr; + + // CFR (Configuration register) bitfields. + struct { + Object *w; // [0:6] 7-bit window value + Object *wdgtb0; // [7:7] Timer base + Object *wdgtb1; // [8:8] Timer base + Object *ewi; // [9:9] Early wakeup interrupt + } cfr; + + // SR (Status register) bitfields. + struct { + Object *ewif; // [0:0] Early wakeup interrupt flag + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32WWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_WWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx-patch.json b/gnu-mcu-eclipse/devices/support/STM32F411xx-patch.json new file mode 100644 index 0000000000..8ce3b67c99 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx-patch.json @@ -0,0 +1,139 @@ +{ + "comment": "Patch for QEMU use.", + "device": { + "name": "STM32F411xx", + "cpu": { + "name": "CM4", + "revision": "r0p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "true", + "nvicPrioBits": "4", + "deviceNumInterrupts": "86", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "access": "read-write", + "qemuAlignment": "any", + "peripherals": [ + { + "name": "GPIOA", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOG", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOH", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOI", + "qemuGroupName": "GPIO" + }, + { + "name": "USART1", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART2", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART3", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART6", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART4", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART5", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "ADC1", + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "qemuGroupName": "ADC" + }, + { + "name": "I2C1", + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "qemuGroupName": "I2C" + }, + { + "name": "I2C3", + "qemuGroupName": "I2C" + }, + { + "name": "CAN1", + "qemuGroupName": "CAN" + }, + { + "name": "CAN2", + "qemuGroupName": "CAN" + }, + { + "name": "DMA1", + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "qemuGroupName": "DMA" + }, + { + "name": "SPI1", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "qemuGroupName": "SPI" + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx-xsvd.json b/gnu-mcu-eclipse/devices/support/STM32F411xx-xsvd.json new file mode 100644 index 0000000000..11f022af0f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx-xsvd.json @@ -0,0 +1,24365 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F411xx.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.10", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F411xx.svd", + "--output", + "STM32F411xx-xsvd.json" + ], + "date": "2016-12-25T11:51:46.377Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F411xx", + "version": "1.0", + "description": "STM32F411xx", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "ADC_Common", + "description": "ADC common registers", + "groupName": "ADC", + "baseAddress": "0x40012300", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x100", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FPU", + "description": "FPU interrupt", + "value": "81" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "ADC Common status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVR3", + "description": "Overrun flag of ADC3", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "STRT3", + "description": "Regular channel Start flag of ADC 3", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "JSTRT3", + "description": "Injected channel Start flag of ADC 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "JEOC3", + "description": "Injected channel end of conversion of ADC 3", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "EOC3", + "description": "End of conversion of ADC 3", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "AWD3", + "description": "Analog watchdog flag of ADC 3", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "OVR2", + "description": "Overrun flag of ADC 2", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "STRT2", + "description": "Regular channel Start flag of ADC 2", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "JSTRT2", + "description": "Injected channel Start flag of ADC 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEOC2", + "description": "Injected channel end of conversion of ADC 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOC2", + "description": "End of conversion of ADC 2", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "AWD2", + "description": "Analog watchdog flag of ADC 2", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OVR1", + "description": "Overrun flag of ADC 1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT1", + "description": "Regular channel Start flag of ADC 1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT1", + "description": "Injected channel Start flag of ADC 1", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC1", + "description": "Injected channel end of conversion of ADC 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC1", + "description": "End of conversion of ADC 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD1", + "description": "Analog watchdog flag of ADC 1", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "ADC common control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "VBATE", + "description": "VBAT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DMA", + "description": "Direct memory access mode for multi ADC mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "DDS", + "description": "DMA disable selection for multi-ADC mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DELAY", + "description": "Delay between 2 sampling phases", + "bitOffset": "8", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "ADC1", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVR", + "description": "Overrun", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Resolution", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "EXTEN", + "description": "External trigger enable for regular channels", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "JEXTEN", + "description": "External trigger enable for injected channels", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "EOCS", + "description": "End of conversion selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DDS", + "description": "DMA disable selection (for single ADC mode)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode (for single ADC mode)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADON", + "description": "A/D Converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "Cryptographic processor", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Control regidter", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DBGMCU_IDCODE", + "displayName": "DBGMCU_IDCODE", + "description": "IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x10006411", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DBGMCU_CR", + "displayName": "DBGMCU_CR", + "description": "Control Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + } + ] + }, + { + "name": "DBGMCU_APB1_FZ", + "displayName": "DBGMCU_APB1_FZ", + "description": "Debug MCU APB1 Freeze registe", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3 _STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBG_RTC_Stop", + "description": "RTC stopped when Core is halted", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDEG_STOP", + "description": "DBG_IWDEG_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_I2C1_SMBUS_TIMEOUT", + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DBG_I2C2_SMBUS_TIMEOUT", + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBG_I2C3SMBUS_TIMEOUT", + "description": "DBG_J2C3SMBUS_TIMEOUT", + "bitOffset": "23", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB2_FZ", + "displayName": "DBGMCU_APB2_FZ", + "description": "Debug MCU APB2 Freeze registe", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM1_STOP", + "description": "TIM1 counter stopped when core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM9_STOP", + "description": "TIM9 counter stopped when core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM10_STOP", + "description": "TIM10 counter stopped when core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM11_STOP", + "description": "TIM11 counter stopped when core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40013C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMP_STAMP", + "description": "Tamper and TimeStamp interrupts through the EXTI line", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Rising trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Rising trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Rising trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Falling trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Falling trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Falling trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SWIER20", + "description": "Software Interrupt on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SWIER21", + "description": "Software Interrupt on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWIER22", + "description": "Software Interrupt on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PR20", + "description": "Pending bit 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PR21", + "description": "Pending bit 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PR22", + "description": "Pending bit 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40023C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "FLASH global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bitOffset": "11", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OPERR", + "description": "Operation error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGPERR", + "description": "Programming parallelism error", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x80000000", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SER", + "description": "Sector Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SNB", + "description": "Sector number", + "bitOffset": "3", + "bitWidth": "4" + }, + { + "name": "PSIZE", + "description": "Program size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OPTCR", + "displayName": "OPTCR", + "description": "Flash option control register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000014", + "fields": [ + { + "name": "OPTLOCK", + "description": "Option lock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OPTSTRT", + "description": "Option start", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "WDG_SW", + "description": "WDG_SW User option bytes", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP User option bytes", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY User option bytes", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Read protect", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_FS_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + } + ] + }, + { + "name": "OTG_FS_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "OTG_FS_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VOS", + "description": "Regulator voltage scaling output selection", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "ADCDC1", + "description": "ADCDC1", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FPDS", + "description": "Flash power down in Stop mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BRR", + "description": "Backup regulator ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BRE", + "description": "Backup regulator enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VOSRDY", + "description": "Regulator voltage scaling output selection ready bit", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40023800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "PLLI2SRDY", + "description": "PLLI2S clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SON", + "description": "PLLI2S enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "Main PLL (PLL) clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLON", + "description": "Main PLL (PLL) enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock security system enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSEBYP", + "description": "HSE clock bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "HSE clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "HSE clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal high-speed clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal high-speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal high-speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSION", + "description": "Internal high-speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PLLCFGR", + "displayName": "PLLCFGR", + "description": "PLL configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003010", + "fields": [ + { + "name": "PLLQ3", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PLLQ2", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PLLQ1", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "PLLQ0", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "PLLSRC", + "description": "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PLLP1", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PLLP0", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PLLN8", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PLLN7", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PLLN6", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PLLN5", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PLLN4", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PLLN3", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PLLN2", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLLN1", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PLLN0", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PLLM5", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PLLM4", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLLM3", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLLM2", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PLLM1", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PLLM0", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCO2", + "description": "Microcontroller clock output 2", + "bitOffset": "30", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "MCO2PRE", + "description": "MCO2 prescaler", + "bitOffset": "27", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO1PRE", + "description": "MCO1 prescaler", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "I2SSRC", + "description": "I2S clock selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO1", + "description": "Microcontroller clock output 1", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCPRE", + "description": "HSE division factor for RTC clock", + "bitOffset": "16", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB high-speed prescaler (APB2)", + "bitOffset": "13", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "10", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "SWS1", + "description": "System clock switch status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SWS0", + "description": "System clock switch status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SW1", + "description": "System clock switch", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SW0", + "description": "System clock switch", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYC", + "description": "PLLI2S ready interrupt clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "Main PLL(PLL) ready interrupt clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE ready interrupt clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI ready interrupt clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE ready interrupt clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSIRDYC", + "description": "LSI ready interrupt clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYIE", + "description": "PLLI2S ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "Main PLL (PLL) ready interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE ready interrupt enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI ready interrupt enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE ready interrupt enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYIE", + "description": "LSI ready interrupt enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSF", + "description": "Clock security system interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SRDYF", + "description": "PLLI2S ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "Main PLL (PLL) ready interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE ready interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI ready interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE ready interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYF", + "description": "LSI ready interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "AHB1RSTR", + "displayName": "AHB1RSTR", + "description": "AHB1 peripheral reset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMA2RST", + "description": "DMA2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1RST", + "description": "DMA2 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CRCRST", + "description": "CRC reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOHRST", + "description": "IO port H reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOERST", + "description": "IO port E reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODRST", + "description": "IO port D reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCRST", + "description": "IO port C reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBRST", + "description": "IO port B reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOARST", + "description": "IO port A reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2RSTR", + "displayName": "AHB2RSTR", + "description": "AHB2 peripheral reset register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSRST", + "description": "USB OTG FS module reset", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "I2C3RST", + "description": "I2C3 reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C 2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C 1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "UART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI 3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI 2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "TIM5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "TIM4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "TIM3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM2RST", + "description": "TIM2 reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM11RST", + "description": "TIM11 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SYSCFGRST", + "description": "System configuration controller reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SDIORST", + "description": "SDIO reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset (common to all ADCs)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "USART6RST", + "description": "USART6 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM1RST", + "description": "TIM1 reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1ENR", + "displayName": "AHB1ENR", + "description": "AHB1 peripheral clock register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00100000", + "fields": [ + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOHEN", + "description": "IO port H clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOEEN", + "description": "IO port E clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODEN", + "description": "IO port D clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCEN", + "description": "IO port C clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBEN", + "description": "IO port B clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOAEN", + "description": "IO port A clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2ENR", + "displayName": "AHB2ENR", + "description": "AHB2 peripheral clock enable register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "I2C3EN", + "description": "I2C3 clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "TIM5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "TIM4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "TIM3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM2EN", + "description": "TIM2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1EN", + "description": "TIM1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6EN", + "description": "USART6 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC1 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4EN", + "description": "SPI4 clock enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGEN", + "description": "System configuration controller clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11EN", + "description": "TIM11 clock enable", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1LPENR", + "displayName": "AHB1LPENR", + "description": "AHB1 peripheral clock enable in low power mode register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7E6791FF", + "fields": [ + { + "name": "DMA2LPEN", + "description": "DMA2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1LPEN", + "description": "DMA1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SRAM1LPEN", + "description": "SRAM 1interface clock enable during Sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FLITFLPEN", + "description": "Flash interface clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CRCLPEN", + "description": "CRC clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOHLPEN", + "description": "IO port H clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOELPEN", + "description": "IO port E clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODLPEN", + "description": "IO port D clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCLPEN", + "description": "IO port C clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBLPEN", + "description": "IO port B clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOALPEN", + "description": "IO port A clock enable during sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2LPENR", + "displayName": "AHB2LPENR", + "description": "AHB2 peripheral clock enable in low power mode register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000F1", + "fields": [ + { + "name": "OTGFSLPEN", + "description": "USB OTG FS clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1LPENR", + "displayName": "APB1LPENR", + "description": "APB1 peripheral clock enable in low power mode register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x36FEC9FF", + "fields": [ + { + "name": "PWRLPEN", + "description": "Power interface clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "I2C3LPEN", + "description": "I2C3 clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "I2C2LPEN", + "description": "I2C2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C1LPEN", + "description": "I2C1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "USART2LPEN", + "description": "USART2 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SPI3LPEN", + "description": "SPI3 clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SPI2LPEN", + "description": "SPI2 clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WWDGLPEN", + "description": "Window watchdog clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TIM5LPEN", + "description": "TIM5 clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM4LPEN", + "description": "TIM4 clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM3LPEN", + "description": "TIM3 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM2LPEN", + "description": "TIM2 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2LPENR", + "displayName": "APB2LPENR", + "description": "APB2 peripheral clock enabled in low power mode register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00075F33", + "fields": [ + { + "name": "TIM1LPEN", + "description": "TIM1 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "USART1LPEN", + "description": "USART1 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6LPEN", + "description": "USART6 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1LPEN", + "description": "ADC1 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIOLPEN", + "description": "SDIO clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1LPEN", + "description": "SPI 1 clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4LPEN", + "description": "SPI4 clock enable during Sleep mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGLPEN", + "description": "System configuration controller clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9LPEN", + "description": "TIM9 clock enable during sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10LPEN", + "description": "TIM10 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11LPEN", + "description": "TIM11 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register", + "addressOffset": "0x70", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL1", + "description": "RTC clock source selection", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL0", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSEBYP", + "description": "External low-speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEON", + "description": "External low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Clock control & status register", + "addressOffset": "0x74", + "size": "0x20", + "resetValue": "0x0E000000", + "fields": [ + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PADRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BORRSTF", + "description": "BOR reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSION", + "description": "Internal low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SSCGR", + "displayName": "SSCGR", + "description": "Spread spectrum clock generation register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SSCGEN", + "description": "Spread spectrum modulation enable", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SPREADSEL", + "description": "Spread Select", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "INCSTEP", + "description": "Incrementation step", + "bitOffset": "13", + "bitWidth": "15" + }, + { + "name": "MODPER", + "description": "Modulation period", + "bitOffset": "0", + "bitWidth": "13" + } + ] + }, + { + "name": "PLLI2SCFGR", + "displayName": "PLLI2SCFGR", + "description": "PLLI2S configuration register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20003000", + "fields": [ + { + "name": "PLLI2SRx", + "description": "PLLI2S division factor for I2S clocks", + "bitOffset": "28", + "bitWidth": "3" + }, + { + "name": "PLLI2SNx", + "description": "PLLI2S multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "COSEL", + "description": "Calibration Output selection", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WUTIE", + "description": "Wakeup timer interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ALRBIE", + "description": "Alarm B interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WUTE", + "description": "Wakeup timer enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ALRBE", + "description": "Alarm B enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DCE", + "description": "Coarse digital calibration enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BYPSHAD", + "description": "Bypass the shadow registers", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "REFCKON", + "description": "Reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WCKSEL", + "description": "Wakeup clock selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALRBWF", + "description": "Alarm B write flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "WUTWF", + "description": "Wakeup timer write flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRBF", + "description": "Alarm B flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUTF", + "description": "Wakeup timer flag", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "Tamper detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "TAMPER2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + }, + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "WUTR", + "displayName": "WUTR", + "description": "Wakeup timer register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "WUT", + "description": "Wakeup auto-reload value bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALIBR", + "displayName": "CALIBR", + "description": "Calibration register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCS", + "description": "Digital calibration sign", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "Digital calibration", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "ALRMBR", + "displayName": "ALRMBR", + "description": "Alarm B register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm B date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm B hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm B minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm B seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADD1S", + "description": "Add one second", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Time stamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Time stamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Timestamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALP", + "description": "Increase frequency of RTC by 488.5 ppm", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALW16", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TAMPPUDIS", + "description": "TAMPER pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMPPRCH", + "description": "Tamper precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPFLT", + "description": "Tamper filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMP2TRG", + "description": "Active level for tamper 2", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "Tamper 2 detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "ALRMBSSR", + "displayName": "ALRMBSSR", + "description": "Alarm B sub second register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP5R", + "displayName": "BKP5R", + "description": "Backup register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP6R", + "displayName": "BKP6R", + "description": "Backup register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP7R", + "displayName": "BKP7R", + "description": "Backup register", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP8R", + "displayName": "BKP8R", + "description": "Backup register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP9R", + "displayName": "BKP9R", + "description": "Backup register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP10R", + "displayName": "BKP10R", + "description": "Backup register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP11R", + "displayName": "BKP11R", + "description": "Backup register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP12R", + "displayName": "BKP12R", + "description": "Backup register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP13R", + "displayName": "BKP13R", + "description": "Backup register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP14R", + "displayName": "BKP14R", + "description": "Backup register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP15R", + "displayName": "BKP15R", + "description": "Backup register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP16R", + "displayName": "BKP16R", + "description": "Backup register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP17R", + "displayName": "BKP17R", + "description": "Backup register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP18R", + "displayName": "BKP18R", + "description": "Backup register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP19R", + "displayName": "BKP19R", + "description": "Backup register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Argument register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "Command register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CE_ATACMD", + "description": "CE-ATA command", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "Not Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "Enable CMD completion", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SD I/O suspend command", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "Command path state machine (CPSM) Enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "CPSM Waits for ends of data transfer (CmdPend internal signal).", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WAITINT", + "description": "CPSM waits for interrupt request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITRESP", + "description": "Wait for response bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CMDINDEX", + "description": "Command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "Command response register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "Response command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESP1", + "displayName": "RESP1", + "description": "Response 1..4 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Response 1..4 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Response 1..4 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Response 1..4 register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "Card Status", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Data timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Data length register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "Data control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SDIOEN", + "description": "SD I/O enable functions", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "Read wait mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "RWSTOP", + "description": "Read wait stop", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWSTART", + "description": "Read wait start", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "Data block size", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DMAEN", + "description": "DMA enable bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "Data transfer mode selection 1: Stream or SDIO multibyte data transfer.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "Data transfer direction selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Data counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAEND", + "description": "CE-ATA command completion signal received for CMD61", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIO interrupt received", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "Data available in receive FIFO", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "Data available in transmit FIFO", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "Receive FIFO empty", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "Transmit FIFO empty", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "Receive FIFO full", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "Transmit FIFO full", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "Receive FIFO half full: there are at least 8 words in the FIFO", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "Transmit FIFO half empty: at least 8 words can be written into the FIFO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "Data receive in progress", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "Data transmit in progress", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "Command transfer in progress", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "Data block sent/received (CRC check passed)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "Start bit not detected on all data signals in wide bus mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "Data end (data counter, SDIDCOUNT, is zero)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "Command sent (no response required)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "Command response received (CRC check passed)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "Received FIFO overrun error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "Transmit FIFO underrun error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "Data timeout", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "Command response timeout", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "Data block sent/received (CRC check failed)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAIL", + "description": "Command response received (CRC check failed)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAENDC", + "description": "CEATAEND flag clear bit", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOIT flag clear bit", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKEND flag clear bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERR flag clear bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAEND flag clear bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENT flag clear bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDREND flag clear bit", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERR flag clear bit", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERR flag clear bit", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUT flag clear bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUT flag clear bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAIL flag clear bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAILC", + "description": "CCRCFAIL flag clear bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "Mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAENDIE", + "description": "CE-ATA command completion signal received interrupt enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIO mode interrupt received interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "Data available in Rx FIFO interrupt enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "Data available in Tx FIFO interrupt enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "Rx FIFO empty interrupt enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "Tx FIFO empty interrupt enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "Rx FIFO full interrupt enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "Tx FIFO full interrupt enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "Rx FIFO half full interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "Tx FIFO half empty interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "Data receive acting interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "Data transmit acting interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "Command acting interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBCKENDIE", + "description": "Data block end interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "Start bit error interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "Data end interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "Command sent interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "Command response received interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "Rx FIFO overrun error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "Tx FIFO underrun error interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "Data timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "Command timeout interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "Data CRC fail interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAILIE", + "description": "Command CRC fail interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "FIFO counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOCOUNT", + "description": "Remaining number of words to be written to or read from the FIFO.", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Data FIFO register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "Receive and transmit FIFO data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MEMRM", + "displayName": "MEMRM", + "description": "Memory remap register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "MEM_MODE", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PMC", + "displayName": "PMC", + "description": "Peripheral mode configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADC1DC2", + "description": "ADC1DC2", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI3", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI0", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI7", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI4", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI11", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI8", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI15", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI12", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CMPCR", + "displayName": "CMPCR", + "description": "Compensation cell control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "READY", + "description": "READY", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMP_PD", + "description": "Compensation cell power-down", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40010400" + }, + { + "name": "TIM10", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM11", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Input 1 remapping capability", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ITR1_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM3", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI4", + "description": "SPI4 global interrupt", + "value": "84" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM3", + "baseAddress": "0x40000800" + }, + { + "name": "TIM5", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "IT4_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "6", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM9", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "USART1", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40011000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS_WKUP", + "description": "USB On-The-Go FS Wakeup through EXTI line interrupt", + "value": "42" + }, + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "USART2", + "derivedFrom": "USART1", + "baseAddress": "0x40004400" + }, + { + "name": "USART6", + "derivedFrom": "USART1", + "baseAddress": "0x40011400" + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WDGTB1", + "description": "Timer base", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WDGTB0", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA2", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40026400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "LISR", + "displayName": "LISR", + "description": "Low interrupt status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TCIF3", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMEIF3", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FEIF3", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMEIF2", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FEIF2", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMEIF1", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FEIF1", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCIF0", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF0", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TEIF0", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMEIF0", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FEIF0", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "HISR", + "displayName": "HISR", + "description": "High interrupt status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TCIF7", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMEIF7", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FEIF7", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMEIF6", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FEIF6", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMEIF5", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FEIF5", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMEIF4", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FEIF4", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LIFCR", + "displayName": "LIFCR", + "description": "Low interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTCIF3", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CDMEIF3", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CFEIF3", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CDMEIF2", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CFEIF2", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CDMEIF1", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CFEIF1", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTCIF0", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF0", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTEIF0", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CDMEIF0", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CFEIF0", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "HIFCR", + "displayName": "HIFCR", + "description": "High interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTCIF7", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CDMEIF7", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CFEIF7", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CDMEIF6", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CFEIF6", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CDMEIF5", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CFEIF5", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CDMEIF4", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CFEIF4", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S0CR", + "displayName": "S0CR", + "description": "Stream x configuration register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S0NDTR", + "displayName": "S0NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S0PAR", + "displayName": "S0PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M0AR", + "displayName": "S0M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M1AR", + "displayName": "S0M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0FCR", + "displayName": "S0FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S1CR", + "displayName": "S1CR", + "description": "Stream x configuration register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S1NDTR", + "displayName": "S1NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S1PAR", + "displayName": "S1PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M0AR", + "displayName": "S1M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M1AR", + "displayName": "S1M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1FCR", + "displayName": "S1FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x3C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S2CR", + "displayName": "S2CR", + "description": "Stream x configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S2NDTR", + "displayName": "S2NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S2PAR", + "displayName": "S2PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M0AR", + "displayName": "S2M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M1AR", + "displayName": "S2M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2FCR", + "displayName": "S2FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S3CR", + "displayName": "S3CR", + "description": "Stream x configuration register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S3NDTR", + "displayName": "S3NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S3PAR", + "displayName": "S3PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M0AR", + "displayName": "S3M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M1AR", + "displayName": "S3M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3FCR", + "displayName": "S3FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x6C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S4CR", + "displayName": "S4CR", + "description": "Stream x configuration register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S4NDTR", + "displayName": "S4NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S4PAR", + "displayName": "S4PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M0AR", + "displayName": "S4M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M1AR", + "displayName": "S4M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4FCR", + "displayName": "S4FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S5CR", + "displayName": "S5CR", + "description": "Stream x configuration register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S5NDTR", + "displayName": "S5NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S5PAR", + "displayName": "S5PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M0AR", + "displayName": "S5M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M1AR", + "displayName": "S5M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5FCR", + "displayName": "S5FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x9C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S6CR", + "displayName": "S6CR", + "description": "Stream x configuration register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S6NDTR", + "displayName": "S6NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S6PAR", + "displayName": "S6PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M0AR", + "displayName": "S6M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M1AR", + "displayName": "S6M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6FCR", + "displayName": "S6FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xB4", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S7CR", + "displayName": "S7CR", + "description": "Stream x configuration register", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S7NDTR", + "displayName": "S7NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xBC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S7PAR", + "displayName": "S7PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xC0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M0AR", + "displayName": "S7M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M1AR", + "displayName": "S7M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xC8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7FCR", + "displayName": "S7FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xCC", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "DMA1", + "derivedFrom": "DMA2", + "baseAddress": "0x40026000", + "interrupts": [ + { + "name": "RTC_WKUP", + "description": "RTC Wakeup interrupt through the EXTI line", + "value": "3" + }, + { + "name": "RTC_Alarm", + "description": "RTC Alarms (A and B) through EXTI line interrupt", + "value": "41" + } + ] + }, + { + "name": "GPIOH", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40021C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOH", + "baseAddress": "0x40021000" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOH", + "baseAddress": "0X40020C00", + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ] + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOH", + "baseAddress": "0x40020800", + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ] + }, + { + "name": "GPIOB", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000280", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000C0", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000100", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xA8000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x64000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "I2C3", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + } + ] + }, + { + "name": "I2C2", + "derivedFrom": "I2C3", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ] + }, + { + "name": "I2C1", + "derivedFrom": "I2C3", + "baseAddress": "0x40005400", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ] + }, + { + "name": "I2S2ext", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40003400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "I2S3ext", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40004000" + }, + { + "name": "SPI1", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40013000" + }, + { + "name": "SPI2", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ] + }, + { + "name": "SPI3", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ] + }, + { + "name": "SPI4", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40013400", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ] + }, + { + "name": "SPI5", + "derivedFrom": "I2S2ext", + "baseAddress": "0x40015000" + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1001", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ICTR", + "displayName": "ICTR", + "description": "Interrupt Controller Type Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTLINESNUM", + "description": "Total number of interrupt lines in groups", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "STIR", + "displayName": "STIR", + "description": "Software Triggered Interrupt Register", + "addressOffset": "0xF00", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTID", + "description": "Interrupt to be triggered", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "ISER0", + "displayName": "ISER0", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER1", + "displayName": "ISER1", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER2", + "displayName": "ISER2", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER0", + "displayName": "ICER0", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER1", + "displayName": "ICER1", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER2", + "displayName": "ICER2", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR0", + "displayName": "ISPR0", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR1", + "displayName": "ISPR1", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR2", + "displayName": "ISPR2", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x208", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR0", + "displayName": "ICPR0", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR1", + "displayName": "ICPR1", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR2", + "displayName": "ICPR2", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR0", + "displayName": "IABR0", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR1", + "displayName": "IABR1", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR2", + "displayName": "IABR2", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register", + "addressOffset": "0x404", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register", + "addressOffset": "0x408", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register", + "addressOffset": "0x40C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register", + "addressOffset": "0x410", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register", + "addressOffset": "0x414", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register", + "addressOffset": "0x418", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register", + "addressOffset": "0x41C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR8", + "displayName": "IPR8", + "description": "Interrupt Priority Register", + "addressOffset": "0x420", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR9", + "displayName": "IPR9", + "description": "Interrupt Priority Register", + "addressOffset": "0x424", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR10", + "displayName": "IPR10", + "description": "Interrupt Priority Register", + "addressOffset": "0x428", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR11", + "displayName": "IPR11", + "description": "Interrupt Priority Register", + "addressOffset": "0x42C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR12", + "displayName": "IPR12", + "description": "Interrupt Priority Register", + "addressOffset": "0x430", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR13", + "displayName": "IPR13", + "description": "Interrupt Priority Register", + "addressOffset": "0x434", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR14", + "displayName": "IPR14", + "description": "Interrupt Priority Register", + "addressOffset": "0x438", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR15", + "displayName": "IPR15", + "description": "Interrupt Priority Register", + "addressOffset": "0x43C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR16", + "displayName": "IPR16", + "description": "Interrupt Priority Register", + "addressOffset": "0x440", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR17", + "displayName": "IPR17", + "description": "Interrupt Priority Register", + "addressOffset": "0x444", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR18", + "displayName": "IPR18", + "description": "Interrupt Priority Register", + "addressOffset": "0x448", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR19", + "displayName": "IPR19", + "description": "Interrupt Priority Register", + "addressOffset": "0x44C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/adc1.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc1.c new file mode 100644 index 0000000000..8038d26b16 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc1.c @@ -0,0 +1,366 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smpr1 = cm_object_get_child_by_name(obj, "SMPR1"); + state->u.f4.reg.smpr2 = cm_object_get_child_by_name(obj, "SMPR2"); + state->u.f4.reg.jofr1 = cm_object_get_child_by_name(obj, "JOFR1"); + state->u.f4.reg.jofr2 = cm_object_get_child_by_name(obj, "JOFR2"); + state->u.f4.reg.jofr3 = cm_object_get_child_by_name(obj, "JOFR3"); + state->u.f4.reg.jofr4 = cm_object_get_child_by_name(obj, "JOFR4"); + state->u.f4.reg.htr = cm_object_get_child_by_name(obj, "HTR"); + state->u.f4.reg.ltr = cm_object_get_child_by_name(obj, "LTR"); + state->u.f4.reg.sqr1 = cm_object_get_child_by_name(obj, "SQR1"); + state->u.f4.reg.sqr2 = cm_object_get_child_by_name(obj, "SQR2"); + state->u.f4.reg.sqr3 = cm_object_get_child_by_name(obj, "SQR3"); + state->u.f4.reg.jsqr = cm_object_get_child_by_name(obj, "JSQR"); + state->u.f4.reg.jdr1 = cm_object_get_child_by_name(obj, "JDR1"); + state->u.f4.reg.jdr2 = cm_object_get_child_by_name(obj, "JDR2"); + state->u.f4.reg.jdr3 = cm_object_get_child_by_name(obj, "JDR3"); + state->u.f4.reg.jdr4 = cm_object_get_child_by_name(obj, "JDR4"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // SR bitfields. + state->u.f4.fld.sr.awd = cm_object_get_child_by_name(state->u.f4.reg.sr, "AWD"); + state->u.f4.fld.sr.eoc = cm_object_get_child_by_name(state->u.f4.reg.sr, "EOC"); + state->u.f4.fld.sr.jeoc = cm_object_get_child_by_name(state->u.f4.reg.sr, "JEOC"); + state->u.f4.fld.sr.jstrt = cm_object_get_child_by_name(state->u.f4.reg.sr, "JSTRT"); + state->u.f4.fld.sr.strt = cm_object_get_child_by_name(state->u.f4.reg.sr, "STRT"); + state->u.f4.fld.sr.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OVR"); + + // CR1 bitfields. + state->u.f4.fld.cr1.awdch = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDCH"); + state->u.f4.fld.cr1.eocie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "EOCIE"); + state->u.f4.fld.cr1.awdie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDIE"); + state->u.f4.fld.cr1.jeocie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JEOCIE"); + state->u.f4.fld.cr1.scan = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SCAN"); + state->u.f4.fld.cr1.awdsgl = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDSGL"); + state->u.f4.fld.cr1.jauto = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JAUTO"); + state->u.f4.fld.cr1.discen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DISCEN"); + state->u.f4.fld.cr1.jdiscen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JDISCEN"); + state->u.f4.fld.cr1.discnum = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DISCNUM"); + state->u.f4.fld.cr1.jawden = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JAWDEN"); + state->u.f4.fld.cr1.awden = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDEN"); + state->u.f4.fld.cr1.res = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RES"); + state->u.f4.fld.cr1.ovrie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVRIE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.adon = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADON"); + state->u.f4.fld.cr2.cont = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CONT"); + state->u.f4.fld.cr2.dma = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DMA"); + state->u.f4.fld.cr2.dds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DDS"); + state->u.f4.fld.cr2.eocs = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EOCS"); + state->u.f4.fld.cr2.align = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ALIGN"); + state->u.f4.fld.cr2.jextsel = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JEXTSEL"); + state->u.f4.fld.cr2.jexten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JEXTEN"); + state->u.f4.fld.cr2.jswstart = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JSWSTART"); + state->u.f4.fld.cr2.extsel = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EXTSEL"); + state->u.f4.fld.cr2.exten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EXTEN"); + state->u.f4.fld.cr2.swstart = cm_object_get_child_by_name(state->u.f4.reg.cr2, "SWSTART"); + + // SMPR1 bitfields. + state->u.f4.fld.smpr1.smpx_x = cm_object_get_child_by_name(state->u.f4.reg.smpr1, "SMPx_x"); + + // SMPR2 bitfields. + state->u.f4.fld.smpr2.smpx_x = cm_object_get_child_by_name(state->u.f4.reg.smpr2, "SMPx_x"); + + // JOFR1 bitfields. + state->u.f4.fld.jofr1.joffset1 = cm_object_get_child_by_name(state->u.f4.reg.jofr1, "JOFFSET1"); + + // JOFR2 bitfields. + state->u.f4.fld.jofr2.joffset2 = cm_object_get_child_by_name(state->u.f4.reg.jofr2, "JOFFSET2"); + + // JOFR3 bitfields. + state->u.f4.fld.jofr3.joffset3 = cm_object_get_child_by_name(state->u.f4.reg.jofr3, "JOFFSET3"); + + // JOFR4 bitfields. + state->u.f4.fld.jofr4.joffset4 = cm_object_get_child_by_name(state->u.f4.reg.jofr4, "JOFFSET4"); + + // HTR bitfields. + state->u.f4.fld.htr.ht = cm_object_get_child_by_name(state->u.f4.reg.htr, "HT"); + + // LTR bitfields. + state->u.f4.fld.ltr.lt = cm_object_get_child_by_name(state->u.f4.reg.ltr, "LT"); + + // SQR1 bitfields. + state->u.f4.fld.sqr1.sq13 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ13"); + state->u.f4.fld.sqr1.sq14 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ14"); + state->u.f4.fld.sqr1.sq15 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ15"); + state->u.f4.fld.sqr1.sq16 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ16"); + state->u.f4.fld.sqr1.l = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "L"); + + // SQR2 bitfields. + state->u.f4.fld.sqr2.sq7 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ7"); + state->u.f4.fld.sqr2.sq8 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ8"); + state->u.f4.fld.sqr2.sq9 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ9"); + state->u.f4.fld.sqr2.sq10 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ10"); + state->u.f4.fld.sqr2.sq11 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ11"); + state->u.f4.fld.sqr2.sq12 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ12"); + + // SQR3 bitfields. + state->u.f4.fld.sqr3.sq1 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ1"); + state->u.f4.fld.sqr3.sq2 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ2"); + state->u.f4.fld.sqr3.sq3 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ3"); + state->u.f4.fld.sqr3.sq4 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ4"); + state->u.f4.fld.sqr3.sq5 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ5"); + state->u.f4.fld.sqr3.sq6 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ6"); + + // JSQR bitfields. + state->u.f4.fld.jsqr.jsq1 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ1"); + state->u.f4.fld.jsqr.jsq2 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ2"); + state->u.f4.fld.jsqr.jsq3 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ3"); + state->u.f4.fld.jsqr.jsq4 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ4"); + state->u.f4.fld.jsqr.jl = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JL"); + + // JDR1 bitfields. + state->u.f4.fld.jdr1.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr1, "JDATA"); + + // JDR2 bitfields. + state->u.f4.fld.jdr2.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr2, "JDATA"); + + // JDR3 bitfields. + state->u.f4.fld.jdr3.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr3, "JDATA"); + + // JDR4 bitfields. + state->u.f4.fld.jdr4.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr4, "JDATA"); + + // DR bitfields. + state->u.f4.fld.dr.data = cm_object_get_child_by_name(state->u.f4.reg.dr, "DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_ADC_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC%dEN", + 1 + state->port_index - STM32_PORT_ADC1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/adc1.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc1.h new file mode 100644 index 0000000000..38c035c4dc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc1.h @@ -0,0 +1,276 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_ADC1, + STM32_PORT_ADC_UNDEFINED = 0xFF, +} stm32_adc_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_adc_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 ADC (Analog-to-digital converter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *cr1; // 0x4 (Control register 1) + Object *cr2; // 0x8 (Control register 2) + Object *smpr1; // 0xC (Sample time register 1) + Object *smpr2; // 0x10 (Sample time register 2) + Object *jofr1; // 0x14 (Injected channel data offset register x) + Object *jofr2; // 0x18 (Injected channel data offset register x) + Object *jofr3; // 0x1C (Injected channel data offset register x) + Object *jofr4; // 0x20 (Injected channel data offset register x) + Object *htr; // 0x24 (Watchdog higher threshold register) + Object *ltr; // 0x28 (Watchdog lower threshold register) + Object *sqr1; // 0x2C (Regular sequence register 1) + Object *sqr2; // 0x30 (Regular sequence register 2) + Object *sqr3; // 0x34 (Regular sequence register 3) + Object *jsqr; // 0x38 (Injected sequence register) + Object *jdr1; // 0x3C (Injected data register x) + Object *jdr2; // 0x40 (Injected data register x) + Object *jdr3; // 0x44 (Injected data register x) + Object *jdr4; // 0x48 (Injected data register x) + Object *dr; // 0x4C (Regular data register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *awd; // [0:0] Analog watchdog flag + Object *eoc; // [1:1] Regular channel end of conversion + Object *jeoc; // [2:2] Injected channel end of conversion + Object *jstrt; // [3:3] Injected channel start flag + Object *strt; // [4:4] Regular channel start flag + Object *ovr; // [5:5] Overrun + } sr; + + // CR1 (Control register 1) bitfields. + struct { + Object *awdch; // [0:4] Analog watchdog channel select bits + Object *eocie; // [5:5] Interrupt enable for EOC + Object *awdie; // [6:6] Analog watchdog interrupt enable + Object *jeocie; // [7:7] Interrupt enable for injected channels + Object *scan; // [8:8] Scan mode + Object *awdsgl; // [9:9] Enable the watchdog on a single channel in scan mode + Object *jauto; // [10:10] Automatic injected group conversion + Object *discen; // [11:11] Discontinuous mode on regular channels + Object *jdiscen; // [12:12] Discontinuous mode on injected channels + Object *discnum; // [13:15] Discontinuous mode channel count + Object *jawden; // [22:22] Analog watchdog enable on injected channels + Object *awden; // [23:23] Analog watchdog enable on regular channels + Object *res; // [24:25] Resolution + Object *ovrie; // [26:26] Overrun interrupt enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *adon; // [0:0] A/D Converter ON / OFF + Object *cont; // [1:1] Continuous conversion + Object *dma; // [8:8] Direct memory access mode (for single ADC mode) + Object *dds; // [9:9] DMA disable selection (for single ADC mode) + Object *eocs; // [10:10] End of conversion selection + Object *align; // [11:11] Data alignment + Object *jextsel; // [16:19] External event select for injected group + Object *jexten; // [20:21] External trigger enable for injected channels + Object *jswstart; // [22:22] Start conversion of injected channels + Object *extsel; // [24:27] External event select for regular group + Object *exten; // [28:29] External trigger enable for regular channels + Object *swstart; // [30:30] Start conversion of regular channels + } cr2; + + // SMPR1 (Sample time register 1) bitfields. + struct { + Object *smpx_x; // [0:31] Sample time bits + } smpr1; + + // SMPR2 (Sample time register 2) bitfields. + struct { + Object *smpx_x; // [0:31] Sample time bits + } smpr2; + + // JOFR1 (Injected channel data offset register x) bitfields. + struct { + Object *joffset1; // [0:11] Data offset for injected channel x + } jofr1; + + // JOFR2 (Injected channel data offset register x) bitfields. + struct { + Object *joffset2; // [0:11] Data offset for injected channel x + } jofr2; + + // JOFR3 (Injected channel data offset register x) bitfields. + struct { + Object *joffset3; // [0:11] Data offset for injected channel x + } jofr3; + + // JOFR4 (Injected channel data offset register x) bitfields. + struct { + Object *joffset4; // [0:11] Data offset for injected channel x + } jofr4; + + // HTR (Watchdog higher threshold register) bitfields. + struct { + Object *ht; // [0:11] Analog watchdog higher threshold + } htr; + + // LTR (Watchdog lower threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + } ltr; + + // SQR1 (Regular sequence register 1) bitfields. + struct { + Object *sq13; // [0:4] 13th conversion in regular sequence + Object *sq14; // [5:9] 14th conversion in regular sequence + Object *sq15; // [10:14] 15th conversion in regular sequence + Object *sq16; // [15:19] 16th conversion in regular sequence + Object *l; // [20:23] Regular channel sequence length + } sqr1; + + // SQR2 (Regular sequence register 2) bitfields. + struct { + Object *sq7; // [0:4] 7th conversion in regular sequence + Object *sq8; // [5:9] 8th conversion in regular sequence + Object *sq9; // [10:14] 9th conversion in regular sequence + Object *sq10; // [15:19] 10th conversion in regular sequence + Object *sq11; // [20:24] 11th conversion in regular sequence + Object *sq12; // [25:29] 12th conversion in regular sequence + } sqr2; + + // SQR3 (Regular sequence register 3) bitfields. + struct { + Object *sq1; // [0:4] 1st conversion in regular sequence + Object *sq2; // [5:9] 2nd conversion in regular sequence + Object *sq3; // [10:14] 3rd conversion in regular sequence + Object *sq4; // [15:19] 4th conversion in regular sequence + Object *sq5; // [20:24] 5th conversion in regular sequence + Object *sq6; // [25:29] 6th conversion in regular sequence + } sqr3; + + // JSQR (Injected sequence register) bitfields. + struct { + Object *jsq1; // [0:4] 1st conversion in injected sequence + Object *jsq2; // [5:9] 2nd conversion in injected sequence + Object *jsq3; // [10:14] 3rd conversion in injected sequence + Object *jsq4; // [15:19] 4th conversion in injected sequence + Object *jl; // [20:21] Injected sequence length + } jsqr; + + // JDR1 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr1; + + // JDR2 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr2; + + // JDR3 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr3; + + // JDR4 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr4; + + // DR (Regular data register) bitfields. + struct { + Object *data; // [0:15] Regular data + } dr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/adc_common.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc_common.c new file mode 100644 index 0000000000..25a6d06de0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc_common.c @@ -0,0 +1,264 @@ +/* + * STM32 - ADC_Common (ADC common registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_adc_common_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f4.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + + + // CSR bitfields. + state->u.f4.fld.csr.awd1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD1"); + state->u.f4.fld.csr.eoc1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC1"); + state->u.f4.fld.csr.jeoc1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC1"); + state->u.f4.fld.csr.jstrt1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT1"); + state->u.f4.fld.csr.strt1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT1"); + state->u.f4.fld.csr.ovr1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR1"); + state->u.f4.fld.csr.awd2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD2"); + state->u.f4.fld.csr.eoc2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC2"); + state->u.f4.fld.csr.jeoc2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC2"); + state->u.f4.fld.csr.jstrt2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT2"); + state->u.f4.fld.csr.strt2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT2"); + state->u.f4.fld.csr.ovr2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR2"); + state->u.f4.fld.csr.awd3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD3"); + state->u.f4.fld.csr.eoc3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC3"); + state->u.f4.fld.csr.jeoc3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC3"); + state->u.f4.fld.csr.jstrt3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT3"); + state->u.f4.fld.csr.strt3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT3"); + state->u.f4.fld.csr.ovr3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR3"); + + // CCR bitfields. + state->u.f4.fld.ccr.delay = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DELAY"); + state->u.f4.fld.ccr.dds = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DDS"); + state->u.f4.fld.ccr.dma = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DMA"); + state->u.f4.fld.ccr.adcpre = cm_object_get_child_by_name(state->u.f4.reg.ccr, "ADCPRE"); + state->u.f4.fld.ccr.vbate = cm_object_get_child_by_name(state->u.f4.reg.ccr, "VBATE"); + state->u.f4.fld.ccr.tsvrefe = cm_object_get_child_by_name(state->u.f4.reg.ccr, "TSVREFE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_common_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_common_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_common_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_common_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_common_is_enabled(Object *obj) +{ + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_common_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_common_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC_Common)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADC_CommonState *state = STM32_ADC_Common_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC_Common"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_adc_common_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_common_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_adc_common_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_common_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_adc_common_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC_CommonEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_common_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC_Common); +} + +static void stm32_adc_common_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_common_reset_callback; + dc->realize = stm32_adc_common_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_common_is_enabled; +} + +static const TypeInfo stm32_adc_common_type_info = { + .name = TYPE_STM32_ADC_Common, + .parent = TYPE_STM32_ADC_Common_PARENT, + .instance_init = stm32_adc_common_instance_init_callback, + .instance_size = sizeof(STM32ADC_CommonState), + .class_init = stm32_adc_common_class_init_callback, + .class_size = sizeof(STM32ADC_CommonClass) }; + +static void stm32_adc_common_register_types(void) +{ + type_register_static(&stm32_adc_common_type_info); +} + +type_init(stm32_adc_common_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/adc_common.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc_common.h new file mode 100644 index 0000000000..c4aa749a01 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/adc_common.h @@ -0,0 +1,133 @@ +/* + * STM32 - ADC_Common (ADC common registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_Common_H_ +#define STM32_ADC_Common_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC_Common DEVICE_PATH_STM32 "ADC_Common" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC_Common TYPE_STM32_PREFIX "adc_common" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_Common_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADC_CommonParentClass; +typedef PeripheralState STM32ADC_CommonParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_Common_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADC_CommonClass, (obj), TYPE_STM32_ADC_Common) +#define STM32_ADC_Common_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADC_CommonClass, (klass), TYPE_STM32_ADC_Common) + +typedef struct { + // private: + STM32ADC_CommonParentClass parent_class; + // public: + + // None, so far. +} STM32ADC_CommonClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_Common_STATE(obj) \ + OBJECT_CHECK(STM32ADC_CommonState, (obj), TYPE_STM32_ADC_Common) + +typedef struct { + // private: + STM32ADC_CommonParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 ADC_Common (ADC common registers) registers. + struct { + Object *csr; // 0x0 (ADC Common status register) + Object *ccr; // 0x4 (ADC common control register) + } reg; + + struct { + + // CSR (ADC Common status register) bitfields. + struct { + Object *awd1; // [0:0] Analog watchdog flag of ADC 1 + Object *eoc1; // [1:1] End of conversion of ADC 1 + Object *jeoc1; // [2:2] Injected channel end of conversion of ADC 1 + Object *jstrt1; // [3:3] Injected channel Start flag of ADC 1 + Object *strt1; // [4:4] Regular channel Start flag of ADC 1 + Object *ovr1; // [5:5] Overrun flag of ADC 1 + Object *awd2; // [8:8] Analog watchdog flag of ADC 2 + Object *eoc2; // [9:9] End of conversion of ADC 2 + Object *jeoc2; // [10:10] Injected channel end of conversion of ADC 2 + Object *jstrt2; // [11:11] Injected channel Start flag of ADC 2 + Object *strt2; // [12:12] Regular channel Start flag of ADC 2 + Object *ovr2; // [13:13] Overrun flag of ADC 2 + Object *awd3; // [16:16] Analog watchdog flag of ADC 3 + Object *eoc3; // [17:17] End of conversion of ADC 3 + Object *jeoc3; // [18:18] Injected channel end of conversion of ADC 3 + Object *jstrt3; // [19:19] Injected channel Start flag of ADC 3 + Object *strt3; // [20:20] Regular channel Start flag of ADC 3 + Object *ovr3; // [21:21] Overrun flag of ADC3 + } csr; + + // CCR (ADC common control register) bitfields. + struct { + Object *delay; // [8:11] Delay between 2 sampling phases + Object *dds; // [13:13] DMA disable selection for multi-ADC mode + Object *dma; // [14:15] Direct memory access mode for multi ADC mode + Object *adcpre; // [16:17] ADC prescaler + Object *vbate; // [22:22] VBAT enable + Object *tsvrefe; // [23:23] Temperature sensor and VREFINT enable + } ccr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADC_CommonState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_Common_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/crc.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/crc.c new file mode 100644 index 0000000000..5eac09b421 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/crc.c @@ -0,0 +1,246 @@ +/* + * STM32 - CRC (Cryptographic processor) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_crc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // IDR bitfields. + state->u.f4.fld.idr.idr = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR"); + + // CR bitfields. + state->u.f4.fld.cr.cr = cm_object_get_child_by_name(state->u.f4.reg.cr, "CR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crc_is_enabled(Object *obj) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRCState *state = STM32_CRC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRCState *state = STM32_CRC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_crc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_crc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_crc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_crc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_crc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRC); +} + +static void stm32_crc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crc_reset_callback; + dc->realize = stm32_crc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crc_is_enabled; +} + +static const TypeInfo stm32_crc_type_info = { + .name = TYPE_STM32_CRC, + .parent = TYPE_STM32_CRC_PARENT, + .instance_init = stm32_crc_instance_init_callback, + .instance_size = sizeof(STM32CRCState), + .class_init = stm32_crc_class_init_callback, + .class_size = sizeof(STM32CRCClass) }; + +static void stm32_crc_register_types(void) +{ + type_register_static(&stm32_crc_type_info); +} + +type_init(stm32_crc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/crc.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/crc.h new file mode 100644 index 0000000000..10e5fff9cc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/crc.h @@ -0,0 +1,117 @@ +/* + * STM32 - CRC (Cryptographic processor) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRC_H_ +#define STM32_CRC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRC DEVICE_PATH_STM32 "CRC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRC TYPE_STM32_PREFIX "crc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRCParentClass; +typedef PeripheralState STM32CRCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRCClass, (obj), TYPE_STM32_CRC) +#define STM32_CRC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRCClass, (klass), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentClass parent_class; + // public: + + // None, so far. +} STM32CRCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRC_STATE(obj) \ + OBJECT_CHECK(STM32CRCState, (obj), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 CRC (Cryptographic processor) registers. + struct { + Object *dr; // 0x0 (Data register) + Object *idr; // 0x4 (Independent Data register) + Object *cr; // 0x8 (Control register) + } reg; + + struct { + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:31] Data Register + } dr; + + // IDR (Independent Data register) bitfields. + struct { + Object *idr; // [0:7] Independent Data register + } idr; + + // CR (Control register) bitfields. + struct { + Object *cr; // [0:0] Control regidter + } cr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/dbg.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/dbg.c new file mode 100644 index 0000000000..127f74a2b1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/dbg.c @@ -0,0 +1,267 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_dbg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dbgmcu_idcode = cm_object_get_child_by_name(obj, "DBGMCU_IDCODE"); + state->u.f4.reg.dbgmcu_cr = cm_object_get_child_by_name(obj, "DBGMCU_CR"); + state->u.f4.reg.dbgmcu_apb1_fz = cm_object_get_child_by_name(obj, "DBGMCU_APB1_FZ"); + state->u.f4.reg.dbgmcu_apb2_fz = cm_object_get_child_by_name(obj, "DBGMCU_APB2_FZ"); + + + // DBGMCU_IDCODE bitfields. + state->u.f4.fld.dbgmcu_idcode.dev_id = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_idcode, "DEV_ID"); + state->u.f4.fld.dbgmcu_idcode.rev_id = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_idcode, "REV_ID"); + + // DBGMCU_CR bitfields. + state->u.f4.fld.dbgmcu_cr.dbg_sleep = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_SLEEP"); + state->u.f4.fld.dbgmcu_cr.dbg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_STOP"); + state->u.f4.fld.dbgmcu_cr.dbg_standby = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_STANDBY"); + state->u.f4.fld.dbgmcu_cr.trace_ioen = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "TRACE_IOEN"); + state->u.f4.fld.dbgmcu_cr.trace_mode = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "TRACE_MODE"); + + // DBGMCU_APB1_FZ bitfields. + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim2_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM2_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim3_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM3_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim4_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM4_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim5_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM5_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_rtc_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_RTC_Stop"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_wwdg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_WWDG_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_iwdeg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_IWDEG_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_i2c1_smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_I2C1_SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_i2c2_smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_I2C2_SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_i2c3smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_I2C3SMBUS_TIMEOUT"); + + // DBGMCU_APB2_FZ bitfields. + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim1_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM1_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim9_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM9_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim10_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM10_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim11_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM11_STOP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dbg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dbg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dbg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dbg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dbg_is_enabled(Object *obj) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dbg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DBGState *state = STM32_DBG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dbg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DBG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DBGState *state = STM32_DBG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DBG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_dbg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dbg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dbg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dbg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dbg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DBGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dbg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DBG); +} + +static void stm32_dbg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dbg_reset_callback; + dc->realize = stm32_dbg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dbg_is_enabled; +} + +static const TypeInfo stm32_dbg_type_info = { + .name = TYPE_STM32_DBG, + .parent = TYPE_STM32_DBG_PARENT, + .instance_init = stm32_dbg_instance_init_callback, + .instance_size = sizeof(STM32DBGState), + .class_init = stm32_dbg_class_init_callback, + .class_size = sizeof(STM32DBGClass) }; + +static void stm32_dbg_register_types(void) +{ + type_register_static(&stm32_dbg_type_info); +} + +type_init(stm32_dbg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/dbg.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/dbg.h new file mode 100644 index 0000000000..2d6b7b0f31 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/dbg.h @@ -0,0 +1,140 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DBG_H_ +#define STM32_DBG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DBG DEVICE_PATH_STM32 "DBG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DBG TYPE_STM32_PREFIX "dbg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DBG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DBGParentClass; +typedef PeripheralState STM32DBGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DBG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DBGClass, (obj), TYPE_STM32_DBG) +#define STM32_DBG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DBGClass, (klass), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentClass parent_class; + // public: + + // None, so far. +} STM32DBGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DBG_STATE(obj) \ + OBJECT_CHECK(STM32DBGState, (obj), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DBG (Debug support) registers. + struct { + Object *dbgmcu_idcode; // 0x0 (IDCODE) + Object *dbgmcu_cr; // 0x4 (Control Register) + Object *dbgmcu_apb1_fz; // 0x8 (Debug MCU APB1 Freeze registe) + Object *dbgmcu_apb2_fz; // 0xC (Debug MCU APB2 Freeze registe) + } reg; + + struct { + + // DBGMCU_IDCODE (IDCODE) bitfields. + struct { + Object *dev_id; // [0:11] DEV_ID + Object *rev_id; // [16:31] REV_ID + } dbgmcu_idcode; + + // DBGMCU_CR (Control Register) bitfields. + struct { + Object *dbg_sleep; // [0:0] DBG_SLEEP + Object *dbg_stop; // [1:1] DBG_STOP + Object *dbg_standby; // [2:2] DBG_STANDBY + Object *trace_ioen; // [5:5] TRACE_IOEN + Object *trace_mode; // [6:7] TRACE_MODE + } dbgmcu_cr; + + // DBGMCU_APB1_FZ (Debug MCU APB1 Freeze registe) bitfields. + struct { + Object *dbg_tim2_stop; // [0:0] DBG_TIM2_STOP + Object *dbg_tim3_stop; // [1:1] DBG_TIM3 _STOP + Object *dbg_tim4_stop; // [2:2] DBG_TIM4_STOP + Object *dbg_tim5_stop; // [3:3] DBG_TIM5_STOP + Object *dbg_rtc_stop; // [10:10] RTC stopped when Core is halted + Object *dbg_wwdg_stop; // [11:11] DBG_WWDG_STOP + Object *dbg_iwdeg_stop; // [12:12] DBG_IWDEG_STOP + Object *dbg_i2c1_smbus_timeout; // [21:21] DBG_J2C1_SMBUS_TIMEOUT + Object *dbg_i2c2_smbus_timeout; // [22:22] DBG_J2C2_SMBUS_TIMEOUT + Object *dbg_i2c3smbus_timeout; // [23:23] DBG_J2C3SMBUS_TIMEOUT + } dbgmcu_apb1_fz; + + // DBGMCU_APB2_FZ (Debug MCU APB2 Freeze registe) bitfields. + struct { + Object *dbg_tim1_stop; // [0:0] TIM1 counter stopped when core is halted + Object *dbg_tim9_stop; // [16:16] TIM9 counter stopped when core is halted + Object *dbg_tim10_stop; // [17:17] TIM10 counter stopped when core is halted + Object *dbg_tim11_stop; // [18:18] TIM11 counter stopped when core is halted + } dbgmcu_apb2_fz; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DBGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DBG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/dma2.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/dma2.c new file mode 100644 index 0000000000..290e49b07b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/dma2.c @@ -0,0 +1,698 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.lisr = cm_object_get_child_by_name(obj, "LISR"); + state->u.f4.reg.hisr = cm_object_get_child_by_name(obj, "HISR"); + state->u.f4.reg.lifcr = cm_object_get_child_by_name(obj, "LIFCR"); + state->u.f4.reg.hifcr = cm_object_get_child_by_name(obj, "HIFCR"); + state->u.f4.reg.s0cr = cm_object_get_child_by_name(obj, "S0CR"); + state->u.f4.reg.s0ndtr = cm_object_get_child_by_name(obj, "S0NDTR"); + state->u.f4.reg.s0par = cm_object_get_child_by_name(obj, "S0PAR"); + state->u.f4.reg.s0m0ar = cm_object_get_child_by_name(obj, "S0M0AR"); + state->u.f4.reg.s0m1ar = cm_object_get_child_by_name(obj, "S0M1AR"); + state->u.f4.reg.s0fcr = cm_object_get_child_by_name(obj, "S0FCR"); + state->u.f4.reg.s1cr = cm_object_get_child_by_name(obj, "S1CR"); + state->u.f4.reg.s1ndtr = cm_object_get_child_by_name(obj, "S1NDTR"); + state->u.f4.reg.s1par = cm_object_get_child_by_name(obj, "S1PAR"); + state->u.f4.reg.s1m0ar = cm_object_get_child_by_name(obj, "S1M0AR"); + state->u.f4.reg.s1m1ar = cm_object_get_child_by_name(obj, "S1M1AR"); + state->u.f4.reg.s1fcr = cm_object_get_child_by_name(obj, "S1FCR"); + state->u.f4.reg.s2cr = cm_object_get_child_by_name(obj, "S2CR"); + state->u.f4.reg.s2ndtr = cm_object_get_child_by_name(obj, "S2NDTR"); + state->u.f4.reg.s2par = cm_object_get_child_by_name(obj, "S2PAR"); + state->u.f4.reg.s2m0ar = cm_object_get_child_by_name(obj, "S2M0AR"); + state->u.f4.reg.s2m1ar = cm_object_get_child_by_name(obj, "S2M1AR"); + state->u.f4.reg.s2fcr = cm_object_get_child_by_name(obj, "S2FCR"); + state->u.f4.reg.s3cr = cm_object_get_child_by_name(obj, "S3CR"); + state->u.f4.reg.s3ndtr = cm_object_get_child_by_name(obj, "S3NDTR"); + state->u.f4.reg.s3par = cm_object_get_child_by_name(obj, "S3PAR"); + state->u.f4.reg.s3m0ar = cm_object_get_child_by_name(obj, "S3M0AR"); + state->u.f4.reg.s3m1ar = cm_object_get_child_by_name(obj, "S3M1AR"); + state->u.f4.reg.s3fcr = cm_object_get_child_by_name(obj, "S3FCR"); + state->u.f4.reg.s4cr = cm_object_get_child_by_name(obj, "S4CR"); + state->u.f4.reg.s4ndtr = cm_object_get_child_by_name(obj, "S4NDTR"); + state->u.f4.reg.s4par = cm_object_get_child_by_name(obj, "S4PAR"); + state->u.f4.reg.s4m0ar = cm_object_get_child_by_name(obj, "S4M0AR"); + state->u.f4.reg.s4m1ar = cm_object_get_child_by_name(obj, "S4M1AR"); + state->u.f4.reg.s4fcr = cm_object_get_child_by_name(obj, "S4FCR"); + state->u.f4.reg.s5cr = cm_object_get_child_by_name(obj, "S5CR"); + state->u.f4.reg.s5ndtr = cm_object_get_child_by_name(obj, "S5NDTR"); + state->u.f4.reg.s5par = cm_object_get_child_by_name(obj, "S5PAR"); + state->u.f4.reg.s5m0ar = cm_object_get_child_by_name(obj, "S5M0AR"); + state->u.f4.reg.s5m1ar = cm_object_get_child_by_name(obj, "S5M1AR"); + state->u.f4.reg.s5fcr = cm_object_get_child_by_name(obj, "S5FCR"); + state->u.f4.reg.s6cr = cm_object_get_child_by_name(obj, "S6CR"); + state->u.f4.reg.s6ndtr = cm_object_get_child_by_name(obj, "S6NDTR"); + state->u.f4.reg.s6par = cm_object_get_child_by_name(obj, "S6PAR"); + state->u.f4.reg.s6m0ar = cm_object_get_child_by_name(obj, "S6M0AR"); + state->u.f4.reg.s6m1ar = cm_object_get_child_by_name(obj, "S6M1AR"); + state->u.f4.reg.s6fcr = cm_object_get_child_by_name(obj, "S6FCR"); + state->u.f4.reg.s7cr = cm_object_get_child_by_name(obj, "S7CR"); + state->u.f4.reg.s7ndtr = cm_object_get_child_by_name(obj, "S7NDTR"); + state->u.f4.reg.s7par = cm_object_get_child_by_name(obj, "S7PAR"); + state->u.f4.reg.s7m0ar = cm_object_get_child_by_name(obj, "S7M0AR"); + state->u.f4.reg.s7m1ar = cm_object_get_child_by_name(obj, "S7M1AR"); + state->u.f4.reg.s7fcr = cm_object_get_child_by_name(obj, "S7FCR"); + + + // LISR bitfields. + state->u.f4.fld.lisr.feif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF0"); + state->u.f4.fld.lisr.dmeif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF0"); + state->u.f4.fld.lisr.teif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF0"); + state->u.f4.fld.lisr.htif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF0"); + state->u.f4.fld.lisr.tcif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF0"); + state->u.f4.fld.lisr.feif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF1"); + state->u.f4.fld.lisr.dmeif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF1"); + state->u.f4.fld.lisr.teif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF1"); + state->u.f4.fld.lisr.htif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF1"); + state->u.f4.fld.lisr.tcif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF1"); + state->u.f4.fld.lisr.feif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF2"); + state->u.f4.fld.lisr.dmeif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF2"); + state->u.f4.fld.lisr.teif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF2"); + state->u.f4.fld.lisr.htif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF2"); + state->u.f4.fld.lisr.tcif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF2"); + state->u.f4.fld.lisr.feif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF3"); + state->u.f4.fld.lisr.dmeif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF3"); + state->u.f4.fld.lisr.teif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF3"); + state->u.f4.fld.lisr.htif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF3"); + state->u.f4.fld.lisr.tcif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF3"); + + // HISR bitfields. + state->u.f4.fld.hisr.feif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF4"); + state->u.f4.fld.hisr.dmeif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF4"); + state->u.f4.fld.hisr.teif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF4"); + state->u.f4.fld.hisr.htif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF4"); + state->u.f4.fld.hisr.tcif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF4"); + state->u.f4.fld.hisr.feif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF5"); + state->u.f4.fld.hisr.dmeif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF5"); + state->u.f4.fld.hisr.teif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF5"); + state->u.f4.fld.hisr.htif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF5"); + state->u.f4.fld.hisr.tcif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF5"); + state->u.f4.fld.hisr.feif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF6"); + state->u.f4.fld.hisr.dmeif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF6"); + state->u.f4.fld.hisr.teif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF6"); + state->u.f4.fld.hisr.htif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF6"); + state->u.f4.fld.hisr.tcif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF6"); + state->u.f4.fld.hisr.feif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF7"); + state->u.f4.fld.hisr.dmeif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF7"); + state->u.f4.fld.hisr.teif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF7"); + state->u.f4.fld.hisr.htif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF7"); + state->u.f4.fld.hisr.tcif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF7"); + + // LIFCR bitfields. + state->u.f4.fld.lifcr.cfeif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF0"); + state->u.f4.fld.lifcr.cdmeif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF0"); + state->u.f4.fld.lifcr.cteif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF0"); + state->u.f4.fld.lifcr.chtif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF0"); + state->u.f4.fld.lifcr.ctcif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF0"); + state->u.f4.fld.lifcr.cfeif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF1"); + state->u.f4.fld.lifcr.cdmeif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF1"); + state->u.f4.fld.lifcr.cteif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF1"); + state->u.f4.fld.lifcr.chtif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF1"); + state->u.f4.fld.lifcr.ctcif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF1"); + state->u.f4.fld.lifcr.cfeif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF2"); + state->u.f4.fld.lifcr.cdmeif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF2"); + state->u.f4.fld.lifcr.cteif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF2"); + state->u.f4.fld.lifcr.chtif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF2"); + state->u.f4.fld.lifcr.ctcif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF2"); + state->u.f4.fld.lifcr.cfeif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF3"); + state->u.f4.fld.lifcr.cdmeif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF3"); + state->u.f4.fld.lifcr.cteif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF3"); + state->u.f4.fld.lifcr.chtif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF3"); + state->u.f4.fld.lifcr.ctcif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF3"); + + // HIFCR bitfields. + state->u.f4.fld.hifcr.cfeif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF4"); + state->u.f4.fld.hifcr.cdmeif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF4"); + state->u.f4.fld.hifcr.cteif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF4"); + state->u.f4.fld.hifcr.chtif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF4"); + state->u.f4.fld.hifcr.ctcif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF4"); + state->u.f4.fld.hifcr.cfeif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF5"); + state->u.f4.fld.hifcr.cdmeif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF5"); + state->u.f4.fld.hifcr.cteif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF5"); + state->u.f4.fld.hifcr.chtif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF5"); + state->u.f4.fld.hifcr.ctcif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF5"); + state->u.f4.fld.hifcr.cfeif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF6"); + state->u.f4.fld.hifcr.cdmeif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF6"); + state->u.f4.fld.hifcr.cteif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF6"); + state->u.f4.fld.hifcr.chtif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF6"); + state->u.f4.fld.hifcr.ctcif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF6"); + state->u.f4.fld.hifcr.cfeif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF7"); + state->u.f4.fld.hifcr.cdmeif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF7"); + state->u.f4.fld.hifcr.cteif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF7"); + state->u.f4.fld.hifcr.chtif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF7"); + state->u.f4.fld.hifcr.ctcif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF7"); + + // S0CR bitfields. + state->u.f4.fld.s0cr.en = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "EN"); + state->u.f4.fld.s0cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DMEIE"); + state->u.f4.fld.s0cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "TEIE"); + state->u.f4.fld.s0cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "HTIE"); + state->u.f4.fld.s0cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "TCIE"); + state->u.f4.fld.s0cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PFCTRL"); + state->u.f4.fld.s0cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DIR"); + state->u.f4.fld.s0cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CIRC"); + state->u.f4.fld.s0cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PINC"); + state->u.f4.fld.s0cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MINC"); + state->u.f4.fld.s0cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PSIZE"); + state->u.f4.fld.s0cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MSIZE"); + state->u.f4.fld.s0cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PINCOS"); + state->u.f4.fld.s0cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PL"); + state->u.f4.fld.s0cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DBM"); + state->u.f4.fld.s0cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CT"); + state->u.f4.fld.s0cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PBURST"); + state->u.f4.fld.s0cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MBURST"); + state->u.f4.fld.s0cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CHSEL"); + + // S0NDTR bitfields. + state->u.f4.fld.s0ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s0ndtr, "NDT"); + + // S0PAR bitfields. + state->u.f4.fld.s0par.pa = cm_object_get_child_by_name(state->u.f4.reg.s0par, "PA"); + + // S0M0AR bitfields. + state->u.f4.fld.s0m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s0m0ar, "M0A"); + + // S0M1AR bitfields. + state->u.f4.fld.s0m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s0m1ar, "M1A"); + + // S0FCR bitfields. + state->u.f4.fld.s0fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FTH"); + state->u.f4.fld.s0fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "DMDIS"); + state->u.f4.fld.s0fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FS"); + state->u.f4.fld.s0fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FEIE"); + + // S1CR bitfields. + state->u.f4.fld.s1cr.en = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "EN"); + state->u.f4.fld.s1cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DMEIE"); + state->u.f4.fld.s1cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "TEIE"); + state->u.f4.fld.s1cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "HTIE"); + state->u.f4.fld.s1cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "TCIE"); + state->u.f4.fld.s1cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PFCTRL"); + state->u.f4.fld.s1cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DIR"); + state->u.f4.fld.s1cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CIRC"); + state->u.f4.fld.s1cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PINC"); + state->u.f4.fld.s1cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MINC"); + state->u.f4.fld.s1cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PSIZE"); + state->u.f4.fld.s1cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MSIZE"); + state->u.f4.fld.s1cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PINCOS"); + state->u.f4.fld.s1cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PL"); + state->u.f4.fld.s1cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DBM"); + state->u.f4.fld.s1cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CT"); + state->u.f4.fld.s1cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "ACK"); + state->u.f4.fld.s1cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PBURST"); + state->u.f4.fld.s1cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MBURST"); + state->u.f4.fld.s1cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CHSEL"); + + // S1NDTR bitfields. + state->u.f4.fld.s1ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s1ndtr, "NDT"); + + // S1PAR bitfields. + state->u.f4.fld.s1par.pa = cm_object_get_child_by_name(state->u.f4.reg.s1par, "PA"); + + // S1M0AR bitfields. + state->u.f4.fld.s1m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s1m0ar, "M0A"); + + // S1M1AR bitfields. + state->u.f4.fld.s1m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s1m1ar, "M1A"); + + // S1FCR bitfields. + state->u.f4.fld.s1fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FTH"); + state->u.f4.fld.s1fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "DMDIS"); + state->u.f4.fld.s1fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FS"); + state->u.f4.fld.s1fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FEIE"); + + // S2CR bitfields. + state->u.f4.fld.s2cr.en = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "EN"); + state->u.f4.fld.s2cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DMEIE"); + state->u.f4.fld.s2cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "TEIE"); + state->u.f4.fld.s2cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "HTIE"); + state->u.f4.fld.s2cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "TCIE"); + state->u.f4.fld.s2cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PFCTRL"); + state->u.f4.fld.s2cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DIR"); + state->u.f4.fld.s2cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CIRC"); + state->u.f4.fld.s2cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PINC"); + state->u.f4.fld.s2cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MINC"); + state->u.f4.fld.s2cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PSIZE"); + state->u.f4.fld.s2cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MSIZE"); + state->u.f4.fld.s2cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PINCOS"); + state->u.f4.fld.s2cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PL"); + state->u.f4.fld.s2cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DBM"); + state->u.f4.fld.s2cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CT"); + state->u.f4.fld.s2cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "ACK"); + state->u.f4.fld.s2cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PBURST"); + state->u.f4.fld.s2cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MBURST"); + state->u.f4.fld.s2cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CHSEL"); + + // S2NDTR bitfields. + state->u.f4.fld.s2ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s2ndtr, "NDT"); + + // S2PAR bitfields. + state->u.f4.fld.s2par.pa = cm_object_get_child_by_name(state->u.f4.reg.s2par, "PA"); + + // S2M0AR bitfields. + state->u.f4.fld.s2m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s2m0ar, "M0A"); + + // S2M1AR bitfields. + state->u.f4.fld.s2m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s2m1ar, "M1A"); + + // S2FCR bitfields. + state->u.f4.fld.s2fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FTH"); + state->u.f4.fld.s2fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "DMDIS"); + state->u.f4.fld.s2fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FS"); + state->u.f4.fld.s2fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FEIE"); + + // S3CR bitfields. + state->u.f4.fld.s3cr.en = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "EN"); + state->u.f4.fld.s3cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DMEIE"); + state->u.f4.fld.s3cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "TEIE"); + state->u.f4.fld.s3cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "HTIE"); + state->u.f4.fld.s3cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "TCIE"); + state->u.f4.fld.s3cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PFCTRL"); + state->u.f4.fld.s3cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DIR"); + state->u.f4.fld.s3cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CIRC"); + state->u.f4.fld.s3cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PINC"); + state->u.f4.fld.s3cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MINC"); + state->u.f4.fld.s3cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PSIZE"); + state->u.f4.fld.s3cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MSIZE"); + state->u.f4.fld.s3cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PINCOS"); + state->u.f4.fld.s3cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PL"); + state->u.f4.fld.s3cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DBM"); + state->u.f4.fld.s3cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CT"); + state->u.f4.fld.s3cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "ACK"); + state->u.f4.fld.s3cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PBURST"); + state->u.f4.fld.s3cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MBURST"); + state->u.f4.fld.s3cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CHSEL"); + + // S3NDTR bitfields. + state->u.f4.fld.s3ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s3ndtr, "NDT"); + + // S3PAR bitfields. + state->u.f4.fld.s3par.pa = cm_object_get_child_by_name(state->u.f4.reg.s3par, "PA"); + + // S3M0AR bitfields. + state->u.f4.fld.s3m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s3m0ar, "M0A"); + + // S3M1AR bitfields. + state->u.f4.fld.s3m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s3m1ar, "M1A"); + + // S3FCR bitfields. + state->u.f4.fld.s3fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FTH"); + state->u.f4.fld.s3fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "DMDIS"); + state->u.f4.fld.s3fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FS"); + state->u.f4.fld.s3fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FEIE"); + + // S4CR bitfields. + state->u.f4.fld.s4cr.en = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "EN"); + state->u.f4.fld.s4cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DMEIE"); + state->u.f4.fld.s4cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "TEIE"); + state->u.f4.fld.s4cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "HTIE"); + state->u.f4.fld.s4cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "TCIE"); + state->u.f4.fld.s4cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PFCTRL"); + state->u.f4.fld.s4cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DIR"); + state->u.f4.fld.s4cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CIRC"); + state->u.f4.fld.s4cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PINC"); + state->u.f4.fld.s4cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MINC"); + state->u.f4.fld.s4cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PSIZE"); + state->u.f4.fld.s4cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MSIZE"); + state->u.f4.fld.s4cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PINCOS"); + state->u.f4.fld.s4cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PL"); + state->u.f4.fld.s4cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DBM"); + state->u.f4.fld.s4cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CT"); + state->u.f4.fld.s4cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "ACK"); + state->u.f4.fld.s4cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PBURST"); + state->u.f4.fld.s4cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MBURST"); + state->u.f4.fld.s4cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CHSEL"); + + // S4NDTR bitfields. + state->u.f4.fld.s4ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s4ndtr, "NDT"); + + // S4PAR bitfields. + state->u.f4.fld.s4par.pa = cm_object_get_child_by_name(state->u.f4.reg.s4par, "PA"); + + // S4M0AR bitfields. + state->u.f4.fld.s4m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s4m0ar, "M0A"); + + // S4M1AR bitfields. + state->u.f4.fld.s4m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s4m1ar, "M1A"); + + // S4FCR bitfields. + state->u.f4.fld.s4fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FTH"); + state->u.f4.fld.s4fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "DMDIS"); + state->u.f4.fld.s4fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FS"); + state->u.f4.fld.s4fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FEIE"); + + // S5CR bitfields. + state->u.f4.fld.s5cr.en = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "EN"); + state->u.f4.fld.s5cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DMEIE"); + state->u.f4.fld.s5cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "TEIE"); + state->u.f4.fld.s5cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "HTIE"); + state->u.f4.fld.s5cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "TCIE"); + state->u.f4.fld.s5cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PFCTRL"); + state->u.f4.fld.s5cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DIR"); + state->u.f4.fld.s5cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CIRC"); + state->u.f4.fld.s5cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PINC"); + state->u.f4.fld.s5cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MINC"); + state->u.f4.fld.s5cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PSIZE"); + state->u.f4.fld.s5cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MSIZE"); + state->u.f4.fld.s5cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PINCOS"); + state->u.f4.fld.s5cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PL"); + state->u.f4.fld.s5cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DBM"); + state->u.f4.fld.s5cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CT"); + state->u.f4.fld.s5cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "ACK"); + state->u.f4.fld.s5cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PBURST"); + state->u.f4.fld.s5cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MBURST"); + state->u.f4.fld.s5cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CHSEL"); + + // S5NDTR bitfields. + state->u.f4.fld.s5ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s5ndtr, "NDT"); + + // S5PAR bitfields. + state->u.f4.fld.s5par.pa = cm_object_get_child_by_name(state->u.f4.reg.s5par, "PA"); + + // S5M0AR bitfields. + state->u.f4.fld.s5m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s5m0ar, "M0A"); + + // S5M1AR bitfields. + state->u.f4.fld.s5m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s5m1ar, "M1A"); + + // S5FCR bitfields. + state->u.f4.fld.s5fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FTH"); + state->u.f4.fld.s5fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "DMDIS"); + state->u.f4.fld.s5fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FS"); + state->u.f4.fld.s5fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FEIE"); + + // S6CR bitfields. + state->u.f4.fld.s6cr.en = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "EN"); + state->u.f4.fld.s6cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DMEIE"); + state->u.f4.fld.s6cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "TEIE"); + state->u.f4.fld.s6cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "HTIE"); + state->u.f4.fld.s6cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "TCIE"); + state->u.f4.fld.s6cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PFCTRL"); + state->u.f4.fld.s6cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DIR"); + state->u.f4.fld.s6cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CIRC"); + state->u.f4.fld.s6cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PINC"); + state->u.f4.fld.s6cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MINC"); + state->u.f4.fld.s6cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PSIZE"); + state->u.f4.fld.s6cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MSIZE"); + state->u.f4.fld.s6cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PINCOS"); + state->u.f4.fld.s6cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PL"); + state->u.f4.fld.s6cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DBM"); + state->u.f4.fld.s6cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CT"); + state->u.f4.fld.s6cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "ACK"); + state->u.f4.fld.s6cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PBURST"); + state->u.f4.fld.s6cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MBURST"); + state->u.f4.fld.s6cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CHSEL"); + + // S6NDTR bitfields. + state->u.f4.fld.s6ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s6ndtr, "NDT"); + + // S6PAR bitfields. + state->u.f4.fld.s6par.pa = cm_object_get_child_by_name(state->u.f4.reg.s6par, "PA"); + + // S6M0AR bitfields. + state->u.f4.fld.s6m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s6m0ar, "M0A"); + + // S6M1AR bitfields. + state->u.f4.fld.s6m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s6m1ar, "M1A"); + + // S6FCR bitfields. + state->u.f4.fld.s6fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FTH"); + state->u.f4.fld.s6fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "DMDIS"); + state->u.f4.fld.s6fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FS"); + state->u.f4.fld.s6fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FEIE"); + + // S7CR bitfields. + state->u.f4.fld.s7cr.en = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "EN"); + state->u.f4.fld.s7cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DMEIE"); + state->u.f4.fld.s7cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "TEIE"); + state->u.f4.fld.s7cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "HTIE"); + state->u.f4.fld.s7cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "TCIE"); + state->u.f4.fld.s7cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PFCTRL"); + state->u.f4.fld.s7cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DIR"); + state->u.f4.fld.s7cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CIRC"); + state->u.f4.fld.s7cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PINC"); + state->u.f4.fld.s7cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MINC"); + state->u.f4.fld.s7cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PSIZE"); + state->u.f4.fld.s7cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MSIZE"); + state->u.f4.fld.s7cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PINCOS"); + state->u.f4.fld.s7cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PL"); + state->u.f4.fld.s7cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DBM"); + state->u.f4.fld.s7cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CT"); + state->u.f4.fld.s7cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "ACK"); + state->u.f4.fld.s7cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PBURST"); + state->u.f4.fld.s7cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MBURST"); + state->u.f4.fld.s7cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CHSEL"); + + // S7NDTR bitfields. + state->u.f4.fld.s7ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s7ndtr, "NDT"); + + // S7PAR bitfields. + state->u.f4.fld.s7par.pa = cm_object_get_child_by_name(state->u.f4.reg.s7par, "PA"); + + // S7M0AR bitfields. + state->u.f4.fld.s7m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s7m0ar, "M0A"); + + // S7M1AR bitfields. + state->u.f4.fld.s7m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s7m1ar, "M1A"); + + // S7FCR bitfields. + state->u.f4.fld.s7fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FTH"); + state->u.f4.fld.s7fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "DMDIS"); + state->u.f4.fld.s7fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FS"); + state->u.f4.fld.s7fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FEIE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma_is_enabled(Object *obj) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMAState *state = STM32_DMA_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_DMA_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMAState *state = STM32_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA%dEN", + 1 + state->port_index - STM32_PORT_DMA1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA); +} + +static void stm32_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma_reset_callback; + dc->realize = stm32_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma_is_enabled; +} + +static const TypeInfo stm32_dma_type_info = { + .name = TYPE_STM32_DMA, + .parent = TYPE_STM32_DMA_PARENT, + .instance_init = stm32_dma_instance_init_callback, + .instance_size = sizeof(STM32DMAState), + .class_init = stm32_dma_class_init_callback, + .class_size = sizeof(STM32DMAClass) }; + +static void stm32_dma_register_types(void) +{ + type_register_static(&stm32_dma_type_info); +} + +type_init(stm32_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/dma2.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/dma2.h new file mode 100644 index 0000000000..b8356b45c9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/dma2.h @@ -0,0 +1,673 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA_H_ +#define STM32_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMA DEVICE_PATH_STM32 "DMA" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_DMA1, + STM32_PORT_DMA2, + STM32_PORT_DMA_UNDEFINED = 0xFF, +} stm32_dma_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMA TYPE_STM32_PREFIX "dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMAParentClass; +typedef PeripheralState STM32DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMAClass, (obj), TYPE_STM32_DMA) +#define STM32_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMAClass, (klass), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentClass parent_class; + // public: + + // None, so far. +} STM32DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA_STATE(obj) \ + OBJECT_CHECK(STM32DMAState, (obj), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_dma_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DMA (DMA controller) registers. + struct { + Object *lisr; // 0x0 (Low interrupt status register) + Object *hisr; // 0x4 (High interrupt status register) + Object *lifcr; // 0x8 (Low interrupt flag clear register) + Object *hifcr; // 0xC (High interrupt flag clear register) + Object *s0cr; // 0x10 (Stream x configuration register) + Object *s0ndtr; // 0x14 (Stream x number of data register) + Object *s0par; // 0x18 (Stream x peripheral address register) + Object *s0m0ar; // 0x1C (Stream x memory 0 address register) + Object *s0m1ar; // 0x20 (Stream x memory 1 address register) + Object *s0fcr; // 0x24 (Stream x FIFO control register) + Object *s1cr; // 0x28 (Stream x configuration register) + Object *s1ndtr; // 0x2C (Stream x number of data register) + Object *s1par; // 0x30 (Stream x peripheral address register) + Object *s1m0ar; // 0x34 (Stream x memory 0 address register) + Object *s1m1ar; // 0x38 (Stream x memory 1 address register) + Object *s1fcr; // 0x3C (Stream x FIFO control register) + Object *s2cr; // 0x40 (Stream x configuration register) + Object *s2ndtr; // 0x44 (Stream x number of data register) + Object *s2par; // 0x48 (Stream x peripheral address register) + Object *s2m0ar; // 0x4C (Stream x memory 0 address register) + Object *s2m1ar; // 0x50 (Stream x memory 1 address register) + Object *s2fcr; // 0x54 (Stream x FIFO control register) + Object *s3cr; // 0x58 (Stream x configuration register) + Object *s3ndtr; // 0x5C (Stream x number of data register) + Object *s3par; // 0x60 (Stream x peripheral address register) + Object *s3m0ar; // 0x64 (Stream x memory 0 address register) + Object *s3m1ar; // 0x68 (Stream x memory 1 address register) + Object *s3fcr; // 0x6C (Stream x FIFO control register) + Object *s4cr; // 0x70 (Stream x configuration register) + Object *s4ndtr; // 0x74 (Stream x number of data register) + Object *s4par; // 0x78 (Stream x peripheral address register) + Object *s4m0ar; // 0x7C (Stream x memory 0 address register) + Object *s4m1ar; // 0x80 (Stream x memory 1 address register) + Object *s4fcr; // 0x84 (Stream x FIFO control register) + Object *s5cr; // 0x88 (Stream x configuration register) + Object *s5ndtr; // 0x8C (Stream x number of data register) + Object *s5par; // 0x90 (Stream x peripheral address register) + Object *s5m0ar; // 0x94 (Stream x memory 0 address register) + Object *s5m1ar; // 0x98 (Stream x memory 1 address register) + Object *s5fcr; // 0x9C (Stream x FIFO control register) + Object *s6cr; // 0xA0 (Stream x configuration register) + Object *s6ndtr; // 0xA4 (Stream x number of data register) + Object *s6par; // 0xA8 (Stream x peripheral address register) + Object *s6m0ar; // 0xAC (Stream x memory 0 address register) + Object *s6m1ar; // 0xB0 (Stream x memory 1 address register) + Object *s6fcr; // 0xB4 (Stream x FIFO control register) + Object *s7cr; // 0xB8 (Stream x configuration register) + Object *s7ndtr; // 0xBC (Stream x number of data register) + Object *s7par; // 0xC0 (Stream x peripheral address register) + Object *s7m0ar; // 0xC4 (Stream x memory 0 address register) + Object *s7m1ar; // 0xC8 (Stream x memory 1 address register) + Object *s7fcr; // 0xCC (Stream x FIFO control register) + } reg; + + struct { + + // LISR (Low interrupt status register) bitfields. + struct { + Object *feif0; // [0:0] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif0; // [2:2] Stream x direct mode error interrupt flag (x=3..0) + Object *teif0; // [3:3] Stream x transfer error interrupt flag (x=3..0) + Object *htif0; // [4:4] Stream x half transfer interrupt flag (x=3..0) + Object *tcif0; // [5:5] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif1; // [6:6] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif1; // [8:8] Stream x direct mode error interrupt flag (x=3..0) + Object *teif1; // [9:9] Stream x transfer error interrupt flag (x=3..0) + Object *htif1; // [10:10] Stream x half transfer interrupt flag (x=3..0) + Object *tcif1; // [11:11] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif2; // [16:16] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif2; // [18:18] Stream x direct mode error interrupt flag (x=3..0) + Object *teif2; // [19:19] Stream x transfer error interrupt flag (x=3..0) + Object *htif2; // [20:20] Stream x half transfer interrupt flag (x=3..0) + Object *tcif2; // [21:21] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif3; // [22:22] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif3; // [24:24] Stream x direct mode error interrupt flag (x=3..0) + Object *teif3; // [25:25] Stream x transfer error interrupt flag (x=3..0) + Object *htif3; // [26:26] Stream x half transfer interrupt flag (x=3..0) + Object *tcif3; // [27:27] Stream x transfer complete interrupt flag (x = 3..0) + } lisr; + + // HISR (High interrupt status register) bitfields. + struct { + Object *feif4; // [0:0] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif4; // [2:2] Stream x direct mode error interrupt flag (x=7..4) + Object *teif4; // [3:3] Stream x transfer error interrupt flag (x=7..4) + Object *htif4; // [4:4] Stream x half transfer interrupt flag (x=7..4) + Object *tcif4; // [5:5] Stream x transfer complete interrupt flag (x=7..4) + Object *feif5; // [6:6] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif5; // [8:8] Stream x direct mode error interrupt flag (x=7..4) + Object *teif5; // [9:9] Stream x transfer error interrupt flag (x=7..4) + Object *htif5; // [10:10] Stream x half transfer interrupt flag (x=7..4) + Object *tcif5; // [11:11] Stream x transfer complete interrupt flag (x=7..4) + Object *feif6; // [16:16] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif6; // [18:18] Stream x direct mode error interrupt flag (x=7..4) + Object *teif6; // [19:19] Stream x transfer error interrupt flag (x=7..4) + Object *htif6; // [20:20] Stream x half transfer interrupt flag (x=7..4) + Object *tcif6; // [21:21] Stream x transfer complete interrupt flag (x=7..4) + Object *feif7; // [22:22] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif7; // [24:24] Stream x direct mode error interrupt flag (x=7..4) + Object *teif7; // [25:25] Stream x transfer error interrupt flag (x=7..4) + Object *htif7; // [26:26] Stream x half transfer interrupt flag (x=7..4) + Object *tcif7; // [27:27] Stream x transfer complete interrupt flag (x=7..4) + } hisr; + + // LIFCR (Low interrupt flag clear register) bitfields. + struct { + Object *cfeif0; // [0:0] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif0; // [2:2] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif0; // [3:3] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif0; // [4:4] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif0; // [5:5] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif1; // [6:6] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif1; // [8:8] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif1; // [9:9] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif1; // [10:10] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif1; // [11:11] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif2; // [16:16] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif2; // [18:18] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif2; // [19:19] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif2; // [20:20] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif2; // [21:21] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif3; // [22:22] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif3; // [24:24] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif3; // [25:25] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif3; // [26:26] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif3; // [27:27] Stream x clear transfer complete interrupt flag (x = 3..0) + } lifcr; + + // HIFCR (High interrupt flag clear register) bitfields. + struct { + Object *cfeif4; // [0:0] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif4; // [2:2] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif4; // [3:3] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif4; // [4:4] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif4; // [5:5] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif5; // [6:6] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif5; // [8:8] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif5; // [9:9] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif5; // [10:10] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif5; // [11:11] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif6; // [16:16] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif6; // [18:18] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif6; // [19:19] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif6; // [20:20] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif6; // [21:21] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif7; // [22:22] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif7; // [24:24] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif7; // [25:25] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif7; // [26:26] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif7; // [27:27] Stream x clear transfer complete interrupt flag (x = 7..4) + } hifcr; + + // S0CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s0cr; + + // S0NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s0ndtr; + + // S0PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s0par; + + // S0M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s0m0ar; + + // S0M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s0m1ar; + + // S0FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s0fcr; + + // S1CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s1cr; + + // S1NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s1ndtr; + + // S1PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s1par; + + // S1M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s1m0ar; + + // S1M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s1m1ar; + + // S1FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s1fcr; + + // S2CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s2cr; + + // S2NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s2ndtr; + + // S2PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s2par; + + // S2M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s2m0ar; + + // S2M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s2m1ar; + + // S2FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s2fcr; + + // S3CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s3cr; + + // S3NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s3ndtr; + + // S3PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s3par; + + // S3M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s3m0ar; + + // S3M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s3m1ar; + + // S3FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s3fcr; + + // S4CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s4cr; + + // S4NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s4ndtr; + + // S4PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s4par; + + // S4M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s4m0ar; + + // S4M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s4m1ar; + + // S4FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s4fcr; + + // S5CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s5cr; + + // S5NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s5ndtr; + + // S5PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s5par; + + // S5M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s5m0ar; + + // S5M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s5m1ar; + + // S5FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s5fcr; + + // S6CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s6cr; + + // S6NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s6ndtr; + + // S6PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s6par; + + // S6M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s6m0ar; + + // S6M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s6m1ar; + + // S6FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s6fcr; + + // S7CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s7cr; + + // S7NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s7ndtr; + + // S7PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s7par; + + // S7M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s7m0ar; + + // S7M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s7m1ar; + + // S7FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s7fcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/exti.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/exti.c new file mode 100644 index 0000000000..44b86e94b8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/exti.c @@ -0,0 +1,390 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_exti_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.imr = cm_object_get_child_by_name(obj, "IMR"); + state->u.f4.reg.emr = cm_object_get_child_by_name(obj, "EMR"); + state->u.f4.reg.rtsr = cm_object_get_child_by_name(obj, "RTSR"); + state->u.f4.reg.ftsr = cm_object_get_child_by_name(obj, "FTSR"); + state->u.f4.reg.swier = cm_object_get_child_by_name(obj, "SWIER"); + state->u.f4.reg.pr = cm_object_get_child_by_name(obj, "PR"); + + + // IMR bitfields. + state->u.f4.fld.imr.mr0 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR0"); + state->u.f4.fld.imr.mr1 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR1"); + state->u.f4.fld.imr.mr2 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR2"); + state->u.f4.fld.imr.mr3 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR3"); + state->u.f4.fld.imr.mr4 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR4"); + state->u.f4.fld.imr.mr5 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR5"); + state->u.f4.fld.imr.mr6 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR6"); + state->u.f4.fld.imr.mr7 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR7"); + state->u.f4.fld.imr.mr8 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR8"); + state->u.f4.fld.imr.mr9 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR9"); + state->u.f4.fld.imr.mr10 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR10"); + state->u.f4.fld.imr.mr11 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR11"); + state->u.f4.fld.imr.mr12 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR12"); + state->u.f4.fld.imr.mr13 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR13"); + state->u.f4.fld.imr.mr14 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR14"); + state->u.f4.fld.imr.mr15 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR15"); + state->u.f4.fld.imr.mr16 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR16"); + state->u.f4.fld.imr.mr17 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR17"); + state->u.f4.fld.imr.mr18 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR18"); + state->u.f4.fld.imr.mr19 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR19"); + state->u.f4.fld.imr.mr20 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR20"); + state->u.f4.fld.imr.mr21 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR21"); + state->u.f4.fld.imr.mr22 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR22"); + + // EMR bitfields. + state->u.f4.fld.emr.mr0 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR0"); + state->u.f4.fld.emr.mr1 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR1"); + state->u.f4.fld.emr.mr2 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR2"); + state->u.f4.fld.emr.mr3 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR3"); + state->u.f4.fld.emr.mr4 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR4"); + state->u.f4.fld.emr.mr5 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR5"); + state->u.f4.fld.emr.mr6 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR6"); + state->u.f4.fld.emr.mr7 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR7"); + state->u.f4.fld.emr.mr8 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR8"); + state->u.f4.fld.emr.mr9 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR9"); + state->u.f4.fld.emr.mr10 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR10"); + state->u.f4.fld.emr.mr11 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR11"); + state->u.f4.fld.emr.mr12 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR12"); + state->u.f4.fld.emr.mr13 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR13"); + state->u.f4.fld.emr.mr14 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR14"); + state->u.f4.fld.emr.mr15 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR15"); + state->u.f4.fld.emr.mr16 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR16"); + state->u.f4.fld.emr.mr17 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR17"); + state->u.f4.fld.emr.mr18 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR18"); + state->u.f4.fld.emr.mr19 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR19"); + state->u.f4.fld.emr.mr20 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR20"); + state->u.f4.fld.emr.mr21 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR21"); + state->u.f4.fld.emr.mr22 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR22"); + + // RTSR bitfields. + state->u.f4.fld.rtsr.tr0 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR0"); + state->u.f4.fld.rtsr.tr1 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR1"); + state->u.f4.fld.rtsr.tr2 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR2"); + state->u.f4.fld.rtsr.tr3 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR3"); + state->u.f4.fld.rtsr.tr4 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR4"); + state->u.f4.fld.rtsr.tr5 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR5"); + state->u.f4.fld.rtsr.tr6 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR6"); + state->u.f4.fld.rtsr.tr7 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR7"); + state->u.f4.fld.rtsr.tr8 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR8"); + state->u.f4.fld.rtsr.tr9 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR9"); + state->u.f4.fld.rtsr.tr10 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR10"); + state->u.f4.fld.rtsr.tr11 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR11"); + state->u.f4.fld.rtsr.tr12 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR12"); + state->u.f4.fld.rtsr.tr13 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR13"); + state->u.f4.fld.rtsr.tr14 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR14"); + state->u.f4.fld.rtsr.tr15 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR15"); + state->u.f4.fld.rtsr.tr16 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR16"); + state->u.f4.fld.rtsr.tr17 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR17"); + state->u.f4.fld.rtsr.tr18 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR18"); + state->u.f4.fld.rtsr.tr19 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR19"); + state->u.f4.fld.rtsr.tr20 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR20"); + state->u.f4.fld.rtsr.tr21 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR21"); + state->u.f4.fld.rtsr.tr22 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR22"); + + // FTSR bitfields. + state->u.f4.fld.ftsr.tr0 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR0"); + state->u.f4.fld.ftsr.tr1 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR1"); + state->u.f4.fld.ftsr.tr2 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR2"); + state->u.f4.fld.ftsr.tr3 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR3"); + state->u.f4.fld.ftsr.tr4 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR4"); + state->u.f4.fld.ftsr.tr5 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR5"); + state->u.f4.fld.ftsr.tr6 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR6"); + state->u.f4.fld.ftsr.tr7 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR7"); + state->u.f4.fld.ftsr.tr8 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR8"); + state->u.f4.fld.ftsr.tr9 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR9"); + state->u.f4.fld.ftsr.tr10 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR10"); + state->u.f4.fld.ftsr.tr11 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR11"); + state->u.f4.fld.ftsr.tr12 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR12"); + state->u.f4.fld.ftsr.tr13 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR13"); + state->u.f4.fld.ftsr.tr14 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR14"); + state->u.f4.fld.ftsr.tr15 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR15"); + state->u.f4.fld.ftsr.tr16 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR16"); + state->u.f4.fld.ftsr.tr17 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR17"); + state->u.f4.fld.ftsr.tr18 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR18"); + state->u.f4.fld.ftsr.tr19 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR19"); + state->u.f4.fld.ftsr.tr20 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR20"); + state->u.f4.fld.ftsr.tr21 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR21"); + state->u.f4.fld.ftsr.tr22 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR22"); + + // SWIER bitfields. + state->u.f4.fld.swier.swier0 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER0"); + state->u.f4.fld.swier.swier1 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER1"); + state->u.f4.fld.swier.swier2 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER2"); + state->u.f4.fld.swier.swier3 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER3"); + state->u.f4.fld.swier.swier4 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER4"); + state->u.f4.fld.swier.swier5 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER5"); + state->u.f4.fld.swier.swier6 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER6"); + state->u.f4.fld.swier.swier7 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER7"); + state->u.f4.fld.swier.swier8 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER8"); + state->u.f4.fld.swier.swier9 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER9"); + state->u.f4.fld.swier.swier10 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER10"); + state->u.f4.fld.swier.swier11 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER11"); + state->u.f4.fld.swier.swier12 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER12"); + state->u.f4.fld.swier.swier13 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER13"); + state->u.f4.fld.swier.swier14 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER14"); + state->u.f4.fld.swier.swier15 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER15"); + state->u.f4.fld.swier.swier16 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER16"); + state->u.f4.fld.swier.swier17 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER17"); + state->u.f4.fld.swier.swier18 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER18"); + state->u.f4.fld.swier.swier19 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER19"); + state->u.f4.fld.swier.swier20 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER20"); + state->u.f4.fld.swier.swier21 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER21"); + state->u.f4.fld.swier.swier22 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER22"); + + // PR bitfields. + state->u.f4.fld.pr.pr0 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR0"); + state->u.f4.fld.pr.pr1 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR1"); + state->u.f4.fld.pr.pr2 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR2"); + state->u.f4.fld.pr.pr3 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR3"); + state->u.f4.fld.pr.pr4 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR4"); + state->u.f4.fld.pr.pr5 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR5"); + state->u.f4.fld.pr.pr6 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR6"); + state->u.f4.fld.pr.pr7 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR7"); + state->u.f4.fld.pr.pr8 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR8"); + state->u.f4.fld.pr.pr9 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR9"); + state->u.f4.fld.pr.pr10 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR10"); + state->u.f4.fld.pr.pr11 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR11"); + state->u.f4.fld.pr.pr12 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR12"); + state->u.f4.fld.pr.pr13 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR13"); + state->u.f4.fld.pr.pr14 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR14"); + state->u.f4.fld.pr.pr15 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR15"); + state->u.f4.fld.pr.pr16 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR16"); + state->u.f4.fld.pr.pr17 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR17"); + state->u.f4.fld.pr.pr18 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR18"); + state->u.f4.fld.pr.pr19 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR19"); + state->u.f4.fld.pr.pr20 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR20"); + state->u.f4.fld.pr.pr21 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR21"); + state->u.f4.fld.pr.pr22 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR22"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_exti_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_exti_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_exti_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_exti_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_exti_is_enabled(Object *obj) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_exti_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_exti_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_EXTI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32EXTIState *state = STM32_EXTI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "EXTI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_exti_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_exti_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_exti_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_exti_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_exti_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/EXTIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_exti_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_EXTI); +} + +static void stm32_exti_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_exti_reset_callback; + dc->realize = stm32_exti_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_exti_is_enabled; +} + +static const TypeInfo stm32_exti_type_info = { + .name = TYPE_STM32_EXTI, + .parent = TYPE_STM32_EXTI_PARENT, + .instance_init = stm32_exti_instance_init_callback, + .instance_size = sizeof(STM32EXTIState), + .class_init = stm32_exti_class_init_callback, + .class_size = sizeof(STM32EXTIClass) }; + +static void stm32_exti_register_types(void) +{ + type_register_static(&stm32_exti_type_info); +} + +type_init(stm32_exti_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/exti.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/exti.h new file mode 100644 index 0000000000..c60df55b50 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/exti.h @@ -0,0 +1,267 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_EXTI_H_ +#define STM32_EXTI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_EXTI DEVICE_PATH_STM32 "EXTI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_EXTI TYPE_STM32_PREFIX "exti" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_EXTI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32EXTIParentClass; +typedef PeripheralState STM32EXTIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_EXTI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32EXTIClass, (obj), TYPE_STM32_EXTI) +#define STM32_EXTI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32EXTIClass, (klass), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentClass parent_class; + // public: + + // None, so far. +} STM32EXTIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_EXTI_STATE(obj) \ + OBJECT_CHECK(STM32EXTIState, (obj), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 EXTI (External interrupt/event controller) registers. + struct { + Object *imr; // 0x0 (Interrupt mask register (EXTI_IMR)) + Object *emr; // 0x4 (Event mask register (EXTI_EMR)) + Object *rtsr; // 0x8 (Rising Trigger selection register (EXTI_RTSR)) + Object *ftsr; // 0xC (Falling Trigger selection register (EXTI_FTSR)) + Object *swier; // 0x10 (Software interrupt event register (EXTI_SWIER)) + Object *pr; // 0x14 (Pending register (EXTI_PR)) + } reg; + + struct { + + // IMR (Interrupt mask register (EXTI_IMR)) bitfields. + struct { + Object *mr0; // [0:0] Interrupt Mask on line 0 + Object *mr1; // [1:1] Interrupt Mask on line 1 + Object *mr2; // [2:2] Interrupt Mask on line 2 + Object *mr3; // [3:3] Interrupt Mask on line 3 + Object *mr4; // [4:4] Interrupt Mask on line 4 + Object *mr5; // [5:5] Interrupt Mask on line 5 + Object *mr6; // [6:6] Interrupt Mask on line 6 + Object *mr7; // [7:7] Interrupt Mask on line 7 + Object *mr8; // [8:8] Interrupt Mask on line 8 + Object *mr9; // [9:9] Interrupt Mask on line 9 + Object *mr10; // [10:10] Interrupt Mask on line 10 + Object *mr11; // [11:11] Interrupt Mask on line 11 + Object *mr12; // [12:12] Interrupt Mask on line 12 + Object *mr13; // [13:13] Interrupt Mask on line 13 + Object *mr14; // [14:14] Interrupt Mask on line 14 + Object *mr15; // [15:15] Interrupt Mask on line 15 + Object *mr16; // [16:16] Interrupt Mask on line 16 + Object *mr17; // [17:17] Interrupt Mask on line 17 + Object *mr18; // [18:18] Interrupt Mask on line 18 + Object *mr19; // [19:19] Interrupt Mask on line 19 + Object *mr20; // [20:20] Interrupt Mask on line 20 + Object *mr21; // [21:21] Interrupt Mask on line 21 + Object *mr22; // [22:22] Interrupt Mask on line 22 + } imr; + + // EMR (Event mask register (EXTI_EMR)) bitfields. + struct { + Object *mr0; // [0:0] Event Mask on line 0 + Object *mr1; // [1:1] Event Mask on line 1 + Object *mr2; // [2:2] Event Mask on line 2 + Object *mr3; // [3:3] Event Mask on line 3 + Object *mr4; // [4:4] Event Mask on line 4 + Object *mr5; // [5:5] Event Mask on line 5 + Object *mr6; // [6:6] Event Mask on line 6 + Object *mr7; // [7:7] Event Mask on line 7 + Object *mr8; // [8:8] Event Mask on line 8 + Object *mr9; // [9:9] Event Mask on line 9 + Object *mr10; // [10:10] Event Mask on line 10 + Object *mr11; // [11:11] Event Mask on line 11 + Object *mr12; // [12:12] Event Mask on line 12 + Object *mr13; // [13:13] Event Mask on line 13 + Object *mr14; // [14:14] Event Mask on line 14 + Object *mr15; // [15:15] Event Mask on line 15 + Object *mr16; // [16:16] Event Mask on line 16 + Object *mr17; // [17:17] Event Mask on line 17 + Object *mr18; // [18:18] Event Mask on line 18 + Object *mr19; // [19:19] Event Mask on line 19 + Object *mr20; // [20:20] Event Mask on line 20 + Object *mr21; // [21:21] Event Mask on line 21 + Object *mr22; // [22:22] Event Mask on line 22 + } emr; + + // RTSR (Rising Trigger selection register (EXTI_RTSR)) bitfields. + struct { + Object *tr0; // [0:0] Rising trigger event configuration of line 0 + Object *tr1; // [1:1] Rising trigger event configuration of line 1 + Object *tr2; // [2:2] Rising trigger event configuration of line 2 + Object *tr3; // [3:3] Rising trigger event configuration of line 3 + Object *tr4; // [4:4] Rising trigger event configuration of line 4 + Object *tr5; // [5:5] Rising trigger event configuration of line 5 + Object *tr6; // [6:6] Rising trigger event configuration of line 6 + Object *tr7; // [7:7] Rising trigger event configuration of line 7 + Object *tr8; // [8:8] Rising trigger event configuration of line 8 + Object *tr9; // [9:9] Rising trigger event configuration of line 9 + Object *tr10; // [10:10] Rising trigger event configuration of line 10 + Object *tr11; // [11:11] Rising trigger event configuration of line 11 + Object *tr12; // [12:12] Rising trigger event configuration of line 12 + Object *tr13; // [13:13] Rising trigger event configuration of line 13 + Object *tr14; // [14:14] Rising trigger event configuration of line 14 + Object *tr15; // [15:15] Rising trigger event configuration of line 15 + Object *tr16; // [16:16] Rising trigger event configuration of line 16 + Object *tr17; // [17:17] Rising trigger event configuration of line 17 + Object *tr18; // [18:18] Rising trigger event configuration of line 18 + Object *tr19; // [19:19] Rising trigger event configuration of line 19 + Object *tr20; // [20:20] Rising trigger event configuration of line 20 + Object *tr21; // [21:21] Rising trigger event configuration of line 21 + Object *tr22; // [22:22] Rising trigger event configuration of line 22 + } rtsr; + + // FTSR (Falling Trigger selection register (EXTI_FTSR)) bitfields. + struct { + Object *tr0; // [0:0] Falling trigger event configuration of line 0 + Object *tr1; // [1:1] Falling trigger event configuration of line 1 + Object *tr2; // [2:2] Falling trigger event configuration of line 2 + Object *tr3; // [3:3] Falling trigger event configuration of line 3 + Object *tr4; // [4:4] Falling trigger event configuration of line 4 + Object *tr5; // [5:5] Falling trigger event configuration of line 5 + Object *tr6; // [6:6] Falling trigger event configuration of line 6 + Object *tr7; // [7:7] Falling trigger event configuration of line 7 + Object *tr8; // [8:8] Falling trigger event configuration of line 8 + Object *tr9; // [9:9] Falling trigger event configuration of line 9 + Object *tr10; // [10:10] Falling trigger event configuration of line 10 + Object *tr11; // [11:11] Falling trigger event configuration of line 11 + Object *tr12; // [12:12] Falling trigger event configuration of line 12 + Object *tr13; // [13:13] Falling trigger event configuration of line 13 + Object *tr14; // [14:14] Falling trigger event configuration of line 14 + Object *tr15; // [15:15] Falling trigger event configuration of line 15 + Object *tr16; // [16:16] Falling trigger event configuration of line 16 + Object *tr17; // [17:17] Falling trigger event configuration of line 17 + Object *tr18; // [18:18] Falling trigger event configuration of line 18 + Object *tr19; // [19:19] Falling trigger event configuration of line 19 + Object *tr20; // [20:20] Falling trigger event configuration of line 20 + Object *tr21; // [21:21] Falling trigger event configuration of line 21 + Object *tr22; // [22:22] Falling trigger event configuration of line 22 + } ftsr; + + // SWIER (Software interrupt event register (EXTI_SWIER)) bitfields. + struct { + Object *swier0; // [0:0] Software Interrupt on line 0 + Object *swier1; // [1:1] Software Interrupt on line 1 + Object *swier2; // [2:2] Software Interrupt on line 2 + Object *swier3; // [3:3] Software Interrupt on line 3 + Object *swier4; // [4:4] Software Interrupt on line 4 + Object *swier5; // [5:5] Software Interrupt on line 5 + Object *swier6; // [6:6] Software Interrupt on line 6 + Object *swier7; // [7:7] Software Interrupt on line 7 + Object *swier8; // [8:8] Software Interrupt on line 8 + Object *swier9; // [9:9] Software Interrupt on line 9 + Object *swier10; // [10:10] Software Interrupt on line 10 + Object *swier11; // [11:11] Software Interrupt on line 11 + Object *swier12; // [12:12] Software Interrupt on line 12 + Object *swier13; // [13:13] Software Interrupt on line 13 + Object *swier14; // [14:14] Software Interrupt on line 14 + Object *swier15; // [15:15] Software Interrupt on line 15 + Object *swier16; // [16:16] Software Interrupt on line 16 + Object *swier17; // [17:17] Software Interrupt on line 17 + Object *swier18; // [18:18] Software Interrupt on line 18 + Object *swier19; // [19:19] Software Interrupt on line 19 + Object *swier20; // [20:20] Software Interrupt on line 20 + Object *swier21; // [21:21] Software Interrupt on line 21 + Object *swier22; // [22:22] Software Interrupt on line 22 + } swier; + + // PR (Pending register (EXTI_PR)) bitfields. + struct { + Object *pr0; // [0:0] Pending bit 0 + Object *pr1; // [1:1] Pending bit 1 + Object *pr2; // [2:2] Pending bit 2 + Object *pr3; // [3:3] Pending bit 3 + Object *pr4; // [4:4] Pending bit 4 + Object *pr5; // [5:5] Pending bit 5 + Object *pr6; // [6:6] Pending bit 6 + Object *pr7; // [7:7] Pending bit 7 + Object *pr8; // [8:8] Pending bit 8 + Object *pr9; // [9:9] Pending bit 9 + Object *pr10; // [10:10] Pending bit 10 + Object *pr11; // [11:11] Pending bit 11 + Object *pr12; // [12:12] Pending bit 12 + Object *pr13; // [13:13] Pending bit 13 + Object *pr14; // [14:14] Pending bit 14 + Object *pr15; // [15:15] Pending bit 15 + Object *pr16; // [16:16] Pending bit 16 + Object *pr17; // [17:17] Pending bit 17 + Object *pr18; // [18:18] Pending bit 18 + Object *pr19; // [19:19] Pending bit 19 + Object *pr20; // [20:20] Pending bit 20 + Object *pr21; // [21:21] Pending bit 21 + Object *pr22; // [22:22] Pending bit 22 + } pr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32EXTIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_EXTI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/flash.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/flash.c new file mode 100644 index 0000000000..f9e6f5a7d0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/flash.c @@ -0,0 +1,284 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_flash_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.acr = cm_object_get_child_by_name(obj, "ACR"); + state->u.f4.reg.keyr = cm_object_get_child_by_name(obj, "KEYR"); + state->u.f4.reg.optkeyr = cm_object_get_child_by_name(obj, "OPTKEYR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.optcr = cm_object_get_child_by_name(obj, "OPTCR"); + + + // ACR bitfields. + state->u.f4.fld.acr.latency = cm_object_get_child_by_name(state->u.f4.reg.acr, "LATENCY"); + state->u.f4.fld.acr.prften = cm_object_get_child_by_name(state->u.f4.reg.acr, "PRFTEN"); + state->u.f4.fld.acr.icen = cm_object_get_child_by_name(state->u.f4.reg.acr, "ICEN"); + state->u.f4.fld.acr.dcen = cm_object_get_child_by_name(state->u.f4.reg.acr, "DCEN"); + state->u.f4.fld.acr.icrst = cm_object_get_child_by_name(state->u.f4.reg.acr, "ICRST"); + state->u.f4.fld.acr.dcrst = cm_object_get_child_by_name(state->u.f4.reg.acr, "DCRST"); + + // KEYR bitfields. + state->u.f4.fld.keyr.key = cm_object_get_child_by_name(state->u.f4.reg.keyr, "KEY"); + + // OPTKEYR bitfields. + state->u.f4.fld.optkeyr.optkey = cm_object_get_child_by_name(state->u.f4.reg.optkeyr, "OPTKEY"); + + // SR bitfields. + state->u.f4.fld.sr.eop = cm_object_get_child_by_name(state->u.f4.reg.sr, "EOP"); + state->u.f4.fld.sr.operr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OPERR"); + state->u.f4.fld.sr.wrperr = cm_object_get_child_by_name(state->u.f4.reg.sr, "WRPERR"); + state->u.f4.fld.sr.pgaerr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGAERR"); + state->u.f4.fld.sr.pgperr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGPERR"); + state->u.f4.fld.sr.pgserr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGSERR"); + state->u.f4.fld.sr.bsy = cm_object_get_child_by_name(state->u.f4.reg.sr, "BSY"); + + // CR bitfields. + state->u.f4.fld.cr.pg = cm_object_get_child_by_name(state->u.f4.reg.cr, "PG"); + state->u.f4.fld.cr.ser = cm_object_get_child_by_name(state->u.f4.reg.cr, "SER"); + state->u.f4.fld.cr.mer = cm_object_get_child_by_name(state->u.f4.reg.cr, "MER"); + state->u.f4.fld.cr.snb = cm_object_get_child_by_name(state->u.f4.reg.cr, "SNB"); + state->u.f4.fld.cr.psize = cm_object_get_child_by_name(state->u.f4.reg.cr, "PSIZE"); + state->u.f4.fld.cr.strt = cm_object_get_child_by_name(state->u.f4.reg.cr, "STRT"); + state->u.f4.fld.cr.eopie = cm_object_get_child_by_name(state->u.f4.reg.cr, "EOPIE"); + state->u.f4.fld.cr.errie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ERRIE"); + state->u.f4.fld.cr.lock = cm_object_get_child_by_name(state->u.f4.reg.cr, "LOCK"); + + // OPTCR bitfields. + state->u.f4.fld.optcr.optlock = cm_object_get_child_by_name(state->u.f4.reg.optcr, "OPTLOCK"); + state->u.f4.fld.optcr.optstrt = cm_object_get_child_by_name(state->u.f4.reg.optcr, "OPTSTRT"); + state->u.f4.fld.optcr.bor_lev = cm_object_get_child_by_name(state->u.f4.reg.optcr, "BOR_LEV"); + state->u.f4.fld.optcr.wdg_sw = cm_object_get_child_by_name(state->u.f4.reg.optcr, "WDG_SW"); + state->u.f4.fld.optcr.nrst_stop = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nRST_STOP"); + state->u.f4.fld.optcr.nrst_stdby = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nRST_STDBY"); + state->u.f4.fld.optcr.rdp = cm_object_get_child_by_name(state->u.f4.reg.optcr, "RDP"); + state->u.f4.fld.optcr.nwrp = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nWRP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_flash_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_flash_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_flash_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_flash_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_flash_is_enabled(Object *obj) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_flash_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_flash_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FLASH)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FLASHState *state = STM32_FLASH_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FLASH"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_flash_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_flash_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_flash_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_flash_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_flash_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FLASHEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_flash_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FLASH); +} + +static void stm32_flash_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_flash_reset_callback; + dc->realize = stm32_flash_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_flash_is_enabled; +} + +static const TypeInfo stm32_flash_type_info = { + .name = TYPE_STM32_FLASH, + .parent = TYPE_STM32_FLASH_PARENT, + .instance_init = stm32_flash_instance_init_callback, + .instance_size = sizeof(STM32FLASHState), + .class_init = stm32_flash_class_init_callback, + .class_size = sizeof(STM32FLASHClass) }; + +static void stm32_flash_register_types(void) +{ + type_register_static(&stm32_flash_type_info); +} + +type_init(stm32_flash_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/flash.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/flash.h new file mode 100644 index 0000000000..21558b4bbe --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/flash.h @@ -0,0 +1,161 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FLASH_H_ +#define STM32_FLASH_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FLASH DEVICE_PATH_STM32 "FLASH" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FLASH TYPE_STM32_PREFIX "flash" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FLASH_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FLASHParentClass; +typedef PeripheralState STM32FLASHParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FLASH_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FLASHClass, (obj), TYPE_STM32_FLASH) +#define STM32_FLASH_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FLASHClass, (klass), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentClass parent_class; + // public: + + // None, so far. +} STM32FLASHClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FLASH_STATE(obj) \ + OBJECT_CHECK(STM32FLASHState, (obj), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 FLASH (FLASH) registers. + struct { + Object *acr; // 0x0 (Flash access control register) + Object *keyr; // 0x4 (Flash key register) + Object *optkeyr; // 0x8 (Flash option key register) + Object *sr; // 0xC (Status register) + Object *cr; // 0x10 (Control register) + Object *optcr; // 0x14 (Flash option control register) + } reg; + + struct { + + // ACR (Flash access control register) bitfields. + struct { + Object *latency; // [0:2] Latency + Object *prften; // [8:8] Prefetch enable + Object *icen; // [9:9] Instruction cache enable + Object *dcen; // [10:10] Data cache enable + Object *icrst; // [11:11] Instruction cache reset + Object *dcrst; // [12:12] Data cache reset + } acr; + + // KEYR (Flash key register) bitfields. + struct { + Object *key; // [0:31] FPEC key + } keyr; + + // OPTKEYR (Flash option key register) bitfields. + struct { + Object *optkey; // [0:31] Option byte key + } optkeyr; + + // SR (Status register) bitfields. + struct { + Object *eop; // [0:0] End of operation + Object *operr; // [1:1] Operation error + Object *wrperr; // [4:4] Write protection error + Object *pgaerr; // [5:5] Programming alignment error + Object *pgperr; // [6:6] Programming parallelism error + Object *pgserr; // [7:7] Programming sequence error + Object *bsy; // [16:16] Busy + } sr; + + // CR (Control register) bitfields. + struct { + Object *pg; // [0:0] Programming + Object *ser; // [1:1] Sector Erase + Object *mer; // [2:2] Mass Erase + Object *snb; // [3:6] Sector number + Object *psize; // [8:9] Program size + Object *strt; // [16:16] Start + Object *eopie; // [24:24] End of operation interrupt enable + Object *errie; // [25:25] Error interrupt enable + Object *lock; // [31:31] Lock + } cr; + + // OPTCR (Flash option control register) bitfields. + struct { + Object *optlock; // [0:0] Option lock + Object *optstrt; // [1:1] Option start + Object *bor_lev; // [2:3] BOR reset Level + Object *wdg_sw; // [5:5] WDG_SW User option bytes + Object *nrst_stop; // [6:6] NRST_STOP User option bytes + Object *nrst_stdby; // [7:7] NRST_STDBY User option bytes + Object *rdp; // [8:15] Read protect + Object *nwrp; // [16:27] Not write protect + } optcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FLASHState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FLASH_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioa.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioa.c new file mode 100644 index 0000000000..4a9296793a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioa.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioa.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioa.h new file mode 100644 index 0000000000..a9fc55c378 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioa.h @@ -0,0 +1,325 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOH, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/gpiob.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpiob.c new file mode 100644 index 0000000000..4a9296793a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpiob.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/gpiob.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpiob.h new file mode 100644 index 0000000000..a9fc55c378 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpiob.h @@ -0,0 +1,325 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOH, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioh.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioh.c new file mode 100644 index 0000000000..4a9296793a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioh.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioh.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioh.h new file mode 100644 index 0000000000..a9fc55c378 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/gpioh.h @@ -0,0 +1,325 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOH, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/i2c3.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2c3.c new file mode 100644 index 0000000000..8217dc3c75 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2c3.c @@ -0,0 +1,319 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_i2c_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.oar1 = cm_object_get_child_by_name(obj, "OAR1"); + state->u.f4.reg.oar2 = cm_object_get_child_by_name(obj, "OAR2"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.sr1 = cm_object_get_child_by_name(obj, "SR1"); + state->u.f4.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f4.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + state->u.f4.reg.trise = cm_object_get_child_by_name(obj, "TRISE"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.pe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PE"); + state->u.f4.fld.cr1.smbus = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SMBUS"); + state->u.f4.fld.cr1.smbtype = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SMBTYPE"); + state->u.f4.fld.cr1.enarp = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENARP"); + state->u.f4.fld.cr1.enpec = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENPEC"); + state->u.f4.fld.cr1.engc = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENGC"); + state->u.f4.fld.cr1.nostretch = cm_object_get_child_by_name(state->u.f4.reg.cr1, "NOSTRETCH"); + state->u.f4.fld.cr1.start = cm_object_get_child_by_name(state->u.f4.reg.cr1, "START"); + state->u.f4.fld.cr1.stop = cm_object_get_child_by_name(state->u.f4.reg.cr1, "STOP"); + state->u.f4.fld.cr1.ack = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ACK"); + state->u.f4.fld.cr1.pos = cm_object_get_child_by_name(state->u.f4.reg.cr1, "POS"); + state->u.f4.fld.cr1.pec = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEC"); + state->u.f4.fld.cr1.alert = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ALERT"); + state->u.f4.fld.cr1.swrst = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SWRST"); + + // CR2 bitfields. + state->u.f4.fld.cr2.freq = cm_object_get_child_by_name(state->u.f4.reg.cr2, "FREQ"); + state->u.f4.fld.cr2.iterren = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITERREN"); + state->u.f4.fld.cr2.itevten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITEVTEN"); + state->u.f4.fld.cr2.itbufen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITBUFEN"); + state->u.f4.fld.cr2.dmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DMAEN"); + state->u.f4.fld.cr2.last = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LAST"); + + // OAR1 bitfields. + state->u.f4.fld.oar1.add0 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD0"); + state->u.f4.fld.oar1.add7 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD7"); + state->u.f4.fld.oar1.add10 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD10"); + state->u.f4.fld.oar1.addmode = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADDMODE"); + + // OAR2 bitfields. + state->u.f4.fld.oar2.endual = cm_object_get_child_by_name(state->u.f4.reg.oar2, "ENDUAL"); + state->u.f4.fld.oar2.add2 = cm_object_get_child_by_name(state->u.f4.reg.oar2, "ADD2"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // SR1 bitfields. + state->u.f4.fld.sr1.sb = cm_object_get_child_by_name(state->u.f4.reg.sr1, "SB"); + state->u.f4.fld.sr1.addr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ADDR"); + state->u.f4.fld.sr1.btf = cm_object_get_child_by_name(state->u.f4.reg.sr1, "BTF"); + state->u.f4.fld.sr1.add10 = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ADD10"); + state->u.f4.fld.sr1.stopf = cm_object_get_child_by_name(state->u.f4.reg.sr1, "STOPF"); + state->u.f4.fld.sr1.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr1, "RxNE"); + state->u.f4.fld.sr1.txe = cm_object_get_child_by_name(state->u.f4.reg.sr1, "TxE"); + state->u.f4.fld.sr1.berr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "BERR"); + state->u.f4.fld.sr1.arlo = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ARLO"); + state->u.f4.fld.sr1.af = cm_object_get_child_by_name(state->u.f4.reg.sr1, "AF"); + state->u.f4.fld.sr1.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "OVR"); + state->u.f4.fld.sr1.pecerr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "PECERR"); + state->u.f4.fld.sr1.timeout = cm_object_get_child_by_name(state->u.f4.reg.sr1, "TIMEOUT"); + state->u.f4.fld.sr1.smbalert = cm_object_get_child_by_name(state->u.f4.reg.sr1, "SMBALERT"); + + // SR2 bitfields. + state->u.f4.fld.sr2.msl = cm_object_get_child_by_name(state->u.f4.reg.sr2, "MSL"); + state->u.f4.fld.sr2.busy = cm_object_get_child_by_name(state->u.f4.reg.sr2, "BUSY"); + state->u.f4.fld.sr2.tra = cm_object_get_child_by_name(state->u.f4.reg.sr2, "TRA"); + state->u.f4.fld.sr2.gencall = cm_object_get_child_by_name(state->u.f4.reg.sr2, "GENCALL"); + state->u.f4.fld.sr2.smbdefault = cm_object_get_child_by_name(state->u.f4.reg.sr2, "SMBDEFAULT"); + state->u.f4.fld.sr2.smbhost = cm_object_get_child_by_name(state->u.f4.reg.sr2, "SMBHOST"); + state->u.f4.fld.sr2.dualf = cm_object_get_child_by_name(state->u.f4.reg.sr2, "DUALF"); + state->u.f4.fld.sr2.pec = cm_object_get_child_by_name(state->u.f4.reg.sr2, "PEC"); + + // CCR bitfields. + state->u.f4.fld.ccr.ccr = cm_object_get_child_by_name(state->u.f4.reg.ccr, "CCR"); + state->u.f4.fld.ccr.duty = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DUTY"); + state->u.f4.fld.ccr.f_s = cm_object_get_child_by_name(state->u.f4.reg.ccr, "F_S"); + + // TRISE bitfields. + state->u.f4.fld.trise.trise = cm_object_get_child_by_name(state->u.f4.reg.trise, "TRISE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2c_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2c_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2c_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2c_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2c_is_enabled(Object *obj) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2c_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2CState *state = STM32_I2C_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_I2C_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2c_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2C)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2CState *state = STM32_I2C_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2C"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_i2c_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2c_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_i2c_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2c_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_i2c_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2C%dEN", + 1 + state->port_index - STM32_PORT_I2C1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2c_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2C); +} + +static void stm32_i2c_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2c_reset_callback; + dc->realize = stm32_i2c_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2c_is_enabled; +} + +static const TypeInfo stm32_i2c_type_info = { + .name = TYPE_STM32_I2C, + .parent = TYPE_STM32_I2C_PARENT, + .instance_init = stm32_i2c_instance_init_callback, + .instance_size = sizeof(STM32I2CState), + .class_init = stm32_i2c_class_init_callback, + .class_size = sizeof(STM32I2CClass) }; + +static void stm32_i2c_register_types(void) +{ + type_register_static(&stm32_i2c_type_info); +} + +type_init(stm32_i2c_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/i2c3.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2c3.h new file mode 100644 index 0000000000..a94d1f8319 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2c3.h @@ -0,0 +1,209 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2C_H_ +#define STM32_I2C_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2C DEVICE_PATH_STM32 "I2C" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_I2C1, + STM32_PORT_I2C2, + STM32_PORT_I2C3, + STM32_PORT_I2C_UNDEFINED = 0xFF, +} stm32_i2c_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2C TYPE_STM32_PREFIX "i2c" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2C_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2CParentClass; +typedef PeripheralState STM32I2CParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2CClass, (obj), TYPE_STM32_I2C) +#define STM32_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2CClass, (klass), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentClass parent_class; + // public: + + // None, so far. +} STM32I2CClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2C_STATE(obj) \ + OBJECT_CHECK(STM32I2CState, (obj), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_i2c_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 I2C (Inter-integrated circuit) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *oar1; // 0x8 (Own address register 1) + Object *oar2; // 0xC (Own address register 2) + Object *dr; // 0x10 (Data register) + Object *sr1; // 0x14 (Status register 1) + Object *sr2; // 0x18 (Status register 2) + Object *ccr; // 0x1C (Clock control register) + Object *trise; // 0x20 (TRISE register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *pe; // [0:0] Peripheral enable + Object *smbus; // [1:1] SMBus mode + Object *smbtype; // [3:3] SMBus type + Object *enarp; // [4:4] ARP enable + Object *enpec; // [5:5] PEC enable + Object *engc; // [6:6] General call enable + Object *nostretch; // [7:7] Clock stretching disable (Slave mode) + Object *start; // [8:8] Start generation + Object *stop; // [9:9] Stop generation + Object *ack; // [10:10] Acknowledge enable + Object *pos; // [11:11] Acknowledge/PEC Position (for data reception) + Object *pec; // [12:12] Packet error checking + Object *alert; // [13:13] SMBus alert + Object *swrst; // [15:15] Software reset + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *freq; // [0:5] Peripheral clock frequency + Object *iterren; // [8:8] Error interrupt enable + Object *itevten; // [9:9] Event interrupt enable + Object *itbufen; // [10:10] Buffer interrupt enable + Object *dmaen; // [11:11] DMA requests enable + Object *last; // [12:12] DMA last transfer + } cr2; + + // OAR1 (Own address register 1) bitfields. + struct { + Object *add0; // [0:0] Interface address + Object *add7; // [1:7] Interface address + Object *add10; // [8:9] Interface address + Object *addmode; // [15:15] Addressing mode (slave mode) + } oar1; + + // OAR2 (Own address register 2) bitfields. + struct { + Object *endual; // [0:0] Dual addressing mode enable + Object *add2; // [1:7] Interface address + } oar2; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:7] 8-bit data register + } dr; + + // SR1 (Status register 1) bitfields. + struct { + Object *sb; // [0:0] Start bit (Master mode) + Object *addr; // [1:1] Address sent (master mode)/matched (slave mode) + Object *btf; // [2:2] Byte transfer finished + Object *add10; // [3:3] 10-bit header sent (Master mode) + Object *stopf; // [4:4] Stop detection (slave mode) + Object *rxne; // [6:6] Data register not empty (receivers) + Object *txe; // [7:7] Data register empty (transmitters) + Object *berr; // [8:8] Bus error + Object *arlo; // [9:9] Arbitration lost (master mode) + Object *af; // [10:10] Acknowledge failure + Object *ovr; // [11:11] Overrun/Underrun + Object *pecerr; // [12:12] PEC Error in reception + Object *timeout; // [14:14] Timeout or Tlow error + Object *smbalert; // [15:15] SMBus alert + } sr1; + + // SR2 (Status register 2) bitfields. + struct { + Object *msl; // [0:0] Master/slave + Object *busy; // [1:1] Bus busy + Object *tra; // [2:2] Transmitter/receiver + Object *gencall; // [4:4] General call address (Slave mode) + Object *smbdefault; // [5:5] SMBus device default address (Slave mode) + Object *smbhost; // [6:6] SMBus host header (Slave mode) + Object *dualf; // [7:7] Dual flag (Slave mode) + Object *pec; // [8:15] Acket error checking register + } sr2; + + // CCR (Clock control register) bitfields. + struct { + Object *ccr; // [0:11] Clock control register in Fast/Standard mode (Master mode) + Object *duty; // [14:14] Fast mode duty cycle + Object *f_s; // [15:15] I2C master mode selection + } ccr; + + // TRISE (TRISE register) bitfields. + struct { + Object *trise; // [0:5] Maximum rise time in Fast/Standard mode (Master mode) + } trise; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2CState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2C_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/i2s2ext.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2s2ext.c new file mode 100644 index 0000000000..b2526330f1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2s2ext.c @@ -0,0 +1,306 @@ +/* + * STM32 - I2S2ext (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_i2s2ext_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2S2extState *state = STM32_I2S2ext_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.crcpr = cm_object_get_child_by_name(obj, "CRCPR"); + state->u.f4.reg.rxcrcr = cm_object_get_child_by_name(obj, "RXCRCR"); + state->u.f4.reg.txcrcr = cm_object_get_child_by_name(obj, "TXCRCR"); + state->u.f4.reg.i2scfgr = cm_object_get_child_by_name(obj, "I2SCFGR"); + state->u.f4.reg.i2spr = cm_object_get_child_by_name(obj, "I2SPR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cpha = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CPHA"); + state->u.f4.fld.cr1.cpol = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CPOL"); + state->u.f4.fld.cr1.mstr = cm_object_get_child_by_name(state->u.f4.reg.cr1, "MSTR"); + state->u.f4.fld.cr1.br = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BR"); + state->u.f4.fld.cr1.spe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SPE"); + state->u.f4.fld.cr1.lsbfirst = cm_object_get_child_by_name(state->u.f4.reg.cr1, "LSBFIRST"); + state->u.f4.fld.cr1.ssi = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SSI"); + state->u.f4.fld.cr1.ssm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SSM"); + state->u.f4.fld.cr1.rxonly = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXONLY"); + state->u.f4.fld.cr1.dff = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DFF"); + state->u.f4.fld.cr1.crcnext = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CRCNEXT"); + state->u.f4.fld.cr1.crcen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CRCEN"); + state->u.f4.fld.cr1.bidioe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BIDIOE"); + state->u.f4.fld.cr1.bidimode = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BIDIMODE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.rxdmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "RXDMAEN"); + state->u.f4.fld.cr2.txdmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TXDMAEN"); + state->u.f4.fld.cr2.ssoe = cm_object_get_child_by_name(state->u.f4.reg.cr2, "SSOE"); + state->u.f4.fld.cr2.frf = cm_object_get_child_by_name(state->u.f4.reg.cr2, "FRF"); + state->u.f4.fld.cr2.errie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ERRIE"); + state->u.f4.fld.cr2.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "RXNEIE"); + state->u.f4.fld.cr2.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TXEIE"); + + // SR bitfields. + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.chside = cm_object_get_child_by_name(state->u.f4.reg.sr, "CHSIDE"); + state->u.f4.fld.sr.udr = cm_object_get_child_by_name(state->u.f4.reg.sr, "UDR"); + state->u.f4.fld.sr.crcerr = cm_object_get_child_by_name(state->u.f4.reg.sr, "CRCERR"); + state->u.f4.fld.sr.modf = cm_object_get_child_by_name(state->u.f4.reg.sr, "MODF"); + state->u.f4.fld.sr.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OVR"); + state->u.f4.fld.sr.bsy = cm_object_get_child_by_name(state->u.f4.reg.sr, "BSY"); + state->u.f4.fld.sr.tifrfe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIFRFE"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // CRCPR bitfields. + state->u.f4.fld.crcpr.crcpoly = cm_object_get_child_by_name(state->u.f4.reg.crcpr, "CRCPOLY"); + + // RXCRCR bitfields. + state->u.f4.fld.rxcrcr.rxcrc = cm_object_get_child_by_name(state->u.f4.reg.rxcrcr, "RxCRC"); + + // TXCRCR bitfields. + state->u.f4.fld.txcrcr.txcrc = cm_object_get_child_by_name(state->u.f4.reg.txcrcr, "TxCRC"); + + // I2SCFGR bitfields. + state->u.f4.fld.i2scfgr.chlen = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "CHLEN"); + state->u.f4.fld.i2scfgr.datlen = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "DATLEN"); + state->u.f4.fld.i2scfgr.ckpol = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "CKPOL"); + state->u.f4.fld.i2scfgr.i2sstd = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SSTD"); + state->u.f4.fld.i2scfgr.pcmsync = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "PCMSYNC"); + state->u.f4.fld.i2scfgr.i2scfg = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SCFG"); + state->u.f4.fld.i2scfgr.i2se = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SE"); + state->u.f4.fld.i2scfgr.i2smod = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SMOD"); + + // I2SPR bitfields. + state->u.f4.fld.i2spr.i2sdiv = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "I2SDIV"); + state->u.f4.fld.i2spr.odd = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "ODD"); + state->u.f4.fld.i2spr.mckoe = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "MCKOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2s2ext_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2S2extState *state = STM32_I2S2ext_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2s2ext_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2S2extState *state = STM32_I2S2ext_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2s2ext_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2S2extState *state = STM32_I2S2ext_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2s2ext_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2S2extState *state = STM32_I2S2ext_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2s2ext_is_enabled(Object *obj) +{ + STM32I2S2extState *state = STM32_I2S2ext_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2s2ext_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2S2extState *state = STM32_I2S2ext_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2s2ext_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2S2ext)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2S2extState *state = STM32_I2S2ext_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2S2ext"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_i2s2ext_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2s2ext_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_i2s2ext_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2s2ext_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_i2s2ext_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2S2extEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2s2ext_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2S2ext); +} + +static void stm32_i2s2ext_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2s2ext_reset_callback; + dc->realize = stm32_i2s2ext_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2s2ext_is_enabled; +} + +static const TypeInfo stm32_i2s2ext_type_info = { + .name = TYPE_STM32_I2S2ext, + .parent = TYPE_STM32_I2S2ext_PARENT, + .instance_init = stm32_i2s2ext_instance_init_callback, + .instance_size = sizeof(STM32I2S2extState), + .class_init = stm32_i2s2ext_class_init_callback, + .class_size = sizeof(STM32I2S2extClass) }; + +static void stm32_i2s2ext_register_types(void) +{ + type_register_static(&stm32_i2s2ext_type_info); +} + +type_init(stm32_i2s2ext_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/i2s2ext.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2s2ext.h new file mode 100644 index 0000000000..8564a567d0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/i2s2ext.h @@ -0,0 +1,189 @@ +/* + * STM32 - I2S2ext (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2S2ext_H_ +#define STM32_I2S2ext_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2S2ext DEVICE_PATH_STM32 "I2S2ext" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2S2ext TYPE_STM32_PREFIX "i2s2ext" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2S2ext_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2S2extParentClass; +typedef PeripheralState STM32I2S2extParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2S2ext_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2S2extClass, (obj), TYPE_STM32_I2S2ext) +#define STM32_I2S2ext_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2S2extClass, (klass), TYPE_STM32_I2S2ext) + +typedef struct { + // private: + STM32I2S2extParentClass parent_class; + // public: + + // None, so far. +} STM32I2S2extClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2S2ext_STATE(obj) \ + OBJECT_CHECK(STM32I2S2extState, (obj), TYPE_STM32_I2S2ext) + +typedef struct { + // private: + STM32I2S2extParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 I2S2ext (Serial peripheral interface) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *sr; // 0x8 (Status register) + Object *dr; // 0xC (Data register) + Object *crcpr; // 0x10 (CRC polynomial register) + Object *rxcrcr; // 0x14 (RX CRC register) + Object *txcrcr; // 0x18 (TX CRC register) + Object *i2scfgr; // 0x1C (I2S configuration register) + Object *i2spr; // 0x20 (I2S prescaler register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cpha; // [0:0] Clock phase + Object *cpol; // [1:1] Clock polarity + Object *mstr; // [2:2] Master selection + Object *br; // [3:5] Baud rate control + Object *spe; // [6:6] SPI enable + Object *lsbfirst; // [7:7] Frame format + Object *ssi; // [8:8] Internal slave select + Object *ssm; // [9:9] Software slave management + Object *rxonly; // [10:10] Receive only + Object *dff; // [11:11] Data frame format + Object *crcnext; // [12:12] CRC transfer next + Object *crcen; // [13:13] Hardware CRC calculation enable + Object *bidioe; // [14:14] Output enable in bidirectional mode + Object *bidimode; // [15:15] Bidirectional data mode enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *rxdmaen; // [0:0] Rx buffer DMA enable + Object *txdmaen; // [1:1] Tx buffer DMA enable + Object *ssoe; // [2:2] SS output enable + Object *frf; // [4:4] Frame format + Object *errie; // [5:5] Error interrupt enable + Object *rxneie; // [6:6] RX buffer not empty interrupt enable + Object *txeie; // [7:7] Tx buffer empty interrupt enable + } cr2; + + // SR (Status register) bitfields. + struct { + Object *rxne; // [0:0] Receive buffer not empty + Object *txe; // [1:1] Transmit buffer empty + Object *chside; // [2:2] Channel side + Object *udr; // [3:3] Underrun flag + Object *crcerr; // [4:4] CRC error flag + Object *modf; // [5:5] Mode fault + Object *ovr; // [6:6] Overrun flag + Object *bsy; // [7:7] Busy flag + Object *tifrfe; // [8:8] TI frame format error + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:15] Data register + } dr; + + // CRCPR (CRC polynomial register) bitfields. + struct { + Object *crcpoly; // [0:15] CRC polynomial register + } crcpr; + + // RXCRCR (RX CRC register) bitfields. + struct { + Object *rxcrc; // [0:15] Rx CRC register + } rxcrcr; + + // TXCRCR (TX CRC register) bitfields. + struct { + Object *txcrc; // [0:15] Tx CRC register + } txcrcr; + + // I2SCFGR (I2S configuration register) bitfields. + struct { + Object *chlen; // [0:0] Channel length (number of bits per audio channel) + Object *datlen; // [1:2] Data length to be transferred + Object *ckpol; // [3:3] Steady state clock polarity + Object *i2sstd; // [4:5] I2S standard selection + Object *pcmsync; // [7:7] PCM frame synchronization + Object *i2scfg; // [8:9] I2S configuration mode + Object *i2se; // [10:10] I2S Enable + Object *i2smod; // [11:11] I2S mode selection + } i2scfgr; + + // I2SPR (I2S prescaler register) bitfields. + struct { + Object *i2sdiv; // [0:7] I2S Linear prescaler + Object *odd; // [8:8] Odd factor for the prescaler + Object *mckoe; // [9:9] Master clock output enable + } i2spr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2S2extState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2S2ext_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/iwdg.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/iwdg.c new file mode 100644 index 0000000000..9ae2c9735c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/iwdg.c @@ -0,0 +1,251 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_iwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.kr = cm_object_get_child_by_name(obj, "KR"); + state->u.f4.reg.pr = cm_object_get_child_by_name(obj, "PR"); + state->u.f4.reg.rlr = cm_object_get_child_by_name(obj, "RLR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // KR bitfields. + state->u.f4.fld.kr.key = cm_object_get_child_by_name(state->u.f4.reg.kr, "KEY"); + + // PR bitfields. + state->u.f4.fld.pr.pr = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR"); + + // RLR bitfields. + state->u.f4.fld.rlr.rl = cm_object_get_child_by_name(state->u.f4.reg.rlr, "RL"); + + // SR bitfields. + state->u.f4.fld.sr.pvu = cm_object_get_child_by_name(state->u.f4.reg.sr, "PVU"); + state->u.f4.fld.sr.rvu = cm_object_get_child_by_name(state->u.f4.reg.sr, "RVU"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_iwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_iwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_iwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_iwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_iwdg_is_enabled(Object *obj) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_iwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_iwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_IWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32IWDGState *state = STM32_IWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "IWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_iwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_iwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_iwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_iwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_iwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/IWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_iwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_IWDG); +} + +static void stm32_iwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_iwdg_reset_callback; + dc->realize = stm32_iwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_iwdg_is_enabled; +} + +static const TypeInfo stm32_iwdg_type_info = { + .name = TYPE_STM32_IWDG, + .parent = TYPE_STM32_IWDG_PARENT, + .instance_init = stm32_iwdg_instance_init_callback, + .instance_size = sizeof(STM32IWDGState), + .class_init = stm32_iwdg_class_init_callback, + .class_size = sizeof(STM32IWDGClass) }; + +static void stm32_iwdg_register_types(void) +{ + type_register_static(&stm32_iwdg_type_info); +} + +type_init(stm32_iwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/iwdg.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/iwdg.h new file mode 100644 index 0000000000..a8b6eaf767 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/iwdg.h @@ -0,0 +1,124 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_IWDG_H_ +#define STM32_IWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_IWDG DEVICE_PATH_STM32 "IWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_IWDG TYPE_STM32_PREFIX "iwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_IWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32IWDGParentClass; +typedef PeripheralState STM32IWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_IWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32IWDGClass, (obj), TYPE_STM32_IWDG) +#define STM32_IWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32IWDGClass, (klass), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentClass parent_class; + // public: + + // None, so far. +} STM32IWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_IWDG_STATE(obj) \ + OBJECT_CHECK(STM32IWDGState, (obj), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 IWDG (Independent watchdog) registers. + struct { + Object *kr; // 0x0 (Key register) + Object *pr; // 0x4 (Prescaler register) + Object *rlr; // 0x8 (Reload register) + Object *sr; // 0xC (Status register) + } reg; + + struct { + + // KR (Key register) bitfields. + struct { + Object *key; // [0:15] Key value + } kr; + + // PR (Prescaler register) bitfields. + struct { + Object *pr; // [0:2] Prescaler divider + } pr; + + // RLR (Reload register) bitfields. + struct { + Object *rl; // [0:11] Watchdog counter reload value + } rlr; + + // SR (Status register) bitfields. + struct { + Object *pvu; // [0:0] Watchdog prescaler value update + Object *rvu; // [1:1] Watchdog counter reload value update + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32IWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_IWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_device.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_device.c new file mode 100644 index 0000000000..c31015e1fa --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_device.c @@ -0,0 +1,552 @@ +/* + * STM32 - OTG_FS_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_otg_fs_device_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_dcfg = cm_object_get_child_by_name(obj, "FS_DCFG"); + state->u.f4.reg.fs_dctl = cm_object_get_child_by_name(obj, "FS_DCTL"); + state->u.f4.reg.fs_dsts = cm_object_get_child_by_name(obj, "FS_DSTS"); + state->u.f4.reg.fs_diepmsk = cm_object_get_child_by_name(obj, "FS_DIEPMSK"); + state->u.f4.reg.fs_doepmsk = cm_object_get_child_by_name(obj, "FS_DOEPMSK"); + state->u.f4.reg.fs_daint = cm_object_get_child_by_name(obj, "FS_DAINT"); + state->u.f4.reg.fs_daintmsk = cm_object_get_child_by_name(obj, "FS_DAINTMSK"); + state->u.f4.reg.dvbusdis = cm_object_get_child_by_name(obj, "DVBUSDIS"); + state->u.f4.reg.dvbuspulse = cm_object_get_child_by_name(obj, "DVBUSPULSE"); + state->u.f4.reg.diepempmsk = cm_object_get_child_by_name(obj, "DIEPEMPMSK"); + state->u.f4.reg.fs_diepctl0 = cm_object_get_child_by_name(obj, "FS_DIEPCTL0"); + state->u.f4.reg.diepctl1 = cm_object_get_child_by_name(obj, "DIEPCTL1"); + state->u.f4.reg.diepctl2 = cm_object_get_child_by_name(obj, "DIEPCTL2"); + state->u.f4.reg.diepctl3 = cm_object_get_child_by_name(obj, "DIEPCTL3"); + state->u.f4.reg.doepctl0 = cm_object_get_child_by_name(obj, "DOEPCTL0"); + state->u.f4.reg.doepctl1 = cm_object_get_child_by_name(obj, "DOEPCTL1"); + state->u.f4.reg.doepctl2 = cm_object_get_child_by_name(obj, "DOEPCTL2"); + state->u.f4.reg.doepctl3 = cm_object_get_child_by_name(obj, "DOEPCTL3"); + state->u.f4.reg.diepint0 = cm_object_get_child_by_name(obj, "DIEPINT0"); + state->u.f4.reg.diepint1 = cm_object_get_child_by_name(obj, "DIEPINT1"); + state->u.f4.reg.diepint2 = cm_object_get_child_by_name(obj, "DIEPINT2"); + state->u.f4.reg.diepint3 = cm_object_get_child_by_name(obj, "DIEPINT3"); + state->u.f4.reg.doepint0 = cm_object_get_child_by_name(obj, "DOEPINT0"); + state->u.f4.reg.doepint1 = cm_object_get_child_by_name(obj, "DOEPINT1"); + state->u.f4.reg.doepint2 = cm_object_get_child_by_name(obj, "DOEPINT2"); + state->u.f4.reg.doepint3 = cm_object_get_child_by_name(obj, "DOEPINT3"); + state->u.f4.reg.dieptsiz0 = cm_object_get_child_by_name(obj, "DIEPTSIZ0"); + state->u.f4.reg.doeptsiz0 = cm_object_get_child_by_name(obj, "DOEPTSIZ0"); + state->u.f4.reg.dieptsiz1 = cm_object_get_child_by_name(obj, "DIEPTSIZ1"); + state->u.f4.reg.dieptsiz2 = cm_object_get_child_by_name(obj, "DIEPTSIZ2"); + state->u.f4.reg.dieptsiz3 = cm_object_get_child_by_name(obj, "DIEPTSIZ3"); + state->u.f4.reg.dtxfsts0 = cm_object_get_child_by_name(obj, "DTXFSTS0"); + state->u.f4.reg.dtxfsts1 = cm_object_get_child_by_name(obj, "DTXFSTS1"); + state->u.f4.reg.dtxfsts2 = cm_object_get_child_by_name(obj, "DTXFSTS2"); + state->u.f4.reg.dtxfsts3 = cm_object_get_child_by_name(obj, "DTXFSTS3"); + state->u.f4.reg.doeptsiz1 = cm_object_get_child_by_name(obj, "DOEPTSIZ1"); + state->u.f4.reg.doeptsiz2 = cm_object_get_child_by_name(obj, "DOEPTSIZ2"); + state->u.f4.reg.doeptsiz3 = cm_object_get_child_by_name(obj, "DOEPTSIZ3"); + + + // FS_DCFG bitfields. + state->u.f4.fld.fs_dcfg.dspd = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "DSPD"); + state->u.f4.fld.fs_dcfg.nzlsohsk = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "NZLSOHSK"); + state->u.f4.fld.fs_dcfg.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "DAD"); + state->u.f4.fld.fs_dcfg.pfivl = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "PFIVL"); + + // FS_DCTL bitfields. + state->u.f4.fld.fs_dctl.rwusig = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "RWUSIG"); + state->u.f4.fld.fs_dctl.sdis = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SDIS"); + state->u.f4.fld.fs_dctl.ginsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "GINSTS"); + state->u.f4.fld.fs_dctl.gonsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "GONSTS"); + state->u.f4.fld.fs_dctl.tctl = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "TCTL"); + state->u.f4.fld.fs_dctl.sginak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SGINAK"); + state->u.f4.fld.fs_dctl.cginak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "CGINAK"); + state->u.f4.fld.fs_dctl.sgonak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SGONAK"); + state->u.f4.fld.fs_dctl.cgonak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "CGONAK"); + state->u.f4.fld.fs_dctl.poprgdne = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "POPRGDNE"); + + // FS_DSTS bitfields. + state->u.f4.fld.fs_dsts.suspsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "SUSPSTS"); + state->u.f4.fld.fs_dsts.enumspd = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "ENUMSPD"); + state->u.f4.fld.fs_dsts.eerr = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "EERR"); + state->u.f4.fld.fs_dsts.fnsof = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "FNSOF"); + + // FS_DIEPMSK bitfields. + state->u.f4.fld.fs_diepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "XFRCM"); + state->u.f4.fld.fs_diepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "EPDM"); + state->u.f4.fld.fs_diepmsk.tom = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "TOM"); + state->u.f4.fld.fs_diepmsk.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "ITTXFEMSK"); + state->u.f4.fld.fs_diepmsk.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "INEPNMM"); + state->u.f4.fld.fs_diepmsk.inepnem = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "INEPNEM"); + + // FS_DOEPMSK bitfields. + state->u.f4.fld.fs_doepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "XFRCM"); + state->u.f4.fld.fs_doepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "EPDM"); + state->u.f4.fld.fs_doepmsk.stupm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "STUPM"); + state->u.f4.fld.fs_doepmsk.otepdm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "OTEPDM"); + + // FS_DAINT bitfields. + state->u.f4.fld.fs_daint.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daint, "IEPINT"); + state->u.f4.fld.fs_daint.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daint, "OEPINT"); + + // FS_DAINTMSK bitfields. + state->u.f4.fld.fs_daintmsk.iepm = cm_object_get_child_by_name(state->u.f4.reg.fs_daintmsk, "IEPM"); + state->u.f4.fld.fs_daintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daintmsk, "OEPINT"); + + // DVBUSDIS bitfields. + state->u.f4.fld.dvbusdis.vbusdt = cm_object_get_child_by_name(state->u.f4.reg.dvbusdis, "VBUSDT"); + + // DVBUSPULSE bitfields. + state->u.f4.fld.dvbuspulse.dvbusp = cm_object_get_child_by_name(state->u.f4.reg.dvbuspulse, "DVBUSP"); + + // DIEPEMPMSK bitfields. + state->u.f4.fld.diepempmsk.ineptxfem = cm_object_get_child_by_name(state->u.f4.reg.diepempmsk, "INEPTXFEM"); + + // FS_DIEPCTL0 bitfields. + state->u.f4.fld.fs_diepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "MPSIZ"); + state->u.f4.fld.fs_diepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "USBAEP"); + state->u.f4.fld.fs_diepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "NAKSTS"); + state->u.f4.fld.fs_diepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPTYP"); + state->u.f4.fld.fs_diepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "STALL"); + state->u.f4.fld.fs_diepctl0.txfnum = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "TXFNUM"); + state->u.f4.fld.fs_diepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "CNAK"); + state->u.f4.fld.fs_diepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "SNAK"); + state->u.f4.fld.fs_diepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPDIS"); + state->u.f4.fld.fs_diepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPENA"); + + // DIEPCTL1 bitfields. + state->u.f4.fld.diepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "MPSIZ"); + state->u.f4.fld.diepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "USBAEP"); + state->u.f4.fld.diepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EONUM_DPID"); + state->u.f4.fld.diepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "NAKSTS"); + state->u.f4.fld.diepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPTYP"); + state->u.f4.fld.diepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "Stall"); + state->u.f4.fld.diepctl1.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "TXFNUM"); + state->u.f4.fld.diepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "CNAK"); + state->u.f4.fld.diepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SNAK"); + state->u.f4.fld.diepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl1.soddfrm_sd1pid = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SODDFRM_SD1PID"); + state->u.f4.fld.diepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPDIS"); + state->u.f4.fld.diepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPENA"); + + // DIEPCTL2 bitfields. + state->u.f4.fld.diepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "MPSIZ"); + state->u.f4.fld.diepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "USBAEP"); + state->u.f4.fld.diepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EONUM_DPID"); + state->u.f4.fld.diepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "NAKSTS"); + state->u.f4.fld.diepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPTYP"); + state->u.f4.fld.diepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "Stall"); + state->u.f4.fld.diepctl2.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "TXFNUM"); + state->u.f4.fld.diepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "CNAK"); + state->u.f4.fld.diepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SNAK"); + state->u.f4.fld.diepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SODDFRM"); + state->u.f4.fld.diepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPDIS"); + state->u.f4.fld.diepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPENA"); + + // DIEPCTL3 bitfields. + state->u.f4.fld.diepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "MPSIZ"); + state->u.f4.fld.diepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "USBAEP"); + state->u.f4.fld.diepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EONUM_DPID"); + state->u.f4.fld.diepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "NAKSTS"); + state->u.f4.fld.diepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPTYP"); + state->u.f4.fld.diepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "Stall"); + state->u.f4.fld.diepctl3.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "TXFNUM"); + state->u.f4.fld.diepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "CNAK"); + state->u.f4.fld.diepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SNAK"); + state->u.f4.fld.diepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SODDFRM"); + state->u.f4.fld.diepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPDIS"); + state->u.f4.fld.diepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPENA"); + + // DOEPCTL0 bitfields. + state->u.f4.fld.doepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "MPSIZ"); + state->u.f4.fld.doepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "USBAEP"); + state->u.f4.fld.doepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "NAKSTS"); + state->u.f4.fld.doepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPTYP"); + state->u.f4.fld.doepctl0.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "SNPM"); + state->u.f4.fld.doepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "Stall"); + state->u.f4.fld.doepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "CNAK"); + state->u.f4.fld.doepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "SNAK"); + state->u.f4.fld.doepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPDIS"); + state->u.f4.fld.doepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPENA"); + + // DOEPCTL1 bitfields. + state->u.f4.fld.doepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "MPSIZ"); + state->u.f4.fld.doepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "USBAEP"); + state->u.f4.fld.doepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EONUM_DPID"); + state->u.f4.fld.doepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "NAKSTS"); + state->u.f4.fld.doepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPTYP"); + state->u.f4.fld.doepctl1.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SNPM"); + state->u.f4.fld.doepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "Stall"); + state->u.f4.fld.doepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "CNAK"); + state->u.f4.fld.doepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SNAK"); + state->u.f4.fld.doepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl1.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SODDFRM"); + state->u.f4.fld.doepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPDIS"); + state->u.f4.fld.doepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPENA"); + + // DOEPCTL2 bitfields. + state->u.f4.fld.doepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "MPSIZ"); + state->u.f4.fld.doepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "USBAEP"); + state->u.f4.fld.doepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EONUM_DPID"); + state->u.f4.fld.doepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "NAKSTS"); + state->u.f4.fld.doepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPTYP"); + state->u.f4.fld.doepctl2.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SNPM"); + state->u.f4.fld.doepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "Stall"); + state->u.f4.fld.doepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "CNAK"); + state->u.f4.fld.doepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SNAK"); + state->u.f4.fld.doepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SODDFRM"); + state->u.f4.fld.doepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPDIS"); + state->u.f4.fld.doepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPENA"); + + // DOEPCTL3 bitfields. + state->u.f4.fld.doepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "MPSIZ"); + state->u.f4.fld.doepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "USBAEP"); + state->u.f4.fld.doepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EONUM_DPID"); + state->u.f4.fld.doepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "NAKSTS"); + state->u.f4.fld.doepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPTYP"); + state->u.f4.fld.doepctl3.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SNPM"); + state->u.f4.fld.doepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "Stall"); + state->u.f4.fld.doepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "CNAK"); + state->u.f4.fld.doepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SNAK"); + state->u.f4.fld.doepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SODDFRM"); + state->u.f4.fld.doepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPDIS"); + state->u.f4.fld.doepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPENA"); + + // DIEPINT0 bitfields. + state->u.f4.fld.diepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "XFRC"); + state->u.f4.fld.diepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "EPDISD"); + state->u.f4.fld.diepint0.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "TOC"); + state->u.f4.fld.diepint0.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "ITTXFE"); + state->u.f4.fld.diepint0.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "INEPNE"); + state->u.f4.fld.diepint0.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "TXFE"); + + // DIEPINT1 bitfields. + state->u.f4.fld.diepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "XFRC"); + state->u.f4.fld.diepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "EPDISD"); + state->u.f4.fld.diepint1.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "TOC"); + state->u.f4.fld.diepint1.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "ITTXFE"); + state->u.f4.fld.diepint1.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "INEPNE"); + state->u.f4.fld.diepint1.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "TXFE"); + + // DIEPINT2 bitfields. + state->u.f4.fld.diepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "XFRC"); + state->u.f4.fld.diepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "EPDISD"); + state->u.f4.fld.diepint2.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "TOC"); + state->u.f4.fld.diepint2.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "ITTXFE"); + state->u.f4.fld.diepint2.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "INEPNE"); + state->u.f4.fld.diepint2.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "TXFE"); + + // DIEPINT3 bitfields. + state->u.f4.fld.diepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "XFRC"); + state->u.f4.fld.diepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "EPDISD"); + state->u.f4.fld.diepint3.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "TOC"); + state->u.f4.fld.diepint3.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "ITTXFE"); + state->u.f4.fld.diepint3.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "INEPNE"); + state->u.f4.fld.diepint3.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "TXFE"); + + // DOEPINT0 bitfields. + state->u.f4.fld.doepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "XFRC"); + state->u.f4.fld.doepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "EPDISD"); + state->u.f4.fld.doepint0.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "STUP"); + state->u.f4.fld.doepint0.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "OTEPDIS"); + state->u.f4.fld.doepint0.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "B2BSTUP"); + + // DOEPINT1 bitfields. + state->u.f4.fld.doepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "XFRC"); + state->u.f4.fld.doepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "EPDISD"); + state->u.f4.fld.doepint1.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "STUP"); + state->u.f4.fld.doepint1.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "OTEPDIS"); + state->u.f4.fld.doepint1.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "B2BSTUP"); + + // DOEPINT2 bitfields. + state->u.f4.fld.doepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "XFRC"); + state->u.f4.fld.doepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "EPDISD"); + state->u.f4.fld.doepint2.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "STUP"); + state->u.f4.fld.doepint2.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "OTEPDIS"); + state->u.f4.fld.doepint2.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "B2BSTUP"); + + // DOEPINT3 bitfields. + state->u.f4.fld.doepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "XFRC"); + state->u.f4.fld.doepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "EPDISD"); + state->u.f4.fld.doepint3.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "STUP"); + state->u.f4.fld.doepint3.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "OTEPDIS"); + state->u.f4.fld.doepint3.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "B2BSTUP"); + + // DIEPTSIZ0 bitfields. + state->u.f4.fld.dieptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz0, "XFRSIZ"); + state->u.f4.fld.dieptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz0, "PKTCNT"); + + // DOEPTSIZ0 bitfields. + state->u.f4.fld.doeptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "XFRSIZ"); + state->u.f4.fld.doeptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "PKTCNT"); + state->u.f4.fld.doeptsiz0.stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "STUPCNT"); + + // DIEPTSIZ1 bitfields. + state->u.f4.fld.dieptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "XFRSIZ"); + state->u.f4.fld.dieptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "PKTCNT"); + state->u.f4.fld.dieptsiz1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "MCNT"); + + // DIEPTSIZ2 bitfields. + state->u.f4.fld.dieptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "XFRSIZ"); + state->u.f4.fld.dieptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "PKTCNT"); + state->u.f4.fld.dieptsiz2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "MCNT"); + + // DIEPTSIZ3 bitfields. + state->u.f4.fld.dieptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "XFRSIZ"); + state->u.f4.fld.dieptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "PKTCNT"); + state->u.f4.fld.dieptsiz3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "MCNT"); + + // DTXFSTS0 bitfields. + state->u.f4.fld.dtxfsts0.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts0, "INEPTFSAV"); + + // DTXFSTS1 bitfields. + state->u.f4.fld.dtxfsts1.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts1, "INEPTFSAV"); + + // DTXFSTS2 bitfields. + state->u.f4.fld.dtxfsts2.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts2, "INEPTFSAV"); + + // DTXFSTS3 bitfields. + state->u.f4.fld.dtxfsts3.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts3, "INEPTFSAV"); + + // DOEPTSIZ1 bitfields. + state->u.f4.fld.doeptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "XFRSIZ"); + state->u.f4.fld.doeptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "PKTCNT"); + state->u.f4.fld.doeptsiz1.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "RXDPID_STUPCNT"); + + // DOEPTSIZ2 bitfields. + state->u.f4.fld.doeptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "XFRSIZ"); + state->u.f4.fld.doeptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "PKTCNT"); + state->u.f4.fld.doeptsiz2.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "RXDPID_STUPCNT"); + + // DOEPTSIZ3 bitfields. + state->u.f4.fld.doeptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "XFRSIZ"); + state->u.f4.fld.doeptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "PKTCNT"); + state->u.f4.fld.doeptsiz3.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "RXDPID_STUPCNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_device_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_device_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_device_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_device_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_device_is_enabled(Object *obj) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_device_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_device_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_DEVICE)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_DEVICE"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_otg_fs_device_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_DEVICEEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_device_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_DEVICE); +} + +static void stm32_otg_fs_device_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_device_reset_callback; + dc->realize = stm32_otg_fs_device_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_device_is_enabled; +} + +static const TypeInfo stm32_otg_fs_device_type_info = { + .name = TYPE_STM32_OTG_FS_DEVICE, + .parent = TYPE_STM32_OTG_FS_DEVICE_PARENT, + .instance_init = stm32_otg_fs_device_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_DEVICEState), + .class_init = stm32_otg_fs_device_class_init_callback, + .class_size = sizeof(STM32OTG_FS_DEVICEClass) }; + +static void stm32_otg_fs_device_register_types(void) +{ + type_register_static(&stm32_otg_fs_device_type_info); +} + +type_init(stm32_otg_fs_device_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_device.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_device.h new file mode 100644 index 0000000000..42475e75f6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_device.h @@ -0,0 +1,493 @@ +/* + * STM32 - OTG_FS_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_DEVICE_H_ +#define STM32_OTG_FS_DEVICE_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_DEVICE DEVICE_PATH_STM32 "OTG_FS_DEVICE" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_DEVICE TYPE_STM32_PREFIX "otg_fs_device" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_DEVICE_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_DEVICEParentClass; +typedef PeripheralState STM32OTG_FS_DEVICEParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_DEVICEClass, (obj), TYPE_STM32_OTG_FS_DEVICE) +#define STM32_OTG_FS_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_DEVICEClass, (klass), TYPE_STM32_OTG_FS_DEVICE) + +typedef struct { + // private: + STM32OTG_FS_DEVICEParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_DEVICEClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_DEVICE_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_DEVICEState, (obj), TYPE_STM32_OTG_FS_DEVICE) + +typedef struct { + // private: + STM32OTG_FS_DEVICEParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_DEVICE (USB on the go full speed) registers. + struct { + Object *fs_dcfg; // 0x0 (OTG_FS device configuration register (OTG_FS_DCFG)) + Object *fs_dctl; // 0x4 (OTG_FS device control register (OTG_FS_DCTL)) + Object *fs_dsts; // 0x8 (OTG_FS device status register (OTG_FS_DSTS)) + Object *fs_diepmsk; // 0x10 (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) + Object *fs_doepmsk; // 0x14 (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) + Object *fs_daint; // 0x18 (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) + Object *fs_daintmsk; // 0x1C (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) + Object *dvbusdis; // 0x28 (OTG_FS device VBUS discharge time register) + Object *dvbuspulse; // 0x2C (OTG_FS device VBUS pulsing time register) + Object *diepempmsk; // 0x34 (OTG_FS device IN endpoint FIFO empty interrupt mask register) + Object *fs_diepctl0; // 0x100 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) + Object *diepctl1; // 0x120 (OTG device endpoint-1 control register) + Object *diepctl2; // 0x140 (OTG device endpoint-2 control register) + Object *diepctl3; // 0x160 (OTG device endpoint-3 control register) + Object *doepctl0; // 0x300 (Device endpoint-0 control register) + Object *doepctl1; // 0x320 (Device endpoint-1 control register) + Object *doepctl2; // 0x340 (Device endpoint-2 control register) + Object *doepctl3; // 0x360 (Device endpoint-3 control register) + Object *diepint0; // 0x108 (Device endpoint-x interrupt register) + Object *diepint1; // 0x128 (Device endpoint-1 interrupt register) + Object *diepint2; // 0x148 (Device endpoint-2 interrupt register) + Object *diepint3; // 0x168 (Device endpoint-3 interrupt register) + Object *doepint0; // 0x308 (Device endpoint-0 interrupt register) + Object *doepint1; // 0x328 (Device endpoint-1 interrupt register) + Object *doepint2; // 0x348 (Device endpoint-2 interrupt register) + Object *doepint3; // 0x368 (Device endpoint-3 interrupt register) + Object *dieptsiz0; // 0x110 (Device endpoint-0 transfer size register) + Object *doeptsiz0; // 0x310 (Device OUT endpoint-0 transfer size register) + Object *dieptsiz1; // 0x130 (Device endpoint-1 transfer size register) + Object *dieptsiz2; // 0x150 (Device endpoint-2 transfer size register) + Object *dieptsiz3; // 0x170 (Device endpoint-3 transfer size register) + Object *dtxfsts0; // 0x118 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts1; // 0x138 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts2; // 0x158 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts3; // 0x178 (OTG_FS device IN endpoint transmit FIFO status register) + Object *doeptsiz1; // 0x330 (Device OUT endpoint-1 transfer size register) + Object *doeptsiz2; // 0x350 (Device OUT endpoint-2 transfer size register) + Object *doeptsiz3; // 0x370 (Device OUT endpoint-3 transfer size register) + } reg; + + struct { + + // FS_DCFG (OTG_FS device configuration register (OTG_FS_DCFG)) bitfields. + struct { + Object *dspd; // [0:1] Device speed + Object *nzlsohsk; // [2:2] Non-zero-length status OUT handshake + Object *dad; // [4:10] Device address + Object *pfivl; // [11:12] Periodic frame interval + } fs_dcfg; + + // FS_DCTL (OTG_FS device control register (OTG_FS_DCTL)) bitfields. + struct { + Object *rwusig; // [0:0] Remote wakeup signaling + Object *sdis; // [1:1] Soft disconnect + Object *ginsts; // [2:2] Global IN NAK status + Object *gonsts; // [3:3] Global OUT NAK status + Object *tctl; // [4:6] Test control + Object *sginak; // [7:7] Set global IN NAK + Object *cginak; // [8:8] Clear global IN NAK + Object *sgonak; // [9:9] Set global OUT NAK + Object *cgonak; // [10:10] Clear global OUT NAK + Object *poprgdne; // [11:11] Power-on programming done + } fs_dctl; + + // FS_DSTS (OTG_FS device status register (OTG_FS_DSTS)) bitfields. + struct { + Object *suspsts; // [0:0] Suspend status + Object *enumspd; // [1:2] Enumerated speed + Object *eerr; // [3:3] Erratic error + Object *fnsof; // [8:21] Frame number of the received SOF + } fs_dsts; + + // FS_DIEPMSK (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (Non-isochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + } fs_diepmsk; + + // FS_DOEPMSK (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *stupm; // [3:3] SETUP phase done mask + Object *otepdm; // [4:4] OUT token received when endpoint disabled mask + } fs_doepmsk; + + // FS_DAINT (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) bitfields. + struct { + Object *iepint; // [0:15] IN endpoint interrupt bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daint; + + // FS_DAINTMSK (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) bitfields. + struct { + Object *iepm; // [0:15] IN EP interrupt mask bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daintmsk; + + // DVBUSDIS (OTG_FS device VBUS discharge time register) bitfields. + struct { + Object *vbusdt; // [0:15] Device VBUS discharge time + } dvbusdis; + + // DVBUSPULSE (OTG_FS device VBUS pulsing time register) bitfields. + struct { + Object *dvbusp; // [0:11] Device VBUS pulsing time + } dvbuspulse; + + // DIEPEMPMSK (OTG_FS device IN endpoint FIFO empty interrupt mask register) bitfields. + struct { + Object *ineptxfem; // [0:15] IN EP Tx FIFO empty interrupt mask bits + } diepempmsk; + + // FS_DIEPCTL0 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) bitfields. + struct { + Object *mpsiz; // [0:1] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } fs_diepctl0; + + // DIEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm_sd1pid; // [29:29] SODDFRM/SD1PID + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl1; + + // DIEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl2; + + // DIEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl3; + + // DOEPCTL0 (Device endpoint-0 control register) bitfields. + struct { + Object *mpsiz; // [0:1] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl0; + + // DOEPCTL1 (Device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl1; + + // DOEPCTL2 (Device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl2; + + // DOEPCTL3 (Device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl3; + + // DIEPINT0 (Device endpoint-x interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint0; + + // DIEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint1; + + // DIEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint2; + + // DIEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint3; + + // DOEPINT0 (Device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint0; + + // DOEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint1; + + // DOEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint2; + + // DOEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint3; + + // DIEPTSIZ0 (Device endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:20] Packet count + } dieptsiz0; + + // DOEPTSIZ0 (Device OUT endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:19] Packet count + Object *stupcnt; // [29:30] SETUP packet count + } doeptsiz0; + + // DIEPTSIZ1 (Device endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz1; + + // DIEPTSIZ2 (Device endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz2; + + // DIEPTSIZ3 (Device endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz3; + + // DTXFSTS0 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts0; + + // DTXFSTS1 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts1; + + // DTXFSTS2 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts2; + + // DTXFSTS3 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts3; + + // DOEPTSIZ1 (Device OUT endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz1; + + // DOEPTSIZ2 (Device OUT endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz2; + + // DOEPTSIZ3 (Device OUT endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_DEVICEState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_DEVICE_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_global.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_global.c new file mode 100644 index 0000000000..4ffb364323 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_global.c @@ -0,0 +1,406 @@ +/* + * STM32 - OTG_FS_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_otg_fs_global_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_gotgctl = cm_object_get_child_by_name(obj, "FS_GOTGCTL"); + state->u.f4.reg.fs_gotgint = cm_object_get_child_by_name(obj, "FS_GOTGINT"); + state->u.f4.reg.fs_gahbcfg = cm_object_get_child_by_name(obj, "FS_GAHBCFG"); + state->u.f4.reg.fs_gusbcfg = cm_object_get_child_by_name(obj, "FS_GUSBCFG"); + state->u.f4.reg.fs_grstctl = cm_object_get_child_by_name(obj, "FS_GRSTCTL"); + state->u.f4.reg.fs_gintsts = cm_object_get_child_by_name(obj, "FS_GINTSTS"); + state->u.f4.reg.fs_gintmsk = cm_object_get_child_by_name(obj, "FS_GINTMSK"); + state->u.f4.reg.fs_grxstsr_device = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Device"); + state->u.f4.reg.fs_grxstsr_host = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Host"); + state->u.f4.reg.fs_grxfsiz = cm_object_get_child_by_name(obj, "FS_GRXFSIZ"); + state->u.f4.reg.fs_gnptxfsiz_device = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Device"); + state->u.f4.reg.fs_gnptxfsiz_host = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Host"); + state->u.f4.reg.fs_gnptxsts = cm_object_get_child_by_name(obj, "FS_GNPTXSTS"); + state->u.f4.reg.fs_gccfg = cm_object_get_child_by_name(obj, "FS_GCCFG"); + state->u.f4.reg.fs_cid = cm_object_get_child_by_name(obj, "FS_CID"); + state->u.f4.reg.fs_hptxfsiz = cm_object_get_child_by_name(obj, "FS_HPTXFSIZ"); + state->u.f4.reg.fs_dieptxf1 = cm_object_get_child_by_name(obj, "FS_DIEPTXF1"); + state->u.f4.reg.fs_dieptxf2 = cm_object_get_child_by_name(obj, "FS_DIEPTXF2"); + state->u.f4.reg.fs_dieptxf3 = cm_object_get_child_by_name(obj, "FS_DIEPTXF3"); + + + // FS_GOTGCTL bitfields. + state->u.f4.fld.fs_gotgctl.srqscs = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "SRQSCS"); + state->u.f4.fld.fs_gotgctl.srq = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "SRQ"); + state->u.f4.fld.fs_gotgctl.hngscs = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HNGSCS"); + state->u.f4.fld.fs_gotgctl.hnprq = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HNPRQ"); + state->u.f4.fld.fs_gotgctl.hshnpen = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HSHNPEN"); + state->u.f4.fld.fs_gotgctl.dhnpen = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "DHNPEN"); + state->u.f4.fld.fs_gotgctl.cidsts = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "CIDSTS"); + state->u.f4.fld.fs_gotgctl.dbct = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "DBCT"); + state->u.f4.fld.fs_gotgctl.asvld = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "ASVLD"); + state->u.f4.fld.fs_gotgctl.bsvld = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "BSVLD"); + + // FS_GOTGINT bitfields. + state->u.f4.fld.fs_gotgint.sedet = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "SEDET"); + state->u.f4.fld.fs_gotgint.srsschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "SRSSCHG"); + state->u.f4.fld.fs_gotgint.hnsschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "HNSSCHG"); + state->u.f4.fld.fs_gotgint.hngdet = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "HNGDET"); + state->u.f4.fld.fs_gotgint.adtochg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "ADTOCHG"); + state->u.f4.fld.fs_gotgint.dbcdne = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "DBCDNE"); + + // FS_GAHBCFG bitfields. + state->u.f4.fld.fs_gahbcfg.gint = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "GINT"); + state->u.f4.fld.fs_gahbcfg.txfelvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "TXFELVL"); + state->u.f4.fld.fs_gahbcfg.ptxfelvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "PTXFELVL"); + + // FS_GUSBCFG bitfields. + state->u.f4.fld.fs_gusbcfg.tocal = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "TOCAL"); + state->u.f4.fld.fs_gusbcfg.physel = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "PHYSEL"); + state->u.f4.fld.fs_gusbcfg.srpcap = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "SRPCAP"); + state->u.f4.fld.fs_gusbcfg.hnpcap = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "HNPCAP"); + state->u.f4.fld.fs_gusbcfg.trdt = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "TRDT"); + state->u.f4.fld.fs_gusbcfg.fhmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "FHMOD"); + state->u.f4.fld.fs_gusbcfg.fdmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "FDMOD"); + state->u.f4.fld.fs_gusbcfg.ctxpkt = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "CTXPKT"); + + // FS_GRSTCTL bitfields. + state->u.f4.fld.fs_grstctl.csrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "CSRST"); + state->u.f4.fld.fs_grstctl.hsrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "HSRST"); + state->u.f4.fld.fs_grstctl.fcrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "FCRST"); + state->u.f4.fld.fs_grstctl.rxfflsh = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "RXFFLSH"); + state->u.f4.fld.fs_grstctl.txfflsh = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "TXFFLSH"); + state->u.f4.fld.fs_grstctl.txfnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "TXFNUM"); + state->u.f4.fld.fs_grstctl.ahbidl = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "AHBIDL"); + + // FS_GINTSTS bitfields. + state->u.f4.fld.fs_gintsts.cmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "CMOD"); + state->u.f4.fld.fs_gintsts.mmis = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "MMIS"); + state->u.f4.fld.fs_gintsts.otgint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "OTGINT"); + state->u.f4.fld.fs_gintsts.sof = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "SOF"); + state->u.f4.fld.fs_gintsts.rxflvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "RXFLVL"); + state->u.f4.fld.fs_gintsts.nptxfe = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "NPTXFE"); + state->u.f4.fld.fs_gintsts.ginakeff = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "GINAKEFF"); + state->u.f4.fld.fs_gintsts.goutnakeff = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "GOUTNAKEFF"); + state->u.f4.fld.fs_gintsts.esusp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ESUSP"); + state->u.f4.fld.fs_gintsts.usbsusp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "USBSUSP"); + state->u.f4.fld.fs_gintsts.usbrst = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "USBRST"); + state->u.f4.fld.fs_gintsts.enumdne = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ENUMDNE"); + state->u.f4.fld.fs_gintsts.isoodrp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ISOODRP"); + state->u.f4.fld.fs_gintsts.eopf = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "EOPF"); + state->u.f4.fld.fs_gintsts.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IEPINT"); + state->u.f4.fld.fs_gintsts.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "OEPINT"); + state->u.f4.fld.fs_gintsts.iisoixfr = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IISOIXFR"); + state->u.f4.fld.fs_gintsts.ipxfr_incompisoout = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IPXFR_INCOMPISOOUT"); + state->u.f4.fld.fs_gintsts.hprtint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "HPRTINT"); + state->u.f4.fld.fs_gintsts.hcint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "HCINT"); + state->u.f4.fld.fs_gintsts.ptxfe = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "PTXFE"); + state->u.f4.fld.fs_gintsts.cidschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "CIDSCHG"); + state->u.f4.fld.fs_gintsts.discint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "DISCINT"); + state->u.f4.fld.fs_gintsts.srqint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "SRQINT"); + state->u.f4.fld.fs_gintsts.wkupint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "WKUPINT"); + + // FS_GINTMSK bitfields. + state->u.f4.fld.fs_gintmsk.mmism = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "MMISM"); + state->u.f4.fld.fs_gintmsk.otgint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "OTGINT"); + state->u.f4.fld.fs_gintmsk.sofm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "SOFM"); + state->u.f4.fld.fs_gintmsk.rxflvlm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "RXFLVLM"); + state->u.f4.fld.fs_gintmsk.nptxfem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "NPTXFEM"); + state->u.f4.fld.fs_gintmsk.ginakeffm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "GINAKEFFM"); + state->u.f4.fld.fs_gintmsk.gonakeffm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "GONAKEFFM"); + state->u.f4.fld.fs_gintmsk.esuspm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ESUSPM"); + state->u.f4.fld.fs_gintmsk.usbsuspm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "USBSUSPM"); + state->u.f4.fld.fs_gintmsk.usbrst = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "USBRST"); + state->u.f4.fld.fs_gintmsk.enumdnem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ENUMDNEM"); + state->u.f4.fld.fs_gintmsk.isoodrpm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ISOODRPM"); + state->u.f4.fld.fs_gintmsk.eopfm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "EOPFM"); + state->u.f4.fld.fs_gintmsk.epmism = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "EPMISM"); + state->u.f4.fld.fs_gintmsk.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IEPINT"); + state->u.f4.fld.fs_gintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "OEPINT"); + state->u.f4.fld.fs_gintmsk.iisoixfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IISOIXFRM"); + state->u.f4.fld.fs_gintmsk.ipxfrm_iisooxfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IPXFRM_IISOOXFRM"); + state->u.f4.fld.fs_gintmsk.prtim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "PRTIM"); + state->u.f4.fld.fs_gintmsk.hcim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "HCIM"); + state->u.f4.fld.fs_gintmsk.ptxfem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "PTXFEM"); + state->u.f4.fld.fs_gintmsk.cidschgm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "CIDSCHGM"); + state->u.f4.fld.fs_gintmsk.discint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "DISCINT"); + state->u.f4.fld.fs_gintmsk.srqim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "SRQIM"); + state->u.f4.fld.fs_gintmsk.wuim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "WUIM"); + + // FS_GRXSTSR_Device bitfields. + state->u.f4.fld.fs_grxstsr_device.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "EPNUM"); + state->u.f4.fld.fs_grxstsr_device.bcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "BCNT"); + state->u.f4.fld.fs_grxstsr_device.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "DPID"); + state->u.f4.fld.fs_grxstsr_device.pktsts = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "PKTSTS"); + state->u.f4.fld.fs_grxstsr_device.frmnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "FRMNUM"); + + // FS_GRXSTSR_Host bitfields. + state->u.f4.fld.fs_grxstsr_host.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "EPNUM"); + state->u.f4.fld.fs_grxstsr_host.bcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "BCNT"); + state->u.f4.fld.fs_grxstsr_host.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "DPID"); + state->u.f4.fld.fs_grxstsr_host.pktsts = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "PKTSTS"); + state->u.f4.fld.fs_grxstsr_host.frmnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "FRMNUM"); + + // FS_GRXFSIZ bitfields. + state->u.f4.fld.fs_grxfsiz.rxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_grxfsiz, "RXFD"); + + // FS_GNPTXFSIZ_Device bitfields. + state->u.f4.fld.fs_gnptxfsiz_device.tx0fsa = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_device, "TX0FSA"); + state->u.f4.fld.fs_gnptxfsiz_device.tx0fd = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_device, "TX0FD"); + + // FS_GNPTXFSIZ_Host bitfields. + state->u.f4.fld.fs_gnptxfsiz_host.nptxfsa = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_host, "NPTXFSA"); + state->u.f4.fld.fs_gnptxfsiz_host.nptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_host, "NPTXFD"); + + // FS_GNPTXSTS bitfields. + state->u.f4.fld.fs_gnptxsts.nptxfsav = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTXFSAV"); + state->u.f4.fld.fs_gnptxsts.nptqxsav = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTQXSAV"); + state->u.f4.fld.fs_gnptxsts.nptxqtop = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTXQTOP"); + + // FS_GCCFG bitfields. + state->u.f4.fld.fs_gccfg.pwrdwn = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "PWRDWN"); + state->u.f4.fld.fs_gccfg.vbusasen = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "VBUSASEN"); + state->u.f4.fld.fs_gccfg.vbusbsen = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "VBUSBSEN"); + state->u.f4.fld.fs_gccfg.sofouten = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "SOFOUTEN"); + + // FS_CID bitfields. + state->u.f4.fld.fs_cid.product_id = cm_object_get_child_by_name(state->u.f4.reg.fs_cid, "PRODUCT_ID"); + + // FS_HPTXFSIZ bitfields. + state->u.f4.fld.fs_hptxfsiz.ptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxfsiz, "PTXSA"); + state->u.f4.fld.fs_hptxfsiz.ptxfsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxfsiz, "PTXFSIZ"); + + // FS_DIEPTXF1 bitfields. + state->u.f4.fld.fs_dieptxf1.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf1, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf1.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf1, "INEPTXFD"); + + // FS_DIEPTXF2 bitfields. + state->u.f4.fld.fs_dieptxf2.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf2, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf2.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf2, "INEPTXFD"); + + // FS_DIEPTXF3 bitfields. + state->u.f4.fld.fs_dieptxf3.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf3, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf3.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf3, "INEPTXFD"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_global_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_global_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_global_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_global_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_global_is_enabled(Object *obj) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_global_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_global_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_GLOBAL)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_GLOBAL"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_otg_fs_global_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_GLOBALEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_global_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_GLOBAL); +} + +static void stm32_otg_fs_global_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_global_reset_callback; + dc->realize = stm32_otg_fs_global_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_global_is_enabled; +} + +static const TypeInfo stm32_otg_fs_global_type_info = { + .name = TYPE_STM32_OTG_FS_GLOBAL, + .parent = TYPE_STM32_OTG_FS_GLOBAL_PARENT, + .instance_init = stm32_otg_fs_global_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_GLOBALState), + .class_init = stm32_otg_fs_global_class_init_callback, + .class_size = sizeof(STM32OTG_FS_GLOBALClass) }; + +static void stm32_otg_fs_global_register_types(void) +{ + type_register_static(&stm32_otg_fs_global_type_info); +} + +type_init(stm32_otg_fs_global_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_global.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_global.h new file mode 100644 index 0000000000..5dabd26c69 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_global.h @@ -0,0 +1,309 @@ +/* + * STM32 - OTG_FS_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_GLOBAL_H_ +#define STM32_OTG_FS_GLOBAL_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_GLOBAL DEVICE_PATH_STM32 "OTG_FS_GLOBAL" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_GLOBAL TYPE_STM32_PREFIX "otg_fs_global" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_GLOBAL_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_GLOBALParentClass; +typedef PeripheralState STM32OTG_FS_GLOBALParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_GLOBAL_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_GLOBALClass, (obj), TYPE_STM32_OTG_FS_GLOBAL) +#define STM32_OTG_FS_GLOBAL_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_GLOBALClass, (klass), TYPE_STM32_OTG_FS_GLOBAL) + +typedef struct { + // private: + STM32OTG_FS_GLOBALParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_GLOBALClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_GLOBAL_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_GLOBALState, (obj), TYPE_STM32_OTG_FS_GLOBAL) + +typedef struct { + // private: + STM32OTG_FS_GLOBALParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_GLOBAL (USB on the go full speed) registers. + struct { + Object *fs_gotgctl; // 0x0 (OTG_FS control and status register (OTG_FS_GOTGCTL)) + Object *fs_gotgint; // 0x4 (OTG_FS interrupt register (OTG_FS_GOTGINT)) + Object *fs_gahbcfg; // 0x8 (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) + Object *fs_gusbcfg; // 0xC (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) + Object *fs_grstctl; // 0x10 (OTG_FS reset register (OTG_FS_GRSTCTL)) + Object *fs_gintsts; // 0x14 (OTG_FS core interrupt register (OTG_FS_GINTSTS)) + Object *fs_gintmsk; // 0x18 (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) + Object *fs_grxstsr_device; // 0x1C (OTG_FS Receive status debug read(Device mode)) + Object *fs_grxstsr_host; // 0x1C (OTG_FS Receive status debug read(Host mode)) + Object *fs_grxfsiz; // 0x24 (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) + Object *fs_gnptxfsiz_device; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Device mode)) + Object *fs_gnptxfsiz_host; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Host mode)) + Object *fs_gnptxsts; // 0x2C (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) + Object *fs_gccfg; // 0x38 (OTG_FS general core configuration register (OTG_FS_GCCFG)) + Object *fs_cid; // 0x3C (Core ID register) + Object *fs_hptxfsiz; // 0x100 (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) + Object *fs_dieptxf1; // 0x104 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) + Object *fs_dieptxf2; // 0x108 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) + Object *fs_dieptxf3; // 0x10C (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) + } reg; + + struct { + + // FS_GOTGCTL (OTG_FS control and status register (OTG_FS_GOTGCTL)) bitfields. + struct { + Object *srqscs; // [0:0] Session request success + Object *srq; // [1:1] Session request + Object *hngscs; // [8:8] Host negotiation success + Object *hnprq; // [9:9] HNP request + Object *hshnpen; // [10:10] Host set HNP enable + Object *dhnpen; // [11:11] Device HNP enabled + Object *cidsts; // [16:16] Connector ID status + Object *dbct; // [17:17] Long/short debounce time + Object *asvld; // [18:18] A-session valid + Object *bsvld; // [19:19] B-session valid + } fs_gotgctl; + + // FS_GOTGINT (OTG_FS interrupt register (OTG_FS_GOTGINT)) bitfields. + struct { + Object *sedet; // [2:2] Session end detected + Object *srsschg; // [8:8] Session request success status change + Object *hnsschg; // [9:9] Host negotiation success status change + Object *hngdet; // [17:17] Host negotiation detected + Object *adtochg; // [18:18] A-device timeout change + Object *dbcdne; // [19:19] Debounce done + } fs_gotgint; + + // FS_GAHBCFG (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) bitfields. + struct { + Object *gint; // [0:0] Global interrupt mask + Object *txfelvl; // [7:7] TxFIFO empty level + Object *ptxfelvl; // [8:8] Periodic TxFIFO empty level + } fs_gahbcfg; + + // FS_GUSBCFG (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) bitfields. + struct { + Object *tocal; // [0:2] FS timeout calibration + Object *physel; // [6:6] Full Speed serial transceiver select + Object *srpcap; // [8:8] SRP-capable + Object *hnpcap; // [9:9] HNP-capable + Object *trdt; // [10:13] USB turnaround time + Object *fhmod; // [29:29] Force host mode + Object *fdmod; // [30:30] Force device mode + Object *ctxpkt; // [31:31] Corrupt Tx packet + } fs_gusbcfg; + + // FS_GRSTCTL (OTG_FS reset register (OTG_FS_GRSTCTL)) bitfields. + struct { + Object *csrst; // [0:0] Core soft reset + Object *hsrst; // [1:1] HCLK soft reset + Object *fcrst; // [2:2] Host frame counter reset + Object *rxfflsh; // [4:4] RxFIFO flush + Object *txfflsh; // [5:5] TxFIFO flush + Object *txfnum; // [6:10] TxFIFO number + Object *ahbidl; // [31:31] AHB master idle + } fs_grstctl; + + // FS_GINTSTS (OTG_FS core interrupt register (OTG_FS_GINTSTS)) bitfields. + struct { + Object *cmod; // [0:0] Current mode of operation + Object *mmis; // [1:1] Mode mismatch interrupt + Object *otgint; // [2:2] OTG interrupt + Object *sof; // [3:3] Start of frame + Object *rxflvl; // [4:4] RxFIFO non-empty + Object *nptxfe; // [5:5] Non-periodic TxFIFO empty + Object *ginakeff; // [6:6] Global IN non-periodic NAK effective + Object *goutnakeff; // [7:7] Global OUT NAK effective + Object *esusp; // [10:10] Early suspend + Object *usbsusp; // [11:11] USB suspend + Object *usbrst; // [12:12] USB reset + Object *enumdne; // [13:13] Enumeration done + Object *isoodrp; // [14:14] Isochronous OUT packet dropped interrupt + Object *eopf; // [15:15] End of periodic frame interrupt + Object *iepint; // [18:18] IN endpoint interrupt + Object *oepint; // [19:19] OUT endpoint interrupt + Object *iisoixfr; // [20:20] Incomplete isochronous IN transfer + Object *ipxfr_incompisoout; // [21:21] Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + Object *hprtint; // [24:24] Host port interrupt + Object *hcint; // [25:25] Host channels interrupt + Object *ptxfe; // [26:26] Periodic TxFIFO empty + Object *cidschg; // [28:28] Connector ID status change + Object *discint; // [29:29] Disconnect detected interrupt + Object *srqint; // [30:30] Session request/new session detected interrupt + Object *wkupint; // [31:31] Resume/remote wakeup detected interrupt + } fs_gintsts; + + // FS_GINTMSK (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) bitfields. + struct { + Object *mmism; // [1:1] Mode mismatch interrupt mask + Object *otgint; // [2:2] OTG interrupt mask + Object *sofm; // [3:3] Start of frame mask + Object *rxflvlm; // [4:4] Receive FIFO non-empty mask + Object *nptxfem; // [5:5] Non-periodic TxFIFO empty mask + Object *ginakeffm; // [6:6] Global non-periodic IN NAK effective mask + Object *gonakeffm; // [7:7] Global OUT NAK effective mask + Object *esuspm; // [10:10] Early suspend mask + Object *usbsuspm; // [11:11] USB suspend mask + Object *usbrst; // [12:12] USB reset mask + Object *enumdnem; // [13:13] Enumeration done mask + Object *isoodrpm; // [14:14] Isochronous OUT packet dropped interrupt mask + Object *eopfm; // [15:15] End of periodic frame interrupt mask + Object *epmism; // [17:17] Endpoint mismatch interrupt mask + Object *iepint; // [18:18] IN endpoints interrupt mask + Object *oepint; // [19:19] OUT endpoints interrupt mask + Object *iisoixfrm; // [20:20] Incomplete isochronous IN transfer mask + Object *ipxfrm_iisooxfrm; // [21:21] Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + Object *prtim; // [24:24] Host port interrupt mask + Object *hcim; // [25:25] Host channels interrupt mask + Object *ptxfem; // [26:26] Periodic TxFIFO empty mask + Object *cidschgm; // [28:28] Connector ID status change mask + Object *discint; // [29:29] Disconnect detected interrupt mask + Object *srqim; // [30:30] Session request/new session detected interrupt mask + Object *wuim; // [31:31] Resume/remote wakeup detected interrupt mask + } fs_gintmsk; + + // FS_GRXSTSR_Device (OTG_FS Receive status debug read(Device mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_device; + + // FS_GRXSTSR_Host (OTG_FS Receive status debug read(Host mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_host; + + // FS_GRXFSIZ (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) bitfields. + struct { + Object *rxfd; // [0:15] RxFIFO depth + } fs_grxfsiz; + + // FS_GNPTXFSIZ_Device (OTG_FS non-periodic transmit FIFO size register (Device mode)) bitfields. + struct { + Object *tx0fsa; // [0:15] Endpoint 0 transmit RAM start address + Object *tx0fd; // [16:31] Endpoint 0 TxFIFO depth + } fs_gnptxfsiz_device; + + // FS_GNPTXFSIZ_Host (OTG_FS non-periodic transmit FIFO size register (Host mode)) bitfields. + struct { + Object *nptxfsa; // [0:15] Non-periodic transmit RAM start address + Object *nptxfd; // [16:31] Non-periodic TxFIFO depth + } fs_gnptxfsiz_host; + + // FS_GNPTXSTS (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) bitfields. + struct { + Object *nptxfsav; // [0:15] Non-periodic TxFIFO space available + Object *nptqxsav; // [16:23] Non-periodic transmit request queue space available + Object *nptxqtop; // [24:30] Top of the non-periodic transmit request queue + } fs_gnptxsts; + + // FS_GCCFG (OTG_FS general core configuration register (OTG_FS_GCCFG)) bitfields. + struct { + Object *pwrdwn; // [16:16] Power down + Object *vbusasen; // [18:18] Enable the VBUS sensing device + Object *vbusbsen; // [19:19] Enable the VBUS sensing device + Object *sofouten; // [20:20] SOF output enable + } fs_gccfg; + + // FS_CID (Core ID register) bitfields. + struct { + Object *product_id; // [0:31] Product ID field + } fs_cid; + + // FS_HPTXFSIZ (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) bitfields. + struct { + Object *ptxsa; // [0:15] Host periodic TxFIFO start address + Object *ptxfsiz; // [16:31] Host periodic TxFIFO depth + } fs_hptxfsiz; + + // FS_DIEPTXF1 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO2 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf1; + + // FS_DIEPTXF2 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO3 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf2; + + // FS_DIEPTXF3 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO4 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_GLOBALState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_GLOBAL_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_host.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_host.c new file mode 100644 index 0000000000..786e33104a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_host.c @@ -0,0 +1,630 @@ +/* + * STM32 - OTG_FS_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_otg_fs_host_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_hcfg = cm_object_get_child_by_name(obj, "FS_HCFG"); + state->u.f4.reg.hfir = cm_object_get_child_by_name(obj, "HFIR"); + state->u.f4.reg.fs_hfnum = cm_object_get_child_by_name(obj, "FS_HFNUM"); + state->u.f4.reg.fs_hptxsts = cm_object_get_child_by_name(obj, "FS_HPTXSTS"); + state->u.f4.reg.haint = cm_object_get_child_by_name(obj, "HAINT"); + state->u.f4.reg.haintmsk = cm_object_get_child_by_name(obj, "HAINTMSK"); + state->u.f4.reg.fs_hprt = cm_object_get_child_by_name(obj, "FS_HPRT"); + state->u.f4.reg.fs_hcchar0 = cm_object_get_child_by_name(obj, "FS_HCCHAR0"); + state->u.f4.reg.fs_hcchar1 = cm_object_get_child_by_name(obj, "FS_HCCHAR1"); + state->u.f4.reg.fs_hcchar2 = cm_object_get_child_by_name(obj, "FS_HCCHAR2"); + state->u.f4.reg.fs_hcchar3 = cm_object_get_child_by_name(obj, "FS_HCCHAR3"); + state->u.f4.reg.fs_hcchar4 = cm_object_get_child_by_name(obj, "FS_HCCHAR4"); + state->u.f4.reg.fs_hcchar5 = cm_object_get_child_by_name(obj, "FS_HCCHAR5"); + state->u.f4.reg.fs_hcchar6 = cm_object_get_child_by_name(obj, "FS_HCCHAR6"); + state->u.f4.reg.fs_hcchar7 = cm_object_get_child_by_name(obj, "FS_HCCHAR7"); + state->u.f4.reg.fs_hcint0 = cm_object_get_child_by_name(obj, "FS_HCINT0"); + state->u.f4.reg.fs_hcint1 = cm_object_get_child_by_name(obj, "FS_HCINT1"); + state->u.f4.reg.fs_hcint2 = cm_object_get_child_by_name(obj, "FS_HCINT2"); + state->u.f4.reg.fs_hcint3 = cm_object_get_child_by_name(obj, "FS_HCINT3"); + state->u.f4.reg.fs_hcint4 = cm_object_get_child_by_name(obj, "FS_HCINT4"); + state->u.f4.reg.fs_hcint5 = cm_object_get_child_by_name(obj, "FS_HCINT5"); + state->u.f4.reg.fs_hcint6 = cm_object_get_child_by_name(obj, "FS_HCINT6"); + state->u.f4.reg.fs_hcint7 = cm_object_get_child_by_name(obj, "FS_HCINT7"); + state->u.f4.reg.fs_hcintmsk0 = cm_object_get_child_by_name(obj, "FS_HCINTMSK0"); + state->u.f4.reg.fs_hcintmsk1 = cm_object_get_child_by_name(obj, "FS_HCINTMSK1"); + state->u.f4.reg.fs_hcintmsk2 = cm_object_get_child_by_name(obj, "FS_HCINTMSK2"); + state->u.f4.reg.fs_hcintmsk3 = cm_object_get_child_by_name(obj, "FS_HCINTMSK3"); + state->u.f4.reg.fs_hcintmsk4 = cm_object_get_child_by_name(obj, "FS_HCINTMSK4"); + state->u.f4.reg.fs_hcintmsk5 = cm_object_get_child_by_name(obj, "FS_HCINTMSK5"); + state->u.f4.reg.fs_hcintmsk6 = cm_object_get_child_by_name(obj, "FS_HCINTMSK6"); + state->u.f4.reg.fs_hcintmsk7 = cm_object_get_child_by_name(obj, "FS_HCINTMSK7"); + state->u.f4.reg.fs_hctsiz0 = cm_object_get_child_by_name(obj, "FS_HCTSIZ0"); + state->u.f4.reg.fs_hctsiz1 = cm_object_get_child_by_name(obj, "FS_HCTSIZ1"); + state->u.f4.reg.fs_hctsiz2 = cm_object_get_child_by_name(obj, "FS_HCTSIZ2"); + state->u.f4.reg.fs_hctsiz3 = cm_object_get_child_by_name(obj, "FS_HCTSIZ3"); + state->u.f4.reg.fs_hctsiz4 = cm_object_get_child_by_name(obj, "FS_HCTSIZ4"); + state->u.f4.reg.fs_hctsiz5 = cm_object_get_child_by_name(obj, "FS_HCTSIZ5"); + state->u.f4.reg.fs_hctsiz6 = cm_object_get_child_by_name(obj, "FS_HCTSIZ6"); + state->u.f4.reg.fs_hctsiz7 = cm_object_get_child_by_name(obj, "FS_HCTSIZ7"); + + + // FS_HCFG bitfields. + state->u.f4.fld.fs_hcfg.fslspcs = cm_object_get_child_by_name(state->u.f4.reg.fs_hcfg, "FSLSPCS"); + state->u.f4.fld.fs_hcfg.fslss = cm_object_get_child_by_name(state->u.f4.reg.fs_hcfg, "FSLSS"); + + // HFIR bitfields. + state->u.f4.fld.hfir.frivl = cm_object_get_child_by_name(state->u.f4.reg.hfir, "FRIVL"); + + // FS_HFNUM bitfields. + state->u.f4.fld.fs_hfnum.frnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hfnum, "FRNUM"); + state->u.f4.fld.fs_hfnum.ftrem = cm_object_get_child_by_name(state->u.f4.reg.fs_hfnum, "FTREM"); + + // FS_HPTXSTS bitfields. + state->u.f4.fld.fs_hptxsts.ptxfsavl = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXFSAVL"); + state->u.f4.fld.fs_hptxsts.ptxqsav = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXQSAV"); + state->u.f4.fld.fs_hptxsts.ptxqtop = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXQTOP"); + + // HAINT bitfields. + state->u.f4.fld.haint.haint = cm_object_get_child_by_name(state->u.f4.reg.haint, "HAINT"); + + // HAINTMSK bitfields. + state->u.f4.fld.haintmsk.haintm = cm_object_get_child_by_name(state->u.f4.reg.haintmsk, "HAINTM"); + + // FS_HPRT bitfields. + state->u.f4.fld.fs_hprt.pcsts = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PCSTS"); + state->u.f4.fld.fs_hprt.pcdet = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PCDET"); + state->u.f4.fld.fs_hprt.pena = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PENA"); + state->u.f4.fld.fs_hprt.penchng = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PENCHNG"); + state->u.f4.fld.fs_hprt.poca = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "POCA"); + state->u.f4.fld.fs_hprt.pocchng = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "POCCHNG"); + state->u.f4.fld.fs_hprt.pres = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PRES"); + state->u.f4.fld.fs_hprt.psusp = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PSUSP"); + state->u.f4.fld.fs_hprt.prst = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PRST"); + state->u.f4.fld.fs_hprt.plsts = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PLSTS"); + state->u.f4.fld.fs_hprt.ppwr = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PPWR"); + state->u.f4.fld.fs_hprt.ptctl = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PTCTL"); + state->u.f4.fld.fs_hprt.pspd = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PSPD"); + + // FS_HCCHAR0 bitfields. + state->u.f4.fld.fs_hcchar0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "MPSIZ"); + state->u.f4.fld.fs_hcchar0.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPNUM"); + state->u.f4.fld.fs_hcchar0.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPDIR"); + state->u.f4.fld.fs_hcchar0.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "LSDEV"); + state->u.f4.fld.fs_hcchar0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPTYP"); + state->u.f4.fld.fs_hcchar0.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "MCNT"); + state->u.f4.fld.fs_hcchar0.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "DAD"); + state->u.f4.fld.fs_hcchar0.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "ODDFRM"); + state->u.f4.fld.fs_hcchar0.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "CHDIS"); + state->u.f4.fld.fs_hcchar0.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "CHENA"); + + // FS_HCCHAR1 bitfields. + state->u.f4.fld.fs_hcchar1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "MPSIZ"); + state->u.f4.fld.fs_hcchar1.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPNUM"); + state->u.f4.fld.fs_hcchar1.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPDIR"); + state->u.f4.fld.fs_hcchar1.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "LSDEV"); + state->u.f4.fld.fs_hcchar1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPTYP"); + state->u.f4.fld.fs_hcchar1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "MCNT"); + state->u.f4.fld.fs_hcchar1.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "DAD"); + state->u.f4.fld.fs_hcchar1.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "ODDFRM"); + state->u.f4.fld.fs_hcchar1.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "CHDIS"); + state->u.f4.fld.fs_hcchar1.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "CHENA"); + + // FS_HCCHAR2 bitfields. + state->u.f4.fld.fs_hcchar2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "MPSIZ"); + state->u.f4.fld.fs_hcchar2.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPNUM"); + state->u.f4.fld.fs_hcchar2.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPDIR"); + state->u.f4.fld.fs_hcchar2.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "LSDEV"); + state->u.f4.fld.fs_hcchar2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPTYP"); + state->u.f4.fld.fs_hcchar2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "MCNT"); + state->u.f4.fld.fs_hcchar2.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "DAD"); + state->u.f4.fld.fs_hcchar2.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "ODDFRM"); + state->u.f4.fld.fs_hcchar2.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "CHDIS"); + state->u.f4.fld.fs_hcchar2.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "CHENA"); + + // FS_HCCHAR3 bitfields. + state->u.f4.fld.fs_hcchar3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "MPSIZ"); + state->u.f4.fld.fs_hcchar3.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPNUM"); + state->u.f4.fld.fs_hcchar3.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPDIR"); + state->u.f4.fld.fs_hcchar3.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "LSDEV"); + state->u.f4.fld.fs_hcchar3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPTYP"); + state->u.f4.fld.fs_hcchar3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "MCNT"); + state->u.f4.fld.fs_hcchar3.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "DAD"); + state->u.f4.fld.fs_hcchar3.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "ODDFRM"); + state->u.f4.fld.fs_hcchar3.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "CHDIS"); + state->u.f4.fld.fs_hcchar3.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "CHENA"); + + // FS_HCCHAR4 bitfields. + state->u.f4.fld.fs_hcchar4.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "MPSIZ"); + state->u.f4.fld.fs_hcchar4.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPNUM"); + state->u.f4.fld.fs_hcchar4.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPDIR"); + state->u.f4.fld.fs_hcchar4.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "LSDEV"); + state->u.f4.fld.fs_hcchar4.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPTYP"); + state->u.f4.fld.fs_hcchar4.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "MCNT"); + state->u.f4.fld.fs_hcchar4.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "DAD"); + state->u.f4.fld.fs_hcchar4.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "ODDFRM"); + state->u.f4.fld.fs_hcchar4.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "CHDIS"); + state->u.f4.fld.fs_hcchar4.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "CHENA"); + + // FS_HCCHAR5 bitfields. + state->u.f4.fld.fs_hcchar5.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "MPSIZ"); + state->u.f4.fld.fs_hcchar5.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPNUM"); + state->u.f4.fld.fs_hcchar5.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPDIR"); + state->u.f4.fld.fs_hcchar5.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "LSDEV"); + state->u.f4.fld.fs_hcchar5.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPTYP"); + state->u.f4.fld.fs_hcchar5.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "MCNT"); + state->u.f4.fld.fs_hcchar5.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "DAD"); + state->u.f4.fld.fs_hcchar5.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "ODDFRM"); + state->u.f4.fld.fs_hcchar5.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "CHDIS"); + state->u.f4.fld.fs_hcchar5.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "CHENA"); + + // FS_HCCHAR6 bitfields. + state->u.f4.fld.fs_hcchar6.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "MPSIZ"); + state->u.f4.fld.fs_hcchar6.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPNUM"); + state->u.f4.fld.fs_hcchar6.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPDIR"); + state->u.f4.fld.fs_hcchar6.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "LSDEV"); + state->u.f4.fld.fs_hcchar6.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPTYP"); + state->u.f4.fld.fs_hcchar6.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "MCNT"); + state->u.f4.fld.fs_hcchar6.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "DAD"); + state->u.f4.fld.fs_hcchar6.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "ODDFRM"); + state->u.f4.fld.fs_hcchar6.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "CHDIS"); + state->u.f4.fld.fs_hcchar6.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "CHENA"); + + // FS_HCCHAR7 bitfields. + state->u.f4.fld.fs_hcchar7.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "MPSIZ"); + state->u.f4.fld.fs_hcchar7.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPNUM"); + state->u.f4.fld.fs_hcchar7.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPDIR"); + state->u.f4.fld.fs_hcchar7.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "LSDEV"); + state->u.f4.fld.fs_hcchar7.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPTYP"); + state->u.f4.fld.fs_hcchar7.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "MCNT"); + state->u.f4.fld.fs_hcchar7.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "DAD"); + state->u.f4.fld.fs_hcchar7.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "ODDFRM"); + state->u.f4.fld.fs_hcchar7.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "CHDIS"); + state->u.f4.fld.fs_hcchar7.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "CHENA"); + + // FS_HCINT0 bitfields. + state->u.f4.fld.fs_hcint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "XFRC"); + state->u.f4.fld.fs_hcint0.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "CHH"); + state->u.f4.fld.fs_hcint0.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "STALL"); + state->u.f4.fld.fs_hcint0.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "NAK"); + state->u.f4.fld.fs_hcint0.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "ACK"); + state->u.f4.fld.fs_hcint0.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "TXERR"); + state->u.f4.fld.fs_hcint0.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "BBERR"); + state->u.f4.fld.fs_hcint0.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "FRMOR"); + state->u.f4.fld.fs_hcint0.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "DTERR"); + + // FS_HCINT1 bitfields. + state->u.f4.fld.fs_hcint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "XFRC"); + state->u.f4.fld.fs_hcint1.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "CHH"); + state->u.f4.fld.fs_hcint1.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "STALL"); + state->u.f4.fld.fs_hcint1.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "NAK"); + state->u.f4.fld.fs_hcint1.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "ACK"); + state->u.f4.fld.fs_hcint1.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "TXERR"); + state->u.f4.fld.fs_hcint1.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "BBERR"); + state->u.f4.fld.fs_hcint1.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "FRMOR"); + state->u.f4.fld.fs_hcint1.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "DTERR"); + + // FS_HCINT2 bitfields. + state->u.f4.fld.fs_hcint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "XFRC"); + state->u.f4.fld.fs_hcint2.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "CHH"); + state->u.f4.fld.fs_hcint2.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "STALL"); + state->u.f4.fld.fs_hcint2.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "NAK"); + state->u.f4.fld.fs_hcint2.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "ACK"); + state->u.f4.fld.fs_hcint2.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "TXERR"); + state->u.f4.fld.fs_hcint2.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "BBERR"); + state->u.f4.fld.fs_hcint2.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "FRMOR"); + state->u.f4.fld.fs_hcint2.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "DTERR"); + + // FS_HCINT3 bitfields. + state->u.f4.fld.fs_hcint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "XFRC"); + state->u.f4.fld.fs_hcint3.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "CHH"); + state->u.f4.fld.fs_hcint3.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "STALL"); + state->u.f4.fld.fs_hcint3.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "NAK"); + state->u.f4.fld.fs_hcint3.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "ACK"); + state->u.f4.fld.fs_hcint3.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "TXERR"); + state->u.f4.fld.fs_hcint3.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "BBERR"); + state->u.f4.fld.fs_hcint3.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "FRMOR"); + state->u.f4.fld.fs_hcint3.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "DTERR"); + + // FS_HCINT4 bitfields. + state->u.f4.fld.fs_hcint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "XFRC"); + state->u.f4.fld.fs_hcint4.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "CHH"); + state->u.f4.fld.fs_hcint4.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "STALL"); + state->u.f4.fld.fs_hcint4.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "NAK"); + state->u.f4.fld.fs_hcint4.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "ACK"); + state->u.f4.fld.fs_hcint4.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "TXERR"); + state->u.f4.fld.fs_hcint4.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "BBERR"); + state->u.f4.fld.fs_hcint4.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "FRMOR"); + state->u.f4.fld.fs_hcint4.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "DTERR"); + + // FS_HCINT5 bitfields. + state->u.f4.fld.fs_hcint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "XFRC"); + state->u.f4.fld.fs_hcint5.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "CHH"); + state->u.f4.fld.fs_hcint5.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "STALL"); + state->u.f4.fld.fs_hcint5.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "NAK"); + state->u.f4.fld.fs_hcint5.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "ACK"); + state->u.f4.fld.fs_hcint5.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "TXERR"); + state->u.f4.fld.fs_hcint5.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "BBERR"); + state->u.f4.fld.fs_hcint5.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "FRMOR"); + state->u.f4.fld.fs_hcint5.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "DTERR"); + + // FS_HCINT6 bitfields. + state->u.f4.fld.fs_hcint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "XFRC"); + state->u.f4.fld.fs_hcint6.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "CHH"); + state->u.f4.fld.fs_hcint6.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "STALL"); + state->u.f4.fld.fs_hcint6.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "NAK"); + state->u.f4.fld.fs_hcint6.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "ACK"); + state->u.f4.fld.fs_hcint6.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "TXERR"); + state->u.f4.fld.fs_hcint6.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "BBERR"); + state->u.f4.fld.fs_hcint6.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "FRMOR"); + state->u.f4.fld.fs_hcint6.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "DTERR"); + + // FS_HCINT7 bitfields. + state->u.f4.fld.fs_hcint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "XFRC"); + state->u.f4.fld.fs_hcint7.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "CHH"); + state->u.f4.fld.fs_hcint7.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "STALL"); + state->u.f4.fld.fs_hcint7.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "NAK"); + state->u.f4.fld.fs_hcint7.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "ACK"); + state->u.f4.fld.fs_hcint7.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "TXERR"); + state->u.f4.fld.fs_hcint7.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "BBERR"); + state->u.f4.fld.fs_hcint7.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "FRMOR"); + state->u.f4.fld.fs_hcint7.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "DTERR"); + + // FS_HCINTMSK0 bitfields. + state->u.f4.fld.fs_hcintmsk0.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "XFRCM"); + state->u.f4.fld.fs_hcintmsk0.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "CHHM"); + state->u.f4.fld.fs_hcintmsk0.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "STALLM"); + state->u.f4.fld.fs_hcintmsk0.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "NAKM"); + state->u.f4.fld.fs_hcintmsk0.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "ACKM"); + state->u.f4.fld.fs_hcintmsk0.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "NYET"); + state->u.f4.fld.fs_hcintmsk0.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "TXERRM"); + state->u.f4.fld.fs_hcintmsk0.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "BBERRM"); + state->u.f4.fld.fs_hcintmsk0.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "FRMORM"); + state->u.f4.fld.fs_hcintmsk0.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "DTERRM"); + + // FS_HCINTMSK1 bitfields. + state->u.f4.fld.fs_hcintmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "XFRCM"); + state->u.f4.fld.fs_hcintmsk1.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "CHHM"); + state->u.f4.fld.fs_hcintmsk1.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "STALLM"); + state->u.f4.fld.fs_hcintmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "NAKM"); + state->u.f4.fld.fs_hcintmsk1.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "ACKM"); + state->u.f4.fld.fs_hcintmsk1.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "NYET"); + state->u.f4.fld.fs_hcintmsk1.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "TXERRM"); + state->u.f4.fld.fs_hcintmsk1.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "BBERRM"); + state->u.f4.fld.fs_hcintmsk1.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "FRMORM"); + state->u.f4.fld.fs_hcintmsk1.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "DTERRM"); + + // FS_HCINTMSK2 bitfields. + state->u.f4.fld.fs_hcintmsk2.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "XFRCM"); + state->u.f4.fld.fs_hcintmsk2.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "CHHM"); + state->u.f4.fld.fs_hcintmsk2.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "STALLM"); + state->u.f4.fld.fs_hcintmsk2.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "NAKM"); + state->u.f4.fld.fs_hcintmsk2.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "ACKM"); + state->u.f4.fld.fs_hcintmsk2.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "NYET"); + state->u.f4.fld.fs_hcintmsk2.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "TXERRM"); + state->u.f4.fld.fs_hcintmsk2.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "BBERRM"); + state->u.f4.fld.fs_hcintmsk2.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "FRMORM"); + state->u.f4.fld.fs_hcintmsk2.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "DTERRM"); + + // FS_HCINTMSK3 bitfields. + state->u.f4.fld.fs_hcintmsk3.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "XFRCM"); + state->u.f4.fld.fs_hcintmsk3.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "CHHM"); + state->u.f4.fld.fs_hcintmsk3.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "STALLM"); + state->u.f4.fld.fs_hcintmsk3.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "NAKM"); + state->u.f4.fld.fs_hcintmsk3.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "ACKM"); + state->u.f4.fld.fs_hcintmsk3.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "NYET"); + state->u.f4.fld.fs_hcintmsk3.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "TXERRM"); + state->u.f4.fld.fs_hcintmsk3.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "BBERRM"); + state->u.f4.fld.fs_hcintmsk3.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "FRMORM"); + state->u.f4.fld.fs_hcintmsk3.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "DTERRM"); + + // FS_HCINTMSK4 bitfields. + state->u.f4.fld.fs_hcintmsk4.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "XFRCM"); + state->u.f4.fld.fs_hcintmsk4.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "CHHM"); + state->u.f4.fld.fs_hcintmsk4.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "STALLM"); + state->u.f4.fld.fs_hcintmsk4.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "NAKM"); + state->u.f4.fld.fs_hcintmsk4.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "ACKM"); + state->u.f4.fld.fs_hcintmsk4.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "NYET"); + state->u.f4.fld.fs_hcintmsk4.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "TXERRM"); + state->u.f4.fld.fs_hcintmsk4.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "BBERRM"); + state->u.f4.fld.fs_hcintmsk4.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "FRMORM"); + state->u.f4.fld.fs_hcintmsk4.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "DTERRM"); + + // FS_HCINTMSK5 bitfields. + state->u.f4.fld.fs_hcintmsk5.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "XFRCM"); + state->u.f4.fld.fs_hcintmsk5.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "CHHM"); + state->u.f4.fld.fs_hcintmsk5.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "STALLM"); + state->u.f4.fld.fs_hcintmsk5.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "NAKM"); + state->u.f4.fld.fs_hcintmsk5.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "ACKM"); + state->u.f4.fld.fs_hcintmsk5.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "NYET"); + state->u.f4.fld.fs_hcintmsk5.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "TXERRM"); + state->u.f4.fld.fs_hcintmsk5.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "BBERRM"); + state->u.f4.fld.fs_hcintmsk5.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "FRMORM"); + state->u.f4.fld.fs_hcintmsk5.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "DTERRM"); + + // FS_HCINTMSK6 bitfields. + state->u.f4.fld.fs_hcintmsk6.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "XFRCM"); + state->u.f4.fld.fs_hcintmsk6.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "CHHM"); + state->u.f4.fld.fs_hcintmsk6.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "STALLM"); + state->u.f4.fld.fs_hcintmsk6.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "NAKM"); + state->u.f4.fld.fs_hcintmsk6.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "ACKM"); + state->u.f4.fld.fs_hcintmsk6.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "NYET"); + state->u.f4.fld.fs_hcintmsk6.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "TXERRM"); + state->u.f4.fld.fs_hcintmsk6.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "BBERRM"); + state->u.f4.fld.fs_hcintmsk6.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "FRMORM"); + state->u.f4.fld.fs_hcintmsk6.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "DTERRM"); + + // FS_HCINTMSK7 bitfields. + state->u.f4.fld.fs_hcintmsk7.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "XFRCM"); + state->u.f4.fld.fs_hcintmsk7.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "CHHM"); + state->u.f4.fld.fs_hcintmsk7.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "STALLM"); + state->u.f4.fld.fs_hcintmsk7.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "NAKM"); + state->u.f4.fld.fs_hcintmsk7.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "ACKM"); + state->u.f4.fld.fs_hcintmsk7.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "NYET"); + state->u.f4.fld.fs_hcintmsk7.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "TXERRM"); + state->u.f4.fld.fs_hcintmsk7.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "BBERRM"); + state->u.f4.fld.fs_hcintmsk7.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "FRMORM"); + state->u.f4.fld.fs_hcintmsk7.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "DTERRM"); + + // FS_HCTSIZ0 bitfields. + state->u.f4.fld.fs_hctsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "PKTCNT"); + state->u.f4.fld.fs_hctsiz0.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "DPID"); + + // FS_HCTSIZ1 bitfields. + state->u.f4.fld.fs_hctsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "PKTCNT"); + state->u.f4.fld.fs_hctsiz1.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "DPID"); + + // FS_HCTSIZ2 bitfields. + state->u.f4.fld.fs_hctsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "PKTCNT"); + state->u.f4.fld.fs_hctsiz2.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "DPID"); + + // FS_HCTSIZ3 bitfields. + state->u.f4.fld.fs_hctsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "PKTCNT"); + state->u.f4.fld.fs_hctsiz3.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "DPID"); + + // FS_HCTSIZ4 bitfields. + state->u.f4.fld.fs_hctsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "PKTCNT"); + state->u.f4.fld.fs_hctsiz4.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "DPID"); + + // FS_HCTSIZ5 bitfields. + state->u.f4.fld.fs_hctsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz5.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "PKTCNT"); + state->u.f4.fld.fs_hctsiz5.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "DPID"); + + // FS_HCTSIZ6 bitfields. + state->u.f4.fld.fs_hctsiz6.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz6.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "PKTCNT"); + state->u.f4.fld.fs_hctsiz6.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "DPID"); + + // FS_HCTSIZ7 bitfields. + state->u.f4.fld.fs_hctsiz7.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz7.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "PKTCNT"); + state->u.f4.fld.fs_hctsiz7.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "DPID"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_host_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_host_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_host_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_host_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_host_is_enabled(Object *obj) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_host_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_host_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_HOST)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_HOST"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_otg_fs_host_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_HOSTEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_host_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_HOST); +} + +static void stm32_otg_fs_host_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_host_reset_callback; + dc->realize = stm32_otg_fs_host_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_host_is_enabled; +} + +static const TypeInfo stm32_otg_fs_host_type_info = { + .name = TYPE_STM32_OTG_FS_HOST, + .parent = TYPE_STM32_OTG_FS_HOST_PARENT, + .instance_init = stm32_otg_fs_host_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_HOSTState), + .class_init = stm32_otg_fs_host_class_init_callback, + .class_size = sizeof(STM32OTG_FS_HOSTClass) }; + +static void stm32_otg_fs_host_register_types(void) +{ + type_register_static(&stm32_otg_fs_host_type_info); +} + +type_init(stm32_otg_fs_host_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_host.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_host.h new file mode 100644 index 0000000000..c08c620d0e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_host.h @@ -0,0 +1,573 @@ +/* + * STM32 - OTG_FS_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_HOST_H_ +#define STM32_OTG_FS_HOST_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_HOST DEVICE_PATH_STM32 "OTG_FS_HOST" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_HOST TYPE_STM32_PREFIX "otg_fs_host" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_HOST_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_HOSTParentClass; +typedef PeripheralState STM32OTG_FS_HOSTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_HOST_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_HOSTClass, (obj), TYPE_STM32_OTG_FS_HOST) +#define STM32_OTG_FS_HOST_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_HOSTClass, (klass), TYPE_STM32_OTG_FS_HOST) + +typedef struct { + // private: + STM32OTG_FS_HOSTParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_HOSTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_HOST_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_HOSTState, (obj), TYPE_STM32_OTG_FS_HOST) + +typedef struct { + // private: + STM32OTG_FS_HOSTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_HOST (USB on the go full speed) registers. + struct { + Object *fs_hcfg; // 0x0 (OTG_FS host configuration register (OTG_FS_HCFG)) + Object *hfir; // 0x4 (OTG_FS Host frame interval register) + Object *fs_hfnum; // 0x8 (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) + Object *fs_hptxsts; // 0x10 (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) + Object *haint; // 0x14 (OTG_FS Host all channels interrupt register) + Object *haintmsk; // 0x18 (OTG_FS host all channels interrupt mask register) + Object *fs_hprt; // 0x40 (OTG_FS host port control and status register (OTG_FS_HPRT)) + Object *fs_hcchar0; // 0x100 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) + Object *fs_hcchar1; // 0x120 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) + Object *fs_hcchar2; // 0x140 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) + Object *fs_hcchar3; // 0x160 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) + Object *fs_hcchar4; // 0x180 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) + Object *fs_hcchar5; // 0x1A0 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) + Object *fs_hcchar6; // 0x1C0 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) + Object *fs_hcchar7; // 0x1E0 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) + Object *fs_hcint0; // 0x108 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) + Object *fs_hcint1; // 0x128 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) + Object *fs_hcint2; // 0x148 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) + Object *fs_hcint3; // 0x168 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) + Object *fs_hcint4; // 0x188 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) + Object *fs_hcint5; // 0x1A8 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) + Object *fs_hcint6; // 0x1C8 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) + Object *fs_hcint7; // 0x1E8 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) + Object *fs_hcintmsk0; // 0x10C (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) + Object *fs_hcintmsk1; // 0x12C (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) + Object *fs_hcintmsk2; // 0x14C (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) + Object *fs_hcintmsk3; // 0x16C (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) + Object *fs_hcintmsk4; // 0x18C (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) + Object *fs_hcintmsk5; // 0x1AC (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) + Object *fs_hcintmsk6; // 0x1CC (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) + Object *fs_hcintmsk7; // 0x1EC (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) + Object *fs_hctsiz0; // 0x110 (OTG_FS host channel-0 transfer size register) + Object *fs_hctsiz1; // 0x130 (OTG_FS host channel-1 transfer size register) + Object *fs_hctsiz2; // 0x150 (OTG_FS host channel-2 transfer size register) + Object *fs_hctsiz3; // 0x170 (OTG_FS host channel-3 transfer size register) + Object *fs_hctsiz4; // 0x190 (OTG_FS host channel-x transfer size register) + Object *fs_hctsiz5; // 0x1B0 (OTG_FS host channel-5 transfer size register) + Object *fs_hctsiz6; // 0x1D0 (OTG_FS host channel-6 transfer size register) + Object *fs_hctsiz7; // 0x1F0 (OTG_FS host channel-7 transfer size register) + } reg; + + struct { + + // FS_HCFG (OTG_FS host configuration register (OTG_FS_HCFG)) bitfields. + struct { + Object *fslspcs; // [0:1] FS/LS PHY clock select + Object *fslss; // [2:2] FS- and LS-only support + } fs_hcfg; + + // HFIR (OTG_FS Host frame interval register) bitfields. + struct { + Object *frivl; // [0:15] Frame interval + } hfir; + + // FS_HFNUM (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) bitfields. + struct { + Object *frnum; // [0:15] Frame number + Object *ftrem; // [16:31] Frame time remaining + } fs_hfnum; + + // FS_HPTXSTS (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) bitfields. + struct { + Object *ptxfsavl; // [0:15] Periodic transmit data FIFO space available + Object *ptxqsav; // [16:23] Periodic transmit request queue space available + Object *ptxqtop; // [24:31] Top of the periodic transmit request queue + } fs_hptxsts; + + // HAINT (OTG_FS Host all channels interrupt register) bitfields. + struct { + Object *haint; // [0:15] Channel interrupts + } haint; + + // HAINTMSK (OTG_FS host all channels interrupt mask register) bitfields. + struct { + Object *haintm; // [0:15] Channel interrupt mask + } haintmsk; + + // FS_HPRT (OTG_FS host port control and status register (OTG_FS_HPRT)) bitfields. + struct { + Object *pcsts; // [0:0] Port connect status + Object *pcdet; // [1:1] Port connect detected + Object *pena; // [2:2] Port enable + Object *penchng; // [3:3] Port enable/disable change + Object *poca; // [4:4] Port overcurrent active + Object *pocchng; // [5:5] Port overcurrent change + Object *pres; // [6:6] Port resume + Object *psusp; // [7:7] Port suspend + Object *prst; // [8:8] Port reset + Object *plsts; // [10:11] Port line status + Object *ppwr; // [12:12] Port power + Object *ptctl; // [13:16] Port test control + Object *pspd; // [17:18] Port speed + } fs_hprt; + + // FS_HCCHAR0 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar0; + + // FS_HCCHAR1 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar1; + + // FS_HCCHAR2 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar2; + + // FS_HCCHAR3 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar3; + + // FS_HCCHAR4 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar4; + + // FS_HCCHAR5 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar5; + + // FS_HCCHAR6 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar6; + + // FS_HCCHAR7 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar7; + + // FS_HCINT0 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint0; + + // FS_HCINT1 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint1; + + // FS_HCINT2 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint2; + + // FS_HCINT3 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint3; + + // FS_HCINT4 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint4; + + // FS_HCINT5 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint5; + + // FS_HCINT6 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint6; + + // FS_HCINT7 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint7; + + // FS_HCINTMSK0 (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk0; + + // FS_HCINTMSK1 (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk1; + + // FS_HCINTMSK2 (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk2; + + // FS_HCINTMSK3 (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk3; + + // FS_HCINTMSK4 (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk4; + + // FS_HCINTMSK5 (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk5; + + // FS_HCINTMSK6 (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk6; + + // FS_HCINTMSK7 (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk7; + + // FS_HCTSIZ0 (OTG_FS host channel-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz0; + + // FS_HCTSIZ1 (OTG_FS host channel-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz1; + + // FS_HCTSIZ2 (OTG_FS host channel-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz2; + + // FS_HCTSIZ3 (OTG_FS host channel-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz3; + + // FS_HCTSIZ4 (OTG_FS host channel-x transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz4; + + // FS_HCTSIZ5 (OTG_FS host channel-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz5; + + // FS_HCTSIZ6 (OTG_FS host channel-6 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz6; + + // FS_HCTSIZ7 (OTG_FS host channel-7 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz7; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_HOSTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_HOST_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_pwrclk.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_pwrclk.c new file mode 100644 index 0000000000..8b9f556eaf --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_pwrclk.c @@ -0,0 +1,240 @@ +/* + * STM32 - OTG_FS_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_otg_fs_pwrclk_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_pcgcctl = cm_object_get_child_by_name(obj, "FS_PCGCCTL"); + + + // FS_PCGCCTL bitfields. + state->u.f4.fld.fs_pcgcctl.stppclk = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "STPPCLK"); + state->u.f4.fld.fs_pcgcctl.gatehclk = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "GATEHCLK"); + state->u.f4.fld.fs_pcgcctl.physusp = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "PHYSUSP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_pwrclk_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_pwrclk_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_pwrclk_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_pwrclk_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_pwrclk_is_enabled(Object *obj) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_pwrclk_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_pwrclk_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_PWRCLK)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_PWRCLK"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_otg_fs_pwrclk_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_PWRCLKEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_pwrclk_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_PWRCLK); +} + +static void stm32_otg_fs_pwrclk_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_pwrclk_reset_callback; + dc->realize = stm32_otg_fs_pwrclk_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_pwrclk_is_enabled; +} + +static const TypeInfo stm32_otg_fs_pwrclk_type_info = { + .name = TYPE_STM32_OTG_FS_PWRCLK, + .parent = TYPE_STM32_OTG_FS_PWRCLK_PARENT, + .instance_init = stm32_otg_fs_pwrclk_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_PWRCLKState), + .class_init = stm32_otg_fs_pwrclk_class_init_callback, + .class_size = sizeof(STM32OTG_FS_PWRCLKClass) }; + +static void stm32_otg_fs_pwrclk_register_types(void) +{ + type_register_static(&stm32_otg_fs_pwrclk_type_info); +} + +type_init(stm32_otg_fs_pwrclk_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_pwrclk.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_pwrclk.h new file mode 100644 index 0000000000..5044b8fa1b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/otg_fs_pwrclk.h @@ -0,0 +1,107 @@ +/* + * STM32 - OTG_FS_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_PWRCLK_H_ +#define STM32_OTG_FS_PWRCLK_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_PWRCLK DEVICE_PATH_STM32 "OTG_FS_PWRCLK" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_PWRCLK TYPE_STM32_PREFIX "otg_fs_pwrclk" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_PWRCLK_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_PWRCLKParentClass; +typedef PeripheralState STM32OTG_FS_PWRCLKParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_PWRCLK_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_PWRCLKClass, (obj), TYPE_STM32_OTG_FS_PWRCLK) +#define STM32_OTG_FS_PWRCLK_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_PWRCLKClass, (klass), TYPE_STM32_OTG_FS_PWRCLK) + +typedef struct { + // private: + STM32OTG_FS_PWRCLKParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_PWRCLKClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_PWRCLK_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_PWRCLKState, (obj), TYPE_STM32_OTG_FS_PWRCLK) + +typedef struct { + // private: + STM32OTG_FS_PWRCLKParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_PWRCLK (USB on the go full speed) registers. + struct { + Object *fs_pcgcctl; // 0x0 (OTG_FS power and clock gating control register) + } reg; + + struct { + + // FS_PCGCCTL (OTG_FS power and clock gating control register) bitfields. + struct { + Object *stppclk; // [0:0] Stop PHY clock + Object *gatehclk; // [1:1] Gate HCLK + Object *physusp; // [4:4] PHY Suspended + } fs_pcgcctl; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_PWRCLKState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_PWRCLK_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/pwr.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/pwr.c new file mode 100644 index 0000000000..0111dc8e57 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/pwr.c @@ -0,0 +1,257 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_pwr_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CR bitfields. + state->u.f4.fld.cr.lpds = cm_object_get_child_by_name(state->u.f4.reg.cr, "LPDS"); + state->u.f4.fld.cr.pdds = cm_object_get_child_by_name(state->u.f4.reg.cr, "PDDS"); + state->u.f4.fld.cr.cwuf = cm_object_get_child_by_name(state->u.f4.reg.cr, "CWUF"); + state->u.f4.fld.cr.csbf = cm_object_get_child_by_name(state->u.f4.reg.cr, "CSBF"); + state->u.f4.fld.cr.pvde = cm_object_get_child_by_name(state->u.f4.reg.cr, "PVDE"); + state->u.f4.fld.cr.pls = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLS"); + state->u.f4.fld.cr.dbp = cm_object_get_child_by_name(state->u.f4.reg.cr, "DBP"); + state->u.f4.fld.cr.fpds = cm_object_get_child_by_name(state->u.f4.reg.cr, "FPDS"); + state->u.f4.fld.cr.adcdc1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "ADCDC1"); + state->u.f4.fld.cr.vos = cm_object_get_child_by_name(state->u.f4.reg.cr, "VOS"); + + // CSR bitfields. + state->u.f4.fld.csr.wuf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WUF"); + state->u.f4.fld.csr.sbf = cm_object_get_child_by_name(state->u.f4.reg.csr, "SBF"); + state->u.f4.fld.csr.pvdo = cm_object_get_child_by_name(state->u.f4.reg.csr, "PVDO"); + state->u.f4.fld.csr.brr = cm_object_get_child_by_name(state->u.f4.reg.csr, "BRR"); + state->u.f4.fld.csr.ewup = cm_object_get_child_by_name(state->u.f4.reg.csr, "EWUP"); + state->u.f4.fld.csr.bre = cm_object_get_child_by_name(state->u.f4.reg.csr, "BRE"); + state->u.f4.fld.csr.vosrdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "VOSRDY"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_pwr_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_pwr_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_pwr_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_pwr_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_pwr_is_enabled(Object *obj) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_pwr_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32PWRState *state = STM32_PWR_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_pwr_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_PWR)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32PWRState *state = STM32_PWR_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "PWR"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_pwr_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_pwr_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_pwr_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_pwr_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_pwr_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/PWREN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_pwr_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_PWR); +} + +static void stm32_pwr_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_pwr_reset_callback; + dc->realize = stm32_pwr_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_pwr_is_enabled; +} + +static const TypeInfo stm32_pwr_type_info = { + .name = TYPE_STM32_PWR, + .parent = TYPE_STM32_PWR_PARENT, + .instance_init = stm32_pwr_instance_init_callback, + .instance_size = sizeof(STM32PWRState), + .class_init = stm32_pwr_class_init_callback, + .class_size = sizeof(STM32PWRClass) }; + +static void stm32_pwr_register_types(void) +{ + type_register_static(&stm32_pwr_type_info); +} + +type_init(stm32_pwr_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/pwr.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/pwr.h new file mode 100644 index 0000000000..1e36ff645d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/pwr.h @@ -0,0 +1,126 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_PWR_H_ +#define STM32_PWR_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_PWR DEVICE_PATH_STM32 "PWR" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_PWR TYPE_STM32_PREFIX "pwr" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_PWR_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32PWRParentClass; +typedef PeripheralState STM32PWRParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_PWR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32PWRClass, (obj), TYPE_STM32_PWR) +#define STM32_PWR_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32PWRClass, (klass), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentClass parent_class; + // public: + + // None, so far. +} STM32PWRClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_PWR_STATE(obj) \ + OBJECT_CHECK(STM32PWRState, (obj), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 PWR (Power control) registers. + struct { + Object *cr; // 0x0 (Power control register) + Object *csr; // 0x4 (Power control/status register) + } reg; + + struct { + + // CR (Power control register) bitfields. + struct { + Object *lpds; // [0:0] Low-power deep sleep + Object *pdds; // [1:1] Power down deepsleep + Object *cwuf; // [2:2] Clear wakeup flag + Object *csbf; // [3:3] Clear standby flag + Object *pvde; // [4:4] Power voltage detector enable + Object *pls; // [5:7] PVD level selection + Object *dbp; // [8:8] Disable backup domain write protection + Object *fpds; // [9:9] Flash power down in Stop mode + Object *adcdc1; // [13:13] ADCDC1 + Object *vos; // [14:15] Regulator voltage scaling output selection + } cr; + + // CSR (Power control/status register) bitfields. + struct { + Object *wuf; // [0:0] Wakeup flag + Object *sbf; // [1:1] Standby flag + Object *pvdo; // [2:2] PVD output + Object *brr; // [3:3] Backup regulator ready + Object *ewup; // [8:8] Enable WKUP pin + Object *bre; // [9:9] Backup regulator enable + Object *vosrdy; // [14:14] Regulator voltage scaling output selection ready bit + } csr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32PWRState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_PWR_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/rcc.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/rcc.c new file mode 100644 index 0000000000..0a80148ef8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/rcc.c @@ -0,0 +1,464 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_rcc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.pllcfgr = cm_object_get_child_by_name(obj, "PLLCFGR"); + state->u.f4.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f4.reg.cir = cm_object_get_child_by_name(obj, "CIR"); + state->u.f4.reg.ahb1rstr = cm_object_get_child_by_name(obj, "AHB1RSTR"); + state->u.f4.reg.ahb2rstr = cm_object_get_child_by_name(obj, "AHB2RSTR"); + state->u.f4.reg.apb1rstr = cm_object_get_child_by_name(obj, "APB1RSTR"); + state->u.f4.reg.apb2rstr = cm_object_get_child_by_name(obj, "APB2RSTR"); + state->u.f4.reg.ahb1enr = cm_object_get_child_by_name(obj, "AHB1ENR"); + state->u.f4.reg.ahb2enr = cm_object_get_child_by_name(obj, "AHB2ENR"); + state->u.f4.reg.apb1enr = cm_object_get_child_by_name(obj, "APB1ENR"); + state->u.f4.reg.apb2enr = cm_object_get_child_by_name(obj, "APB2ENR"); + state->u.f4.reg.ahb1lpenr = cm_object_get_child_by_name(obj, "AHB1LPENR"); + state->u.f4.reg.ahb2lpenr = cm_object_get_child_by_name(obj, "AHB2LPENR"); + state->u.f4.reg.apb1lpenr = cm_object_get_child_by_name(obj, "APB1LPENR"); + state->u.f4.reg.apb2lpenr = cm_object_get_child_by_name(obj, "APB2LPENR"); + state->u.f4.reg.bdcr = cm_object_get_child_by_name(obj, "BDCR"); + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f4.reg.sscgr = cm_object_get_child_by_name(obj, "SSCGR"); + state->u.f4.reg.plli2scfgr = cm_object_get_child_by_name(obj, "PLLI2SCFGR"); + + + // CR bitfields. + state->u.f4.fld.cr.hsion = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSION"); + state->u.f4.fld.cr.hsirdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSIRDY"); + state->u.f4.fld.cr.hsitrim = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSITRIM"); + state->u.f4.fld.cr.hsical = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSICAL"); + state->u.f4.fld.cr.hseon = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSEON"); + state->u.f4.fld.cr.hserdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSERDY"); + state->u.f4.fld.cr.hsebyp = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSEBYP"); + state->u.f4.fld.cr.csson = cm_object_get_child_by_name(state->u.f4.reg.cr, "CSSON"); + state->u.f4.fld.cr.pllon = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLON"); + state->u.f4.fld.cr.pllrdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLRDY"); + state->u.f4.fld.cr.plli2son = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLI2SON"); + state->u.f4.fld.cr.plli2srdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLI2SRDY"); + + // PLLCFGR bitfields. + state->u.f4.fld.pllcfgr.pllm = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLM"); + state->u.f4.fld.pllcfgr.plln = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLN"); + state->u.f4.fld.pllcfgr.pllp = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLP"); + state->u.f4.fld.pllcfgr.pllsrc = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLSRC"); + state->u.f4.fld.pllcfgr.pllq = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLQ"); + + // CFGR bitfields. + state->u.f4.fld.cfgr.sw = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "SW"); + state->u.f4.fld.cfgr.sws = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "SWS"); + state->u.f4.fld.cfgr.hpre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "HPRE"); + state->u.f4.fld.cfgr.ppre1 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "PPRE1"); + state->u.f4.fld.cfgr.ppre2 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "PPRE2"); + state->u.f4.fld.cfgr.rtcpre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "RTCPRE"); + state->u.f4.fld.cfgr.mco1 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO1"); + state->u.f4.fld.cfgr.i2ssrc = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "I2SSRC"); + state->u.f4.fld.cfgr.mco1pre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO1PRE"); + state->u.f4.fld.cfgr.mco2pre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO2PRE"); + state->u.f4.fld.cfgr.mco2 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO2"); + + // CIR bitfields. + state->u.f4.fld.cir.lsirdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYF"); + state->u.f4.fld.cir.lserdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYF"); + state->u.f4.fld.cir.hsirdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYF"); + state->u.f4.fld.cir.hserdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYF"); + state->u.f4.fld.cir.pllrdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYF"); + state->u.f4.fld.cir.plli2srdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYF"); + state->u.f4.fld.cir.cssf = cm_object_get_child_by_name(state->u.f4.reg.cir, "CSSF"); + state->u.f4.fld.cir.lsirdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYIE"); + state->u.f4.fld.cir.lserdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYIE"); + state->u.f4.fld.cir.hsirdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYIE"); + state->u.f4.fld.cir.hserdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYIE"); + state->u.f4.fld.cir.pllrdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYIE"); + state->u.f4.fld.cir.plli2srdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYIE"); + state->u.f4.fld.cir.lsirdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYC"); + state->u.f4.fld.cir.lserdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYC"); + state->u.f4.fld.cir.hsirdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYC"); + state->u.f4.fld.cir.hserdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYC"); + state->u.f4.fld.cir.pllrdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYC"); + state->u.f4.fld.cir.plli2srdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYC"); + state->u.f4.fld.cir.cssc = cm_object_get_child_by_name(state->u.f4.reg.cir, "CSSC"); + + // AHB1RSTR bitfields. + state->u.f4.fld.ahb1rstr.gpioarst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOARST"); + state->u.f4.fld.ahb1rstr.gpiobrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOBRST"); + state->u.f4.fld.ahb1rstr.gpiocrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOCRST"); + state->u.f4.fld.ahb1rstr.gpiodrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIODRST"); + state->u.f4.fld.ahb1rstr.gpioerst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOERST"); + state->u.f4.fld.ahb1rstr.gpiohrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOHRST"); + state->u.f4.fld.ahb1rstr.crcrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "CRCRST"); + state->u.f4.fld.ahb1rstr.dma1rst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "DMA1RST"); + state->u.f4.fld.ahb1rstr.dma2rst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "DMA2RST"); + + // AHB2RSTR bitfields. + state->u.f4.fld.ahb2rstr.otgfsrst = cm_object_get_child_by_name(state->u.f4.reg.ahb2rstr, "OTGFSRST"); + + // APB1RSTR bitfields. + state->u.f4.fld.apb1rstr.tim2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM2RST"); + state->u.f4.fld.apb1rstr.tim3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM3RST"); + state->u.f4.fld.apb1rstr.tim4rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM4RST"); + state->u.f4.fld.apb1rstr.tim5rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM5RST"); + state->u.f4.fld.apb1rstr.wwdgrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "WWDGRST"); + state->u.f4.fld.apb1rstr.spi2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "SPI2RST"); + state->u.f4.fld.apb1rstr.spi3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "SPI3RST"); + state->u.f4.fld.apb1rstr.uart2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART2RST"); + state->u.f4.fld.apb1rstr.i2c1rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C1RST"); + state->u.f4.fld.apb1rstr.i2c2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C2RST"); + state->u.f4.fld.apb1rstr.i2c3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C3RST"); + state->u.f4.fld.apb1rstr.pwrrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "PWRRST"); + + // APB2RSTR bitfields. + state->u.f4.fld.apb2rstr.tim1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM1RST"); + state->u.f4.fld.apb2rstr.usart1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "USART1RST"); + state->u.f4.fld.apb2rstr.usart6rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "USART6RST"); + state->u.f4.fld.apb2rstr.adcrst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "ADCRST"); + state->u.f4.fld.apb2rstr.sdiorst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SDIORST"); + state->u.f4.fld.apb2rstr.spi1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SPI1RST"); + state->u.f4.fld.apb2rstr.syscfgrst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SYSCFGRST"); + state->u.f4.fld.apb2rstr.tim9rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM9RST"); + state->u.f4.fld.apb2rstr.tim10rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM10RST"); + state->u.f4.fld.apb2rstr.tim11rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM11RST"); + + // AHB1ENR bitfields. + state->u.f4.fld.ahb1enr.gpioaen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOAEN"); + state->u.f4.fld.ahb1enr.gpioben = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOBEN"); + state->u.f4.fld.ahb1enr.gpiocen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOCEN"); + state->u.f4.fld.ahb1enr.gpioden = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIODEN"); + state->u.f4.fld.ahb1enr.gpioeen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOEEN"); + state->u.f4.fld.ahb1enr.gpiohen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOHEN"); + state->u.f4.fld.ahb1enr.crcen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "CRCEN"); + state->u.f4.fld.ahb1enr.dma1en = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "DMA1EN"); + state->u.f4.fld.ahb1enr.dma2en = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "DMA2EN"); + + // AHB2ENR bitfields. + state->u.f4.fld.ahb2enr.otgfsen = cm_object_get_child_by_name(state->u.f4.reg.ahb2enr, "OTGFSEN"); + + // APB1ENR bitfields. + state->u.f4.fld.apb1enr.tim2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM2EN"); + state->u.f4.fld.apb1enr.tim3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM3EN"); + state->u.f4.fld.apb1enr.tim4en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM4EN"); + state->u.f4.fld.apb1enr.tim5en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM5EN"); + state->u.f4.fld.apb1enr.wwdgen = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "WWDGEN"); + state->u.f4.fld.apb1enr.spi2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "SPI2EN"); + state->u.f4.fld.apb1enr.spi3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "SPI3EN"); + state->u.f4.fld.apb1enr.usart2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "USART2EN"); + state->u.f4.fld.apb1enr.i2c1en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C1EN"); + state->u.f4.fld.apb1enr.i2c2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C2EN"); + state->u.f4.fld.apb1enr.i2c3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C3EN"); + state->u.f4.fld.apb1enr.pwren = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "PWREN"); + + // APB2ENR bitfields. + state->u.f4.fld.apb2enr.tim1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM1EN"); + state->u.f4.fld.apb2enr.usart1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "USART1EN"); + state->u.f4.fld.apb2enr.usart6en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "USART6EN"); + state->u.f4.fld.apb2enr.adc1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "ADC1EN"); + state->u.f4.fld.apb2enr.sdioen = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SDIOEN"); + state->u.f4.fld.apb2enr.spi1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SPI1EN"); + state->u.f4.fld.apb2enr.spi4en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SPI4EN"); + state->u.f4.fld.apb2enr.syscfgen = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SYSCFGEN"); + state->u.f4.fld.apb2enr.tim9en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM9EN"); + state->u.f4.fld.apb2enr.tim10en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM10EN"); + state->u.f4.fld.apb2enr.tim11en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM11EN"); + + // AHB1LPENR bitfields. + state->u.f4.fld.ahb1lpenr.gpioalpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOALPEN"); + state->u.f4.fld.ahb1lpenr.gpioblpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOBLPEN"); + state->u.f4.fld.ahb1lpenr.gpioclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOCLPEN"); + state->u.f4.fld.ahb1lpenr.gpiodlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIODLPEN"); + state->u.f4.fld.ahb1lpenr.gpioelpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOELPEN"); + state->u.f4.fld.ahb1lpenr.gpiohlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOHLPEN"); + state->u.f4.fld.ahb1lpenr.crclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "CRCLPEN"); + state->u.f4.fld.ahb1lpenr.flitflpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "FLITFLPEN"); + state->u.f4.fld.ahb1lpenr.sram1lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "SRAM1LPEN"); + state->u.f4.fld.ahb1lpenr.dma1lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "DMA1LPEN"); + state->u.f4.fld.ahb1lpenr.dma2lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "DMA2LPEN"); + + // AHB2LPENR bitfields. + state->u.f4.fld.ahb2lpenr.otgfslpen = cm_object_get_child_by_name(state->u.f4.reg.ahb2lpenr, "OTGFSLPEN"); + + // APB1LPENR bitfields. + state->u.f4.fld.apb1lpenr.tim2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM2LPEN"); + state->u.f4.fld.apb1lpenr.tim3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM3LPEN"); + state->u.f4.fld.apb1lpenr.tim4lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM4LPEN"); + state->u.f4.fld.apb1lpenr.tim5lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM5LPEN"); + state->u.f4.fld.apb1lpenr.wwdglpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "WWDGLPEN"); + state->u.f4.fld.apb1lpenr.spi2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "SPI2LPEN"); + state->u.f4.fld.apb1lpenr.spi3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "SPI3LPEN"); + state->u.f4.fld.apb1lpenr.usart2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "USART2LPEN"); + state->u.f4.fld.apb1lpenr.i2c1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C1LPEN"); + state->u.f4.fld.apb1lpenr.i2c2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C2LPEN"); + state->u.f4.fld.apb1lpenr.i2c3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C3LPEN"); + state->u.f4.fld.apb1lpenr.pwrlpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "PWRLPEN"); + + // APB2LPENR bitfields. + state->u.f4.fld.apb2lpenr.tim1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM1LPEN"); + state->u.f4.fld.apb2lpenr.usart1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "USART1LPEN"); + state->u.f4.fld.apb2lpenr.usart6lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "USART6LPEN"); + state->u.f4.fld.apb2lpenr.adc1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "ADC1LPEN"); + state->u.f4.fld.apb2lpenr.sdiolpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SDIOLPEN"); + state->u.f4.fld.apb2lpenr.spi1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SPI1LPEN"); + state->u.f4.fld.apb2lpenr.spi4lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SPI4LPEN"); + state->u.f4.fld.apb2lpenr.syscfglpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SYSCFGLPEN"); + state->u.f4.fld.apb2lpenr.tim9lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM9LPEN"); + state->u.f4.fld.apb2lpenr.tim10lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM10LPEN"); + state->u.f4.fld.apb2lpenr.tim11lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM11LPEN"); + + // BDCR bitfields. + state->u.f4.fld.bdcr.lseon = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSEON"); + state->u.f4.fld.bdcr.lserdy = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSERDY"); + state->u.f4.fld.bdcr.lsebyp = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSEBYP"); + state->u.f4.fld.bdcr.rtcsel = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "RTCSEL"); + state->u.f4.fld.bdcr.rtcen = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "RTCEN"); + state->u.f4.fld.bdcr.bdrst = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "BDRST"); + + // CSR bitfields. + state->u.f4.fld.csr.lsion = cm_object_get_child_by_name(state->u.f4.reg.csr, "LSION"); + state->u.f4.fld.csr.lsirdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "LSIRDY"); + state->u.f4.fld.csr.rmvf = cm_object_get_child_by_name(state->u.f4.reg.csr, "RMVF"); + state->u.f4.fld.csr.borrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "BORRSTF"); + state->u.f4.fld.csr.padrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "PADRSTF"); + state->u.f4.fld.csr.porrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "PORRSTF"); + state->u.f4.fld.csr.sftrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "SFTRSTF"); + state->u.f4.fld.csr.wdgrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WDGRSTF"); + state->u.f4.fld.csr.wwdgrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WWDGRSTF"); + state->u.f4.fld.csr.lpwrrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "LPWRRSTF"); + + // SSCGR bitfields. + state->u.f4.fld.sscgr.modper = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "MODPER"); + state->u.f4.fld.sscgr.incstep = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "INCSTEP"); + state->u.f4.fld.sscgr.spreadsel = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "SPREADSEL"); + state->u.f4.fld.sscgr.sscgen = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "SSCGEN"); + + // PLLI2SCFGR bitfields. + state->u.f4.fld.plli2scfgr.plli2snx = cm_object_get_child_by_name(state->u.f4.reg.plli2scfgr, "PLLI2SNx"); + state->u.f4.fld.plli2scfgr.plli2srx = cm_object_get_child_by_name(state->u.f4.reg.plli2scfgr, "PLLI2SRx"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rcc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rcc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rcc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rcc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rcc_is_enabled(Object *obj) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rcc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RCCState *state = STM32_RCC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rcc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RCC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RCCState *state = STM32_RCC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RCC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_rcc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rcc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rcc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rcc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rcc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RCCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rcc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RCC); +} + +static void stm32_rcc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rcc_reset_callback; + dc->realize = stm32_rcc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rcc_is_enabled; +} + +static const TypeInfo stm32_rcc_type_info = { + .name = TYPE_STM32_RCC, + .parent = TYPE_STM32_RCC_PARENT, + .instance_init = stm32_rcc_instance_init_callback, + .instance_size = sizeof(STM32RCCState), + .class_init = stm32_rcc_class_init_callback, + .class_size = sizeof(STM32RCCClass) }; + +static void stm32_rcc_register_types(void) +{ + type_register_static(&stm32_rcc_type_info); +} + +type_init(stm32_rcc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/rcc.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/rcc.h new file mode 100644 index 0000000000..959e8b725f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/rcc.h @@ -0,0 +1,369 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RCC_H_ +#define STM32_RCC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RCC DEVICE_PATH_STM32 "RCC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RCC TYPE_STM32_PREFIX "rcc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RCC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RCCParentClass; +typedef PeripheralState STM32RCCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RCCClass, (obj), TYPE_STM32_RCC) +#define STM32_RCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RCCClass, (klass), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentClass parent_class; + // public: + + // None, so far. +} STM32RCCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RCC_STATE(obj) \ + OBJECT_CHECK(STM32RCCState, (obj), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RCC (Reset and clock control) registers. + struct { + Object *cr; // 0x0 (Clock control register) + Object *pllcfgr; // 0x4 (PLL configuration register) + Object *cfgr; // 0x8 (Clock configuration register) + Object *cir; // 0xC (Clock interrupt register) + Object *ahb1rstr; // 0x10 (AHB1 peripheral reset register) + Object *ahb2rstr; // 0x14 (AHB2 peripheral reset register) + Object *apb1rstr; // 0x20 (APB1 peripheral reset register) + Object *apb2rstr; // 0x24 (APB2 peripheral reset register) + Object *ahb1enr; // 0x30 (AHB1 peripheral clock register) + Object *ahb2enr; // 0x34 (AHB2 peripheral clock enable register) + Object *apb1enr; // 0x40 (APB1 peripheral clock enable register) + Object *apb2enr; // 0x44 (APB2 peripheral clock enable register) + Object *ahb1lpenr; // 0x50 (AHB1 peripheral clock enable in low power mode register) + Object *ahb2lpenr; // 0x54 (AHB2 peripheral clock enable in low power mode register) + Object *apb1lpenr; // 0x60 (APB1 peripheral clock enable in low power mode register) + Object *apb2lpenr; // 0x64 (APB2 peripheral clock enabled in low power mode register) + Object *bdcr; // 0x70 (Backup domain control register) + Object *csr; // 0x74 (Clock control & status register) + Object *sscgr; // 0x80 (Spread spectrum clock generation register) + Object *plli2scfgr; // 0x84 (PLLI2S configuration register) + } reg; + + struct { + + // CR (Clock control register) bitfields. + struct { + Object *hsion; // [0:0] Internal high-speed clock enable + Object *hsirdy; // [1:1] Internal high-speed clock ready flag + Object *hsitrim; // [3:7] Internal high-speed clock trimming + Object *hsical; // [8:15] Internal high-speed clock calibration + Object *hseon; // [16:16] HSE clock enable + Object *hserdy; // [17:17] HSE clock ready flag + Object *hsebyp; // [18:18] HSE clock bypass + Object *csson; // [19:19] Clock security system enable + Object *pllon; // [24:24] Main PLL (PLL) enable + Object *pllrdy; // [25:25] Main PLL (PLL) clock ready flag + Object *plli2son; // [26:26] PLLI2S enable + Object *plli2srdy; // [27:27] PLLI2S clock ready flag + } cr; + + // PLLCFGR (PLL configuration register) bitfields. + struct { + Object *pllm; // [0:5] Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + Object *plln; // [6:14] Main PLL (PLL) multiplication factor for VCO + Object *pllp; // [16:17] Main PLL (PLL) division factor for main system clock + Object *pllsrc; // [22:22] Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + Object *pllq; // [24:27] Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + } pllcfgr; + + // CFGR (Clock configuration register) bitfields. + struct { + Object *sw; // [0:1] System clock switch + Object *sws; // [2:3] System clock switch status + Object *hpre; // [4:7] AHB prescaler + Object *ppre1; // [10:12] APB Low speed prescaler (APB1) + Object *ppre2; // [13:15] APB high-speed prescaler (APB2) + Object *rtcpre; // [16:20] HSE division factor for RTC clock + Object *mco1; // [21:22] Microcontroller clock output 1 + Object *i2ssrc; // [23:23] I2S clock selection + Object *mco1pre; // [24:26] MCO1 prescaler + Object *mco2pre; // [27:29] MCO2 prescaler + Object *mco2; // [30:31] Microcontroller clock output 2 + } cfgr; + + // CIR (Clock interrupt register) bitfields. + struct { + Object *lsirdyf; // [0:0] LSI ready interrupt flag + Object *lserdyf; // [1:1] LSE ready interrupt flag + Object *hsirdyf; // [2:2] HSI ready interrupt flag + Object *hserdyf; // [3:3] HSE ready interrupt flag + Object *pllrdyf; // [4:4] Main PLL (PLL) ready interrupt flag + Object *plli2srdyf; // [5:5] PLLI2S ready interrupt flag + Object *cssf; // [7:7] Clock security system interrupt flag + Object *lsirdyie; // [8:8] LSI ready interrupt enable + Object *lserdyie; // [9:9] LSE ready interrupt enable + Object *hsirdyie; // [10:10] HSI ready interrupt enable + Object *hserdyie; // [11:11] HSE ready interrupt enable + Object *pllrdyie; // [12:12] Main PLL (PLL) ready interrupt enable + Object *plli2srdyie; // [13:13] PLLI2S ready interrupt enable + Object *lsirdyc; // [16:16] LSI ready interrupt clear + Object *lserdyc; // [17:17] LSE ready interrupt clear + Object *hsirdyc; // [18:18] HSI ready interrupt clear + Object *hserdyc; // [19:19] HSE ready interrupt clear + Object *pllrdyc; // [20:20] Main PLL(PLL) ready interrupt clear + Object *plli2srdyc; // [21:21] PLLI2S ready interrupt clear + Object *cssc; // [23:23] Clock security system interrupt clear + } cir; + + // AHB1RSTR (AHB1 peripheral reset register) bitfields. + struct { + Object *gpioarst; // [0:0] IO port A reset + Object *gpiobrst; // [1:1] IO port B reset + Object *gpiocrst; // [2:2] IO port C reset + Object *gpiodrst; // [3:3] IO port D reset + Object *gpioerst; // [4:4] IO port E reset + Object *gpiohrst; // [7:7] IO port H reset + Object *crcrst; // [12:12] CRC reset + Object *dma1rst; // [21:21] DMA2 reset + Object *dma2rst; // [22:22] DMA2 reset + } ahb1rstr; + + // AHB2RSTR (AHB2 peripheral reset register) bitfields. + struct { + Object *otgfsrst; // [7:7] USB OTG FS module reset + } ahb2rstr; + + // APB1RSTR (APB1 peripheral reset register) bitfields. + struct { + Object *tim2rst; // [0:0] TIM2 reset + Object *tim3rst; // [1:1] TIM3 reset + Object *tim4rst; // [2:2] TIM4 reset + Object *tim5rst; // [3:3] TIM5 reset + Object *wwdgrst; // [11:11] Window watchdog reset + Object *spi2rst; // [14:14] SPI 2 reset + Object *spi3rst; // [15:15] SPI 3 reset + Object *uart2rst; // [17:17] USART 2 reset + Object *i2c1rst; // [21:21] I2C 1 reset + Object *i2c2rst; // [22:22] I2C 2 reset + Object *i2c3rst; // [23:23] I2C3 reset + Object *pwrrst; // [28:28] Power interface reset + } apb1rstr; + + // APB2RSTR (APB2 peripheral reset register) bitfields. + struct { + Object *tim1rst; // [0:0] TIM1 reset + Object *usart1rst; // [4:4] USART1 reset + Object *usart6rst; // [5:5] USART6 reset + Object *adcrst; // [8:8] ADC interface reset (common to all ADCs) + Object *sdiorst; // [11:11] SDIO reset + Object *spi1rst; // [12:12] SPI 1 reset + Object *syscfgrst; // [14:14] System configuration controller reset + Object *tim9rst; // [16:16] TIM9 reset + Object *tim10rst; // [17:17] TIM10 reset + Object *tim11rst; // [18:18] TIM11 reset + } apb2rstr; + + // AHB1ENR (AHB1 peripheral clock register) bitfields. + struct { + Object *gpioaen; // [0:0] IO port A clock enable + Object *gpioben; // [1:1] IO port B clock enable + Object *gpiocen; // [2:2] IO port C clock enable + Object *gpioden; // [3:3] IO port D clock enable + Object *gpioeen; // [4:4] IO port E clock enable + Object *gpiohen; // [7:7] IO port H clock enable + Object *crcen; // [12:12] CRC clock enable + Object *dma1en; // [21:21] DMA1 clock enable + Object *dma2en; // [22:22] DMA2 clock enable + } ahb1enr; + + // AHB2ENR (AHB2 peripheral clock enable register) bitfields. + struct { + Object *otgfsen; // [7:7] USB OTG FS clock enable + } ahb2enr; + + // APB1ENR (APB1 peripheral clock enable register) bitfields. + struct { + Object *tim2en; // [0:0] TIM2 clock enable + Object *tim3en; // [1:1] TIM3 clock enable + Object *tim4en; // [2:2] TIM4 clock enable + Object *tim5en; // [3:3] TIM5 clock enable + Object *wwdgen; // [11:11] Window watchdog clock enable + Object *spi2en; // [14:14] SPI2 clock enable + Object *spi3en; // [15:15] SPI3 clock enable + Object *usart2en; // [17:17] USART 2 clock enable + Object *i2c1en; // [21:21] I2C1 clock enable + Object *i2c2en; // [22:22] I2C2 clock enable + Object *i2c3en; // [23:23] I2C3 clock enable + Object *pwren; // [28:28] Power interface clock enable + } apb1enr; + + // APB2ENR (APB2 peripheral clock enable register) bitfields. + struct { + Object *tim1en; // [0:0] TIM1 clock enable + Object *usart1en; // [4:4] USART1 clock enable + Object *usart6en; // [5:5] USART6 clock enable + Object *adc1en; // [8:8] ADC1 clock enable + Object *sdioen; // [11:11] SDIO clock enable + Object *spi1en; // [12:12] SPI1 clock enable + Object *spi4en; // [13:13] SPI4 clock enable + Object *syscfgen; // [14:14] System configuration controller clock enable + Object *tim9en; // [16:16] TIM9 clock enable + Object *tim10en; // [17:17] TIM10 clock enable + Object *tim11en; // [18:18] TIM11 clock enable + } apb2enr; + + // AHB1LPENR (AHB1 peripheral clock enable in low power mode register) bitfields. + struct { + Object *gpioalpen; // [0:0] IO port A clock enable during sleep mode + Object *gpioblpen; // [1:1] IO port B clock enable during Sleep mode + Object *gpioclpen; // [2:2] IO port C clock enable during Sleep mode + Object *gpiodlpen; // [3:3] IO port D clock enable during Sleep mode + Object *gpioelpen; // [4:4] IO port E clock enable during Sleep mode + Object *gpiohlpen; // [7:7] IO port H clock enable during Sleep mode + Object *crclpen; // [12:12] CRC clock enable during Sleep mode + Object *flitflpen; // [15:15] Flash interface clock enable during Sleep mode + Object *sram1lpen; // [16:16] SRAM 1interface clock enable during Sleep mode + Object *dma1lpen; // [21:21] DMA1 clock enable during Sleep mode + Object *dma2lpen; // [22:22] DMA2 clock enable during Sleep mode + } ahb1lpenr; + + // AHB2LPENR (AHB2 peripheral clock enable in low power mode register) bitfields. + struct { + Object *otgfslpen; // [7:7] USB OTG FS clock enable during Sleep mode + } ahb2lpenr; + + // APB1LPENR (APB1 peripheral clock enable in low power mode register) bitfields. + struct { + Object *tim2lpen; // [0:0] TIM2 clock enable during Sleep mode + Object *tim3lpen; // [1:1] TIM3 clock enable during Sleep mode + Object *tim4lpen; // [2:2] TIM4 clock enable during Sleep mode + Object *tim5lpen; // [3:3] TIM5 clock enable during Sleep mode + Object *wwdglpen; // [11:11] Window watchdog clock enable during Sleep mode + Object *spi2lpen; // [14:14] SPI2 clock enable during Sleep mode + Object *spi3lpen; // [15:15] SPI3 clock enable during Sleep mode + Object *usart2lpen; // [17:17] USART2 clock enable during Sleep mode + Object *i2c1lpen; // [21:21] I2C1 clock enable during Sleep mode + Object *i2c2lpen; // [22:22] I2C2 clock enable during Sleep mode + Object *i2c3lpen; // [23:23] I2C3 clock enable during Sleep mode + Object *pwrlpen; // [28:28] Power interface clock enable during Sleep mode + } apb1lpenr; + + // APB2LPENR (APB2 peripheral clock enabled in low power mode register) bitfields. + struct { + Object *tim1lpen; // [0:0] TIM1 clock enable during Sleep mode + Object *usart1lpen; // [4:4] USART1 clock enable during Sleep mode + Object *usart6lpen; // [5:5] USART6 clock enable during Sleep mode + Object *adc1lpen; // [8:8] ADC1 clock enable during Sleep mode + Object *sdiolpen; // [11:11] SDIO clock enable during Sleep mode + Object *spi1lpen; // [12:12] SPI 1 clock enable during Sleep mode + Object *spi4lpen; // [13:13] SPI4 clock enable during Sleep mode + Object *syscfglpen; // [14:14] System configuration controller clock enable during Sleep mode + Object *tim9lpen; // [16:16] TIM9 clock enable during sleep mode + Object *tim10lpen; // [17:17] TIM10 clock enable during Sleep mode + Object *tim11lpen; // [18:18] TIM11 clock enable during Sleep mode + } apb2lpenr; + + // BDCR (Backup domain control register) bitfields. + struct { + Object *lseon; // [0:0] External low-speed oscillator enable + Object *lserdy; // [1:1] External low-speed oscillator ready + Object *lsebyp; // [2:2] External low-speed oscillator bypass + Object *rtcsel; // [8:9] RTC clock source selection + Object *rtcen; // [15:15] RTC clock enable + Object *bdrst; // [16:16] Backup domain software reset + } bdcr; + + // CSR (Clock control & status register) bitfields. + struct { + Object *lsion; // [0:0] Internal low-speed oscillator enable + Object *lsirdy; // [1:1] Internal low-speed oscillator ready + Object *rmvf; // [24:24] Remove reset flag + Object *borrstf; // [25:25] BOR reset flag + Object *padrstf; // [26:26] PIN reset flag + Object *porrstf; // [27:27] POR/PDR reset flag + Object *sftrstf; // [28:28] Software reset flag + Object *wdgrstf; // [29:29] Independent watchdog reset flag + Object *wwdgrstf; // [30:30] Window watchdog reset flag + Object *lpwrrstf; // [31:31] Low-power reset flag + } csr; + + // SSCGR (Spread spectrum clock generation register) bitfields. + struct { + Object *modper; // [0:12] Modulation period + Object *incstep; // [13:27] Incrementation step + Object *spreadsel; // [30:30] Spread Select + Object *sscgen; // [31:31] Spread spectrum modulation enable + } sscgr; + + // PLLI2SCFGR (PLLI2S configuration register) bitfields. + struct { + Object *plli2snx; // [6:14] PLLI2S multiplication factor for VCO + Object *plli2srx; // [28:30] PLLI2S division factor for I2S clocks + } plli2scfgr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RCCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RCC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/rtc.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/rtc.c new file mode 100644 index 0000000000..d205e8e70e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/rtc.c @@ -0,0 +1,493 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_rtc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.tr = cm_object_get_child_by_name(obj, "TR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f4.reg.prer = cm_object_get_child_by_name(obj, "PRER"); + state->u.f4.reg.wutr = cm_object_get_child_by_name(obj, "WUTR"); + state->u.f4.reg.calibr = cm_object_get_child_by_name(obj, "CALIBR"); + state->u.f4.reg.alrmar = cm_object_get_child_by_name(obj, "ALRMAR"); + state->u.f4.reg.alrmbr = cm_object_get_child_by_name(obj, "ALRMBR"); + state->u.f4.reg.wpr = cm_object_get_child_by_name(obj, "WPR"); + state->u.f4.reg.ssr = cm_object_get_child_by_name(obj, "SSR"); + state->u.f4.reg.shiftr = cm_object_get_child_by_name(obj, "SHIFTR"); + state->u.f4.reg.tstr = cm_object_get_child_by_name(obj, "TSTR"); + state->u.f4.reg.tsdr = cm_object_get_child_by_name(obj, "TSDR"); + state->u.f4.reg.tsssr = cm_object_get_child_by_name(obj, "TSSSR"); + state->u.f4.reg.calr = cm_object_get_child_by_name(obj, "CALR"); + state->u.f4.reg.tafcr = cm_object_get_child_by_name(obj, "TAFCR"); + state->u.f4.reg.alrmassr = cm_object_get_child_by_name(obj, "ALRMASSR"); + state->u.f4.reg.alrmbssr = cm_object_get_child_by_name(obj, "ALRMBSSR"); + state->u.f4.reg.bkp0r = cm_object_get_child_by_name(obj, "BKP0R"); + state->u.f4.reg.bkp1r = cm_object_get_child_by_name(obj, "BKP1R"); + state->u.f4.reg.bkp2r = cm_object_get_child_by_name(obj, "BKP2R"); + state->u.f4.reg.bkp3r = cm_object_get_child_by_name(obj, "BKP3R"); + state->u.f4.reg.bkp4r = cm_object_get_child_by_name(obj, "BKP4R"); + state->u.f4.reg.bkp5r = cm_object_get_child_by_name(obj, "BKP5R"); + state->u.f4.reg.bkp6r = cm_object_get_child_by_name(obj, "BKP6R"); + state->u.f4.reg.bkp7r = cm_object_get_child_by_name(obj, "BKP7R"); + state->u.f4.reg.bkp8r = cm_object_get_child_by_name(obj, "BKP8R"); + state->u.f4.reg.bkp9r = cm_object_get_child_by_name(obj, "BKP9R"); + state->u.f4.reg.bkp10r = cm_object_get_child_by_name(obj, "BKP10R"); + state->u.f4.reg.bkp11r = cm_object_get_child_by_name(obj, "BKP11R"); + state->u.f4.reg.bkp12r = cm_object_get_child_by_name(obj, "BKP12R"); + state->u.f4.reg.bkp13r = cm_object_get_child_by_name(obj, "BKP13R"); + state->u.f4.reg.bkp14r = cm_object_get_child_by_name(obj, "BKP14R"); + state->u.f4.reg.bkp15r = cm_object_get_child_by_name(obj, "BKP15R"); + state->u.f4.reg.bkp16r = cm_object_get_child_by_name(obj, "BKP16R"); + state->u.f4.reg.bkp17r = cm_object_get_child_by_name(obj, "BKP17R"); + state->u.f4.reg.bkp18r = cm_object_get_child_by_name(obj, "BKP18R"); + state->u.f4.reg.bkp19r = cm_object_get_child_by_name(obj, "BKP19R"); + + + // TR bitfields. + state->u.f4.fld.tr.su = cm_object_get_child_by_name(state->u.f4.reg.tr, "SU"); + state->u.f4.fld.tr.st = cm_object_get_child_by_name(state->u.f4.reg.tr, "ST"); + state->u.f4.fld.tr.mnu = cm_object_get_child_by_name(state->u.f4.reg.tr, "MNU"); + state->u.f4.fld.tr.mnt = cm_object_get_child_by_name(state->u.f4.reg.tr, "MNT"); + state->u.f4.fld.tr.hu = cm_object_get_child_by_name(state->u.f4.reg.tr, "HU"); + state->u.f4.fld.tr.ht = cm_object_get_child_by_name(state->u.f4.reg.tr, "HT"); + state->u.f4.fld.tr.pm = cm_object_get_child_by_name(state->u.f4.reg.tr, "PM"); + + // DR bitfields. + state->u.f4.fld.dr.du = cm_object_get_child_by_name(state->u.f4.reg.dr, "DU"); + state->u.f4.fld.dr.dt = cm_object_get_child_by_name(state->u.f4.reg.dr, "DT"); + state->u.f4.fld.dr.mu = cm_object_get_child_by_name(state->u.f4.reg.dr, "MU"); + state->u.f4.fld.dr.mt = cm_object_get_child_by_name(state->u.f4.reg.dr, "MT"); + state->u.f4.fld.dr.wdu = cm_object_get_child_by_name(state->u.f4.reg.dr, "WDU"); + state->u.f4.fld.dr.yu = cm_object_get_child_by_name(state->u.f4.reg.dr, "YU"); + state->u.f4.fld.dr.yt = cm_object_get_child_by_name(state->u.f4.reg.dr, "YT"); + + // CR bitfields. + state->u.f4.fld.cr.wcksel = cm_object_get_child_by_name(state->u.f4.reg.cr, "WCKSEL"); + state->u.f4.fld.cr.tsedge = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSEDGE"); + state->u.f4.fld.cr.refckon = cm_object_get_child_by_name(state->u.f4.reg.cr, "REFCKON"); + state->u.f4.fld.cr.bypshad = cm_object_get_child_by_name(state->u.f4.reg.cr, "BYPSHAD"); + state->u.f4.fld.cr.fmt = cm_object_get_child_by_name(state->u.f4.reg.cr, "FMT"); + state->u.f4.fld.cr.dce = cm_object_get_child_by_name(state->u.f4.reg.cr, "DCE"); + state->u.f4.fld.cr.alrae = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRAE"); + state->u.f4.fld.cr.alrbe = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRBE"); + state->u.f4.fld.cr.wute = cm_object_get_child_by_name(state->u.f4.reg.cr, "WUTE"); + state->u.f4.fld.cr.tse = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSE"); + state->u.f4.fld.cr.alraie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRAIE"); + state->u.f4.fld.cr.alrbie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRBIE"); + state->u.f4.fld.cr.wutie = cm_object_get_child_by_name(state->u.f4.reg.cr, "WUTIE"); + state->u.f4.fld.cr.tsie = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSIE"); + state->u.f4.fld.cr.add1h = cm_object_get_child_by_name(state->u.f4.reg.cr, "ADD1H"); + state->u.f4.fld.cr.sub1h = cm_object_get_child_by_name(state->u.f4.reg.cr, "SUB1H"); + state->u.f4.fld.cr.bkp = cm_object_get_child_by_name(state->u.f4.reg.cr, "BKP"); + state->u.f4.fld.cr.cosel = cm_object_get_child_by_name(state->u.f4.reg.cr, "COSEL"); + state->u.f4.fld.cr.pol = cm_object_get_child_by_name(state->u.f4.reg.cr, "POL"); + state->u.f4.fld.cr.osel = cm_object_get_child_by_name(state->u.f4.reg.cr, "OSEL"); + state->u.f4.fld.cr.coe = cm_object_get_child_by_name(state->u.f4.reg.cr, "COE"); + + // ISR bitfields. + state->u.f4.fld.isr.alrawf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRAWF"); + state->u.f4.fld.isr.alrbwf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRBWF"); + state->u.f4.fld.isr.wutwf = cm_object_get_child_by_name(state->u.f4.reg.isr, "WUTWF"); + state->u.f4.fld.isr.shpf = cm_object_get_child_by_name(state->u.f4.reg.isr, "SHPF"); + state->u.f4.fld.isr.inits = cm_object_get_child_by_name(state->u.f4.reg.isr, "INITS"); + state->u.f4.fld.isr.rsf = cm_object_get_child_by_name(state->u.f4.reg.isr, "RSF"); + state->u.f4.fld.isr.initf = cm_object_get_child_by_name(state->u.f4.reg.isr, "INITF"); + state->u.f4.fld.isr.init = cm_object_get_child_by_name(state->u.f4.reg.isr, "INIT"); + state->u.f4.fld.isr.alraf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRAF"); + state->u.f4.fld.isr.alrbf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRBF"); + state->u.f4.fld.isr.wutf = cm_object_get_child_by_name(state->u.f4.reg.isr, "WUTF"); + state->u.f4.fld.isr.tsf = cm_object_get_child_by_name(state->u.f4.reg.isr, "TSF"); + state->u.f4.fld.isr.tsovf = cm_object_get_child_by_name(state->u.f4.reg.isr, "TSOVF"); + state->u.f4.fld.isr.tamp1f = cm_object_get_child_by_name(state->u.f4.reg.isr, "TAMP1F"); + state->u.f4.fld.isr.tamp2f = cm_object_get_child_by_name(state->u.f4.reg.isr, "TAMP2F"); + state->u.f4.fld.isr.recalpf = cm_object_get_child_by_name(state->u.f4.reg.isr, "RECALPF"); + + // PRER bitfields. + state->u.f4.fld.prer.prediv_s = cm_object_get_child_by_name(state->u.f4.reg.prer, "PREDIV_S"); + state->u.f4.fld.prer.prediv_a = cm_object_get_child_by_name(state->u.f4.reg.prer, "PREDIV_A"); + + // WUTR bitfields. + state->u.f4.fld.wutr.wut = cm_object_get_child_by_name(state->u.f4.reg.wutr, "WUT"); + + // CALIBR bitfields. + state->u.f4.fld.calibr.dc = cm_object_get_child_by_name(state->u.f4.reg.calibr, "DC"); + state->u.f4.fld.calibr.dcs = cm_object_get_child_by_name(state->u.f4.reg.calibr, "DCS"); + + // ALRMAR bitfields. + state->u.f4.fld.alrmar.su = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "SU"); + state->u.f4.fld.alrmar.st = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "ST"); + state->u.f4.fld.alrmar.msk1 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK1"); + state->u.f4.fld.alrmar.mnu = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MNU"); + state->u.f4.fld.alrmar.mnt = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MNT"); + state->u.f4.fld.alrmar.msk2 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK2"); + state->u.f4.fld.alrmar.hu = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "HU"); + state->u.f4.fld.alrmar.ht = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "HT"); + state->u.f4.fld.alrmar.pm = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "PM"); + state->u.f4.fld.alrmar.msk3 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK3"); + state->u.f4.fld.alrmar.du = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "DU"); + state->u.f4.fld.alrmar.dt = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "DT"); + state->u.f4.fld.alrmar.wdsel = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "WDSEL"); + state->u.f4.fld.alrmar.msk4 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK4"); + + // ALRMBR bitfields. + state->u.f4.fld.alrmbr.su = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "SU"); + state->u.f4.fld.alrmbr.st = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "ST"); + state->u.f4.fld.alrmbr.msk1 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK1"); + state->u.f4.fld.alrmbr.mnu = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MNU"); + state->u.f4.fld.alrmbr.mnt = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MNT"); + state->u.f4.fld.alrmbr.msk2 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK2"); + state->u.f4.fld.alrmbr.hu = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "HU"); + state->u.f4.fld.alrmbr.ht = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "HT"); + state->u.f4.fld.alrmbr.pm = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "PM"); + state->u.f4.fld.alrmbr.msk3 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK3"); + state->u.f4.fld.alrmbr.du = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "DU"); + state->u.f4.fld.alrmbr.dt = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "DT"); + state->u.f4.fld.alrmbr.wdsel = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "WDSEL"); + state->u.f4.fld.alrmbr.msk4 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK4"); + + // WPR bitfields. + state->u.f4.fld.wpr.key = cm_object_get_child_by_name(state->u.f4.reg.wpr, "KEY"); + + // SSR bitfields. + state->u.f4.fld.ssr.ss = cm_object_get_child_by_name(state->u.f4.reg.ssr, "SS"); + + // SHIFTR bitfields. + state->u.f4.fld.shiftr.subfs = cm_object_get_child_by_name(state->u.f4.reg.shiftr, "SUBFS"); + state->u.f4.fld.shiftr.add1s = cm_object_get_child_by_name(state->u.f4.reg.shiftr, "ADD1S"); + + // TSTR bitfields. + state->u.f4.fld.tstr.su = cm_object_get_child_by_name(state->u.f4.reg.tstr, "SU"); + state->u.f4.fld.tstr.st = cm_object_get_child_by_name(state->u.f4.reg.tstr, "ST"); + state->u.f4.fld.tstr.mnu = cm_object_get_child_by_name(state->u.f4.reg.tstr, "MNU"); + state->u.f4.fld.tstr.mnt = cm_object_get_child_by_name(state->u.f4.reg.tstr, "MNT"); + state->u.f4.fld.tstr.hu = cm_object_get_child_by_name(state->u.f4.reg.tstr, "HU"); + state->u.f4.fld.tstr.ht = cm_object_get_child_by_name(state->u.f4.reg.tstr, "HT"); + state->u.f4.fld.tstr.pm = cm_object_get_child_by_name(state->u.f4.reg.tstr, "PM"); + + // TSDR bitfields. + state->u.f4.fld.tsdr.du = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "DU"); + state->u.f4.fld.tsdr.dt = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "DT"); + state->u.f4.fld.tsdr.mu = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "MU"); + state->u.f4.fld.tsdr.mt = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "MT"); + state->u.f4.fld.tsdr.wdu = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "WDU"); + + // TSSSR bitfields. + state->u.f4.fld.tsssr.ss = cm_object_get_child_by_name(state->u.f4.reg.tsssr, "SS"); + + // CALR bitfields. + state->u.f4.fld.calr.calm = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALM"); + state->u.f4.fld.calr.calw16 = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALW16"); + state->u.f4.fld.calr.calw8 = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALW8"); + state->u.f4.fld.calr.calp = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALP"); + + // TAFCR bitfields. + state->u.f4.fld.tafcr.tamp1e = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1E"); + state->u.f4.fld.tafcr.tamp1trg = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1TRG"); + state->u.f4.fld.tafcr.tampie = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPIE"); + state->u.f4.fld.tafcr.tamp2e = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP2E"); + state->u.f4.fld.tafcr.tamp2trg = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP2TRG"); + state->u.f4.fld.tafcr.tampts = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPTS"); + state->u.f4.fld.tafcr.tampfreq = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPFREQ"); + state->u.f4.fld.tafcr.tampflt = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPFLT"); + state->u.f4.fld.tafcr.tampprch = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPPRCH"); + state->u.f4.fld.tafcr.tamppudis = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPPUDIS"); + state->u.f4.fld.tafcr.tamp1insel = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1INSEL"); + state->u.f4.fld.tafcr.tsinsel = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TSINSEL"); + state->u.f4.fld.tafcr.alarmouttype = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "ALARMOUTTYPE"); + + // ALRMASSR bitfields. + state->u.f4.fld.alrmassr.ss = cm_object_get_child_by_name(state->u.f4.reg.alrmassr, "SS"); + state->u.f4.fld.alrmassr.maskss = cm_object_get_child_by_name(state->u.f4.reg.alrmassr, "MASKSS"); + + // ALRMBSSR bitfields. + state->u.f4.fld.alrmbssr.ss = cm_object_get_child_by_name(state->u.f4.reg.alrmbssr, "SS"); + state->u.f4.fld.alrmbssr.maskss = cm_object_get_child_by_name(state->u.f4.reg.alrmbssr, "MASKSS"); + + // BKP0R bitfields. + state->u.f4.fld.bkp0r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp0r, "BKP"); + + // BKP1R bitfields. + state->u.f4.fld.bkp1r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp1r, "BKP"); + + // BKP2R bitfields. + state->u.f4.fld.bkp2r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp2r, "BKP"); + + // BKP3R bitfields. + state->u.f4.fld.bkp3r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp3r, "BKP"); + + // BKP4R bitfields. + state->u.f4.fld.bkp4r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp4r, "BKP"); + + // BKP5R bitfields. + state->u.f4.fld.bkp5r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp5r, "BKP"); + + // BKP6R bitfields. + state->u.f4.fld.bkp6r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp6r, "BKP"); + + // BKP7R bitfields. + state->u.f4.fld.bkp7r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp7r, "BKP"); + + // BKP8R bitfields. + state->u.f4.fld.bkp8r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp8r, "BKP"); + + // BKP9R bitfields. + state->u.f4.fld.bkp9r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp9r, "BKP"); + + // BKP10R bitfields. + state->u.f4.fld.bkp10r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp10r, "BKP"); + + // BKP11R bitfields. + state->u.f4.fld.bkp11r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp11r, "BKP"); + + // BKP12R bitfields. + state->u.f4.fld.bkp12r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp12r, "BKP"); + + // BKP13R bitfields. + state->u.f4.fld.bkp13r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp13r, "BKP"); + + // BKP14R bitfields. + state->u.f4.fld.bkp14r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp14r, "BKP"); + + // BKP15R bitfields. + state->u.f4.fld.bkp15r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp15r, "BKP"); + + // BKP16R bitfields. + state->u.f4.fld.bkp16r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp16r, "BKP"); + + // BKP17R bitfields. + state->u.f4.fld.bkp17r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp17r, "BKP"); + + // BKP18R bitfields. + state->u.f4.fld.bkp18r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp18r, "BKP"); + + // BKP19R bitfields. + state->u.f4.fld.bkp19r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp19r, "BKP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rtc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rtc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rtc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rtc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rtc_is_enabled(Object *obj) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rtc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RTCState *state = STM32_RTC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rtc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RTC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RTCState *state = STM32_RTC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RTC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_rtc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rtc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rtc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rtc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rtc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RTCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rtc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RTC); +} + +static void stm32_rtc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rtc_reset_callback; + dc->realize = stm32_rtc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rtc_is_enabled; +} + +static const TypeInfo stm32_rtc_type_info = { + .name = TYPE_STM32_RTC, + .parent = TYPE_STM32_RTC_PARENT, + .instance_init = stm32_rtc_instance_init_callback, + .instance_size = sizeof(STM32RTCState), + .class_init = stm32_rtc_class_init_callback, + .class_size = sizeof(STM32RTCClass) }; + +static void stm32_rtc_register_types(void) +{ + type_register_static(&stm32_rtc_type_info); +} + +type_init(stm32_rtc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/rtc.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/rtc.h new file mode 100644 index 0000000000..6ef6b5d9d7 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/rtc.h @@ -0,0 +1,436 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RTC_H_ +#define STM32_RTC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RTC DEVICE_PATH_STM32 "RTC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RTC TYPE_STM32_PREFIX "rtc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RTC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RTCParentClass; +typedef PeripheralState STM32RTCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RTCClass, (obj), TYPE_STM32_RTC) +#define STM32_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RTCClass, (klass), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentClass parent_class; + // public: + + // None, so far. +} STM32RTCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RTC_STATE(obj) \ + OBJECT_CHECK(STM32RTCState, (obj), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RTC (Real-time clock) registers. + struct { + Object *tr; // 0x0 (Time register) + Object *dr; // 0x4 (Date register) + Object *cr; // 0x8 (Control register) + Object *isr; // 0xC (Initialization and status register) + Object *prer; // 0x10 (Prescaler register) + Object *wutr; // 0x14 (Wakeup timer register) + Object *calibr; // 0x18 (Calibration register) + Object *alrmar; // 0x1C (Alarm A register) + Object *alrmbr; // 0x20 (Alarm B register) + Object *wpr; // 0x24 (Write protection register) + Object *ssr; // 0x28 (Sub second register) + Object *shiftr; // 0x2C (Shift control register) + Object *tstr; // 0x30 (Time stamp time register) + Object *tsdr; // 0x34 (Time stamp date register) + Object *tsssr; // 0x38 (Timestamp sub second register) + Object *calr; // 0x3C (Calibration register) + Object *tafcr; // 0x40 (Tamper and alternate function configuration register) + Object *alrmassr; // 0x44 (Alarm A sub second register) + Object *alrmbssr; // 0x48 (Alarm B sub second register) + Object *bkp0r; // 0x50 (Backup register) + Object *bkp1r; // 0x54 (Backup register) + Object *bkp2r; // 0x58 (Backup register) + Object *bkp3r; // 0x5C (Backup register) + Object *bkp4r; // 0x60 (Backup register) + Object *bkp5r; // 0x64 (Backup register) + Object *bkp6r; // 0x68 (Backup register) + Object *bkp7r; // 0x6C (Backup register) + Object *bkp8r; // 0x70 (Backup register) + Object *bkp9r; // 0x74 (Backup register) + Object *bkp10r; // 0x78 (Backup register) + Object *bkp11r; // 0x7C (Backup register) + Object *bkp12r; // 0x80 (Backup register) + Object *bkp13r; // 0x84 (Backup register) + Object *bkp14r; // 0x88 (Backup register) + Object *bkp15r; // 0x8C (Backup register) + Object *bkp16r; // 0x90 (Backup register) + Object *bkp17r; // 0x94 (Backup register) + Object *bkp18r; // 0x98 (Backup register) + Object *bkp19r; // 0x9C (Backup register) + } reg; + + struct { + + // TR (Time register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + } tr; + + // DR (Date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + Object *yu; // [16:19] Year units in BCD format + Object *yt; // [20:23] Year tens in BCD format + } dr; + + // CR (Control register) bitfields. + struct { + Object *wcksel; // [0:2] Wakeup clock selection + Object *tsedge; // [3:3] Time-stamp event active edge + Object *refckon; // [4:4] Reference clock detection enable (50 or 60 Hz) + Object *bypshad; // [5:5] Bypass the shadow registers + Object *fmt; // [6:6] Hour format + Object *dce; // [7:7] Coarse digital calibration enable + Object *alrae; // [8:8] Alarm A enable + Object *alrbe; // [9:9] Alarm B enable + Object *wute; // [10:10] Wakeup timer enable + Object *tse; // [11:11] Time stamp enable + Object *alraie; // [12:12] Alarm A interrupt enable + Object *alrbie; // [13:13] Alarm B interrupt enable + Object *wutie; // [14:14] Wakeup timer interrupt enable + Object *tsie; // [15:15] Time-stamp interrupt enable + Object *add1h; // [16:16] Add 1 hour (summer time change) + Object *sub1h; // [17:17] Subtract 1 hour (winter time change) + Object *bkp; // [18:18] Backup + Object *cosel; // [19:19] Calibration Output selection + Object *pol; // [20:20] Output polarity + Object *osel; // [21:22] Output selection + Object *coe; // [23:23] Calibration output enable + } cr; + + // ISR (Initialization and status register) bitfields. + struct { + Object *alrawf; // [0:0] Alarm A write flag + Object *alrbwf; // [1:1] Alarm B write flag + Object *wutwf; // [2:2] Wakeup timer write flag + Object *shpf; // [3:3] Shift operation pending + Object *inits; // [4:4] Initialization status flag + Object *rsf; // [5:5] Registers synchronization flag + Object *initf; // [6:6] Initialization flag + Object *init; // [7:7] Initialization mode + Object *alraf; // [8:8] Alarm A flag + Object *alrbf; // [9:9] Alarm B flag + Object *wutf; // [10:10] Wakeup timer flag + Object *tsf; // [11:11] Time-stamp flag + Object *tsovf; // [12:12] Time-stamp overflow flag + Object *tamp1f; // [13:13] Tamper detection flag + Object *tamp2f; // [14:14] TAMPER2 detection flag + Object *recalpf; // [16:16] Recalibration pending Flag + } isr; + + // PRER (Prescaler register) bitfields. + struct { + Object *prediv_s; // [0:14] Synchronous prescaler factor + Object *prediv_a; // [16:22] Asynchronous prescaler factor + } prer; + + // WUTR (Wakeup timer register) bitfields. + struct { + Object *wut; // [0:15] Wakeup auto-reload value bits + } wutr; + + // CALIBR (Calibration register) bitfields. + struct { + Object *dc; // [0:4] Digital calibration + Object *dcs; // [7:7] Digital calibration sign + } calibr; + + // ALRMAR (Alarm A register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *msk1; // [7:7] Alarm A seconds mask + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *msk2; // [15:15] Alarm A minutes mask + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + Object *msk3; // [23:23] Alarm A hours mask + Object *du; // [24:27] Date units or day in BCD format + Object *dt; // [28:29] Date tens in BCD format + Object *wdsel; // [30:30] Week day selection + Object *msk4; // [31:31] Alarm A date mask + } alrmar; + + // ALRMBR (Alarm B register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *msk1; // [7:7] Alarm B seconds mask + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *msk2; // [15:15] Alarm B minutes mask + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + Object *msk3; // [23:23] Alarm B hours mask + Object *du; // [24:27] Date units or day in BCD format + Object *dt; // [28:29] Date tens in BCD format + Object *wdsel; // [30:30] Week day selection + Object *msk4; // [31:31] Alarm B date mask + } alrmbr; + + // WPR (Write protection register) bitfields. + struct { + Object *key; // [0:7] Write protection key + } wpr; + + // SSR (Sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } ssr; + + // SHIFTR (Shift control register) bitfields. + struct { + Object *subfs; // [0:14] Subtract a fraction of a second + Object *add1s; // [31:31] Add one second + } shiftr; + + // TSTR (Time stamp time register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + } tstr; + + // TSDR (Time stamp date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + } tsdr; + + // TSSSR (Timestamp sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } tsssr; + + // CALR (Calibration register) bitfields. + struct { + Object *calm; // [0:8] Calibration minus + Object *calw16; // [13:13] Use a 16-second calibration cycle period + Object *calw8; // [14:14] Use an 8-second calibration cycle period + Object *calp; // [15:15] Increase frequency of RTC by 488.5 ppm + } calr; + + // TAFCR (Tamper and alternate function configuration register) bitfields. + struct { + Object *tamp1e; // [0:0] Tamper 1 detection enable + Object *tamp1trg; // [1:1] Active level for tamper 1 + Object *tampie; // [2:2] Tamper interrupt enable + Object *tamp2e; // [3:3] Tamper 2 detection enable + Object *tamp2trg; // [4:4] Active level for tamper 2 + Object *tampts; // [7:7] Activate timestamp on tamper detection event + Object *tampfreq; // [8:10] Tamper sampling frequency + Object *tampflt; // [11:12] Tamper filter count + Object *tampprch; // [13:14] Tamper precharge duration + Object *tamppudis; // [15:15] TAMPER pull-up disable + Object *tamp1insel; // [16:16] TAMPER1 mapping + Object *tsinsel; // [17:17] TIMESTAMP mapping + Object *alarmouttype; // [18:18] AFO_ALARM output type + } tafcr; + + // ALRMASSR (Alarm A sub second register) bitfields. + struct { + Object *ss; // [0:14] Sub seconds value + Object *maskss; // [24:27] Mask the most-significant bits starting at this bit + } alrmassr; + + // ALRMBSSR (Alarm B sub second register) bitfields. + struct { + Object *ss; // [0:14] Sub seconds value + Object *maskss; // [24:27] Mask the most-significant bits starting at this bit + } alrmbssr; + + // BKP0R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp0r; + + // BKP1R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp1r; + + // BKP2R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp2r; + + // BKP3R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp3r; + + // BKP4R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp4r; + + // BKP5R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp5r; + + // BKP6R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp6r; + + // BKP7R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp7r; + + // BKP8R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp8r; + + // BKP9R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp9r; + + // BKP10R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp10r; + + // BKP11R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp11r; + + // BKP12R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp12r; + + // BKP13R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp13r; + + // BKP14R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp14r; + + // BKP15R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp15r; + + // BKP16R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp16r; + + // BKP17R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp17r; + + // BKP18R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp18r; + + // BKP19R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp19r; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RTCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RTC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/sdio.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/sdio.c new file mode 100644 index 0000000000..46f699c5d2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/sdio.c @@ -0,0 +1,386 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_sdio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.power = cm_object_get_child_by_name(obj, "POWER"); + state->u.f4.reg.clkcr = cm_object_get_child_by_name(obj, "CLKCR"); + state->u.f4.reg.arg = cm_object_get_child_by_name(obj, "ARG"); + state->u.f4.reg.cmd = cm_object_get_child_by_name(obj, "CMD"); + state->u.f4.reg.respcmd = cm_object_get_child_by_name(obj, "RESPCMD"); + state->u.f4.reg.resp1 = cm_object_get_child_by_name(obj, "RESP1"); + state->u.f4.reg.resp2 = cm_object_get_child_by_name(obj, "RESP2"); + state->u.f4.reg.resp3 = cm_object_get_child_by_name(obj, "RESP3"); + state->u.f4.reg.resp4 = cm_object_get_child_by_name(obj, "RESP4"); + state->u.f4.reg.dtimer = cm_object_get_child_by_name(obj, "DTIMER"); + state->u.f4.reg.dlen = cm_object_get_child_by_name(obj, "DLEN"); + state->u.f4.reg.dctrl = cm_object_get_child_by_name(obj, "DCTRL"); + state->u.f4.reg.dcount = cm_object_get_child_by_name(obj, "DCOUNT"); + state->u.f4.reg.sta = cm_object_get_child_by_name(obj, "STA"); + state->u.f4.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f4.reg.mask = cm_object_get_child_by_name(obj, "MASK"); + state->u.f4.reg.fifocnt = cm_object_get_child_by_name(obj, "FIFOCNT"); + state->u.f4.reg.fifo = cm_object_get_child_by_name(obj, "FIFO"); + + + // POWER bitfields. + state->u.f4.fld.power.pwrctrl = cm_object_get_child_by_name(state->u.f4.reg.power, "PWRCTRL"); + + // CLKCR bitfields. + state->u.f4.fld.clkcr.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "CLKDIV"); + state->u.f4.fld.clkcr.clken = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "CLKEN"); + state->u.f4.fld.clkcr.pwrsav = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "PWRSAV"); + state->u.f4.fld.clkcr.bypass = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "BYPASS"); + state->u.f4.fld.clkcr.widbus = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "WIDBUS"); + state->u.f4.fld.clkcr.negedge = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "NEGEDGE"); + state->u.f4.fld.clkcr.hwfc_en = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "HWFC_EN"); + + // ARG bitfields. + state->u.f4.fld.arg.cmdarg = cm_object_get_child_by_name(state->u.f4.reg.arg, "CMDARG"); + + // CMD bitfields. + state->u.f4.fld.cmd.cmdindex = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CMDINDEX"); + state->u.f4.fld.cmd.waitresp = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITRESP"); + state->u.f4.fld.cmd.waitint = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITINT"); + state->u.f4.fld.cmd.waitpend = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITPEND"); + state->u.f4.fld.cmd.cpsmen = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CPSMEN"); + state->u.f4.fld.cmd.sdiosuspend = cm_object_get_child_by_name(state->u.f4.reg.cmd, "SDIOSuspend"); + state->u.f4.fld.cmd.encmdcompl = cm_object_get_child_by_name(state->u.f4.reg.cmd, "ENCMDcompl"); + state->u.f4.fld.cmd.nien = cm_object_get_child_by_name(state->u.f4.reg.cmd, "nIEN"); + state->u.f4.fld.cmd.ce_atacmd = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CE_ATACMD"); + + // RESPCMD bitfields. + state->u.f4.fld.respcmd.respcmd = cm_object_get_child_by_name(state->u.f4.reg.respcmd, "RESPCMD"); + + // RESP1 bitfields. + state->u.f4.fld.resp1.cardstatus1 = cm_object_get_child_by_name(state->u.f4.reg.resp1, "CARDSTATUS1"); + + // RESP2 bitfields. + state->u.f4.fld.resp2.cardstatus2 = cm_object_get_child_by_name(state->u.f4.reg.resp2, "CARDSTATUS2"); + + // RESP3 bitfields. + state->u.f4.fld.resp3.cardstatus3 = cm_object_get_child_by_name(state->u.f4.reg.resp3, "CARDSTATUS3"); + + // RESP4 bitfields. + state->u.f4.fld.resp4.cardstatus4 = cm_object_get_child_by_name(state->u.f4.reg.resp4, "CARDSTATUS4"); + + // DTIMER bitfields. + state->u.f4.fld.dtimer.datatime = cm_object_get_child_by_name(state->u.f4.reg.dtimer, "DATATIME"); + + // DLEN bitfields. + state->u.f4.fld.dlen.datalength = cm_object_get_child_by_name(state->u.f4.reg.dlen, "DATALENGTH"); + + // DCTRL bitfields. + state->u.f4.fld.dctrl.dten = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTEN"); + state->u.f4.fld.dctrl.dtdir = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTDIR"); + state->u.f4.fld.dctrl.dtmode = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTMODE"); + state->u.f4.fld.dctrl.dmaen = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DMAEN"); + state->u.f4.fld.dctrl.dblocksize = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DBLOCKSIZE"); + state->u.f4.fld.dctrl.rwstart = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWSTART"); + state->u.f4.fld.dctrl.rwstop = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWSTOP"); + state->u.f4.fld.dctrl.rwmod = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWMOD"); + state->u.f4.fld.dctrl.sdioen = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "SDIOEN"); + + // DCOUNT bitfields. + state->u.f4.fld.dcount.datacount = cm_object_get_child_by_name(state->u.f4.reg.dcount, "DATACOUNT"); + + // STA bitfields. + state->u.f4.fld.sta.ccrcfail = cm_object_get_child_by_name(state->u.f4.reg.sta, "CCRCFAIL"); + state->u.f4.fld.sta.dcrcfail = cm_object_get_child_by_name(state->u.f4.reg.sta, "DCRCFAIL"); + state->u.f4.fld.sta.ctimeout = cm_object_get_child_by_name(state->u.f4.reg.sta, "CTIMEOUT"); + state->u.f4.fld.sta.dtimeout = cm_object_get_child_by_name(state->u.f4.reg.sta, "DTIMEOUT"); + state->u.f4.fld.sta.txunderr = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXUNDERR"); + state->u.f4.fld.sta.rxoverr = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXOVERR"); + state->u.f4.fld.sta.cmdrend = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDREND"); + state->u.f4.fld.sta.cmdsent = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDSENT"); + state->u.f4.fld.sta.dataend = cm_object_get_child_by_name(state->u.f4.reg.sta, "DATAEND"); + state->u.f4.fld.sta.stbiterr = cm_object_get_child_by_name(state->u.f4.reg.sta, "STBITERR"); + state->u.f4.fld.sta.dbckend = cm_object_get_child_by_name(state->u.f4.reg.sta, "DBCKEND"); + state->u.f4.fld.sta.cmdact = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDACT"); + state->u.f4.fld.sta.txact = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXACT"); + state->u.f4.fld.sta.rxact = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXACT"); + state->u.f4.fld.sta.txfifohe = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOHE"); + state->u.f4.fld.sta.rxfifohf = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOHF"); + state->u.f4.fld.sta.txfifof = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOF"); + state->u.f4.fld.sta.rxfifof = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOF"); + state->u.f4.fld.sta.txfifoe = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOE"); + state->u.f4.fld.sta.rxfifoe = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOE"); + state->u.f4.fld.sta.txdavl = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXDAVL"); + state->u.f4.fld.sta.rxdavl = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXDAVL"); + state->u.f4.fld.sta.sdioit = cm_object_get_child_by_name(state->u.f4.reg.sta, "SDIOIT"); + state->u.f4.fld.sta.ceataend = cm_object_get_child_by_name(state->u.f4.reg.sta, "CEATAEND"); + + // ICR bitfields. + state->u.f4.fld.icr.ccrcfailc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CCRCFAILC"); + state->u.f4.fld.icr.dcrcfailc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DCRCFAILC"); + state->u.f4.fld.icr.ctimeoutc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CTIMEOUTC"); + state->u.f4.fld.icr.dtimeoutc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DTIMEOUTC"); + state->u.f4.fld.icr.txunderrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "TXUNDERRC"); + state->u.f4.fld.icr.rxoverrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "RXOVERRC"); + state->u.f4.fld.icr.cmdrendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CMDRENDC"); + state->u.f4.fld.icr.cmdsentc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CMDSENTC"); + state->u.f4.fld.icr.dataendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DATAENDC"); + state->u.f4.fld.icr.stbiterrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "STBITERRC"); + state->u.f4.fld.icr.dbckendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DBCKENDC"); + state->u.f4.fld.icr.sdioitc = cm_object_get_child_by_name(state->u.f4.reg.icr, "SDIOITC"); + state->u.f4.fld.icr.ceataendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CEATAENDC"); + + // MASK bitfields. + state->u.f4.fld.mask.ccrcfailie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CCRCFAILIE"); + state->u.f4.fld.mask.dcrcfailie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DCRCFAILIE"); + state->u.f4.fld.mask.ctimeoutie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CTIMEOUTIE"); + state->u.f4.fld.mask.dtimeoutie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DTIMEOUTIE"); + state->u.f4.fld.mask.txunderrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXUNDERRIE"); + state->u.f4.fld.mask.rxoverrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXOVERRIE"); + state->u.f4.fld.mask.cmdrendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDRENDIE"); + state->u.f4.fld.mask.cmdsentie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDSENTIE"); + state->u.f4.fld.mask.dataendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DATAENDIE"); + state->u.f4.fld.mask.stbiterrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "STBITERRIE"); + state->u.f4.fld.mask.dbckendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DBCKENDIE"); + state->u.f4.fld.mask.cmdactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDACTIE"); + state->u.f4.fld.mask.txactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXACTIE"); + state->u.f4.fld.mask.rxactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXACTIE"); + state->u.f4.fld.mask.txfifoheie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOHEIE"); + state->u.f4.fld.mask.rxfifohfie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOHFIE"); + state->u.f4.fld.mask.txfifofie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOFIE"); + state->u.f4.fld.mask.rxfifofie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOFIE"); + state->u.f4.fld.mask.txfifoeie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOEIE"); + state->u.f4.fld.mask.rxfifoeie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOEIE"); + state->u.f4.fld.mask.txdavlie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXDAVLIE"); + state->u.f4.fld.mask.rxdavlie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXDAVLIE"); + state->u.f4.fld.mask.sdioitie = cm_object_get_child_by_name(state->u.f4.reg.mask, "SDIOITIE"); + state->u.f4.fld.mask.ceataendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CEATAENDIE"); + + // FIFOCNT bitfields. + state->u.f4.fld.fifocnt.fifocount = cm_object_get_child_by_name(state->u.f4.reg.fifocnt, "FIFOCOUNT"); + + // FIFO bitfields. + state->u.f4.fld.fifo.fifodata = cm_object_get_child_by_name(state->u.f4.reg.fifo, "FIFOData"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_sdio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_sdio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_sdio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_sdio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_sdio_is_enabled(Object *obj) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_sdio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_sdio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SDIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SDIOState *state = STM32_SDIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SDIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_sdio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sdio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_sdio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sdio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_sdio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SDIOEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_sdio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SDIO); +} + +static void stm32_sdio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_sdio_reset_callback; + dc->realize = stm32_sdio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_sdio_is_enabled; +} + +static const TypeInfo stm32_sdio_type_info = { + .name = TYPE_STM32_SDIO, + .parent = TYPE_STM32_SDIO_PARENT, + .instance_init = stm32_sdio_instance_init_callback, + .instance_size = sizeof(STM32SDIOState), + .class_init = stm32_sdio_class_init_callback, + .class_size = sizeof(STM32SDIOClass) }; + +static void stm32_sdio_register_types(void) +{ + type_register_static(&stm32_sdio_type_info); +} + +type_init(stm32_sdio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/sdio.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/sdio.h new file mode 100644 index 0000000000..63bda18fd4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/sdio.h @@ -0,0 +1,287 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SDIO_H_ +#define STM32_SDIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SDIO DEVICE_PATH_STM32 "SDIO" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SDIO TYPE_STM32_PREFIX "sdio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SDIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SDIOParentClass; +typedef PeripheralState STM32SDIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SDIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SDIOClass, (obj), TYPE_STM32_SDIO) +#define STM32_SDIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SDIOClass, (klass), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentClass parent_class; + // public: + + // None, so far. +} STM32SDIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SDIO_STATE(obj) \ + OBJECT_CHECK(STM32SDIOState, (obj), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SDIO (Secure digital input/output interface) registers. + struct { + Object *power; // 0x0 (Power control register) + Object *clkcr; // 0x4 (SDI clock control register) + Object *arg; // 0x8 (Argument register) + Object *cmd; // 0xC (Command register) + Object *respcmd; // 0x10 (Command response register) + Object *resp1; // 0x14 (Response 1..4 register) + Object *resp2; // 0x18 (Response 1..4 register) + Object *resp3; // 0x1C (Response 1..4 register) + Object *resp4; // 0x20 (Response 1..4 register) + Object *dtimer; // 0x24 (Data timer register) + Object *dlen; // 0x28 (Data length register) + Object *dctrl; // 0x2C (Data control register) + Object *dcount; // 0x30 (Data counter register) + Object *sta; // 0x34 (Status register) + Object *icr; // 0x38 (Interrupt clear register) + Object *mask; // 0x3C (Mask register) + Object *fifocnt; // 0x48 (FIFO counter register) + Object *fifo; // 0x80 (Data FIFO register) + } reg; + + struct { + + // POWER (Power control register) bitfields. + struct { + Object *pwrctrl; // [0:1] PWRCTRL + } power; + + // CLKCR (SDI clock control register) bitfields. + struct { + Object *clkdiv; // [0:7] Clock divide factor + Object *clken; // [8:8] Clock enable bit + Object *pwrsav; // [9:9] Power saving configuration bit + Object *bypass; // [10:10] Clock divider bypass enable bit + Object *widbus; // [11:12] Wide bus mode enable bit + Object *negedge; // [13:13] SDIO_CK dephasing selection bit + Object *hwfc_en; // [14:14] HW Flow Control enable + } clkcr; + + // ARG (Argument register) bitfields. + struct { + Object *cmdarg; // [0:31] Command argument + } arg; + + // CMD (Command register) bitfields. + struct { + Object *cmdindex; // [0:5] Command index + Object *waitresp; // [6:7] Wait for response bits + Object *waitint; // [8:8] CPSM waits for interrupt request + Object *waitpend; // [9:9] CPSM Waits for ends of data transfer (CmdPend internal signal). + Object *cpsmen; // [10:10] Command path state machine (CPSM) Enable bit + Object *sdiosuspend; // [11:11] SD I/O suspend command + Object *encmdcompl; // [12:12] Enable CMD completion + Object *nien; // [13:13] Not Interrupt Enable + Object *ce_atacmd; // [14:14] CE-ATA command + } cmd; + + // RESPCMD (Command response register) bitfields. + struct { + Object *respcmd; // [0:5] Response command index + } respcmd; + + // RESP1 (Response 1..4 register) bitfields. + struct { + Object *cardstatus1; // [0:31] Card Status + } resp1; + + // RESP2 (Response 1..4 register) bitfields. + struct { + Object *cardstatus2; // [0:31] Card Status + } resp2; + + // RESP3 (Response 1..4 register) bitfields. + struct { + Object *cardstatus3; // [0:31] Card Status + } resp3; + + // RESP4 (Response 1..4 register) bitfields. + struct { + Object *cardstatus4; // [0:31] Card Status + } resp4; + + // DTIMER (Data timer register) bitfields. + struct { + Object *datatime; // [0:31] Data timeout period + } dtimer; + + // DLEN (Data length register) bitfields. + struct { + Object *datalength; // [0:24] Data length value + } dlen; + + // DCTRL (Data control register) bitfields. + struct { + Object *dten; // [0:0] DTEN + Object *dtdir; // [1:1] Data transfer direction selection + Object *dtmode; // [2:2] Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + Object *dmaen; // [3:3] DMA enable bit + Object *dblocksize; // [4:7] Data block size + Object *rwstart; // [8:8] Read wait start + Object *rwstop; // [9:9] Read wait stop + Object *rwmod; // [10:10] Read wait mode + Object *sdioen; // [11:11] SD I/O enable functions + } dctrl; + + // DCOUNT (Data counter register) bitfields. + struct { + Object *datacount; // [0:24] Data count value + } dcount; + + // STA (Status register) bitfields. + struct { + Object *ccrcfail; // [0:0] Command response received (CRC check failed) + Object *dcrcfail; // [1:1] Data block sent/received (CRC check failed) + Object *ctimeout; // [2:2] Command response timeout + Object *dtimeout; // [3:3] Data timeout + Object *txunderr; // [4:4] Transmit FIFO underrun error + Object *rxoverr; // [5:5] Received FIFO overrun error + Object *cmdrend; // [6:6] Command response received (CRC check passed) + Object *cmdsent; // [7:7] Command sent (no response required) + Object *dataend; // [8:8] Data end (data counter, SDIDCOUNT, is zero) + Object *stbiterr; // [9:9] Start bit not detected on all data signals in wide bus mode + Object *dbckend; // [10:10] Data block sent/received (CRC check passed) + Object *cmdact; // [11:11] Command transfer in progress + Object *txact; // [12:12] Data transmit in progress + Object *rxact; // [13:13] Data receive in progress + Object *txfifohe; // [14:14] Transmit FIFO half empty: at least 8 words can be written into the FIFO + Object *rxfifohf; // [15:15] Receive FIFO half full: there are at least 8 words in the FIFO + Object *txfifof; // [16:16] Transmit FIFO full + Object *rxfifof; // [17:17] Receive FIFO full + Object *txfifoe; // [18:18] Transmit FIFO empty + Object *rxfifoe; // [19:19] Receive FIFO empty + Object *txdavl; // [20:20] Data available in transmit FIFO + Object *rxdavl; // [21:21] Data available in receive FIFO + Object *sdioit; // [22:22] SDIO interrupt received + Object *ceataend; // [23:23] CE-ATA command completion signal received for CMD61 + } sta; + + // ICR (Interrupt clear register) bitfields. + struct { + Object *ccrcfailc; // [0:0] CCRCFAIL flag clear bit + Object *dcrcfailc; // [1:1] DCRCFAIL flag clear bit + Object *ctimeoutc; // [2:2] CTIMEOUT flag clear bit + Object *dtimeoutc; // [3:3] DTIMEOUT flag clear bit + Object *txunderrc; // [4:4] TXUNDERR flag clear bit + Object *rxoverrc; // [5:5] RXOVERR flag clear bit + Object *cmdrendc; // [6:6] CMDREND flag clear bit + Object *cmdsentc; // [7:7] CMDSENT flag clear bit + Object *dataendc; // [8:8] DATAEND flag clear bit + Object *stbiterrc; // [9:9] STBITERR flag clear bit + Object *dbckendc; // [10:10] DBCKEND flag clear bit + Object *sdioitc; // [22:22] SDIOIT flag clear bit + Object *ceataendc; // [23:23] CEATAEND flag clear bit + } icr; + + // MASK (Mask register) bitfields. + struct { + Object *ccrcfailie; // [0:0] Command CRC fail interrupt enable + Object *dcrcfailie; // [1:1] Data CRC fail interrupt enable + Object *ctimeoutie; // [2:2] Command timeout interrupt enable + Object *dtimeoutie; // [3:3] Data timeout interrupt enable + Object *txunderrie; // [4:4] Tx FIFO underrun error interrupt enable + Object *rxoverrie; // [5:5] Rx FIFO overrun error interrupt enable + Object *cmdrendie; // [6:6] Command response received interrupt enable + Object *cmdsentie; // [7:7] Command sent interrupt enable + Object *dataendie; // [8:8] Data end interrupt enable + Object *stbiterrie; // [9:9] Start bit error interrupt enable + Object *dbckendie; // [10:10] Data block end interrupt enable + Object *cmdactie; // [11:11] Command acting interrupt enable + Object *txactie; // [12:12] Data transmit acting interrupt enable + Object *rxactie; // [13:13] Data receive acting interrupt enable + Object *txfifoheie; // [14:14] Tx FIFO half empty interrupt enable + Object *rxfifohfie; // [15:15] Rx FIFO half full interrupt enable + Object *txfifofie; // [16:16] Tx FIFO full interrupt enable + Object *rxfifofie; // [17:17] Rx FIFO full interrupt enable + Object *txfifoeie; // [18:18] Tx FIFO empty interrupt enable + Object *rxfifoeie; // [19:19] Rx FIFO empty interrupt enable + Object *txdavlie; // [20:20] Data available in Tx FIFO interrupt enable + Object *rxdavlie; // [21:21] Data available in Rx FIFO interrupt enable + Object *sdioitie; // [22:22] SDIO mode interrupt received interrupt enable + Object *ceataendie; // [23:23] CE-ATA command completion signal received interrupt enable + } mask; + + // FIFOCNT (FIFO counter register) bitfields. + struct { + Object *fifocount; // [0:23] Remaining number of words to be written to or read from the FIFO. + } fifocnt; + + // FIFO (Data FIFO register) bitfields. + struct { + Object *fifodata; // [0:31] Receive and transmit FIFO data + } fifo; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SDIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SDIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/syscfg.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/syscfg.c new file mode 100644 index 0000000000..d430a6bc80 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/syscfg.c @@ -0,0 +1,275 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_syscfg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.memrm = cm_object_get_child_by_name(obj, "MEMRM"); + state->u.f4.reg.pmc = cm_object_get_child_by_name(obj, "PMC"); + state->u.f4.reg.exticr1 = cm_object_get_child_by_name(obj, "EXTICR1"); + state->u.f4.reg.exticr2 = cm_object_get_child_by_name(obj, "EXTICR2"); + state->u.f4.reg.exticr3 = cm_object_get_child_by_name(obj, "EXTICR3"); + state->u.f4.reg.exticr4 = cm_object_get_child_by_name(obj, "EXTICR4"); + state->u.f4.reg.cmpcr = cm_object_get_child_by_name(obj, "CMPCR"); + + + // MEMRM bitfields. + state->u.f4.fld.memrm.mem_mode = cm_object_get_child_by_name(state->u.f4.reg.memrm, "MEM_MODE"); + + // PMC bitfields. + state->u.f4.fld.pmc.adc1dc2 = cm_object_get_child_by_name(state->u.f4.reg.pmc, "ADC1DC2"); + + // EXTICR1 bitfields. + state->u.f4.fld.exticr1.exti0 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI0"); + state->u.f4.fld.exticr1.exti1 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI1"); + state->u.f4.fld.exticr1.exti2 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI2"); + state->u.f4.fld.exticr1.exti3 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI3"); + + // EXTICR2 bitfields. + state->u.f4.fld.exticr2.exti4 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI4"); + state->u.f4.fld.exticr2.exti5 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI5"); + state->u.f4.fld.exticr2.exti6 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI6"); + state->u.f4.fld.exticr2.exti7 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI7"); + + // EXTICR3 bitfields. + state->u.f4.fld.exticr3.exti8 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI8"); + state->u.f4.fld.exticr3.exti9 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI9"); + state->u.f4.fld.exticr3.exti10 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI10"); + state->u.f4.fld.exticr3.exti11 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI11"); + + // EXTICR4 bitfields. + state->u.f4.fld.exticr4.exti12 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI12"); + state->u.f4.fld.exticr4.exti13 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI13"); + state->u.f4.fld.exticr4.exti14 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI14"); + state->u.f4.fld.exticr4.exti15 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI15"); + + // CMPCR bitfields. + state->u.f4.fld.cmpcr.cmp_pd = cm_object_get_child_by_name(state->u.f4.reg.cmpcr, "CMP_PD"); + state->u.f4.fld.cmpcr.ready = cm_object_get_child_by_name(state->u.f4.reg.cmpcr, "READY"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_syscfg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_syscfg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_syscfg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_syscfg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_syscfg_is_enabled(Object *obj) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_syscfg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_syscfg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SYSCFG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SYSCFG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_syscfg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_syscfg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_syscfg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_syscfg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_syscfg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SYSCFGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_syscfg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SYSCFG); +} + +static void stm32_syscfg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_syscfg_reset_callback; + dc->realize = stm32_syscfg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_syscfg_is_enabled; +} + +static const TypeInfo stm32_syscfg_type_info = { + .name = TYPE_STM32_SYSCFG, + .parent = TYPE_STM32_SYSCFG_PARENT, + .instance_init = stm32_syscfg_instance_init_callback, + .instance_size = sizeof(STM32SYSCFGState), + .class_init = stm32_syscfg_class_init_callback, + .class_size = sizeof(STM32SYSCFGClass) }; + +static void stm32_syscfg_register_types(void) +{ + type_register_static(&stm32_syscfg_type_info); +} + +type_init(stm32_syscfg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/syscfg.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/syscfg.h new file mode 100644 index 0000000000..6b4c0ec9c5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/syscfg.h @@ -0,0 +1,154 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SYSCFG_H_ +#define STM32_SYSCFG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SYSCFG DEVICE_PATH_STM32 "SYSCFG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SYSCFG TYPE_STM32_PREFIX "syscfg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SYSCFG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SYSCFGParentClass; +typedef PeripheralState STM32SYSCFGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SYSCFG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SYSCFGClass, (obj), TYPE_STM32_SYSCFG) +#define STM32_SYSCFG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SYSCFGClass, (klass), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentClass parent_class; + // public: + + // None, so far. +} STM32SYSCFGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SYSCFG_STATE(obj) \ + OBJECT_CHECK(STM32SYSCFGState, (obj), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SYSCFG (System configuration controller) registers. + struct { + Object *memrm; // 0x0 (Memory remap register) + Object *pmc; // 0x4 (Peripheral mode configuration register) + Object *exticr1; // 0x8 (External interrupt configuration register 1) + Object *exticr2; // 0xC (External interrupt configuration register 2) + Object *exticr3; // 0x10 (External interrupt configuration register 3) + Object *exticr4; // 0x14 (External interrupt configuration register 4) + Object *cmpcr; // 0x20 (Compensation cell control register) + } reg; + + struct { + + // MEMRM (Memory remap register) bitfields. + struct { + Object *mem_mode; // [0:1] MEM_MODE + } memrm; + + // PMC (Peripheral mode configuration register) bitfields. + struct { + Object *adc1dc2; // [16:16] ADC1DC2 + } pmc; + + // EXTICR1 (External interrupt configuration register 1) bitfields. + struct { + Object *exti0; // [0:3] EXTI x configuration (x = 0 to 3) + Object *exti1; // [4:7] EXTI x configuration (x = 0 to 3) + Object *exti2; // [8:11] EXTI x configuration (x = 0 to 3) + Object *exti3; // [12:15] EXTI x configuration (x = 0 to 3) + } exticr1; + + // EXTICR2 (External interrupt configuration register 2) bitfields. + struct { + Object *exti4; // [0:3] EXTI x configuration (x = 4 to 7) + Object *exti5; // [4:7] EXTI x configuration (x = 4 to 7) + Object *exti6; // [8:11] EXTI x configuration (x = 4 to 7) + Object *exti7; // [12:15] EXTI x configuration (x = 4 to 7) + } exticr2; + + // EXTICR3 (External interrupt configuration register 3) bitfields. + struct { + Object *exti8; // [0:3] EXTI x configuration (x = 8 to 11) + Object *exti9; // [4:7] EXTI x configuration (x = 8 to 11) + Object *exti10; // [8:11] EXTI10 + Object *exti11; // [12:15] EXTI x configuration (x = 8 to 11) + } exticr3; + + // EXTICR4 (External interrupt configuration register 4) bitfields. + struct { + Object *exti12; // [0:3] EXTI x configuration (x = 12 to 15) + Object *exti13; // [4:7] EXTI x configuration (x = 12 to 15) + Object *exti14; // [8:11] EXTI x configuration (x = 12 to 15) + Object *exti15; // [12:15] EXTI x configuration (x = 12 to 15) + } exticr4; + + // CMPCR (Compensation cell control register) bitfields. + struct { + Object *cmp_pd; // [0:0] Compensation cell power-down + Object *ready; // [8:8] READY + } cmpcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SYSCFGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SYSCFG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim1.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim1.c new file mode 100644 index 0000000000..af80ea1923 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim1.c @@ -0,0 +1,427 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_tim1_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f4.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCPC"); + state->u.f4.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCUS"); + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + state->u.f4.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS1"); + state->u.f4.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS1N"); + state->u.f4.fld.cr2.ois2 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS2"); + state->u.f4.fld.cr2.ois2n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS2N"); + state->u.f4.fld.cr2.ois3 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS3"); + state->u.f4.fld.cr2.ois3n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS3N"); + state->u.f4.fld.cr2.ois4 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS4"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.comie = cm_object_get_child_by_name(state->u.f4.reg.dier, "COMIE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.bie = cm_object_get_child_by_name(state->u.f4.reg.dier, "BIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.comde = cm_object_get_child_by_name(state->u.f4.reg.dier, "COMDE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.comif = cm_object_get_child_by_name(state->u.f4.reg.sr, "COMIF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.bif = cm_object_get_child_by_name(state->u.f4.reg.sr, "BIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.comg = cm_object_get_child_by_name(state->u.f4.reg.egr, "COMG"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + state->u.f4.fld.egr.bg = cm_object_get_child_by_name(state->u.f4.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NE"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NE"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NE"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // RCR bitfields. + state->u.f4.fld.rcr.rep = cm_object_get_child_by_name(state->u.f4.reg.rcr, "REP"); + + // BDTR bitfields. + state->u.f4.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "DTG"); + state->u.f4.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "LOCK"); + state->u.f4.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "OSSI"); + state->u.f4.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "OSSR"); + state->u.f4.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "BKE"); + state->u.f4.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "BKP"); + state->u.f4.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "AOE"); + state->u.f4.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "MOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim1_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim1_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim1_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim1_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim1_is_enabled(Object *obj) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim1_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim1_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM1)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM1State *state = STM32_TIM1_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM1"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_tim1_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim1_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim1_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim1_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim1_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM1EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim1_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM1); +} + +static void stm32_tim1_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim1_reset_callback; + dc->realize = stm32_tim1_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim1_is_enabled; +} + +static const TypeInfo stm32_tim1_type_info = { + .name = TYPE_STM32_TIM1, + .parent = TYPE_STM32_TIM1_PARENT, + .instance_init = stm32_tim1_instance_init_callback, + .instance_size = sizeof(STM32TIM1State), + .class_init = stm32_tim1_class_init_callback, + .class_size = sizeof(STM32TIM1Class) }; + +static void stm32_tim1_register_types(void) +{ + type_register_static(&stm32_tim1_type_info); +} + +type_init(stm32_tim1_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim1.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim1.h new file mode 100644 index 0000000000..de5c1bbab8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim1.h @@ -0,0 +1,336 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM1_H_ +#define STM32_TIM1_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM1 DEVICE_PATH_STM32 "TIM1" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM1 TYPE_STM32_PREFIX "tim1" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM1_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM1ParentClass; +typedef PeripheralState STM32TIM1ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM1_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM1Class, (obj), TYPE_STM32_TIM1) +#define STM32_TIM1_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM1Class, (klass), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM1Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM1_STATE(obj) \ + OBJECT_CHECK(STM32TIM1State, (obj), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM1 (Advanced-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *rcr; // 0x30 (Repetition counter register) + Object *bdtr; // 0x44 (Break and dead-time register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + Object *ois2; // [10:10] Output Idle state 2 + Object *ois2n; // [11:11] Output Idle state 2 + Object *ois3; // [12:12] Output Idle state 3 + Object *ois3n; // [13:13] Output Idle state 3 + Object *ois4; // [14:14] Output Idle state 4 + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *comde; // [13:13] COM DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *oc1ce; // [7:7] Output Compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + Object *oc2ce; // [15:15] Output Compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2ne; // [6:6] Capture/Compare 2 complementary output enable + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3ne; // [10:10] Capture/Compare 3 complementary output enable + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM1State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM1_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim10.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim10.c new file mode 100644 index 0000000000..89e280b1ef --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim10.c @@ -0,0 +1,293 @@ +/* + * STM32 - TIM10 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_tim10_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim10_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim10_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim10_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim10_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim10_is_enabled(Object *obj) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim10_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim10_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM10)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM10State *state = STM32_TIM10_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM10"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_tim10_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim10_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim10_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim10_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim10_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM10EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim10_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM10); +} + +static void stm32_tim10_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim10_reset_callback; + dc->realize = stm32_tim10_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim10_is_enabled; +} + +static const TypeInfo stm32_tim10_type_info = { + .name = TYPE_STM32_TIM10, + .parent = TYPE_STM32_TIM10_PARENT, + .instance_init = stm32_tim10_instance_init_callback, + .instance_size = sizeof(STM32TIM10State), + .class_init = stm32_tim10_class_init_callback, + .class_size = sizeof(STM32TIM10Class) }; + +static void stm32_tim10_register_types(void) +{ + type_register_static(&stm32_tim10_type_info); +} + +type_init(stm32_tim10_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim10.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim10.h new file mode 100644 index 0000000000..db54c1c071 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim10.h @@ -0,0 +1,180 @@ +/* + * STM32 - TIM10 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM10_H_ +#define STM32_TIM10_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM10 DEVICE_PATH_STM32 "TIM10" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM10 TYPE_STM32_PREFIX "tim10" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM10_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM10ParentClass; +typedef PeripheralState STM32TIM10ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM10_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM10Class, (obj), TYPE_STM32_TIM10) +#define STM32_TIM10_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM10Class, (klass), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM10Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM10_STATE(obj) \ + OBJECT_CHECK(STM32TIM10State, (obj), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM10 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM10State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM10_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim11.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim11.c new file mode 100644 index 0000000000..df292fd5bd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim11.c @@ -0,0 +1,297 @@ +/* + * STM32 - TIM11 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_tim11_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // OR bitfields. + state->u.f4.fld.or_.rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim11_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim11_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim11_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim11_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim11_is_enabled(Object *obj) +{ + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim11_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim11_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM11)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM11State *state = STM32_TIM11_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM11"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_tim11_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim11_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim11_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim11_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim11_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM11EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim11_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM11); +} + +static void stm32_tim11_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim11_reset_callback; + dc->realize = stm32_tim11_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim11_is_enabled; +} + +static const TypeInfo stm32_tim11_type_info = { + .name = TYPE_STM32_TIM11, + .parent = TYPE_STM32_TIM11_PARENT, + .instance_init = stm32_tim11_instance_init_callback, + .instance_size = sizeof(STM32TIM11State), + .class_init = stm32_tim11_class_init_callback, + .class_size = sizeof(STM32TIM11Class) }; + +static void stm32_tim11_register_types(void) +{ + type_register_static(&stm32_tim11_type_info); +} + +type_init(stm32_tim11_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim11.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim11.h new file mode 100644 index 0000000000..22f02a5127 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim11.h @@ -0,0 +1,186 @@ +/* + * STM32 - TIM11 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM11_H_ +#define STM32_TIM11_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM11 DEVICE_PATH_STM32 "TIM11" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM11 TYPE_STM32_PREFIX "tim11" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM11_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM11ParentClass; +typedef PeripheralState STM32TIM11ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM11_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM11Class, (obj), TYPE_STM32_TIM11) +#define STM32_TIM11_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM11Class, (klass), TYPE_STM32_TIM11) + +typedef struct { + // private: + STM32TIM11ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM11Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM11_STATE(obj) \ + OBJECT_CHECK(STM32TIM11State, (obj), TYPE_STM32_TIM11) + +typedef struct { + // private: + STM32TIM11ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM11 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *or_; // 0x50 (Option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // OR (Option register) bitfields. + struct { + Object *rmp; // [0:1] Input 1 remapping capability + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM11State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM11_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim2.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim2.c new file mode 100644 index 0000000000..ab6d3e1a26 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim2.c @@ -0,0 +1,404 @@ +/* + * STM32 - TIM2 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_tim2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // OR bitfields. + state->u.f4.fld.or_.itr1_rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "ITR1_RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim2_is_enabled(Object *obj) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM2State *state = STM32_TIM2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_tim2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim2_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM2EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM2); +} + +static void stm32_tim2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim2_reset_callback; + dc->realize = stm32_tim2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim2_is_enabled; +} + +static const TypeInfo stm32_tim2_type_info = { + .name = TYPE_STM32_TIM2, + .parent = TYPE_STM32_TIM2_PARENT, + .instance_init = stm32_tim2_instance_init_callback, + .instance_size = sizeof(STM32TIM2State), + .class_init = stm32_tim2_class_init_callback, + .class_size = sizeof(STM32TIM2Class) }; + +static void stm32_tim2_register_types(void) +{ + type_register_static(&stm32_tim2_type_info); +} + +type_init(stm32_tim2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim2.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim2.h new file mode 100644 index 0000000000..142585db3d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim2.h @@ -0,0 +1,311 @@ +/* + * STM32 - TIM2 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM2_H_ +#define STM32_TIM2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM2 DEVICE_PATH_STM32 "TIM2" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM2 TYPE_STM32_PREFIX "tim2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM2ParentClass; +typedef PeripheralState STM32TIM2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM2Class, (obj), TYPE_STM32_TIM2) +#define STM32_TIM2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM2Class, (klass), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM2_STATE(obj) \ + OBJECT_CHECK(STM32TIM2State, (obj), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM2 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *or_; // 0x50 (TIM5 option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // OR (TIM5 option register) bitfields. + struct { + Object *itr1_rmp; // [10:11] Timer Input 4 remap + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim3.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim3.c new file mode 100644 index 0000000000..6ca65b50ce --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim3.c @@ -0,0 +1,400 @@ +/* + * STM32 - TIM3 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_tim3_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim3_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim3_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim3_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim3_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim3_is_enabled(Object *obj) +{ + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim3_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim3_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM3)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM3State *state = STM32_TIM3_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM3"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_tim3_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim3_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim3_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim3_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim3_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM3EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim3_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM3); +} + +static void stm32_tim3_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim3_reset_callback; + dc->realize = stm32_tim3_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim3_is_enabled; +} + +static const TypeInfo stm32_tim3_type_info = { + .name = TYPE_STM32_TIM3, + .parent = TYPE_STM32_TIM3_PARENT, + .instance_init = stm32_tim3_instance_init_callback, + .instance_size = sizeof(STM32TIM3State), + .class_init = stm32_tim3_class_init_callback, + .class_size = sizeof(STM32TIM3Class) }; + +static void stm32_tim3_register_types(void) +{ + type_register_static(&stm32_tim3_type_info); +} + +type_init(stm32_tim3_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim3.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim3.h new file mode 100644 index 0000000000..7f70acd7eb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim3.h @@ -0,0 +1,305 @@ +/* + * STM32 - TIM3 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM3_H_ +#define STM32_TIM3_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM3 DEVICE_PATH_STM32 "TIM3" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM3 TYPE_STM32_PREFIX "tim3" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM3_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM3ParentClass; +typedef PeripheralState STM32TIM3ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM3_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM3Class, (obj), TYPE_STM32_TIM3) +#define STM32_TIM3_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM3Class, (klass), TYPE_STM32_TIM3) + +typedef struct { + // private: + STM32TIM3ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM3Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM3_STATE(obj) \ + OBJECT_CHECK(STM32TIM3State, (obj), TYPE_STM32_TIM3) + +typedef struct { + // private: + STM32TIM3ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM3 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM3State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM3_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim5.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim5.c new file mode 100644 index 0000000000..6843f1604d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim5.c @@ -0,0 +1,404 @@ +/* + * STM32 - TIM5 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_tim5_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // OR bitfields. + state->u.f4.fld.or_.it4_rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "IT4_RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim5_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim5_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim5_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim5_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim5_is_enabled(Object *obj) +{ + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim5_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim5_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM5)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM5State *state = STM32_TIM5_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM5"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_tim5_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim5_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim5_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim5_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim5_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM5EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim5_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM5); +} + +static void stm32_tim5_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim5_reset_callback; + dc->realize = stm32_tim5_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim5_is_enabled; +} + +static const TypeInfo stm32_tim5_type_info = { + .name = TYPE_STM32_TIM5, + .parent = TYPE_STM32_TIM5_PARENT, + .instance_init = stm32_tim5_instance_init_callback, + .instance_size = sizeof(STM32TIM5State), + .class_init = stm32_tim5_class_init_callback, + .class_size = sizeof(STM32TIM5Class) }; + +static void stm32_tim5_register_types(void) +{ + type_register_static(&stm32_tim5_type_info); +} + +type_init(stm32_tim5_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim5.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim5.h new file mode 100644 index 0000000000..41d6bcf531 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim5.h @@ -0,0 +1,311 @@ +/* + * STM32 - TIM5 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM5_H_ +#define STM32_TIM5_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM5 DEVICE_PATH_STM32 "TIM5" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM5 TYPE_STM32_PREFIX "tim5" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM5_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM5ParentClass; +typedef PeripheralState STM32TIM5ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM5_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM5Class, (obj), TYPE_STM32_TIM5) +#define STM32_TIM5_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM5Class, (klass), TYPE_STM32_TIM5) + +typedef struct { + // private: + STM32TIM5ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM5Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM5_STATE(obj) \ + OBJECT_CHECK(STM32TIM5State, (obj), TYPE_STM32_TIM5) + +typedef struct { + // private: + STM32TIM5ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM5 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *or_; // 0x50 (TIM5 option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // OR (TIM5 option register) bitfields. + struct { + Object *it4_rmp; // [6:7] Timer Input 4 remap + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM5State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM5_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim9.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim9.c new file mode 100644 index 0000000000..9e1742a84a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim9.c @@ -0,0 +1,325 @@ +/* + * STM32 - TIM9 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_tim9_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim9_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim9_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim9_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim9_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim9_is_enabled(Object *obj) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim9_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim9_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM9)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM9State *state = STM32_TIM9_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM9"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_tim9_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim9_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim9_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim9_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim9_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM9EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim9_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM9); +} + +static void stm32_tim9_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim9_reset_callback; + dc->realize = stm32_tim9_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim9_is_enabled; +} + +static const TypeInfo stm32_tim9_type_info = { + .name = TYPE_STM32_TIM9, + .parent = TYPE_STM32_TIM9_PARENT, + .instance_init = stm32_tim9_instance_init_callback, + .instance_size = sizeof(STM32TIM9State), + .class_init = stm32_tim9_class_init_callback, + .class_size = sizeof(STM32TIM9Class) }; + +static void stm32_tim9_register_types(void) +{ + type_register_static(&stm32_tim9_type_info); +} + +type_init(stm32_tim9_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/tim9.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim9.h new file mode 100644 index 0000000000..c05086f65e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/tim9.h @@ -0,0 +1,218 @@ +/* + * STM32 - TIM9 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM9_H_ +#define STM32_TIM9_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM9 DEVICE_PATH_STM32 "TIM9" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM9 TYPE_STM32_PREFIX "tim9" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM9_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM9ParentClass; +typedef PeripheralState STM32TIM9ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM9_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM9Class, (obj), TYPE_STM32_TIM9) +#define STM32_TIM9_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM9Class, (klass), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM9Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM9_STATE(obj) \ + OBJECT_CHECK(STM32TIM9State, (obj), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM9 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:6] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:14] Input capture 2 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM9State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM9_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/usart1.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/usart1.c new file mode 100644 index 0000000000..2c159aa693 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/usart1.c @@ -0,0 +1,311 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_usart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + state->u.f4.reg.gtpr = cm_object_get_child_by_name(obj, "GTPR"); + + + // SR bitfields. + state->u.f4.fld.sr.pe = cm_object_get_child_by_name(state->u.f4.reg.sr, "PE"); + state->u.f4.fld.sr.fe = cm_object_get_child_by_name(state->u.f4.reg.sr, "FE"); + state->u.f4.fld.sr.nf = cm_object_get_child_by_name(state->u.f4.reg.sr, "NF"); + state->u.f4.fld.sr.ore = cm_object_get_child_by_name(state->u.f4.reg.sr, "ORE"); + state->u.f4.fld.sr.idle = cm_object_get_child_by_name(state->u.f4.reg.sr, "IDLE"); + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.tc = cm_object_get_child_by_name(state->u.f4.reg.sr, "TC"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.lbd = cm_object_get_child_by_name(state->u.f4.reg.sr, "LBD"); + state->u.f4.fld.sr.cts = cm_object_get_child_by_name(state->u.f4.reg.sr, "CTS"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // BRR bitfields. + state->u.f4.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Fraction"); + state->u.f4.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f4.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SBK"); + state->u.f4.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RWU"); + state->u.f4.fld.cr1.re = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RE"); + state->u.f4.fld.cr1.te = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TE"); + state->u.f4.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "IDLEIE"); + state->u.f4.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXNEIE"); + state->u.f4.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TCIE"); + state->u.f4.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TXEIE"); + state->u.f4.fld.cr1.peie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEIE"); + state->u.f4.fld.cr1.ps = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PS"); + state->u.f4.fld.cr1.pce = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PCE"); + state->u.f4.fld.cr1.wake = cm_object_get_child_by_name(state->u.f4.reg.cr1, "WAKE"); + state->u.f4.fld.cr1.m = cm_object_get_child_by_name(state->u.f4.reg.cr1, "M"); + state->u.f4.fld.cr1.ue = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UE"); + state->u.f4.fld.cr1.over8 = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVER8"); + + // CR2 bitfields. + state->u.f4.fld.cr2.add = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADD"); + state->u.f4.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDL"); + state->u.f4.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDIE"); + state->u.f4.fld.cr2.lbcl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBCL"); + state->u.f4.fld.cr2.cpha = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CPHA"); + state->u.f4.fld.cr2.cpol = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CPOL"); + state->u.f4.fld.cr2.clken = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CLKEN"); + state->u.f4.fld.cr2.stop = cm_object_get_child_by_name(state->u.f4.reg.cr2, "STOP"); + state->u.f4.fld.cr2.linen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f4.fld.cr3.eie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "EIE"); + state->u.f4.fld.cr3.iren = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IREN"); + state->u.f4.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IRLP"); + state->u.f4.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f4.reg.cr3, "HDSEL"); + state->u.f4.fld.cr3.nack = cm_object_get_child_by_name(state->u.f4.reg.cr3, "NACK"); + state->u.f4.fld.cr3.scen = cm_object_get_child_by_name(state->u.f4.reg.cr3, "SCEN"); + state->u.f4.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAR"); + state->u.f4.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAT"); + state->u.f4.fld.cr3.rtse = cm_object_get_child_by_name(state->u.f4.reg.cr3, "RTSE"); + state->u.f4.fld.cr3.ctse = cm_object_get_child_by_name(state->u.f4.reg.cr3, "CTSE"); + state->u.f4.fld.cr3.ctsie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "CTSIE"); + state->u.f4.fld.cr3.onebit = cm_object_get_child_by_name(state->u.f4.reg.cr3, "ONEBIT"); + + // GTPR bitfields. + state->u.f4.fld.gtpr.psc = cm_object_get_child_by_name(state->u.f4.reg.gtpr, "PSC"); + state->u.f4.fld.gtpr.gt = cm_object_get_child_by_name(state->u.f4.reg.gtpr, "GT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usart_is_enabled(Object *obj) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USARTState *state = STM32_USART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_USART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USARTState *state = STM32_USART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_usart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_usart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_usart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_usart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_usart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USART%dEN", + 1 + state->port_index - STM32_PORT_USART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USART); +} + +static void stm32_usart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usart_reset_callback; + dc->realize = stm32_usart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usart_is_enabled; +} + +static const TypeInfo stm32_usart_type_info = { + .name = TYPE_STM32_USART, + .parent = TYPE_STM32_USART_PARENT, + .instance_init = stm32_usart_instance_init_callback, + .instance_size = sizeof(STM32USARTState), + .class_init = stm32_usart_class_init_callback, + .class_size = sizeof(STM32USARTClass) }; + +static void stm32_usart_register_types(void) +{ + type_register_static(&stm32_usart_type_info); +} + +type_init(stm32_usart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/usart1.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/usart1.h new file mode 100644 index 0000000000..e2cc860caa --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/usart1.h @@ -0,0 +1,197 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USART_H_ +#define STM32_USART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USART DEVICE_PATH_STM32 "USART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_USART1, + STM32_PORT_USART2, + STM32_PORT_USART6, + STM32_PORT_USART_UNDEFINED = 0xFF, +} stm32_usart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USART TYPE_STM32_PREFIX "usart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USARTParentClass; +typedef PeripheralState STM32USARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USARTClass, (obj), TYPE_STM32_USART) +#define STM32_USART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USARTClass, (klass), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentClass parent_class; + // public: + + // None, so far. +} STM32USARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USART_STATE(obj) \ + OBJECT_CHECK(STM32USARTState, (obj), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_usart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 USART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *dr; // 0x4 (Data register) + Object *brr; // 0x8 (Baud rate register) + Object *cr1; // 0xC (Control register 1) + Object *cr2; // 0x10 (Control register 2) + Object *cr3; // 0x14 (Control register 3) + Object *gtpr; // 0x18 (Guard time and prescaler register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *nf; // [2:2] Noise detected flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + Object *cts; // [9:9] CTS flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:8] Data value + } dr; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // CR1 (Control register 1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + Object *over8; // [15:15] Oversampling mode + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *lbcl; // [8:8] Last bit clock pulse + Object *cpha; // [9:9] Clock phase + Object *cpol; // [10:10] Clock polarity + Object *clken; // [11:11] Clock enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *nack; // [4:4] Smartcard NACK enable + Object *scen; // [5:5] Smartcard mode enable + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *rtse; // [8:8] RTS enable + Object *ctse; // [9:9] CTS enable + Object *ctsie; // [10:10] CTS interrupt enable + Object *onebit; // [11:11] One sample bit method enable + } cr3; + + // GTPR (Guard time and prescaler register) bitfields. + struct { + Object *psc; // [0:7] Prescaler value + Object *gt; // [8:15] Guard time value + } gtpr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/wwdg.c b/gnu-mcu-eclipse/devices/support/STM32F411xx/wwdg.c new file mode 100644 index 0000000000..a67d5b412e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/wwdg.c @@ -0,0 +1,250 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f411xx_wwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.cfr = cm_object_get_child_by_name(obj, "CFR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f4.fld.cr.t = cm_object_get_child_by_name(state->u.f4.reg.cr, "T"); + state->u.f4.fld.cr.wdga = cm_object_get_child_by_name(state->u.f4.reg.cr, "WDGA"); + + // CFR bitfields. + state->u.f4.fld.cfr.w = cm_object_get_child_by_name(state->u.f4.reg.cfr, "W"); + state->u.f4.fld.cfr.wdgtb0 = cm_object_get_child_by_name(state->u.f4.reg.cfr, "WDGTB0"); + state->u.f4.fld.cfr.wdgtb1 = cm_object_get_child_by_name(state->u.f4.reg.cfr, "WDGTB1"); + state->u.f4.fld.cfr.ewi = cm_object_get_child_by_name(state->u.f4.reg.cfr, "EWI"); + + // SR bitfields. + state->u.f4.fld.sr.ewif = cm_object_get_child_by_name(state->u.f4.reg.sr, "EWIF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_wwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_wwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_wwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_wwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_wwdg_is_enabled(Object *obj) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_wwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_wwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_WWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32WWDGState *state = STM32_WWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "WWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_411xx ) { + + stm32f411xx_wwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_wwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_wwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_wwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_wwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/WWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_wwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_WWDG); +} + +static void stm32_wwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_wwdg_reset_callback; + dc->realize = stm32_wwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_wwdg_is_enabled; +} + +static const TypeInfo stm32_wwdg_type_info = { + .name = TYPE_STM32_WWDG, + .parent = TYPE_STM32_WWDG_PARENT, + .instance_init = stm32_wwdg_instance_init_callback, + .instance_size = sizeof(STM32WWDGState), + .class_init = stm32_wwdg_class_init_callback, + .class_size = sizeof(STM32WWDGClass) }; + +static void stm32_wwdg_register_types(void) +{ + type_register_static(&stm32_wwdg_type_info); +} + +type_init(stm32_wwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F411xx/wwdg.h b/gnu-mcu-eclipse/devices/support/STM32F411xx/wwdg.h new file mode 100644 index 0000000000..9e32867abb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F411xx/wwdg.h @@ -0,0 +1,121 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_WWDG_H_ +#define STM32_WWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_WWDG DEVICE_PATH_STM32 "WWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_WWDG TYPE_STM32_PREFIX "wwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_WWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32WWDGParentClass; +typedef PeripheralState STM32WWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_WWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32WWDGClass, (obj), TYPE_STM32_WWDG) +#define STM32_WWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32WWDGClass, (klass), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentClass parent_class; + // public: + + // None, so far. +} STM32WWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_WWDG_STATE(obj) \ + OBJECT_CHECK(STM32WWDGState, (obj), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 WWDG (Window watchdog) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *cfr; // 0x4 (Configuration register) + Object *sr; // 0x8 (Status register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *t; // [0:6] 7-bit counter (MSB to LSB) + Object *wdga; // [7:7] Activation bit + } cr; + + // CFR (Configuration register) bitfields. + struct { + Object *w; // [0:6] 7-bit window value + Object *wdgtb0; // [7:7] Timer base + Object *wdgtb1; // [8:8] Timer base + Object *ewi; // [9:9] Early wakeup interrupt + } cfr; + + // SR (Status register) bitfields. + struct { + Object *ewif; // [0:0] Early wakeup interrupt flag + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32WWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_WWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x-patch.json b/gnu-mcu-eclipse/devices/support/STM32F429x-patch.json new file mode 100644 index 0000000000..889d5d0ddd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x-patch.json @@ -0,0 +1,147 @@ +{ + "comment": "Patch for QEMU use.", + "device": { + "name": "STM32F429x", + "cpu": { + "name": "CM4", + "revision": "r0p1", + "endian": "little", + "mpuPresent": "true", + "fpuPresent": "true", + "nvicPrioBits": "4", + "deviceNumInterrupts": "91", + "vendorSystickConfig": "false", + "qemuItmPresent": "true" + }, + "access": "read-write", + "qemuAlignment": "any", + "peripherals": [ + { + "name": "GPIOA", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOB", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOC", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOD", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOE", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOF", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOG", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOH", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOI", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOJ", + "qemuGroupName": "GPIO" + }, + { + "name": "GPIOK", + "qemuGroupName": "GPIO" + }, + { + "name": "USART1", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART2", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART3", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "USART6", + "qemuGroupName": "USART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART4", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "UART5", + "qemuGroupName": "UART", + "qemuAlignment": "word-halfWord" + }, + { + "name": "ADC1", + "qemuGroupName": "ADC" + }, + { + "name": "ADC2", + "qemuGroupName": "ADC" + }, + { + "name": "ADC3", + "qemuGroupName": "ADC" + }, + { + "name": "I2C1", + "qemuGroupName": "I2C" + }, + { + "name": "I2C2", + "qemuGroupName": "I2C" + }, + { + "name": "I2C3", + "qemuGroupName": "I2C" + }, + { + "name": "CAN1", + "qemuGroupName": "CAN" + }, + { + "name": "CAN2", + "qemuGroupName": "CAN" + }, + { + "name": "DMA1", + "qemuGroupName": "DMA" + }, + { + "name": "DMA2", + "qemuGroupName": "DMA" + }, + { + "name": "SPI1", + "qemuGroupName": "SPI" + }, + { + "name": "SPI2", + "qemuGroupName": "SPI" + }, + { + "name": "SPI3", + "qemuGroupName": "SPI" + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x-xsvd.json b/gnu-mcu-eclipse/devices/support/STM32F429x-xsvd.json new file mode 100644 index 0000000000..3024a5c9d3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x-xsvd.json @@ -0,0 +1,55395 @@ +{ + "warning": "DO NOT EDIT! Automatically generated from STM32F429x.svd", + "generators": [ + { + "tool": "xcdl", + "version": "1.6.9", + "command": [ + "svd-convert", + "--file", + "/Users/ilg/Library/xPacks/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F429x.svd", + "--output", + "STM32F429x-xsvd.json" + ], + "date": "2016-12-20T10:25:56.691Z" + } + ], + "device": { + "xml": { + "schemaVersion": "1.1", + "xmlns:xs": "http://www.w3.org/2001/XMLSchema-instance", + "xs:noNamespaceSchemaLocation": "CMSIS-SVD_Schema_1_1.xsd" + }, + "name": "STM32F429x", + "version": "1.0", + "description": "STM32F429x", + "addressUnitBits": "8", + "width": "32", + "size": "0x20", + "resetValue": "0x0", + "resetMask": "0xFFFFFFFF", + "peripherals": [ + { + "name": "RNG", + "description": "Random number generator", + "groupName": "RNG", + "baseAddress": "0x50060800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FPU", + "description": "FPU interrupt", + "value": "81" + }, + { + "name": "RNG", + "description": "Rng global interrupt", + "value": "80" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IE", + "description": "Interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RNGEN", + "description": "Random number generator enable", + "bitOffset": "2", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEIS", + "description": "Seed error interrupt status", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CEIS", + "description": "Clock error interrupt status", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SECS", + "description": "Seed error current status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CECS", + "description": "Clock error current status", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DRDY", + "description": "Data ready", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RNDATA", + "description": "Random data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DCMI", + "description": "Digital camera interface", + "groupName": "DCMI", + "baseAddress": "0x50050000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DCMI", + "description": "DCMI global interrupt", + "value": "78" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ENABLE", + "description": "DCMI enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "EDM", + "description": "Extended data mode", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "FCRC", + "description": "Frame capture rate control", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "VSPOL", + "description": "Vertical synchronization polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "HSPOL", + "description": "Horizontal synchronization polarity", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PCKPOL", + "description": "Pixel clock polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ESS", + "description": "Embedded synchronization select", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JPEG", + "description": "JPEG format", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CROP", + "description": "Crop feature", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CM", + "description": "Capture mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CAPTURE", + "description": "Capture enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "FNE", + "description": "FIFO not empty", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "VSYNC", + "description": "VSYNC", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HSYNC", + "description": "HSYNC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "RIS", + "displayName": "RIS", + "description": "Raw interrupt status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_RIS", + "description": "Line raw interrupt status", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_RIS", + "description": "VSYNC raw interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_RIS", + "description": "Synchronization error raw interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_RIS", + "description": "Overrun raw interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_RIS", + "description": "Capture complete raw interrupt status", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_IE", + "description": "Line interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_IE", + "description": "VSYNC interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_IE", + "description": "Synchronization error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_IE", + "description": "Overrun interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_IE", + "description": "Capture complete interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "MIS", + "displayName": "MIS", + "description": "Masked interrupt status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_MIS", + "description": "Line masked interrupt status", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_MIS", + "description": "VSYNC masked interrupt status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_MIS", + "description": "Synchronization error masked interrupt status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_MIS", + "description": "Overrun masked interrupt status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_MIS", + "description": "Capture complete masked interrupt status", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINE_ISC", + "description": "Line interrupt status clear", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "VSYNC_ISC", + "description": "Vertical synch interrupt status clear", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ERR_ISC", + "description": "Synchronization error interrupt status clear", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OVR_ISC", + "description": "Overrun interrupt status clear", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FRAME_ISC", + "description": "Capture complete interrupt status clear", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ESCR", + "displayName": "ESCR", + "description": "Embedded synchronization code register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FEC", + "description": "Frame end delimiter code", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "LEC", + "description": "Line end delimiter code", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "LSC", + "description": "Line start delimiter code", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "FSC", + "description": "Frame start delimiter code", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ESUR", + "displayName": "ESUR", + "description": "Embedded synchronization unmask register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "FEU", + "description": "Frame end delimiter unmask", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "LEU", + "description": "Line end delimiter unmask", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "LSU", + "description": "Line start delimiter unmask", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "FSU", + "description": "Frame start delimiter unmask", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CWSTRT", + "displayName": "CWSTRT", + "description": "Crop window start", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "VST", + "description": "Vertical start line count", + "bitOffset": "16", + "bitWidth": "13" + }, + { + "name": "HOFFCNT", + "description": "Horizontal offset count", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "CWSIZE", + "displayName": "CWSIZE", + "description": "Crop window size", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "VLINE", + "description": "Vertical line count", + "bitOffset": "16", + "bitWidth": "14" + }, + { + "name": "CAPCNT", + "description": "Capture count", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "Byte3", + "description": "Data byte 3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "Byte2", + "description": "Data byte 2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "Byte1", + "description": "Data byte 1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "Byte0", + "description": "Data byte 0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "FMC", + "description": "Flexible memory controller", + "groupName": "FSMC", + "baseAddress": "0xA0000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FMC", + "description": "FMC global interrupt", + "value": "48" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "SRAM/NOR-Flash chip-select control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CCLKEN", + "description": "CCLKEN", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR1", + "displayName": "BTR1", + "description": "SRAM/NOR-Flash chip-select timing register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "SRAM/NOR-Flash chip-select control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR2", + "displayName": "BTR2", + "description": "SRAM/NOR-Flash chip-select timing register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR3", + "displayName": "BCR3", + "description": "SRAM/NOR-Flash chip-select control register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR3", + "displayName": "BTR3", + "description": "SRAM/NOR-Flash chip-select timing register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BCR4", + "displayName": "BCR4", + "description": "SRAM/NOR-Flash chip-select control register 4", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000030D0", + "fields": [ + { + "name": "CBURSTRW", + "description": "CBURSTRW", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "ASYNCWAIT", + "description": "ASYNCWAIT", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "EXTMOD", + "description": "EXTMOD", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "WAITEN", + "description": "WAITEN", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WREN", + "description": "WREN", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAITCFG", + "description": "WAITCFG", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WRAPMOD", + "description": "WRAPMOD", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPOL", + "description": "WAITPOL", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BURSTEN", + "description": "BURSTEN", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACCEN", + "description": "FACCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MWID", + "description": "MWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MTYP", + "description": "MTYP", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MUXEN", + "description": "MUXEN", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MBKEN", + "description": "MBKEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BTR4", + "displayName": "BTR4", + "description": "SRAM/NOR-Flash chip-select timing register 4", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "BUSTURN", + "description": "BUSTURN", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "PCR2", + "displayName": "PCR2", + "description": "PC Card/NAND Flash control register 2", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "FIFO status and interrupt register 2", + "addressOffset": "0x64", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM2", + "displayName": "PMEM2", + "description": "Common memory space timing register 2", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT2", + "displayName": "PATT2", + "description": "Attribute memory space timing register 2", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR2", + "displayName": "ECCR2", + "description": "ECC result register 2", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR3", + "displayName": "PCR3", + "description": "PC Card/NAND Flash control register 3", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR3", + "displayName": "SR3", + "description": "FIFO status and interrupt register 3", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM3", + "displayName": "PMEM3", + "description": "Common memory space timing register 3", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT3", + "displayName": "PATT3", + "description": "Attribute memory space timing register 3", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ECCR3", + "displayName": "ECCR3", + "description": "ECC result register 3", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ECCx", + "description": "ECCx", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PCR4", + "displayName": "PCR4", + "description": "PC Card/NAND Flash control register 4", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000018", + "fields": [ + { + "name": "ECCPS", + "description": "ECCPS", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "TAR", + "description": "TAR", + "bitOffset": "13", + "bitWidth": "4" + }, + { + "name": "TCLR", + "description": "TCLR", + "bitOffset": "9", + "bitWidth": "4" + }, + { + "name": "ECCEN", + "description": "ECCEN", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PWID", + "description": "PWID", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PTYP", + "description": "PTYP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PBKEN", + "description": "PBKEN", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PWAITEN", + "description": "PWAITEN", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "SR4", + "displayName": "SR4", + "description": "FIFO status and interrupt register 4", + "addressOffset": "0xA4", + "size": "0x20", + "resetValue": "0x00000040", + "fields": [ + { + "name": "FEMPT", + "description": "FEMPT", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IFEN", + "description": "IFEN", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILEN", + "description": "ILEN", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IREN", + "description": "IREN", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IFS", + "description": "IFS", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ILS", + "description": "ILS", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IRS", + "description": "IRS", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PMEM4", + "displayName": "PMEM4", + "description": "Common memory space timing register 4", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "MEMHIZx", + "description": "MEMHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "MEMHOLDx", + "description": "MEMHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "MEMWAITx", + "description": "MEMWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "MEMSETx", + "description": "MEMSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PATT4", + "displayName": "PATT4", + "description": "Attribute memory space timing register 4", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "ATTHIZx", + "description": "ATTHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "ATTHOLDx", + "description": "ATTHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "ATTWAITx", + "description": "ATTWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ATTSETx", + "description": "ATTSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PIO4", + "displayName": "PIO4", + "description": "I/O space timing register 4", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFCFCFCFC", + "fields": [ + { + "name": "IOHIZx", + "description": "IOHIZx", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "IOHOLDx", + "description": "IOHOLDx", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IOWAITx", + "description": "IOWAITx", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IOSETx", + "description": "IOSETx", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BWTR1", + "displayName": "BWTR1", + "description": "SRAM/NOR-Flash write timing registers 1", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR2", + "displayName": "BWTR2", + "description": "SRAM/NOR-Flash write timing registers 2", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR3", + "displayName": "BWTR3", + "description": "SRAM/NOR-Flash write timing registers 3", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BWTR4", + "displayName": "BWTR4", + "description": "SRAM/NOR-Flash write timing registers 4", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "ACCMOD", + "description": "ACCMOD", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DATLAT", + "description": "DATLAT", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "CLKDIV", + "description": "CLKDIV", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "DATAST", + "description": "DATAST", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "ADDHLD", + "description": "ADDHLD", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ADDSET", + "description": "ADDSET", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "SDCR1", + "displayName": "SDCR1", + "description": "SDRAM Control Register 1", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000002D0", + "fields": [ + { + "name": "NC", + "description": "Number of column address bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NR", + "description": "Number of row address bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "Memory data bus width", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "NB", + "description": "Number of internal banks", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CAS", + "description": "CAS latency", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "WP", + "description": "Write protection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SDCLK", + "description": "SDRAM clock configuration", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "RBURST", + "description": "Burst read", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RPIPE", + "description": "Read pipe", + "bitOffset": "13", + "bitWidth": "2" + } + ] + }, + { + "name": "SDCR2", + "displayName": "SDCR2", + "description": "SDRAM Control Register 2", + "addressOffset": "0x144", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000002D0", + "fields": [ + { + "name": "NC", + "description": "Number of column address bits", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NR", + "description": "Number of row address bits", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MWID", + "description": "Memory data bus width", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "NB", + "description": "Number of internal banks", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CAS", + "description": "CAS latency", + "bitOffset": "7", + "bitWidth": "2" + }, + { + "name": "WP", + "description": "Write protection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SDCLK", + "description": "SDRAM clock configuration", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "RBURST", + "description": "Burst read", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "RPIPE", + "description": "Read pipe", + "bitOffset": "13", + "bitWidth": "2" + } + ] + }, + { + "name": "SDTR1", + "displayName": "SDTR1", + "description": "SDRAM Timing register 1", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "TMRD", + "description": "Load Mode Register to Active", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TXSR", + "description": "Exit self-refresh delay", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "TRAS", + "description": "Self refresh time", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "TRC", + "description": "Row cycle delay", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "TWR", + "description": "Recovery delay", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TRP", + "description": "Row precharge delay", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "TRCD", + "description": "Row to column delay", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "SDTR2", + "displayName": "SDTR2", + "description": "SDRAM Timing register 2", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFFFFF", + "fields": [ + { + "name": "TMRD", + "description": "Load Mode Register to Active", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "TXSR", + "description": "Exit self-refresh delay", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "TRAS", + "description": "Self refresh time", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "TRC", + "description": "Row cycle delay", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "TWR", + "description": "Recovery delay", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "TRP", + "description": "Row precharge delay", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "TRCD", + "description": "Row to column delay", + "bitOffset": "24", + "bitWidth": "4" + } + ] + }, + { + "name": "SDCMR", + "displayName": "SDCMR", + "description": "SDRAM Command Mode register", + "addressOffset": "0x150", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODE", + "description": "Command mode", + "bitOffset": "0", + "bitWidth": "3", + "access": "write-only" + }, + { + "name": "CTB2", + "description": "Command target bank 2", + "bitOffset": "3", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CTB1", + "description": "Command target bank 1", + "bitOffset": "4", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "NRFS", + "description": "Number of Auto-refresh", + "bitOffset": "5", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "MRD", + "description": "Mode Register definition", + "bitOffset": "9", + "bitWidth": "13", + "access": "read-write" + } + ] + }, + { + "name": "SDRTR", + "displayName": "SDRTR", + "description": "SDRAM Refresh Timer register", + "addressOffset": "0x154", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CRE", + "description": "Clear Refresh error flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "COUNT", + "description": "Refresh Timer Count", + "bitOffset": "1", + "bitWidth": "13", + "access": "read-write" + }, + { + "name": "REIE", + "description": "RES Interrupt Enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SDSR", + "displayName": "SDSR", + "description": "SDRAM Status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RE", + "description": "Refresh error flag", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MODES1", + "description": "Status Mode for Bank 1", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "MODES2", + "description": "Status Mode for Bank 2", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "BUSY", + "description": "Busy status", + "bitOffset": "5", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DBG", + "description": "Debug support", + "groupName": "DBG", + "baseAddress": "0xE0042000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DBGMCU_IDCODE", + "displayName": "DBGMCU_IDCODE", + "description": "IDCODE", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x10006411", + "fields": [ + { + "name": "DEV_ID", + "description": "DEV_ID", + "bitOffset": "0", + "bitWidth": "12" + }, + { + "name": "REV_ID", + "description": "REV_ID", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DBGMCU_CR", + "displayName": "DBGMCU_CR", + "description": "Control Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_SLEEP", + "description": "DBG_SLEEP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_STOP", + "description": "DBG_STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_STANDBY", + "description": "DBG_STANDBY", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TRACE_IOEN", + "description": "TRACE_IOEN", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRACE_MODE", + "description": "TRACE_MODE", + "bitOffset": "6", + "bitWidth": "2" + } + ] + }, + { + "name": "DBGMCU_APB1_FZ", + "displayName": "DBGMCU_APB1_FZ", + "description": "Debug MCU APB1 Freeze registe", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM2_STOP", + "description": "DBG_TIM2_STOP", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM3_STOP", + "description": "DBG_TIM3 _STOP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM4_STOP", + "description": "DBG_TIM4_STOP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DBG_TIM5_STOP", + "description": "DBG_TIM5_STOP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DBG_TIM6_STOP", + "description": "DBG_TIM6_STOP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DBG_TIM7_STOP", + "description": "DBG_TIM7_STOP", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "DBG_TIM12_STOP", + "description": "DBG_TIM12_STOP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DBG_TIM13_STOP", + "description": "DBG_TIM13_STOP", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DBG_TIM14_STOP", + "description": "DBG_TIM14_STOP", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBG_WWDG_STOP", + "description": "DBG_WWDG_STOP", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBG_IWDEG_STOP", + "description": "DBG_IWDEG_STOP", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DBG_J2C1_SMBUS_TIMEOUT", + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DBG_J2C2_SMBUS_TIMEOUT", + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBG_J2C3SMBUS_TIMEOUT", + "description": "DBG_J2C3SMBUS_TIMEOUT", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DBG_CAN1_STOP", + "description": "DBG_CAN1_STOP", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DBG_CAN2_STOP", + "description": "DBG_CAN2_STOP", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DBGMCU_APB2_FZ", + "displayName": "DBGMCU_APB2_FZ", + "description": "Debug MCU APB2 Freeze registe", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DBG_TIM1_STOP", + "description": "TIM1 counter stopped when core is halted", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DBG_TIM8_STOP", + "description": "TIM8 counter stopped when core is halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DBG_TIM9_STOP", + "description": "TIM9 counter stopped when core is halted", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DBG_TIM10_STOP", + "description": "TIM10 counter stopped when core is halted", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "DBG_TIM11_STOP", + "description": "TIM11 counter stopped when core is halted", + "bitOffset": "18", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "DMA2", + "description": "DMA controller", + "groupName": "DMA", + "baseAddress": "0x40026400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA2_Stream0", + "description": "DMA2 Stream0 global interrupt", + "value": "56" + }, + { + "name": "DMA2_Stream1", + "description": "DMA2 Stream1 global interrupt", + "value": "57" + }, + { + "name": "DMA2_Stream2", + "description": "DMA2 Stream2 global interrupt", + "value": "58" + }, + { + "name": "DMA2_Stream3", + "description": "DMA2 Stream3 global interrupt", + "value": "59" + }, + { + "name": "DMA2_Stream4", + "description": "DMA2 Stream4 global interrupt", + "value": "60" + }, + { + "name": "DMA2_Stream5", + "description": "DMA2 Stream5 global interrupt", + "value": "68" + }, + { + "name": "DMA2_Stream6", + "description": "DMA2 Stream6 global interrupt", + "value": "69" + }, + { + "name": "DMA2_Stream7", + "description": "DMA2 Stream7 global interrupt", + "value": "70" + } + ], + "registers": [ + { + "name": "LISR", + "displayName": "LISR", + "description": "Low interrupt status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TCIF3", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "HTIF3", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF3", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMEIF3", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FEIF3", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TCIF2", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF2", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEIF2", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMEIF2", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FEIF2", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF1", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HTIF1", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF1", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMEIF1", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FEIF1", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCIF0", + "description": "Stream x transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF0", + "description": "Stream x half transfer interrupt flag (x=3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TEIF0", + "description": "Stream x transfer error interrupt flag (x=3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMEIF0", + "description": "Stream x direct mode error interrupt flag (x=3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FEIF0", + "description": "Stream x FIFO error interrupt flag (x=3..0)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "HISR", + "displayName": "HISR", + "description": "High interrupt status register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TCIF7", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "HTIF7", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "TEIF7", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMEIF7", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FEIF7", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "TCIF6", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "HTIF6", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TEIF6", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMEIF6", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FEIF6", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TCIF5", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "HTIF5", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TEIF5", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMEIF5", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FEIF5", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TCIF4", + "description": "Stream x transfer complete interrupt flag (x=7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "HTIF4", + "description": "Stream x half transfer interrupt flag (x=7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TEIF4", + "description": "Stream x transfer error interrupt flag (x=7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DMEIF4", + "description": "Stream x direct mode error interrupt flag (x=7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FEIF4", + "description": "Stream x FIFO error interrupt flag (x=7..4)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LIFCR", + "displayName": "LIFCR", + "description": "Low interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTCIF3", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "CHTIF3", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF3", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CDMEIF3", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CFEIF3", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTCIF2", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF2", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTEIF2", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CDMEIF2", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CFEIF2", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF1", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHTIF1", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF1", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CDMEIF1", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CFEIF1", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTCIF0", + "description": "Stream x clear transfer complete interrupt flag (x = 3..0)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF0", + "description": "Stream x clear half transfer interrupt flag (x = 3..0)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTEIF0", + "description": "Stream x clear transfer error interrupt flag (x = 3..0)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CDMEIF0", + "description": "Stream x clear direct mode error interrupt flag (x = 3..0)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CFEIF0", + "description": "Stream x clear FIFO error interrupt flag (x = 3..0)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "HIFCR", + "displayName": "HIFCR", + "description": "High interrupt flag clear register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CTCIF7", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "CHTIF7", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "CTEIF7", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CDMEIF7", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "CFEIF7", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "CTCIF6", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CHTIF6", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CTEIF6", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "CDMEIF6", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CFEIF6", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "CTCIF5", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CHTIF5", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTEIF5", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CDMEIF5", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CFEIF5", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CTCIF4", + "description": "Stream x clear transfer complete interrupt flag (x = 7..4)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CHTIF4", + "description": "Stream x clear half transfer interrupt flag (x = 7..4)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CTEIF4", + "description": "Stream x clear transfer error interrupt flag (x = 7..4)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CDMEIF4", + "description": "Stream x clear direct mode error interrupt flag (x = 7..4)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CFEIF4", + "description": "Stream x clear FIFO error interrupt flag (x = 7..4)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S0CR", + "displayName": "S0CR", + "description": "Stream x configuration register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S0NDTR", + "displayName": "S0NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S0PAR", + "displayName": "S0PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M0AR", + "displayName": "S0M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0M1AR", + "displayName": "S0M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S0FCR", + "displayName": "S0FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x24", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S1CR", + "displayName": "S1CR", + "description": "Stream x configuration register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S1NDTR", + "displayName": "S1NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S1PAR", + "displayName": "S1PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M0AR", + "displayName": "S1M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1M1AR", + "displayName": "S1M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S1FCR", + "displayName": "S1FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x3C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S2CR", + "displayName": "S2CR", + "description": "Stream x configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S2NDTR", + "displayName": "S2NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S2PAR", + "displayName": "S2PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M0AR", + "displayName": "S2M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2M1AR", + "displayName": "S2M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S2FCR", + "displayName": "S2FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x54", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S3CR", + "displayName": "S3CR", + "description": "Stream x configuration register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S3NDTR", + "displayName": "S3NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S3PAR", + "displayName": "S3PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M0AR", + "displayName": "S3M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3M1AR", + "displayName": "S3M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S3FCR", + "displayName": "S3FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x6C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S4CR", + "displayName": "S4CR", + "description": "Stream x configuration register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S4NDTR", + "displayName": "S4NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S4PAR", + "displayName": "S4PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M0AR", + "displayName": "S4M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4M1AR", + "displayName": "S4M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S4FCR", + "displayName": "S4FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x84", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S5CR", + "displayName": "S5CR", + "description": "Stream x configuration register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S5NDTR", + "displayName": "S5NDTR", + "description": "Stream x number of data register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S5PAR", + "displayName": "S5PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M0AR", + "displayName": "S5M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5M1AR", + "displayName": "S5M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S5FCR", + "displayName": "S5FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0x9C", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S6CR", + "displayName": "S6CR", + "description": "Stream x configuration register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S6NDTR", + "displayName": "S6NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xA4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S6PAR", + "displayName": "S6PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xA8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M0AR", + "displayName": "S6M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6M1AR", + "displayName": "S6M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S6FCR", + "displayName": "S6FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xB4", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + }, + { + "name": "S7CR", + "displayName": "S7CR", + "description": "Stream x configuration register", + "addressOffset": "0xB8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CHSEL", + "description": "Channel selection", + "bitOffset": "25", + "bitWidth": "3" + }, + { + "name": "MBURST", + "description": "Memory burst transfer configuration", + "bitOffset": "23", + "bitWidth": "2" + }, + { + "name": "PBURST", + "description": "Peripheral burst transfer configuration", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "ACK", + "description": "ACK", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "CT", + "description": "Current target (only in double buffer mode)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DBM", + "description": "Double buffer mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PL", + "description": "Priority level", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PINCOS", + "description": "Peripheral increment offset size", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MSIZE", + "description": "Memory data size", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "PSIZE", + "description": "Peripheral data size", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "MINC", + "description": "Memory increment mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PINC", + "description": "Peripheral increment mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CIRC", + "description": "Circular mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DIR", + "description": "Data transfer direction", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PFCTRL", + "description": "Peripheral flow controller", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HTIE", + "description": "Half transfer interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DMEIE", + "description": "Direct mode error interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN", + "description": "Stream enable / flag stream ready when read low", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "S7NDTR", + "displayName": "S7NDTR", + "description": "Stream x number of data register", + "addressOffset": "0xBC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "NDT", + "description": "Number of data items to transfer", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "S7PAR", + "displayName": "S7PAR", + "description": "Stream x peripheral address register", + "addressOffset": "0xC0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PA", + "description": "Peripheral address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M0AR", + "displayName": "S7M0AR", + "description": "Stream x memory 0 address register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M0A", + "description": "Memory 0 address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7M1AR", + "displayName": "S7M1AR", + "description": "Stream x memory 1 address register", + "addressOffset": "0xC8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "M1A", + "description": "Memory 1 address (used in case of Double buffer mode)", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "S7FCR", + "displayName": "S7FCR", + "description": "Stream x FIFO control register", + "addressOffset": "0xCC", + "size": "0x20", + "resetValue": "0x00000021", + "fields": [ + { + "name": "FEIE", + "description": "FIFO error interrupt enable", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FS", + "description": "FIFO status", + "bitOffset": "3", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DMDIS", + "description": "Direct mode disable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FTH", + "description": "FIFO threshold selection", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + } + ] + } + ] + }, + { + "name": "DMA1", + "derivedFrom": "DMA2", + "baseAddress": "0x40026000", + "interrupts": [ + { + "name": "DMA1_Stream0", + "description": "DMA1 Stream0 global interrupt", + "value": "11" + }, + { + "name": "DMA1_Stream1", + "description": "DMA1 Stream1 global interrupt", + "value": "12" + }, + { + "name": "DMA1_Stream2", + "description": "DMA1 Stream2 global interrupt", + "value": "13" + }, + { + "name": "DMA1_Stream3", + "description": "DMA1 Stream3 global interrupt", + "value": "14" + }, + { + "name": "DMA1_Stream4", + "description": "DMA1 Stream4 global interrupt", + "value": "15" + }, + { + "name": "DMA1_Stream5", + "description": "DMA1 Stream5 global interrupt", + "value": "16" + }, + { + "name": "DMA1_Stream6", + "description": "DMA1 Stream6 global interrupt", + "value": "17" + }, + { + "name": "DMA1_Stream7", + "description": "DMA1 Stream7 global interrupt", + "value": "47" + } + ] + }, + { + "name": "RCC", + "description": "Reset and clock control", + "groupName": "RCC", + "baseAddress": "0x40023800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RCC", + "description": "RCC global interrupt", + "value": "5" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Clock control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000083", + "fields": [ + { + "name": "PLLI2SRDY", + "description": "PLLI2S clock ready flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SON", + "description": "PLLI2S enable", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDY", + "description": "Main PLL (PLL) clock ready flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLON", + "description": "Main PLL (PLL) enable", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSON", + "description": "Clock security system enable", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSEBYP", + "description": "HSE clock bypass", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDY", + "description": "HSE clock ready flag", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSEON", + "description": "HSE clock enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSICAL", + "description": "Internal high-speed clock calibration", + "bitOffset": "8", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "HSITRIM", + "description": "Internal high-speed clock trimming", + "bitOffset": "3", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "HSIRDY", + "description": "Internal high-speed clock ready flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSION", + "description": "Internal high-speed clock enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "PLLCFGR", + "displayName": "PLLCFGR", + "description": "PLL configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003010", + "fields": [ + { + "name": "PLLQ3", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "PLLQ2", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PLLQ1", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "PLLQ0", + "description": "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "PLLSRC", + "description": "Main PLL(PLL) and audio PLL (PLLI2S) entry clock source", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "PLLP1", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PLLP0", + "description": "Main PLL (PLL) division factor for main system clock", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PLLN8", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PLLN7", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PLLN6", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PLLN5", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PLLN4", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PLLN3", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PLLN2", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PLLN1", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PLLN0", + "description": "Main PLL (PLL) multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PLLM5", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PLLM4", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLLM3", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLLM2", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PLLM1", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PLLM0", + "description": "Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CFGR", + "displayName": "CFGR", + "description": "Clock configuration register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCO2", + "description": "Microcontroller clock output 2", + "bitOffset": "30", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "MCO2PRE", + "description": "MCO2 prescaler", + "bitOffset": "27", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "MCO1PRE", + "description": "MCO1 prescaler", + "bitOffset": "24", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "I2SSRC", + "description": "I2S clock selection", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MCO1", + "description": "Microcontroller clock output 1", + "bitOffset": "21", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "RTCPRE", + "description": "HSE division factor for RTC clock", + "bitOffset": "16", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "PPRE2", + "description": "APB high-speed prescaler (APB2)", + "bitOffset": "13", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PPRE1", + "description": "APB Low speed prescaler (APB1)", + "bitOffset": "10", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "HPRE", + "description": "AHB prescaler", + "bitOffset": "4", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "SWS1", + "description": "System clock switch status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SWS0", + "description": "System clock switch status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SW1", + "description": "System clock switch", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SW0", + "description": "System clock switch", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CIR", + "displayName": "CIR", + "description": "Clock interrupt register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CSSC", + "description": "Clock security system interrupt clear", + "bitOffset": "23", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLSAIRDYC", + "description": "PLLSAI Ready Interrupt Clear", + "bitOffset": "22", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLI2SRDYC", + "description": "PLLI2S ready interrupt clear", + "bitOffset": "21", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLRDYC", + "description": "Main PLL(PLL) ready interrupt clear", + "bitOffset": "20", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSERDYC", + "description": "HSE ready interrupt clear", + "bitOffset": "19", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "HSIRDYC", + "description": "HSI ready interrupt clear", + "bitOffset": "18", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSERDYC", + "description": "LSE ready interrupt clear", + "bitOffset": "17", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "LSIRDYC", + "description": "LSI ready interrupt clear", + "bitOffset": "16", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "PLLSAIRDYIE", + "description": "PLLSAI Ready Interrupt Enable", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLI2SRDYIE", + "description": "PLLI2S ready interrupt enable", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLLRDYIE", + "description": "Main PLL (PLL) ready interrupt enable", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSERDYIE", + "description": "HSE ready interrupt enable", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSIRDYIE", + "description": "HSI ready interrupt enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDYIE", + "description": "LSE ready interrupt enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDYIE", + "description": "LSI ready interrupt enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CSSF", + "description": "Clock security system interrupt flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLSAIRDYF", + "description": "PLLSAI ready interrupt flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLI2SRDYF", + "description": "PLLI2S ready interrupt flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PLLRDYF", + "description": "Main PLL (PLL) ready interrupt flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSERDYF", + "description": "HSE ready interrupt flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HSIRDYF", + "description": "HSI ready interrupt flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSERDYF", + "description": "LSE ready interrupt flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSIRDYF", + "description": "LSI ready interrupt flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "AHB1RSTR", + "displayName": "AHB1RSTR", + "description": "AHB1 peripheral reset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGHSRST", + "description": "USB OTG HS module reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "ETHMACRST", + "description": "Ethernet MAC reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMA2DRST", + "description": "DMA2D reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DMA2RST", + "description": "DMA2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1RST", + "description": "DMA2 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CRCRST", + "description": "CRC reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOKRST", + "description": "IO port K reset", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "GPIOJRST", + "description": "IO port J reset", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "GPIOIRST", + "description": "IO port I reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOHRST", + "description": "IO port H reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOGRST", + "description": "IO port G reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOFRST", + "description": "IO port F reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOERST", + "description": "IO port E reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODRST", + "description": "IO port D reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCRST", + "description": "IO port C reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBRST", + "description": "IO port B reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOARST", + "description": "IO port A reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2RSTR", + "displayName": "AHB2RSTR", + "description": "AHB2 peripheral reset register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSRST", + "description": "USB OTG FS module reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RNGRST", + "description": "Random number generator module reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCMIRST", + "description": "Camera interface reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3RSTR", + "displayName": "AHB3RSTR", + "description": "AHB3 peripheral reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMCRST", + "description": "Flexible memory controller module reset", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1RSTR", + "displayName": "APB1RSTR", + "description": "APB1 peripheral reset register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2RST", + "description": "TIM2 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3RST", + "description": "TIM3 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4RST", + "description": "TIM4 reset", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5RST", + "description": "TIM5 reset", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6RST", + "description": "TIM6 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7RST", + "description": "TIM7 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12RST", + "description": "TIM12 reset", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13RST", + "description": "TIM13 reset", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14RST", + "description": "TIM14 reset", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGRST", + "description": "Window watchdog reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2RST", + "description": "SPI 2 reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3RST", + "description": "SPI 3 reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UART2RST", + "description": "USART 2 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "UART3RST", + "description": "USART 3 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4RST", + "description": "USART 4 reset", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5RST", + "description": "USART 5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1RST", + "description": "I2C 1 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2RST", + "description": "I2C 2 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3RST", + "description": "I2C3 reset", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1RST", + "description": "CAN1 reset", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2RST", + "description": "CAN2 reset", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWRRST", + "description": "Power interface reset", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACRST", + "description": "DAC reset", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "UART7RST", + "description": "UART7 reset", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "UART8RST", + "description": "UART8 reset", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2RSTR", + "displayName": "APB2RSTR", + "description": "APB2 peripheral reset register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1RST", + "description": "TIM1 reset", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8RST", + "description": "TIM8 reset", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1RST", + "description": "USART1 reset", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6RST", + "description": "USART6 reset", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADCRST", + "description": "ADC interface reset (common to all ADCs)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SDIORST", + "description": "SDIO reset", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1RST", + "description": "SPI 1 reset", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4RST", + "description": "SPI4 reset", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGRST", + "description": "System configuration controller reset", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9RST", + "description": "TIM9 reset", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10RST", + "description": "TIM10 reset", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11RST", + "description": "TIM11 reset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SPI5RST", + "description": "SPI5 reset", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SPI6RST", + "description": "SPI6 reset", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SAI1RST", + "description": "SAI1 reset", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "LTDCRST", + "description": "LTDC reset", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1ENR", + "displayName": "AHB1ENR", + "description": "AHB1 peripheral clock register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00100000", + "fields": [ + { + "name": "OTGHSULPIEN", + "description": "USB OTG HSULPI clock enable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "OTGHSEN", + "description": "USB OTG HS clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPEN", + "description": "Ethernet PTP clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "ETHMACRXEN", + "description": "Ethernet Reception clock enable", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACTXEN", + "description": "Ethernet Transmission clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACEN", + "description": "Ethernet MAC clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DMA2DEN", + "description": "DMA2D clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "DMA2EN", + "description": "DMA2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA1EN", + "description": "DMA1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "CCMDATARAMEN", + "description": "CCM data RAM clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BKPSRAMEN", + "description": "Backup SRAM interface clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "CRC clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "GPIOKEN", + "description": "IO port K clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "GPIOJEN", + "description": "IO port J clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "GPIOIEN", + "description": "IO port I clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOHEN", + "description": "IO port H clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOGEN", + "description": "IO port G clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOFEN", + "description": "IO port F clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOEEN", + "description": "IO port E clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIODEN", + "description": "IO port D clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOCEN", + "description": "IO port C clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIOBEN", + "description": "IO port B clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOAEN", + "description": "IO port A clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2ENR", + "displayName": "AHB2ENR", + "description": "AHB2 peripheral clock enable register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OTGFSEN", + "description": "USB OTG FS clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RNGEN", + "description": "Random number generator clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCMIEN", + "description": "Camera interface enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3ENR", + "displayName": "AHB3ENR", + "description": "AHB3 peripheral clock enable register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FMCEN", + "description": "Flexible memory controller module clock enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1ENR", + "displayName": "APB1ENR", + "description": "APB1 peripheral clock enable register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM2EN", + "description": "TIM2 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3EN", + "description": "TIM3 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4EN", + "description": "TIM4 clock enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5EN", + "description": "TIM5 clock enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6EN", + "description": "TIM6 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7EN", + "description": "TIM7 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12EN", + "description": "TIM12 clock enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13EN", + "description": "TIM13 clock enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14EN", + "description": "TIM14 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGEN", + "description": "Window watchdog clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2EN", + "description": "SPI2 clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3EN", + "description": "SPI3 clock enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2EN", + "description": "USART 2 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3EN", + "description": "USART3 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4EN", + "description": "UART4 clock enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5EN", + "description": "UART5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1EN", + "description": "I2C1 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2EN", + "description": "I2C2 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3EN", + "description": "I2C3 clock enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1EN", + "description": "CAN 1 clock enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2EN", + "description": "CAN 2 clock enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWREN", + "description": "Power interface clock enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACEN", + "description": "DAC interface clock enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "UART7ENR", + "description": "UART7 clock enable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "UART8ENR", + "description": "UART8 clock enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2ENR", + "displayName": "APB2ENR", + "description": "APB2 peripheral clock enable register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIM1EN", + "description": "TIM1 clock enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8EN", + "description": "TIM8 clock enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1EN", + "description": "USART1 clock enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6EN", + "description": "USART6 clock enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1EN", + "description": "ADC1 clock enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC2EN", + "description": "ADC2 clock enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC3EN", + "description": "ADC3 clock enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOEN", + "description": "SDIO clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1EN", + "description": "SPI1 clock enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4ENR", + "description": "SPI4 clock enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGEN", + "description": "System configuration controller clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9EN", + "description": "TIM9 clock enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10EN", + "description": "TIM10 clock enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11EN", + "description": "TIM11 clock enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SPI5ENR", + "description": "SPI5 clock enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SPI6ENR", + "description": "SPI6 clock enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SAI1EN", + "description": "SAI1 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "LTDCEN", + "description": "LTDC clock enable", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB1LPENR", + "displayName": "AHB1LPENR", + "description": "AHB1 peripheral clock enable in low power mode register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7E6791FF", + "fields": [ + { + "name": "GPIOALPEN", + "description": "IO port A clock enable during sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GPIOBLPEN", + "description": "IO port B clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "GPIOCLPEN", + "description": "IO port C clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "GPIODLPEN", + "description": "IO port D clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "GPIOELPEN", + "description": "IO port E clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "GPIOFLPEN", + "description": "IO port F clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GPIOGLPEN", + "description": "IO port G clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GPIOHLPEN", + "description": "IO port H clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "GPIOILPEN", + "description": "IO port I clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "GPIOJLPEN", + "description": "IO port J clock enable during Sleep mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "GPIOKLPEN", + "description": "IO port K clock enable during Sleep mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CRCLPEN", + "description": "CRC clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FLITFLPEN", + "description": "Flash interface clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SRAM1LPEN", + "description": "SRAM 1interface clock enable during Sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SRAM2LPEN", + "description": "SRAM 2 interface clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BKPSRAMLPEN", + "description": "Backup SRAM interface clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SRAM3LPEN", + "description": "SRAM 3 interface clock enable during Sleep mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMA1LPEN", + "description": "DMA1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DMA2LPEN", + "description": "DMA2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DMA2DLPEN", + "description": "DMA2D clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ETHMACLPEN", + "description": "Ethernet MAC clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "ETHMACTXLPEN", + "description": "Ethernet transmission clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "ETHMACRXLPEN", + "description": "Ethernet reception clock enable during Sleep mode", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "ETHMACPTPLPEN", + "description": "Ethernet PTP clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "OTGHSLPEN", + "description": "USB OTG HS clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "OTGHSULPILPEN", + "description": "USB OTG HS ULPI clock enable during Sleep mode", + "bitOffset": "30", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB2LPENR", + "displayName": "AHB2LPENR", + "description": "AHB2 peripheral clock enable in low power mode register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000F1", + "fields": [ + { + "name": "OTGFSLPEN", + "description": "USB OTG FS clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RNGLPEN", + "description": "Random number generator clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "DCMILPEN", + "description": "Camera interface enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AHB3LPENR", + "displayName": "AHB3LPENR", + "description": "AHB3 peripheral clock enable in low power mode register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000001", + "fields": [ + { + "name": "FMCLPEN", + "description": "Flexible memory controller module clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "APB1LPENR", + "displayName": "APB1LPENR", + "description": "APB1 peripheral clock enable in low power mode register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x36FEC9FF", + "fields": [ + { + "name": "TIM2LPEN", + "description": "TIM2 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM3LPEN", + "description": "TIM3 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TIM4LPEN", + "description": "TIM4 clock enable during Sleep mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TIM5LPEN", + "description": "TIM5 clock enable during Sleep mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TIM6LPEN", + "description": "TIM6 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TIM7LPEN", + "description": "TIM7 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TIM12LPEN", + "description": "TIM12 clock enable during Sleep mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TIM13LPEN", + "description": "TIM13 clock enable during Sleep mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIM14LPEN", + "description": "TIM14 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WWDGLPEN", + "description": "Window watchdog clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI2LPEN", + "description": "SPI2 clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SPI3LPEN", + "description": "SPI3 clock enable during Sleep mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "USART2LPEN", + "description": "USART2 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "USART3LPEN", + "description": "USART3 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "UART4LPEN", + "description": "UART4 clock enable during Sleep mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "UART5LPEN", + "description": "UART5 clock enable during Sleep mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "I2C1LPEN", + "description": "I2C1 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "I2C2LPEN", + "description": "I2C2 clock enable during Sleep mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "I2C3LPEN", + "description": "I2C3 clock enable during Sleep mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CAN1LPEN", + "description": "CAN 1 clock enable during Sleep mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "CAN2LPEN", + "description": "CAN 2 clock enable during Sleep mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "PWRLPEN", + "description": "Power interface clock enable during Sleep mode", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "DACLPEN", + "description": "DAC interface clock enable during Sleep mode", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "UART7LPEN", + "description": "UART7 clock enable during Sleep mode", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "UART8LPEN", + "description": "UART8 clock enable during Sleep mode", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "APB2LPENR", + "displayName": "APB2LPENR", + "description": "APB2 peripheral clock enabled in low power mode register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00075F33", + "fields": [ + { + "name": "TIM1LPEN", + "description": "TIM1 clock enable during Sleep mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TIM8LPEN", + "description": "TIM8 clock enable during Sleep mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "USART1LPEN", + "description": "USART1 clock enable during Sleep mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "USART6LPEN", + "description": "USART6 clock enable during Sleep mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADC1LPEN", + "description": "ADC1 clock enable during Sleep mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ADC2LPEN", + "description": "ADC2 clock enable during Sleep mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ADC3LPEN", + "description": "ADC 3 clock enable during Sleep mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SDIOLPEN", + "description": "SDIO clock enable during Sleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SPI1LPEN", + "description": "SPI 1 clock enable during Sleep mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SPI4LPEN", + "description": "SPI 4 clock enable during Sleep mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SYSCFGLPEN", + "description": "System configuration controller clock enable during Sleep mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TIM9LPEN", + "description": "TIM9 clock enable during sleep mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TIM10LPEN", + "description": "TIM10 clock enable during Sleep mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TIM11LPEN", + "description": "TIM11 clock enable during Sleep mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SPI5LPEN", + "description": "SPI 5 clock enable during Sleep mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SPI6LPEN", + "description": "SPI 6 clock enable during Sleep mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SAI1LPEN", + "description": "SAI1 clock enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "LTDCLPEN", + "description": "LTDC clock enable", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "BDCR", + "displayName": "BDCR", + "description": "Backup domain control register", + "addressOffset": "0x70", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BDRST", + "description": "Backup domain software reset", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCEN", + "description": "RTC clock enable", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL1", + "description": "RTC clock source selection", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RTCSEL0", + "description": "RTC clock source selection", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSEBYP", + "description": "External low-speed oscillator bypass", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSERDY", + "description": "External low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSEON", + "description": "External low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Clock control & status register", + "addressOffset": "0x74", + "size": "0x20", + "resetValue": "0x0E000000", + "fields": [ + { + "name": "LPWRRSTF", + "description": "Low-power reset flag", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WDGRSTF", + "description": "Independent watchdog reset flag", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SFTRSTF", + "description": "Software reset flag", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PORRSTF", + "description": "POR/PDR reset flag", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PADRSTF", + "description": "PIN reset flag", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BORRSTF", + "description": "BOR reset flag", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RMVF", + "description": "Remove reset flag", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LSIRDY", + "description": "Internal low-speed oscillator ready", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LSION", + "description": "Internal low-speed oscillator enable", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SSCGR", + "displayName": "SSCGR", + "description": "Spread spectrum clock generation register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SSCGEN", + "description": "Spread spectrum modulation enable", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SPREADSEL", + "description": "Spread Select", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "INCSTEP", + "description": "Incrementation step", + "bitOffset": "13", + "bitWidth": "15" + }, + { + "name": "MODPER", + "description": "Modulation period", + "bitOffset": "0", + "bitWidth": "13" + } + ] + }, + { + "name": "PLLI2SCFGR", + "displayName": "PLLI2SCFGR", + "description": "PLLI2S configuration register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x20003000", + "fields": [ + { + "name": "PLLI2SR", + "description": "PLLI2S division factor for I2S clocks", + "bitOffset": "28", + "bitWidth": "3" + }, + { + "name": "PLLI2SQ", + "description": "PLLI2S division factor for SAI1 clock", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "PLLI2SN", + "description": "PLLI2S multiplication factor for VCO", + "bitOffset": "6", + "bitWidth": "9" + } + ] + }, + { + "name": "PLLSAICFGR", + "displayName": "PLLSAICFGR", + "description": "PLLSAICFGR", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x24003000", + "fields": [ + { + "name": "PLLSAIN", + "description": "PLLSAIN", + "bitOffset": "6", + "bitWidth": "9" + }, + { + "name": "PLLSAIQ", + "description": "PLLSAIN", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "PLLSAIR", + "description": "PLLSAIN", + "bitOffset": "28", + "bitWidth": "3" + } + ] + }, + { + "name": "DCKCFGR", + "displayName": "DCKCFGR", + "description": "DCKCFGR", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PLLI2SDIVQ", + "description": "PLLI2SDIVQ", + "bitOffset": "0", + "bitWidth": "5" + }, + { + "name": "PLLSAIDIVQ", + "description": "PLLSAIDIVQ", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "PLLSAIDIVR", + "description": "PLLSAIDIVR", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "SAI1ASRC", + "description": "SAI1ASRC", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "SAI1BSRC", + "description": "SAI1BSRC", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "TIMPRE", + "description": "TIMPRE", + "bitOffset": "24", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "GPIOK", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40022800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "GPIOJ", + "derivedFrom": "GPIOK", + "baseAddress": "0x40022400" + }, + { + "name": "GPIOI", + "derivedFrom": "GPIOK", + "baseAddress": "0x40022000" + }, + { + "name": "GPIOH", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021C00" + }, + { + "name": "GPIOG", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021800" + }, + { + "name": "GPIOF", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021400" + }, + { + "name": "GPIOE", + "derivedFrom": "GPIOK", + "baseAddress": "0x40021000" + }, + { + "name": "GPIOD", + "derivedFrom": "GPIOK", + "baseAddress": "0X40020C00" + }, + { + "name": "GPIOC", + "derivedFrom": "GPIOK", + "baseAddress": "0x40020800" + }, + { + "name": "GPIOB", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000280", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000000C0", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000100", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "GPIOA", + "description": "General-purpose I/Os", + "groupName": "GPIO", + "baseAddress": "0x40020000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MODER", + "displayName": "MODER", + "description": "GPIO port mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xA8000000", + "fields": [ + { + "name": "MODER15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "MODER14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "MODER13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "MODER12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "MODER11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "MODER10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "MODER9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MODER8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "MODER7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "MODER6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "MODER5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "MODER4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MODER3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "MODER2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "MODER1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODER0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "OTYPER", + "displayName": "OTYPER", + "description": "GPIO port output type register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OT15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OT14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OT13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OT12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OT11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OT10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OT9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OT8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OT7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OT6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OT5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "OT4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OT3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OT2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "OT1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OT0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OSPEEDR", + "displayName": "OSPEEDR", + "description": "GPIO port output speed register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OSPEEDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "OSPEEDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "OSPEEDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "OSPEEDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "OSPEEDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "OSPEEDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "OSPEEDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "OSPEEDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "OSPEEDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "OSPEEDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "OSPEEDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "OSPEEDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OSPEEDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "OSPEEDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "OSPEEDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "OSPEEDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "PUPDR", + "displayName": "PUPDR", + "description": "GPIO port pull-up/pull-down register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x64000000", + "fields": [ + { + "name": "PUPDR15", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "30", + "bitWidth": "2" + }, + { + "name": "PUPDR14", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "PUPDR13", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "26", + "bitWidth": "2" + }, + { + "name": "PUPDR12", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "PUPDR11", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "PUPDR10", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "PUPDR9", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "PUPDR8", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "PUPDR7", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "PUPDR6", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "PUPDR5", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "PUPDR4", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PUPDR3", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "PUPDR2", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "PUPDR1", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "PUPDR0", + "description": "Port x configuration bits (y = 0..15)", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "GPIO port input data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR15", + "description": "Port input data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "IDR14", + "description": "Port input data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "IDR13", + "description": "Port input data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "IDR12", + "description": "Port input data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "IDR11", + "description": "Port input data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "IDR10", + "description": "Port input data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "IDR9", + "description": "Port input data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IDR8", + "description": "Port input data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "IDR7", + "description": "Port input data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "IDR6", + "description": "Port input data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "IDR5", + "description": "Port input data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDR4", + "description": "Port input data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "IDR3", + "description": "Port input data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IDR2", + "description": "Port input data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IDR1", + "description": "Port input data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IDR0", + "description": "Port input data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ODR", + "displayName": "ODR", + "description": "GPIO port output data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ODR15", + "description": "Port output data (y = 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ODR14", + "description": "Port output data (y = 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ODR13", + "description": "Port output data (y = 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ODR12", + "description": "Port output data (y = 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ODR11", + "description": "Port output data (y = 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ODR10", + "description": "Port output data (y = 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ODR9", + "description": "Port output data (y = 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODR8", + "description": "Port output data (y = 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ODR7", + "description": "Port output data (y = 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ODR6", + "description": "Port output data (y = 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ODR5", + "description": "Port output data (y = 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ODR4", + "description": "Port output data (y = 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ODR3", + "description": "Port output data (y = 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ODR2", + "description": "Port output data (y = 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "ODR1", + "description": "Port output data (y = 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ODR0", + "description": "Port output data (y = 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSRR", + "displayName": "BSRR", + "description": "GPIO port bit set/reset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BR15", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "BR14", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "BR13", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "BR12", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "BR11", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "BR10", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "BR9", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "BR8", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "BR7", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "BR6", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "BR5", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "BR4", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BR3", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "BR2", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BR1", + "description": "Port x reset bit y (y = 0..15)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "BR0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "BS15", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BS14", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BS13", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BS12", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "BS11", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BS10", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "BS9", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BS8", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BS7", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BS6", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BS5", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "BS4", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BS3", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "BS2", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BS1", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BS0", + "description": "Port x set bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LCKR", + "displayName": "LCKR", + "description": "GPIO port configuration lock register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LCKK", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "LCK15", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LCK14", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "LCK13", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "LCK12", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "LCK11", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LCK10", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LCK9", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LCK8", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LCK7", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "LCK6", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LCK5", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "LCK4", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "LCK3", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "LCK2", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "LCK1", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LCK0", + "description": "Port x lock bit y (y= 0..15)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "AFRL", + "displayName": "AFRL", + "description": "GPIO alternate function low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRL7", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRL6", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRL5", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRL4", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRL3", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRL2", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRL1", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRL0", + "description": "Alternate function selection for port x bit y (y = 0..7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "AFRH", + "displayName": "AFRH", + "description": "GPIO alternate function high register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AFRH15", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "28", + "bitWidth": "4" + }, + { + "name": "AFRH14", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "AFRH13", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "AFRH12", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "AFRH11", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "AFRH10", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "AFRH9", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "AFRH8", + "description": "Alternate function selection for port x bit y (y = 8..15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "SYSCFG", + "description": "System configuration controller", + "groupName": "SYSCFG", + "baseAddress": "0x40013800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MEMRM", + "displayName": "MEMRM", + "description": "Memory remap register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MEM_MODE", + "description": "Memory mapping selection", + "bitOffset": "0", + "bitWidth": "3" + }, + { + "name": "FB_MODE", + "description": "Flash bank mode selection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWP_FMC", + "description": "FMC memory mapping swap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + }, + { + "name": "PMC", + "displayName": "PMC", + "description": "Peripheral mode configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MII_RMII_SEL", + "description": "Ethernet PHY interface selection", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "ADC1DC2", + "description": "ADC1DC2", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ADC2DC2", + "description": "ADC2DC2", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADC3DC2", + "description": "ADC3DC2", + "bitOffset": "18", + "bitWidth": "1" + } + ] + }, + { + "name": "EXTICR1", + "displayName": "EXTICR1", + "description": "External interrupt configuration register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI3", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI2", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI1", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI0", + "description": "EXTI x configuration (x = 0 to 3)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR2", + "displayName": "EXTICR2", + "description": "External interrupt configuration register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI7", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI6", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI5", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI4", + "description": "EXTI x configuration (x = 4 to 7)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR3", + "displayName": "EXTICR3", + "description": "External interrupt configuration register 3", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI11", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI10", + "description": "EXTI10", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI9", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI8", + "description": "EXTI x configuration (x = 8 to 11)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "EXTICR4", + "displayName": "EXTICR4", + "description": "External interrupt configuration register 4", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "EXTI15", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "EXTI14", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "EXTI13", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "EXTI12", + "description": "EXTI x configuration (x = 12 to 15)", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CMPCR", + "displayName": "CMPCR", + "description": "Compensation cell control register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "READY", + "description": "READY", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMP_PD", + "description": "Compensation cell power-down", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "SPI1", + "description": "Serial peripheral interface", + "groupName": "SPI", + "baseAddress": "0x40013000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SPI1", + "description": "SPI1 global interrupt", + "value": "35" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "BIDIMODE", + "description": "Bidirectional data mode enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "BIDIOE", + "description": "Output enable in bidirectional mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CRCEN", + "description": "Hardware CRC calculation enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CRCNEXT", + "description": "CRC transfer next", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DFF", + "description": "Data frame format", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RXONLY", + "description": "Receive only", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SSM", + "description": "Software slave management", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SSI", + "description": "Internal slave select", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Frame format", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SPE", + "description": "SPI enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "BR", + "description": "Baud rate control", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "MSTR", + "description": "Master selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TXEIE", + "description": "Tx buffer empty interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RX buffer not empty interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FRF", + "description": "Frame format", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SSOE", + "description": "SS output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TXDMAEN", + "description": "Tx buffer DMA enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RXDMAEN", + "description": "Rx buffer DMA enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x0002", + "fields": [ + { + "name": "TIFRFE", + "description": "TI frame format error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSY", + "description": "Busy flag", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OVR", + "description": "Overrun flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MODF", + "description": "Mode fault", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CRCERR", + "description": "CRC error flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "UDR", + "description": "Underrun flag", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CHSIDE", + "description": "Channel side", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXE", + "description": "Transmit buffer empty", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXNE", + "description": "Receive buffer not empty", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "Data register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CRCPR", + "displayName": "CRCPR", + "description": "CRC polynomial register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0007", + "fields": [ + { + "name": "CRCPOLY", + "description": "CRC polynomial register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RXCRCR", + "displayName": "RXCRCR", + "description": "RX CRC register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "RxCRC", + "description": "Rx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "TXCRCR", + "displayName": "TXCRCR", + "description": "TX CRC register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TxCRC", + "description": "Tx CRC register", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "I2SCFGR", + "displayName": "I2SCFGR", + "description": "I2S configuration register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "I2SMOD", + "description": "I2S mode selection", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "I2SE", + "description": "I2S Enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "I2SCFG", + "description": "I2S configuration mode", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "PCMSYNC", + "description": "PCM frame synchronization", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "I2SSTD", + "description": "I2S standard selection", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "CKPOL", + "description": "Steady state clock polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DATLEN", + "description": "Data length to be transferred", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "CHLEN", + "description": "Channel length (number of bits per audio channel)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "I2SPR", + "displayName": "I2SPR", + "description": "I2S prescaler register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "00000010", + "fields": [ + { + "name": "MCKOE", + "description": "Master clock output enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ODD", + "description": "Odd factor for the prescaler", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "I2SDIV", + "description": "I2S Linear prescaler", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "SPI2", + "derivedFrom": "SPI1", + "baseAddress": "0x40003800", + "interrupts": [ + { + "name": "SPI2", + "description": "SPI2 global interrupt", + "value": "36" + } + ] + }, + { + "name": "SPI3", + "derivedFrom": "SPI1", + "baseAddress": "0x40003C00", + "interrupts": [ + { + "name": "SPI3", + "description": "SPI3 global interrupt", + "value": "51" + } + ] + }, + { + "name": "I2S2ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40003400" + }, + { + "name": "I2S3ext", + "derivedFrom": "SPI1", + "baseAddress": "0x40004000" + }, + { + "name": "SPI4", + "derivedFrom": "SPI1", + "baseAddress": "0x40013400", + "interrupts": [ + { + "name": "SPI4", + "description": "SPI 4 global interrupt", + "value": "84" + } + ] + }, + { + "name": "SPI5", + "derivedFrom": "SPI1", + "baseAddress": "0x40015000", + "interrupts": [ + { + "name": "SPI5", + "description": "SPI 5 global interrupt", + "value": "85" + } + ] + }, + { + "name": "SPI6", + "derivedFrom": "SPI1", + "baseAddress": "0x40015400", + "interrupts": [ + { + "name": "SPI6", + "description": "SPI 6 global interrupt", + "value": "86" + } + ] + }, + { + "name": "SDIO", + "description": "Secure digital input/output interface", + "groupName": "SDIO", + "baseAddress": "0x40012C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SDIO", + "description": "SDIO global interrupt", + "value": "49" + } + ], + "registers": [ + { + "name": "POWER", + "displayName": "POWER", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRCTRL", + "description": "PWRCTRL", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CLKCR", + "displayName": "CLKCR", + "description": "SDI clock control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HWFC_EN", + "description": "HW Flow Control enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "NEGEDGE", + "description": "SDIO_CK dephasing selection bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "WIDBUS", + "description": "Wide bus mode enable bit", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "BYPASS", + "description": "Clock divider bypass enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PWRSAV", + "description": "Power saving configuration bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CLKEN", + "description": "Clock enable bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CLKDIV", + "description": "Clock divide factor", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ARG", + "displayName": "ARG", + "description": "Argument register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CMDARG", + "description": "Command argument", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "CMD", + "displayName": "CMD", + "description": "Command register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CE_ATACMD", + "description": "CE-ATA command", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "nIEN", + "description": "Not Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ENCMDcompl", + "description": "Enable CMD completion", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SDIOSuspend", + "description": "SD I/O suspend command", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPSMEN", + "description": "Command path state machine (CPSM) Enable bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "WAITPEND", + "description": "CPSM Waits for ends of data transfer (CmdPend internal signal).", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WAITINT", + "description": "CPSM waits for interrupt request", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WAITRESP", + "description": "Wait for response bits", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "CMDINDEX", + "description": "Command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESPCMD", + "displayName": "RESPCMD", + "description": "Command response register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RESPCMD", + "description": "Response command index", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "RESP1", + "displayName": "RESP1", + "description": "Response 1..4 register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS1", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP2", + "displayName": "RESP2", + "description": "Response 1..4 register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS2", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP3", + "displayName": "RESP3", + "description": "Response 1..4 register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS3", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "RESP4", + "displayName": "RESP4", + "description": "Response 1..4 register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CARDSTATUS4", + "description": "See Table 132.", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DTIMER", + "displayName": "DTIMER", + "description": "Data timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATATIME", + "description": "Data timeout period", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DLEN", + "displayName": "DLEN", + "description": "Data length register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATALENGTH", + "description": "Data length value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "DCTRL", + "displayName": "DCTRL", + "description": "Data control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SDIOEN", + "description": "SD I/O enable functions", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "RWMOD", + "description": "Read wait mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "RWSTOP", + "description": "Read wait stop", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RWSTART", + "description": "Read wait start", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DBLOCKSIZE", + "description": "Data block size", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "DMAEN", + "description": "DMA enable bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DTMODE", + "description": "Data transfer mode selection 1: Stream or SDIO multibyte data transfer.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DTDIR", + "description": "Data transfer direction selection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DTEN", + "description": "DTEN", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DCOUNT", + "displayName": "DCOUNT", + "description": "Data counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATACOUNT", + "description": "Data count value", + "bitOffset": "0", + "bitWidth": "25" + } + ] + }, + { + "name": "STA", + "displayName": "STA", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAEND", + "description": "CE-ATA command completion signal received for CMD61", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOIT", + "description": "SDIO interrupt received", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "RXDAVL", + "description": "Data available in receive FIFO", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TXDAVL", + "description": "Data available in transmit FIFO", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXFIFOE", + "description": "Receive FIFO empty", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXFIFOE", + "description": "Transmit FIFO empty", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOF", + "description": "Receive FIFO full", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOF", + "description": "Transmit FIFO full", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOHF", + "description": "Receive FIFO half full: there are at least 8 words in the FIFO", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOHE", + "description": "Transmit FIFO half empty: at least 8 words can be written into the FIFO", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXACT", + "description": "Data receive in progress", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXACT", + "description": "Data transmit in progress", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMDACT", + "description": "Command transfer in progress", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBCKEND", + "description": "Data block sent/received (CRC check passed)", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERR", + "description": "Start bit not detected on all data signals in wide bus mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAEND", + "description": "Data end (data counter, SDIDCOUNT, is zero)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENT", + "description": "Command sent (no response required)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDREND", + "description": "Command response received (CRC check passed)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERR", + "description": "Received FIFO overrun error", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERR", + "description": "Transmit FIFO underrun error", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUT", + "description": "Data timeout", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUT", + "description": "Command response timeout", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAIL", + "description": "Data block sent/received (CRC check failed)", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAIL", + "description": "Command response received (CRC check failed)", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt clear register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAENDC", + "description": "CEATAEND flag clear bit", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOITC", + "description": "SDIOIT flag clear bit", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DBCKENDC", + "description": "DBCKEND flag clear bit", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERRC", + "description": "STBITERR flag clear bit", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAENDC", + "description": "DATAEND flag clear bit", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENTC", + "description": "CMDSENT flag clear bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDRENDC", + "description": "CMDREND flag clear bit", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERRC", + "description": "RXOVERR flag clear bit", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERRC", + "description": "TXUNDERR flag clear bit", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTC", + "description": "DTIMEOUT flag clear bit", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTC", + "description": "CTIMEOUT flag clear bit", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAILC", + "description": "DCRCFAIL flag clear bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAILC", + "description": "CCRCFAIL flag clear bit", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "MASK", + "displayName": "MASK", + "description": "Mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEATAENDIE", + "description": "CE-ATA command completion signal received interrupt enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "SDIOITIE", + "description": "SDIO mode interrupt received interrupt enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "RXDAVLIE", + "description": "Data available in Rx FIFO interrupt enable", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TXDAVLIE", + "description": "Data available in Tx FIFO interrupt enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "RXFIFOEIE", + "description": "Rx FIFO empty interrupt enable", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TXFIFOEIE", + "description": "Tx FIFO empty interrupt enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "RXFIFOFIE", + "description": "Rx FIFO full interrupt enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TXFIFOFIE", + "description": "Tx FIFO full interrupt enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXFIFOHFIE", + "description": "Rx FIFO half full interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TXFIFOHEIE", + "description": "Tx FIFO half empty interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "RXACTIE", + "description": "Data receive acting interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TXACTIE", + "description": "Data transmit acting interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CMDACTIE", + "description": "Command acting interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DBCKENDIE", + "description": "Data block end interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STBITERRIE", + "description": "Start bit error interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DATAENDIE", + "description": "Data end interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CMDSENTIE", + "description": "Command sent interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMDRENDIE", + "description": "Command response received interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXOVERRIE", + "description": "Rx FIFO overrun error interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXUNDERRIE", + "description": "Tx FIFO underrun error interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "DTIMEOUTIE", + "description": "Data timeout interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTIMEOUTIE", + "description": "Command timeout interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DCRCFAILIE", + "description": "Data CRC fail interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CCRCFAILIE", + "description": "Command CRC fail interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "FIFOCNT", + "displayName": "FIFOCNT", + "description": "FIFO counter register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOCOUNT", + "description": "Remaining number of words to be written to or read from the FIFO.", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "FIFO", + "displayName": "FIFO", + "description": "Data FIFO register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FIFOData", + "description": "Receive and transmit FIFO data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "ADC1", + "description": "Analog-to-digital converter", + "groupName": "ADC", + "baseAddress": "0x40012000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ADC", + "description": "ADC1 global interrupt", + "value": "18" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVR", + "description": "Overrun", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Regular channel start flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT", + "description": "Injected channel start flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC", + "description": "Injected channel end of conversion", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC", + "description": "Regular channel end of conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "RES", + "description": "Resolution", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable on regular channels", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "JAWDEN", + "description": "Analog watchdog enable on injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "DISCNUM", + "description": "Discontinuous mode channel count", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "JDISCEN", + "description": "Discontinuous mode on injected channels", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DISCEN", + "description": "Discontinuous mode on regular channels", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JAUTO", + "description": "Automatic injected group conversion", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel in scan mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SCAN", + "description": "Scan mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "JEOCIE", + "description": "Interrupt enable for injected channels", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "EOCIE", + "description": "Interrupt enable for EOC", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel select bits", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWSTART", + "description": "Start conversion of regular channels", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "EXTEN", + "description": "External trigger enable for regular channels", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "EXTSEL", + "description": "External event select for regular group", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "JSWSTART", + "description": "Start conversion of injected channels", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "JEXTEN", + "description": "External trigger enable for injected channels", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JEXTSEL", + "description": "External event select for injected group", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "EOCS", + "description": "End of conversion selection", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DDS", + "description": "DMA disable selection (for single ADC mode)", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DMA", + "description": "Direct memory access mode (for single ADC mode)", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CONT", + "description": "Continuous conversion", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ADON", + "description": "A/D Converter ON / OFF", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMPR1", + "displayName": "SMPR1", + "description": "Sample time register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SMPR2", + "displayName": "SMPR2", + "description": "Sample time register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SMPx_x", + "description": "Sample time bits", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "JOFR1", + "displayName": "JOFR1", + "description": "Injected channel data offset register x", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET1", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR2", + "displayName": "JOFR2", + "description": "Injected channel data offset register x", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET2", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR3", + "displayName": "JOFR3", + "description": "Injected channel data offset register x", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET3", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "JOFR4", + "displayName": "JOFR4", + "description": "Injected channel data offset register x", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JOFFSET4", + "description": "Data offset for injected channel x", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "HTR", + "displayName": "HTR", + "description": "Watchdog higher threshold register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "LTR", + "displayName": "LTR", + "description": "Watchdog lower threshold register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SQR1", + "displayName": "SQR1", + "description": "Regular sequence register 1", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "L", + "description": "Regular channel sequence length", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "SQ16", + "description": "16th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ15", + "description": "15th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ14", + "description": "14th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ13", + "description": "13th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR2", + "displayName": "SQR2", + "description": "Regular sequence register 2", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ12", + "description": "12th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ11", + "description": "11th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ10", + "description": "10th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ9", + "description": "9th conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ8", + "description": "8th conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ7", + "description": "7th conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "SQR3", + "displayName": "SQR3", + "description": "Regular sequence register 3", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SQ6", + "description": "6th conversion in regular sequence", + "bitOffset": "25", + "bitWidth": "5" + }, + { + "name": "SQ5", + "description": "5th conversion in regular sequence", + "bitOffset": "20", + "bitWidth": "5" + }, + { + "name": "SQ4", + "description": "4th conversion in regular sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "SQ3", + "description": "3rd conversion in regular sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "SQ2", + "description": "2nd conversion in regular sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "SQ1", + "description": "1st conversion in regular sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JSQR", + "displayName": "JSQR", + "description": "Injected sequence register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JL", + "description": "Injected sequence length", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "JSQ4", + "description": "4th conversion in injected sequence", + "bitOffset": "15", + "bitWidth": "5" + }, + { + "name": "JSQ3", + "description": "3rd conversion in injected sequence", + "bitOffset": "10", + "bitWidth": "5" + }, + { + "name": "JSQ2", + "description": "2nd conversion in injected sequence", + "bitOffset": "5", + "bitWidth": "5" + }, + { + "name": "JSQ1", + "description": "1st conversion in injected sequence", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "JDR1", + "displayName": "JDR1", + "description": "Injected data register x", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR2", + "displayName": "JDR2", + "description": "Injected data register x", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR3", + "displayName": "JDR3", + "description": "Injected data register x", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "JDR4", + "displayName": "JDR4", + "description": "Injected data register x", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "JDATA", + "description": "Injected data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Regular data register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Regular data", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "ADC2", + "derivedFrom": "ADC1", + "baseAddress": "0x40012100", + "interrupts": [ + { + "name": "ADC", + "description": "ADC2 global interrupts", + "value": "18" + } + ] + }, + { + "name": "ADC3", + "derivedFrom": "ADC1", + "baseAddress": "0x40012200", + "interrupts": [ + { + "name": "ADC", + "description": "ADC3 global interrupts", + "value": "18" + } + ] + }, + { + "name": "USART6", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40011400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "USART6", + "description": "USART6 global interrupt", + "value": "71" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "CTS", + "description": "CTS flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "CLKEN", + "description": "Clock enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CPOL", + "description": "Clock polarity", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CPHA", + "description": "Clock phase", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LBCL", + "description": "Last bit clock pulse", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CTSIE", + "description": "CTS interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CTSE", + "description": "CTS enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RTSE", + "description": "RTS enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SCEN", + "description": "Smartcard mode enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NACK", + "description": "Smartcard NACK enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "GTPR", + "displayName": "GTPR", + "description": "Guard time and prescaler register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "GT", + "description": "Guard time value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "USART1", + "derivedFrom": "USART6", + "baseAddress": "0x40011000", + "interrupts": [ + { + "name": "USART1", + "description": "USART1 global interrupt", + "value": "37" + } + ] + }, + { + "name": "USART2", + "derivedFrom": "USART6", + "baseAddress": "0x40004400", + "interrupts": [ + { + "name": "USART2", + "description": "USART2 global interrupt", + "value": "38" + } + ] + }, + { + "name": "USART3", + "derivedFrom": "USART6", + "baseAddress": "0x40004800", + "interrupts": [ + { + "name": "USART3", + "description": "USART3 global interrupt", + "value": "39" + } + ] + }, + { + "name": "UART7", + "derivedFrom": "USART6", + "baseAddress": "0x40007800", + "interrupts": [ + { + "name": "UART7", + "description": "UART 7 global interrupt", + "value": "82" + } + ] + }, + { + "name": "UART8", + "derivedFrom": "USART6", + "baseAddress": "0x40007C00", + "interrupts": [ + { + "name": "UART8", + "description": "UART 8 global interrupt", + "value": "83" + } + ] + }, + { + "name": "DAC", + "description": "Digital-to-analog converter", + "groupName": "DAC", + "baseAddress": "0x40007400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDRIE2", + "description": "DAC channel2 DMA underrun interrupt enable", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "DMAEN2", + "description": "DAC channel2 DMA enable", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "MAMP2", + "description": "DAC channel2 mask/amplitude selector", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "WAVE2", + "description": "DAC channel2 noise/triangle wave generation enable", + "bitOffset": "22", + "bitWidth": "2" + }, + { + "name": "TSEL2", + "description": "DAC channel2 trigger selection", + "bitOffset": "19", + "bitWidth": "3" + }, + { + "name": "TEN2", + "description": "DAC channel2 trigger enable", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "BOFF2", + "description": "DAC channel2 output buffer disable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EN2", + "description": "DAC channel2 enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "DMAUDRIE1", + "description": "DAC channel1 DMA Underrun Interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DMAEN1", + "description": "DAC channel1 DMA enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MAMP1", + "description": "DAC channel1 mask/amplitude selector", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "WAVE1", + "description": "DAC channel1 noise/triangle wave generation enable", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "TSEL1", + "description": "DAC channel1 trigger selection", + "bitOffset": "3", + "bitWidth": "3" + }, + { + "name": "TEN1", + "description": "DAC channel1 trigger enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BOFF1", + "description": "DAC channel1 output buffer disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EN1", + "description": "DAC channel1 enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SWTRIGR", + "displayName": "SWTRIGR", + "description": "Software trigger register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWTRIG2", + "description": "DAC channel2 software trigger", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWTRIG1", + "description": "DAC channel1 software trigger", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DHR12R1", + "displayName": "DHR12R1", + "description": "Channel1 12-bit right-aligned data holding register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L1", + "displayName": "DHR12L1", + "description": "Channel1 12-bit left aligned data holding register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R1", + "displayName": "DHR8R1", + "description": "Channel1 8-bit right aligned data holding register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12R2", + "displayName": "DHR12R2", + "description": "Channel2 12-bit right aligned data holding register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12L2", + "displayName": "DHR12L2", + "description": "Channel2 12-bit left aligned data holding register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8R2", + "displayName": "DHR8R2", + "description": "Channel2 8-bit right-aligned data holding register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DHR12RD", + "displayName": "DHR12RD", + "description": "Dual DAC 12-bit right-aligned data holding register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit right-aligned data", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR12LD", + "displayName": "DHR12LD", + "description": "DUAL DAC 12-bit left aligned data holding register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 12-bit left-aligned data", + "bitOffset": "20", + "bitWidth": "12" + }, + { + "name": "DACC1DHR", + "description": "DAC channel1 12-bit left-aligned data", + "bitOffset": "4", + "bitWidth": "12" + } + ] + }, + { + "name": "DHR8RD", + "displayName": "DHR8RD", + "description": "DUAL DAC 8-bit right aligned data holding register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DHR", + "description": "DAC channel2 8-bit right-aligned data", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DACC1DHR", + "description": "DAC channel1 8-bit right-aligned data", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DOR1", + "displayName": "DOR1", + "description": "Channel1 data output register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC1DOR", + "description": "DAC channel1 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DOR2", + "displayName": "DOR2", + "description": "Channel2 data output register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DACC2DOR", + "description": "DAC channel2 data output", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DMAUDR2", + "description": "DAC channel2 DMA underrun flag", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "DMAUDR1", + "description": "DAC channel1 DMA underrun flag", + "bitOffset": "13", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "I2C3", + "description": "Inter-integrated circuit", + "groupName": "I2C", + "baseAddress": "0x40005C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "I2C3_EV", + "description": "I2C3 event interrupt", + "value": "72" + }, + { + "name": "I2C3_ER", + "description": "I2C3 error interrupt", + "value": "73" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "SWRST", + "description": "Software reset", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ALERT", + "description": "SMBus alert", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PEC", + "description": "Packet error checking", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "POS", + "description": "Acknowledge/PEC Position (for data reception)", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "Acknowledge enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "Stop generation", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start generation", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "NOSTRETCH", + "description": "Clock stretching disable (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ENGC", + "description": "General call enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "ENPEC", + "description": "PEC enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ENARP", + "description": "ARP enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SMBTYPE", + "description": "SMBus type", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SMBUS", + "description": "SMBus mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PE", + "description": "Peripheral enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LAST", + "description": "DMA last transfer", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA requests enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ITBUFEN", + "description": "Buffer interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ITEVTEN", + "description": "Event interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ITERREN", + "description": "Error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "Peripheral clock frequency", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "OAR1", + "displayName": "OAR1", + "description": "Own address register 1", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADDMODE", + "description": "Addressing mode (slave mode)", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ADD10", + "description": "Interface address", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ADD7", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ADD0", + "description": "Interface address", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "OAR2", + "displayName": "OAR2", + "description": "Own address register 2", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ADD2", + "description": "Interface address", + "bitOffset": "1", + "bitWidth": "7" + }, + { + "name": "ENDUAL", + "description": "Dual addressing mode enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DR", + "description": "8-bit data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SR1", + "displayName": "SR1", + "description": "Status register 1", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x0000", + "fields": [ + { + "name": "SMBALERT", + "description": "SMBus alert", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TIMEOUT", + "description": "Timeout or Tlow error", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PECERR", + "description": "PEC Error in reception", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OVR", + "description": "Overrun/Underrun", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AF", + "description": "Acknowledge failure", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ARLO", + "description": "Arbitration lost (master mode)", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Bus error", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TxE", + "description": "Data register empty (transmitters)", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RxNE", + "description": "Data register not empty (receivers)", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "STOPF", + "description": "Stop detection (slave mode)", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADD10", + "description": "10-bit header sent (Master mode)", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BTF", + "description": "Byte transfer finished", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ADDR", + "description": "Address sent (master mode)/matched (slave mode)", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SB", + "description": "Start bit (Master mode)", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "SR2", + "displayName": "SR2", + "description": "Status register 2", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "PEC", + "description": "Acket error checking register", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DUALF", + "description": "Dual flag (Slave mode)", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SMBHOST", + "description": "SMBus host header (Slave mode)", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SMBDEFAULT", + "description": "SMBus device default address (Slave mode)", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "GENCALL", + "description": "General call address (Slave mode)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TRA", + "description": "Transmitter/receiver", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "BUSY", + "description": "Bus busy", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MSL", + "description": "Master/slave", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "Clock control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "F_S", + "description": "I2C master mode selection", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "DUTY", + "description": "Fast mode duty cycle", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CCR", + "description": "Clock control register in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "TRISE", + "displayName": "TRISE", + "description": "TRISE register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0002", + "fields": [ + { + "name": "TRISE", + "description": "Maximum rise time in Fast/Standard mode (Master mode)", + "bitOffset": "0", + "bitWidth": "6" + } + ] + }, + { + "name": "FLTR", + "displayName": "FLTR", + "description": "I2C FLTR register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DNF", + "description": "Digital noise filter", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "ANOFF", + "description": "Analog noise filter OFF", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "I2C2", + "derivedFrom": "I2C3", + "baseAddress": "0x40005800", + "interrupts": [ + { + "name": "I2C2_EV", + "description": "I2C2 event interrupt", + "value": "33" + }, + { + "name": "I2C2_ER", + "description": "I2C2 error interrupt", + "value": "34" + } + ] + }, + { + "name": "I2C1", + "derivedFrom": "I2C3", + "baseAddress": "0x40005400", + "interrupts": [ + { + "name": "I2C1_EV", + "description": "I2C1 event interrupt", + "value": "31" + }, + { + "name": "I2C1_ER", + "description": "I2C1 error interrupt", + "value": "32" + } + ] + }, + { + "name": "IWDG", + "description": "Independent watchdog", + "groupName": "IWDG", + "baseAddress": "0x40003000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "KR", + "displayName": "KR", + "description": "Key register", + "addressOffset": "0x0", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Key value (write only, read 0000h)", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Prescaler register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR", + "description": "Prescaler divider", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "RLR", + "displayName": "RLR", + "description": "Reload register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000FFF", + "fields": [ + { + "name": "RL", + "description": "Watchdog counter reload value", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RVU", + "description": "Watchdog counter reload value update", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PVU", + "description": "Watchdog prescaler value update", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "WWDG", + "description": "Window watchdog", + "groupName": "WWDG", + "baseAddress": "0x40002C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "WWDG", + "description": "Window Watchdog interrupt", + "value": "0" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "WDGA", + "description": "Activation bit", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "T", + "description": "7-bit counter (MSB to LSB)", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "CFR", + "displayName": "CFR", + "description": "Configuration register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x7F", + "fields": [ + { + "name": "EWI", + "description": "Early wakeup interrupt", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WDGTB1", + "description": "Timer base", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "WDGTB0", + "description": "Timer base", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "W", + "description": "7-bit window value", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00", + "fields": [ + { + "name": "EWIF", + "description": "Early wakeup interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "RTC", + "description": "Real-time clock", + "groupName": "RTC", + "baseAddress": "0x40002800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "RTC_WKUP", + "description": "RTC Wakeup interrupt through the EXTI line", + "value": "3" + }, + { + "name": "RTC_Alarm", + "description": "RTC Alarms (A and B) through EXTI line interrupt", + "value": "41" + } + ], + "registers": [ + { + "name": "TR", + "displayName": "TR", + "description": "Time register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Date register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "YT", + "description": "Year tens in BCD format", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "YU", + "description": "Year units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COE", + "description": "Calibration output enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "OSEL", + "description": "Output selection", + "bitOffset": "21", + "bitWidth": "2" + }, + { + "name": "POL", + "description": "Output polarity", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Backup", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SUB1H", + "description": "Subtract 1 hour (winter time change)", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADD1H", + "description": "Add 1 hour (summer time change)", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TSIE", + "description": "Time-stamp interrupt enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "WUTIE", + "description": "Wakeup timer interrupt enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ALRBIE", + "description": "Alarm B interrupt enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ALRAIE", + "description": "Alarm A interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TSE", + "description": "Time stamp enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "WUTE", + "description": "Wakeup timer enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "ALRBE", + "description": "Alarm B enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ALRAE", + "description": "Alarm A enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DCE", + "description": "Coarse digital calibration enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FMT", + "description": "Hour format", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "REFCKON", + "description": "Reference clock detection enable (50 or 60 Hz)", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TSEDGE", + "description": "Time-stamp event active edge", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WCKSEL", + "description": "Wakeup clock selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Initialization and status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000007", + "fields": [ + { + "name": "ALRAWF", + "description": "Alarm A write flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ALRBWF", + "description": "Alarm B write flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "WUTWF", + "description": "Wakeup timer write flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SHPF", + "description": "Shift operation pending", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITS", + "description": "Initialization status flag", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RSF", + "description": "Registers synchronization flag", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INITF", + "description": "Initialization flag", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INIT", + "description": "Initialization mode", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRAF", + "description": "Alarm A flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALRBF", + "description": "Alarm B flag", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUTF", + "description": "Wakeup timer flag", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSF", + "description": "Time-stamp flag", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSOVF", + "description": "Time-stamp overflow flag", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP1F", + "description": "Tamper detection flag", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TAMP2F", + "description": "TAMPER2 detection flag", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RECALPF", + "description": "Recalibration pending Flag", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "PRER", + "displayName": "PRER", + "description": "Prescaler register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x007F00FF", + "fields": [ + { + "name": "PREDIV_A", + "description": "Asynchronous prescaler factor", + "bitOffset": "16", + "bitWidth": "7" + }, + { + "name": "PREDIV_S", + "description": "Synchronous prescaler factor", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "WUTR", + "displayName": "WUTR", + "description": "Wakeup timer register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "WUT", + "description": "Wakeup auto-reload value bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALIBR", + "displayName": "CALIBR", + "description": "Calibration register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCS", + "description": "Digital calibration sign", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "Digital calibration", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "ALRMAR", + "displayName": "ALRMAR", + "description": "Alarm A register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm A date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm A hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm A minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm A seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "ALRMBR", + "displayName": "ALRMBR", + "description": "Alarm B register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MSK4", + "description": "Alarm B date mask", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "WDSEL", + "description": "Week day selection", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "28", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units or day in BCD format", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "MSK3", + "description": "Alarm B hours mask", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "PM", + "description": "AM/PM notation", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "HT", + "description": "Hour tens in BCD format", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "HU", + "description": "Hour units in BCD format", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "MSK2", + "description": "Alarm B minutes mask", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MNT", + "description": "Minute tens in BCD format", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "MNU", + "description": "Minute units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSK1", + "description": "Alarm B seconds mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "Second tens in BCD format", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SU", + "description": "Second units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "WPR", + "displayName": "WPR", + "description": "Write protection register", + "addressOffset": "0x24", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "Write protection key", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "SSR", + "displayName": "SSR", + "description": "Sub second register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "SHIFTR", + "displayName": "SHIFTR", + "description": "Shift control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ADD1S", + "description": "Add one second", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "SUBFS", + "description": "Subtract a fraction of a second", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "TSTR", + "displayName": "TSTR", + "description": "Time stamp time register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TSDR", + "displayName": "TSDR", + "description": "Time stamp date register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WDU", + "description": "Week day units", + "bitOffset": "13", + "bitWidth": "3" + }, + { + "name": "MT", + "description": "Month tens in BCD format", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MU", + "description": "Month units in BCD format", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "DT", + "description": "Date tens in BCD format", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "DU", + "description": "Date units in BCD format", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TSSSR", + "displayName": "TSSSR", + "description": "Timestamp sub second register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SS", + "description": "Sub second value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CALR", + "displayName": "CALR", + "description": "Calibration register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CALP", + "description": "Increase frequency of RTC by 488.5 ppm", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CALW8", + "description": "Use an 8-second calibration cycle period", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CALW16", + "description": "Use a 16-second calibration cycle period", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CALM", + "description": "Calibration minus", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "TAFCR", + "displayName": "TAFCR", + "description": "Tamper and alternate function configuration register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALARMOUTTYPE", + "description": "AFO_ALARM output type", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSINSEL", + "description": "TIMESTAMP mapping", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TAMP1INSEL", + "description": "TAMPER1 mapping", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TAMPPUDIS", + "description": "TAMPER pull-up disable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TAMPPRCH", + "description": "Tamper precharge duration", + "bitOffset": "13", + "bitWidth": "2" + }, + { + "name": "TAMPFLT", + "description": "Tamper filter count", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "TAMPTS", + "description": "Activate timestamp on tamper detection event", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TAMP2TRG", + "description": "Active level for tamper 2", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TAMP2E", + "description": "Tamper 2 detection enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TAMPIE", + "description": "Tamper interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TAMP1TRG", + "description": "Active level for tamper 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TAMP1E", + "description": "Tamper 1 detection enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ALRMASSR", + "displayName": "ALRMASSR", + "description": "Alarm A sub second register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "ALRMBSSR", + "displayName": "ALRMBSSR", + "description": "Alarm B sub second register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MASKSS", + "description": "Mask the most-significant bits starting at this bit", + "bitOffset": "24", + "bitWidth": "4" + }, + { + "name": "SS", + "description": "Sub seconds value", + "bitOffset": "0", + "bitWidth": "15" + } + ] + }, + { + "name": "BKP0R", + "displayName": "BKP0R", + "description": "Backup register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP1R", + "displayName": "BKP1R", + "description": "Backup register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP2R", + "displayName": "BKP2R", + "description": "Backup register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP3R", + "displayName": "BKP3R", + "description": "Backup register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP4R", + "displayName": "BKP4R", + "description": "Backup register", + "addressOffset": "0x60", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP5R", + "displayName": "BKP5R", + "description": "Backup register", + "addressOffset": "0x64", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP6R", + "displayName": "BKP6R", + "description": "Backup register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP7R", + "displayName": "BKP7R", + "description": "Backup register", + "addressOffset": "0x6C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP8R", + "displayName": "BKP8R", + "description": "Backup register", + "addressOffset": "0x70", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP9R", + "displayName": "BKP9R", + "description": "Backup register", + "addressOffset": "0x74", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP10R", + "displayName": "BKP10R", + "description": "Backup register", + "addressOffset": "0x78", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP11R", + "displayName": "BKP11R", + "description": "Backup register", + "addressOffset": "0x7C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP12R", + "displayName": "BKP12R", + "description": "Backup register", + "addressOffset": "0x80", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP13R", + "displayName": "BKP13R", + "description": "Backup register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP14R", + "displayName": "BKP14R", + "description": "Backup register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP15R", + "displayName": "BKP15R", + "description": "Backup register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP16R", + "displayName": "BKP16R", + "description": "Backup register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP17R", + "displayName": "BKP17R", + "description": "Backup register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP18R", + "displayName": "BKP18R", + "description": "Backup register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BKP19R", + "displayName": "BKP19R", + "description": "Backup register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BKP", + "description": "BKP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "UART4", + "description": "Universal synchronous asynchronous receiver transmitter", + "groupName": "USART", + "baseAddress": "0x40004C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "UART4", + "description": "UART4 global interrupt", + "value": "52" + } + ], + "registers": [ + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00C00000", + "fields": [ + { + "name": "LBD", + "description": "LIN break detection flag", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXE", + "description": "Transmit data register empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TC", + "description": "Transmission complete", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXNE", + "description": "Read data register not empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IDLE", + "description": "IDLE line detected", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ORE", + "description": "Overrun error", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NF", + "description": "Noise detected flag", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "FE", + "description": "Framing error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PE", + "description": "Parity error", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DR", + "description": "Data value", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "BRR", + "displayName": "BRR", + "description": "Baud rate register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DIV_Mantissa", + "description": "Mantissa of USARTDIV", + "bitOffset": "4", + "bitWidth": "12" + }, + { + "name": "DIV_Fraction", + "description": "Fraction of USARTDIV", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OVER8", + "description": "Oversampling mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "UE", + "description": "USART enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "M", + "description": "Word length", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "WAKE", + "description": "Wakeup method", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PCE", + "description": "Parity control enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PS", + "description": "Parity selection", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PEIE", + "description": "PE interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TXEIE", + "description": "TXE interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transmission complete interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RXNEIE", + "description": "RXNE interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "IDLEIE", + "description": "IDLE interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "Transmitter enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RE", + "description": "Receiver enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RWU", + "description": "Receiver wakeup", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SBK", + "description": "Send break", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "LINEN", + "description": "LIN mode enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "STOP", + "description": "STOP bits", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "LBDIE", + "description": "LIN break detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "LBDL", + "description": "Lin break detection length", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "ADD", + "description": "Address of the USART node", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "CR3", + "displayName": "CR3", + "description": "Control register 3", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ONEBIT", + "description": "One sample bit method enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "DMAT", + "description": "DMA enable transmitter", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "DMAR", + "description": "DMA enable receiver", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "HDSEL", + "description": "Half-duplex selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "IRLP", + "description": "IrDA low-power", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "IREN", + "description": "IrDA mode enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "EIE", + "description": "Error interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "UART5", + "derivedFrom": "UART4", + "baseAddress": "0x40005000", + "interrupts": [ + { + "name": "UART5", + "description": "UART5 global interrupt", + "value": "53" + } + ] + }, + { + "name": "C_ADC", + "description": "Common ADC registers", + "groupName": "ADC", + "baseAddress": "0x40012300", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "CSR", + "displayName": "CSR", + "description": "ADC Common status register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OVR3", + "description": "Overrun flag of ADC3", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "STRT3", + "description": "Regular channel Start flag of ADC 3", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "JSTRT3", + "description": "Injected channel Start flag of ADC 3", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "JEOC3", + "description": "Injected channel end of conversion of ADC 3", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "EOC3", + "description": "End of conversion of ADC 3", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "AWD3", + "description": "Analog watchdog flag of ADC 3", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "OVR2", + "description": "Overrun flag of ADC 2", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "STRT2", + "description": "Regular channel Start flag of ADC 2", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "JSTRT2", + "description": "Injected channel Start flag of ADC 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "JEOC2", + "description": "Injected channel end of conversion of ADC 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EOC2", + "description": "End of conversion of ADC 2", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "AWD2", + "description": "Analog watchdog flag of ADC 2", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "OVR1", + "description": "Overrun flag of ADC 1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "STRT1", + "description": "Regular channel Start flag of ADC 1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "JSTRT1", + "description": "Injected channel Start flag of ADC 1", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "JEOC1", + "description": "Injected channel end of conversion of ADC 1", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "EOC1", + "description": "End of conversion of ADC 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AWD1", + "description": "Analog watchdog flag of ADC 1", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCR", + "displayName": "CCR", + "description": "ADC common control register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSVREFE", + "description": "Temperature sensor and VREFINT enable", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "VBATE", + "description": "VBAT enable", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "ADCPRE", + "description": "ADC prescaler", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "DMA", + "description": "Direct memory access mode for multi ADC mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "DDS", + "description": "DMA disable selection for multi-ADC mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "DELAY", + "description": "Delay between 2 sampling phases", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MULT", + "description": "Multi ADC mode selection", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "CDR", + "displayName": "CDR", + "description": "ADC common regular data register for dual and triple modes", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA2", + "description": "2nd data item of a pair of regular conversions", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "DATA1", + "description": "1st data item of a pair of regular conversions", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM1", + "description": "Advanced-timers", + "groupName": "TIM", + "baseAddress": "0x40010000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + }, + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + }, + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + }, + { + "name": "TIM1_CC", + "description": "TIM1 Capture Compare interrupt", + "value": "27" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "OIS4", + "description": "Output Idle state 4", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "OIS3N", + "description": "Output Idle state 3", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "OIS3", + "description": "Output Idle state 3", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OIS2N", + "description": "Output Idle state 2", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OIS2", + "description": "Output Idle state 2", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "OIS1N", + "description": "Output Idle state 1", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "OIS1", + "description": "Output Idle state 1", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CCUS", + "description": "Capture/compare control update selection", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CCPC", + "description": "Capture/compare preloaded control", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "COMDE", + "description": "COM DMA request enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "BIE", + "description": "Break interrupt enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "COMIE", + "description": "COM interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BIF", + "description": "Break interrupt flag", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMIF", + "description": "COM interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "BG", + "description": "Break generation", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "COMG", + "description": "Capture/Compare control update generation", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "Output Compare 2 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "Output Compare 1 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC4CE", + "description": "Output compare 4 clear enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "Output compare 4 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "Output compare 4 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "Output compare 4 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "Output compare 3 clear enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "Output compare 3 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "Output compare 3 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "Output compare 3 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "Capture/Compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3NE", + "description": "Capture/Compare 3 complementary output enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2NE", + "description": "Capture/Compare 2 complementary output enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1NE", + "description": "Capture/Compare 1 complementary output enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4", + "description": "Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "RCR", + "displayName": "RCR", + "description": "Repetition counter register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "REP", + "description": "Repetition counter value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BDTR", + "displayName": "BDTR", + "description": "Break and dead-time register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MOE", + "description": "Main output enable", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "AOE", + "description": "Automatic output enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "BKP", + "description": "Break polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "BKE", + "description": "Break enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "OSSR", + "description": "Off-state selection for Run mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OSSI", + "description": "Off-state selection for Idle mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock configuration", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "DTG", + "description": "Dead-time generator setup", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "TIM8", + "derivedFrom": "TIM1", + "baseAddress": "0x40010400", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + }, + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + }, + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + }, + { + "name": "TIM8_CC", + "description": "TIM8 Capture Compare interrupt", + "value": "46" + } + ] + }, + { + "name": "TIM2", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM2", + "description": "TIM2 global interrupt", + "value": "28" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ITR1_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "10", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM3", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM3", + "description": "TIM3 global interrupt", + "value": "29" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM4", + "derivedFrom": "TIM3", + "baseAddress": "0x40000800", + "interrupts": [ + { + "name": "TIM4", + "description": "TIM4 global interrupt", + "value": "30" + } + ] + }, + { + "name": "TIM5", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40000C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM5", + "description": "TIM5 global interrupt", + "value": "50" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CMS", + "description": "Center-aligned mode selection", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "DIR", + "description": "Direction", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TI1S", + "description": "TI1 selection", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "CCDS", + "description": "Capture/compare DMA selection", + "bitOffset": "3", + "bitWidth": "1" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ETP", + "description": "External trigger polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "ECE", + "description": "External clock enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "ETPS", + "description": "External trigger prescaler", + "bitOffset": "12", + "bitWidth": "2" + }, + { + "name": "ETF", + "description": "External trigger filter", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TDE", + "description": "Trigger DMA request enable", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CC4DE", + "description": "Capture/Compare 4 DMA request enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3DE", + "description": "Capture/Compare 3 DMA request enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2DE", + "description": "Capture/Compare 2 DMA request enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1DE", + "description": "Capture/Compare 1 DMA request enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IE", + "description": "Capture/Compare 4 interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IE", + "description": "Capture/Compare 3 interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4OF", + "description": "Capture/Compare 4 overcapture flag", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3OF", + "description": "Capture/Compare 3 overcapture flag", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4IF", + "description": "Capture/Compare 4 interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3IF", + "description": "Capture/Compare 3 interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC4G", + "description": "Capture/compare 4 generation", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC3G", + "description": "Capture/compare 3 generation", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2CE", + "description": "OC2CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC2M", + "description": "OC2M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "OC2PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "OC2FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "CC2S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1CE", + "description": "OC1CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC1M", + "description": "OC1M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "OC1PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "OC1FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "CC1S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Output", + "displayName": "CCMR2_Output", + "description": "Capture/compare mode register 2 (output mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "O24CE", + "description": "O24CE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "OC4M", + "description": "OC4M", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC4PE", + "description": "OC4PE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC4FE", + "description": "OC4FE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC4S", + "description": "CC4S", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC3CE", + "description": "OC3CE", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OC3M", + "description": "OC3M", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC3PE", + "description": "OC3PE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC3FE", + "description": "OC3FE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC3S", + "description": "CC3S", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR2_Input", + "displayName": "CCMR2_Input", + "description": "Capture/compare mode register 2 (input mode)", + "headerStructName": "CCMR2_Output", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC4F", + "description": "Input capture 4 filter", + "bitOffset": "12", + "bitWidth": "4" + }, + { + "name": "IC4PSC", + "description": "Input capture 4 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC4S", + "description": "Capture/Compare 4 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC3F", + "description": "Input capture 3 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "IC3PSC", + "description": "Input capture 3 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC3S", + "description": "Capture/compare 3 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC4NP", + "description": "Capture/Compare 4 output Polarity", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "CC4P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CC4E", + "description": "Capture/Compare 4 output enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CC3NP", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "CC3P", + "description": "Capture/Compare 3 output Polarity", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC3E", + "description": "Capture/Compare 3 output enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT_H", + "description": "High counter value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CNT_L", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR_H", + "description": "High Auto-reload value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "ARR_L", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1_H", + "description": "High Capture/Compare 1 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR1_L", + "description": "Low Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2_H", + "description": "High Capture/Compare 2 value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR2_L", + "description": "Low Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR3", + "displayName": "CCR3", + "description": "Capture/compare register 3", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR3_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR3_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR4", + "displayName": "CCR4", + "description": "Capture/compare register 4", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR4_H", + "description": "High Capture/Compare value", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CCR4_L", + "description": "Low Capture/Compare value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DCR", + "displayName": "DCR", + "description": "DMA control register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DBL", + "description": "DMA burst length", + "bitOffset": "8", + "bitWidth": "5" + }, + { + "name": "DBA", + "description": "DMA base address", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "DMAR", + "displayName": "DMAR", + "description": "DMA address for full transfer", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "DMAB", + "description": "DMA register for burst accesses", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "TIM5 option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "IT4_RMP", + "description": "Timer Input 4 remap", + "bitOffset": "6", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM9", + "description": "General purpose timers", + "groupName": "TIM", + "baseAddress": "0x40014000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_BRK_TIM9", + "description": "TIM1 Break interrupt and TIM9 global interrupt", + "value": "24" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "SMCR", + "displayName": "SMCR", + "description": "Slave mode control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MSM", + "description": "Master/Slave mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TS", + "description": "Trigger selection", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "SMS", + "description": "Slave mode selection", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "TIE", + "description": "Trigger interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IE", + "description": "Capture/Compare 2 interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2OF", + "description": "Capture/compare 2 overcapture flag", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TIF", + "description": "Trigger interrupt flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2IF", + "description": "Capture/Compare 2 interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "TG", + "description": "Trigger generation", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CC2G", + "description": "Capture/compare 2 generation", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC2M", + "description": "Output Compare 2 mode", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "OC2PE", + "description": "Output Compare 2 preload enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "OC2FE", + "description": "Output Compare 2 fast enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC2F", + "description": "Input capture 2 filter", + "bitOffset": "12", + "bitWidth": "3" + }, + { + "name": "IC2PCS", + "description": "Input capture 2 prescaler", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CC2S", + "description": "Capture/Compare 2 selection", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC2NP", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "CC2P", + "description": "Capture/Compare 2 output Polarity", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CC2E", + "description": "Capture/Compare 2 output enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR2", + "displayName": "CCR2", + "description": "Capture/compare register 2", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR2", + "description": "Capture/Compare 2 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM12", + "derivedFrom": "TIM9", + "baseAddress": "0x40001800", + "interrupts": [ + { + "name": "TIM8_BRK_TIM12", + "description": "TIM8 Break interrupt and TIM12 global interrupt", + "value": "43" + } + ] + }, + { + "name": "TIM10", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_UP_TIM10", + "description": "TIM1 Update interrupt and TIM10 global interrupt", + "value": "25" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM13", + "derivedFrom": "TIM10", + "baseAddress": "0x40001C00", + "interrupts": [ + { + "name": "TIM8_UP_TIM13", + "description": "TIM8 Update interrupt and TIM13 global interrupt", + "value": "44" + } + ] + }, + { + "name": "TIM14", + "derivedFrom": "TIM10", + "baseAddress": "0x40002000", + "interrupts": [ + { + "name": "TIM8_TRG_COM_TIM14", + "description": "TIM8 Trigger and Commutation interrupts and TIM14 global interrupt", + "value": "45" + } + ] + }, + { + "name": "TIM11", + "description": "General-purpose-timers", + "groupName": "TIM", + "baseAddress": "0x40014800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM1_TRG_COM_TIM11", + "description": "TIM1 Trigger and Commutation interrupts and TIM11 global interrupt", + "value": "26" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CKD", + "description": "Clock division", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1IE", + "description": "Capture/Compare 1 interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1OF", + "description": "Capture/Compare 1 overcapture flag", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "CC1IF", + "description": "Capture/compare 1 interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1G", + "description": "Capture/compare 1 generation", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CCMR1_Output", + "displayName": "CCMR1_Output", + "description": "Capture/compare mode register 1 (output mode)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OC1M", + "description": "Output Compare 1 mode", + "bitOffset": "4", + "bitWidth": "3" + }, + { + "name": "OC1PE", + "description": "Output Compare 1 preload enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OC1FE", + "description": "Output Compare 1 fast enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCMR1_Input", + "displayName": "CCMR1_Input", + "description": "Capture/compare mode register 1 (input mode)", + "headerStructName": "CCMR1_Output", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IC1F", + "description": "Input capture 1 filter", + "bitOffset": "4", + "bitWidth": "4" + }, + { + "name": "ICPCS", + "description": "Input capture 1 prescaler", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "CC1S", + "description": "Capture/Compare 1 selection", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "CCER", + "displayName": "CCER", + "description": "Capture/compare enable register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "CC1NP", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CC1P", + "description": "Capture/Compare 1 output Polarity", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CC1E", + "description": "Capture/Compare 1 output enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CCR1", + "displayName": "CCR1", + "description": "Capture/compare register 1", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCR1", + "description": "Capture/Compare 1 value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OR", + "displayName": "OR", + "description": "Option register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RMP", + "description": "Input 1 remapping capability", + "bitOffset": "0", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "TIM6", + "description": "Basic timers", + "groupName": "TIM", + "baseAddress": "0x40001000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TIM6_DAC", + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt", + "value": "54" + } + ], + "registers": [ + { + "name": "CR1", + "displayName": "CR1", + "description": "Control register 1", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "ARPE", + "description": "Auto-reload preload enable", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "OPM", + "description": "One-pulse mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "URS", + "description": "Update request source", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UDIS", + "description": "Update disable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CEN", + "description": "Counter enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CR2", + "displayName": "CR2", + "description": "Control register 2", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "MMS", + "description": "Master mode selection", + "bitOffset": "4", + "bitWidth": "3" + } + ] + }, + { + "name": "DIER", + "displayName": "DIER", + "description": "DMA/Interrupt enable register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UDE", + "description": "Update DMA request enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "UIE", + "description": "Update interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "UIF", + "description": "Update interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "EGR", + "displayName": "EGR", + "description": "Event generation register", + "addressOffset": "0x14", + "size": "0x20", + "access": "write-only", + "resetValue": "0x0000", + "fields": [ + { + "name": "UG", + "description": "Update generation", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "CNT", + "displayName": "CNT", + "description": "Counter", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CNT", + "description": "Low counter value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "PSC", + "displayName": "PSC", + "description": "Prescaler", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000", + "fields": [ + { + "name": "PSC", + "description": "Prescaler value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "ARR", + "displayName": "ARR", + "description": "Auto-reload register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ARR", + "description": "Low Auto-reload value", + "bitOffset": "0", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "TIM7", + "derivedFrom": "TIM6", + "baseAddress": "0x40001400", + "interrupts": [ + { + "name": "TIM7", + "description": "TIM7 global interrupt", + "value": "55" + } + ] + }, + { + "name": "Ethernet_MAC", + "description": "Ethernet: media access control (MAC)", + "groupName": "Ethernet", + "baseAddress": "0x40028000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "ETH", + "description": "Ethernet global interrupt", + "value": "61" + }, + { + "name": "ETH_WKUP", + "description": "Ethernet Wakeup through EXTI line interrupt", + "value": "62" + } + ], + "registers": [ + { + "name": "MACCR", + "displayName": "MACCR", + "description": "Ethernet MAC configuration register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0008000", + "fields": [ + { + "name": "RE", + "description": "RE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TE", + "description": "TE", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "DC", + "description": "DC", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BL", + "description": "BL", + "bitOffset": "5", + "bitWidth": "2" + }, + { + "name": "APCS", + "description": "APCS", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RD", + "description": "RD", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "IPCO", + "description": "IPCO", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "DM", + "description": "DM", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "LM", + "description": "LM", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "ROD", + "description": "ROD", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FES", + "description": "FES", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "CSD", + "description": "CSD", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "IFG", + "description": "IFG", + "bitOffset": "17", + "bitWidth": "3" + }, + { + "name": "JD", + "description": "JD", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "WD", + "description": "WD", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "CSTF", + "description": "CSTF", + "bitOffset": "25", + "bitWidth": "1" + } + ] + }, + { + "name": "MACFFR", + "displayName": "MACFFR", + "description": "Ethernet MAC frame filter register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PM", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "HM", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAIF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "RAM", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "BFD", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PCF", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SAIF", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SAF", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HPF", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "RA", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACHTHR", + "displayName": "MACHTHR", + "description": "Ethernet MAC hash table high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACHTLR", + "displayName": "MACHTLR", + "description": "Ethernet MAC hash table low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACMIIAR", + "displayName": "MACMIIAR", + "description": "Ethernet MAC MII address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MW", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "3" + }, + { + "name": "MR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "5" + }, + { + "name": "PA", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "5" + } + ] + }, + { + "name": "MACMIIDR", + "displayName": "MACMIIDR", + "description": "Ethernet MAC MII data register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "MACFCR", + "displayName": "MACFCR", + "description": "Ethernet MAC flow control register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FCB", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TFCE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "RFCE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "UPFD", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PLT", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "2" + }, + { + "name": "ZQPD", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "MACVLANTR", + "displayName": "MACVLANTR", + "description": "Ethernet MAC VLAN tag register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VLANTI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "VLANTC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MACPMTCSR", + "displayName": "MACPMTCSR", + "description": "Ethernet MAC PMT control and status register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MPE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "WFE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MPR", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "WFR", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "GU", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "WFFRPR", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACDBGR", + "displayName": "MACDBGR", + "description": "Ethernet MAC debug register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "CR", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "CSR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "ROR", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "MCF", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "MCP", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "MCFHP", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MACSR", + "displayName": "MACSR", + "description": "Ethernet MAC interrupt status register", + "addressOffset": "0x38", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCRS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMCTS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "MACIMR", + "displayName": "MACIMR", + "description": "Ethernet MAC interrupt mask register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PMTIM", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSTIM", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA0HR", + "displayName": "MACA0HR", + "description": "Ethernet MAC address 0 high register", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x0010FFFF", + "fields": [ + { + "name": "MACA0H", + "description": "MAC address0 high", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "MO", + "description": "Always 1", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "MACA0LR", + "displayName": "MACA0LR", + "description": "Ethernet MAC address 0 low register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA0L", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA1HR", + "displayName": "MACA1HR", + "description": "Ethernet MAC address 1 high register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA1H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA1LR", + "displayName": "MACA1LR", + "description": "Ethernet MAC address1 low register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA1LR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MACA2HR", + "displayName": "MACA2HR", + "description": "Ethernet MAC address 2 high register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MAC2AH", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA2LR", + "displayName": "MACA2LR", + "description": "Ethernet MAC address 2 low register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MACA2L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + } + ] + }, + { + "name": "MACA3HR", + "displayName": "MACA3HR", + "description": "Ethernet MAC address 3 high register", + "addressOffset": "0x58", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000FFFF", + "fields": [ + { + "name": "MACA3H", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "MBC", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "6" + }, + { + "name": "SA", + "description": "No description available", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "AE", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "MACA3LR", + "displayName": "MACA3LR", + "description": "Ethernet MAC address 3 low register", + "addressOffset": "0x5C", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "MBCA3L", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_MMC", + "description": "Ethernet: MAC management counters", + "groupName": "Ethernet", + "baseAddress": "0x40028100", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "MMCCR", + "displayName": "MMCCR", + "description": "Ethernet MMC control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CSR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "ROR", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MCF", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MCP", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MCFHP", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIR", + "displayName": "MMCRIR", + "description": "Ethernet MMC receive interrupt register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCES", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAES", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIR", + "displayName": "MMCTIR", + "description": "Ethernet MMC transmit interrupt register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFS", + "description": "No description available", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCRIMR", + "displayName": "MMCRIMR", + "description": "Ethernet MMC receive interrupt mask register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCEM", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RFAEM", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RGUFM", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTIMR", + "displayName": "MMCTIMR", + "description": "Ethernet MMC transmit interrupt mask register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCM", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TGFMSCM", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TGFM", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "MMCTGFSCCR", + "displayName": "MMCTGFSCCR", + "description": "Ethernet MMC transmitted good frames after a single collision counter", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFMSCCR", + "displayName": "MMCTGFMSCCR", + "description": "Ethernet MMC transmitted good frames after more than a single collision", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFMSCC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCTGFCR", + "displayName": "MMCTGFCR", + "description": "Ethernet MMC transmitted good frames counter register", + "addressOffset": "0x68", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TGFC", + "description": "HTL", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFCECR", + "displayName": "MMCRFCECR", + "description": "Ethernet MMC received frames with CRC error counter register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFCFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRFAECR", + "displayName": "MMCRFAECR", + "description": "Ethernet MMC received frames with alignment error counter register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFAEC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "MMCRGUFCR", + "displayName": "MMCRGUFCR", + "description": "MMC received good unicast frames counter register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RGUFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "Ethernet_PTP", + "description": "Ethernet: Precision time protocol", + "groupName": "Ethernet", + "baseAddress": "0x40028700", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "PTPTSCR", + "displayName": "PTPTSCR", + "description": "Ethernet PTP time stamp control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002000", + "fields": [ + { + "name": "TSE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSFCU", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TSPTPPSV2E", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TSSPTPOEFE", + "description": "No description available", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TSSIPV6FE", + "description": "No description available", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TSSIPV4FE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TSSEME", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TSSMRME", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TSCNT", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "TSPFFMAE", + "description": "No description available", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TSSTI", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TSSTU", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TSITE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TTSARU", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TSSARFE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TSSSR", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPSSIR", + "displayName": "PTPSSIR", + "description": "Ethernet PTP subsecond increment register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSSI", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "PTPTSHR", + "displayName": "PTPTSHR", + "description": "Ethernet PTP time stamp high register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLR", + "displayName": "PTPTSLR", + "description": "Ethernet PTP time stamp low register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "STPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSHUR", + "displayName": "PTPTSHUR", + "description": "Ethernet PTP time stamp high update register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSLUR", + "displayName": "PTPTSLUR", + "description": "Ethernet PTP time stamp low update register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSUSS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "31" + }, + { + "name": "TSUPNS", + "description": "No description available", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPTSAR", + "displayName": "PTPTSAR", + "description": "Ethernet PTP time stamp addend register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSA", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTHR", + "displayName": "PTPTTHR", + "description": "Ethernet PTP target time high register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSH", + "description": "0", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTTLR", + "displayName": "PTPTTLR", + "description": "Ethernet PTP target time low register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TTSL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "PTPTSSR", + "displayName": "PTPTSSR", + "description": "Ethernet PTP time stamp status register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "PTPPPSCR", + "displayName": "PTPPPSCR", + "description": "Ethernet PTP PPS control register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TSSO", + "description": "TSSO", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TSTTR", + "description": "TSTTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "Ethernet_DMA", + "description": "Ethernet: DMA controller operation", + "groupName": "Ethernet", + "baseAddress": "0x40029000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DMABMR", + "displayName": "DMABMR", + "description": "Ethernet DMA bus mode register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00002101", + "fields": [ + { + "name": "SR", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "DA", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "DSL", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "5" + }, + { + "name": "EDFE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PBL", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "RTPR", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "FB", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "6" + }, + { + "name": "USP", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FPM", + "description": "No description available", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "AAB", + "description": "No description available", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "MB", + "description": "No description available", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMATPDR", + "displayName": "DMATPDR", + "description": "Ethernet DMA transmit poll demand register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TPD", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARPDR", + "displayName": "DMARPDR", + "description": "EHERNET DMA receive poll demand register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RPD", + "description": "RPD", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMARDLAR", + "displayName": "DMARDLAR", + "description": "Ethernet DMA receive descriptor list address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SRL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMATDLAR", + "displayName": "DMATDLAR", + "description": "Ethernet DMA transmit descriptor list address register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STL", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMASR", + "displayName": "DMASR", + "description": "Ethernet DMA status register", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TS", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TPSS", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TBUS", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TJTS", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ROS", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TUS", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RS", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RBUS", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPSS", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PWTS", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ETS", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FBES", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERS", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "AIS", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NIS", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RPS", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "TPS", + "description": "No description available", + "bitOffset": "20", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "EBS", + "description": "No description available", + "bitOffset": "23", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "MMCS", + "description": "No description available", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PMTS", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TSTS", + "description": "No description available", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DMAOMR", + "displayName": "DMAOMR", + "description": "Ethernet DMA operation mode register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SR", + "description": "SR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OSF", + "description": "OSF", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTC", + "description": "RTC", + "bitOffset": "3", + "bitWidth": "2" + }, + { + "name": "FUGF", + "description": "FUGF", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FEF", + "description": "FEF", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ST", + "description": "ST", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TTC", + "description": "TTC", + "bitOffset": "14", + "bitWidth": "3" + }, + { + "name": "FTF", + "description": "FTF", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TSF", + "description": "TSF", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "DFRF", + "description": "DFRF", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "RSF", + "description": "RSF", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "DTCEFD", + "description": "DTCEFD", + "bitOffset": "26", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAIER", + "displayName": "DMAIER", + "description": "Ethernet DMA interrupt enable register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIE", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TPSIE", + "description": "No description available", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TBUIE", + "description": "No description available", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TJTIE", + "description": "No description available", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ROIE", + "description": "No description available", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TUIE", + "description": "No description available", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "RIE", + "description": "No description available", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "RBUIE", + "description": "No description available", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RPSIE", + "description": "No description available", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "RWTIE", + "description": "No description available", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "ETIE", + "description": "No description available", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBEIE", + "description": "No description available", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "ERIE", + "description": "No description available", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "AISE", + "description": "No description available", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "NISE", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + } + ] + }, + { + "name": "DMAMFBOCR", + "displayName": "DMAMFBOCR", + "description": "Ethernet DMA missed frame and buffer overflow counter register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MFC", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OMFC", + "description": "No description available", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MFA", + "description": "No description available", + "bitOffset": "17", + "bitWidth": "11" + }, + { + "name": "OFOC", + "description": "No description available", + "bitOffset": "28", + "bitWidth": "1" + } + ] + }, + { + "name": "DMARSWTR", + "displayName": "DMARSWTR", + "description": "Ethernet DMA receive status watchdog timer register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RSWTC", + "description": "RSWTC", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "DMACHTDR", + "displayName": "DMACHTDR", + "description": "Ethernet DMA current host transmit descriptor register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTDAP", + "description": "HTDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRDR", + "displayName": "DMACHRDR", + "description": "Ethernet DMA current host receive descriptor register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRDAP", + "description": "HRDAP", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHTBAR", + "displayName": "DMACHTBAR", + "description": "Ethernet DMA current host transmit buffer address register", + "addressOffset": "0x50", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HTBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "DMACHRBAR", + "displayName": "DMACHRBAR", + "description": "Ethernet DMA current host receive buffer address register", + "addressOffset": "0x54", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HRBAP", + "description": "No description available", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "CRC", + "description": "Cryptographic processor", + "groupName": "CRC", + "baseAddress": "0x40023000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "DR", + "displayName": "DR", + "description": "Data register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0xFFFFFFFF", + "fields": [ + { + "name": "DR", + "description": "Data Register", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IDR", + "displayName": "IDR", + "description": "Independent Data register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IDR", + "description": "Independent Data register", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CR", + "description": "Control regidter", + "bitOffset": "0", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_FS_GLOBAL", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_FS_WKUP", + "description": "USB On-The-Go FS Wakeup through EXTI line interrupt", + "value": "42" + }, + { + "name": "OTG_FS", + "description": "USB On The Go FS global interrupt", + "value": "67" + } + ], + "registers": [ + { + "name": "FS_GOTGCTL", + "displayName": "FS_GOTGCTL", + "description": "OTG_FS control and status register (OTG_FS_GOTGCTL)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GOTGINT", + "displayName": "FS_GOTGINT", + "description": "OTG_FS interrupt register (OTG_FS_GOTGINT)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GAHBCFG", + "displayName": "FS_GAHBCFG", + "description": "OTG_FS AHB configuration register (OTG_FS_GAHBCFG)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_GUSBCFG", + "displayName": "FS_GUSBCFG", + "description": "OTG_FS USB configuration register (OTG_FS_GUSBCFG)", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "Full Speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Force host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Force device mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRSTCTL", + "displayName": "FS_GRSTCTL", + "description": "OTG_FS reset register (OTG_FS_GRSTCTL)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "FS_GINTSTS", + "displayName": "FS_GINTSTS", + "description": "OTG_FS core interrupt register (OTG_FS_GINTSTS)", + "addressOffset": "0x14", + "size": "0x20", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO non-empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Non-periodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN non-periodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUPINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GINTMSK", + "displayName": "FS_GINTMSK", + "description": "OTG_FS interrupt mask register (OTG_FS_GINTMSK)", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO non-empty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Non-periodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global non-periodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IPXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_GRXSTSR_Device", + "displayName": "FS_GRXSTSR_Device", + "description": "OTG_FS Receive status debug read(Device mode)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXSTSR_Host", + "displayName": "FS_GRXSTSR_Host", + "description": "OTG_FS Receive status debug read(Host mode)", + "headerStructName": "FS_GRXSTSR_Device", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "FS_GRXFSIZ", + "displayName": "FS_GRXFSIZ", + "description": "OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Device", + "displayName": "FS_GNPTXFSIZ_Device", + "description": "OTG_FS non-periodic transmit FIFO size register (Device mode)", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXFSIZ_Host", + "displayName": "FS_GNPTXFSIZ_Host", + "description": "OTG_FS non-periodic transmit FIFO size register (Host mode)", + "headerStructName": "FS_GNPTXFSIZ_Device", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Non-periodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Non-periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_GNPTXSTS", + "displayName": "FS_GNPTXSTS", + "description": "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Non-periodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Non-periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the non-periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "FS_GCCFG", + "displayName": "FS_GCCFG", + "description": "OTG_FS general core configuration register (OTG_FS_GCCFG)", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_CID", + "displayName": "FS_CID", + "description": "Core ID register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00001000", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FS_HPTXFSIZ", + "displayName": "FS_HPTXFSIZ", + "description": "OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFSIZ", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF1", + "displayName": "FS_DIEPTXF1", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO2 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF2", + "displayName": "FS_DIEPTXF2", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO3 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPTXF3", + "displayName": "FS_DIEPTXF3", + "description": "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFO4 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + } + ] + }, + { + "name": "OTG_FS_HOST", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_HCFG", + "displayName": "FS_HCFG", + "description": "OTG_FS host configuration register (OTG_FS_HCFG)", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "HFIR", + "displayName": "HFIR", + "description": "OTG_FS Host frame interval register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HFNUM", + "displayName": "FS_HFNUM", + "description": "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPTXSTS", + "displayName": "FS_HPTXSTS", + "description": "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "HAINT", + "displayName": "HAINT", + "description": "OTG_FS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "HAINTMSK", + "displayName": "HAINTMSK", + "description": "OTG_FS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_HPRT", + "displayName": "FS_HPRT", + "description": "OTG_FS host port control and status register (OTG_FS_HPRT)", + "addressOffset": "0x40", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "FS_HCCHAR0", + "displayName": "FS_HCCHAR0", + "description": "OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR1", + "displayName": "FS_HCCHAR1", + "description": "OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR2", + "displayName": "FS_HCCHAR2", + "description": "OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)", + "addressOffset": "0x140", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR3", + "displayName": "FS_HCCHAR3", + "description": "OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)", + "addressOffset": "0x160", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR4", + "displayName": "FS_HCCHAR4", + "description": "OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR5", + "displayName": "FS_HCCHAR5", + "description": "OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR6", + "displayName": "FS_HCCHAR6", + "description": "OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCCHAR7", + "displayName": "FS_HCCHAR7", + "description": "OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)", + "addressOffset": "0x1E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MCNT", + "description": "Multicount", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT0", + "displayName": "FS_HCINT0", + "description": "OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT1", + "displayName": "FS_HCINT1", + "description": "OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)", + "addressOffset": "0x128", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT2", + "displayName": "FS_HCINT2", + "description": "OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)", + "addressOffset": "0x148", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT3", + "displayName": "FS_HCINT3", + "description": "OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)", + "addressOffset": "0x168", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT4", + "displayName": "FS_HCINT4", + "description": "OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT5", + "displayName": "FS_HCINT5", + "description": "OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT6", + "displayName": "FS_HCINT6", + "description": "OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINT7", + "displayName": "FS_HCINT7", + "description": "OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)", + "addressOffset": "0x1E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK0", + "displayName": "FS_HCINTMSK0", + "description": "OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK1", + "displayName": "FS_HCINTMSK1", + "description": "OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK2", + "displayName": "FS_HCINTMSK2", + "description": "OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)", + "addressOffset": "0x14C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK3", + "displayName": "FS_HCINTMSK3", + "description": "OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)", + "addressOffset": "0x16C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK4", + "displayName": "FS_HCINTMSK4", + "description": "OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK5", + "displayName": "FS_HCINTMSK5", + "description": "OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK6", + "displayName": "FS_HCINTMSK6", + "description": "OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCINTMSK7", + "displayName": "FS_HCINTMSK7", + "description": "OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)", + "addressOffset": "0x1EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_HCTSIZ0", + "displayName": "FS_HCTSIZ0", + "description": "OTG_FS host channel-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ1", + "displayName": "FS_HCTSIZ1", + "description": "OTG_FS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ2", + "displayName": "FS_HCTSIZ2", + "description": "OTG_FS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ3", + "displayName": "FS_HCTSIZ3", + "description": "OTG_FS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ4", + "displayName": "FS_HCTSIZ4", + "description": "OTG_FS host channel-x transfer size register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ5", + "displayName": "FS_HCTSIZ5", + "description": "OTG_FS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ6", + "displayName": "FS_HCTSIZ6", + "description": "OTG_FS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_HCTSIZ7", + "displayName": "FS_HCTSIZ7", + "description": "OTG_FS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_FS_DEVICE", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_DCFG", + "displayName": "FS_DCFG", + "description": "OTG_FS device configuration register (OTG_FS_DCFG)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Non-zero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic frame interval", + "bitOffset": "11", + "bitWidth": "2" + } + ] + }, + { + "name": "FS_DCTL", + "displayName": "FS_DCTL", + "description": "OTG_FS device control register (OTG_FS_DCTL)", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "FS_DSTS", + "displayName": "FS_DSTS", + "description": "OTG_FS device status register (OTG_FS_DSTS)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "FS_DIEPMSK", + "displayName": "FS_DIEPMSK", + "description": "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (Non-isochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DOEPMSK", + "displayName": "FS_DOEPMSK", + "description": "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + } + ] + }, + { + "name": "FS_DAINT", + "displayName": "FS_DAINT", + "description": "OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DAINTMSK", + "displayName": "FS_DAINTMSK", + "description": "OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSDIS", + "displayName": "DVBUSDIS", + "description": "OTG_FS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DVBUSPULSE", + "displayName": "DVBUSPULSE", + "description": "OTG_FS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "DIEPEMPMSK", + "displayName": "DIEPEMPMSK", + "description": "OTG_FS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "FS_DIEPCTL0", + "displayName": "FS_DIEPCTL0", + "description": "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)", + "addressOffset": "0x100", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "STALL", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "DIEPCTL1", + "displayName": "DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL2", + "displayName": "DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPCTL3", + "displayName": "DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "TXFNUM", + "description": "TXFNUM", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL0", + "displayName": "DOEPCTL0", + "description": "Device endpoint-0 control register", + "addressOffset": "0x300", + "size": "0x20", + "resetValue": "0x00008000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "DOEPCTL1", + "displayName": "DOEPCTL1", + "description": "Device endpoint-1 control register", + "addressOffset": "0x320", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL2", + "displayName": "DOEPCTL2", + "description": "Device endpoint-2 control register", + "addressOffset": "0x340", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DOEPCTL3", + "displayName": "DOEPCTL3", + "description": "Device endpoint-3 control register", + "addressOffset": "0x360", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EPENA", + "description": "EPENA", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDIS", + "description": "EPDIS", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SODDFRM", + "description": "SODDFRM", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "SNAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CNAK", + "description": "CNAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "Stall", + "description": "Stall", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "SNPM", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPTYP", + "description": "EPTYP", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "NAKSTS", + "description": "NAKSTS", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EONUM_DPID", + "description": "EONUM/DPID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USBAEP", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "MPSIZ", + "description": "MPSIZ", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT0", + "displayName": "DIEPINT0", + "description": "Device endpoint-x interrupt register", + "addressOffset": "0x108", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT1", + "displayName": "DIEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT2", + "displayName": "DIEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DIEPINT3", + "displayName": "DIEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "0x20", + "resetValue": "0x00000080", + "fields": [ + { + "name": "TXFE", + "description": "TXFE", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INEPNE", + "description": "INEPNE", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "ITTXFE", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "TOC", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "DOEPINT0", + "displayName": "DOEPINT0", + "description": "Device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT1", + "displayName": "DOEPINT1", + "description": "Device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT2", + "displayName": "DOEPINT2", + "description": "Device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DOEPINT3", + "displayName": "DOEPINT3", + "description": "Device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "B2BSTUP", + "description": "B2BSTUP", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OTEPDIS", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "STUP", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "EPDISD", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "XFRC", + "description": "XFRC", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "DIEPTSIZ0", + "displayName": "DIEPTSIZ0", + "description": "Device endpoint-0 transfer size register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DOEPTSIZ0", + "displayName": "DOEPTSIZ0", + "description": "Device OUT endpoint-0 transfer size register", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + } + ] + }, + { + "name": "DIEPTSIZ1", + "displayName": "DIEPTSIZ1", + "description": "Device endpoint-1 transfer size register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ2", + "displayName": "DIEPTSIZ2", + "description": "Device endpoint-2 transfer size register", + "addressOffset": "0x150", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DIEPTSIZ3", + "displayName": "DIEPTSIZ3", + "description": "Device endpoint-3 transfer size register", + "addressOffset": "0x170", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DTXFSTS0", + "displayName": "DTXFSTS0", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS1", + "displayName": "DTXFSTS1", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS2", + "displayName": "DTXFSTS2", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DTXFSTS3", + "displayName": "DTXFSTS3", + "description": "OTG_FS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "DOEPTSIZ1", + "displayName": "DOEPTSIZ1", + "description": "Device OUT endpoint-1 transfer size register", + "addressOffset": "0x330", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ2", + "displayName": "DOEPTSIZ2", + "description": "Device OUT endpoint-2 transfer size register", + "addressOffset": "0x350", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + }, + { + "name": "DOEPTSIZ3", + "displayName": "DOEPTSIZ3", + "description": "Device OUT endpoint-3 transfer size register", + "addressOffset": "0x370", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + } + ] + } + ] + }, + { + "name": "OTG_FS_PWRCLK", + "description": "USB on the go full speed", + "groupName": "USB_OTG_FS", + "baseAddress": "0x50000E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "FS_PCGCCTL", + "displayName": "FS_PCGCCTL", + "description": "OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY Suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN1", + "description": "Controller area network", + "groupName": "CAN", + "baseAddress": "0x40006400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "CAN1_TX", + "description": "CAN1 TX interrupts", + "value": "19" + }, + { + "name": "CAN1_RX0", + "description": "CAN1 RX0 interrupts", + "value": "20" + }, + { + "name": "CAN1_RX1", + "description": "CAN1 RX1 interrupts", + "value": "21" + }, + { + "name": "CAN1_SCE", + "description": "CAN1 SCE interrupt", + "value": "22" + } + ], + "registers": [ + { + "name": "MCR", + "displayName": "MCR", + "description": "Master control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00010002", + "fields": [ + { + "name": "DBF", + "description": "DBF", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RESET", + "description": "RESET", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TTCM", + "description": "TTCM", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "ABOM", + "description": "ABOM", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AWUM", + "description": "AWUM", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NART", + "description": "NART", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "RFLM", + "description": "RFLM", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TXFP", + "description": "TXFP", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SLEEP", + "description": "SLEEP", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "INRQ", + "description": "INRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "MSR", + "displayName": "MSR", + "description": "Master status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000C02", + "fields": [ + { + "name": "RX", + "description": "RX", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SAMP", + "description": "SAMP", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "RXM", + "description": "RXM", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXM", + "description": "TXM", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SLAKI", + "description": "SLAKI", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUI", + "description": "WKUI", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ERRI", + "description": "ERRI", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SLAK", + "description": "SLAK", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "INAK", + "description": "INAK", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "TSR", + "displayName": "TSR", + "description": "Transmit status register", + "addressOffset": "0x8", + "size": "0x20", + "resetValue": "0x1C000000", + "fields": [ + { + "name": "LOW2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "LOW0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME2", + "description": "Lowest priority flag for mailbox 2", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME1", + "description": "Lowest priority flag for mailbox 1", + "bitOffset": "27", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TME0", + "description": "Lowest priority flag for mailbox 0", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CODE", + "description": "CODE", + "bitOffset": "24", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "ABRQ2", + "description": "ABRQ2", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR2", + "description": "TERR2", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST2", + "description": "ALST2", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK2", + "description": "TXOK2", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP2", + "description": "RQCP2", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ1", + "description": "ABRQ1", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR1", + "description": "TERR1", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST1", + "description": "ALST1", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK1", + "description": "TXOK1", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP1", + "description": "RQCP1", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ABRQ0", + "description": "ABRQ0", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TERR0", + "description": "TERR0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ALST0", + "description": "ALST0", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXOK0", + "description": "TXOK0", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RQCP0", + "description": "RQCP0", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "RF0R", + "displayName": "RF0R", + "description": "Receive FIFO 0 register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM0", + "description": "RFOM0", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR0", + "description": "FOVR0", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL0", + "description": "FULL0", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP0", + "description": "FMP0", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "RF1R", + "displayName": "RF1R", + "description": "Receive FIFO 1 register", + "addressOffset": "0x10", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RFOM1", + "description": "RFOM1", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FOVR1", + "description": "FOVR1", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FULL1", + "description": "FULL1", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FMP1", + "description": "FMP1", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt enable register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLKIE", + "description": "SLKIE", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "WKUIE", + "description": "WKUIE", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "ERRIE", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LECIE", + "description": "LECIE", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "BOFIE", + "description": "BOFIE", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "EPVIE", + "description": "EPVIE", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "EWGIE", + "description": "EWGIE", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FOVIE1", + "description": "FOVIE1", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFIE1", + "description": "FFIE1", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FMPIE1", + "description": "FMPIE1", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FOVIE0", + "description": "FOVIE0", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFIE0", + "description": "FFIE0", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FMPIE0", + "description": "FMPIE0", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TMEIE", + "description": "TMEIE", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ESR", + "displayName": "ESR", + "description": "Interrupt enable register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "REC", + "description": "REC", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "TEC", + "description": "TEC", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "LEC", + "description": "LEC", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "BOFF", + "description": "BOFF", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPVF", + "description": "EPVF", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWGF", + "description": "EWGF", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "BTR", + "displayName": "BTR", + "description": "Bit timing register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SILM", + "description": "SILM", + "bitOffset": "31", + "bitWidth": "1" + }, + { + "name": "LBKM", + "description": "LBKM", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "SJW", + "description": "SJW", + "bitOffset": "24", + "bitWidth": "2" + }, + { + "name": "TS2", + "description": "TS2", + "bitOffset": "20", + "bitWidth": "3" + }, + { + "name": "TS1", + "description": "TS1", + "bitOffset": "16", + "bitWidth": "4" + }, + { + "name": "BRP", + "description": "BRP", + "bitOffset": "0", + "bitWidth": "10" + } + ] + }, + { + "name": "TI0R", + "displayName": "TI0R", + "description": "TX mailbox identifier register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TDT0R", + "displayName": "TDT0R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TDL0R", + "displayName": "TDL0R", + "description": "Mailbox data low register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH0R", + "displayName": "TDH0R", + "description": "Mailbox data high register", + "addressOffset": "0x18C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TI1R", + "displayName": "TI1R", + "description": "Mailbox identifier register", + "addressOffset": "0x190", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TDT1R", + "displayName": "TDT1R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x194", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TDL1R", + "displayName": "TDL1R", + "description": "Mailbox data low register", + "addressOffset": "0x198", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH1R", + "displayName": "TDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x19C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TI2R", + "displayName": "TI2R", + "description": "Mailbox identifier register", + "addressOffset": "0x1A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXRQ", + "description": "TXRQ", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "TDT2R", + "displayName": "TDT2R", + "description": "Mailbox data length control and time stamp register", + "addressOffset": "0x1A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "TGT", + "description": "TGT", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "TDL2R", + "displayName": "TDL2R", + "description": "Mailbox data low register", + "addressOffset": "0x1A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "TDH2R", + "displayName": "TDH2R", + "description": "Mailbox data high register", + "addressOffset": "0x1AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RI0R", + "displayName": "RI0R", + "description": "Receive FIFO mailbox identifier register", + "addressOffset": "0x1B0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "RDT0R", + "displayName": "RDT0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "RDL0R", + "displayName": "RDL0R", + "description": "Mailbox data high register", + "addressOffset": "0x1B8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH0R", + "displayName": "RDH0R", + "description": "Receive FIFO mailbox data high register", + "addressOffset": "0x1BC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RI1R", + "displayName": "RI1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C0", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "STID", + "description": "STID", + "bitOffset": "21", + "bitWidth": "11" + }, + { + "name": "EXID", + "description": "EXID", + "bitOffset": "3", + "bitWidth": "18" + }, + { + "name": "IDE", + "description": "IDE", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "RTR", + "description": "RTR", + "bitOffset": "1", + "bitWidth": "1" + } + ] + }, + { + "name": "RDT1R", + "displayName": "RDT1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TIME", + "description": "TIME", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "FMI", + "description": "FMI", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DLC", + "description": "DLC", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "RDL1R", + "displayName": "RDL1R", + "description": "Mailbox data high register", + "addressOffset": "0x1C8", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA3", + "description": "DATA3", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA2", + "description": "DATA2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA1", + "description": "DATA1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA0", + "description": "DATA0", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "RDH1R", + "displayName": "RDH1R", + "description": "Mailbox data high register", + "addressOffset": "0x1CC", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA7", + "description": "DATA7", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DATA6", + "description": "DATA6", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DATA5", + "description": "DATA5", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DATA4", + "description": "DATA4", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "FMR", + "displayName": "FMR", + "description": "Filter master register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x2A1C0E01", + "fields": [ + { + "name": "CAN2SB", + "description": "CAN2SB", + "bitOffset": "8", + "bitWidth": "6" + }, + { + "name": "FINIT", + "description": "FINIT", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "FM1R", + "displayName": "FM1R", + "description": "Filter mode register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FBM0", + "description": "Filter mode", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FBM1", + "description": "Filter mode", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FBM2", + "description": "Filter mode", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FBM3", + "description": "Filter mode", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FBM4", + "description": "Filter mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FBM5", + "description": "Filter mode", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FBM6", + "description": "Filter mode", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FBM7", + "description": "Filter mode", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FBM8", + "description": "Filter mode", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FBM9", + "description": "Filter mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FBM10", + "description": "Filter mode", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FBM11", + "description": "Filter mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FBM12", + "description": "Filter mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FBM13", + "description": "Filter mode", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FBM14", + "description": "Filter mode", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FBM15", + "description": "Filter mode", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FBM16", + "description": "Filter mode", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FBM17", + "description": "Filter mode", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FBM18", + "description": "Filter mode", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FBM19", + "description": "Filter mode", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FBM20", + "description": "Filter mode", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FBM21", + "description": "Filter mode", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FBM22", + "description": "Filter mode", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FBM23", + "description": "Filter mode", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FBM24", + "description": "Filter mode", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FBM25", + "description": "Filter mode", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FBM26", + "description": "Filter mode", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FBM27", + "description": "Filter mode", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FS1R", + "displayName": "FS1R", + "description": "Filter scale register", + "addressOffset": "0x20C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FSC0", + "description": "Filter scale configuration", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FSC1", + "description": "Filter scale configuration", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FSC2", + "description": "Filter scale configuration", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FSC3", + "description": "Filter scale configuration", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FSC4", + "description": "Filter scale configuration", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FSC5", + "description": "Filter scale configuration", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FSC6", + "description": "Filter scale configuration", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FSC7", + "description": "Filter scale configuration", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FSC8", + "description": "Filter scale configuration", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FSC9", + "description": "Filter scale configuration", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FSC10", + "description": "Filter scale configuration", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FSC11", + "description": "Filter scale configuration", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FSC12", + "description": "Filter scale configuration", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FSC13", + "description": "Filter scale configuration", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FSC14", + "description": "Filter scale configuration", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FSC15", + "description": "Filter scale configuration", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FSC16", + "description": "Filter scale configuration", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSC17", + "description": "Filter scale configuration", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSC18", + "description": "Filter scale configuration", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSC19", + "description": "Filter scale configuration", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FSC20", + "description": "Filter scale configuration", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FSC21", + "description": "Filter scale configuration", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FSC22", + "description": "Filter scale configuration", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FSC23", + "description": "Filter scale configuration", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FSC24", + "description": "Filter scale configuration", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FSC25", + "description": "Filter scale configuration", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FSC26", + "description": "Filter scale configuration", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FSC27", + "description": "Filter scale configuration", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FFA1R", + "displayName": "FFA1R", + "description": "Filter FIFO assignment register", + "addressOffset": "0x214", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FFA0", + "description": "Filter FIFO assignment for filter 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FFA1", + "description": "Filter FIFO assignment for filter 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FFA2", + "description": "Filter FIFO assignment for filter 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FFA3", + "description": "Filter FIFO assignment for filter 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FFA4", + "description": "Filter FIFO assignment for filter 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFA5", + "description": "Filter FIFO assignment for filter 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FFA6", + "description": "Filter FIFO assignment for filter 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FFA7", + "description": "Filter FIFO assignment for filter 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FFA8", + "description": "Filter FIFO assignment for filter 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FFA9", + "description": "Filter FIFO assignment for filter 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FFA10", + "description": "Filter FIFO assignment for filter 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FFA11", + "description": "Filter FIFO assignment for filter 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FFA12", + "description": "Filter FIFO assignment for filter 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FFA13", + "description": "Filter FIFO assignment for filter 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FFA14", + "description": "Filter FIFO assignment for filter 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FFA15", + "description": "Filter FIFO assignment for filter 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FFA16", + "description": "Filter FIFO assignment for filter 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FFA17", + "description": "Filter FIFO assignment for filter 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FFA18", + "description": "Filter FIFO assignment for filter 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FFA19", + "description": "Filter FIFO assignment for filter 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FFA20", + "description": "Filter FIFO assignment for filter 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FFA21", + "description": "Filter FIFO assignment for filter 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FFA22", + "description": "Filter FIFO assignment for filter 22", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FFA23", + "description": "Filter FIFO assignment for filter 23", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FFA24", + "description": "Filter FIFO assignment for filter 24", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FFA25", + "description": "Filter FIFO assignment for filter 25", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FFA26", + "description": "Filter FIFO assignment for filter 26", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FFA27", + "description": "Filter FIFO assignment for filter 27", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "FA1R", + "displayName": "FA1R", + "description": "Filter activation register", + "addressOffset": "0x21C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FACT0", + "description": "Filter active", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FACT1", + "description": "Filter active", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FACT2", + "description": "Filter active", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FACT3", + "description": "Filter active", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FACT4", + "description": "Filter active", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FACT5", + "description": "Filter active", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FACT6", + "description": "Filter active", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FACT7", + "description": "Filter active", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FACT8", + "description": "Filter active", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FACT9", + "description": "Filter active", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FACT10", + "description": "Filter active", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FACT11", + "description": "Filter active", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FACT12", + "description": "Filter active", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FACT13", + "description": "Filter active", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FACT14", + "description": "Filter active", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FACT15", + "description": "Filter active", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FACT16", + "description": "Filter active", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FACT17", + "description": "Filter active", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FACT18", + "description": "Filter active", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FACT19", + "description": "Filter active", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FACT20", + "description": "Filter active", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FACT21", + "description": "Filter active", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FACT22", + "description": "Filter active", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FACT23", + "description": "Filter active", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FACT24", + "description": "Filter active", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FACT25", + "description": "Filter active", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FACT26", + "description": "Filter active", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FACT27", + "description": "Filter active", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R1", + "displayName": "F0R1", + "description": "Filter bank 0 register 1", + "addressOffset": "0x240", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F0R2", + "displayName": "F0R2", + "description": "Filter bank 0 register 2", + "addressOffset": "0x244", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R1", + "displayName": "F1R1", + "description": "Filter bank 1 register 1", + "addressOffset": "0x248", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F1R2", + "displayName": "F1R2", + "description": "Filter bank 1 register 2", + "addressOffset": "0x24C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R1", + "displayName": "F2R1", + "description": "Filter bank 2 register 1", + "addressOffset": "0x250", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F2R2", + "displayName": "F2R2", + "description": "Filter bank 2 register 2", + "addressOffset": "0x254", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R1", + "displayName": "F3R1", + "description": "Filter bank 3 register 1", + "addressOffset": "0x258", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F3R2", + "displayName": "F3R2", + "description": "Filter bank 3 register 2", + "addressOffset": "0x25C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R1", + "displayName": "F4R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x260", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F4R2", + "displayName": "F4R2", + "description": "Filter bank 4 register 2", + "addressOffset": "0x264", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R1", + "displayName": "F5R1", + "description": "Filter bank 5 register 1", + "addressOffset": "0x268", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F5R2", + "displayName": "F5R2", + "description": "Filter bank 5 register 2", + "addressOffset": "0x26C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R1", + "displayName": "F6R1", + "description": "Filter bank 6 register 1", + "addressOffset": "0x270", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F6R2", + "displayName": "F6R2", + "description": "Filter bank 6 register 2", + "addressOffset": "0x274", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R1", + "displayName": "F7R1", + "description": "Filter bank 7 register 1", + "addressOffset": "0x278", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F7R2", + "displayName": "F7R2", + "description": "Filter bank 7 register 2", + "addressOffset": "0x27C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R1", + "displayName": "F8R1", + "description": "Filter bank 8 register 1", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F8R2", + "displayName": "F8R2", + "description": "Filter bank 8 register 2", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R1", + "displayName": "F9R1", + "description": "Filter bank 9 register 1", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F9R2", + "displayName": "F9R2", + "description": "Filter bank 9 register 2", + "addressOffset": "0x28C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R1", + "displayName": "F10R1", + "description": "Filter bank 10 register 1", + "addressOffset": "0x290", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F10R2", + "displayName": "F10R2", + "description": "Filter bank 10 register 2", + "addressOffset": "0x294", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R1", + "displayName": "F11R1", + "description": "Filter bank 11 register 1", + "addressOffset": "0x298", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F11R2", + "displayName": "F11R2", + "description": "Filter bank 11 register 2", + "addressOffset": "0x29C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R1", + "displayName": "F12R1", + "description": "Filter bank 4 register 1", + "addressOffset": "0x2A0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F12R2", + "displayName": "F12R2", + "description": "Filter bank 12 register 2", + "addressOffset": "0x2A4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R1", + "displayName": "F13R1", + "description": "Filter bank 13 register 1", + "addressOffset": "0x2A8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F13R2", + "displayName": "F13R2", + "description": "Filter bank 13 register 2", + "addressOffset": "0x2AC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R1", + "displayName": "F14R1", + "description": "Filter bank 14 register 1", + "addressOffset": "0x2B0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F14R2", + "displayName": "F14R2", + "description": "Filter bank 14 register 2", + "addressOffset": "0x2B4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R1", + "displayName": "F15R1", + "description": "Filter bank 15 register 1", + "addressOffset": "0x2B8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F15R2", + "displayName": "F15R2", + "description": "Filter bank 15 register 2", + "addressOffset": "0x2BC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R1", + "displayName": "F16R1", + "description": "Filter bank 16 register 1", + "addressOffset": "0x2C0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F16R2", + "displayName": "F16R2", + "description": "Filter bank 16 register 2", + "addressOffset": "0x2C4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R1", + "displayName": "F17R1", + "description": "Filter bank 17 register 1", + "addressOffset": "0x2C8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F17R2", + "displayName": "F17R2", + "description": "Filter bank 17 register 2", + "addressOffset": "0x2CC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R1", + "displayName": "F18R1", + "description": "Filter bank 18 register 1", + "addressOffset": "0x2D0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F18R2", + "displayName": "F18R2", + "description": "Filter bank 18 register 2", + "addressOffset": "0x2D4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R1", + "displayName": "F19R1", + "description": "Filter bank 19 register 1", + "addressOffset": "0x2D8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F19R2", + "displayName": "F19R2", + "description": "Filter bank 19 register 2", + "addressOffset": "0x2DC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R1", + "displayName": "F20R1", + "description": "Filter bank 20 register 1", + "addressOffset": "0x2E0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F20R2", + "displayName": "F20R2", + "description": "Filter bank 20 register 2", + "addressOffset": "0x2E4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R1", + "displayName": "F21R1", + "description": "Filter bank 21 register 1", + "addressOffset": "0x2E8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F21R2", + "displayName": "F21R2", + "description": "Filter bank 21 register 2", + "addressOffset": "0x2EC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R1", + "displayName": "F22R1", + "description": "Filter bank 22 register 1", + "addressOffset": "0x2F0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F22R2", + "displayName": "F22R2", + "description": "Filter bank 22 register 2", + "addressOffset": "0x2F4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R1", + "displayName": "F23R1", + "description": "Filter bank 23 register 1", + "addressOffset": "0x2F8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F23R2", + "displayName": "F23R2", + "description": "Filter bank 23 register 2", + "addressOffset": "0x2FC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R1", + "displayName": "F24R1", + "description": "Filter bank 24 register 1", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F24R2", + "displayName": "F24R2", + "description": "Filter bank 24 register 2", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R1", + "displayName": "F25R1", + "description": "Filter bank 25 register 1", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F25R2", + "displayName": "F25R2", + "description": "Filter bank 25 register 2", + "addressOffset": "0x30C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R1", + "displayName": "F26R1", + "description": "Filter bank 26 register 1", + "addressOffset": "0x310", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F26R2", + "displayName": "F26R2", + "description": "Filter bank 26 register 2", + "addressOffset": "0x314", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R1", + "displayName": "F27R1", + "description": "Filter bank 27 register 1", + "addressOffset": "0x318", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "F27R2", + "displayName": "F27R2", + "description": "Filter bank 27 register 2", + "addressOffset": "0x31C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FB0", + "description": "Filter bits", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "FB1", + "description": "Filter bits", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "FB2", + "description": "Filter bits", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FB3", + "description": "Filter bits", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FB4", + "description": "Filter bits", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FB5", + "description": "Filter bits", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "FB6", + "description": "Filter bits", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "FB7", + "description": "Filter bits", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "FB8", + "description": "Filter bits", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FB9", + "description": "Filter bits", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "FB10", + "description": "Filter bits", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "FB11", + "description": "Filter bits", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "FB12", + "description": "Filter bits", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "FB13", + "description": "Filter bits", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "FB14", + "description": "Filter bits", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "FB15", + "description": "Filter bits", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "FB16", + "description": "Filter bits", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FB17", + "description": "Filter bits", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FB18", + "description": "Filter bits", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FB19", + "description": "Filter bits", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "FB20", + "description": "Filter bits", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "FB21", + "description": "Filter bits", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "FB22", + "description": "Filter bits", + "bitOffset": "22", + "bitWidth": "1" + }, + { + "name": "FB23", + "description": "Filter bits", + "bitOffset": "23", + "bitWidth": "1" + }, + { + "name": "FB24", + "description": "Filter bits", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "FB25", + "description": "Filter bits", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "FB26", + "description": "Filter bits", + "bitOffset": "26", + "bitWidth": "1" + }, + { + "name": "FB27", + "description": "Filter bits", + "bitOffset": "27", + "bitWidth": "1" + }, + { + "name": "FB28", + "description": "Filter bits", + "bitOffset": "28", + "bitWidth": "1" + }, + { + "name": "FB29", + "description": "Filter bits", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "FB30", + "description": "Filter bits", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "FB31", + "description": "Filter bits", + "bitOffset": "31", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "CAN2", + "derivedFrom": "CAN1", + "baseAddress": "0x40006800", + "interrupts": [ + { + "name": "CAN2_TX", + "description": "CAN2 TX interrupts", + "value": "63" + }, + { + "name": "CAN2_RX0", + "description": "CAN2 RX0 interrupts", + "value": "64" + }, + { + "name": "CAN2_RX1", + "description": "CAN2 RX1 interrupts", + "value": "65" + }, + { + "name": "CAN2_SCE", + "description": "CAN2 SCE interrupt", + "value": "66" + } + ] + }, + { + "name": "NVIC", + "description": "Nested Vectored Interrupt Controller", + "groupName": "NVIC", + "baseAddress": "0xE000E000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x1001", + "usage": "registers" + } + ], + "registers": [ + { + "name": "ICTR", + "displayName": "ICTR", + "description": "Interrupt Controller Type Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTLINESNUM", + "description": "Total number of interrupt lines in groups", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "STIR", + "displayName": "STIR", + "description": "Software Triggered Interrupt Register", + "addressOffset": "0xF00", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "INTID", + "description": "Interrupt to be triggered", + "bitOffset": "0", + "bitWidth": "9" + } + ] + }, + { + "name": "ISER0", + "displayName": "ISER0", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x100", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER1", + "displayName": "ISER1", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISER2", + "displayName": "ISER2", + "description": "Interrupt Set-Enable Register", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETENA", + "description": "SETENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER0", + "displayName": "ICER0", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x180", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER1", + "displayName": "ICER1", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x184", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICER2", + "displayName": "ICER2", + "description": "Interrupt Clear-Enable Register", + "addressOffset": "0x188", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRENA", + "description": "CLRENA", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR0", + "displayName": "ISPR0", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x200", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR1", + "displayName": "ISPR1", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x204", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ISPR2", + "displayName": "ISPR2", + "description": "Interrupt Set-Pending Register", + "addressOffset": "0x208", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SETPEND", + "description": "SETPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR0", + "displayName": "ICPR0", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x280", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR1", + "displayName": "ICPR1", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x284", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ICPR2", + "displayName": "ICPR2", + "description": "Interrupt Clear-Pending Register", + "addressOffset": "0x288", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLRPEND", + "description": "CLRPEND", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR0", + "displayName": "IABR0", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x300", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR1", + "displayName": "IABR1", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x304", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IABR2", + "displayName": "IABR2", + "description": "Interrupt Active Bit Register", + "addressOffset": "0x308", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ACTIVE", + "description": "ACTIVE", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "IPR0", + "displayName": "IPR0", + "description": "Interrupt Priority Register", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR1", + "displayName": "IPR1", + "description": "Interrupt Priority Register", + "addressOffset": "0x404", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR2", + "displayName": "IPR2", + "description": "Interrupt Priority Register", + "addressOffset": "0x408", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR3", + "displayName": "IPR3", + "description": "Interrupt Priority Register", + "addressOffset": "0x40C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR4", + "displayName": "IPR4", + "description": "Interrupt Priority Register", + "addressOffset": "0x410", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR5", + "displayName": "IPR5", + "description": "Interrupt Priority Register", + "addressOffset": "0x414", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR6", + "displayName": "IPR6", + "description": "Interrupt Priority Register", + "addressOffset": "0x418", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR7", + "displayName": "IPR7", + "description": "Interrupt Priority Register", + "addressOffset": "0x41C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR8", + "displayName": "IPR8", + "description": "Interrupt Priority Register", + "addressOffset": "0x420", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR9", + "displayName": "IPR9", + "description": "Interrupt Priority Register", + "addressOffset": "0x424", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR10", + "displayName": "IPR10", + "description": "Interrupt Priority Register", + "addressOffset": "0x428", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR11", + "displayName": "IPR11", + "description": "Interrupt Priority Register", + "addressOffset": "0x42C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR12", + "displayName": "IPR12", + "description": "Interrupt Priority Register", + "addressOffset": "0x430", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR13", + "displayName": "IPR13", + "description": "Interrupt Priority Register", + "addressOffset": "0x434", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR14", + "displayName": "IPR14", + "description": "Interrupt Priority Register", + "addressOffset": "0x438", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR15", + "displayName": "IPR15", + "description": "Interrupt Priority Register", + "addressOffset": "0x43C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR16", + "displayName": "IPR16", + "description": "Interrupt Priority Register", + "addressOffset": "0x440", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR17", + "displayName": "IPR17", + "description": "Interrupt Priority Register", + "addressOffset": "0x444", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR18", + "displayName": "IPR18", + "description": "Interrupt Priority Register", + "addressOffset": "0x448", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR19", + "displayName": "IPR19", + "description": "Interrupt Priority Register", + "addressOffset": "0x44C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + }, + { + "name": "IPR20", + "displayName": "IPR20", + "description": "Interrupt Priority Register", + "addressOffset": "0x450", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "IPR_N0", + "description": "IPR_N0", + "bitOffset": "0", + "bitWidth": "8" + }, + { + "name": "IPR_N1", + "description": "IPR_N1", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "IPR_N2", + "description": "IPR_N2", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "IPR_N3", + "description": "IPR_N3", + "bitOffset": "24", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "FLASH", + "description": "FLASH", + "groupName": "FLASH", + "baseAddress": "0x40023C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "FLASH", + "description": "Flash global interrupt", + "value": "4" + } + ], + "registers": [ + { + "name": "ACR", + "displayName": "ACR", + "description": "Flash access control register", + "addressOffset": "0x0", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LATENCY", + "description": "Latency", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PRFTEN", + "description": "Prefetch enable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICEN", + "description": "Instruction cache enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DCEN", + "description": "Data cache enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ICRST", + "description": "Instruction cache reset", + "bitOffset": "11", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "DCRST", + "description": "Data cache reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "KEYR", + "displayName": "KEYR", + "description": "Flash key register", + "addressOffset": "0x4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "KEY", + "description": "FPEC key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPTKEYR", + "displayName": "OPTKEYR", + "description": "Flash option key register", + "addressOffset": "0x8", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "OPTKEY", + "description": "Option byte key", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "SR", + "displayName": "SR", + "description": "Status register", + "addressOffset": "0xC", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "EOP", + "description": "End of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OPERR", + "description": "Operation error", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WRPERR", + "description": "Write protection error", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGAERR", + "description": "Programming alignment error", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGPERR", + "description": "Programming parallelism error", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PGSERR", + "description": "Programming sequence error", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BSY", + "description": "Busy", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x80000000", + "fields": [ + { + "name": "PG", + "description": "Programming", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SER", + "description": "Sector Erase", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MER", + "description": "Mass Erase of sectors 0 to 11", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SNB", + "description": "Sector number", + "bitOffset": "3", + "bitWidth": "5" + }, + { + "name": "PSIZE", + "description": "Program size", + "bitOffset": "8", + "bitWidth": "2" + }, + { + "name": "MER1", + "description": "Mass Erase of sectors 12 to 23", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "STRT", + "description": "Start", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "EOPIE", + "description": "End of operation interrupt enable", + "bitOffset": "24", + "bitWidth": "1" + }, + { + "name": "ERRIE", + "description": "Error interrupt enable", + "bitOffset": "25", + "bitWidth": "1" + }, + { + "name": "LOCK", + "description": "Lock", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OPTCR", + "displayName": "OPTCR", + "description": "Flash option control register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFFAAED", + "fields": [ + { + "name": "OPTLOCK", + "description": "Option lock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "OPTSTRT", + "description": "Option start", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "BOR_LEV", + "description": "BOR reset Level", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "WDG_SW", + "description": "WDG_SW User option bytes", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "nRST_STOP", + "description": "NRST_STOP User option bytes", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "nRST_STDBY", + "description": "NRST_STDBY User option bytes", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "RDP", + "description": "Read protect", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + }, + { + "name": "OPTCR1", + "displayName": "OPTCR1", + "description": "Flash option control register 1", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0FFF0000", + "fields": [ + { + "name": "nWRP", + "description": "Not write protect", + "bitOffset": "16", + "bitWidth": "12" + } + ] + } + ] + }, + { + "name": "EXTI", + "description": "External interrupt/event controller", + "groupName": "EXTI", + "baseAddress": "0x40013C00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "TAMP_STAMP", + "description": "Tamper and TimeStamp interrupts through the EXTI line", + "value": "2" + }, + { + "name": "EXTI0", + "description": "EXTI Line0 interrupt", + "value": "6" + }, + { + "name": "EXTI1", + "description": "EXTI Line1 interrupt", + "value": "7" + }, + { + "name": "EXTI2", + "description": "EXTI Line2 interrupt", + "value": "8" + }, + { + "name": "EXTI3", + "description": "EXTI Line3 interrupt", + "value": "9" + }, + { + "name": "EXTI4", + "description": "EXTI Line4 interrupt", + "value": "10" + }, + { + "name": "EXTI9_5", + "description": "EXTI Line[9:5] interrupts", + "value": "23" + }, + { + "name": "EXTI15_10", + "description": "EXTI Line[15:10] interrupts", + "value": "40" + } + ], + "registers": [ + { + "name": "IMR", + "displayName": "IMR", + "description": "Interrupt mask register (EXTI_IMR)", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Interrupt Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Interrupt Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Interrupt Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Interrupt Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Interrupt Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Interrupt Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Interrupt Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Interrupt Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Interrupt Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Interrupt Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Interrupt Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Interrupt Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Interrupt Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Interrupt Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Interrupt Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Interrupt Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Interrupt Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Interrupt Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Interrupt Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Interrupt Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Interrupt Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Interrupt Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Interrupt Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "EMR", + "displayName": "EMR", + "description": "Event mask register (EXTI_EMR)", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MR0", + "description": "Event Mask on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "MR1", + "description": "Event Mask on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "MR2", + "description": "Event Mask on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MR3", + "description": "Event Mask on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "MR4", + "description": "Event Mask on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "MR5", + "description": "Event Mask on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "MR6", + "description": "Event Mask on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MR7", + "description": "Event Mask on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "MR8", + "description": "Event Mask on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "MR9", + "description": "Event Mask on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "MR10", + "description": "Event Mask on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MR11", + "description": "Event Mask on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "MR12", + "description": "Event Mask on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "MR13", + "description": "Event Mask on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MR14", + "description": "Event Mask on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "MR15", + "description": "Event Mask on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "MR16", + "description": "Event Mask on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "MR17", + "description": "Event Mask on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "MR18", + "description": "Event Mask on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "MR19", + "description": "Event Mask on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "MR20", + "description": "Event Mask on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "MR21", + "description": "Event Mask on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "MR22", + "description": "Event Mask on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "RTSR", + "displayName": "RTSR", + "description": "Rising Trigger selection register (EXTI_RTSR)", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Rising trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Rising trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Rising trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Rising trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Rising trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Rising trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Rising trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Rising trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Rising trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Rising trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Rising trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Rising trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Rising trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Rising trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Rising trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Rising trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Rising trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Rising trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Rising trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Rising trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Rising trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Rising trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Rising trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "FTSR", + "displayName": "FTSR", + "description": "Falling Trigger selection register (EXTI_FTSR)", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TR0", + "description": "Falling trigger event configuration of line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "TR1", + "description": "Falling trigger event configuration of line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TR2", + "description": "Falling trigger event configuration of line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TR3", + "description": "Falling trigger event configuration of line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TR4", + "description": "Falling trigger event configuration of line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "TR5", + "description": "Falling trigger event configuration of line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TR6", + "description": "Falling trigger event configuration of line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TR7", + "description": "Falling trigger event configuration of line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "TR8", + "description": "Falling trigger event configuration of line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "TR9", + "description": "Falling trigger event configuration of line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TR10", + "description": "Falling trigger event configuration of line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TR11", + "description": "Falling trigger event configuration of line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TR12", + "description": "Falling trigger event configuration of line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "TR13", + "description": "Falling trigger event configuration of line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "TR14", + "description": "Falling trigger event configuration of line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "TR15", + "description": "Falling trigger event configuration of line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "TR16", + "description": "Falling trigger event configuration of line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "TR17", + "description": "Falling trigger event configuration of line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "TR18", + "description": "Falling trigger event configuration of line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "TR19", + "description": "Falling trigger event configuration of line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "TR20", + "description": "Falling trigger event configuration of line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "TR21", + "description": "Falling trigger event configuration of line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "TR22", + "description": "Falling trigger event configuration of line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "SWIER", + "displayName": "SWIER", + "description": "Software interrupt event register (EXTI_SWIER)", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SWIER0", + "description": "Software Interrupt on line 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "SWIER1", + "description": "Software Interrupt on line 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "SWIER2", + "description": "Software Interrupt on line 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SWIER3", + "description": "Software Interrupt on line 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "SWIER4", + "description": "Software Interrupt on line 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "SWIER5", + "description": "Software Interrupt on line 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "SWIER6", + "description": "Software Interrupt on line 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "SWIER7", + "description": "Software Interrupt on line 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "SWIER8", + "description": "Software Interrupt on line 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "SWIER9", + "description": "Software Interrupt on line 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "SWIER10", + "description": "Software Interrupt on line 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "SWIER11", + "description": "Software Interrupt on line 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "SWIER12", + "description": "Software Interrupt on line 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SWIER13", + "description": "Software Interrupt on line 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "SWIER14", + "description": "Software Interrupt on line 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "SWIER15", + "description": "Software Interrupt on line 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "SWIER16", + "description": "Software Interrupt on line 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SWIER17", + "description": "Software Interrupt on line 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SWIER18", + "description": "Software Interrupt on line 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "SWIER19", + "description": "Software Interrupt on line 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SWIER20", + "description": "Software Interrupt on line 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "SWIER21", + "description": "Software Interrupt on line 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "SWIER22", + "description": "Software Interrupt on line 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + }, + { + "name": "PR", + "displayName": "PR", + "description": "Pending register (EXTI_PR)", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PR0", + "description": "Pending bit 0", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PR1", + "description": "Pending bit 1", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PR2", + "description": "Pending bit 2", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "PR3", + "description": "Pending bit 3", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PR4", + "description": "Pending bit 4", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PR5", + "description": "Pending bit 5", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "PR6", + "description": "Pending bit 6", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "PR7", + "description": "Pending bit 7", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PR8", + "description": "Pending bit 8", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "PR9", + "description": "Pending bit 9", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "PR10", + "description": "Pending bit 10", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "PR11", + "description": "Pending bit 11", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "PR12", + "description": "Pending bit 12", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "PR13", + "description": "Pending bit 13", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "PR14", + "description": "Pending bit 14", + "bitOffset": "14", + "bitWidth": "1" + }, + { + "name": "PR15", + "description": "Pending bit 15", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "PR16", + "description": "Pending bit 16", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "PR17", + "description": "Pending bit 17", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "PR18", + "description": "Pending bit 18", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "PR19", + "description": "Pending bit 19", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "PR20", + "description": "Pending bit 20", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "PR21", + "description": "Pending bit 21", + "bitOffset": "21", + "bitWidth": "1" + }, + { + "name": "PR22", + "description": "Pending bit 22", + "bitOffset": "22", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "OTG_HS_GLOBAL", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "OTG_HS_EP1_OUT", + "description": "USB On The Go HS End Point 1 Out global interrupt", + "value": "74" + }, + { + "name": "OTG_HS_EP1_IN", + "description": "USB On The Go HS End Point 1 In global interrupt", + "value": "75" + }, + { + "name": "OTG_HS_WKUP", + "description": "USB On The Go HS Wakeup through EXTI interrupt", + "value": "76" + }, + { + "name": "OTG_HS", + "description": "USB On The Go HS global interrupt", + "value": "77" + } + ], + "registers": [ + { + "name": "OTG_HS_GOTGCTL", + "displayName": "OTG_HS_GOTGCTL", + "description": "OTG_HS control and status register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x00000800", + "fields": [ + { + "name": "SRQSCS", + "description": "Session request success", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SRQ", + "description": "Session request", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNGSCS", + "description": "Host negotiation success", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HNPRQ", + "description": "HNP request", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSHNPEN", + "description": "Host set HNP enable", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DHNPEN", + "description": "Device HNP enabled", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSTS", + "description": "Connector ID status", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "DBCT", + "description": "Long/short debounce time", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ASVLD", + "description": "A-session valid", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BSVLD", + "description": "B-session valid", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GOTGINT", + "displayName": "OTG_HS_GOTGINT", + "description": "OTG_HS interrupt register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "SEDET", + "description": "Session end detected", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SRSSCHG", + "description": "Session request success status change", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "HNSSCHG", + "description": "Host negotiation success status change", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "HNGDET", + "description": "Host negotiation detected", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "ADTOCHG", + "description": "A-device timeout change", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "DBCDNE", + "description": "Debounce done", + "bitOffset": "19", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GAHBCFG", + "displayName": "OTG_HS_GAHBCFG", + "description": "OTG_HS AHB configuration register", + "addressOffset": "0x8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "GINT", + "description": "Global interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "HBSTLEN", + "description": "Burst length/type", + "bitOffset": "1", + "bitWidth": "4" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TXFELVL", + "description": "TxFIFO empty level", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "PTXFELVL", + "description": "Periodic TxFIFO empty level", + "bitOffset": "8", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_GUSBCFG", + "displayName": "OTG_HS_GUSBCFG", + "description": "OTG_HS USB configuration register", + "addressOffset": "0xC", + "size": "32", + "resetValue": "0x00000A00", + "fields": [ + { + "name": "TOCAL", + "description": "FS timeout calibration", + "bitOffset": "0", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "PHYSEL", + "description": "USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select", + "bitOffset": "6", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SRPCAP", + "description": "SRP-capable", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HNPCAP", + "description": "HNP-capable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TRDT", + "description": "USB turnaround time", + "bitOffset": "10", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PHYLPCS", + "description": "PHY Low-power clock select", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIFSLS", + "description": "ULPI FS/LS select", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIAR", + "description": "ULPI Auto-resume", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPICSM", + "description": "ULPI Clock SuspendM", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSD", + "description": "ULPI External VBUS Drive", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIEVBUSI", + "description": "ULPI external VBUS indicator", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TSDPS", + "description": "TermSel DLine pulsing selection", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PCCI", + "description": "Indicator complement", + "bitOffset": "23", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCI", + "description": "Indicator pass through", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ULPIIPD", + "description": "ULPI interface protect disable", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FHMOD", + "description": "Forced host mode", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FDMOD", + "description": "Forced peripheral mode", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CTXPKT", + "description": "Corrupt Tx packet", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRSTCTL", + "displayName": "OTG_HS_GRSTCTL", + "description": "OTG_HS reset register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x20000000", + "fields": [ + { + "name": "CSRST", + "description": "Core soft reset", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HSRST", + "description": "HCLK soft reset", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FCRST", + "description": "Host frame counter reset", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFFLSH", + "description": "RxFIFO flush", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFFLSH", + "description": "TxFIFO flush", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "6", + "bitWidth": "5", + "access": "read-write" + }, + { + "name": "DMAREQ", + "description": "DMA request signal", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "AHBIDL", + "description": "AHB master idle", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_GINTSTS", + "displayName": "OTG_HS_GINTSTS", + "description": "OTG_HS core interrupt register", + "addressOffset": "0x14", + "size": "32", + "resetValue": "0x04000020", + "fields": [ + { + "name": "CMOD", + "description": "Current mode of operation", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "MMIS", + "description": "Mode mismatch interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SOF", + "description": "Start of frame", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVL", + "description": "RxFIFO nonempty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NPTXFE", + "description": "Nonperiodic TxFIFO empty", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GINAKEFF", + "description": "Global IN nonperiodic NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BOUTNAKEFF", + "description": "Global OUT NAK effective", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ESUSP", + "description": "Early suspend", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSP", + "description": "USB suspend", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNE", + "description": "Enumeration done", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRP", + "description": "Isochronous OUT packet dropped interrupt", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPF", + "description": "End of periodic frame interrupt", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoint interrupt", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "IISOIXFR", + "description": "Incomplete isochronous IN transfer", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFR_INCOMPISOOUT", + "description": "Incomplete periodic transfer", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DATAFSUSP", + "description": "Data fetch suspended", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "HPRTINT", + "description": "Host port interrupt", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCINT", + "description": "Host channels interrupt", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PTXFE", + "description": "Periodic TxFIFO empty", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "CIDSCHG", + "description": "Connector ID status change", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQINT", + "description": "Session request/new session detected interrupt", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WKUINT", + "description": "Resume/remote wakeup detected interrupt", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GINTMSK", + "displayName": "OTG_HS_GINTMSK", + "description": "OTG_HS interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MMISM", + "description": "Mode mismatch interrupt mask", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OTGINT", + "description": "OTG interrupt mask", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SOFM", + "description": "Start of frame mask", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "RXFLVLM", + "description": "Receive FIFO nonempty mask", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NPTXFEM", + "description": "Nonperiodic TxFIFO empty mask", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINAKEFFM", + "description": "Global nonperiodic IN NAK effective mask", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GONAKEFFM", + "description": "Global OUT NAK effective mask", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ESUSPM", + "description": "Early suspend mask", + "bitOffset": "10", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBSUSPM", + "description": "USB suspend mask", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "USBRST", + "description": "USB reset mask", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ENUMDNEM", + "description": "Enumeration done mask", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ISOODRPM", + "description": "Isochronous OUT packet dropped interrupt mask", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EOPFM", + "description": "End of periodic frame interrupt mask", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPMISM", + "description": "Endpoint mismatch interrupt mask", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IEPINT", + "description": "IN endpoints interrupt mask", + "bitOffset": "18", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "OEPINT", + "description": "OUT endpoints interrupt mask", + "bitOffset": "19", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "IISOIXFRM", + "description": "Incomplete isochronous IN transfer mask", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PXFRM_IISOOXFRM", + "description": "Incomplete periodic transfer mask", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "FSUSPM", + "description": "Data fetch suspended mask", + "bitOffset": "22", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRTIM", + "description": "Host port interrupt mask", + "bitOffset": "24", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "HCIM", + "description": "Host channels interrupt mask", + "bitOffset": "25", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTXFEM", + "description": "Periodic TxFIFO empty mask", + "bitOffset": "26", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CIDSCHGM", + "description": "Connector ID status change mask", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DISCINT", + "description": "Disconnect detected interrupt mask", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SRQIM", + "description": "Session request/new session detected interrupt mask", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "WUIM", + "description": "Resume/remote wakeup detected interrupt mask", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Host", + "displayName": "OTG_HS_GRXSTSR_Host", + "description": "OTG_HS Receive status debug read register (host mode)", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Host", + "displayName": "OTG_HS_GRXSTSP_Host", + "description": "OTG_HS status read and pop register (host mode)", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "CHNUM", + "description": "Channel number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXFSIZ", + "displayName": "OTG_HS_GRXFSIZ", + "description": "OTG_HS Receive FIFO size register", + "addressOffset": "0x24", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "RXFD", + "description": "RxFIFO depth", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXFSIZ_Host", + "displayName": "OTG_HS_GNPTXFSIZ_Host", + "description": "OTG_HS nonperiodic transmit FIFO size register (host mode)", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "NPTXFSA", + "description": "Nonperiodic transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTXFD", + "description": "Nonperiodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_TX0FSIZ_Peripheral", + "displayName": "OTG_HS_TX0FSIZ_Peripheral", + "description": "Endpoint 0 transmit FIFO size (peripheral mode)", + "headerStructName": "OTG_HS_GNPTXFSIZ_Host", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x00000200", + "fields": [ + { + "name": "TX0FSA", + "description": "Endpoint 0 transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "TX0FD", + "description": "Endpoint 0 TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GNPTXSTS", + "displayName": "OTG_HS_GNPTXSTS", + "description": "OTG_HS nonperiodic transmit FIFO/queue status register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-only", + "resetValue": "0x00080200", + "fields": [ + { + "name": "NPTXFSAV", + "description": "Nonperiodic TxFIFO space available", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "NPTQXSAV", + "description": "Nonperiodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "NPTXQTOP", + "description": "Top of the nonperiodic transmit request queue", + "bitOffset": "24", + "bitWidth": "7" + } + ] + }, + { + "name": "OTG_HS_GCCFG", + "displayName": "OTG_HS_GCCFG", + "description": "OTG_HS general core configuration register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PWRDWN", + "description": "Power down", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "I2CPADEN", + "description": "Enable I2C bus connection for the external I2C PHY interface", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "VBUSASEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "VBUSBSEN", + "description": "Enable the VBUS sensing device", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "SOFOUTEN", + "description": "SOF output enable", + "bitOffset": "20", + "bitWidth": "1" + }, + { + "name": "NOVBUSSENS", + "description": "VBUS sensing disable option", + "bitOffset": "21", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_CID", + "displayName": "OTG_HS_CID", + "description": "OTG_HS core ID register", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x00001200", + "fields": [ + { + "name": "PRODUCT_ID", + "description": "Product ID field", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HPTXFSIZ", + "displayName": "OTG_HS_HPTXFSIZ", + "description": "OTG_HS Host periodic transmit FIFO size register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x02000600", + "fields": [ + { + "name": "PTXSA", + "description": "Host periodic TxFIFO start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "PTXFD", + "description": "Host periodic TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF1", + "displayName": "OTG_HS_DIEPTXF1", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF2", + "displayName": "OTG_HS_DIEPTXF2", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF3", + "displayName": "OTG_HS_DIEPTXF3", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x11C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF4", + "displayName": "OTG_HS_DIEPTXF4", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF5", + "displayName": "OTG_HS_DIEPTXF5", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF6", + "displayName": "OTG_HS_DIEPTXF6", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTXF7", + "displayName": "OTG_HS_DIEPTXF7", + "description": "OTG_HS device IN endpoint transmit FIFO size register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x02000400", + "fields": [ + { + "name": "INEPTXSA", + "description": "IN endpoint FIFOx transmit RAM start address", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "INEPTXFD", + "description": "IN endpoint TxFIFO depth", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_GRXSTSR_Peripheral", + "displayName": "OTG_HS_GRXSTSR_Peripheral", + "description": "OTG_HS Receive status debug read register (peripheral mode mode)", + "headerStructName": "OTG_HS_GRXSTSR_Host", + "addressOffset": "0x1C", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + }, + { + "name": "OTG_HS_GRXSTSP_Peripheral", + "displayName": "OTG_HS_GRXSTSP_Peripheral", + "description": "OTG_HS status read and pop register (peripheral mode)", + "headerStructName": "OTG_HS_GRXSTSP_Host", + "addressOffset": "0x20", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "0", + "bitWidth": "4" + }, + { + "name": "BCNT", + "description": "Byte count", + "bitOffset": "4", + "bitWidth": "11" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "15", + "bitWidth": "2" + }, + { + "name": "PKTSTS", + "description": "Packet status", + "bitOffset": "17", + "bitWidth": "4" + }, + { + "name": "FRMNUM", + "description": "Frame number", + "bitOffset": "21", + "bitWidth": "4" + } + ] + } + ] + }, + { + "name": "OTG_HS_HOST", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040400", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_HCFG", + "displayName": "OTG_HS_HCFG", + "description": "OTG_HS host configuration register", + "addressOffset": "0x0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "FSLSPCS", + "description": "FS/LS PHY clock select", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "FSLSS", + "description": "FS- and LS-only support", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HFIR", + "displayName": "OTG_HS_HFIR", + "description": "OTG_HS Host frame interval register", + "addressOffset": "0x4", + "size": "32", + "access": "read-write", + "resetValue": "0x0000EA60", + "fields": [ + { + "name": "FRIVL", + "description": "Frame interval", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HFNUM", + "displayName": "OTG_HS_HFNUM", + "description": "OTG_HS host frame number/frame time remaining register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00003FFF", + "fields": [ + { + "name": "FRNUM", + "description": "Frame number", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "FTREM", + "description": "Frame time remaining", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPTXSTS", + "displayName": "OTG_HS_HPTXSTS", + "description": "OTG_HS_Host periodic transmit FIFO/queue status register", + "addressOffset": "0x10", + "size": "32", + "resetValue": "0x00080100", + "fields": [ + { + "name": "PTXFSAVL", + "description": "Periodic transmit data FIFO space available", + "bitOffset": "0", + "bitWidth": "16", + "access": "read-write" + }, + { + "name": "PTXQSAV", + "description": "Periodic transmit request queue space available", + "bitOffset": "16", + "bitWidth": "8", + "access": "read-only" + }, + { + "name": "PTXQTOP", + "description": "Top of the periodic transmit request queue", + "bitOffset": "24", + "bitWidth": "8", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HAINT", + "displayName": "OTG_HS_HAINT", + "description": "OTG_HS Host all channels interrupt register", + "addressOffset": "0x14", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINT", + "description": "Channel interrupts", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HAINTMSK", + "displayName": "OTG_HS_HAINTMSK", + "description": "OTG_HS host all channels interrupt mask register", + "addressOffset": "0x18", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "HAINTM", + "description": "Channel interrupt mask", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_HPRT", + "displayName": "OTG_HS_HPRT", + "description": "OTG_HS host port control and status register", + "addressOffset": "0x40", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "PCSTS", + "description": "Port connect status", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PCDET", + "description": "Port connect detected", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENA", + "description": "Port enable", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PENCHNG", + "description": "Port enable/disable change", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "POCA", + "description": "Port overcurrent active", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "POCCHNG", + "description": "Port overcurrent change", + "bitOffset": "5", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRES", + "description": "Port resume", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PSUSP", + "description": "Port suspend", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PRST", + "description": "Port reset", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PLSTS", + "description": "Port line status", + "bitOffset": "10", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "PPWR", + "description": "Port power", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PTCTL", + "description": "Port test control", + "bitOffset": "13", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "PSPD", + "description": "Port speed", + "bitOffset": "17", + "bitWidth": "2", + "access": "read-only" + } + ] + }, + { + "name": "OTG_HS_HCCHAR0", + "displayName": "OTG_HS_HCCHAR0", + "description": "OTG_HS host channel-0 characteristics register", + "addressOffset": "0x100", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR1", + "displayName": "OTG_HS_HCCHAR1", + "description": "OTG_HS host channel-1 characteristics register", + "addressOffset": "0x120", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR2", + "displayName": "OTG_HS_HCCHAR2", + "description": "OTG_HS host channel-2 characteristics register", + "addressOffset": "0x140", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR3", + "displayName": "OTG_HS_HCCHAR3", + "description": "OTG_HS host channel-3 characteristics register", + "addressOffset": "0x160", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR4", + "displayName": "OTG_HS_HCCHAR4", + "description": "OTG_HS host channel-4 characteristics register", + "addressOffset": "0x180", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR5", + "displayName": "OTG_HS_HCCHAR5", + "description": "OTG_HS host channel-5 characteristics register", + "addressOffset": "0x1A0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR6", + "displayName": "OTG_HS_HCCHAR6", + "description": "OTG_HS host channel-6 characteristics register", + "addressOffset": "0x1C0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR7", + "displayName": "OTG_HS_HCCHAR7", + "description": "OTG_HS host channel-7 characteristics register", + "addressOffset": "0x1E0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR8", + "displayName": "OTG_HS_HCCHAR8", + "description": "OTG_HS host channel-8 characteristics register", + "addressOffset": "0x200", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR9", + "displayName": "OTG_HS_HCCHAR9", + "description": "OTG_HS host channel-9 characteristics register", + "addressOffset": "0x220", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR10", + "displayName": "OTG_HS_HCCHAR10", + "description": "OTG_HS host channel-10 characteristics register", + "addressOffset": "0x240", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCCHAR11", + "displayName": "OTG_HS_HCCHAR11", + "description": "OTG_HS host channel-11 characteristics register", + "addressOffset": "0x260", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11" + }, + { + "name": "EPNUM", + "description": "Endpoint number", + "bitOffset": "11", + "bitWidth": "4" + }, + { + "name": "EPDIR", + "description": "Endpoint direction", + "bitOffset": "15", + "bitWidth": "1" + }, + { + "name": "LSDEV", + "description": "Low-speed device", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2" + }, + { + "name": "MC", + "description": "Multi Count (MC) / Error Count (EC)", + "bitOffset": "20", + "bitWidth": "2" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "22", + "bitWidth": "7" + }, + { + "name": "ODDFRM", + "description": "Odd frame", + "bitOffset": "29", + "bitWidth": "1" + }, + { + "name": "CHDIS", + "description": "Channel disable", + "bitOffset": "30", + "bitWidth": "1" + }, + { + "name": "CHENA", + "description": "Channel enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT0", + "displayName": "OTG_HS_HCSPLT0", + "description": "OTG_HS host channel-0 split control register", + "addressOffset": "0x104", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT1", + "displayName": "OTG_HS_HCSPLT1", + "description": "OTG_HS host channel-1 split control register", + "addressOffset": "0x124", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT2", + "displayName": "OTG_HS_HCSPLT2", + "description": "OTG_HS host channel-2 split control register", + "addressOffset": "0x144", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT3", + "displayName": "OTG_HS_HCSPLT3", + "description": "OTG_HS host channel-3 split control register", + "addressOffset": "0x164", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT4", + "displayName": "OTG_HS_HCSPLT4", + "description": "OTG_HS host channel-4 split control register", + "addressOffset": "0x184", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT5", + "displayName": "OTG_HS_HCSPLT5", + "description": "OTG_HS host channel-5 split control register", + "addressOffset": "0x1A4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT6", + "displayName": "OTG_HS_HCSPLT6", + "description": "OTG_HS host channel-6 split control register", + "addressOffset": "0x1C4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT7", + "displayName": "OTG_HS_HCSPLT7", + "description": "OTG_HS host channel-7 split control register", + "addressOffset": "0x1E4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT8", + "displayName": "OTG_HS_HCSPLT8", + "description": "OTG_HS host channel-8 split control register", + "addressOffset": "0x204", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT9", + "displayName": "OTG_HS_HCSPLT9", + "description": "OTG_HS host channel-9 split control register", + "addressOffset": "0x224", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT10", + "displayName": "OTG_HS_HCSPLT10", + "description": "OTG_HS host channel-10 split control register", + "addressOffset": "0x244", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCSPLT11", + "displayName": "OTG_HS_HCSPLT11", + "description": "OTG_HS host channel-11 split control register", + "addressOffset": "0x264", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "PRTADDR", + "description": "Port address", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "HUBADDR", + "description": "Hub address", + "bitOffset": "7", + "bitWidth": "7" + }, + { + "name": "XACTPOS", + "description": "XACTPOS", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "COMPLSPLT", + "description": "Do complete split", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "SPLITEN", + "description": "Split enable", + "bitOffset": "31", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT0", + "displayName": "OTG_HS_HCINT0", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x108", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT1", + "displayName": "OTG_HS_HCINT1", + "description": "OTG_HS host channel-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT2", + "displayName": "OTG_HS_HCINT2", + "description": "OTG_HS host channel-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT3", + "displayName": "OTG_HS_HCINT3", + "description": "OTG_HS host channel-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT4", + "displayName": "OTG_HS_HCINT4", + "description": "OTG_HS host channel-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT5", + "displayName": "OTG_HS_HCINT5", + "description": "OTG_HS host channel-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT6", + "displayName": "OTG_HS_HCINT6", + "description": "OTG_HS host channel-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT7", + "displayName": "OTG_HS_HCINT7", + "description": "OTG_HS host channel-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT8", + "displayName": "OTG_HS_HCINT8", + "description": "OTG_HS host channel-8 interrupt register", + "addressOffset": "0x208", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT9", + "displayName": "OTG_HS_HCINT9", + "description": "OTG_HS host channel-9 interrupt register", + "addressOffset": "0x228", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT10", + "displayName": "OTG_HS_HCINT10", + "description": "OTG_HS host channel-10 interrupt register", + "addressOffset": "0x248", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINT11", + "displayName": "OTG_HS_HCINT11", + "description": "OTG_HS host channel-11 interrupt register", + "addressOffset": "0x268", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHH", + "description": "Channel halted", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALL", + "description": "STALL response received interrupt", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAK", + "description": "NAK response received interrupt", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACK", + "description": "ACK response received/transmitted interrupt", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERR", + "description": "Transaction error", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERR", + "description": "Babble error", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMOR", + "description": "Frame overrun", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERR", + "description": "Data toggle error", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK0", + "displayName": "OTG_HS_HCINTMSK0", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x10C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK1", + "displayName": "OTG_HS_HCINTMSK1", + "description": "OTG_HS host channel-1 interrupt mask register", + "addressOffset": "0x12C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK2", + "displayName": "OTG_HS_HCINTMSK2", + "description": "OTG_HS host channel-2 interrupt mask register", + "addressOffset": "0x14C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK3", + "displayName": "OTG_HS_HCINTMSK3", + "description": "OTG_HS host channel-3 interrupt mask register", + "addressOffset": "0x16C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK4", + "displayName": "OTG_HS_HCINTMSK4", + "description": "OTG_HS host channel-4 interrupt mask register", + "addressOffset": "0x18C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK5", + "displayName": "OTG_HS_HCINTMSK5", + "description": "OTG_HS host channel-5 interrupt mask register", + "addressOffset": "0x1AC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK6", + "displayName": "OTG_HS_HCINTMSK6", + "description": "OTG_HS host channel-6 interrupt mask register", + "addressOffset": "0x1CC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK7", + "displayName": "OTG_HS_HCINTMSK7", + "description": "OTG_HS host channel-7 interrupt mask register", + "addressOffset": "0x1EC", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK8", + "displayName": "OTG_HS_HCINTMSK8", + "description": "OTG_HS host channel-8 interrupt mask register", + "addressOffset": "0x20C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK9", + "displayName": "OTG_HS_HCINTMSK9", + "description": "OTG_HS host channel-9 interrupt mask register", + "addressOffset": "0x22C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK10", + "displayName": "OTG_HS_HCINTMSK10", + "description": "OTG_HS host channel-10 interrupt mask register", + "addressOffset": "0x24C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCINTMSK11", + "displayName": "OTG_HS_HCINTMSK11", + "description": "OTG_HS host channel-11 interrupt mask register", + "addressOffset": "0x26C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "CHHM", + "description": "Channel halted mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "AHBERR", + "description": "AHB error", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "STALLM", + "description": "STALL response received interrupt mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK response received interrupt mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "ACKM", + "description": "ACK response received/transmitted interrupt mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "Response received interrupt mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXERRM", + "description": "Transaction error mask", + "bitOffset": "7", + "bitWidth": "1" + }, + { + "name": "BBERRM", + "description": "Babble error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FRMORM", + "description": "Frame overrun mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "DTERRM", + "description": "Data toggle error mask", + "bitOffset": "10", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ0", + "displayName": "OTG_HS_HCTSIZ0", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ1", + "displayName": "OTG_HS_HCTSIZ1", + "description": "OTG_HS host channel-1 transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ2", + "displayName": "OTG_HS_HCTSIZ2", + "description": "OTG_HS host channel-2 transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ3", + "displayName": "OTG_HS_HCTSIZ3", + "description": "OTG_HS host channel-3 transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ4", + "displayName": "OTG_HS_HCTSIZ4", + "description": "OTG_HS host channel-4 transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ5", + "displayName": "OTG_HS_HCTSIZ5", + "description": "OTG_HS host channel-5 transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ6", + "displayName": "OTG_HS_HCTSIZ6", + "description": "OTG_HS host channel-6 transfer size register", + "addressOffset": "0x1D0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ7", + "displayName": "OTG_HS_HCTSIZ7", + "description": "OTG_HS host channel-7 transfer size register", + "addressOffset": "0x1F0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ8", + "displayName": "OTG_HS_HCTSIZ8", + "description": "OTG_HS host channel-8 transfer size register", + "addressOffset": "0x210", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ9", + "displayName": "OTG_HS_HCTSIZ9", + "description": "OTG_HS host channel-9 transfer size register", + "addressOffset": "0x230", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ10", + "displayName": "OTG_HS_HCTSIZ10", + "description": "OTG_HS host channel-10 transfer size register", + "addressOffset": "0x250", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCTSIZ11", + "displayName": "OTG_HS_HCTSIZ11", + "description": "OTG_HS host channel-11 transfer size register", + "addressOffset": "0x270", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "DPID", + "description": "Data PID", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_HCDMA0", + "displayName": "OTG_HS_HCDMA0", + "description": "OTG_HS host channel-0 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA1", + "displayName": "OTG_HS_HCDMA1", + "description": "OTG_HS host channel-1 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA2", + "displayName": "OTG_HS_HCDMA2", + "description": "OTG_HS host channel-2 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA3", + "displayName": "OTG_HS_HCDMA3", + "description": "OTG_HS host channel-3 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA4", + "displayName": "OTG_HS_HCDMA4", + "description": "OTG_HS host channel-4 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA5", + "displayName": "OTG_HS_HCDMA5", + "description": "OTG_HS host channel-5 DMA address register", + "addressOffset": "0x1B4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA6", + "displayName": "OTG_HS_HCDMA6", + "description": "OTG_HS host channel-6 DMA address register", + "addressOffset": "0x1D4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA7", + "displayName": "OTG_HS_HCDMA7", + "description": "OTG_HS host channel-7 DMA address register", + "addressOffset": "0x1F4", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA8", + "displayName": "OTG_HS_HCDMA8", + "description": "OTG_HS host channel-8 DMA address register", + "addressOffset": "0x214", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA9", + "displayName": "OTG_HS_HCDMA9", + "description": "OTG_HS host channel-9 DMA address register", + "addressOffset": "0x234", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA10", + "displayName": "OTG_HS_HCDMA10", + "description": "OTG_HS host channel-10 DMA address register", + "addressOffset": "0x254", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_HCDMA11", + "displayName": "OTG_HS_HCDMA11", + "description": "OTG_HS host channel-11 DMA address register", + "addressOffset": "0x274", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "OTG_HS_DEVICE", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_DCFG", + "displayName": "OTG_HS_DCFG", + "description": "OTG_HS device configuration register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x02200000", + "fields": [ + { + "name": "DSPD", + "description": "Device speed", + "bitOffset": "0", + "bitWidth": "2" + }, + { + "name": "NZLSOHSK", + "description": "Nonzero-length status OUT handshake", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "DAD", + "description": "Device address", + "bitOffset": "4", + "bitWidth": "7" + }, + { + "name": "PFIVL", + "description": "Periodic (micro)frame interval", + "bitOffset": "11", + "bitWidth": "2" + }, + { + "name": "PERSCHIVL", + "description": "Periodic scheduling interval", + "bitOffset": "24", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DCTL", + "displayName": "OTG_HS_DCTL", + "description": "OTG_HS device control register", + "addressOffset": "0x4", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "RWUSIG", + "description": "Remote wakeup signaling", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "SDIS", + "description": "Soft disconnect", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "GINSTS", + "description": "Global IN NAK status", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "GONSTS", + "description": "Global OUT NAK status", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TCTL", + "description": "Test control", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-write" + }, + { + "name": "SGINAK", + "description": "Set global IN NAK", + "bitOffset": "7", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGINAK", + "description": "Clear global IN NAK", + "bitOffset": "8", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SGONAK", + "description": "Set global OUT NAK", + "bitOffset": "9", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "CGONAK", + "description": "Clear global OUT NAK", + "bitOffset": "10", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "POPRGDNE", + "description": "Power-on programming done", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DSTS", + "displayName": "OTG_HS_DSTS", + "description": "OTG_HS device status register", + "addressOffset": "0x8", + "size": "32", + "access": "read-only", + "resetValue": "0x00000010", + "fields": [ + { + "name": "SUSPSTS", + "description": "Suspend status", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ENUMSPD", + "description": "Enumerated speed", + "bitOffset": "1", + "bitWidth": "2" + }, + { + "name": "EERR", + "description": "Erratic error", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FNSOF", + "description": "Frame number of the received SOF", + "bitOffset": "8", + "bitWidth": "14" + } + ] + }, + { + "name": "OTG_HS_DIEPMSK", + "displayName": "OTG_HS_DIEPMSK", + "description": "OTG_HS device IN endpoint common interrupt mask register", + "addressOffset": "0x10", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPMSK", + "displayName": "OTG_HS_DOEPMSK", + "description": "OTG_HS device OUT endpoint common interrupt mask register", + "addressOffset": "0x14", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUPM", + "description": "SETUP phase done mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDM", + "description": "OUT token received when endpoint disabled mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "OPEM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BOIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DAINT", + "displayName": "OTG_HS_DAINT", + "description": "OTG_HS device all endpoints interrupt register", + "addressOffset": "0x18", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPINT", + "description": "IN endpoint interrupt bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPINT", + "description": "OUT endpoint interrupt bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DAINTMSK", + "displayName": "OTG_HS_DAINTMSK", + "description": "OTG_HS all endpoints interrupt mask register", + "addressOffset": "0x1C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEPM", + "description": "IN EP interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + }, + { + "name": "OEPM", + "description": "OUT EP interrupt mask bits", + "bitOffset": "16", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSDIS", + "displayName": "OTG_HS_DVBUSDIS", + "description": "OTG_HS device VBUS discharge time register", + "addressOffset": "0x28", + "size": "32", + "access": "read-write", + "resetValue": "0x000017D7", + "fields": [ + { + "name": "VBUSDT", + "description": "Device VBUS discharge time", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DVBUSPULSE", + "displayName": "OTG_HS_DVBUSPULSE", + "description": "OTG_HS device VBUS pulsing time register", + "addressOffset": "0x2C", + "size": "32", + "access": "read-write", + "resetValue": "0x000005B8", + "fields": [ + { + "name": "DVBUSP", + "description": "Device VBUS pulsing time", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "OTG_HS_DTHRCTL", + "displayName": "OTG_HS_DTHRCTL", + "description": "OTG_HS Device threshold control register", + "addressOffset": "0x30", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "NONISOTHREN", + "description": "Nonisochronous IN endpoints threshold enable", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "ISOTHREN", + "description": "ISO IN endpoint threshold enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TXTHRLEN", + "description": "Transmit threshold length", + "bitOffset": "2", + "bitWidth": "9" + }, + { + "name": "RXTHREN", + "description": "Receive threshold enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "RXTHRLEN", + "description": "Receive threshold length", + "bitOffset": "17", + "bitWidth": "9" + }, + { + "name": "ARPEN", + "description": "Arbiter parking enable", + "bitOffset": "27", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEMPMSK", + "displayName": "OTG_HS_DIEPEMPMSK", + "description": "OTG_HS device IN endpoint FIFO empty interrupt mask register", + "addressOffset": "0x34", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTXFEM", + "description": "IN EP Tx FIFO empty interrupt mask bits", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DEACHINT", + "displayName": "OTG_HS_DEACHINT", + "description": "OTG_HS device each endpoint interrupt register", + "addressOffset": "0x38", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INT", + "description": "IN endpoint 1interrupt bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INT", + "description": "OUT endpoint 1 interrupt bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DEACHINTMSK", + "displayName": "OTG_HS_DEACHINTMSK", + "description": "OTG_HS device each endpoint interrupt register mask", + "addressOffset": "0x3C", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "IEP1INTM", + "description": "IN Endpoint 1 interrupt mask bit", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OEP1INTM", + "description": "OUT Endpoint 1 interrupt mask bit", + "bitOffset": "17", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPEACHMSK1", + "displayName": "OTG_HS_DIEPEACHMSK1", + "description": "OTG_HS device each in endpoint-1 interrupt register", + "addressOffset": "0x40", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask (nonisochronous endpoints)", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "FIFO underrun mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPEACHMSK1", + "displayName": "OTG_HS_DOEPEACHMSK1", + "description": "OTG_HS device each OUT endpoint-1 interrupt register", + "addressOffset": "0x80", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRCM", + "description": "Transfer completed interrupt mask", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDM", + "description": "Endpoint disabled interrupt mask", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TOM", + "description": "Timeout condition mask", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "ITTXFEMSK", + "description": "IN token received when TxFIFO empty mask", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "INEPNMM", + "description": "IN token received with EP mismatch mask", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "INEPNEM", + "description": "IN endpoint NAK effective mask", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "TXFURM", + "description": "OUT packet error mask", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "BIM", + "description": "BNA interrupt mask", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "BERRM", + "description": "Bubble error interrupt mask", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "NAKM", + "description": "NAK interrupt mask", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "NYETM", + "description": "NYET interrupt mask", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL0", + "displayName": "OTG_HS_DIEPCTL0", + "description": "OTG device endpoint-0 control register", + "addressOffset": "0x100", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL1", + "displayName": "OTG_HS_DIEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x120", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL2", + "displayName": "OTG_HS_DIEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x140", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL3", + "displayName": "OTG_HS_DIEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x160", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL4", + "displayName": "OTG_HS_DIEPCTL4", + "description": "OTG device endpoint-4 control register", + "addressOffset": "0x180", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL5", + "displayName": "OTG_HS_DIEPCTL5", + "description": "OTG device endpoint-5 control register", + "addressOffset": "0x1A0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL6", + "displayName": "OTG_HS_DIEPCTL6", + "description": "OTG device endpoint-6 control register", + "addressOffset": "0x1C0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPCTL7", + "displayName": "OTG_HS_DIEPCTL7", + "description": "OTG device endpoint-7 control register", + "addressOffset": "0x1E0", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even/odd frame", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFNUM", + "description": "TxFIFO number", + "bitOffset": "22", + "bitWidth": "4", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT0", + "displayName": "OTG_HS_DIEPINT0", + "description": "OTG device endpoint-0 interrupt register", + "addressOffset": "0x108", + "size": "32", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT1", + "displayName": "OTG_HS_DIEPINT1", + "description": "OTG device endpoint-1 interrupt register", + "addressOffset": "0x128", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT2", + "displayName": "OTG_HS_DIEPINT2", + "description": "OTG device endpoint-2 interrupt register", + "addressOffset": "0x148", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT3", + "displayName": "OTG_HS_DIEPINT3", + "description": "OTG device endpoint-3 interrupt register", + "addressOffset": "0x168", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT4", + "displayName": "OTG_HS_DIEPINT4", + "description": "OTG device endpoint-4 interrupt register", + "addressOffset": "0x188", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT5", + "displayName": "OTG_HS_DIEPINT5", + "description": "OTG device endpoint-5 interrupt register", + "addressOffset": "0x1A8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT6", + "displayName": "OTG_HS_DIEPINT6", + "description": "OTG device endpoint-6 interrupt register", + "addressOffset": "0x1C8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPINT7", + "displayName": "OTG_HS_DIEPINT7", + "description": "OTG device endpoint-7 interrupt register", + "addressOffset": "0x1E8", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TOC", + "description": "Timeout condition", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ITTXFE", + "description": "IN token received when TxFIFO is empty", + "bitOffset": "4", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "INEPNE", + "description": "IN endpoint NAK effective", + "bitOffset": "6", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "TXFE", + "description": "Transmit FIFO empty", + "bitOffset": "7", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "TXFIFOUDRN", + "description": "Transmit Fifo Underrun", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BNA", + "description": "Buffer not available interrupt", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PKTDRPSTS", + "description": "Packet dropped status", + "bitOffset": "11", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BERR", + "description": "Babble error interrupt", + "bitOffset": "12", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "NAK", + "description": "NAK interrupt", + "bitOffset": "13", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ0", + "displayName": "OTG_HS_DIEPTSIZ0", + "description": "OTG_HS device IN endpoint 0 transfer size register", + "addressOffset": "0x110", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA1", + "displayName": "OTG_HS_DIEPDMA1", + "description": "OTG_HS device endpoint-1 DMA address register", + "addressOffset": "0x114", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA2", + "displayName": "OTG_HS_DIEPDMA2", + "description": "OTG_HS device endpoint-2 DMA address register", + "addressOffset": "0x134", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA3", + "displayName": "OTG_HS_DIEPDMA3", + "description": "OTG_HS device endpoint-3 DMA address register", + "addressOffset": "0x154", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA4", + "displayName": "OTG_HS_DIEPDMA4", + "description": "OTG_HS device endpoint-4 DMA address register", + "addressOffset": "0x174", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DIEPDMA5", + "displayName": "OTG_HS_DIEPDMA5", + "description": "OTG_HS device endpoint-5 DMA address register", + "addressOffset": "0x194", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "DMAADDR", + "description": "DMA address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS0", + "displayName": "OTG_HS_DTXFSTS0", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x118", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS1", + "displayName": "OTG_HS_DTXFSTS1", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x138", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS2", + "displayName": "OTG_HS_DTXFSTS2", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x158", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS3", + "displayName": "OTG_HS_DTXFSTS3", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x178", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS4", + "displayName": "OTG_HS_DTXFSTS4", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x198", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DTXFSTS5", + "displayName": "OTG_HS_DTXFSTS5", + "description": "OTG_HS device IN endpoint transmit FIFO status register", + "addressOffset": "0x1B8", + "size": "32", + "access": "read-only", + "resetValue": "0x0", + "fields": [ + { + "name": "INEPTFSAV", + "description": "IN endpoint TxFIFO space avail", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ1", + "displayName": "OTG_HS_DIEPTSIZ1", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x130", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ2", + "displayName": "OTG_HS_DIEPTSIZ2", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x150", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ3", + "displayName": "OTG_HS_DIEPTSIZ3", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x170", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ4", + "displayName": "OTG_HS_DIEPTSIZ4", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x190", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DIEPTSIZ5", + "displayName": "OTG_HS_DIEPTSIZ5", + "description": "OTG_HS device endpoint transfer size register", + "addressOffset": "0x1B0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "MCNT", + "description": "Multi count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL0", + "displayName": "OTG_HS_DOEPCTL0", + "description": "OTG_HS device control OUT endpoint 0 control register", + "addressOffset": "0x300", + "size": "32", + "resetValue": "0x00008000", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-only" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "write-only" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL1", + "displayName": "OTG_HS_DOEPCTL1", + "description": "OTG device endpoint-1 control register", + "addressOffset": "0x320", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL2", + "displayName": "OTG_HS_DOEPCTL2", + "description": "OTG device endpoint-2 control register", + "addressOffset": "0x340", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPCTL3", + "displayName": "OTG_HS_DOEPCTL3", + "description": "OTG device endpoint-3 control register", + "addressOffset": "0x360", + "size": "32", + "resetValue": "0x0", + "fields": [ + { + "name": "MPSIZ", + "description": "Maximum packet size", + "bitOffset": "0", + "bitWidth": "11", + "access": "read-write" + }, + { + "name": "USBAEP", + "description": "USB active endpoint", + "bitOffset": "15", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EONUM_DPID", + "description": "Even odd frame/Endpoint data PID", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "NAKSTS", + "description": "NAK status", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EPTYP", + "description": "Endpoint type", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + }, + { + "name": "SNPM", + "description": "Snoop mode", + "bitOffset": "20", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "Stall", + "description": "STALL handshake", + "bitOffset": "21", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "CNAK", + "description": "Clear NAK", + "bitOffset": "26", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SNAK", + "description": "Set NAK", + "bitOffset": "27", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SD0PID_SEVNFRM", + "description": "Set DATA0 PID/Set even frame", + "bitOffset": "28", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "SODDFRM", + "description": "Set odd frame", + "bitOffset": "29", + "bitWidth": "1", + "access": "write-only" + }, + { + "name": "EPDIS", + "description": "Endpoint disable", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "EPENA", + "description": "Endpoint enable", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "OTG_HS_DOEPINT0", + "displayName": "OTG_HS_DOEPINT0", + "description": "OTG_HS device endpoint-0 interrupt register", + "addressOffset": "0x308", + "size": "32", + "access": "read-write", + "resetValue": "0x00000080", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT1", + "displayName": "OTG_HS_DOEPINT1", + "description": "OTG_HS device endpoint-1 interrupt register", + "addressOffset": "0x328", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT2", + "displayName": "OTG_HS_DOEPINT2", + "description": "OTG_HS device endpoint-2 interrupt register", + "addressOffset": "0x348", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT3", + "displayName": "OTG_HS_DOEPINT3", + "description": "OTG_HS device endpoint-3 interrupt register", + "addressOffset": "0x368", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT4", + "displayName": "OTG_HS_DOEPINT4", + "description": "OTG_HS device endpoint-4 interrupt register", + "addressOffset": "0x388", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT5", + "displayName": "OTG_HS_DOEPINT5", + "description": "OTG_HS device endpoint-5 interrupt register", + "addressOffset": "0x3A8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT6", + "displayName": "OTG_HS_DOEPINT6", + "description": "OTG_HS device endpoint-6 interrupt register", + "addressOffset": "0x3C8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPINT7", + "displayName": "OTG_HS_DOEPINT7", + "description": "OTG_HS device endpoint-7 interrupt register", + "addressOffset": "0x3E8", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRC", + "description": "Transfer completed interrupt", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "EPDISD", + "description": "Endpoint disabled interrupt", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "STUP", + "description": "SETUP phase done", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "OTEPDIS", + "description": "OUT token received when endpoint disabled", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "B2BSTUP", + "description": "Back-to-back SETUP packets received", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "NYET", + "description": "NYET interrupt", + "bitOffset": "14", + "bitWidth": "1" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ0", + "displayName": "OTG_HS_DOEPTSIZ0", + "description": "OTG_HS device endpoint-1 transfer size register", + "addressOffset": "0x310", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "7" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "STUPCNT", + "description": "SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ1", + "displayName": "OTG_HS_DOEPTSIZ1", + "description": "OTG_HS device endpoint-2 transfer size register", + "addressOffset": "0x330", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ2", + "displayName": "OTG_HS_DOEPTSIZ2", + "description": "OTG_HS device endpoint-3 transfer size register", + "addressOffset": "0x350", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ3", + "displayName": "OTG_HS_DOEPTSIZ3", + "description": "OTG_HS device endpoint-4 transfer size register", + "addressOffset": "0x370", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + }, + { + "name": "OTG_HS_DOEPTSIZ4", + "displayName": "OTG_HS_DOEPTSIZ4", + "description": "OTG_HS device endpoint-5 transfer size register", + "addressOffset": "0x390", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "XFRSIZ", + "description": "Transfer size", + "bitOffset": "0", + "bitWidth": "19" + }, + { + "name": "PKTCNT", + "description": "Packet count", + "bitOffset": "19", + "bitWidth": "10" + }, + { + "name": "RXDPID_STUPCNT", + "description": "Received data PID/SETUP packet count", + "bitOffset": "29", + "bitWidth": "2" + } + ] + } + ] + }, + { + "name": "OTG_HS_PWRCLK", + "description": "USB on the go high speed", + "groupName": "USB_OTG_HS", + "baseAddress": "0x40040E00", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x3F200", + "usage": "registers" + } + ], + "registers": [ + { + "name": "OTG_HS_PCGCR", + "displayName": "OTG_HS_PCGCR", + "description": "Power and clock gating control register", + "addressOffset": "0x0", + "size": "32", + "access": "read-write", + "resetValue": "0x0", + "fields": [ + { + "name": "STPPCLK", + "description": "Stop PHY clock", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "GATEHCLK", + "description": "Gate HCLK", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "PHYSUSP", + "description": "PHY suspended", + "bitOffset": "4", + "bitWidth": "1" + } + ] + } + ] + }, + { + "name": "LTDC", + "description": "LCD-TFT Controller", + "groupName": "LTDC", + "baseAddress": "0x40016800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "LCD_TFT", + "description": "LTDC global interrupt", + "value": "88" + }, + { + "name": "LCD_TFT_1", + "description": "LTDC global error interrupt", + "value": "89" + } + ], + "registers": [ + { + "name": "SSCR", + "displayName": "SSCR", + "description": "Synchronization Size Configuration Register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "HSW", + "description": "Horizontal Synchronization Width (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "VSH", + "description": "Vertical Synchronization Height (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "BPCR", + "displayName": "BPCR", + "description": "Back Porch Configuration Register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AHBP", + "description": "Accumulated Horizontal back porch (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "AVBP", + "description": "Accumulated Vertical back porch (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "AWCR", + "displayName": "AWCR", + "description": "Active Width Configuration Register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "AAW", + "description": "Accumulated Active Width (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "AAH", + "description": "Accumulated Active Height (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "TWCR", + "displayName": "TWCR", + "description": "Total Width Configuration Register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "TOTALW", + "description": "Total Width (in units of pixel clock period)", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "TOTALH", + "description": "Total Height (in units of horizontal scan line)", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "GCR", + "displayName": "GCR", + "description": "Global Control Register", + "addressOffset": "0x18", + "size": "0x20", + "resetValue": "0x00002220", + "fields": [ + { + "name": "HSPOL", + "description": "Horizontal Synchronization Polarity", + "bitOffset": "31", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VSPOL", + "description": "Vertical Synchronization Polarity", + "bitOffset": "30", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DEPOL", + "description": "Data Enable Polarity", + "bitOffset": "29", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "PCPOL", + "description": "Pixel Clock Polarity", + "bitOffset": "28", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DEN", + "description": "Dither Enable", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "DRW", + "description": "Dither Red Width", + "bitOffset": "12", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DGW", + "description": "Dither Green Width", + "bitOffset": "8", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "DBW", + "description": "Dither Blue Width", + "bitOffset": "4", + "bitWidth": "3", + "access": "read-only" + }, + { + "name": "LTDCEN", + "description": "LCD-TFT controller enable bit", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-write" + } + ] + }, + { + "name": "SRCR", + "displayName": "SRCR", + "description": "Shadow Reload Configuration Register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "VBR", + "description": "Vertical Blanking Reload", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "IMR", + "description": "Immediate Reload", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BCCR", + "displayName": "BCCR", + "description": "Background Color Configuration Register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "BC", + "description": "Background Color Red value", + "bitOffset": "0", + "bitWidth": "24" + } + ] + }, + { + "name": "IER", + "displayName": "IER", + "description": "Interrupt Enable Register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RRIE", + "description": "Register Reload interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TERRIE", + "description": "Transfer Error Interrupt Enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FUIE", + "description": "FIFO Underrun Interrupt Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LIE", + "description": "Line Interrupt Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt Status Register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RRIF", + "description": "Register Reload Interrupt Flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TERRIF", + "description": "Transfer Error interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "FUIF", + "description": "FIFO Underrun Interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LIF", + "description": "Line Interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ICR", + "displayName": "ICR", + "description": "Interrupt Clear Register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CRRIF", + "description": "Clears Register Reload Interrupt Flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTERRIF", + "description": "Clears the Transfer Error Interrupt Flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CFUIF", + "description": "Clears the FIFO Underrun Interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CLIF", + "description": "Clears the Line Interrupt Flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "LIPCR", + "displayName": "LIPCR", + "description": "Line Interrupt Position Configuration Register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LIPOS", + "description": "Line Interrupt Position", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "CPSR", + "displayName": "CPSR", + "description": "Current Position Status Register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CXPOS", + "description": "Current X Position", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "CYPOS", + "description": "Current Y Position", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "CDSR", + "displayName": "CDSR", + "description": "Current Display Status Register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-only", + "resetValue": "0x0000000F", + "fields": [ + { + "name": "HSYNCS", + "description": "Horizontal Synchronization display Status", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "VSYNCS", + "description": "Vertical Synchronization display Status", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "HDES", + "description": "Horizontal Data Enable display Status", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "VDES", + "description": "Vertical Data Enable display Status", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "L1CR", + "displayName": "L1CR", + "description": "Layerx Control Register", + "addressOffset": "0x84", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLUTEN", + "description": "Color Look-Up Table Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COLKEN", + "description": "Color Keying Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LEN", + "description": "Layer Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "L1WHPCR", + "displayName": "L1WHPCR", + "description": "Layerx Window Horizontal Position Configuration Register", + "addressOffset": "0x88", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WHSPPOS", + "description": "Window Horizontal Stop Position", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "WHSTPOS", + "description": "Window Horizontal Start Position", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "L1WVPCR", + "displayName": "L1WVPCR", + "description": "Layerx Window Vertical Position Configuration Register", + "addressOffset": "0x8C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WVSPPOS", + "description": "Window Vertical Stop Position", + "bitOffset": "16", + "bitWidth": "11" + }, + { + "name": "WVSTPOS", + "description": "Window Vertical Start Position", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "L1CKCR", + "displayName": "L1CKCR", + "description": "Layerx Color Keying Configuration Register", + "addressOffset": "0x90", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CKRED", + "description": "Color Key Red value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "CKGREEN", + "description": "Color Key Green value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "CKBLUE", + "description": "Color Key Blue value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L1PFCR", + "displayName": "L1PFCR", + "description": "Layerx Pixel Format Configuration Register", + "addressOffset": "0x94", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PF", + "description": "Pixel Format", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "L1CACR", + "displayName": "L1CACR", + "description": "Layerx Constant Alpha Configuration Register", + "addressOffset": "0x98", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CONSTA", + "description": "Constant Alpha", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L1DCCR", + "displayName": "L1DCCR", + "description": "Layerx Default Color Configuration Register", + "addressOffset": "0x9C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCALPHA", + "description": "Default Color Alpha", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DCRED", + "description": "Default Color Red", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DCGREEN", + "description": "Default Color Green", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DCBLUE", + "description": "Default Color Blue", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L1BFCR", + "displayName": "L1BFCR", + "description": "Layerx Blending Factors Configuration Register", + "addressOffset": "0xA0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000607", + "fields": [ + { + "name": "BF1", + "description": "Blending Factor 1", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "BF2", + "description": "Blending Factor 2", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "L1CFBAR", + "displayName": "L1CFBAR", + "description": "Layerx Color Frame Buffer Address Register", + "addressOffset": "0xAC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBADD", + "description": "Color Frame Buffer Start Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "L1CFBLR", + "displayName": "L1CFBLR", + "description": "Layerx Color Frame Buffer Length Register", + "addressOffset": "0xB0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBP", + "description": "Color Frame Buffer Pitch in bytes", + "bitOffset": "16", + "bitWidth": "13" + }, + { + "name": "CFBLL", + "description": "Color Frame Buffer Line Length", + "bitOffset": "0", + "bitWidth": "13" + } + ] + }, + { + "name": "L1CFBLNR", + "displayName": "L1CFBLNR", + "description": "Layerx ColorFrame Buffer Line Number Register", + "addressOffset": "0xB4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBLNBR", + "description": "Frame Buffer Line Number", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "L1CLUTWR", + "displayName": "L1CLUTWR", + "description": "Layerx CLUT Write Register", + "addressOffset": "0xC4", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLUTADD", + "description": "CLUT Address", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BLUE", + "description": "Blue value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L2CR", + "displayName": "L2CR", + "description": "Layerx Control Register", + "addressOffset": "0x104", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLUTEN", + "description": "Color Look-Up Table Enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "COLKEN", + "description": "Color Keying Enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "LEN", + "description": "Layer Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "L2WHPCR", + "displayName": "L2WHPCR", + "description": "Layerx Window Horizontal Position Configuration Register", + "addressOffset": "0x108", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WHSPPOS", + "description": "Window Horizontal Stop Position", + "bitOffset": "16", + "bitWidth": "12" + }, + { + "name": "WHSTPOS", + "description": "Window Horizontal Start Position", + "bitOffset": "0", + "bitWidth": "12" + } + ] + }, + { + "name": "L2WVPCR", + "displayName": "L2WVPCR", + "description": "Layerx Window Vertical Position Configuration Register", + "addressOffset": "0x10C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WVSPPOS", + "description": "Window Vertical Stop Position", + "bitOffset": "16", + "bitWidth": "11" + }, + { + "name": "WVSTPOS", + "description": "Window Vertical Start Position", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "L2CKCR", + "displayName": "L2CKCR", + "description": "Layerx Color Keying Configuration Register", + "addressOffset": "0x110", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CKRED", + "description": "Color Key Red value", + "bitOffset": "15", + "bitWidth": "9" + }, + { + "name": "CKGREEN", + "description": "Color Key Green value", + "bitOffset": "8", + "bitWidth": "7" + }, + { + "name": "CKBLUE", + "description": "Color Key Blue value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L2PFCR", + "displayName": "L2PFCR", + "description": "Layerx Pixel Format Configuration Register", + "addressOffset": "0x114", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PF", + "description": "Pixel Format", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "L2CACR", + "displayName": "L2CACR", + "description": "Layerx Constant Alpha Configuration Register", + "addressOffset": "0x118", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CONSTA", + "description": "Constant Alpha", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L2DCCR", + "displayName": "L2DCCR", + "description": "Layerx Default Color Configuration Register", + "addressOffset": "0x11C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DCALPHA", + "description": "Default Color Alpha", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "DCRED", + "description": "Default Color Red", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "DCGREEN", + "description": "Default Color Green", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "DCBLUE", + "description": "Default Color Blue", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "L2BFCR", + "displayName": "L2BFCR", + "description": "Layerx Blending Factors Configuration Register", + "addressOffset": "0x120", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000607", + "fields": [ + { + "name": "BF1", + "description": "Blending Factor 1", + "bitOffset": "8", + "bitWidth": "3" + }, + { + "name": "BF2", + "description": "Blending Factor 2", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "L2CFBAR", + "displayName": "L2CFBAR", + "description": "Layerx Color Frame Buffer Address Register", + "addressOffset": "0x12C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBADD", + "description": "Color Frame Buffer Start Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "L2CFBLR", + "displayName": "L2CFBLR", + "description": "Layerx Color Frame Buffer Length Register", + "addressOffset": "0x130", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBP", + "description": "Color Frame Buffer Pitch in bytes", + "bitOffset": "16", + "bitWidth": "13" + }, + { + "name": "CFBLL", + "description": "Color Frame Buffer Line Length", + "bitOffset": "0", + "bitWidth": "13" + } + ] + }, + { + "name": "L2CFBLNR", + "displayName": "L2CFBLNR", + "description": "Layerx ColorFrame Buffer Line Number Register", + "addressOffset": "0x134", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CFBLNBR", + "description": "Frame Buffer Line Number", + "bitOffset": "0", + "bitWidth": "11" + } + ] + }, + { + "name": "L2CLUTWR", + "displayName": "L2CLUTWR", + "description": "Layerx CLUT Write Register", + "addressOffset": "0x144", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CLUTADD", + "description": "CLUT Address", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BLUE", + "description": "Blue value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "SAI", + "description": "Serial audio interface", + "groupName": "SAI", + "baseAddress": "0x40015800", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "SAI1", + "description": "SAI1 global interrupt", + "value": "87" + } + ], + "registers": [ + { + "name": "BCR1", + "displayName": "BCR1", + "description": "BConfiguration register 1", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000040", + "fields": [ + { + "name": "MCJDIV", + "description": "Master clock divider", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "NODIV", + "description": "No divider", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SAIBEN", + "description": "Audio block B enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "OutDri", + "description": "Output drive", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MONO", + "description": "Mono mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE", + "description": "Audio block mode", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "BCR2", + "displayName": "BCR2", + "description": "BConfiguration register 2", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COMP", + "description": "Companding mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "CPL", + "description": "Complement bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MUTECN", + "description": "Mute counter", + "bitOffset": "7", + "bitWidth": "6" + }, + { + "name": "MUTEVAL", + "description": "Mute value", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MUTE", + "description": "Mute", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRIS", + "description": "Tristate management on data line", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFLUS", + "description": "FIFO flush", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FTH", + "description": "FIFO threshold", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "BFRCR", + "displayName": "BFRCR", + "description": "BFRCR", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000007", + "fields": [ + { + "name": "FSOFF", + "description": "Frame synchronization offset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length", + "bitOffset": "8", + "bitWidth": "7" + }, + { + "name": "FRL", + "description": "Frame length", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BSLOTR", + "displayName": "BSLOTR", + "description": "BSlot register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLOTEN", + "description": "Slot enable", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "SLOTSZ", + "description": "Slot size", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "FBOFF", + "description": "First bit offset", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "BIM", + "displayName": "BIM", + "description": "BInterrupt mask register2", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LFSDETIE", + "description": "Late frame synchronization detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BSR", + "displayName": "BSR", + "description": "BStatus register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FLVL", + "description": "FIFO level threshold", + "bitOffset": "16", + "bitWidth": "3" + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Codec not ready", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "FIFO request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OVRUDR", + "description": "Overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BCLRFR", + "displayName": "BCLRFR", + "description": "BClear flag register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "write-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LFSDET", + "description": "Clear late frame synchronization detection flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Clear codec not ready flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Clear wrong clock configuration flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OVRUDR", + "description": "Clear overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "BDR", + "displayName": "BDR", + "description": "BData register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "ACR1", + "displayName": "ACR1", + "description": "AConfiguration register 1", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000040", + "fields": [ + { + "name": "MCJDIV", + "description": "Master clock divider", + "bitOffset": "20", + "bitWidth": "4" + }, + { + "name": "NODIV", + "description": "No divider", + "bitOffset": "19", + "bitWidth": "1" + }, + { + "name": "DMAEN", + "description": "DMA enable", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "SAIAEN", + "description": "Audio block A enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "OutDri", + "description": "Output drive", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MONO", + "description": "Mono mode", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable", + "bitOffset": "10", + "bitWidth": "2" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "DS", + "description": "Data size", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration", + "bitOffset": "2", + "bitWidth": "2" + }, + { + "name": "MODE", + "description": "Audio block mode", + "bitOffset": "0", + "bitWidth": "2" + } + ] + }, + { + "name": "ACR2", + "displayName": "ACR2", + "description": "AConfiguration register 2", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "COMP", + "description": "Companding mode", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "CPL", + "description": "Complement bit", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "MUTECN", + "description": "Mute counter", + "bitOffset": "7", + "bitWidth": "6" + }, + { + "name": "MUTEVAL", + "description": "Mute value", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "MUTE", + "description": "Mute", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "TRIS", + "description": "Tristate management on data line", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FFLUS", + "description": "FIFO flush", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "FTH", + "description": "FIFO threshold", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "AFRCR", + "displayName": "AFRCR", + "description": "AFRCR", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000007", + "fields": [ + { + "name": "FSOFF", + "description": "Frame synchronization offset", + "bitOffset": "18", + "bitWidth": "1" + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length", + "bitOffset": "8", + "bitWidth": "7" + }, + { + "name": "FRL", + "description": "Frame length", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "ASLOTR", + "displayName": "ASLOTR", + "description": "ASlot register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "SLOTEN", + "description": "Slot enable", + "bitOffset": "16", + "bitWidth": "16" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame", + "bitOffset": "8", + "bitWidth": "4" + }, + { + "name": "SLOTSZ", + "description": "Slot size", + "bitOffset": "6", + "bitWidth": "2" + }, + { + "name": "FBOFF", + "description": "First bit offset", + "bitOffset": "0", + "bitWidth": "5" + } + ] + }, + { + "name": "AIM", + "displayName": "AIM", + "description": "AInterrupt mask register2", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LFSDET", + "description": "Late frame synchronization detection interrupt enable", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration interrupt enable", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection interrupt enable", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ASR", + "displayName": "ASR", + "description": "AStatus register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "FLVL", + "description": "FIFO level threshold", + "bitOffset": "16", + "bitWidth": "3" + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Codec not ready", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "FREQ", + "description": "FIFO request", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag. This bit is read only.", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OVRUDR", + "description": "Overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ACLRFR", + "displayName": "ACLRFR", + "description": "AClear flag register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LFSDET", + "description": "Clear late frame synchronization detection flag", + "bitOffset": "6", + "bitWidth": "1" + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag.", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CNRDY", + "description": "Clear codec not ready flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "WCKCFG", + "description": "Clear wrong clock configuration flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "MUTEDET", + "description": "Mute detection flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "OVRUDR", + "description": "Clear overrun / underrun", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ADR", + "displayName": "ADR", + "description": "AData register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DATA", + "description": "Data", + "bitOffset": "0", + "bitWidth": "32" + } + ] + } + ] + }, + { + "name": "DMA2D", + "description": "DMA2D controller", + "groupName": "DMA2D", + "baseAddress": "0x4002B000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0xC00", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "DMA2D", + "description": "DMA2D global interrupt", + "value": "90" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MODE", + "description": "DMA2D mode", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CEIE", + "description": "Configuration Error Interrupt Enable", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "CTCIE", + "description": "CLUT transfer complete interrupt enable", + "bitOffset": "12", + "bitWidth": "1" + }, + { + "name": "CAEIE", + "description": "CLUT access error interrupt enable", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "TWIE", + "description": "Transfer watermark interrupt enable", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "TCIE", + "description": "Transfer complete interrupt enable", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "TEIE", + "description": "Transfer error interrupt enable", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "ABORT", + "description": "Abort", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "SUSP", + "description": "Suspend", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "START", + "description": "Start", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "ISR", + "displayName": "ISR", + "description": "Interrupt Status Register", + "addressOffset": "0x4", + "size": "0x20", + "access": "read-only", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CEIF", + "description": "Configuration error interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CTCIF", + "description": "CLUT transfer complete interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CAEIF", + "description": "CLUT access error interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "TWIF", + "description": "Transfer watermark interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "TCIF", + "description": "Transfer complete interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "TEIF", + "description": "Transfer error interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "IFCR", + "displayName": "IFCR", + "description": "Interrupt flag clear register", + "addressOffset": "0x8", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CCEIF", + "description": "Clear configuration error interrupt flag", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CCTCIF", + "description": "Clear CLUT transfer complete interrupt flag", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CAECIF", + "description": "Clear CLUT access error interrupt flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "CTWIF", + "description": "Clear transfer watermark interrupt flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CTCIF", + "description": "Clear transfer complete interrupt flag", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CTEIF", + "description": "Clear Transfer error interrupt flag", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "FGMAR", + "displayName": "FGMAR", + "description": "Foreground memory address register", + "addressOffset": "0xC", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "FGOR", + "displayName": "FGOR", + "description": "Foreground offset register", + "addressOffset": "0x10", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LO", + "description": "Line offset", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "BGMAR", + "displayName": "BGMAR", + "description": "Background memory address register", + "addressOffset": "0x14", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BGOR", + "displayName": "BGOR", + "description": "Background offset register", + "addressOffset": "0x18", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LO", + "description": "Line offset", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "FGPFCCR", + "displayName": "FGPFCCR", + "description": "Foreground PFC control register", + "addressOffset": "0x1C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALPHA", + "description": "Alpha value", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "AM", + "description": "Alpha mode", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CS", + "description": "CLUT size", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "START", + "description": "Start", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CCM", + "description": "CLUT color mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CM", + "description": "Color mode", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "FGCOLR", + "displayName": "FGCOLR", + "description": "Foreground color register", + "addressOffset": "0x20", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RED", + "description": "Red Value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green Value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BLUE", + "description": "Blue Value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BGPFCCR", + "displayName": "BGPFCCR", + "description": "Background PFC control register", + "addressOffset": "0x24", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "ALPHA", + "description": "Alpha value", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "AM", + "description": "Alpha mode", + "bitOffset": "16", + "bitWidth": "2" + }, + { + "name": "CS", + "description": "CLUT size", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "START", + "description": "Start", + "bitOffset": "5", + "bitWidth": "1" + }, + { + "name": "CCM", + "description": "CLUT Color mode", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "CM", + "description": "Color mode", + "bitOffset": "0", + "bitWidth": "4" + } + ] + }, + { + "name": "BGCOLR", + "displayName": "BGCOLR", + "description": "Background color register", + "addressOffset": "0x28", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "RED", + "description": "Red Value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green Value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BLUE", + "description": "Blue Value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "FGCMAR", + "displayName": "FGCMAR", + "description": "Foreground CLUT memory address register", + "addressOffset": "0x2C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "BGCMAR", + "displayName": "BGCMAR", + "description": "Background CLUT memory address register", + "addressOffset": "0x30", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OPFCCR", + "displayName": "OPFCCR", + "description": "Output PFC control register", + "addressOffset": "0x34", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "CM", + "description": "Color mode", + "bitOffset": "0", + "bitWidth": "3" + } + ] + }, + { + "name": "OCOLR", + "displayName": "OCOLR", + "description": "Output color register", + "addressOffset": "0x38", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "APLHA", + "description": "Alpha Channel Value", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "Red Value", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "Green Value", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BLUE", + "description": "Blue Value", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "OMAR", + "displayName": "OMAR", + "description": "Output memory address register", + "addressOffset": "0x3C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "MA", + "description": "Memory Address", + "bitOffset": "0", + "bitWidth": "32" + } + ] + }, + { + "name": "OOR", + "displayName": "OOR", + "description": "Output offset register", + "addressOffset": "0x40", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LO", + "description": "Line Offset", + "bitOffset": "0", + "bitWidth": "14" + } + ] + }, + { + "name": "NLR", + "displayName": "NLR", + "description": "Number of line register", + "addressOffset": "0x44", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "PL", + "description": "Pixel per lines", + "bitOffset": "16", + "bitWidth": "14" + }, + { + "name": "NL", + "description": "Number of lines", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "LWR", + "displayName": "LWR", + "description": "Line watermark register", + "addressOffset": "0x48", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "LW", + "description": "Line watermark", + "bitOffset": "0", + "bitWidth": "16" + } + ] + }, + { + "name": "AMTCR", + "displayName": "AMTCR", + "description": "AHB master timer configuration register", + "addressOffset": "0x4C", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "DT", + "description": "Dead Time", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "EN", + "description": "Enable", + "bitOffset": "0", + "bitWidth": "1" + } + ] + }, + { + "name": "FGCLUT", + "displayName": "FGCLUT", + "description": "FGCLUT", + "addressOffset": "0x400", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "APLHA", + "description": "APLHA", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "RED", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "GREEN", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BLUE", + "description": "BLUE", + "bitOffset": "0", + "bitWidth": "8" + } + ] + }, + { + "name": "BGCLUT", + "displayName": "BGCLUT", + "description": "BGCLUT", + "addressOffset": "0x800", + "size": "0x20", + "access": "read-write", + "resetValue": "0x00000000", + "fields": [ + { + "name": "APLHA", + "description": "APLHA", + "bitOffset": "24", + "bitWidth": "8" + }, + { + "name": "RED", + "description": "RED", + "bitOffset": "16", + "bitWidth": "8" + }, + { + "name": "GREEN", + "description": "GREEN", + "bitOffset": "8", + "bitWidth": "8" + }, + { + "name": "BLUE", + "description": "BLUE", + "bitOffset": "0", + "bitWidth": "8" + } + ] + } + ] + }, + { + "name": "PWR", + "description": "Power control", + "groupName": "PWR", + "baseAddress": "0x40007000", + "addressBlocks": [ + { + "offset": "0x0", + "size": "0x400", + "usage": "registers" + } + ], + "interrupts": [ + { + "name": "PVD", + "description": "PVD through EXTI line detection interrupt", + "value": "1" + } + ], + "registers": [ + { + "name": "CR", + "displayName": "CR", + "description": "Power control register", + "addressOffset": "0x0", + "size": "0x20", + "access": "read-write", + "resetValue": "0x0000C000", + "fields": [ + { + "name": "LPDS", + "description": "Low-power deep sleep", + "bitOffset": "0", + "bitWidth": "1" + }, + { + "name": "PDDS", + "description": "Power down deepsleep", + "bitOffset": "1", + "bitWidth": "1" + }, + { + "name": "CWUF", + "description": "Clear wakeup flag", + "bitOffset": "2", + "bitWidth": "1" + }, + { + "name": "CSBF", + "description": "Clear standby flag", + "bitOffset": "3", + "bitWidth": "1" + }, + { + "name": "PVDE", + "description": "Power voltage detector enable", + "bitOffset": "4", + "bitWidth": "1" + }, + { + "name": "PLS", + "description": "PVD level selection", + "bitOffset": "5", + "bitWidth": "3" + }, + { + "name": "DBP", + "description": "Disable backup domain write protection", + "bitOffset": "8", + "bitWidth": "1" + }, + { + "name": "FPDS", + "description": "Flash power down in Stop mode", + "bitOffset": "9", + "bitWidth": "1" + }, + { + "name": "LPUDS", + "description": "Low-Power Regulator Low Voltage in deepsleep", + "bitOffset": "10", + "bitWidth": "1" + }, + { + "name": "MRUDS", + "description": "Main regulator low voltage in deepsleep mode", + "bitOffset": "11", + "bitWidth": "1" + }, + { + "name": "ADCDC1", + "description": "ADCDC1", + "bitOffset": "13", + "bitWidth": "1" + }, + { + "name": "VOS", + "description": "Regulator voltage scaling output selection", + "bitOffset": "14", + "bitWidth": "2" + }, + { + "name": "ODEN", + "description": "Over-drive enable", + "bitOffset": "16", + "bitWidth": "1" + }, + { + "name": "ODSWEN", + "description": "Over-drive switching enabled", + "bitOffset": "17", + "bitWidth": "1" + }, + { + "name": "UDEN", + "description": "Under-drive enable in stop mode", + "bitOffset": "18", + "bitWidth": "2" + } + ] + }, + { + "name": "CSR", + "displayName": "CSR", + "description": "Power control/status register", + "addressOffset": "0x4", + "size": "0x20", + "resetValue": "0x00000000", + "fields": [ + { + "name": "WUF", + "description": "Wakeup flag", + "bitOffset": "0", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "SBF", + "description": "Standby flag", + "bitOffset": "1", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "PVDO", + "description": "PVD output", + "bitOffset": "2", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "BRR", + "description": "Backup regulator ready", + "bitOffset": "3", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "EWUP", + "description": "Enable WKUP pin", + "bitOffset": "8", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "BRE", + "description": "Backup regulator enable", + "bitOffset": "9", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "VOSRDY", + "description": "Regulator voltage scaling output selection ready bit", + "bitOffset": "14", + "bitWidth": "1", + "access": "read-write" + }, + { + "name": "ODRDY", + "description": "Over-drive mode ready", + "bitOffset": "16", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "ODSWRDY", + "description": "Over-drive mode switching ready", + "bitOffset": "17", + "bitWidth": "1", + "access": "read-only" + }, + { + "name": "UDRDY", + "description": "Under-drive ready flag", + "bitOffset": "18", + "bitWidth": "2", + "access": "read-write" + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/adc1.c b/gnu-mcu-eclipse/devices/support/STM32F429x/adc1.c new file mode 100644 index 0000000000..d05f38927c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/adc1.c @@ -0,0 +1,366 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smpr1 = cm_object_get_child_by_name(obj, "SMPR1"); + state->u.f4.reg.smpr2 = cm_object_get_child_by_name(obj, "SMPR2"); + state->u.f4.reg.jofr1 = cm_object_get_child_by_name(obj, "JOFR1"); + state->u.f4.reg.jofr2 = cm_object_get_child_by_name(obj, "JOFR2"); + state->u.f4.reg.jofr3 = cm_object_get_child_by_name(obj, "JOFR3"); + state->u.f4.reg.jofr4 = cm_object_get_child_by_name(obj, "JOFR4"); + state->u.f4.reg.htr = cm_object_get_child_by_name(obj, "HTR"); + state->u.f4.reg.ltr = cm_object_get_child_by_name(obj, "LTR"); + state->u.f4.reg.sqr1 = cm_object_get_child_by_name(obj, "SQR1"); + state->u.f4.reg.sqr2 = cm_object_get_child_by_name(obj, "SQR2"); + state->u.f4.reg.sqr3 = cm_object_get_child_by_name(obj, "SQR3"); + state->u.f4.reg.jsqr = cm_object_get_child_by_name(obj, "JSQR"); + state->u.f4.reg.jdr1 = cm_object_get_child_by_name(obj, "JDR1"); + state->u.f4.reg.jdr2 = cm_object_get_child_by_name(obj, "JDR2"); + state->u.f4.reg.jdr3 = cm_object_get_child_by_name(obj, "JDR3"); + state->u.f4.reg.jdr4 = cm_object_get_child_by_name(obj, "JDR4"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // SR bitfields. + state->u.f4.fld.sr.awd = cm_object_get_child_by_name(state->u.f4.reg.sr, "AWD"); + state->u.f4.fld.sr.eoc = cm_object_get_child_by_name(state->u.f4.reg.sr, "EOC"); + state->u.f4.fld.sr.jeoc = cm_object_get_child_by_name(state->u.f4.reg.sr, "JEOC"); + state->u.f4.fld.sr.jstrt = cm_object_get_child_by_name(state->u.f4.reg.sr, "JSTRT"); + state->u.f4.fld.sr.strt = cm_object_get_child_by_name(state->u.f4.reg.sr, "STRT"); + state->u.f4.fld.sr.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OVR"); + + // CR1 bitfields. + state->u.f4.fld.cr1.awdch = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDCH"); + state->u.f4.fld.cr1.eocie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "EOCIE"); + state->u.f4.fld.cr1.awdie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDIE"); + state->u.f4.fld.cr1.jeocie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JEOCIE"); + state->u.f4.fld.cr1.scan = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SCAN"); + state->u.f4.fld.cr1.awdsgl = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDSGL"); + state->u.f4.fld.cr1.jauto = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JAUTO"); + state->u.f4.fld.cr1.discen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DISCEN"); + state->u.f4.fld.cr1.jdiscen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JDISCEN"); + state->u.f4.fld.cr1.discnum = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DISCNUM"); + state->u.f4.fld.cr1.jawden = cm_object_get_child_by_name(state->u.f4.reg.cr1, "JAWDEN"); + state->u.f4.fld.cr1.awden = cm_object_get_child_by_name(state->u.f4.reg.cr1, "AWDEN"); + state->u.f4.fld.cr1.res = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RES"); + state->u.f4.fld.cr1.ovrie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVRIE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.adon = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADON"); + state->u.f4.fld.cr2.cont = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CONT"); + state->u.f4.fld.cr2.dma = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DMA"); + state->u.f4.fld.cr2.dds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DDS"); + state->u.f4.fld.cr2.eocs = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EOCS"); + state->u.f4.fld.cr2.align = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ALIGN"); + state->u.f4.fld.cr2.jextsel = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JEXTSEL"); + state->u.f4.fld.cr2.jexten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JEXTEN"); + state->u.f4.fld.cr2.jswstart = cm_object_get_child_by_name(state->u.f4.reg.cr2, "JSWSTART"); + state->u.f4.fld.cr2.extsel = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EXTSEL"); + state->u.f4.fld.cr2.exten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "EXTEN"); + state->u.f4.fld.cr2.swstart = cm_object_get_child_by_name(state->u.f4.reg.cr2, "SWSTART"); + + // SMPR1 bitfields. + state->u.f4.fld.smpr1.smpx_x = cm_object_get_child_by_name(state->u.f4.reg.smpr1, "SMPx_x"); + + // SMPR2 bitfields. + state->u.f4.fld.smpr2.smpx_x = cm_object_get_child_by_name(state->u.f4.reg.smpr2, "SMPx_x"); + + // JOFR1 bitfields. + state->u.f4.fld.jofr1.joffset1 = cm_object_get_child_by_name(state->u.f4.reg.jofr1, "JOFFSET1"); + + // JOFR2 bitfields. + state->u.f4.fld.jofr2.joffset2 = cm_object_get_child_by_name(state->u.f4.reg.jofr2, "JOFFSET2"); + + // JOFR3 bitfields. + state->u.f4.fld.jofr3.joffset3 = cm_object_get_child_by_name(state->u.f4.reg.jofr3, "JOFFSET3"); + + // JOFR4 bitfields. + state->u.f4.fld.jofr4.joffset4 = cm_object_get_child_by_name(state->u.f4.reg.jofr4, "JOFFSET4"); + + // HTR bitfields. + state->u.f4.fld.htr.ht = cm_object_get_child_by_name(state->u.f4.reg.htr, "HT"); + + // LTR bitfields. + state->u.f4.fld.ltr.lt = cm_object_get_child_by_name(state->u.f4.reg.ltr, "LT"); + + // SQR1 bitfields. + state->u.f4.fld.sqr1.sq13 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ13"); + state->u.f4.fld.sqr1.sq14 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ14"); + state->u.f4.fld.sqr1.sq15 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ15"); + state->u.f4.fld.sqr1.sq16 = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "SQ16"); + state->u.f4.fld.sqr1.l = cm_object_get_child_by_name(state->u.f4.reg.sqr1, "L"); + + // SQR2 bitfields. + state->u.f4.fld.sqr2.sq7 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ7"); + state->u.f4.fld.sqr2.sq8 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ8"); + state->u.f4.fld.sqr2.sq9 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ9"); + state->u.f4.fld.sqr2.sq10 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ10"); + state->u.f4.fld.sqr2.sq11 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ11"); + state->u.f4.fld.sqr2.sq12 = cm_object_get_child_by_name(state->u.f4.reg.sqr2, "SQ12"); + + // SQR3 bitfields. + state->u.f4.fld.sqr3.sq1 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ1"); + state->u.f4.fld.sqr3.sq2 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ2"); + state->u.f4.fld.sqr3.sq3 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ3"); + state->u.f4.fld.sqr3.sq4 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ4"); + state->u.f4.fld.sqr3.sq5 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ5"); + state->u.f4.fld.sqr3.sq6 = cm_object_get_child_by_name(state->u.f4.reg.sqr3, "SQ6"); + + // JSQR bitfields. + state->u.f4.fld.jsqr.jsq1 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ1"); + state->u.f4.fld.jsqr.jsq2 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ2"); + state->u.f4.fld.jsqr.jsq3 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ3"); + state->u.f4.fld.jsqr.jsq4 = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JSQ4"); + state->u.f4.fld.jsqr.jl = cm_object_get_child_by_name(state->u.f4.reg.jsqr, "JL"); + + // JDR1 bitfields. + state->u.f4.fld.jdr1.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr1, "JDATA"); + + // JDR2 bitfields. + state->u.f4.fld.jdr2.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr2, "JDATA"); + + // JDR3 bitfields. + state->u.f4.fld.jdr3.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr3, "JDATA"); + + // JDR4 bitfields. + state->u.f4.fld.jdr4.jdata = cm_object_get_child_by_name(state->u.f4.reg.jdr4, "JDATA"); + + // DR bitfields. + state->u.f4.fld.dr.data = cm_object_get_child_by_name(state->u.f4.reg.dr, "DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32ADCState *state = STM32_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_adc_is_enabled(Object *obj) +{ + STM32ADCState *state = STM32_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32ADCState *state = STM32_ADC_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_ADC_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32ADCState *state = STM32_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/ADC%dEN", + 1 + state->port_index - STM32_PORT_ADC1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_ADC); +} + +static void stm32_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_adc_reset_callback; + dc->realize = stm32_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_adc_is_enabled; +} + +static const TypeInfo stm32_adc_type_info = { + .name = TYPE_STM32_ADC, + .parent = TYPE_STM32_ADC_PARENT, + .instance_init = stm32_adc_instance_init_callback, + .instance_size = sizeof(STM32ADCState), + .class_init = stm32_adc_class_init_callback, + .class_size = sizeof(STM32ADCClass) }; + +static void stm32_adc_register_types(void) +{ + type_register_static(&stm32_adc_type_info); +} + +type_init(stm32_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/adc1.h b/gnu-mcu-eclipse/devices/support/STM32F429x/adc1.h new file mode 100644 index 0000000000..29cf7373ae --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/adc1.h @@ -0,0 +1,278 @@ +/* + * STM32 - ADC (Analog-to-digital converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_ADC_H_ +#define STM32_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_ADC DEVICE_PATH_STM32 "ADC" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_ADC1, + STM32_PORT_ADC2, + STM32_PORT_ADC3, + STM32_PORT_ADC_UNDEFINED = 0xFF, +} stm32_adc_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_ADC TYPE_STM32_PREFIX "adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32ADCParentClass; +typedef PeripheralState STM32ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32ADCClass, (obj), TYPE_STM32_ADC) +#define STM32_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32ADCClass, (klass), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentClass parent_class; + // public: + + // None, so far. +} STM32ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_ADC_STATE(obj) \ + OBJECT_CHECK(STM32ADCState, (obj), TYPE_STM32_ADC) + +typedef struct { + // private: + STM32ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_adc_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 ADC (Analog-to-digital converter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *cr1; // 0x4 (Control register 1) + Object *cr2; // 0x8 (Control register 2) + Object *smpr1; // 0xC (Sample time register 1) + Object *smpr2; // 0x10 (Sample time register 2) + Object *jofr1; // 0x14 (Injected channel data offset register x) + Object *jofr2; // 0x18 (Injected channel data offset register x) + Object *jofr3; // 0x1C (Injected channel data offset register x) + Object *jofr4; // 0x20 (Injected channel data offset register x) + Object *htr; // 0x24 (Watchdog higher threshold register) + Object *ltr; // 0x28 (Watchdog lower threshold register) + Object *sqr1; // 0x2C (Regular sequence register 1) + Object *sqr2; // 0x30 (Regular sequence register 2) + Object *sqr3; // 0x34 (Regular sequence register 3) + Object *jsqr; // 0x38 (Injected sequence register) + Object *jdr1; // 0x3C (Injected data register x) + Object *jdr2; // 0x40 (Injected data register x) + Object *jdr3; // 0x44 (Injected data register x) + Object *jdr4; // 0x48 (Injected data register x) + Object *dr; // 0x4C (Regular data register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *awd; // [0:0] Analog watchdog flag + Object *eoc; // [1:1] Regular channel end of conversion + Object *jeoc; // [2:2] Injected channel end of conversion + Object *jstrt; // [3:3] Injected channel start flag + Object *strt; // [4:4] Regular channel start flag + Object *ovr; // [5:5] Overrun + } sr; + + // CR1 (Control register 1) bitfields. + struct { + Object *awdch; // [0:4] Analog watchdog channel select bits + Object *eocie; // [5:5] Interrupt enable for EOC + Object *awdie; // [6:6] Analog watchdog interrupt enable + Object *jeocie; // [7:7] Interrupt enable for injected channels + Object *scan; // [8:8] Scan mode + Object *awdsgl; // [9:9] Enable the watchdog on a single channel in scan mode + Object *jauto; // [10:10] Automatic injected group conversion + Object *discen; // [11:11] Discontinuous mode on regular channels + Object *jdiscen; // [12:12] Discontinuous mode on injected channels + Object *discnum; // [13:15] Discontinuous mode channel count + Object *jawden; // [22:22] Analog watchdog enable on injected channels + Object *awden; // [23:23] Analog watchdog enable on regular channels + Object *res; // [24:25] Resolution + Object *ovrie; // [26:26] Overrun interrupt enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *adon; // [0:0] A/D Converter ON / OFF + Object *cont; // [1:1] Continuous conversion + Object *dma; // [8:8] Direct memory access mode (for single ADC mode) + Object *dds; // [9:9] DMA disable selection (for single ADC mode) + Object *eocs; // [10:10] End of conversion selection + Object *align; // [11:11] Data alignment + Object *jextsel; // [16:19] External event select for injected group + Object *jexten; // [20:21] External trigger enable for injected channels + Object *jswstart; // [22:22] Start conversion of injected channels + Object *extsel; // [24:27] External event select for regular group + Object *exten; // [28:29] External trigger enable for regular channels + Object *swstart; // [30:30] Start conversion of regular channels + } cr2; + + // SMPR1 (Sample time register 1) bitfields. + struct { + Object *smpx_x; // [0:31] Sample time bits + } smpr1; + + // SMPR2 (Sample time register 2) bitfields. + struct { + Object *smpx_x; // [0:31] Sample time bits + } smpr2; + + // JOFR1 (Injected channel data offset register x) bitfields. + struct { + Object *joffset1; // [0:11] Data offset for injected channel x + } jofr1; + + // JOFR2 (Injected channel data offset register x) bitfields. + struct { + Object *joffset2; // [0:11] Data offset for injected channel x + } jofr2; + + // JOFR3 (Injected channel data offset register x) bitfields. + struct { + Object *joffset3; // [0:11] Data offset for injected channel x + } jofr3; + + // JOFR4 (Injected channel data offset register x) bitfields. + struct { + Object *joffset4; // [0:11] Data offset for injected channel x + } jofr4; + + // HTR (Watchdog higher threshold register) bitfields. + struct { + Object *ht; // [0:11] Analog watchdog higher threshold + } htr; + + // LTR (Watchdog lower threshold register) bitfields. + struct { + Object *lt; // [0:11] Analog watchdog lower threshold + } ltr; + + // SQR1 (Regular sequence register 1) bitfields. + struct { + Object *sq13; // [0:4] 13th conversion in regular sequence + Object *sq14; // [5:9] 14th conversion in regular sequence + Object *sq15; // [10:14] 15th conversion in regular sequence + Object *sq16; // [15:19] 16th conversion in regular sequence + Object *l; // [20:23] Regular channel sequence length + } sqr1; + + // SQR2 (Regular sequence register 2) bitfields. + struct { + Object *sq7; // [0:4] 7th conversion in regular sequence + Object *sq8; // [5:9] 8th conversion in regular sequence + Object *sq9; // [10:14] 9th conversion in regular sequence + Object *sq10; // [15:19] 10th conversion in regular sequence + Object *sq11; // [20:24] 11th conversion in regular sequence + Object *sq12; // [25:29] 12th conversion in regular sequence + } sqr2; + + // SQR3 (Regular sequence register 3) bitfields. + struct { + Object *sq1; // [0:4] 1st conversion in regular sequence + Object *sq2; // [5:9] 2nd conversion in regular sequence + Object *sq3; // [10:14] 3rd conversion in regular sequence + Object *sq4; // [15:19] 4th conversion in regular sequence + Object *sq5; // [20:24] 5th conversion in regular sequence + Object *sq6; // [25:29] 6th conversion in regular sequence + } sqr3; + + // JSQR (Injected sequence register) bitfields. + struct { + Object *jsq1; // [0:4] 1st conversion in injected sequence + Object *jsq2; // [5:9] 2nd conversion in injected sequence + Object *jsq3; // [10:14] 3rd conversion in injected sequence + Object *jsq4; // [15:19] 4th conversion in injected sequence + Object *jl; // [20:21] Injected sequence length + } jsqr; + + // JDR1 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr1; + + // JDR2 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr2; + + // JDR3 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr3; + + // JDR4 (Injected data register x) bitfields. + struct { + Object *jdata; // [0:15] Injected data + } jdr4; + + // DR (Regular data register) bitfields. + struct { + Object *data; // [0:15] Regular data + } dr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/c_adc.c b/gnu-mcu-eclipse/devices/support/STM32F429x/c_adc.c new file mode 100644 index 0000000000..e79bb017c4 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/c_adc.c @@ -0,0 +1,270 @@ +/* + * STM32 - C_ADC (Common ADC registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_c_adc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f4.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + state->u.f4.reg.cdr = cm_object_get_child_by_name(obj, "CDR"); + + + // CSR bitfields. + state->u.f4.fld.csr.awd1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD1"); + state->u.f4.fld.csr.eoc1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC1"); + state->u.f4.fld.csr.jeoc1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC1"); + state->u.f4.fld.csr.jstrt1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT1"); + state->u.f4.fld.csr.strt1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT1"); + state->u.f4.fld.csr.ovr1 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR1"); + state->u.f4.fld.csr.awd2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD2"); + state->u.f4.fld.csr.eoc2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC2"); + state->u.f4.fld.csr.jeoc2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC2"); + state->u.f4.fld.csr.jstrt2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT2"); + state->u.f4.fld.csr.strt2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT2"); + state->u.f4.fld.csr.ovr2 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR2"); + state->u.f4.fld.csr.awd3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "AWD3"); + state->u.f4.fld.csr.eoc3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "EOC3"); + state->u.f4.fld.csr.jeoc3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JEOC3"); + state->u.f4.fld.csr.jstrt3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "JSTRT3"); + state->u.f4.fld.csr.strt3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "STRT3"); + state->u.f4.fld.csr.ovr3 = cm_object_get_child_by_name(state->u.f4.reg.csr, "OVR3"); + + // CCR bitfields. + state->u.f4.fld.ccr.mult = cm_object_get_child_by_name(state->u.f4.reg.ccr, "MULT"); + state->u.f4.fld.ccr.delay = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DELAY"); + state->u.f4.fld.ccr.dds = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DDS"); + state->u.f4.fld.ccr.dma = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DMA"); + state->u.f4.fld.ccr.adcpre = cm_object_get_child_by_name(state->u.f4.reg.ccr, "ADCPRE"); + state->u.f4.fld.ccr.vbate = cm_object_get_child_by_name(state->u.f4.reg.ccr, "VBATE"); + state->u.f4.fld.ccr.tsvrefe = cm_object_get_child_by_name(state->u.f4.reg.ccr, "TSVREFE"); + + // CDR bitfields. + state->u.f4.fld.cdr.data1 = cm_object_get_child_by_name(state->u.f4.reg.cdr, "DATA1"); + state->u.f4.fld.cdr.data2 = cm_object_get_child_by_name(state->u.f4.reg.cdr, "DATA2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_c_adc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_c_adc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_c_adc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_c_adc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_c_adc_is_enabled(Object *obj) +{ + STM32C_ADCState *state = STM32_C_ADC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_c_adc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32C_ADCState *state = STM32_C_ADC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_c_adc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_C_ADC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32C_ADCState *state = STM32_C_ADC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "C_ADC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_c_adc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_c_adc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_c_adc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_c_adc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_c_adc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/C_ADCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_c_adc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_C_ADC); +} + +static void stm32_c_adc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_c_adc_reset_callback; + dc->realize = stm32_c_adc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_c_adc_is_enabled; +} + +static const TypeInfo stm32_c_adc_type_info = { + .name = TYPE_STM32_C_ADC, + .parent = TYPE_STM32_C_ADC_PARENT, + .instance_init = stm32_c_adc_instance_init_callback, + .instance_size = sizeof(STM32C_ADCState), + .class_init = stm32_c_adc_class_init_callback, + .class_size = sizeof(STM32C_ADCClass) }; + +static void stm32_c_adc_register_types(void) +{ + type_register_static(&stm32_c_adc_type_info); +} + +type_init(stm32_c_adc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/c_adc.h b/gnu-mcu-eclipse/devices/support/STM32F429x/c_adc.h new file mode 100644 index 0000000000..deae314e3a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/c_adc.h @@ -0,0 +1,141 @@ +/* + * STM32 - C_ADC (Common ADC registers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_C_ADC_H_ +#define STM32_C_ADC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_C_ADC DEVICE_PATH_STM32 "C_ADC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_C_ADC TYPE_STM32_PREFIX "c_adc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_C_ADC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32C_ADCParentClass; +typedef PeripheralState STM32C_ADCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_C_ADC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32C_ADCClass, (obj), TYPE_STM32_C_ADC) +#define STM32_C_ADC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32C_ADCClass, (klass), TYPE_STM32_C_ADC) + +typedef struct { + // private: + STM32C_ADCParentClass parent_class; + // public: + + // None, so far. +} STM32C_ADCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_C_ADC_STATE(obj) \ + OBJECT_CHECK(STM32C_ADCState, (obj), TYPE_STM32_C_ADC) + +typedef struct { + // private: + STM32C_ADCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 C_ADC (Common ADC registers) registers. + struct { + Object *csr; // 0x0 (ADC Common status register) + Object *ccr; // 0x4 (ADC common control register) + Object *cdr; // 0x8 (ADC common regular data register for dual and triple modes) + } reg; + + struct { + + // CSR (ADC Common status register) bitfields. + struct { + Object *awd1; // [0:0] Analog watchdog flag of ADC 1 + Object *eoc1; // [1:1] End of conversion of ADC 1 + Object *jeoc1; // [2:2] Injected channel end of conversion of ADC 1 + Object *jstrt1; // [3:3] Injected channel Start flag of ADC 1 + Object *strt1; // [4:4] Regular channel Start flag of ADC 1 + Object *ovr1; // [5:5] Overrun flag of ADC 1 + Object *awd2; // [8:8] Analog watchdog flag of ADC 2 + Object *eoc2; // [9:9] End of conversion of ADC 2 + Object *jeoc2; // [10:10] Injected channel end of conversion of ADC 2 + Object *jstrt2; // [11:11] Injected channel Start flag of ADC 2 + Object *strt2; // [12:12] Regular channel Start flag of ADC 2 + Object *ovr2; // [13:13] Overrun flag of ADC 2 + Object *awd3; // [16:16] Analog watchdog flag of ADC 3 + Object *eoc3; // [17:17] End of conversion of ADC 3 + Object *jeoc3; // [18:18] Injected channel end of conversion of ADC 3 + Object *jstrt3; // [19:19] Injected channel Start flag of ADC 3 + Object *strt3; // [20:20] Regular channel Start flag of ADC 3 + Object *ovr3; // [21:21] Overrun flag of ADC3 + } csr; + + // CCR (ADC common control register) bitfields. + struct { + Object *mult; // [0:4] Multi ADC mode selection + Object *delay; // [8:11] Delay between 2 sampling phases + Object *dds; // [13:13] DMA disable selection for multi-ADC mode + Object *dma; // [14:15] Direct memory access mode for multi ADC mode + Object *adcpre; // [16:17] ADC prescaler + Object *vbate; // [22:22] VBAT enable + Object *tsvrefe; // [23:23] Temperature sensor and VREFINT enable + } ccr; + + // CDR (ADC common regular data register for dual and triple modes) bitfields. + struct { + Object *data1; // [0:15] 1st data item of a pair of regular conversions + Object *data2; // [16:31] 2nd data item of a pair of regular conversions + } cdr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32C_ADCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_C_ADC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/can1.c b/gnu-mcu-eclipse/devices/support/STM32F429x/can1.c new file mode 100644 index 0000000000..9b3d00694f --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/can1.c @@ -0,0 +1,2565 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_can_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.mcr = cm_object_get_child_by_name(obj, "MCR"); + state->u.f4.reg.msr = cm_object_get_child_by_name(obj, "MSR"); + state->u.f4.reg.tsr = cm_object_get_child_by_name(obj, "TSR"); + state->u.f4.reg.rf0r = cm_object_get_child_by_name(obj, "RF0R"); + state->u.f4.reg.rf1r = cm_object_get_child_by_name(obj, "RF1R"); + state->u.f4.reg.ier = cm_object_get_child_by_name(obj, "IER"); + state->u.f4.reg.esr = cm_object_get_child_by_name(obj, "ESR"); + state->u.f4.reg.btr = cm_object_get_child_by_name(obj, "BTR"); + state->u.f4.reg.ti0r = cm_object_get_child_by_name(obj, "TI0R"); + state->u.f4.reg.tdt0r = cm_object_get_child_by_name(obj, "TDT0R"); + state->u.f4.reg.tdl0r = cm_object_get_child_by_name(obj, "TDL0R"); + state->u.f4.reg.tdh0r = cm_object_get_child_by_name(obj, "TDH0R"); + state->u.f4.reg.ti1r = cm_object_get_child_by_name(obj, "TI1R"); + state->u.f4.reg.tdt1r = cm_object_get_child_by_name(obj, "TDT1R"); + state->u.f4.reg.tdl1r = cm_object_get_child_by_name(obj, "TDL1R"); + state->u.f4.reg.tdh1r = cm_object_get_child_by_name(obj, "TDH1R"); + state->u.f4.reg.ti2r = cm_object_get_child_by_name(obj, "TI2R"); + state->u.f4.reg.tdt2r = cm_object_get_child_by_name(obj, "TDT2R"); + state->u.f4.reg.tdl2r = cm_object_get_child_by_name(obj, "TDL2R"); + state->u.f4.reg.tdh2r = cm_object_get_child_by_name(obj, "TDH2R"); + state->u.f4.reg.ri0r = cm_object_get_child_by_name(obj, "RI0R"); + state->u.f4.reg.rdt0r = cm_object_get_child_by_name(obj, "RDT0R"); + state->u.f4.reg.rdl0r = cm_object_get_child_by_name(obj, "RDL0R"); + state->u.f4.reg.rdh0r = cm_object_get_child_by_name(obj, "RDH0R"); + state->u.f4.reg.ri1r = cm_object_get_child_by_name(obj, "RI1R"); + state->u.f4.reg.rdt1r = cm_object_get_child_by_name(obj, "RDT1R"); + state->u.f4.reg.rdl1r = cm_object_get_child_by_name(obj, "RDL1R"); + state->u.f4.reg.rdh1r = cm_object_get_child_by_name(obj, "RDH1R"); + state->u.f4.reg.fmr = cm_object_get_child_by_name(obj, "FMR"); + state->u.f4.reg.fm1r = cm_object_get_child_by_name(obj, "FM1R"); + state->u.f4.reg.fs1r = cm_object_get_child_by_name(obj, "FS1R"); + state->u.f4.reg.ffa1r = cm_object_get_child_by_name(obj, "FFA1R"); + state->u.f4.reg.fa1r = cm_object_get_child_by_name(obj, "FA1R"); + state->u.f4.reg.f0r1 = cm_object_get_child_by_name(obj, "F0R1"); + state->u.f4.reg.f0r2 = cm_object_get_child_by_name(obj, "F0R2"); + state->u.f4.reg.f1r1 = cm_object_get_child_by_name(obj, "F1R1"); + state->u.f4.reg.f1r2 = cm_object_get_child_by_name(obj, "F1R2"); + state->u.f4.reg.f2r1 = cm_object_get_child_by_name(obj, "F2R1"); + state->u.f4.reg.f2r2 = cm_object_get_child_by_name(obj, "F2R2"); + state->u.f4.reg.f3r1 = cm_object_get_child_by_name(obj, "F3R1"); + state->u.f4.reg.f3r2 = cm_object_get_child_by_name(obj, "F3R2"); + state->u.f4.reg.f4r1 = cm_object_get_child_by_name(obj, "F4R1"); + state->u.f4.reg.f4r2 = cm_object_get_child_by_name(obj, "F4R2"); + state->u.f4.reg.f5r1 = cm_object_get_child_by_name(obj, "F5R1"); + state->u.f4.reg.f5r2 = cm_object_get_child_by_name(obj, "F5R2"); + state->u.f4.reg.f6r1 = cm_object_get_child_by_name(obj, "F6R1"); + state->u.f4.reg.f6r2 = cm_object_get_child_by_name(obj, "F6R2"); + state->u.f4.reg.f7r1 = cm_object_get_child_by_name(obj, "F7R1"); + state->u.f4.reg.f7r2 = cm_object_get_child_by_name(obj, "F7R2"); + state->u.f4.reg.f8r1 = cm_object_get_child_by_name(obj, "F8R1"); + state->u.f4.reg.f8r2 = cm_object_get_child_by_name(obj, "F8R2"); + state->u.f4.reg.f9r1 = cm_object_get_child_by_name(obj, "F9R1"); + state->u.f4.reg.f9r2 = cm_object_get_child_by_name(obj, "F9R2"); + state->u.f4.reg.f10r1 = cm_object_get_child_by_name(obj, "F10R1"); + state->u.f4.reg.f10r2 = cm_object_get_child_by_name(obj, "F10R2"); + state->u.f4.reg.f11r1 = cm_object_get_child_by_name(obj, "F11R1"); + state->u.f4.reg.f11r2 = cm_object_get_child_by_name(obj, "F11R2"); + state->u.f4.reg.f12r1 = cm_object_get_child_by_name(obj, "F12R1"); + state->u.f4.reg.f12r2 = cm_object_get_child_by_name(obj, "F12R2"); + state->u.f4.reg.f13r1 = cm_object_get_child_by_name(obj, "F13R1"); + state->u.f4.reg.f13r2 = cm_object_get_child_by_name(obj, "F13R2"); + state->u.f4.reg.f14r1 = cm_object_get_child_by_name(obj, "F14R1"); + state->u.f4.reg.f14r2 = cm_object_get_child_by_name(obj, "F14R2"); + state->u.f4.reg.f15r1 = cm_object_get_child_by_name(obj, "F15R1"); + state->u.f4.reg.f15r2 = cm_object_get_child_by_name(obj, "F15R2"); + state->u.f4.reg.f16r1 = cm_object_get_child_by_name(obj, "F16R1"); + state->u.f4.reg.f16r2 = cm_object_get_child_by_name(obj, "F16R2"); + state->u.f4.reg.f17r1 = cm_object_get_child_by_name(obj, "F17R1"); + state->u.f4.reg.f17r2 = cm_object_get_child_by_name(obj, "F17R2"); + state->u.f4.reg.f18r1 = cm_object_get_child_by_name(obj, "F18R1"); + state->u.f4.reg.f18r2 = cm_object_get_child_by_name(obj, "F18R2"); + state->u.f4.reg.f19r1 = cm_object_get_child_by_name(obj, "F19R1"); + state->u.f4.reg.f19r2 = cm_object_get_child_by_name(obj, "F19R2"); + state->u.f4.reg.f20r1 = cm_object_get_child_by_name(obj, "F20R1"); + state->u.f4.reg.f20r2 = cm_object_get_child_by_name(obj, "F20R2"); + state->u.f4.reg.f21r1 = cm_object_get_child_by_name(obj, "F21R1"); + state->u.f4.reg.f21r2 = cm_object_get_child_by_name(obj, "F21R2"); + state->u.f4.reg.f22r1 = cm_object_get_child_by_name(obj, "F22R1"); + state->u.f4.reg.f22r2 = cm_object_get_child_by_name(obj, "F22R2"); + state->u.f4.reg.f23r1 = cm_object_get_child_by_name(obj, "F23R1"); + state->u.f4.reg.f23r2 = cm_object_get_child_by_name(obj, "F23R2"); + state->u.f4.reg.f24r1 = cm_object_get_child_by_name(obj, "F24R1"); + state->u.f4.reg.f24r2 = cm_object_get_child_by_name(obj, "F24R2"); + state->u.f4.reg.f25r1 = cm_object_get_child_by_name(obj, "F25R1"); + state->u.f4.reg.f25r2 = cm_object_get_child_by_name(obj, "F25R2"); + state->u.f4.reg.f26r1 = cm_object_get_child_by_name(obj, "F26R1"); + state->u.f4.reg.f26r2 = cm_object_get_child_by_name(obj, "F26R2"); + state->u.f4.reg.f27r1 = cm_object_get_child_by_name(obj, "F27R1"); + state->u.f4.reg.f27r2 = cm_object_get_child_by_name(obj, "F27R2"); + + + // MCR bitfields. + state->u.f4.fld.mcr.inrq = cm_object_get_child_by_name(state->u.f4.reg.mcr, "INRQ"); + state->u.f4.fld.mcr.sleep = cm_object_get_child_by_name(state->u.f4.reg.mcr, "SLEEP"); + state->u.f4.fld.mcr.txfp = cm_object_get_child_by_name(state->u.f4.reg.mcr, "TXFP"); + state->u.f4.fld.mcr.rflm = cm_object_get_child_by_name(state->u.f4.reg.mcr, "RFLM"); + state->u.f4.fld.mcr.nart = cm_object_get_child_by_name(state->u.f4.reg.mcr, "NART"); + state->u.f4.fld.mcr.awum = cm_object_get_child_by_name(state->u.f4.reg.mcr, "AWUM"); + state->u.f4.fld.mcr.abom = cm_object_get_child_by_name(state->u.f4.reg.mcr, "ABOM"); + state->u.f4.fld.mcr.ttcm = cm_object_get_child_by_name(state->u.f4.reg.mcr, "TTCM"); + state->u.f4.fld.mcr.reset = cm_object_get_child_by_name(state->u.f4.reg.mcr, "RESET"); + state->u.f4.fld.mcr.dbf = cm_object_get_child_by_name(state->u.f4.reg.mcr, "DBF"); + + // MSR bitfields. + state->u.f4.fld.msr.inak = cm_object_get_child_by_name(state->u.f4.reg.msr, "INAK"); + state->u.f4.fld.msr.slak = cm_object_get_child_by_name(state->u.f4.reg.msr, "SLAK"); + state->u.f4.fld.msr.erri = cm_object_get_child_by_name(state->u.f4.reg.msr, "ERRI"); + state->u.f4.fld.msr.wkui = cm_object_get_child_by_name(state->u.f4.reg.msr, "WKUI"); + state->u.f4.fld.msr.slaki = cm_object_get_child_by_name(state->u.f4.reg.msr, "SLAKI"); + state->u.f4.fld.msr.txm = cm_object_get_child_by_name(state->u.f4.reg.msr, "TXM"); + state->u.f4.fld.msr.rxm = cm_object_get_child_by_name(state->u.f4.reg.msr, "RXM"); + state->u.f4.fld.msr.samp = cm_object_get_child_by_name(state->u.f4.reg.msr, "SAMP"); + state->u.f4.fld.msr.rx = cm_object_get_child_by_name(state->u.f4.reg.msr, "RX"); + + // TSR bitfields. + state->u.f4.fld.tsr.rqcp0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "RQCP0"); + state->u.f4.fld.tsr.txok0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TXOK0"); + state->u.f4.fld.tsr.alst0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ALST0"); + state->u.f4.fld.tsr.terr0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TERR0"); + state->u.f4.fld.tsr.abrq0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ABRQ0"); + state->u.f4.fld.tsr.rqcp1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "RQCP1"); + state->u.f4.fld.tsr.txok1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TXOK1"); + state->u.f4.fld.tsr.alst1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ALST1"); + state->u.f4.fld.tsr.terr1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TERR1"); + state->u.f4.fld.tsr.abrq1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ABRQ1"); + state->u.f4.fld.tsr.rqcp2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "RQCP2"); + state->u.f4.fld.tsr.txok2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TXOK2"); + state->u.f4.fld.tsr.alst2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ALST2"); + state->u.f4.fld.tsr.terr2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TERR2"); + state->u.f4.fld.tsr.abrq2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "ABRQ2"); + state->u.f4.fld.tsr.code = cm_object_get_child_by_name(state->u.f4.reg.tsr, "CODE"); + state->u.f4.fld.tsr.tme0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TME0"); + state->u.f4.fld.tsr.tme1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TME1"); + state->u.f4.fld.tsr.tme2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "TME2"); + state->u.f4.fld.tsr.low0 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "LOW0"); + state->u.f4.fld.tsr.low1 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "LOW1"); + state->u.f4.fld.tsr.low2 = cm_object_get_child_by_name(state->u.f4.reg.tsr, "LOW2"); + + // RF0R bitfields. + state->u.f4.fld.rf0r.fmp0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "FMP0"); + state->u.f4.fld.rf0r.full0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "FULL0"); + state->u.f4.fld.rf0r.fovr0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "FOVR0"); + state->u.f4.fld.rf0r.rfom0 = cm_object_get_child_by_name(state->u.f4.reg.rf0r, "RFOM0"); + + // RF1R bitfields. + state->u.f4.fld.rf1r.fmp1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "FMP1"); + state->u.f4.fld.rf1r.full1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "FULL1"); + state->u.f4.fld.rf1r.fovr1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "FOVR1"); + state->u.f4.fld.rf1r.rfom1 = cm_object_get_child_by_name(state->u.f4.reg.rf1r, "RFOM1"); + + // IER bitfields. + state->u.f4.fld.ier.tmeie = cm_object_get_child_by_name(state->u.f4.reg.ier, "TMEIE"); + state->u.f4.fld.ier.fmpie0 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FMPIE0"); + state->u.f4.fld.ier.ffie0 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FFIE0"); + state->u.f4.fld.ier.fovie0 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FOVIE0"); + state->u.f4.fld.ier.fmpie1 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FMPIE1"); + state->u.f4.fld.ier.ffie1 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FFIE1"); + state->u.f4.fld.ier.fovie1 = cm_object_get_child_by_name(state->u.f4.reg.ier, "FOVIE1"); + state->u.f4.fld.ier.ewgie = cm_object_get_child_by_name(state->u.f4.reg.ier, "EWGIE"); + state->u.f4.fld.ier.epvie = cm_object_get_child_by_name(state->u.f4.reg.ier, "EPVIE"); + state->u.f4.fld.ier.bofie = cm_object_get_child_by_name(state->u.f4.reg.ier, "BOFIE"); + state->u.f4.fld.ier.lecie = cm_object_get_child_by_name(state->u.f4.reg.ier, "LECIE"); + state->u.f4.fld.ier.errie = cm_object_get_child_by_name(state->u.f4.reg.ier, "ERRIE"); + state->u.f4.fld.ier.wkuie = cm_object_get_child_by_name(state->u.f4.reg.ier, "WKUIE"); + state->u.f4.fld.ier.slkie = cm_object_get_child_by_name(state->u.f4.reg.ier, "SLKIE"); + + // ESR bitfields. + state->u.f4.fld.esr.ewgf = cm_object_get_child_by_name(state->u.f4.reg.esr, "EWGF"); + state->u.f4.fld.esr.epvf = cm_object_get_child_by_name(state->u.f4.reg.esr, "EPVF"); + state->u.f4.fld.esr.boff = cm_object_get_child_by_name(state->u.f4.reg.esr, "BOFF"); + state->u.f4.fld.esr.lec = cm_object_get_child_by_name(state->u.f4.reg.esr, "LEC"); + state->u.f4.fld.esr.tec = cm_object_get_child_by_name(state->u.f4.reg.esr, "TEC"); + state->u.f4.fld.esr.rec = cm_object_get_child_by_name(state->u.f4.reg.esr, "REC"); + + // BTR bitfields. + state->u.f4.fld.btr.brp = cm_object_get_child_by_name(state->u.f4.reg.btr, "BRP"); + state->u.f4.fld.btr.ts1 = cm_object_get_child_by_name(state->u.f4.reg.btr, "TS1"); + state->u.f4.fld.btr.ts2 = cm_object_get_child_by_name(state->u.f4.reg.btr, "TS2"); + state->u.f4.fld.btr.sjw = cm_object_get_child_by_name(state->u.f4.reg.btr, "SJW"); + state->u.f4.fld.btr.lbkm = cm_object_get_child_by_name(state->u.f4.reg.btr, "LBKM"); + state->u.f4.fld.btr.silm = cm_object_get_child_by_name(state->u.f4.reg.btr, "SILM"); + + // TI0R bitfields. + state->u.f4.fld.ti0r.txrq = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "TXRQ"); + state->u.f4.fld.ti0r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "RTR"); + state->u.f4.fld.ti0r.ide = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "IDE"); + state->u.f4.fld.ti0r.exid = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "EXID"); + state->u.f4.fld.ti0r.stid = cm_object_get_child_by_name(state->u.f4.reg.ti0r, "STID"); + + // TDT0R bitfields. + state->u.f4.fld.tdt0r.dlc = cm_object_get_child_by_name(state->u.f4.reg.tdt0r, "DLC"); + state->u.f4.fld.tdt0r.tgt = cm_object_get_child_by_name(state->u.f4.reg.tdt0r, "TGT"); + state->u.f4.fld.tdt0r.time = cm_object_get_child_by_name(state->u.f4.reg.tdt0r, "TIME"); + + // TDL0R bitfields. + state->u.f4.fld.tdl0r.data0 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA0"); + state->u.f4.fld.tdl0r.data1 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA1"); + state->u.f4.fld.tdl0r.data2 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA2"); + state->u.f4.fld.tdl0r.data3 = cm_object_get_child_by_name(state->u.f4.reg.tdl0r, "DATA3"); + + // TDH0R bitfields. + state->u.f4.fld.tdh0r.data4 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA4"); + state->u.f4.fld.tdh0r.data5 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA5"); + state->u.f4.fld.tdh0r.data6 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA6"); + state->u.f4.fld.tdh0r.data7 = cm_object_get_child_by_name(state->u.f4.reg.tdh0r, "DATA7"); + + // TI1R bitfields. + state->u.f4.fld.ti1r.txrq = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "TXRQ"); + state->u.f4.fld.ti1r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "RTR"); + state->u.f4.fld.ti1r.ide = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "IDE"); + state->u.f4.fld.ti1r.exid = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "EXID"); + state->u.f4.fld.ti1r.stid = cm_object_get_child_by_name(state->u.f4.reg.ti1r, "STID"); + + // TDT1R bitfields. + state->u.f4.fld.tdt1r.dlc = cm_object_get_child_by_name(state->u.f4.reg.tdt1r, "DLC"); + state->u.f4.fld.tdt1r.tgt = cm_object_get_child_by_name(state->u.f4.reg.tdt1r, "TGT"); + state->u.f4.fld.tdt1r.time = cm_object_get_child_by_name(state->u.f4.reg.tdt1r, "TIME"); + + // TDL1R bitfields. + state->u.f4.fld.tdl1r.data0 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA0"); + state->u.f4.fld.tdl1r.data1 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA1"); + state->u.f4.fld.tdl1r.data2 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA2"); + state->u.f4.fld.tdl1r.data3 = cm_object_get_child_by_name(state->u.f4.reg.tdl1r, "DATA3"); + + // TDH1R bitfields. + state->u.f4.fld.tdh1r.data4 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA4"); + state->u.f4.fld.tdh1r.data5 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA5"); + state->u.f4.fld.tdh1r.data6 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA6"); + state->u.f4.fld.tdh1r.data7 = cm_object_get_child_by_name(state->u.f4.reg.tdh1r, "DATA7"); + + // TI2R bitfields. + state->u.f4.fld.ti2r.txrq = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "TXRQ"); + state->u.f4.fld.ti2r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "RTR"); + state->u.f4.fld.ti2r.ide = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "IDE"); + state->u.f4.fld.ti2r.exid = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "EXID"); + state->u.f4.fld.ti2r.stid = cm_object_get_child_by_name(state->u.f4.reg.ti2r, "STID"); + + // TDT2R bitfields. + state->u.f4.fld.tdt2r.dlc = cm_object_get_child_by_name(state->u.f4.reg.tdt2r, "DLC"); + state->u.f4.fld.tdt2r.tgt = cm_object_get_child_by_name(state->u.f4.reg.tdt2r, "TGT"); + state->u.f4.fld.tdt2r.time = cm_object_get_child_by_name(state->u.f4.reg.tdt2r, "TIME"); + + // TDL2R bitfields. + state->u.f4.fld.tdl2r.data0 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA0"); + state->u.f4.fld.tdl2r.data1 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA1"); + state->u.f4.fld.tdl2r.data2 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA2"); + state->u.f4.fld.tdl2r.data3 = cm_object_get_child_by_name(state->u.f4.reg.tdl2r, "DATA3"); + + // TDH2R bitfields. + state->u.f4.fld.tdh2r.data4 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA4"); + state->u.f4.fld.tdh2r.data5 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA5"); + state->u.f4.fld.tdh2r.data6 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA6"); + state->u.f4.fld.tdh2r.data7 = cm_object_get_child_by_name(state->u.f4.reg.tdh2r, "DATA7"); + + // RI0R bitfields. + state->u.f4.fld.ri0r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "RTR"); + state->u.f4.fld.ri0r.ide = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "IDE"); + state->u.f4.fld.ri0r.exid = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "EXID"); + state->u.f4.fld.ri0r.stid = cm_object_get_child_by_name(state->u.f4.reg.ri0r, "STID"); + + // RDT0R bitfields. + state->u.f4.fld.rdt0r.dlc = cm_object_get_child_by_name(state->u.f4.reg.rdt0r, "DLC"); + state->u.f4.fld.rdt0r.fmi = cm_object_get_child_by_name(state->u.f4.reg.rdt0r, "FMI"); + state->u.f4.fld.rdt0r.time = cm_object_get_child_by_name(state->u.f4.reg.rdt0r, "TIME"); + + // RDL0R bitfields. + state->u.f4.fld.rdl0r.data0 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA0"); + state->u.f4.fld.rdl0r.data1 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA1"); + state->u.f4.fld.rdl0r.data2 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA2"); + state->u.f4.fld.rdl0r.data3 = cm_object_get_child_by_name(state->u.f4.reg.rdl0r, "DATA3"); + + // RDH0R bitfields. + state->u.f4.fld.rdh0r.data4 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA4"); + state->u.f4.fld.rdh0r.data5 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA5"); + state->u.f4.fld.rdh0r.data6 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA6"); + state->u.f4.fld.rdh0r.data7 = cm_object_get_child_by_name(state->u.f4.reg.rdh0r, "DATA7"); + + // RI1R bitfields. + state->u.f4.fld.ri1r.rtr = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "RTR"); + state->u.f4.fld.ri1r.ide = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "IDE"); + state->u.f4.fld.ri1r.exid = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "EXID"); + state->u.f4.fld.ri1r.stid = cm_object_get_child_by_name(state->u.f4.reg.ri1r, "STID"); + + // RDT1R bitfields. + state->u.f4.fld.rdt1r.dlc = cm_object_get_child_by_name(state->u.f4.reg.rdt1r, "DLC"); + state->u.f4.fld.rdt1r.fmi = cm_object_get_child_by_name(state->u.f4.reg.rdt1r, "FMI"); + state->u.f4.fld.rdt1r.time = cm_object_get_child_by_name(state->u.f4.reg.rdt1r, "TIME"); + + // RDL1R bitfields. + state->u.f4.fld.rdl1r.data0 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA0"); + state->u.f4.fld.rdl1r.data1 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA1"); + state->u.f4.fld.rdl1r.data2 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA2"); + state->u.f4.fld.rdl1r.data3 = cm_object_get_child_by_name(state->u.f4.reg.rdl1r, "DATA3"); + + // RDH1R bitfields. + state->u.f4.fld.rdh1r.data4 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA4"); + state->u.f4.fld.rdh1r.data5 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA5"); + state->u.f4.fld.rdh1r.data6 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA6"); + state->u.f4.fld.rdh1r.data7 = cm_object_get_child_by_name(state->u.f4.reg.rdh1r, "DATA7"); + + // FMR bitfields. + state->u.f4.fld.fmr.finit = cm_object_get_child_by_name(state->u.f4.reg.fmr, "FINIT"); + state->u.f4.fld.fmr.can2sb = cm_object_get_child_by_name(state->u.f4.reg.fmr, "CAN2SB"); + + // FM1R bitfields. + state->u.f4.fld.fm1r.fbm0 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM0"); + state->u.f4.fld.fm1r.fbm1 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM1"); + state->u.f4.fld.fm1r.fbm2 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM2"); + state->u.f4.fld.fm1r.fbm3 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM3"); + state->u.f4.fld.fm1r.fbm4 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM4"); + state->u.f4.fld.fm1r.fbm5 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM5"); + state->u.f4.fld.fm1r.fbm6 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM6"); + state->u.f4.fld.fm1r.fbm7 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM7"); + state->u.f4.fld.fm1r.fbm8 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM8"); + state->u.f4.fld.fm1r.fbm9 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM9"); + state->u.f4.fld.fm1r.fbm10 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM10"); + state->u.f4.fld.fm1r.fbm11 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM11"); + state->u.f4.fld.fm1r.fbm12 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM12"); + state->u.f4.fld.fm1r.fbm13 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM13"); + state->u.f4.fld.fm1r.fbm14 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM14"); + state->u.f4.fld.fm1r.fbm15 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM15"); + state->u.f4.fld.fm1r.fbm16 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM16"); + state->u.f4.fld.fm1r.fbm17 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM17"); + state->u.f4.fld.fm1r.fbm18 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM18"); + state->u.f4.fld.fm1r.fbm19 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM19"); + state->u.f4.fld.fm1r.fbm20 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM20"); + state->u.f4.fld.fm1r.fbm21 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM21"); + state->u.f4.fld.fm1r.fbm22 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM22"); + state->u.f4.fld.fm1r.fbm23 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM23"); + state->u.f4.fld.fm1r.fbm24 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM24"); + state->u.f4.fld.fm1r.fbm25 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM25"); + state->u.f4.fld.fm1r.fbm26 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM26"); + state->u.f4.fld.fm1r.fbm27 = cm_object_get_child_by_name(state->u.f4.reg.fm1r, "FBM27"); + + // FS1R bitfields. + state->u.f4.fld.fs1r.fsc0 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC0"); + state->u.f4.fld.fs1r.fsc1 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC1"); + state->u.f4.fld.fs1r.fsc2 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC2"); + state->u.f4.fld.fs1r.fsc3 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC3"); + state->u.f4.fld.fs1r.fsc4 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC4"); + state->u.f4.fld.fs1r.fsc5 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC5"); + state->u.f4.fld.fs1r.fsc6 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC6"); + state->u.f4.fld.fs1r.fsc7 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC7"); + state->u.f4.fld.fs1r.fsc8 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC8"); + state->u.f4.fld.fs1r.fsc9 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC9"); + state->u.f4.fld.fs1r.fsc10 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC10"); + state->u.f4.fld.fs1r.fsc11 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC11"); + state->u.f4.fld.fs1r.fsc12 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC12"); + state->u.f4.fld.fs1r.fsc13 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC13"); + state->u.f4.fld.fs1r.fsc14 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC14"); + state->u.f4.fld.fs1r.fsc15 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC15"); + state->u.f4.fld.fs1r.fsc16 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC16"); + state->u.f4.fld.fs1r.fsc17 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC17"); + state->u.f4.fld.fs1r.fsc18 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC18"); + state->u.f4.fld.fs1r.fsc19 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC19"); + state->u.f4.fld.fs1r.fsc20 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC20"); + state->u.f4.fld.fs1r.fsc21 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC21"); + state->u.f4.fld.fs1r.fsc22 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC22"); + state->u.f4.fld.fs1r.fsc23 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC23"); + state->u.f4.fld.fs1r.fsc24 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC24"); + state->u.f4.fld.fs1r.fsc25 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC25"); + state->u.f4.fld.fs1r.fsc26 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC26"); + state->u.f4.fld.fs1r.fsc27 = cm_object_get_child_by_name(state->u.f4.reg.fs1r, "FSC27"); + + // FFA1R bitfields. + state->u.f4.fld.ffa1r.ffa0 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA0"); + state->u.f4.fld.ffa1r.ffa1 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA1"); + state->u.f4.fld.ffa1r.ffa2 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA2"); + state->u.f4.fld.ffa1r.ffa3 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA3"); + state->u.f4.fld.ffa1r.ffa4 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA4"); + state->u.f4.fld.ffa1r.ffa5 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA5"); + state->u.f4.fld.ffa1r.ffa6 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA6"); + state->u.f4.fld.ffa1r.ffa7 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA7"); + state->u.f4.fld.ffa1r.ffa8 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA8"); + state->u.f4.fld.ffa1r.ffa9 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA9"); + state->u.f4.fld.ffa1r.ffa10 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA10"); + state->u.f4.fld.ffa1r.ffa11 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA11"); + state->u.f4.fld.ffa1r.ffa12 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA12"); + state->u.f4.fld.ffa1r.ffa13 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA13"); + state->u.f4.fld.ffa1r.ffa14 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA14"); + state->u.f4.fld.ffa1r.ffa15 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA15"); + state->u.f4.fld.ffa1r.ffa16 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA16"); + state->u.f4.fld.ffa1r.ffa17 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA17"); + state->u.f4.fld.ffa1r.ffa18 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA18"); + state->u.f4.fld.ffa1r.ffa19 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA19"); + state->u.f4.fld.ffa1r.ffa20 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA20"); + state->u.f4.fld.ffa1r.ffa21 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA21"); + state->u.f4.fld.ffa1r.ffa22 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA22"); + state->u.f4.fld.ffa1r.ffa23 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA23"); + state->u.f4.fld.ffa1r.ffa24 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA24"); + state->u.f4.fld.ffa1r.ffa25 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA25"); + state->u.f4.fld.ffa1r.ffa26 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA26"); + state->u.f4.fld.ffa1r.ffa27 = cm_object_get_child_by_name(state->u.f4.reg.ffa1r, "FFA27"); + + // FA1R bitfields. + state->u.f4.fld.fa1r.fact0 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT0"); + state->u.f4.fld.fa1r.fact1 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT1"); + state->u.f4.fld.fa1r.fact2 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT2"); + state->u.f4.fld.fa1r.fact3 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT3"); + state->u.f4.fld.fa1r.fact4 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT4"); + state->u.f4.fld.fa1r.fact5 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT5"); + state->u.f4.fld.fa1r.fact6 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT6"); + state->u.f4.fld.fa1r.fact7 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT7"); + state->u.f4.fld.fa1r.fact8 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT8"); + state->u.f4.fld.fa1r.fact9 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT9"); + state->u.f4.fld.fa1r.fact10 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT10"); + state->u.f4.fld.fa1r.fact11 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT11"); + state->u.f4.fld.fa1r.fact12 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT12"); + state->u.f4.fld.fa1r.fact13 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT13"); + state->u.f4.fld.fa1r.fact14 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT14"); + state->u.f4.fld.fa1r.fact15 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT15"); + state->u.f4.fld.fa1r.fact16 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT16"); + state->u.f4.fld.fa1r.fact17 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT17"); + state->u.f4.fld.fa1r.fact18 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT18"); + state->u.f4.fld.fa1r.fact19 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT19"); + state->u.f4.fld.fa1r.fact20 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT20"); + state->u.f4.fld.fa1r.fact21 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT21"); + state->u.f4.fld.fa1r.fact22 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT22"); + state->u.f4.fld.fa1r.fact23 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT23"); + state->u.f4.fld.fa1r.fact24 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT24"); + state->u.f4.fld.fa1r.fact25 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT25"); + state->u.f4.fld.fa1r.fact26 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT26"); + state->u.f4.fld.fa1r.fact27 = cm_object_get_child_by_name(state->u.f4.reg.fa1r, "FACT27"); + + // F0R1 bitfields. + state->u.f4.fld.f0r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB0"); + state->u.f4.fld.f0r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB1"); + state->u.f4.fld.f0r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB2"); + state->u.f4.fld.f0r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB3"); + state->u.f4.fld.f0r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB4"); + state->u.f4.fld.f0r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB5"); + state->u.f4.fld.f0r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB6"); + state->u.f4.fld.f0r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB7"); + state->u.f4.fld.f0r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB8"); + state->u.f4.fld.f0r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB9"); + state->u.f4.fld.f0r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB10"); + state->u.f4.fld.f0r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB11"); + state->u.f4.fld.f0r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB12"); + state->u.f4.fld.f0r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB13"); + state->u.f4.fld.f0r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB14"); + state->u.f4.fld.f0r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB15"); + state->u.f4.fld.f0r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB16"); + state->u.f4.fld.f0r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB17"); + state->u.f4.fld.f0r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB18"); + state->u.f4.fld.f0r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB19"); + state->u.f4.fld.f0r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB20"); + state->u.f4.fld.f0r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB21"); + state->u.f4.fld.f0r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB22"); + state->u.f4.fld.f0r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB23"); + state->u.f4.fld.f0r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB24"); + state->u.f4.fld.f0r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB25"); + state->u.f4.fld.f0r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB26"); + state->u.f4.fld.f0r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB27"); + state->u.f4.fld.f0r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB28"); + state->u.f4.fld.f0r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB29"); + state->u.f4.fld.f0r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB30"); + state->u.f4.fld.f0r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f0r1, "FB31"); + + // F0R2 bitfields. + state->u.f4.fld.f0r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB0"); + state->u.f4.fld.f0r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB1"); + state->u.f4.fld.f0r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB2"); + state->u.f4.fld.f0r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB3"); + state->u.f4.fld.f0r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB4"); + state->u.f4.fld.f0r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB5"); + state->u.f4.fld.f0r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB6"); + state->u.f4.fld.f0r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB7"); + state->u.f4.fld.f0r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB8"); + state->u.f4.fld.f0r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB9"); + state->u.f4.fld.f0r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB10"); + state->u.f4.fld.f0r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB11"); + state->u.f4.fld.f0r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB12"); + state->u.f4.fld.f0r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB13"); + state->u.f4.fld.f0r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB14"); + state->u.f4.fld.f0r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB15"); + state->u.f4.fld.f0r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB16"); + state->u.f4.fld.f0r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB17"); + state->u.f4.fld.f0r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB18"); + state->u.f4.fld.f0r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB19"); + state->u.f4.fld.f0r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB20"); + state->u.f4.fld.f0r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB21"); + state->u.f4.fld.f0r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB22"); + state->u.f4.fld.f0r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB23"); + state->u.f4.fld.f0r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB24"); + state->u.f4.fld.f0r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB25"); + state->u.f4.fld.f0r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB26"); + state->u.f4.fld.f0r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB27"); + state->u.f4.fld.f0r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB28"); + state->u.f4.fld.f0r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB29"); + state->u.f4.fld.f0r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB30"); + state->u.f4.fld.f0r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f0r2, "FB31"); + + // F1R1 bitfields. + state->u.f4.fld.f1r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB0"); + state->u.f4.fld.f1r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB1"); + state->u.f4.fld.f1r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB2"); + state->u.f4.fld.f1r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB3"); + state->u.f4.fld.f1r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB4"); + state->u.f4.fld.f1r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB5"); + state->u.f4.fld.f1r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB6"); + state->u.f4.fld.f1r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB7"); + state->u.f4.fld.f1r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB8"); + state->u.f4.fld.f1r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB9"); + state->u.f4.fld.f1r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB10"); + state->u.f4.fld.f1r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB11"); + state->u.f4.fld.f1r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB12"); + state->u.f4.fld.f1r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB13"); + state->u.f4.fld.f1r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB14"); + state->u.f4.fld.f1r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB15"); + state->u.f4.fld.f1r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB16"); + state->u.f4.fld.f1r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB17"); + state->u.f4.fld.f1r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB18"); + state->u.f4.fld.f1r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB19"); + state->u.f4.fld.f1r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB20"); + state->u.f4.fld.f1r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB21"); + state->u.f4.fld.f1r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB22"); + state->u.f4.fld.f1r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB23"); + state->u.f4.fld.f1r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB24"); + state->u.f4.fld.f1r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB25"); + state->u.f4.fld.f1r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB26"); + state->u.f4.fld.f1r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB27"); + state->u.f4.fld.f1r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB28"); + state->u.f4.fld.f1r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB29"); + state->u.f4.fld.f1r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB30"); + state->u.f4.fld.f1r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f1r1, "FB31"); + + // F1R2 bitfields. + state->u.f4.fld.f1r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB0"); + state->u.f4.fld.f1r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB1"); + state->u.f4.fld.f1r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB2"); + state->u.f4.fld.f1r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB3"); + state->u.f4.fld.f1r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB4"); + state->u.f4.fld.f1r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB5"); + state->u.f4.fld.f1r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB6"); + state->u.f4.fld.f1r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB7"); + state->u.f4.fld.f1r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB8"); + state->u.f4.fld.f1r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB9"); + state->u.f4.fld.f1r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB10"); + state->u.f4.fld.f1r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB11"); + state->u.f4.fld.f1r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB12"); + state->u.f4.fld.f1r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB13"); + state->u.f4.fld.f1r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB14"); + state->u.f4.fld.f1r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB15"); + state->u.f4.fld.f1r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB16"); + state->u.f4.fld.f1r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB17"); + state->u.f4.fld.f1r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB18"); + state->u.f4.fld.f1r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB19"); + state->u.f4.fld.f1r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB20"); + state->u.f4.fld.f1r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB21"); + state->u.f4.fld.f1r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB22"); + state->u.f4.fld.f1r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB23"); + state->u.f4.fld.f1r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB24"); + state->u.f4.fld.f1r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB25"); + state->u.f4.fld.f1r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB26"); + state->u.f4.fld.f1r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB27"); + state->u.f4.fld.f1r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB28"); + state->u.f4.fld.f1r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB29"); + state->u.f4.fld.f1r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB30"); + state->u.f4.fld.f1r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f1r2, "FB31"); + + // F2R1 bitfields. + state->u.f4.fld.f2r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB0"); + state->u.f4.fld.f2r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB1"); + state->u.f4.fld.f2r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB2"); + state->u.f4.fld.f2r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB3"); + state->u.f4.fld.f2r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB4"); + state->u.f4.fld.f2r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB5"); + state->u.f4.fld.f2r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB6"); + state->u.f4.fld.f2r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB7"); + state->u.f4.fld.f2r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB8"); + state->u.f4.fld.f2r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB9"); + state->u.f4.fld.f2r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB10"); + state->u.f4.fld.f2r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB11"); + state->u.f4.fld.f2r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB12"); + state->u.f4.fld.f2r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB13"); + state->u.f4.fld.f2r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB14"); + state->u.f4.fld.f2r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB15"); + state->u.f4.fld.f2r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB16"); + state->u.f4.fld.f2r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB17"); + state->u.f4.fld.f2r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB18"); + state->u.f4.fld.f2r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB19"); + state->u.f4.fld.f2r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB20"); + state->u.f4.fld.f2r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB21"); + state->u.f4.fld.f2r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB22"); + state->u.f4.fld.f2r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB23"); + state->u.f4.fld.f2r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB24"); + state->u.f4.fld.f2r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB25"); + state->u.f4.fld.f2r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB26"); + state->u.f4.fld.f2r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB27"); + state->u.f4.fld.f2r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB28"); + state->u.f4.fld.f2r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB29"); + state->u.f4.fld.f2r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB30"); + state->u.f4.fld.f2r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f2r1, "FB31"); + + // F2R2 bitfields. + state->u.f4.fld.f2r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB0"); + state->u.f4.fld.f2r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB1"); + state->u.f4.fld.f2r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB2"); + state->u.f4.fld.f2r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB3"); + state->u.f4.fld.f2r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB4"); + state->u.f4.fld.f2r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB5"); + state->u.f4.fld.f2r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB6"); + state->u.f4.fld.f2r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB7"); + state->u.f4.fld.f2r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB8"); + state->u.f4.fld.f2r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB9"); + state->u.f4.fld.f2r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB10"); + state->u.f4.fld.f2r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB11"); + state->u.f4.fld.f2r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB12"); + state->u.f4.fld.f2r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB13"); + state->u.f4.fld.f2r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB14"); + state->u.f4.fld.f2r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB15"); + state->u.f4.fld.f2r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB16"); + state->u.f4.fld.f2r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB17"); + state->u.f4.fld.f2r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB18"); + state->u.f4.fld.f2r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB19"); + state->u.f4.fld.f2r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB20"); + state->u.f4.fld.f2r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB21"); + state->u.f4.fld.f2r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB22"); + state->u.f4.fld.f2r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB23"); + state->u.f4.fld.f2r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB24"); + state->u.f4.fld.f2r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB25"); + state->u.f4.fld.f2r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB26"); + state->u.f4.fld.f2r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB27"); + state->u.f4.fld.f2r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB28"); + state->u.f4.fld.f2r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB29"); + state->u.f4.fld.f2r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB30"); + state->u.f4.fld.f2r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f2r2, "FB31"); + + // F3R1 bitfields. + state->u.f4.fld.f3r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB0"); + state->u.f4.fld.f3r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB1"); + state->u.f4.fld.f3r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB2"); + state->u.f4.fld.f3r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB3"); + state->u.f4.fld.f3r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB4"); + state->u.f4.fld.f3r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB5"); + state->u.f4.fld.f3r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB6"); + state->u.f4.fld.f3r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB7"); + state->u.f4.fld.f3r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB8"); + state->u.f4.fld.f3r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB9"); + state->u.f4.fld.f3r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB10"); + state->u.f4.fld.f3r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB11"); + state->u.f4.fld.f3r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB12"); + state->u.f4.fld.f3r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB13"); + state->u.f4.fld.f3r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB14"); + state->u.f4.fld.f3r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB15"); + state->u.f4.fld.f3r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB16"); + state->u.f4.fld.f3r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB17"); + state->u.f4.fld.f3r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB18"); + state->u.f4.fld.f3r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB19"); + state->u.f4.fld.f3r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB20"); + state->u.f4.fld.f3r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB21"); + state->u.f4.fld.f3r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB22"); + state->u.f4.fld.f3r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB23"); + state->u.f4.fld.f3r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB24"); + state->u.f4.fld.f3r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB25"); + state->u.f4.fld.f3r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB26"); + state->u.f4.fld.f3r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB27"); + state->u.f4.fld.f3r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB28"); + state->u.f4.fld.f3r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB29"); + state->u.f4.fld.f3r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB30"); + state->u.f4.fld.f3r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f3r1, "FB31"); + + // F3R2 bitfields. + state->u.f4.fld.f3r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB0"); + state->u.f4.fld.f3r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB1"); + state->u.f4.fld.f3r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB2"); + state->u.f4.fld.f3r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB3"); + state->u.f4.fld.f3r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB4"); + state->u.f4.fld.f3r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB5"); + state->u.f4.fld.f3r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB6"); + state->u.f4.fld.f3r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB7"); + state->u.f4.fld.f3r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB8"); + state->u.f4.fld.f3r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB9"); + state->u.f4.fld.f3r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB10"); + state->u.f4.fld.f3r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB11"); + state->u.f4.fld.f3r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB12"); + state->u.f4.fld.f3r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB13"); + state->u.f4.fld.f3r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB14"); + state->u.f4.fld.f3r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB15"); + state->u.f4.fld.f3r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB16"); + state->u.f4.fld.f3r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB17"); + state->u.f4.fld.f3r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB18"); + state->u.f4.fld.f3r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB19"); + state->u.f4.fld.f3r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB20"); + state->u.f4.fld.f3r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB21"); + state->u.f4.fld.f3r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB22"); + state->u.f4.fld.f3r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB23"); + state->u.f4.fld.f3r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB24"); + state->u.f4.fld.f3r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB25"); + state->u.f4.fld.f3r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB26"); + state->u.f4.fld.f3r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB27"); + state->u.f4.fld.f3r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB28"); + state->u.f4.fld.f3r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB29"); + state->u.f4.fld.f3r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB30"); + state->u.f4.fld.f3r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f3r2, "FB31"); + + // F4R1 bitfields. + state->u.f4.fld.f4r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB0"); + state->u.f4.fld.f4r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB1"); + state->u.f4.fld.f4r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB2"); + state->u.f4.fld.f4r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB3"); + state->u.f4.fld.f4r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB4"); + state->u.f4.fld.f4r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB5"); + state->u.f4.fld.f4r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB6"); + state->u.f4.fld.f4r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB7"); + state->u.f4.fld.f4r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB8"); + state->u.f4.fld.f4r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB9"); + state->u.f4.fld.f4r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB10"); + state->u.f4.fld.f4r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB11"); + state->u.f4.fld.f4r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB12"); + state->u.f4.fld.f4r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB13"); + state->u.f4.fld.f4r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB14"); + state->u.f4.fld.f4r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB15"); + state->u.f4.fld.f4r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB16"); + state->u.f4.fld.f4r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB17"); + state->u.f4.fld.f4r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB18"); + state->u.f4.fld.f4r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB19"); + state->u.f4.fld.f4r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB20"); + state->u.f4.fld.f4r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB21"); + state->u.f4.fld.f4r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB22"); + state->u.f4.fld.f4r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB23"); + state->u.f4.fld.f4r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB24"); + state->u.f4.fld.f4r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB25"); + state->u.f4.fld.f4r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB26"); + state->u.f4.fld.f4r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB27"); + state->u.f4.fld.f4r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB28"); + state->u.f4.fld.f4r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB29"); + state->u.f4.fld.f4r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB30"); + state->u.f4.fld.f4r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f4r1, "FB31"); + + // F4R2 bitfields. + state->u.f4.fld.f4r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB0"); + state->u.f4.fld.f4r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB1"); + state->u.f4.fld.f4r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB2"); + state->u.f4.fld.f4r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB3"); + state->u.f4.fld.f4r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB4"); + state->u.f4.fld.f4r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB5"); + state->u.f4.fld.f4r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB6"); + state->u.f4.fld.f4r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB7"); + state->u.f4.fld.f4r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB8"); + state->u.f4.fld.f4r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB9"); + state->u.f4.fld.f4r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB10"); + state->u.f4.fld.f4r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB11"); + state->u.f4.fld.f4r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB12"); + state->u.f4.fld.f4r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB13"); + state->u.f4.fld.f4r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB14"); + state->u.f4.fld.f4r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB15"); + state->u.f4.fld.f4r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB16"); + state->u.f4.fld.f4r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB17"); + state->u.f4.fld.f4r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB18"); + state->u.f4.fld.f4r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB19"); + state->u.f4.fld.f4r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB20"); + state->u.f4.fld.f4r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB21"); + state->u.f4.fld.f4r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB22"); + state->u.f4.fld.f4r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB23"); + state->u.f4.fld.f4r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB24"); + state->u.f4.fld.f4r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB25"); + state->u.f4.fld.f4r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB26"); + state->u.f4.fld.f4r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB27"); + state->u.f4.fld.f4r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB28"); + state->u.f4.fld.f4r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB29"); + state->u.f4.fld.f4r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB30"); + state->u.f4.fld.f4r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f4r2, "FB31"); + + // F5R1 bitfields. + state->u.f4.fld.f5r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB0"); + state->u.f4.fld.f5r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB1"); + state->u.f4.fld.f5r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB2"); + state->u.f4.fld.f5r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB3"); + state->u.f4.fld.f5r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB4"); + state->u.f4.fld.f5r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB5"); + state->u.f4.fld.f5r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB6"); + state->u.f4.fld.f5r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB7"); + state->u.f4.fld.f5r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB8"); + state->u.f4.fld.f5r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB9"); + state->u.f4.fld.f5r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB10"); + state->u.f4.fld.f5r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB11"); + state->u.f4.fld.f5r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB12"); + state->u.f4.fld.f5r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB13"); + state->u.f4.fld.f5r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB14"); + state->u.f4.fld.f5r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB15"); + state->u.f4.fld.f5r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB16"); + state->u.f4.fld.f5r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB17"); + state->u.f4.fld.f5r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB18"); + state->u.f4.fld.f5r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB19"); + state->u.f4.fld.f5r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB20"); + state->u.f4.fld.f5r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB21"); + state->u.f4.fld.f5r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB22"); + state->u.f4.fld.f5r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB23"); + state->u.f4.fld.f5r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB24"); + state->u.f4.fld.f5r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB25"); + state->u.f4.fld.f5r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB26"); + state->u.f4.fld.f5r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB27"); + state->u.f4.fld.f5r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB28"); + state->u.f4.fld.f5r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB29"); + state->u.f4.fld.f5r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB30"); + state->u.f4.fld.f5r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f5r1, "FB31"); + + // F5R2 bitfields. + state->u.f4.fld.f5r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB0"); + state->u.f4.fld.f5r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB1"); + state->u.f4.fld.f5r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB2"); + state->u.f4.fld.f5r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB3"); + state->u.f4.fld.f5r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB4"); + state->u.f4.fld.f5r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB5"); + state->u.f4.fld.f5r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB6"); + state->u.f4.fld.f5r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB7"); + state->u.f4.fld.f5r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB8"); + state->u.f4.fld.f5r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB9"); + state->u.f4.fld.f5r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB10"); + state->u.f4.fld.f5r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB11"); + state->u.f4.fld.f5r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB12"); + state->u.f4.fld.f5r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB13"); + state->u.f4.fld.f5r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB14"); + state->u.f4.fld.f5r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB15"); + state->u.f4.fld.f5r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB16"); + state->u.f4.fld.f5r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB17"); + state->u.f4.fld.f5r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB18"); + state->u.f4.fld.f5r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB19"); + state->u.f4.fld.f5r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB20"); + state->u.f4.fld.f5r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB21"); + state->u.f4.fld.f5r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB22"); + state->u.f4.fld.f5r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB23"); + state->u.f4.fld.f5r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB24"); + state->u.f4.fld.f5r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB25"); + state->u.f4.fld.f5r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB26"); + state->u.f4.fld.f5r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB27"); + state->u.f4.fld.f5r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB28"); + state->u.f4.fld.f5r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB29"); + state->u.f4.fld.f5r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB30"); + state->u.f4.fld.f5r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f5r2, "FB31"); + + // F6R1 bitfields. + state->u.f4.fld.f6r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB0"); + state->u.f4.fld.f6r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB1"); + state->u.f4.fld.f6r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB2"); + state->u.f4.fld.f6r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB3"); + state->u.f4.fld.f6r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB4"); + state->u.f4.fld.f6r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB5"); + state->u.f4.fld.f6r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB6"); + state->u.f4.fld.f6r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB7"); + state->u.f4.fld.f6r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB8"); + state->u.f4.fld.f6r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB9"); + state->u.f4.fld.f6r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB10"); + state->u.f4.fld.f6r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB11"); + state->u.f4.fld.f6r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB12"); + state->u.f4.fld.f6r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB13"); + state->u.f4.fld.f6r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB14"); + state->u.f4.fld.f6r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB15"); + state->u.f4.fld.f6r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB16"); + state->u.f4.fld.f6r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB17"); + state->u.f4.fld.f6r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB18"); + state->u.f4.fld.f6r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB19"); + state->u.f4.fld.f6r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB20"); + state->u.f4.fld.f6r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB21"); + state->u.f4.fld.f6r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB22"); + state->u.f4.fld.f6r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB23"); + state->u.f4.fld.f6r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB24"); + state->u.f4.fld.f6r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB25"); + state->u.f4.fld.f6r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB26"); + state->u.f4.fld.f6r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB27"); + state->u.f4.fld.f6r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB28"); + state->u.f4.fld.f6r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB29"); + state->u.f4.fld.f6r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB30"); + state->u.f4.fld.f6r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f6r1, "FB31"); + + // F6R2 bitfields. + state->u.f4.fld.f6r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB0"); + state->u.f4.fld.f6r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB1"); + state->u.f4.fld.f6r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB2"); + state->u.f4.fld.f6r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB3"); + state->u.f4.fld.f6r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB4"); + state->u.f4.fld.f6r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB5"); + state->u.f4.fld.f6r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB6"); + state->u.f4.fld.f6r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB7"); + state->u.f4.fld.f6r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB8"); + state->u.f4.fld.f6r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB9"); + state->u.f4.fld.f6r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB10"); + state->u.f4.fld.f6r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB11"); + state->u.f4.fld.f6r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB12"); + state->u.f4.fld.f6r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB13"); + state->u.f4.fld.f6r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB14"); + state->u.f4.fld.f6r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB15"); + state->u.f4.fld.f6r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB16"); + state->u.f4.fld.f6r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB17"); + state->u.f4.fld.f6r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB18"); + state->u.f4.fld.f6r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB19"); + state->u.f4.fld.f6r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB20"); + state->u.f4.fld.f6r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB21"); + state->u.f4.fld.f6r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB22"); + state->u.f4.fld.f6r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB23"); + state->u.f4.fld.f6r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB24"); + state->u.f4.fld.f6r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB25"); + state->u.f4.fld.f6r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB26"); + state->u.f4.fld.f6r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB27"); + state->u.f4.fld.f6r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB28"); + state->u.f4.fld.f6r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB29"); + state->u.f4.fld.f6r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB30"); + state->u.f4.fld.f6r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f6r2, "FB31"); + + // F7R1 bitfields. + state->u.f4.fld.f7r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB0"); + state->u.f4.fld.f7r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB1"); + state->u.f4.fld.f7r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB2"); + state->u.f4.fld.f7r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB3"); + state->u.f4.fld.f7r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB4"); + state->u.f4.fld.f7r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB5"); + state->u.f4.fld.f7r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB6"); + state->u.f4.fld.f7r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB7"); + state->u.f4.fld.f7r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB8"); + state->u.f4.fld.f7r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB9"); + state->u.f4.fld.f7r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB10"); + state->u.f4.fld.f7r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB11"); + state->u.f4.fld.f7r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB12"); + state->u.f4.fld.f7r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB13"); + state->u.f4.fld.f7r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB14"); + state->u.f4.fld.f7r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB15"); + state->u.f4.fld.f7r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB16"); + state->u.f4.fld.f7r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB17"); + state->u.f4.fld.f7r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB18"); + state->u.f4.fld.f7r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB19"); + state->u.f4.fld.f7r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB20"); + state->u.f4.fld.f7r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB21"); + state->u.f4.fld.f7r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB22"); + state->u.f4.fld.f7r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB23"); + state->u.f4.fld.f7r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB24"); + state->u.f4.fld.f7r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB25"); + state->u.f4.fld.f7r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB26"); + state->u.f4.fld.f7r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB27"); + state->u.f4.fld.f7r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB28"); + state->u.f4.fld.f7r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB29"); + state->u.f4.fld.f7r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB30"); + state->u.f4.fld.f7r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f7r1, "FB31"); + + // F7R2 bitfields. + state->u.f4.fld.f7r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB0"); + state->u.f4.fld.f7r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB1"); + state->u.f4.fld.f7r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB2"); + state->u.f4.fld.f7r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB3"); + state->u.f4.fld.f7r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB4"); + state->u.f4.fld.f7r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB5"); + state->u.f4.fld.f7r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB6"); + state->u.f4.fld.f7r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB7"); + state->u.f4.fld.f7r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB8"); + state->u.f4.fld.f7r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB9"); + state->u.f4.fld.f7r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB10"); + state->u.f4.fld.f7r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB11"); + state->u.f4.fld.f7r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB12"); + state->u.f4.fld.f7r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB13"); + state->u.f4.fld.f7r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB14"); + state->u.f4.fld.f7r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB15"); + state->u.f4.fld.f7r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB16"); + state->u.f4.fld.f7r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB17"); + state->u.f4.fld.f7r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB18"); + state->u.f4.fld.f7r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB19"); + state->u.f4.fld.f7r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB20"); + state->u.f4.fld.f7r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB21"); + state->u.f4.fld.f7r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB22"); + state->u.f4.fld.f7r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB23"); + state->u.f4.fld.f7r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB24"); + state->u.f4.fld.f7r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB25"); + state->u.f4.fld.f7r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB26"); + state->u.f4.fld.f7r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB27"); + state->u.f4.fld.f7r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB28"); + state->u.f4.fld.f7r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB29"); + state->u.f4.fld.f7r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB30"); + state->u.f4.fld.f7r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f7r2, "FB31"); + + // F8R1 bitfields. + state->u.f4.fld.f8r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB0"); + state->u.f4.fld.f8r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB1"); + state->u.f4.fld.f8r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB2"); + state->u.f4.fld.f8r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB3"); + state->u.f4.fld.f8r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB4"); + state->u.f4.fld.f8r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB5"); + state->u.f4.fld.f8r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB6"); + state->u.f4.fld.f8r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB7"); + state->u.f4.fld.f8r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB8"); + state->u.f4.fld.f8r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB9"); + state->u.f4.fld.f8r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB10"); + state->u.f4.fld.f8r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB11"); + state->u.f4.fld.f8r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB12"); + state->u.f4.fld.f8r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB13"); + state->u.f4.fld.f8r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB14"); + state->u.f4.fld.f8r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB15"); + state->u.f4.fld.f8r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB16"); + state->u.f4.fld.f8r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB17"); + state->u.f4.fld.f8r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB18"); + state->u.f4.fld.f8r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB19"); + state->u.f4.fld.f8r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB20"); + state->u.f4.fld.f8r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB21"); + state->u.f4.fld.f8r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB22"); + state->u.f4.fld.f8r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB23"); + state->u.f4.fld.f8r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB24"); + state->u.f4.fld.f8r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB25"); + state->u.f4.fld.f8r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB26"); + state->u.f4.fld.f8r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB27"); + state->u.f4.fld.f8r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB28"); + state->u.f4.fld.f8r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB29"); + state->u.f4.fld.f8r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB30"); + state->u.f4.fld.f8r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f8r1, "FB31"); + + // F8R2 bitfields. + state->u.f4.fld.f8r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB0"); + state->u.f4.fld.f8r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB1"); + state->u.f4.fld.f8r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB2"); + state->u.f4.fld.f8r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB3"); + state->u.f4.fld.f8r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB4"); + state->u.f4.fld.f8r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB5"); + state->u.f4.fld.f8r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB6"); + state->u.f4.fld.f8r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB7"); + state->u.f4.fld.f8r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB8"); + state->u.f4.fld.f8r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB9"); + state->u.f4.fld.f8r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB10"); + state->u.f4.fld.f8r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB11"); + state->u.f4.fld.f8r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB12"); + state->u.f4.fld.f8r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB13"); + state->u.f4.fld.f8r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB14"); + state->u.f4.fld.f8r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB15"); + state->u.f4.fld.f8r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB16"); + state->u.f4.fld.f8r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB17"); + state->u.f4.fld.f8r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB18"); + state->u.f4.fld.f8r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB19"); + state->u.f4.fld.f8r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB20"); + state->u.f4.fld.f8r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB21"); + state->u.f4.fld.f8r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB22"); + state->u.f4.fld.f8r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB23"); + state->u.f4.fld.f8r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB24"); + state->u.f4.fld.f8r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB25"); + state->u.f4.fld.f8r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB26"); + state->u.f4.fld.f8r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB27"); + state->u.f4.fld.f8r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB28"); + state->u.f4.fld.f8r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB29"); + state->u.f4.fld.f8r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB30"); + state->u.f4.fld.f8r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f8r2, "FB31"); + + // F9R1 bitfields. + state->u.f4.fld.f9r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB0"); + state->u.f4.fld.f9r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB1"); + state->u.f4.fld.f9r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB2"); + state->u.f4.fld.f9r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB3"); + state->u.f4.fld.f9r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB4"); + state->u.f4.fld.f9r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB5"); + state->u.f4.fld.f9r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB6"); + state->u.f4.fld.f9r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB7"); + state->u.f4.fld.f9r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB8"); + state->u.f4.fld.f9r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB9"); + state->u.f4.fld.f9r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB10"); + state->u.f4.fld.f9r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB11"); + state->u.f4.fld.f9r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB12"); + state->u.f4.fld.f9r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB13"); + state->u.f4.fld.f9r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB14"); + state->u.f4.fld.f9r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB15"); + state->u.f4.fld.f9r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB16"); + state->u.f4.fld.f9r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB17"); + state->u.f4.fld.f9r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB18"); + state->u.f4.fld.f9r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB19"); + state->u.f4.fld.f9r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB20"); + state->u.f4.fld.f9r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB21"); + state->u.f4.fld.f9r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB22"); + state->u.f4.fld.f9r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB23"); + state->u.f4.fld.f9r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB24"); + state->u.f4.fld.f9r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB25"); + state->u.f4.fld.f9r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB26"); + state->u.f4.fld.f9r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB27"); + state->u.f4.fld.f9r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB28"); + state->u.f4.fld.f9r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB29"); + state->u.f4.fld.f9r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB30"); + state->u.f4.fld.f9r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f9r1, "FB31"); + + // F9R2 bitfields. + state->u.f4.fld.f9r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB0"); + state->u.f4.fld.f9r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB1"); + state->u.f4.fld.f9r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB2"); + state->u.f4.fld.f9r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB3"); + state->u.f4.fld.f9r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB4"); + state->u.f4.fld.f9r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB5"); + state->u.f4.fld.f9r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB6"); + state->u.f4.fld.f9r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB7"); + state->u.f4.fld.f9r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB8"); + state->u.f4.fld.f9r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB9"); + state->u.f4.fld.f9r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB10"); + state->u.f4.fld.f9r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB11"); + state->u.f4.fld.f9r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB12"); + state->u.f4.fld.f9r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB13"); + state->u.f4.fld.f9r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB14"); + state->u.f4.fld.f9r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB15"); + state->u.f4.fld.f9r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB16"); + state->u.f4.fld.f9r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB17"); + state->u.f4.fld.f9r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB18"); + state->u.f4.fld.f9r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB19"); + state->u.f4.fld.f9r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB20"); + state->u.f4.fld.f9r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB21"); + state->u.f4.fld.f9r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB22"); + state->u.f4.fld.f9r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB23"); + state->u.f4.fld.f9r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB24"); + state->u.f4.fld.f9r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB25"); + state->u.f4.fld.f9r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB26"); + state->u.f4.fld.f9r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB27"); + state->u.f4.fld.f9r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB28"); + state->u.f4.fld.f9r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB29"); + state->u.f4.fld.f9r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB30"); + state->u.f4.fld.f9r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f9r2, "FB31"); + + // F10R1 bitfields. + state->u.f4.fld.f10r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB0"); + state->u.f4.fld.f10r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB1"); + state->u.f4.fld.f10r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB2"); + state->u.f4.fld.f10r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB3"); + state->u.f4.fld.f10r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB4"); + state->u.f4.fld.f10r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB5"); + state->u.f4.fld.f10r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB6"); + state->u.f4.fld.f10r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB7"); + state->u.f4.fld.f10r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB8"); + state->u.f4.fld.f10r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB9"); + state->u.f4.fld.f10r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB10"); + state->u.f4.fld.f10r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB11"); + state->u.f4.fld.f10r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB12"); + state->u.f4.fld.f10r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB13"); + state->u.f4.fld.f10r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB14"); + state->u.f4.fld.f10r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB15"); + state->u.f4.fld.f10r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB16"); + state->u.f4.fld.f10r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB17"); + state->u.f4.fld.f10r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB18"); + state->u.f4.fld.f10r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB19"); + state->u.f4.fld.f10r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB20"); + state->u.f4.fld.f10r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB21"); + state->u.f4.fld.f10r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB22"); + state->u.f4.fld.f10r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB23"); + state->u.f4.fld.f10r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB24"); + state->u.f4.fld.f10r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB25"); + state->u.f4.fld.f10r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB26"); + state->u.f4.fld.f10r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB27"); + state->u.f4.fld.f10r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB28"); + state->u.f4.fld.f10r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB29"); + state->u.f4.fld.f10r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB30"); + state->u.f4.fld.f10r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f10r1, "FB31"); + + // F10R2 bitfields. + state->u.f4.fld.f10r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB0"); + state->u.f4.fld.f10r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB1"); + state->u.f4.fld.f10r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB2"); + state->u.f4.fld.f10r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB3"); + state->u.f4.fld.f10r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB4"); + state->u.f4.fld.f10r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB5"); + state->u.f4.fld.f10r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB6"); + state->u.f4.fld.f10r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB7"); + state->u.f4.fld.f10r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB8"); + state->u.f4.fld.f10r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB9"); + state->u.f4.fld.f10r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB10"); + state->u.f4.fld.f10r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB11"); + state->u.f4.fld.f10r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB12"); + state->u.f4.fld.f10r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB13"); + state->u.f4.fld.f10r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB14"); + state->u.f4.fld.f10r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB15"); + state->u.f4.fld.f10r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB16"); + state->u.f4.fld.f10r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB17"); + state->u.f4.fld.f10r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB18"); + state->u.f4.fld.f10r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB19"); + state->u.f4.fld.f10r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB20"); + state->u.f4.fld.f10r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB21"); + state->u.f4.fld.f10r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB22"); + state->u.f4.fld.f10r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB23"); + state->u.f4.fld.f10r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB24"); + state->u.f4.fld.f10r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB25"); + state->u.f4.fld.f10r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB26"); + state->u.f4.fld.f10r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB27"); + state->u.f4.fld.f10r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB28"); + state->u.f4.fld.f10r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB29"); + state->u.f4.fld.f10r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB30"); + state->u.f4.fld.f10r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f10r2, "FB31"); + + // F11R1 bitfields. + state->u.f4.fld.f11r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB0"); + state->u.f4.fld.f11r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB1"); + state->u.f4.fld.f11r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB2"); + state->u.f4.fld.f11r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB3"); + state->u.f4.fld.f11r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB4"); + state->u.f4.fld.f11r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB5"); + state->u.f4.fld.f11r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB6"); + state->u.f4.fld.f11r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB7"); + state->u.f4.fld.f11r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB8"); + state->u.f4.fld.f11r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB9"); + state->u.f4.fld.f11r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB10"); + state->u.f4.fld.f11r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB11"); + state->u.f4.fld.f11r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB12"); + state->u.f4.fld.f11r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB13"); + state->u.f4.fld.f11r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB14"); + state->u.f4.fld.f11r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB15"); + state->u.f4.fld.f11r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB16"); + state->u.f4.fld.f11r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB17"); + state->u.f4.fld.f11r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB18"); + state->u.f4.fld.f11r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB19"); + state->u.f4.fld.f11r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB20"); + state->u.f4.fld.f11r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB21"); + state->u.f4.fld.f11r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB22"); + state->u.f4.fld.f11r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB23"); + state->u.f4.fld.f11r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB24"); + state->u.f4.fld.f11r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB25"); + state->u.f4.fld.f11r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB26"); + state->u.f4.fld.f11r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB27"); + state->u.f4.fld.f11r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB28"); + state->u.f4.fld.f11r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB29"); + state->u.f4.fld.f11r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB30"); + state->u.f4.fld.f11r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f11r1, "FB31"); + + // F11R2 bitfields. + state->u.f4.fld.f11r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB0"); + state->u.f4.fld.f11r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB1"); + state->u.f4.fld.f11r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB2"); + state->u.f4.fld.f11r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB3"); + state->u.f4.fld.f11r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB4"); + state->u.f4.fld.f11r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB5"); + state->u.f4.fld.f11r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB6"); + state->u.f4.fld.f11r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB7"); + state->u.f4.fld.f11r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB8"); + state->u.f4.fld.f11r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB9"); + state->u.f4.fld.f11r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB10"); + state->u.f4.fld.f11r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB11"); + state->u.f4.fld.f11r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB12"); + state->u.f4.fld.f11r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB13"); + state->u.f4.fld.f11r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB14"); + state->u.f4.fld.f11r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB15"); + state->u.f4.fld.f11r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB16"); + state->u.f4.fld.f11r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB17"); + state->u.f4.fld.f11r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB18"); + state->u.f4.fld.f11r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB19"); + state->u.f4.fld.f11r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB20"); + state->u.f4.fld.f11r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB21"); + state->u.f4.fld.f11r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB22"); + state->u.f4.fld.f11r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB23"); + state->u.f4.fld.f11r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB24"); + state->u.f4.fld.f11r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB25"); + state->u.f4.fld.f11r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB26"); + state->u.f4.fld.f11r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB27"); + state->u.f4.fld.f11r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB28"); + state->u.f4.fld.f11r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB29"); + state->u.f4.fld.f11r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB30"); + state->u.f4.fld.f11r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f11r2, "FB31"); + + // F12R1 bitfields. + state->u.f4.fld.f12r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB0"); + state->u.f4.fld.f12r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB1"); + state->u.f4.fld.f12r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB2"); + state->u.f4.fld.f12r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB3"); + state->u.f4.fld.f12r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB4"); + state->u.f4.fld.f12r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB5"); + state->u.f4.fld.f12r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB6"); + state->u.f4.fld.f12r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB7"); + state->u.f4.fld.f12r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB8"); + state->u.f4.fld.f12r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB9"); + state->u.f4.fld.f12r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB10"); + state->u.f4.fld.f12r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB11"); + state->u.f4.fld.f12r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB12"); + state->u.f4.fld.f12r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB13"); + state->u.f4.fld.f12r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB14"); + state->u.f4.fld.f12r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB15"); + state->u.f4.fld.f12r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB16"); + state->u.f4.fld.f12r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB17"); + state->u.f4.fld.f12r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB18"); + state->u.f4.fld.f12r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB19"); + state->u.f4.fld.f12r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB20"); + state->u.f4.fld.f12r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB21"); + state->u.f4.fld.f12r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB22"); + state->u.f4.fld.f12r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB23"); + state->u.f4.fld.f12r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB24"); + state->u.f4.fld.f12r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB25"); + state->u.f4.fld.f12r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB26"); + state->u.f4.fld.f12r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB27"); + state->u.f4.fld.f12r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB28"); + state->u.f4.fld.f12r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB29"); + state->u.f4.fld.f12r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB30"); + state->u.f4.fld.f12r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f12r1, "FB31"); + + // F12R2 bitfields. + state->u.f4.fld.f12r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB0"); + state->u.f4.fld.f12r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB1"); + state->u.f4.fld.f12r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB2"); + state->u.f4.fld.f12r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB3"); + state->u.f4.fld.f12r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB4"); + state->u.f4.fld.f12r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB5"); + state->u.f4.fld.f12r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB6"); + state->u.f4.fld.f12r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB7"); + state->u.f4.fld.f12r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB8"); + state->u.f4.fld.f12r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB9"); + state->u.f4.fld.f12r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB10"); + state->u.f4.fld.f12r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB11"); + state->u.f4.fld.f12r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB12"); + state->u.f4.fld.f12r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB13"); + state->u.f4.fld.f12r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB14"); + state->u.f4.fld.f12r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB15"); + state->u.f4.fld.f12r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB16"); + state->u.f4.fld.f12r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB17"); + state->u.f4.fld.f12r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB18"); + state->u.f4.fld.f12r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB19"); + state->u.f4.fld.f12r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB20"); + state->u.f4.fld.f12r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB21"); + state->u.f4.fld.f12r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB22"); + state->u.f4.fld.f12r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB23"); + state->u.f4.fld.f12r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB24"); + state->u.f4.fld.f12r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB25"); + state->u.f4.fld.f12r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB26"); + state->u.f4.fld.f12r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB27"); + state->u.f4.fld.f12r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB28"); + state->u.f4.fld.f12r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB29"); + state->u.f4.fld.f12r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB30"); + state->u.f4.fld.f12r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f12r2, "FB31"); + + // F13R1 bitfields. + state->u.f4.fld.f13r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB0"); + state->u.f4.fld.f13r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB1"); + state->u.f4.fld.f13r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB2"); + state->u.f4.fld.f13r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB3"); + state->u.f4.fld.f13r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB4"); + state->u.f4.fld.f13r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB5"); + state->u.f4.fld.f13r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB6"); + state->u.f4.fld.f13r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB7"); + state->u.f4.fld.f13r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB8"); + state->u.f4.fld.f13r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB9"); + state->u.f4.fld.f13r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB10"); + state->u.f4.fld.f13r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB11"); + state->u.f4.fld.f13r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB12"); + state->u.f4.fld.f13r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB13"); + state->u.f4.fld.f13r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB14"); + state->u.f4.fld.f13r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB15"); + state->u.f4.fld.f13r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB16"); + state->u.f4.fld.f13r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB17"); + state->u.f4.fld.f13r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB18"); + state->u.f4.fld.f13r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB19"); + state->u.f4.fld.f13r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB20"); + state->u.f4.fld.f13r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB21"); + state->u.f4.fld.f13r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB22"); + state->u.f4.fld.f13r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB23"); + state->u.f4.fld.f13r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB24"); + state->u.f4.fld.f13r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB25"); + state->u.f4.fld.f13r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB26"); + state->u.f4.fld.f13r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB27"); + state->u.f4.fld.f13r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB28"); + state->u.f4.fld.f13r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB29"); + state->u.f4.fld.f13r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB30"); + state->u.f4.fld.f13r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f13r1, "FB31"); + + // F13R2 bitfields. + state->u.f4.fld.f13r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB0"); + state->u.f4.fld.f13r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB1"); + state->u.f4.fld.f13r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB2"); + state->u.f4.fld.f13r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB3"); + state->u.f4.fld.f13r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB4"); + state->u.f4.fld.f13r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB5"); + state->u.f4.fld.f13r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB6"); + state->u.f4.fld.f13r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB7"); + state->u.f4.fld.f13r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB8"); + state->u.f4.fld.f13r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB9"); + state->u.f4.fld.f13r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB10"); + state->u.f4.fld.f13r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB11"); + state->u.f4.fld.f13r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB12"); + state->u.f4.fld.f13r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB13"); + state->u.f4.fld.f13r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB14"); + state->u.f4.fld.f13r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB15"); + state->u.f4.fld.f13r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB16"); + state->u.f4.fld.f13r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB17"); + state->u.f4.fld.f13r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB18"); + state->u.f4.fld.f13r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB19"); + state->u.f4.fld.f13r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB20"); + state->u.f4.fld.f13r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB21"); + state->u.f4.fld.f13r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB22"); + state->u.f4.fld.f13r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB23"); + state->u.f4.fld.f13r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB24"); + state->u.f4.fld.f13r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB25"); + state->u.f4.fld.f13r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB26"); + state->u.f4.fld.f13r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB27"); + state->u.f4.fld.f13r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB28"); + state->u.f4.fld.f13r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB29"); + state->u.f4.fld.f13r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB30"); + state->u.f4.fld.f13r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f13r2, "FB31"); + + // F14R1 bitfields. + state->u.f4.fld.f14r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB0"); + state->u.f4.fld.f14r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB1"); + state->u.f4.fld.f14r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB2"); + state->u.f4.fld.f14r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB3"); + state->u.f4.fld.f14r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB4"); + state->u.f4.fld.f14r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB5"); + state->u.f4.fld.f14r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB6"); + state->u.f4.fld.f14r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB7"); + state->u.f4.fld.f14r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB8"); + state->u.f4.fld.f14r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB9"); + state->u.f4.fld.f14r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB10"); + state->u.f4.fld.f14r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB11"); + state->u.f4.fld.f14r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB12"); + state->u.f4.fld.f14r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB13"); + state->u.f4.fld.f14r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB14"); + state->u.f4.fld.f14r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB15"); + state->u.f4.fld.f14r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB16"); + state->u.f4.fld.f14r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB17"); + state->u.f4.fld.f14r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB18"); + state->u.f4.fld.f14r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB19"); + state->u.f4.fld.f14r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB20"); + state->u.f4.fld.f14r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB21"); + state->u.f4.fld.f14r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB22"); + state->u.f4.fld.f14r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB23"); + state->u.f4.fld.f14r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB24"); + state->u.f4.fld.f14r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB25"); + state->u.f4.fld.f14r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB26"); + state->u.f4.fld.f14r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB27"); + state->u.f4.fld.f14r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB28"); + state->u.f4.fld.f14r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB29"); + state->u.f4.fld.f14r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB30"); + state->u.f4.fld.f14r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f14r1, "FB31"); + + // F14R2 bitfields. + state->u.f4.fld.f14r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB0"); + state->u.f4.fld.f14r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB1"); + state->u.f4.fld.f14r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB2"); + state->u.f4.fld.f14r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB3"); + state->u.f4.fld.f14r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB4"); + state->u.f4.fld.f14r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB5"); + state->u.f4.fld.f14r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB6"); + state->u.f4.fld.f14r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB7"); + state->u.f4.fld.f14r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB8"); + state->u.f4.fld.f14r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB9"); + state->u.f4.fld.f14r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB10"); + state->u.f4.fld.f14r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB11"); + state->u.f4.fld.f14r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB12"); + state->u.f4.fld.f14r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB13"); + state->u.f4.fld.f14r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB14"); + state->u.f4.fld.f14r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB15"); + state->u.f4.fld.f14r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB16"); + state->u.f4.fld.f14r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB17"); + state->u.f4.fld.f14r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB18"); + state->u.f4.fld.f14r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB19"); + state->u.f4.fld.f14r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB20"); + state->u.f4.fld.f14r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB21"); + state->u.f4.fld.f14r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB22"); + state->u.f4.fld.f14r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB23"); + state->u.f4.fld.f14r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB24"); + state->u.f4.fld.f14r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB25"); + state->u.f4.fld.f14r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB26"); + state->u.f4.fld.f14r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB27"); + state->u.f4.fld.f14r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB28"); + state->u.f4.fld.f14r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB29"); + state->u.f4.fld.f14r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB30"); + state->u.f4.fld.f14r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f14r2, "FB31"); + + // F15R1 bitfields. + state->u.f4.fld.f15r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB0"); + state->u.f4.fld.f15r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB1"); + state->u.f4.fld.f15r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB2"); + state->u.f4.fld.f15r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB3"); + state->u.f4.fld.f15r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB4"); + state->u.f4.fld.f15r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB5"); + state->u.f4.fld.f15r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB6"); + state->u.f4.fld.f15r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB7"); + state->u.f4.fld.f15r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB8"); + state->u.f4.fld.f15r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB9"); + state->u.f4.fld.f15r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB10"); + state->u.f4.fld.f15r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB11"); + state->u.f4.fld.f15r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB12"); + state->u.f4.fld.f15r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB13"); + state->u.f4.fld.f15r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB14"); + state->u.f4.fld.f15r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB15"); + state->u.f4.fld.f15r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB16"); + state->u.f4.fld.f15r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB17"); + state->u.f4.fld.f15r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB18"); + state->u.f4.fld.f15r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB19"); + state->u.f4.fld.f15r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB20"); + state->u.f4.fld.f15r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB21"); + state->u.f4.fld.f15r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB22"); + state->u.f4.fld.f15r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB23"); + state->u.f4.fld.f15r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB24"); + state->u.f4.fld.f15r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB25"); + state->u.f4.fld.f15r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB26"); + state->u.f4.fld.f15r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB27"); + state->u.f4.fld.f15r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB28"); + state->u.f4.fld.f15r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB29"); + state->u.f4.fld.f15r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB30"); + state->u.f4.fld.f15r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f15r1, "FB31"); + + // F15R2 bitfields. + state->u.f4.fld.f15r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB0"); + state->u.f4.fld.f15r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB1"); + state->u.f4.fld.f15r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB2"); + state->u.f4.fld.f15r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB3"); + state->u.f4.fld.f15r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB4"); + state->u.f4.fld.f15r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB5"); + state->u.f4.fld.f15r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB6"); + state->u.f4.fld.f15r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB7"); + state->u.f4.fld.f15r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB8"); + state->u.f4.fld.f15r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB9"); + state->u.f4.fld.f15r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB10"); + state->u.f4.fld.f15r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB11"); + state->u.f4.fld.f15r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB12"); + state->u.f4.fld.f15r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB13"); + state->u.f4.fld.f15r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB14"); + state->u.f4.fld.f15r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB15"); + state->u.f4.fld.f15r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB16"); + state->u.f4.fld.f15r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB17"); + state->u.f4.fld.f15r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB18"); + state->u.f4.fld.f15r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB19"); + state->u.f4.fld.f15r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB20"); + state->u.f4.fld.f15r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB21"); + state->u.f4.fld.f15r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB22"); + state->u.f4.fld.f15r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB23"); + state->u.f4.fld.f15r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB24"); + state->u.f4.fld.f15r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB25"); + state->u.f4.fld.f15r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB26"); + state->u.f4.fld.f15r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB27"); + state->u.f4.fld.f15r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB28"); + state->u.f4.fld.f15r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB29"); + state->u.f4.fld.f15r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB30"); + state->u.f4.fld.f15r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f15r2, "FB31"); + + // F16R1 bitfields. + state->u.f4.fld.f16r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB0"); + state->u.f4.fld.f16r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB1"); + state->u.f4.fld.f16r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB2"); + state->u.f4.fld.f16r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB3"); + state->u.f4.fld.f16r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB4"); + state->u.f4.fld.f16r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB5"); + state->u.f4.fld.f16r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB6"); + state->u.f4.fld.f16r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB7"); + state->u.f4.fld.f16r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB8"); + state->u.f4.fld.f16r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB9"); + state->u.f4.fld.f16r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB10"); + state->u.f4.fld.f16r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB11"); + state->u.f4.fld.f16r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB12"); + state->u.f4.fld.f16r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB13"); + state->u.f4.fld.f16r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB14"); + state->u.f4.fld.f16r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB15"); + state->u.f4.fld.f16r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB16"); + state->u.f4.fld.f16r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB17"); + state->u.f4.fld.f16r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB18"); + state->u.f4.fld.f16r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB19"); + state->u.f4.fld.f16r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB20"); + state->u.f4.fld.f16r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB21"); + state->u.f4.fld.f16r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB22"); + state->u.f4.fld.f16r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB23"); + state->u.f4.fld.f16r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB24"); + state->u.f4.fld.f16r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB25"); + state->u.f4.fld.f16r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB26"); + state->u.f4.fld.f16r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB27"); + state->u.f4.fld.f16r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB28"); + state->u.f4.fld.f16r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB29"); + state->u.f4.fld.f16r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB30"); + state->u.f4.fld.f16r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f16r1, "FB31"); + + // F16R2 bitfields. + state->u.f4.fld.f16r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB0"); + state->u.f4.fld.f16r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB1"); + state->u.f4.fld.f16r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB2"); + state->u.f4.fld.f16r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB3"); + state->u.f4.fld.f16r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB4"); + state->u.f4.fld.f16r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB5"); + state->u.f4.fld.f16r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB6"); + state->u.f4.fld.f16r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB7"); + state->u.f4.fld.f16r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB8"); + state->u.f4.fld.f16r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB9"); + state->u.f4.fld.f16r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB10"); + state->u.f4.fld.f16r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB11"); + state->u.f4.fld.f16r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB12"); + state->u.f4.fld.f16r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB13"); + state->u.f4.fld.f16r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB14"); + state->u.f4.fld.f16r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB15"); + state->u.f4.fld.f16r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB16"); + state->u.f4.fld.f16r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB17"); + state->u.f4.fld.f16r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB18"); + state->u.f4.fld.f16r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB19"); + state->u.f4.fld.f16r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB20"); + state->u.f4.fld.f16r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB21"); + state->u.f4.fld.f16r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB22"); + state->u.f4.fld.f16r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB23"); + state->u.f4.fld.f16r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB24"); + state->u.f4.fld.f16r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB25"); + state->u.f4.fld.f16r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB26"); + state->u.f4.fld.f16r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB27"); + state->u.f4.fld.f16r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB28"); + state->u.f4.fld.f16r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB29"); + state->u.f4.fld.f16r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB30"); + state->u.f4.fld.f16r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f16r2, "FB31"); + + // F17R1 bitfields. + state->u.f4.fld.f17r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB0"); + state->u.f4.fld.f17r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB1"); + state->u.f4.fld.f17r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB2"); + state->u.f4.fld.f17r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB3"); + state->u.f4.fld.f17r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB4"); + state->u.f4.fld.f17r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB5"); + state->u.f4.fld.f17r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB6"); + state->u.f4.fld.f17r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB7"); + state->u.f4.fld.f17r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB8"); + state->u.f4.fld.f17r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB9"); + state->u.f4.fld.f17r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB10"); + state->u.f4.fld.f17r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB11"); + state->u.f4.fld.f17r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB12"); + state->u.f4.fld.f17r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB13"); + state->u.f4.fld.f17r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB14"); + state->u.f4.fld.f17r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB15"); + state->u.f4.fld.f17r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB16"); + state->u.f4.fld.f17r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB17"); + state->u.f4.fld.f17r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB18"); + state->u.f4.fld.f17r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB19"); + state->u.f4.fld.f17r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB20"); + state->u.f4.fld.f17r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB21"); + state->u.f4.fld.f17r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB22"); + state->u.f4.fld.f17r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB23"); + state->u.f4.fld.f17r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB24"); + state->u.f4.fld.f17r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB25"); + state->u.f4.fld.f17r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB26"); + state->u.f4.fld.f17r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB27"); + state->u.f4.fld.f17r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB28"); + state->u.f4.fld.f17r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB29"); + state->u.f4.fld.f17r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB30"); + state->u.f4.fld.f17r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f17r1, "FB31"); + + // F17R2 bitfields. + state->u.f4.fld.f17r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB0"); + state->u.f4.fld.f17r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB1"); + state->u.f4.fld.f17r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB2"); + state->u.f4.fld.f17r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB3"); + state->u.f4.fld.f17r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB4"); + state->u.f4.fld.f17r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB5"); + state->u.f4.fld.f17r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB6"); + state->u.f4.fld.f17r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB7"); + state->u.f4.fld.f17r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB8"); + state->u.f4.fld.f17r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB9"); + state->u.f4.fld.f17r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB10"); + state->u.f4.fld.f17r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB11"); + state->u.f4.fld.f17r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB12"); + state->u.f4.fld.f17r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB13"); + state->u.f4.fld.f17r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB14"); + state->u.f4.fld.f17r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB15"); + state->u.f4.fld.f17r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB16"); + state->u.f4.fld.f17r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB17"); + state->u.f4.fld.f17r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB18"); + state->u.f4.fld.f17r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB19"); + state->u.f4.fld.f17r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB20"); + state->u.f4.fld.f17r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB21"); + state->u.f4.fld.f17r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB22"); + state->u.f4.fld.f17r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB23"); + state->u.f4.fld.f17r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB24"); + state->u.f4.fld.f17r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB25"); + state->u.f4.fld.f17r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB26"); + state->u.f4.fld.f17r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB27"); + state->u.f4.fld.f17r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB28"); + state->u.f4.fld.f17r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB29"); + state->u.f4.fld.f17r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB30"); + state->u.f4.fld.f17r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f17r2, "FB31"); + + // F18R1 bitfields. + state->u.f4.fld.f18r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB0"); + state->u.f4.fld.f18r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB1"); + state->u.f4.fld.f18r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB2"); + state->u.f4.fld.f18r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB3"); + state->u.f4.fld.f18r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB4"); + state->u.f4.fld.f18r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB5"); + state->u.f4.fld.f18r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB6"); + state->u.f4.fld.f18r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB7"); + state->u.f4.fld.f18r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB8"); + state->u.f4.fld.f18r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB9"); + state->u.f4.fld.f18r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB10"); + state->u.f4.fld.f18r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB11"); + state->u.f4.fld.f18r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB12"); + state->u.f4.fld.f18r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB13"); + state->u.f4.fld.f18r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB14"); + state->u.f4.fld.f18r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB15"); + state->u.f4.fld.f18r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB16"); + state->u.f4.fld.f18r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB17"); + state->u.f4.fld.f18r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB18"); + state->u.f4.fld.f18r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB19"); + state->u.f4.fld.f18r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB20"); + state->u.f4.fld.f18r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB21"); + state->u.f4.fld.f18r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB22"); + state->u.f4.fld.f18r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB23"); + state->u.f4.fld.f18r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB24"); + state->u.f4.fld.f18r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB25"); + state->u.f4.fld.f18r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB26"); + state->u.f4.fld.f18r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB27"); + state->u.f4.fld.f18r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB28"); + state->u.f4.fld.f18r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB29"); + state->u.f4.fld.f18r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB30"); + state->u.f4.fld.f18r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f18r1, "FB31"); + + // F18R2 bitfields. + state->u.f4.fld.f18r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB0"); + state->u.f4.fld.f18r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB1"); + state->u.f4.fld.f18r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB2"); + state->u.f4.fld.f18r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB3"); + state->u.f4.fld.f18r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB4"); + state->u.f4.fld.f18r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB5"); + state->u.f4.fld.f18r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB6"); + state->u.f4.fld.f18r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB7"); + state->u.f4.fld.f18r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB8"); + state->u.f4.fld.f18r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB9"); + state->u.f4.fld.f18r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB10"); + state->u.f4.fld.f18r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB11"); + state->u.f4.fld.f18r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB12"); + state->u.f4.fld.f18r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB13"); + state->u.f4.fld.f18r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB14"); + state->u.f4.fld.f18r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB15"); + state->u.f4.fld.f18r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB16"); + state->u.f4.fld.f18r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB17"); + state->u.f4.fld.f18r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB18"); + state->u.f4.fld.f18r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB19"); + state->u.f4.fld.f18r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB20"); + state->u.f4.fld.f18r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB21"); + state->u.f4.fld.f18r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB22"); + state->u.f4.fld.f18r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB23"); + state->u.f4.fld.f18r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB24"); + state->u.f4.fld.f18r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB25"); + state->u.f4.fld.f18r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB26"); + state->u.f4.fld.f18r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB27"); + state->u.f4.fld.f18r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB28"); + state->u.f4.fld.f18r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB29"); + state->u.f4.fld.f18r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB30"); + state->u.f4.fld.f18r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f18r2, "FB31"); + + // F19R1 bitfields. + state->u.f4.fld.f19r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB0"); + state->u.f4.fld.f19r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB1"); + state->u.f4.fld.f19r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB2"); + state->u.f4.fld.f19r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB3"); + state->u.f4.fld.f19r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB4"); + state->u.f4.fld.f19r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB5"); + state->u.f4.fld.f19r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB6"); + state->u.f4.fld.f19r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB7"); + state->u.f4.fld.f19r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB8"); + state->u.f4.fld.f19r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB9"); + state->u.f4.fld.f19r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB10"); + state->u.f4.fld.f19r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB11"); + state->u.f4.fld.f19r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB12"); + state->u.f4.fld.f19r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB13"); + state->u.f4.fld.f19r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB14"); + state->u.f4.fld.f19r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB15"); + state->u.f4.fld.f19r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB16"); + state->u.f4.fld.f19r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB17"); + state->u.f4.fld.f19r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB18"); + state->u.f4.fld.f19r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB19"); + state->u.f4.fld.f19r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB20"); + state->u.f4.fld.f19r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB21"); + state->u.f4.fld.f19r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB22"); + state->u.f4.fld.f19r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB23"); + state->u.f4.fld.f19r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB24"); + state->u.f4.fld.f19r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB25"); + state->u.f4.fld.f19r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB26"); + state->u.f4.fld.f19r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB27"); + state->u.f4.fld.f19r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB28"); + state->u.f4.fld.f19r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB29"); + state->u.f4.fld.f19r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB30"); + state->u.f4.fld.f19r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f19r1, "FB31"); + + // F19R2 bitfields. + state->u.f4.fld.f19r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB0"); + state->u.f4.fld.f19r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB1"); + state->u.f4.fld.f19r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB2"); + state->u.f4.fld.f19r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB3"); + state->u.f4.fld.f19r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB4"); + state->u.f4.fld.f19r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB5"); + state->u.f4.fld.f19r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB6"); + state->u.f4.fld.f19r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB7"); + state->u.f4.fld.f19r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB8"); + state->u.f4.fld.f19r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB9"); + state->u.f4.fld.f19r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB10"); + state->u.f4.fld.f19r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB11"); + state->u.f4.fld.f19r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB12"); + state->u.f4.fld.f19r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB13"); + state->u.f4.fld.f19r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB14"); + state->u.f4.fld.f19r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB15"); + state->u.f4.fld.f19r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB16"); + state->u.f4.fld.f19r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB17"); + state->u.f4.fld.f19r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB18"); + state->u.f4.fld.f19r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB19"); + state->u.f4.fld.f19r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB20"); + state->u.f4.fld.f19r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB21"); + state->u.f4.fld.f19r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB22"); + state->u.f4.fld.f19r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB23"); + state->u.f4.fld.f19r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB24"); + state->u.f4.fld.f19r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB25"); + state->u.f4.fld.f19r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB26"); + state->u.f4.fld.f19r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB27"); + state->u.f4.fld.f19r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB28"); + state->u.f4.fld.f19r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB29"); + state->u.f4.fld.f19r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB30"); + state->u.f4.fld.f19r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f19r2, "FB31"); + + // F20R1 bitfields. + state->u.f4.fld.f20r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB0"); + state->u.f4.fld.f20r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB1"); + state->u.f4.fld.f20r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB2"); + state->u.f4.fld.f20r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB3"); + state->u.f4.fld.f20r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB4"); + state->u.f4.fld.f20r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB5"); + state->u.f4.fld.f20r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB6"); + state->u.f4.fld.f20r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB7"); + state->u.f4.fld.f20r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB8"); + state->u.f4.fld.f20r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB9"); + state->u.f4.fld.f20r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB10"); + state->u.f4.fld.f20r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB11"); + state->u.f4.fld.f20r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB12"); + state->u.f4.fld.f20r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB13"); + state->u.f4.fld.f20r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB14"); + state->u.f4.fld.f20r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB15"); + state->u.f4.fld.f20r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB16"); + state->u.f4.fld.f20r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB17"); + state->u.f4.fld.f20r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB18"); + state->u.f4.fld.f20r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB19"); + state->u.f4.fld.f20r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB20"); + state->u.f4.fld.f20r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB21"); + state->u.f4.fld.f20r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB22"); + state->u.f4.fld.f20r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB23"); + state->u.f4.fld.f20r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB24"); + state->u.f4.fld.f20r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB25"); + state->u.f4.fld.f20r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB26"); + state->u.f4.fld.f20r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB27"); + state->u.f4.fld.f20r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB28"); + state->u.f4.fld.f20r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB29"); + state->u.f4.fld.f20r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB30"); + state->u.f4.fld.f20r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f20r1, "FB31"); + + // F20R2 bitfields. + state->u.f4.fld.f20r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB0"); + state->u.f4.fld.f20r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB1"); + state->u.f4.fld.f20r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB2"); + state->u.f4.fld.f20r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB3"); + state->u.f4.fld.f20r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB4"); + state->u.f4.fld.f20r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB5"); + state->u.f4.fld.f20r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB6"); + state->u.f4.fld.f20r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB7"); + state->u.f4.fld.f20r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB8"); + state->u.f4.fld.f20r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB9"); + state->u.f4.fld.f20r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB10"); + state->u.f4.fld.f20r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB11"); + state->u.f4.fld.f20r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB12"); + state->u.f4.fld.f20r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB13"); + state->u.f4.fld.f20r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB14"); + state->u.f4.fld.f20r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB15"); + state->u.f4.fld.f20r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB16"); + state->u.f4.fld.f20r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB17"); + state->u.f4.fld.f20r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB18"); + state->u.f4.fld.f20r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB19"); + state->u.f4.fld.f20r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB20"); + state->u.f4.fld.f20r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB21"); + state->u.f4.fld.f20r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB22"); + state->u.f4.fld.f20r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB23"); + state->u.f4.fld.f20r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB24"); + state->u.f4.fld.f20r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB25"); + state->u.f4.fld.f20r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB26"); + state->u.f4.fld.f20r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB27"); + state->u.f4.fld.f20r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB28"); + state->u.f4.fld.f20r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB29"); + state->u.f4.fld.f20r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB30"); + state->u.f4.fld.f20r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f20r2, "FB31"); + + // F21R1 bitfields. + state->u.f4.fld.f21r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB0"); + state->u.f4.fld.f21r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB1"); + state->u.f4.fld.f21r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB2"); + state->u.f4.fld.f21r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB3"); + state->u.f4.fld.f21r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB4"); + state->u.f4.fld.f21r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB5"); + state->u.f4.fld.f21r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB6"); + state->u.f4.fld.f21r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB7"); + state->u.f4.fld.f21r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB8"); + state->u.f4.fld.f21r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB9"); + state->u.f4.fld.f21r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB10"); + state->u.f4.fld.f21r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB11"); + state->u.f4.fld.f21r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB12"); + state->u.f4.fld.f21r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB13"); + state->u.f4.fld.f21r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB14"); + state->u.f4.fld.f21r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB15"); + state->u.f4.fld.f21r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB16"); + state->u.f4.fld.f21r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB17"); + state->u.f4.fld.f21r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB18"); + state->u.f4.fld.f21r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB19"); + state->u.f4.fld.f21r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB20"); + state->u.f4.fld.f21r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB21"); + state->u.f4.fld.f21r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB22"); + state->u.f4.fld.f21r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB23"); + state->u.f4.fld.f21r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB24"); + state->u.f4.fld.f21r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB25"); + state->u.f4.fld.f21r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB26"); + state->u.f4.fld.f21r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB27"); + state->u.f4.fld.f21r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB28"); + state->u.f4.fld.f21r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB29"); + state->u.f4.fld.f21r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB30"); + state->u.f4.fld.f21r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f21r1, "FB31"); + + // F21R2 bitfields. + state->u.f4.fld.f21r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB0"); + state->u.f4.fld.f21r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB1"); + state->u.f4.fld.f21r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB2"); + state->u.f4.fld.f21r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB3"); + state->u.f4.fld.f21r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB4"); + state->u.f4.fld.f21r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB5"); + state->u.f4.fld.f21r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB6"); + state->u.f4.fld.f21r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB7"); + state->u.f4.fld.f21r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB8"); + state->u.f4.fld.f21r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB9"); + state->u.f4.fld.f21r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB10"); + state->u.f4.fld.f21r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB11"); + state->u.f4.fld.f21r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB12"); + state->u.f4.fld.f21r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB13"); + state->u.f4.fld.f21r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB14"); + state->u.f4.fld.f21r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB15"); + state->u.f4.fld.f21r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB16"); + state->u.f4.fld.f21r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB17"); + state->u.f4.fld.f21r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB18"); + state->u.f4.fld.f21r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB19"); + state->u.f4.fld.f21r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB20"); + state->u.f4.fld.f21r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB21"); + state->u.f4.fld.f21r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB22"); + state->u.f4.fld.f21r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB23"); + state->u.f4.fld.f21r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB24"); + state->u.f4.fld.f21r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB25"); + state->u.f4.fld.f21r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB26"); + state->u.f4.fld.f21r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB27"); + state->u.f4.fld.f21r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB28"); + state->u.f4.fld.f21r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB29"); + state->u.f4.fld.f21r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB30"); + state->u.f4.fld.f21r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f21r2, "FB31"); + + // F22R1 bitfields. + state->u.f4.fld.f22r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB0"); + state->u.f4.fld.f22r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB1"); + state->u.f4.fld.f22r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB2"); + state->u.f4.fld.f22r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB3"); + state->u.f4.fld.f22r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB4"); + state->u.f4.fld.f22r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB5"); + state->u.f4.fld.f22r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB6"); + state->u.f4.fld.f22r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB7"); + state->u.f4.fld.f22r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB8"); + state->u.f4.fld.f22r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB9"); + state->u.f4.fld.f22r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB10"); + state->u.f4.fld.f22r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB11"); + state->u.f4.fld.f22r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB12"); + state->u.f4.fld.f22r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB13"); + state->u.f4.fld.f22r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB14"); + state->u.f4.fld.f22r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB15"); + state->u.f4.fld.f22r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB16"); + state->u.f4.fld.f22r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB17"); + state->u.f4.fld.f22r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB18"); + state->u.f4.fld.f22r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB19"); + state->u.f4.fld.f22r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB20"); + state->u.f4.fld.f22r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB21"); + state->u.f4.fld.f22r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB22"); + state->u.f4.fld.f22r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB23"); + state->u.f4.fld.f22r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB24"); + state->u.f4.fld.f22r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB25"); + state->u.f4.fld.f22r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB26"); + state->u.f4.fld.f22r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB27"); + state->u.f4.fld.f22r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB28"); + state->u.f4.fld.f22r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB29"); + state->u.f4.fld.f22r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB30"); + state->u.f4.fld.f22r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f22r1, "FB31"); + + // F22R2 bitfields. + state->u.f4.fld.f22r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB0"); + state->u.f4.fld.f22r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB1"); + state->u.f4.fld.f22r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB2"); + state->u.f4.fld.f22r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB3"); + state->u.f4.fld.f22r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB4"); + state->u.f4.fld.f22r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB5"); + state->u.f4.fld.f22r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB6"); + state->u.f4.fld.f22r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB7"); + state->u.f4.fld.f22r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB8"); + state->u.f4.fld.f22r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB9"); + state->u.f4.fld.f22r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB10"); + state->u.f4.fld.f22r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB11"); + state->u.f4.fld.f22r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB12"); + state->u.f4.fld.f22r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB13"); + state->u.f4.fld.f22r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB14"); + state->u.f4.fld.f22r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB15"); + state->u.f4.fld.f22r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB16"); + state->u.f4.fld.f22r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB17"); + state->u.f4.fld.f22r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB18"); + state->u.f4.fld.f22r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB19"); + state->u.f4.fld.f22r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB20"); + state->u.f4.fld.f22r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB21"); + state->u.f4.fld.f22r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB22"); + state->u.f4.fld.f22r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB23"); + state->u.f4.fld.f22r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB24"); + state->u.f4.fld.f22r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB25"); + state->u.f4.fld.f22r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB26"); + state->u.f4.fld.f22r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB27"); + state->u.f4.fld.f22r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB28"); + state->u.f4.fld.f22r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB29"); + state->u.f4.fld.f22r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB30"); + state->u.f4.fld.f22r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f22r2, "FB31"); + + // F23R1 bitfields. + state->u.f4.fld.f23r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB0"); + state->u.f4.fld.f23r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB1"); + state->u.f4.fld.f23r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB2"); + state->u.f4.fld.f23r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB3"); + state->u.f4.fld.f23r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB4"); + state->u.f4.fld.f23r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB5"); + state->u.f4.fld.f23r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB6"); + state->u.f4.fld.f23r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB7"); + state->u.f4.fld.f23r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB8"); + state->u.f4.fld.f23r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB9"); + state->u.f4.fld.f23r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB10"); + state->u.f4.fld.f23r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB11"); + state->u.f4.fld.f23r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB12"); + state->u.f4.fld.f23r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB13"); + state->u.f4.fld.f23r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB14"); + state->u.f4.fld.f23r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB15"); + state->u.f4.fld.f23r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB16"); + state->u.f4.fld.f23r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB17"); + state->u.f4.fld.f23r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB18"); + state->u.f4.fld.f23r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB19"); + state->u.f4.fld.f23r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB20"); + state->u.f4.fld.f23r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB21"); + state->u.f4.fld.f23r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB22"); + state->u.f4.fld.f23r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB23"); + state->u.f4.fld.f23r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB24"); + state->u.f4.fld.f23r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB25"); + state->u.f4.fld.f23r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB26"); + state->u.f4.fld.f23r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB27"); + state->u.f4.fld.f23r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB28"); + state->u.f4.fld.f23r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB29"); + state->u.f4.fld.f23r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB30"); + state->u.f4.fld.f23r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f23r1, "FB31"); + + // F23R2 bitfields. + state->u.f4.fld.f23r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB0"); + state->u.f4.fld.f23r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB1"); + state->u.f4.fld.f23r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB2"); + state->u.f4.fld.f23r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB3"); + state->u.f4.fld.f23r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB4"); + state->u.f4.fld.f23r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB5"); + state->u.f4.fld.f23r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB6"); + state->u.f4.fld.f23r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB7"); + state->u.f4.fld.f23r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB8"); + state->u.f4.fld.f23r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB9"); + state->u.f4.fld.f23r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB10"); + state->u.f4.fld.f23r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB11"); + state->u.f4.fld.f23r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB12"); + state->u.f4.fld.f23r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB13"); + state->u.f4.fld.f23r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB14"); + state->u.f4.fld.f23r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB15"); + state->u.f4.fld.f23r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB16"); + state->u.f4.fld.f23r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB17"); + state->u.f4.fld.f23r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB18"); + state->u.f4.fld.f23r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB19"); + state->u.f4.fld.f23r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB20"); + state->u.f4.fld.f23r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB21"); + state->u.f4.fld.f23r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB22"); + state->u.f4.fld.f23r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB23"); + state->u.f4.fld.f23r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB24"); + state->u.f4.fld.f23r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB25"); + state->u.f4.fld.f23r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB26"); + state->u.f4.fld.f23r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB27"); + state->u.f4.fld.f23r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB28"); + state->u.f4.fld.f23r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB29"); + state->u.f4.fld.f23r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB30"); + state->u.f4.fld.f23r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f23r2, "FB31"); + + // F24R1 bitfields. + state->u.f4.fld.f24r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB0"); + state->u.f4.fld.f24r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB1"); + state->u.f4.fld.f24r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB2"); + state->u.f4.fld.f24r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB3"); + state->u.f4.fld.f24r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB4"); + state->u.f4.fld.f24r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB5"); + state->u.f4.fld.f24r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB6"); + state->u.f4.fld.f24r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB7"); + state->u.f4.fld.f24r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB8"); + state->u.f4.fld.f24r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB9"); + state->u.f4.fld.f24r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB10"); + state->u.f4.fld.f24r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB11"); + state->u.f4.fld.f24r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB12"); + state->u.f4.fld.f24r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB13"); + state->u.f4.fld.f24r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB14"); + state->u.f4.fld.f24r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB15"); + state->u.f4.fld.f24r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB16"); + state->u.f4.fld.f24r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB17"); + state->u.f4.fld.f24r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB18"); + state->u.f4.fld.f24r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB19"); + state->u.f4.fld.f24r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB20"); + state->u.f4.fld.f24r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB21"); + state->u.f4.fld.f24r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB22"); + state->u.f4.fld.f24r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB23"); + state->u.f4.fld.f24r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB24"); + state->u.f4.fld.f24r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB25"); + state->u.f4.fld.f24r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB26"); + state->u.f4.fld.f24r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB27"); + state->u.f4.fld.f24r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB28"); + state->u.f4.fld.f24r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB29"); + state->u.f4.fld.f24r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB30"); + state->u.f4.fld.f24r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f24r1, "FB31"); + + // F24R2 bitfields. + state->u.f4.fld.f24r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB0"); + state->u.f4.fld.f24r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB1"); + state->u.f4.fld.f24r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB2"); + state->u.f4.fld.f24r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB3"); + state->u.f4.fld.f24r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB4"); + state->u.f4.fld.f24r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB5"); + state->u.f4.fld.f24r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB6"); + state->u.f4.fld.f24r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB7"); + state->u.f4.fld.f24r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB8"); + state->u.f4.fld.f24r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB9"); + state->u.f4.fld.f24r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB10"); + state->u.f4.fld.f24r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB11"); + state->u.f4.fld.f24r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB12"); + state->u.f4.fld.f24r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB13"); + state->u.f4.fld.f24r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB14"); + state->u.f4.fld.f24r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB15"); + state->u.f4.fld.f24r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB16"); + state->u.f4.fld.f24r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB17"); + state->u.f4.fld.f24r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB18"); + state->u.f4.fld.f24r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB19"); + state->u.f4.fld.f24r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB20"); + state->u.f4.fld.f24r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB21"); + state->u.f4.fld.f24r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB22"); + state->u.f4.fld.f24r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB23"); + state->u.f4.fld.f24r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB24"); + state->u.f4.fld.f24r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB25"); + state->u.f4.fld.f24r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB26"); + state->u.f4.fld.f24r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB27"); + state->u.f4.fld.f24r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB28"); + state->u.f4.fld.f24r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB29"); + state->u.f4.fld.f24r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB30"); + state->u.f4.fld.f24r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f24r2, "FB31"); + + // F25R1 bitfields. + state->u.f4.fld.f25r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB0"); + state->u.f4.fld.f25r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB1"); + state->u.f4.fld.f25r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB2"); + state->u.f4.fld.f25r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB3"); + state->u.f4.fld.f25r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB4"); + state->u.f4.fld.f25r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB5"); + state->u.f4.fld.f25r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB6"); + state->u.f4.fld.f25r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB7"); + state->u.f4.fld.f25r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB8"); + state->u.f4.fld.f25r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB9"); + state->u.f4.fld.f25r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB10"); + state->u.f4.fld.f25r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB11"); + state->u.f4.fld.f25r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB12"); + state->u.f4.fld.f25r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB13"); + state->u.f4.fld.f25r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB14"); + state->u.f4.fld.f25r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB15"); + state->u.f4.fld.f25r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB16"); + state->u.f4.fld.f25r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB17"); + state->u.f4.fld.f25r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB18"); + state->u.f4.fld.f25r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB19"); + state->u.f4.fld.f25r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB20"); + state->u.f4.fld.f25r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB21"); + state->u.f4.fld.f25r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB22"); + state->u.f4.fld.f25r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB23"); + state->u.f4.fld.f25r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB24"); + state->u.f4.fld.f25r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB25"); + state->u.f4.fld.f25r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB26"); + state->u.f4.fld.f25r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB27"); + state->u.f4.fld.f25r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB28"); + state->u.f4.fld.f25r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB29"); + state->u.f4.fld.f25r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB30"); + state->u.f4.fld.f25r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f25r1, "FB31"); + + // F25R2 bitfields. + state->u.f4.fld.f25r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB0"); + state->u.f4.fld.f25r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB1"); + state->u.f4.fld.f25r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB2"); + state->u.f4.fld.f25r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB3"); + state->u.f4.fld.f25r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB4"); + state->u.f4.fld.f25r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB5"); + state->u.f4.fld.f25r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB6"); + state->u.f4.fld.f25r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB7"); + state->u.f4.fld.f25r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB8"); + state->u.f4.fld.f25r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB9"); + state->u.f4.fld.f25r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB10"); + state->u.f4.fld.f25r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB11"); + state->u.f4.fld.f25r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB12"); + state->u.f4.fld.f25r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB13"); + state->u.f4.fld.f25r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB14"); + state->u.f4.fld.f25r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB15"); + state->u.f4.fld.f25r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB16"); + state->u.f4.fld.f25r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB17"); + state->u.f4.fld.f25r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB18"); + state->u.f4.fld.f25r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB19"); + state->u.f4.fld.f25r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB20"); + state->u.f4.fld.f25r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB21"); + state->u.f4.fld.f25r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB22"); + state->u.f4.fld.f25r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB23"); + state->u.f4.fld.f25r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB24"); + state->u.f4.fld.f25r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB25"); + state->u.f4.fld.f25r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB26"); + state->u.f4.fld.f25r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB27"); + state->u.f4.fld.f25r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB28"); + state->u.f4.fld.f25r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB29"); + state->u.f4.fld.f25r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB30"); + state->u.f4.fld.f25r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f25r2, "FB31"); + + // F26R1 bitfields. + state->u.f4.fld.f26r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB0"); + state->u.f4.fld.f26r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB1"); + state->u.f4.fld.f26r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB2"); + state->u.f4.fld.f26r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB3"); + state->u.f4.fld.f26r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB4"); + state->u.f4.fld.f26r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB5"); + state->u.f4.fld.f26r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB6"); + state->u.f4.fld.f26r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB7"); + state->u.f4.fld.f26r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB8"); + state->u.f4.fld.f26r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB9"); + state->u.f4.fld.f26r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB10"); + state->u.f4.fld.f26r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB11"); + state->u.f4.fld.f26r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB12"); + state->u.f4.fld.f26r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB13"); + state->u.f4.fld.f26r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB14"); + state->u.f4.fld.f26r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB15"); + state->u.f4.fld.f26r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB16"); + state->u.f4.fld.f26r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB17"); + state->u.f4.fld.f26r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB18"); + state->u.f4.fld.f26r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB19"); + state->u.f4.fld.f26r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB20"); + state->u.f4.fld.f26r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB21"); + state->u.f4.fld.f26r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB22"); + state->u.f4.fld.f26r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB23"); + state->u.f4.fld.f26r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB24"); + state->u.f4.fld.f26r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB25"); + state->u.f4.fld.f26r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB26"); + state->u.f4.fld.f26r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB27"); + state->u.f4.fld.f26r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB28"); + state->u.f4.fld.f26r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB29"); + state->u.f4.fld.f26r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB30"); + state->u.f4.fld.f26r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f26r1, "FB31"); + + // F26R2 bitfields. + state->u.f4.fld.f26r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB0"); + state->u.f4.fld.f26r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB1"); + state->u.f4.fld.f26r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB2"); + state->u.f4.fld.f26r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB3"); + state->u.f4.fld.f26r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB4"); + state->u.f4.fld.f26r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB5"); + state->u.f4.fld.f26r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB6"); + state->u.f4.fld.f26r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB7"); + state->u.f4.fld.f26r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB8"); + state->u.f4.fld.f26r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB9"); + state->u.f4.fld.f26r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB10"); + state->u.f4.fld.f26r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB11"); + state->u.f4.fld.f26r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB12"); + state->u.f4.fld.f26r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB13"); + state->u.f4.fld.f26r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB14"); + state->u.f4.fld.f26r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB15"); + state->u.f4.fld.f26r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB16"); + state->u.f4.fld.f26r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB17"); + state->u.f4.fld.f26r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB18"); + state->u.f4.fld.f26r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB19"); + state->u.f4.fld.f26r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB20"); + state->u.f4.fld.f26r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB21"); + state->u.f4.fld.f26r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB22"); + state->u.f4.fld.f26r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB23"); + state->u.f4.fld.f26r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB24"); + state->u.f4.fld.f26r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB25"); + state->u.f4.fld.f26r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB26"); + state->u.f4.fld.f26r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB27"); + state->u.f4.fld.f26r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB28"); + state->u.f4.fld.f26r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB29"); + state->u.f4.fld.f26r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB30"); + state->u.f4.fld.f26r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f26r2, "FB31"); + + // F27R1 bitfields. + state->u.f4.fld.f27r1.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB0"); + state->u.f4.fld.f27r1.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB1"); + state->u.f4.fld.f27r1.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB2"); + state->u.f4.fld.f27r1.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB3"); + state->u.f4.fld.f27r1.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB4"); + state->u.f4.fld.f27r1.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB5"); + state->u.f4.fld.f27r1.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB6"); + state->u.f4.fld.f27r1.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB7"); + state->u.f4.fld.f27r1.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB8"); + state->u.f4.fld.f27r1.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB9"); + state->u.f4.fld.f27r1.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB10"); + state->u.f4.fld.f27r1.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB11"); + state->u.f4.fld.f27r1.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB12"); + state->u.f4.fld.f27r1.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB13"); + state->u.f4.fld.f27r1.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB14"); + state->u.f4.fld.f27r1.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB15"); + state->u.f4.fld.f27r1.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB16"); + state->u.f4.fld.f27r1.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB17"); + state->u.f4.fld.f27r1.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB18"); + state->u.f4.fld.f27r1.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB19"); + state->u.f4.fld.f27r1.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB20"); + state->u.f4.fld.f27r1.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB21"); + state->u.f4.fld.f27r1.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB22"); + state->u.f4.fld.f27r1.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB23"); + state->u.f4.fld.f27r1.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB24"); + state->u.f4.fld.f27r1.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB25"); + state->u.f4.fld.f27r1.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB26"); + state->u.f4.fld.f27r1.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB27"); + state->u.f4.fld.f27r1.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB28"); + state->u.f4.fld.f27r1.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB29"); + state->u.f4.fld.f27r1.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB30"); + state->u.f4.fld.f27r1.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f27r1, "FB31"); + + // F27R2 bitfields. + state->u.f4.fld.f27r2.fb0 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB0"); + state->u.f4.fld.f27r2.fb1 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB1"); + state->u.f4.fld.f27r2.fb2 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB2"); + state->u.f4.fld.f27r2.fb3 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB3"); + state->u.f4.fld.f27r2.fb4 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB4"); + state->u.f4.fld.f27r2.fb5 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB5"); + state->u.f4.fld.f27r2.fb6 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB6"); + state->u.f4.fld.f27r2.fb7 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB7"); + state->u.f4.fld.f27r2.fb8 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB8"); + state->u.f4.fld.f27r2.fb9 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB9"); + state->u.f4.fld.f27r2.fb10 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB10"); + state->u.f4.fld.f27r2.fb11 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB11"); + state->u.f4.fld.f27r2.fb12 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB12"); + state->u.f4.fld.f27r2.fb13 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB13"); + state->u.f4.fld.f27r2.fb14 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB14"); + state->u.f4.fld.f27r2.fb15 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB15"); + state->u.f4.fld.f27r2.fb16 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB16"); + state->u.f4.fld.f27r2.fb17 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB17"); + state->u.f4.fld.f27r2.fb18 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB18"); + state->u.f4.fld.f27r2.fb19 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB19"); + state->u.f4.fld.f27r2.fb20 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB20"); + state->u.f4.fld.f27r2.fb21 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB21"); + state->u.f4.fld.f27r2.fb22 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB22"); + state->u.f4.fld.f27r2.fb23 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB23"); + state->u.f4.fld.f27r2.fb24 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB24"); + state->u.f4.fld.f27r2.fb25 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB25"); + state->u.f4.fld.f27r2.fb26 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB26"); + state->u.f4.fld.f27r2.fb27 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB27"); + state->u.f4.fld.f27r2.fb28 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB28"); + state->u.f4.fld.f27r2.fb29 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB29"); + state->u.f4.fld.f27r2.fb30 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB30"); + state->u.f4.fld.f27r2.fb31 = cm_object_get_child_by_name(state->u.f4.reg.f27r2, "FB31"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_can_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_can_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_can_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_can_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CANState *state = STM32_CAN_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_can_is_enabled(Object *obj) +{ + STM32CANState *state = STM32_CAN_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_can_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CANState *state = STM32_CAN_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_CAN_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_can_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CAN)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CANState *state = STM32_CAN_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CAN"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_can_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_can_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_can_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_can_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_can_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CAN%dEN", + 1 + state->port_index - STM32_PORT_CAN1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_can_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CAN); +} + +static void stm32_can_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_can_reset_callback; + dc->realize = stm32_can_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_can_is_enabled; +} + +static const TypeInfo stm32_can_type_info = { + .name = TYPE_STM32_CAN, + .parent = TYPE_STM32_CAN_PARENT, + .instance_init = stm32_can_instance_init_callback, + .instance_size = sizeof(STM32CANState), + .class_init = stm32_can_class_init_callback, + .class_size = sizeof(STM32CANClass) }; + +static void stm32_can_register_types(void) +{ + type_register_static(&stm32_can_type_info); +} + +type_init(stm32_can_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/can1.h b/gnu-mcu-eclipse/devices/support/STM32F429x/can1.h new file mode 100644 index 0000000000..01b284b8d6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/can1.h @@ -0,0 +1,2614 @@ +/* + * STM32 - CAN (Controller area network) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CAN_H_ +#define STM32_CAN_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CAN DEVICE_PATH_STM32 "CAN" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_CAN1, + STM32_PORT_CAN2, + STM32_PORT_CAN_UNDEFINED = 0xFF, +} stm32_can_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CAN TYPE_STM32_PREFIX "can" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CAN_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CANParentClass; +typedef PeripheralState STM32CANParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CAN_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CANClass, (obj), TYPE_STM32_CAN) +#define STM32_CAN_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CANClass, (klass), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentClass parent_class; + // public: + + // None, so far. +} STM32CANClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CAN_STATE(obj) \ + OBJECT_CHECK(STM32CANState, (obj), TYPE_STM32_CAN) + +typedef struct { + // private: + STM32CANParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_can_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 CAN (Controller area network) registers. + struct { + Object *mcr; // 0x0 (Master control register) + Object *msr; // 0x4 (Master status register) + Object *tsr; // 0x8 (Transmit status register) + Object *rf0r; // 0xC (Receive FIFO 0 register) + Object *rf1r; // 0x10 (Receive FIFO 1 register) + Object *ier; // 0x14 (Interrupt enable register) + Object *esr; // 0x18 (Interrupt enable register) + Object *btr; // 0x1C (Bit timing register) + Object *ti0r; // 0x180 (TX mailbox identifier register) + Object *tdt0r; // 0x184 (Mailbox data length control and time stamp register) + Object *tdl0r; // 0x188 (Mailbox data low register) + Object *tdh0r; // 0x18C (Mailbox data high register) + Object *ti1r; // 0x190 (Mailbox identifier register) + Object *tdt1r; // 0x194 (Mailbox data length control and time stamp register) + Object *tdl1r; // 0x198 (Mailbox data low register) + Object *tdh1r; // 0x19C (Mailbox data high register) + Object *ti2r; // 0x1A0 (Mailbox identifier register) + Object *tdt2r; // 0x1A4 (Mailbox data length control and time stamp register) + Object *tdl2r; // 0x1A8 (Mailbox data low register) + Object *tdh2r; // 0x1AC (Mailbox data high register) + Object *ri0r; // 0x1B0 (Receive FIFO mailbox identifier register) + Object *rdt0r; // 0x1B4 (Mailbox data high register) + Object *rdl0r; // 0x1B8 (Mailbox data high register) + Object *rdh0r; // 0x1BC (Receive FIFO mailbox data high register) + Object *ri1r; // 0x1C0 (Mailbox data high register) + Object *rdt1r; // 0x1C4 (Mailbox data high register) + Object *rdl1r; // 0x1C8 (Mailbox data high register) + Object *rdh1r; // 0x1CC (Mailbox data high register) + Object *fmr; // 0x200 (Filter master register) + Object *fm1r; // 0x204 (Filter mode register) + Object *fs1r; // 0x20C (Filter scale register) + Object *ffa1r; // 0x214 (Filter FIFO assignment register) + Object *fa1r; // 0x21C (Filter activation register) + Object *f0r1; // 0x240 (Filter bank 0 register 1) + Object *f0r2; // 0x244 (Filter bank 0 register 2) + Object *f1r1; // 0x248 (Filter bank 1 register 1) + Object *f1r2; // 0x24C (Filter bank 1 register 2) + Object *f2r1; // 0x250 (Filter bank 2 register 1) + Object *f2r2; // 0x254 (Filter bank 2 register 2) + Object *f3r1; // 0x258 (Filter bank 3 register 1) + Object *f3r2; // 0x25C (Filter bank 3 register 2) + Object *f4r1; // 0x260 (Filter bank 4 register 1) + Object *f4r2; // 0x264 (Filter bank 4 register 2) + Object *f5r1; // 0x268 (Filter bank 5 register 1) + Object *f5r2; // 0x26C (Filter bank 5 register 2) + Object *f6r1; // 0x270 (Filter bank 6 register 1) + Object *f6r2; // 0x274 (Filter bank 6 register 2) + Object *f7r1; // 0x278 (Filter bank 7 register 1) + Object *f7r2; // 0x27C (Filter bank 7 register 2) + Object *f8r1; // 0x280 (Filter bank 8 register 1) + Object *f8r2; // 0x284 (Filter bank 8 register 2) + Object *f9r1; // 0x288 (Filter bank 9 register 1) + Object *f9r2; // 0x28C (Filter bank 9 register 2) + Object *f10r1; // 0x290 (Filter bank 10 register 1) + Object *f10r2; // 0x294 (Filter bank 10 register 2) + Object *f11r1; // 0x298 (Filter bank 11 register 1) + Object *f11r2; // 0x29C (Filter bank 11 register 2) + Object *f12r1; // 0x2A0 (Filter bank 4 register 1) + Object *f12r2; // 0x2A4 (Filter bank 12 register 2) + Object *f13r1; // 0x2A8 (Filter bank 13 register 1) + Object *f13r2; // 0x2AC (Filter bank 13 register 2) + Object *f14r1; // 0x2B0 (Filter bank 14 register 1) + Object *f14r2; // 0x2B4 (Filter bank 14 register 2) + Object *f15r1; // 0x2B8 (Filter bank 15 register 1) + Object *f15r2; // 0x2BC (Filter bank 15 register 2) + Object *f16r1; // 0x2C0 (Filter bank 16 register 1) + Object *f16r2; // 0x2C4 (Filter bank 16 register 2) + Object *f17r1; // 0x2C8 (Filter bank 17 register 1) + Object *f17r2; // 0x2CC (Filter bank 17 register 2) + Object *f18r1; // 0x2D0 (Filter bank 18 register 1) + Object *f18r2; // 0x2D4 (Filter bank 18 register 2) + Object *f19r1; // 0x2D8 (Filter bank 19 register 1) + Object *f19r2; // 0x2DC (Filter bank 19 register 2) + Object *f20r1; // 0x2E0 (Filter bank 20 register 1) + Object *f20r2; // 0x2E4 (Filter bank 20 register 2) + Object *f21r1; // 0x2E8 (Filter bank 21 register 1) + Object *f21r2; // 0x2EC (Filter bank 21 register 2) + Object *f22r1; // 0x2F0 (Filter bank 22 register 1) + Object *f22r2; // 0x2F4 (Filter bank 22 register 2) + Object *f23r1; // 0x2F8 (Filter bank 23 register 1) + Object *f23r2; // 0x2FC (Filter bank 23 register 2) + Object *f24r1; // 0x300 (Filter bank 24 register 1) + Object *f24r2; // 0x304 (Filter bank 24 register 2) + Object *f25r1; // 0x308 (Filter bank 25 register 1) + Object *f25r2; // 0x30C (Filter bank 25 register 2) + Object *f26r1; // 0x310 (Filter bank 26 register 1) + Object *f26r2; // 0x314 (Filter bank 26 register 2) + Object *f27r1; // 0x318 (Filter bank 27 register 1) + Object *f27r2; // 0x31C (Filter bank 27 register 2) + } reg; + + struct { + + // MCR (Master control register) bitfields. + struct { + Object *inrq; // [0:0] INRQ + Object *sleep; // [1:1] SLEEP + Object *txfp; // [2:2] TXFP + Object *rflm; // [3:3] RFLM + Object *nart; // [4:4] NART + Object *awum; // [5:5] AWUM + Object *abom; // [6:6] ABOM + Object *ttcm; // [7:7] TTCM + Object *reset; // [15:15] RESET + Object *dbf; // [16:16] DBF + } mcr; + + // MSR (Master status register) bitfields. + struct { + Object *inak; // [0:0] INAK + Object *slak; // [1:1] SLAK + Object *erri; // [2:2] ERRI + Object *wkui; // [3:3] WKUI + Object *slaki; // [4:4] SLAKI + Object *txm; // [8:8] TXM + Object *rxm; // [9:9] RXM + Object *samp; // [10:10] SAMP + Object *rx; // [11:11] RX + } msr; + + // TSR (Transmit status register) bitfields. + struct { + Object *rqcp0; // [0:0] RQCP0 + Object *txok0; // [1:1] TXOK0 + Object *alst0; // [2:2] ALST0 + Object *terr0; // [3:3] TERR0 + Object *abrq0; // [7:7] ABRQ0 + Object *rqcp1; // [8:8] RQCP1 + Object *txok1; // [9:9] TXOK1 + Object *alst1; // [10:10] ALST1 + Object *terr1; // [11:11] TERR1 + Object *abrq1; // [15:15] ABRQ1 + Object *rqcp2; // [16:16] RQCP2 + Object *txok2; // [17:17] TXOK2 + Object *alst2; // [18:18] ALST2 + Object *terr2; // [19:19] TERR2 + Object *abrq2; // [23:23] ABRQ2 + Object *code; // [24:25] CODE + Object *tme0; // [26:26] Lowest priority flag for mailbox 0 + Object *tme1; // [27:27] Lowest priority flag for mailbox 1 + Object *tme2; // [28:28] Lowest priority flag for mailbox 2 + Object *low0; // [29:29] Lowest priority flag for mailbox 0 + Object *low1; // [30:30] Lowest priority flag for mailbox 1 + Object *low2; // [31:31] Lowest priority flag for mailbox 2 + } tsr; + + // RF0R (Receive FIFO 0 register) bitfields. + struct { + Object *fmp0; // [0:1] FMP0 + Object *full0; // [3:3] FULL0 + Object *fovr0; // [4:4] FOVR0 + Object *rfom0; // [5:5] RFOM0 + } rf0r; + + // RF1R (Receive FIFO 1 register) bitfields. + struct { + Object *fmp1; // [0:1] FMP1 + Object *full1; // [3:3] FULL1 + Object *fovr1; // [4:4] FOVR1 + Object *rfom1; // [5:5] RFOM1 + } rf1r; + + // IER (Interrupt enable register) bitfields. + struct { + Object *tmeie; // [0:0] TMEIE + Object *fmpie0; // [1:1] FMPIE0 + Object *ffie0; // [2:2] FFIE0 + Object *fovie0; // [3:3] FOVIE0 + Object *fmpie1; // [4:4] FMPIE1 + Object *ffie1; // [5:5] FFIE1 + Object *fovie1; // [6:6] FOVIE1 + Object *ewgie; // [8:8] EWGIE + Object *epvie; // [9:9] EPVIE + Object *bofie; // [10:10] BOFIE + Object *lecie; // [11:11] LECIE + Object *errie; // [15:15] ERRIE + Object *wkuie; // [16:16] WKUIE + Object *slkie; // [17:17] SLKIE + } ier; + + // ESR (Interrupt enable register) bitfields. + struct { + Object *ewgf; // [0:0] EWGF + Object *epvf; // [1:1] EPVF + Object *boff; // [2:2] BOFF + Object *lec; // [4:6] LEC + Object *tec; // [16:23] TEC + Object *rec; // [24:31] REC + } esr; + + // BTR (Bit timing register) bitfields. + struct { + Object *brp; // [0:9] BRP + Object *ts1; // [16:19] TS1 + Object *ts2; // [20:22] TS2 + Object *sjw; // [24:25] SJW + Object *lbkm; // [30:30] LBKM + Object *silm; // [31:31] SILM + } btr; + + // TI0R (TX mailbox identifier register) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ti0r; + + // TDT0R (Mailbox data length control and time stamp register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } tdt0r; + + // TDL0R (Mailbox data low register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } tdl0r; + + // TDH0R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } tdh0r; + + // TI1R (Mailbox identifier register) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ti1r; + + // TDT1R (Mailbox data length control and time stamp register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } tdt1r; + + // TDL1R (Mailbox data low register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } tdl1r; + + // TDH1R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } tdh1r; + + // TI2R (Mailbox identifier register) bitfields. + struct { + Object *txrq; // [0:0] TXRQ + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ti2r; + + // TDT2R (Mailbox data length control and time stamp register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *tgt; // [8:8] TGT + Object *time; // [16:31] TIME + } tdt2r; + + // TDL2R (Mailbox data low register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } tdl2r; + + // TDH2R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } tdh2r; + + // RI0R (Receive FIFO mailbox identifier register) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ri0r; + + // RDT0R (Mailbox data high register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } rdt0r; + + // RDL0R (Mailbox data high register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } rdl0r; + + // RDH0R (Receive FIFO mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } rdh0r; + + // RI1R (Mailbox data high register) bitfields. + struct { + Object *rtr; // [1:1] RTR + Object *ide; // [2:2] IDE + Object *exid; // [3:20] EXID + Object *stid; // [21:31] STID + } ri1r; + + // RDT1R (Mailbox data high register) bitfields. + struct { + Object *dlc; // [0:3] DLC + Object *fmi; // [8:15] FMI + Object *time; // [16:31] TIME + } rdt1r; + + // RDL1R (Mailbox data high register) bitfields. + struct { + Object *data0; // [0:7] DATA0 + Object *data1; // [8:15] DATA1 + Object *data2; // [16:23] DATA2 + Object *data3; // [24:31] DATA3 + } rdl1r; + + // RDH1R (Mailbox data high register) bitfields. + struct { + Object *data4; // [0:7] DATA4 + Object *data5; // [8:15] DATA5 + Object *data6; // [16:23] DATA6 + Object *data7; // [24:31] DATA7 + } rdh1r; + + // FMR (Filter master register) bitfields. + struct { + Object *finit; // [0:0] FINIT + Object *can2sb; // [8:13] CAN2SB + } fmr; + + // FM1R (Filter mode register) bitfields. + struct { + Object *fbm0; // [0:0] Filter mode + Object *fbm1; // [1:1] Filter mode + Object *fbm2; // [2:2] Filter mode + Object *fbm3; // [3:3] Filter mode + Object *fbm4; // [4:4] Filter mode + Object *fbm5; // [5:5] Filter mode + Object *fbm6; // [6:6] Filter mode + Object *fbm7; // [7:7] Filter mode + Object *fbm8; // [8:8] Filter mode + Object *fbm9; // [9:9] Filter mode + Object *fbm10; // [10:10] Filter mode + Object *fbm11; // [11:11] Filter mode + Object *fbm12; // [12:12] Filter mode + Object *fbm13; // [13:13] Filter mode + Object *fbm14; // [14:14] Filter mode + Object *fbm15; // [15:15] Filter mode + Object *fbm16; // [16:16] Filter mode + Object *fbm17; // [17:17] Filter mode + Object *fbm18; // [18:18] Filter mode + Object *fbm19; // [19:19] Filter mode + Object *fbm20; // [20:20] Filter mode + Object *fbm21; // [21:21] Filter mode + Object *fbm22; // [22:22] Filter mode + Object *fbm23; // [23:23] Filter mode + Object *fbm24; // [24:24] Filter mode + Object *fbm25; // [25:25] Filter mode + Object *fbm26; // [26:26] Filter mode + Object *fbm27; // [27:27] Filter mode + } fm1r; + + // FS1R (Filter scale register) bitfields. + struct { + Object *fsc0; // [0:0] Filter scale configuration + Object *fsc1; // [1:1] Filter scale configuration + Object *fsc2; // [2:2] Filter scale configuration + Object *fsc3; // [3:3] Filter scale configuration + Object *fsc4; // [4:4] Filter scale configuration + Object *fsc5; // [5:5] Filter scale configuration + Object *fsc6; // [6:6] Filter scale configuration + Object *fsc7; // [7:7] Filter scale configuration + Object *fsc8; // [8:8] Filter scale configuration + Object *fsc9; // [9:9] Filter scale configuration + Object *fsc10; // [10:10] Filter scale configuration + Object *fsc11; // [11:11] Filter scale configuration + Object *fsc12; // [12:12] Filter scale configuration + Object *fsc13; // [13:13] Filter scale configuration + Object *fsc14; // [14:14] Filter scale configuration + Object *fsc15; // [15:15] Filter scale configuration + Object *fsc16; // [16:16] Filter scale configuration + Object *fsc17; // [17:17] Filter scale configuration + Object *fsc18; // [18:18] Filter scale configuration + Object *fsc19; // [19:19] Filter scale configuration + Object *fsc20; // [20:20] Filter scale configuration + Object *fsc21; // [21:21] Filter scale configuration + Object *fsc22; // [22:22] Filter scale configuration + Object *fsc23; // [23:23] Filter scale configuration + Object *fsc24; // [24:24] Filter scale configuration + Object *fsc25; // [25:25] Filter scale configuration + Object *fsc26; // [26:26] Filter scale configuration + Object *fsc27; // [27:27] Filter scale configuration + } fs1r; + + // FFA1R (Filter FIFO assignment register) bitfields. + struct { + Object *ffa0; // [0:0] Filter FIFO assignment for filter 0 + Object *ffa1; // [1:1] Filter FIFO assignment for filter 1 + Object *ffa2; // [2:2] Filter FIFO assignment for filter 2 + Object *ffa3; // [3:3] Filter FIFO assignment for filter 3 + Object *ffa4; // [4:4] Filter FIFO assignment for filter 4 + Object *ffa5; // [5:5] Filter FIFO assignment for filter 5 + Object *ffa6; // [6:6] Filter FIFO assignment for filter 6 + Object *ffa7; // [7:7] Filter FIFO assignment for filter 7 + Object *ffa8; // [8:8] Filter FIFO assignment for filter 8 + Object *ffa9; // [9:9] Filter FIFO assignment for filter 9 + Object *ffa10; // [10:10] Filter FIFO assignment for filter 10 + Object *ffa11; // [11:11] Filter FIFO assignment for filter 11 + Object *ffa12; // [12:12] Filter FIFO assignment for filter 12 + Object *ffa13; // [13:13] Filter FIFO assignment for filter 13 + Object *ffa14; // [14:14] Filter FIFO assignment for filter 14 + Object *ffa15; // [15:15] Filter FIFO assignment for filter 15 + Object *ffa16; // [16:16] Filter FIFO assignment for filter 16 + Object *ffa17; // [17:17] Filter FIFO assignment for filter 17 + Object *ffa18; // [18:18] Filter FIFO assignment for filter 18 + Object *ffa19; // [19:19] Filter FIFO assignment for filter 19 + Object *ffa20; // [20:20] Filter FIFO assignment for filter 20 + Object *ffa21; // [21:21] Filter FIFO assignment for filter 21 + Object *ffa22; // [22:22] Filter FIFO assignment for filter 22 + Object *ffa23; // [23:23] Filter FIFO assignment for filter 23 + Object *ffa24; // [24:24] Filter FIFO assignment for filter 24 + Object *ffa25; // [25:25] Filter FIFO assignment for filter 25 + Object *ffa26; // [26:26] Filter FIFO assignment for filter 26 + Object *ffa27; // [27:27] Filter FIFO assignment for filter 27 + } ffa1r; + + // FA1R (Filter activation register) bitfields. + struct { + Object *fact0; // [0:0] Filter active + Object *fact1; // [1:1] Filter active + Object *fact2; // [2:2] Filter active + Object *fact3; // [3:3] Filter active + Object *fact4; // [4:4] Filter active + Object *fact5; // [5:5] Filter active + Object *fact6; // [6:6] Filter active + Object *fact7; // [7:7] Filter active + Object *fact8; // [8:8] Filter active + Object *fact9; // [9:9] Filter active + Object *fact10; // [10:10] Filter active + Object *fact11; // [11:11] Filter active + Object *fact12; // [12:12] Filter active + Object *fact13; // [13:13] Filter active + Object *fact14; // [14:14] Filter active + Object *fact15; // [15:15] Filter active + Object *fact16; // [16:16] Filter active + Object *fact17; // [17:17] Filter active + Object *fact18; // [18:18] Filter active + Object *fact19; // [19:19] Filter active + Object *fact20; // [20:20] Filter active + Object *fact21; // [21:21] Filter active + Object *fact22; // [22:22] Filter active + Object *fact23; // [23:23] Filter active + Object *fact24; // [24:24] Filter active + Object *fact25; // [25:25] Filter active + Object *fact26; // [26:26] Filter active + Object *fact27; // [27:27] Filter active + } fa1r; + + // F0R1 (Filter bank 0 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r1; + + // F0R2 (Filter bank 0 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f0r2; + + // F1R1 (Filter bank 1 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r1; + + // F1R2 (Filter bank 1 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f1r2; + + // F2R1 (Filter bank 2 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r1; + + // F2R2 (Filter bank 2 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f2r2; + + // F3R1 (Filter bank 3 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r1; + + // F3R2 (Filter bank 3 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f3r2; + + // F4R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r1; + + // F4R2 (Filter bank 4 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f4r2; + + // F5R1 (Filter bank 5 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r1; + + // F5R2 (Filter bank 5 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f5r2; + + // F6R1 (Filter bank 6 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r1; + + // F6R2 (Filter bank 6 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f6r2; + + // F7R1 (Filter bank 7 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r1; + + // F7R2 (Filter bank 7 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f7r2; + + // F8R1 (Filter bank 8 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r1; + + // F8R2 (Filter bank 8 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f8r2; + + // F9R1 (Filter bank 9 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r1; + + // F9R2 (Filter bank 9 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f9r2; + + // F10R1 (Filter bank 10 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r1; + + // F10R2 (Filter bank 10 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f10r2; + + // F11R1 (Filter bank 11 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r1; + + // F11R2 (Filter bank 11 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f11r2; + + // F12R1 (Filter bank 4 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r1; + + // F12R2 (Filter bank 12 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f12r2; + + // F13R1 (Filter bank 13 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r1; + + // F13R2 (Filter bank 13 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f13r2; + + // F14R1 (Filter bank 14 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r1; + + // F14R2 (Filter bank 14 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f14r2; + + // F15R1 (Filter bank 15 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r1; + + // F15R2 (Filter bank 15 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f15r2; + + // F16R1 (Filter bank 16 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r1; + + // F16R2 (Filter bank 16 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f16r2; + + // F17R1 (Filter bank 17 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r1; + + // F17R2 (Filter bank 17 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f17r2; + + // F18R1 (Filter bank 18 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r1; + + // F18R2 (Filter bank 18 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f18r2; + + // F19R1 (Filter bank 19 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r1; + + // F19R2 (Filter bank 19 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f19r2; + + // F20R1 (Filter bank 20 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r1; + + // F20R2 (Filter bank 20 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f20r2; + + // F21R1 (Filter bank 21 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r1; + + // F21R2 (Filter bank 21 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f21r2; + + // F22R1 (Filter bank 22 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r1; + + // F22R2 (Filter bank 22 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f22r2; + + // F23R1 (Filter bank 23 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r1; + + // F23R2 (Filter bank 23 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f23r2; + + // F24R1 (Filter bank 24 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r1; + + // F24R2 (Filter bank 24 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f24r2; + + // F25R1 (Filter bank 25 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r1; + + // F25R2 (Filter bank 25 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f25r2; + + // F26R1 (Filter bank 26 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r1; + + // F26R2 (Filter bank 26 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f26r2; + + // F27R1 (Filter bank 27 register 1) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r1; + + // F27R2 (Filter bank 27 register 2) bitfields. + struct { + Object *fb0; // [0:0] Filter bits + Object *fb1; // [1:1] Filter bits + Object *fb2; // [2:2] Filter bits + Object *fb3; // [3:3] Filter bits + Object *fb4; // [4:4] Filter bits + Object *fb5; // [5:5] Filter bits + Object *fb6; // [6:6] Filter bits + Object *fb7; // [7:7] Filter bits + Object *fb8; // [8:8] Filter bits + Object *fb9; // [9:9] Filter bits + Object *fb10; // [10:10] Filter bits + Object *fb11; // [11:11] Filter bits + Object *fb12; // [12:12] Filter bits + Object *fb13; // [13:13] Filter bits + Object *fb14; // [14:14] Filter bits + Object *fb15; // [15:15] Filter bits + Object *fb16; // [16:16] Filter bits + Object *fb17; // [17:17] Filter bits + Object *fb18; // [18:18] Filter bits + Object *fb19; // [19:19] Filter bits + Object *fb20; // [20:20] Filter bits + Object *fb21; // [21:21] Filter bits + Object *fb22; // [22:22] Filter bits + Object *fb23; // [23:23] Filter bits + Object *fb24; // [24:24] Filter bits + Object *fb25; // [25:25] Filter bits + Object *fb26; // [26:26] Filter bits + Object *fb27; // [27:27] Filter bits + Object *fb28; // [28:28] Filter bits + Object *fb29; // [29:29] Filter bits + Object *fb30; // [30:30] Filter bits + Object *fb31; // [31:31] Filter bits + } f27r2; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CANState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CAN_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/crc.c b/gnu-mcu-eclipse/devices/support/STM32F429x/crc.c new file mode 100644 index 0000000000..1dacd10833 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/crc.c @@ -0,0 +1,246 @@ +/* + * STM32 - CRC (Cryptographic processor) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_crc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // IDR bitfields. + state->u.f4.fld.idr.idr = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR"); + + // CR bitfields. + state->u.f4.fld.cr.cr = cm_object_get_child_by_name(state->u.f4.reg.cr, "CR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_crc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_crc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_crc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_crc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32CRCState *state = STM32_CRC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_crc_is_enabled(Object *obj) +{ + STM32CRCState *state = STM32_CRC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_crc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32CRCState *state = STM32_CRC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_crc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_CRC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32CRCState *state = STM32_CRC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "CRC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_crc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_crc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_crc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_crc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_crc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/CRCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_crc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_CRC); +} + +static void stm32_crc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_crc_reset_callback; + dc->realize = stm32_crc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_crc_is_enabled; +} + +static const TypeInfo stm32_crc_type_info = { + .name = TYPE_STM32_CRC, + .parent = TYPE_STM32_CRC_PARENT, + .instance_init = stm32_crc_instance_init_callback, + .instance_size = sizeof(STM32CRCState), + .class_init = stm32_crc_class_init_callback, + .class_size = sizeof(STM32CRCClass) }; + +static void stm32_crc_register_types(void) +{ + type_register_static(&stm32_crc_type_info); +} + +type_init(stm32_crc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/crc.h b/gnu-mcu-eclipse/devices/support/STM32F429x/crc.h new file mode 100644 index 0000000000..10e5fff9cc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/crc.h @@ -0,0 +1,117 @@ +/* + * STM32 - CRC (Cryptographic processor) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_CRC_H_ +#define STM32_CRC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_CRC DEVICE_PATH_STM32 "CRC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_CRC TYPE_STM32_PREFIX "crc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_CRC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32CRCParentClass; +typedef PeripheralState STM32CRCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_CRC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32CRCClass, (obj), TYPE_STM32_CRC) +#define STM32_CRC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32CRCClass, (klass), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentClass parent_class; + // public: + + // None, so far. +} STM32CRCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_CRC_STATE(obj) \ + OBJECT_CHECK(STM32CRCState, (obj), TYPE_STM32_CRC) + +typedef struct { + // private: + STM32CRCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 CRC (Cryptographic processor) registers. + struct { + Object *dr; // 0x0 (Data register) + Object *idr; // 0x4 (Independent Data register) + Object *cr; // 0x8 (Control register) + } reg; + + struct { + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:31] Data Register + } dr; + + // IDR (Independent Data register) bitfields. + struct { + Object *idr; // [0:7] Independent Data register + } idr; + + // CR (Control register) bitfields. + struct { + Object *cr; // [0:0] Control regidter + } cr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32CRCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_CRC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dac.c b/gnu-mcu-eclipse/devices/support/STM32F429x/dac.c new file mode 100644 index 0000000000..2e67300031 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dac.c @@ -0,0 +1,310 @@ +/* + * STM32 - DAC (Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_dac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.swtrigr = cm_object_get_child_by_name(obj, "SWTRIGR"); + state->u.f4.reg.dhr12r1 = cm_object_get_child_by_name(obj, "DHR12R1"); + state->u.f4.reg.dhr12l1 = cm_object_get_child_by_name(obj, "DHR12L1"); + state->u.f4.reg.dhr8r1 = cm_object_get_child_by_name(obj, "DHR8R1"); + state->u.f4.reg.dhr12r2 = cm_object_get_child_by_name(obj, "DHR12R2"); + state->u.f4.reg.dhr12l2 = cm_object_get_child_by_name(obj, "DHR12L2"); + state->u.f4.reg.dhr8r2 = cm_object_get_child_by_name(obj, "DHR8R2"); + state->u.f4.reg.dhr12rd = cm_object_get_child_by_name(obj, "DHR12RD"); + state->u.f4.reg.dhr12ld = cm_object_get_child_by_name(obj, "DHR12LD"); + state->u.f4.reg.dhr8rd = cm_object_get_child_by_name(obj, "DHR8RD"); + state->u.f4.reg.dor1 = cm_object_get_child_by_name(obj, "DOR1"); + state->u.f4.reg.dor2 = cm_object_get_child_by_name(obj, "DOR2"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f4.fld.cr.en1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "EN1"); + state->u.f4.fld.cr.boff1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "BOFF1"); + state->u.f4.fld.cr.ten1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TEN1"); + state->u.f4.fld.cr.tsel1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSEL1"); + state->u.f4.fld.cr.wave1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "WAVE1"); + state->u.f4.fld.cr.mamp1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "MAMP1"); + state->u.f4.fld.cr.dmaen1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAEN1"); + state->u.f4.fld.cr.dmaudrie1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAUDRIE1"); + state->u.f4.fld.cr.en2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "EN2"); + state->u.f4.fld.cr.boff2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "BOFF2"); + state->u.f4.fld.cr.ten2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TEN2"); + state->u.f4.fld.cr.tsel2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSEL2"); + state->u.f4.fld.cr.wave2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "WAVE2"); + state->u.f4.fld.cr.mamp2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "MAMP2"); + state->u.f4.fld.cr.dmaen2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAEN2"); + state->u.f4.fld.cr.dmaudrie2 = cm_object_get_child_by_name(state->u.f4.reg.cr, "DMAUDRIE2"); + + // SWTRIGR bitfields. + state->u.f4.fld.swtrigr.swtrig1 = cm_object_get_child_by_name(state->u.f4.reg.swtrigr, "SWTRIG1"); + state->u.f4.fld.swtrigr.swtrig2 = cm_object_get_child_by_name(state->u.f4.reg.swtrigr, "SWTRIG2"); + + // DHR12R1 bitfields. + state->u.f4.fld.dhr12r1.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12r1, "DACC1DHR"); + + // DHR12L1 bitfields. + state->u.f4.fld.dhr12l1.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12l1, "DACC1DHR"); + + // DHR8R1 bitfields. + state->u.f4.fld.dhr8r1.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8r1, "DACC1DHR"); + + // DHR12R2 bitfields. + state->u.f4.fld.dhr12r2.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12r2, "DACC2DHR"); + + // DHR12L2 bitfields. + state->u.f4.fld.dhr12l2.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12l2, "DACC2DHR"); + + // DHR8R2 bitfields. + state->u.f4.fld.dhr8r2.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8r2, "DACC2DHR"); + + // DHR12RD bitfields. + state->u.f4.fld.dhr12rd.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12rd, "DACC1DHR"); + state->u.f4.fld.dhr12rd.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12rd, "DACC2DHR"); + + // DHR12LD bitfields. + state->u.f4.fld.dhr12ld.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12ld, "DACC1DHR"); + state->u.f4.fld.dhr12ld.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr12ld, "DACC2DHR"); + + // DHR8RD bitfields. + state->u.f4.fld.dhr8rd.dacc1dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8rd, "DACC1DHR"); + state->u.f4.fld.dhr8rd.dacc2dhr = cm_object_get_child_by_name(state->u.f4.reg.dhr8rd, "DACC2DHR"); + + // DOR1 bitfields. + state->u.f4.fld.dor1.dacc1dor = cm_object_get_child_by_name(state->u.f4.reg.dor1, "DACC1DOR"); + + // DOR2 bitfields. + state->u.f4.fld.dor2.dacc2dor = cm_object_get_child_by_name(state->u.f4.reg.dor2, "DACC2DOR"); + + // SR bitfields. + state->u.f4.fld.sr.dmaudr1 = cm_object_get_child_by_name(state->u.f4.reg.sr, "DMAUDR1"); + state->u.f4.fld.sr.dmaudr2 = cm_object_get_child_by_name(state->u.f4.reg.sr, "DMAUDR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DACState *state = STM32_DAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dac_is_enabled(Object *obj) +{ + STM32DACState *state = STM32_DAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DACState *state = STM32_DAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DACState *state = STM32_DAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_dac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DAC); +} + +static void stm32_dac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dac_reset_callback; + dc->realize = stm32_dac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dac_is_enabled; +} + +static const TypeInfo stm32_dac_type_info = { + .name = TYPE_STM32_DAC, + .parent = TYPE_STM32_DAC_PARENT, + .instance_init = stm32_dac_instance_init_callback, + .instance_size = sizeof(STM32DACState), + .class_init = stm32_dac_class_init_callback, + .class_size = sizeof(STM32DACClass) }; + +static void stm32_dac_register_types(void) +{ + type_register_static(&stm32_dac_type_info); +} + +type_init(stm32_dac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dac.h b/gnu-mcu-eclipse/devices/support/STM32F429x/dac.h new file mode 100644 index 0000000000..2193be3f32 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dac.h @@ -0,0 +1,203 @@ +/* + * STM32 - DAC (Digital-to-analog converter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DAC_H_ +#define STM32_DAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DAC DEVICE_PATH_STM32 "DAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DAC TYPE_STM32_PREFIX "dac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DACParentClass; +typedef PeripheralState STM32DACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DACClass, (obj), TYPE_STM32_DAC) +#define STM32_DAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DACClass, (klass), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentClass parent_class; + // public: + + // None, so far. +} STM32DACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DAC_STATE(obj) \ + OBJECT_CHECK(STM32DACState, (obj), TYPE_STM32_DAC) + +typedef struct { + // private: + STM32DACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DAC (Digital-to-analog converter) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *swtrigr; // 0x4 (Software trigger register) + Object *dhr12r1; // 0x8 (Channel1 12-bit right-aligned data holding register) + Object *dhr12l1; // 0xC (Channel1 12-bit left aligned data holding register) + Object *dhr8r1; // 0x10 (Channel1 8-bit right aligned data holding register) + Object *dhr12r2; // 0x14 (Channel2 12-bit right aligned data holding register) + Object *dhr12l2; // 0x18 (Channel2 12-bit left aligned data holding register) + Object *dhr8r2; // 0x1C (Channel2 8-bit right-aligned data holding register) + Object *dhr12rd; // 0x20 (Dual DAC 12-bit right-aligned data holding register) + Object *dhr12ld; // 0x24 (DUAL DAC 12-bit left aligned data holding register) + Object *dhr8rd; // 0x28 (DUAL DAC 8-bit right aligned data holding register) + Object *dor1; // 0x2C (Channel1 data output register) + Object *dor2; // 0x30 (Channel2 data output register) + Object *sr; // 0x34 (Status register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *en1; // [0:0] DAC channel1 enable + Object *boff1; // [1:1] DAC channel1 output buffer disable + Object *ten1; // [2:2] DAC channel1 trigger enable + Object *tsel1; // [3:5] DAC channel1 trigger selection + Object *wave1; // [6:7] DAC channel1 noise/triangle wave generation enable + Object *mamp1; // [8:11] DAC channel1 mask/amplitude selector + Object *dmaen1; // [12:12] DAC channel1 DMA enable + Object *dmaudrie1; // [13:13] DAC channel1 DMA Underrun Interrupt enable + Object *en2; // [16:16] DAC channel2 enable + Object *boff2; // [17:17] DAC channel2 output buffer disable + Object *ten2; // [18:18] DAC channel2 trigger enable + Object *tsel2; // [19:21] DAC channel2 trigger selection + Object *wave2; // [22:23] DAC channel2 noise/triangle wave generation enable + Object *mamp2; // [24:27] DAC channel2 mask/amplitude selector + Object *dmaen2; // [28:28] DAC channel2 DMA enable + Object *dmaudrie2; // [29:29] DAC channel2 DMA underrun interrupt enable + } cr; + + // SWTRIGR (Software trigger register) bitfields. + struct { + Object *swtrig1; // [0:0] DAC channel1 software trigger + Object *swtrig2; // [1:1] DAC channel2 software trigger + } swtrigr; + + // DHR12R1 (Channel1 12-bit right-aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + } dhr12r1; + + // DHR12L1 (Channel1 12-bit left aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + } dhr12l1; + + // DHR8R1 (Channel1 8-bit right aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + } dhr8r1; + + // DHR12R2 (Channel2 12-bit right aligned data holding register) bitfields. + struct { + Object *dacc2dhr; // [0:11] DAC channel2 12-bit right-aligned data + } dhr12r2; + + // DHR12L2 (Channel2 12-bit left aligned data holding register) bitfields. + struct { + Object *dacc2dhr; // [4:15] DAC channel2 12-bit left-aligned data + } dhr12l2; + + // DHR8R2 (Channel2 8-bit right-aligned data holding register) bitfields. + struct { + Object *dacc2dhr; // [0:7] DAC channel2 8-bit right-aligned data + } dhr8r2; + + // DHR12RD (Dual DAC 12-bit right-aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:11] DAC channel1 12-bit right-aligned data + Object *dacc2dhr; // [16:27] DAC channel2 12-bit right-aligned data + } dhr12rd; + + // DHR12LD (DUAL DAC 12-bit left aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [4:15] DAC channel1 12-bit left-aligned data + Object *dacc2dhr; // [20:31] DAC channel2 12-bit left-aligned data + } dhr12ld; + + // DHR8RD (DUAL DAC 8-bit right aligned data holding register) bitfields. + struct { + Object *dacc1dhr; // [0:7] DAC channel1 8-bit right-aligned data + Object *dacc2dhr; // [8:15] DAC channel2 8-bit right-aligned data + } dhr8rd; + + // DOR1 (Channel1 data output register) bitfields. + struct { + Object *dacc1dor; // [0:11] DAC channel1 data output + } dor1; + + // DOR2 (Channel2 data output register) bitfields. + struct { + Object *dacc2dor; // [0:11] DAC channel2 data output + } dor2; + + // SR (Status register) bitfields. + struct { + Object *dmaudr1; // [13:13] DAC channel1 DMA underrun flag + Object *dmaudr2; // [29:29] DAC channel2 DMA underrun flag + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dbg.c b/gnu-mcu-eclipse/devices/support/STM32F429x/dbg.c new file mode 100644 index 0000000000..d5b71fb6a5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dbg.c @@ -0,0 +1,274 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_dbg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dbgmcu_idcode = cm_object_get_child_by_name(obj, "DBGMCU_IDCODE"); + state->u.f4.reg.dbgmcu_cr = cm_object_get_child_by_name(obj, "DBGMCU_CR"); + state->u.f4.reg.dbgmcu_apb1_fz = cm_object_get_child_by_name(obj, "DBGMCU_APB1_FZ"); + state->u.f4.reg.dbgmcu_apb2_fz = cm_object_get_child_by_name(obj, "DBGMCU_APB2_FZ"); + + + // DBGMCU_IDCODE bitfields. + state->u.f4.fld.dbgmcu_idcode.dev_id = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_idcode, "DEV_ID"); + state->u.f4.fld.dbgmcu_idcode.rev_id = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_idcode, "REV_ID"); + + // DBGMCU_CR bitfields. + state->u.f4.fld.dbgmcu_cr.dbg_sleep = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_SLEEP"); + state->u.f4.fld.dbgmcu_cr.dbg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_STOP"); + state->u.f4.fld.dbgmcu_cr.dbg_standby = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "DBG_STANDBY"); + state->u.f4.fld.dbgmcu_cr.trace_ioen = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "TRACE_IOEN"); + state->u.f4.fld.dbgmcu_cr.trace_mode = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_cr, "TRACE_MODE"); + + // DBGMCU_APB1_FZ bitfields. + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim2_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM2_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim3_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM3_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim4_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM4_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim5_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM5_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim6_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM6_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim7_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM7_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim12_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM12_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim13_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM13_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_tim14_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_TIM14_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_wwdg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_WWDG_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_iwdeg_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_IWDEG_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_j2c1_smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_J2C1_SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_j2c2_smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_J2C2_SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_j2c3smbus_timeout = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_J2C3SMBUS_TIMEOUT"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_can1_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_CAN1_STOP"); + state->u.f4.fld.dbgmcu_apb1_fz.dbg_can2_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb1_fz, "DBG_CAN2_STOP"); + + // DBGMCU_APB2_FZ bitfields. + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim1_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM1_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim8_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM8_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim9_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM9_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim10_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM10_STOP"); + state->u.f4.fld.dbgmcu_apb2_fz.dbg_tim11_stop = cm_object_get_child_by_name(state->u.f4.reg.dbgmcu_apb2_fz, "DBG_TIM11_STOP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dbg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dbg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dbg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dbg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DBGState *state = STM32_DBG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dbg_is_enabled(Object *obj) +{ + STM32DBGState *state = STM32_DBG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dbg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DBGState *state = STM32_DBG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dbg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DBG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DBGState *state = STM32_DBG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DBG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_dbg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dbg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dbg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dbg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dbg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DBGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dbg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DBG); +} + +static void stm32_dbg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dbg_reset_callback; + dc->realize = stm32_dbg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dbg_is_enabled; +} + +static const TypeInfo stm32_dbg_type_info = { + .name = TYPE_STM32_DBG, + .parent = TYPE_STM32_DBG_PARENT, + .instance_init = stm32_dbg_instance_init_callback, + .instance_size = sizeof(STM32DBGState), + .class_init = stm32_dbg_class_init_callback, + .class_size = sizeof(STM32DBGClass) }; + +static void stm32_dbg_register_types(void) +{ + type_register_static(&stm32_dbg_type_info); +} + +type_init(stm32_dbg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dbg.h b/gnu-mcu-eclipse/devices/support/STM32F429x/dbg.h new file mode 100644 index 0000000000..2e0ad5bcc1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dbg.h @@ -0,0 +1,147 @@ +/* + * STM32 - DBG (Debug support) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DBG_H_ +#define STM32_DBG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DBG DEVICE_PATH_STM32 "DBG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DBG TYPE_STM32_PREFIX "dbg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DBG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DBGParentClass; +typedef PeripheralState STM32DBGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DBG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DBGClass, (obj), TYPE_STM32_DBG) +#define STM32_DBG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DBGClass, (klass), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentClass parent_class; + // public: + + // None, so far. +} STM32DBGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DBG_STATE(obj) \ + OBJECT_CHECK(STM32DBGState, (obj), TYPE_STM32_DBG) + +typedef struct { + // private: + STM32DBGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DBG (Debug support) registers. + struct { + Object *dbgmcu_idcode; // 0x0 (IDCODE) + Object *dbgmcu_cr; // 0x4 (Control Register) + Object *dbgmcu_apb1_fz; // 0x8 (Debug MCU APB1 Freeze registe) + Object *dbgmcu_apb2_fz; // 0xC (Debug MCU APB2 Freeze registe) + } reg; + + struct { + + // DBGMCU_IDCODE (IDCODE) bitfields. + struct { + Object *dev_id; // [0:11] DEV_ID + Object *rev_id; // [16:31] REV_ID + } dbgmcu_idcode; + + // DBGMCU_CR (Control Register) bitfields. + struct { + Object *dbg_sleep; // [0:0] DBG_SLEEP + Object *dbg_stop; // [1:1] DBG_STOP + Object *dbg_standby; // [2:2] DBG_STANDBY + Object *trace_ioen; // [5:5] TRACE_IOEN + Object *trace_mode; // [6:7] TRACE_MODE + } dbgmcu_cr; + + // DBGMCU_APB1_FZ (Debug MCU APB1 Freeze registe) bitfields. + struct { + Object *dbg_tim2_stop; // [0:0] DBG_TIM2_STOP + Object *dbg_tim3_stop; // [1:1] DBG_TIM3 _STOP + Object *dbg_tim4_stop; // [2:2] DBG_TIM4_STOP + Object *dbg_tim5_stop; // [3:3] DBG_TIM5_STOP + Object *dbg_tim6_stop; // [4:4] DBG_TIM6_STOP + Object *dbg_tim7_stop; // [5:5] DBG_TIM7_STOP + Object *dbg_tim12_stop; // [6:6] DBG_TIM12_STOP + Object *dbg_tim13_stop; // [7:7] DBG_TIM13_STOP + Object *dbg_tim14_stop; // [8:8] DBG_TIM14_STOP + Object *dbg_wwdg_stop; // [11:11] DBG_WWDG_STOP + Object *dbg_iwdeg_stop; // [12:12] DBG_IWDEG_STOP + Object *dbg_j2c1_smbus_timeout; // [21:21] DBG_J2C1_SMBUS_TIMEOUT + Object *dbg_j2c2_smbus_timeout; // [22:22] DBG_J2C2_SMBUS_TIMEOUT + Object *dbg_j2c3smbus_timeout; // [23:23] DBG_J2C3SMBUS_TIMEOUT + Object *dbg_can1_stop; // [25:25] DBG_CAN1_STOP + Object *dbg_can2_stop; // [26:26] DBG_CAN2_STOP + } dbgmcu_apb1_fz; + + // DBGMCU_APB2_FZ (Debug MCU APB2 Freeze registe) bitfields. + struct { + Object *dbg_tim1_stop; // [0:0] TIM1 counter stopped when core is halted + Object *dbg_tim8_stop; // [1:1] TIM8 counter stopped when core is halted + Object *dbg_tim9_stop; // [16:16] TIM9 counter stopped when core is halted + Object *dbg_tim10_stop; // [17:17] TIM10 counter stopped when core is halted + Object *dbg_tim11_stop; // [18:18] TIM11 counter stopped when core is halted + } dbgmcu_apb2_fz; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DBGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DBG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dcmi.c b/gnu-mcu-eclipse/devices/support/STM32F429x/dcmi.c new file mode 100644 index 0000000000..ff74f5e84d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dcmi.c @@ -0,0 +1,317 @@ +/* + * STM32 - DCMI (Digital camera interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_dcmi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DCMIState *state = STM32_DCMI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.ris = cm_object_get_child_by_name(obj, "RIS"); + state->u.f4.reg.ier = cm_object_get_child_by_name(obj, "IER"); + state->u.f4.reg.mis = cm_object_get_child_by_name(obj, "MIS"); + state->u.f4.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f4.reg.escr = cm_object_get_child_by_name(obj, "ESCR"); + state->u.f4.reg.esur = cm_object_get_child_by_name(obj, "ESUR"); + state->u.f4.reg.cwstrt = cm_object_get_child_by_name(obj, "CWSTRT"); + state->u.f4.reg.cwsize = cm_object_get_child_by_name(obj, "CWSIZE"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // CR bitfields. + state->u.f4.fld.cr.capture = cm_object_get_child_by_name(state->u.f4.reg.cr, "CAPTURE"); + state->u.f4.fld.cr.cm = cm_object_get_child_by_name(state->u.f4.reg.cr, "CM"); + state->u.f4.fld.cr.crop = cm_object_get_child_by_name(state->u.f4.reg.cr, "CROP"); + state->u.f4.fld.cr.jpeg = cm_object_get_child_by_name(state->u.f4.reg.cr, "JPEG"); + state->u.f4.fld.cr.ess = cm_object_get_child_by_name(state->u.f4.reg.cr, "ESS"); + state->u.f4.fld.cr.pckpol = cm_object_get_child_by_name(state->u.f4.reg.cr, "PCKPOL"); + state->u.f4.fld.cr.hspol = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSPOL"); + state->u.f4.fld.cr.vspol = cm_object_get_child_by_name(state->u.f4.reg.cr, "VSPOL"); + state->u.f4.fld.cr.fcrc = cm_object_get_child_by_name(state->u.f4.reg.cr, "FCRC"); + state->u.f4.fld.cr.edm = cm_object_get_child_by_name(state->u.f4.reg.cr, "EDM"); + state->u.f4.fld.cr.enable = cm_object_get_child_by_name(state->u.f4.reg.cr, "ENABLE"); + + // SR bitfields. + state->u.f4.fld.sr.hsync = cm_object_get_child_by_name(state->u.f4.reg.sr, "HSYNC"); + state->u.f4.fld.sr.vsync = cm_object_get_child_by_name(state->u.f4.reg.sr, "VSYNC"); + state->u.f4.fld.sr.fne = cm_object_get_child_by_name(state->u.f4.reg.sr, "FNE"); + + // RIS bitfields. + state->u.f4.fld.ris.frame_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "FRAME_RIS"); + state->u.f4.fld.ris.ovr_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "OVR_RIS"); + state->u.f4.fld.ris.err_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "ERR_RIS"); + state->u.f4.fld.ris.vsync_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "VSYNC_RIS"); + state->u.f4.fld.ris.line_ris = cm_object_get_child_by_name(state->u.f4.reg.ris, "LINE_RIS"); + + // IER bitfields. + state->u.f4.fld.ier.frame_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "FRAME_IE"); + state->u.f4.fld.ier.ovr_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "OVR_IE"); + state->u.f4.fld.ier.err_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "ERR_IE"); + state->u.f4.fld.ier.vsync_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "VSYNC_IE"); + state->u.f4.fld.ier.line_ie = cm_object_get_child_by_name(state->u.f4.reg.ier, "LINE_IE"); + + // MIS bitfields. + state->u.f4.fld.mis.frame_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "FRAME_MIS"); + state->u.f4.fld.mis.ovr_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "OVR_MIS"); + state->u.f4.fld.mis.err_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "ERR_MIS"); + state->u.f4.fld.mis.vsync_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "VSYNC_MIS"); + state->u.f4.fld.mis.line_mis = cm_object_get_child_by_name(state->u.f4.reg.mis, "LINE_MIS"); + + // ICR bitfields. + state->u.f4.fld.icr.frame_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "FRAME_ISC"); + state->u.f4.fld.icr.ovr_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "OVR_ISC"); + state->u.f4.fld.icr.err_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "ERR_ISC"); + state->u.f4.fld.icr.vsync_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "VSYNC_ISC"); + state->u.f4.fld.icr.line_isc = cm_object_get_child_by_name(state->u.f4.reg.icr, "LINE_ISC"); + + // ESCR bitfields. + state->u.f4.fld.escr.fsc = cm_object_get_child_by_name(state->u.f4.reg.escr, "FSC"); + state->u.f4.fld.escr.lsc = cm_object_get_child_by_name(state->u.f4.reg.escr, "LSC"); + state->u.f4.fld.escr.lec = cm_object_get_child_by_name(state->u.f4.reg.escr, "LEC"); + state->u.f4.fld.escr.fec = cm_object_get_child_by_name(state->u.f4.reg.escr, "FEC"); + + // ESUR bitfields. + state->u.f4.fld.esur.fsu = cm_object_get_child_by_name(state->u.f4.reg.esur, "FSU"); + state->u.f4.fld.esur.lsu = cm_object_get_child_by_name(state->u.f4.reg.esur, "LSU"); + state->u.f4.fld.esur.leu = cm_object_get_child_by_name(state->u.f4.reg.esur, "LEU"); + state->u.f4.fld.esur.feu = cm_object_get_child_by_name(state->u.f4.reg.esur, "FEU"); + + // CWSTRT bitfields. + state->u.f4.fld.cwstrt.hoffcnt = cm_object_get_child_by_name(state->u.f4.reg.cwstrt, "HOFFCNT"); + state->u.f4.fld.cwstrt.vst = cm_object_get_child_by_name(state->u.f4.reg.cwstrt, "VST"); + + // CWSIZE bitfields. + state->u.f4.fld.cwsize.capcnt = cm_object_get_child_by_name(state->u.f4.reg.cwsize, "CAPCNT"); + state->u.f4.fld.cwsize.vline = cm_object_get_child_by_name(state->u.f4.reg.cwsize, "VLINE"); + + // DR bitfields. + state->u.f4.fld.dr.byte0 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte0"); + state->u.f4.fld.dr.byte1 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte1"); + state->u.f4.fld.dr.byte2 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte2"); + state->u.f4.fld.dr.byte3 = cm_object_get_child_by_name(state->u.f4.reg.dr, "Byte3"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dcmi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dcmi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dcmi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dcmi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DCMIState *state = STM32_DCMI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dcmi_is_enabled(Object *obj) +{ + STM32DCMIState *state = STM32_DCMI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dcmi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DCMIState *state = STM32_DCMI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dcmi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DCMI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DCMIState *state = STM32_DCMI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DCMI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_dcmi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dcmi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dcmi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dcmi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dcmi_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DCMIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dcmi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DCMI); +} + +static void stm32_dcmi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dcmi_reset_callback; + dc->realize = stm32_dcmi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dcmi_is_enabled; +} + +static const TypeInfo stm32_dcmi_type_info = { + .name = TYPE_STM32_DCMI, + .parent = TYPE_STM32_DCMI_PARENT, + .instance_init = stm32_dcmi_instance_init_callback, + .instance_size = sizeof(STM32DCMIState), + .class_init = stm32_dcmi_class_init_callback, + .class_size = sizeof(STM32DCMIClass) }; + +static void stm32_dcmi_register_types(void) +{ + type_register_static(&stm32_dcmi_type_info); +} + +type_init(stm32_dcmi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dcmi.h b/gnu-mcu-eclipse/devices/support/STM32F429x/dcmi.h new file mode 100644 index 0000000000..e42585bb2d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dcmi.h @@ -0,0 +1,204 @@ +/* + * STM32 - DCMI (Digital camera interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DCMI_H_ +#define STM32_DCMI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DCMI DEVICE_PATH_STM32 "DCMI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DCMI TYPE_STM32_PREFIX "dcmi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DCMI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DCMIParentClass; +typedef PeripheralState STM32DCMIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DCMI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DCMIClass, (obj), TYPE_STM32_DCMI) +#define STM32_DCMI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DCMIClass, (klass), TYPE_STM32_DCMI) + +typedef struct { + // private: + STM32DCMIParentClass parent_class; + // public: + + // None, so far. +} STM32DCMIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DCMI_STATE(obj) \ + OBJECT_CHECK(STM32DCMIState, (obj), TYPE_STM32_DCMI) + +typedef struct { + // private: + STM32DCMIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DCMI (Digital camera interface) registers. + struct { + Object *cr; // 0x0 (Control register 1) + Object *sr; // 0x4 (Status register) + Object *ris; // 0x8 (Raw interrupt status register) + Object *ier; // 0xC (Interrupt enable register) + Object *mis; // 0x10 (Masked interrupt status register) + Object *icr; // 0x14 (Interrupt clear register) + Object *escr; // 0x18 (Embedded synchronization code register) + Object *esur; // 0x1C (Embedded synchronization unmask register) + Object *cwstrt; // 0x20 (Crop window start) + Object *cwsize; // 0x24 (Crop window size) + Object *dr; // 0x28 (Data register) + } reg; + + struct { + + // CR (Control register 1) bitfields. + struct { + Object *capture; // [0:0] Capture enable + Object *cm; // [1:1] Capture mode + Object *crop; // [2:2] Crop feature + Object *jpeg; // [3:3] JPEG format + Object *ess; // [4:4] Embedded synchronization select + Object *pckpol; // [5:5] Pixel clock polarity + Object *hspol; // [6:6] Horizontal synchronization polarity + Object *vspol; // [7:7] Vertical synchronization polarity + Object *fcrc; // [8:9] Frame capture rate control + Object *edm; // [10:11] Extended data mode + Object *enable; // [14:14] DCMI enable + } cr; + + // SR (Status register) bitfields. + struct { + Object *hsync; // [0:0] HSYNC + Object *vsync; // [1:1] VSYNC + Object *fne; // [2:2] FIFO not empty + } sr; + + // RIS (Raw interrupt status register) bitfields. + struct { + Object *frame_ris; // [0:0] Capture complete raw interrupt status + Object *ovr_ris; // [1:1] Overrun raw interrupt status + Object *err_ris; // [2:2] Synchronization error raw interrupt status + Object *vsync_ris; // [3:3] VSYNC raw interrupt status + Object *line_ris; // [4:4] Line raw interrupt status + } ris; + + // IER (Interrupt enable register) bitfields. + struct { + Object *frame_ie; // [0:0] Capture complete interrupt enable + Object *ovr_ie; // [1:1] Overrun interrupt enable + Object *err_ie; // [2:2] Synchronization error interrupt enable + Object *vsync_ie; // [3:3] VSYNC interrupt enable + Object *line_ie; // [4:4] Line interrupt enable + } ier; + + // MIS (Masked interrupt status register) bitfields. + struct { + Object *frame_mis; // [0:0] Capture complete masked interrupt status + Object *ovr_mis; // [1:1] Overrun masked interrupt status + Object *err_mis; // [2:2] Synchronization error masked interrupt status + Object *vsync_mis; // [3:3] VSYNC masked interrupt status + Object *line_mis; // [4:4] Line masked interrupt status + } mis; + + // ICR (Interrupt clear register) bitfields. + struct { + Object *frame_isc; // [0:0] Capture complete interrupt status clear + Object *ovr_isc; // [1:1] Overrun interrupt status clear + Object *err_isc; // [2:2] Synchronization error interrupt status clear + Object *vsync_isc; // [3:3] Vertical synch interrupt status clear + Object *line_isc; // [4:4] Line interrupt status clear + } icr; + + // ESCR (Embedded synchronization code register) bitfields. + struct { + Object *fsc; // [0:7] Frame start delimiter code + Object *lsc; // [8:15] Line start delimiter code + Object *lec; // [16:23] Line end delimiter code + Object *fec; // [24:31] Frame end delimiter code + } escr; + + // ESUR (Embedded synchronization unmask register) bitfields. + struct { + Object *fsu; // [0:7] Frame start delimiter unmask + Object *lsu; // [8:15] Line start delimiter unmask + Object *leu; // [16:23] Line end delimiter unmask + Object *feu; // [24:31] Frame end delimiter unmask + } esur; + + // CWSTRT (Crop window start) bitfields. + struct { + Object *hoffcnt; // [0:13] Horizontal offset count + Object *vst; // [16:28] Vertical start line count + } cwstrt; + + // CWSIZE (Crop window size) bitfields. + struct { + Object *capcnt; // [0:13] Capture count + Object *vline; // [16:29] Vertical line count + } cwsize; + + // DR (Data register) bitfields. + struct { + Object *byte0; // [0:7] Data byte 0 + Object *byte1; // [8:15] Data byte 1 + Object *byte2; // [16:23] Data byte 2 + Object *byte3; // [24:31] Data byte 3 + } dr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DCMIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DCMI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dma2.c b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2.c new file mode 100644 index 0000000000..5a28cffca9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2.c @@ -0,0 +1,698 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.lisr = cm_object_get_child_by_name(obj, "LISR"); + state->u.f4.reg.hisr = cm_object_get_child_by_name(obj, "HISR"); + state->u.f4.reg.lifcr = cm_object_get_child_by_name(obj, "LIFCR"); + state->u.f4.reg.hifcr = cm_object_get_child_by_name(obj, "HIFCR"); + state->u.f4.reg.s0cr = cm_object_get_child_by_name(obj, "S0CR"); + state->u.f4.reg.s0ndtr = cm_object_get_child_by_name(obj, "S0NDTR"); + state->u.f4.reg.s0par = cm_object_get_child_by_name(obj, "S0PAR"); + state->u.f4.reg.s0m0ar = cm_object_get_child_by_name(obj, "S0M0AR"); + state->u.f4.reg.s0m1ar = cm_object_get_child_by_name(obj, "S0M1AR"); + state->u.f4.reg.s0fcr = cm_object_get_child_by_name(obj, "S0FCR"); + state->u.f4.reg.s1cr = cm_object_get_child_by_name(obj, "S1CR"); + state->u.f4.reg.s1ndtr = cm_object_get_child_by_name(obj, "S1NDTR"); + state->u.f4.reg.s1par = cm_object_get_child_by_name(obj, "S1PAR"); + state->u.f4.reg.s1m0ar = cm_object_get_child_by_name(obj, "S1M0AR"); + state->u.f4.reg.s1m1ar = cm_object_get_child_by_name(obj, "S1M1AR"); + state->u.f4.reg.s1fcr = cm_object_get_child_by_name(obj, "S1FCR"); + state->u.f4.reg.s2cr = cm_object_get_child_by_name(obj, "S2CR"); + state->u.f4.reg.s2ndtr = cm_object_get_child_by_name(obj, "S2NDTR"); + state->u.f4.reg.s2par = cm_object_get_child_by_name(obj, "S2PAR"); + state->u.f4.reg.s2m0ar = cm_object_get_child_by_name(obj, "S2M0AR"); + state->u.f4.reg.s2m1ar = cm_object_get_child_by_name(obj, "S2M1AR"); + state->u.f4.reg.s2fcr = cm_object_get_child_by_name(obj, "S2FCR"); + state->u.f4.reg.s3cr = cm_object_get_child_by_name(obj, "S3CR"); + state->u.f4.reg.s3ndtr = cm_object_get_child_by_name(obj, "S3NDTR"); + state->u.f4.reg.s3par = cm_object_get_child_by_name(obj, "S3PAR"); + state->u.f4.reg.s3m0ar = cm_object_get_child_by_name(obj, "S3M0AR"); + state->u.f4.reg.s3m1ar = cm_object_get_child_by_name(obj, "S3M1AR"); + state->u.f4.reg.s3fcr = cm_object_get_child_by_name(obj, "S3FCR"); + state->u.f4.reg.s4cr = cm_object_get_child_by_name(obj, "S4CR"); + state->u.f4.reg.s4ndtr = cm_object_get_child_by_name(obj, "S4NDTR"); + state->u.f4.reg.s4par = cm_object_get_child_by_name(obj, "S4PAR"); + state->u.f4.reg.s4m0ar = cm_object_get_child_by_name(obj, "S4M0AR"); + state->u.f4.reg.s4m1ar = cm_object_get_child_by_name(obj, "S4M1AR"); + state->u.f4.reg.s4fcr = cm_object_get_child_by_name(obj, "S4FCR"); + state->u.f4.reg.s5cr = cm_object_get_child_by_name(obj, "S5CR"); + state->u.f4.reg.s5ndtr = cm_object_get_child_by_name(obj, "S5NDTR"); + state->u.f4.reg.s5par = cm_object_get_child_by_name(obj, "S5PAR"); + state->u.f4.reg.s5m0ar = cm_object_get_child_by_name(obj, "S5M0AR"); + state->u.f4.reg.s5m1ar = cm_object_get_child_by_name(obj, "S5M1AR"); + state->u.f4.reg.s5fcr = cm_object_get_child_by_name(obj, "S5FCR"); + state->u.f4.reg.s6cr = cm_object_get_child_by_name(obj, "S6CR"); + state->u.f4.reg.s6ndtr = cm_object_get_child_by_name(obj, "S6NDTR"); + state->u.f4.reg.s6par = cm_object_get_child_by_name(obj, "S6PAR"); + state->u.f4.reg.s6m0ar = cm_object_get_child_by_name(obj, "S6M0AR"); + state->u.f4.reg.s6m1ar = cm_object_get_child_by_name(obj, "S6M1AR"); + state->u.f4.reg.s6fcr = cm_object_get_child_by_name(obj, "S6FCR"); + state->u.f4.reg.s7cr = cm_object_get_child_by_name(obj, "S7CR"); + state->u.f4.reg.s7ndtr = cm_object_get_child_by_name(obj, "S7NDTR"); + state->u.f4.reg.s7par = cm_object_get_child_by_name(obj, "S7PAR"); + state->u.f4.reg.s7m0ar = cm_object_get_child_by_name(obj, "S7M0AR"); + state->u.f4.reg.s7m1ar = cm_object_get_child_by_name(obj, "S7M1AR"); + state->u.f4.reg.s7fcr = cm_object_get_child_by_name(obj, "S7FCR"); + + + // LISR bitfields. + state->u.f4.fld.lisr.feif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF0"); + state->u.f4.fld.lisr.dmeif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF0"); + state->u.f4.fld.lisr.teif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF0"); + state->u.f4.fld.lisr.htif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF0"); + state->u.f4.fld.lisr.tcif0 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF0"); + state->u.f4.fld.lisr.feif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF1"); + state->u.f4.fld.lisr.dmeif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF1"); + state->u.f4.fld.lisr.teif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF1"); + state->u.f4.fld.lisr.htif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF1"); + state->u.f4.fld.lisr.tcif1 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF1"); + state->u.f4.fld.lisr.feif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF2"); + state->u.f4.fld.lisr.dmeif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF2"); + state->u.f4.fld.lisr.teif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF2"); + state->u.f4.fld.lisr.htif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF2"); + state->u.f4.fld.lisr.tcif2 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF2"); + state->u.f4.fld.lisr.feif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "FEIF3"); + state->u.f4.fld.lisr.dmeif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "DMEIF3"); + state->u.f4.fld.lisr.teif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TEIF3"); + state->u.f4.fld.lisr.htif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "HTIF3"); + state->u.f4.fld.lisr.tcif3 = cm_object_get_child_by_name(state->u.f4.reg.lisr, "TCIF3"); + + // HISR bitfields. + state->u.f4.fld.hisr.feif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF4"); + state->u.f4.fld.hisr.dmeif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF4"); + state->u.f4.fld.hisr.teif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF4"); + state->u.f4.fld.hisr.htif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF4"); + state->u.f4.fld.hisr.tcif4 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF4"); + state->u.f4.fld.hisr.feif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF5"); + state->u.f4.fld.hisr.dmeif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF5"); + state->u.f4.fld.hisr.teif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF5"); + state->u.f4.fld.hisr.htif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF5"); + state->u.f4.fld.hisr.tcif5 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF5"); + state->u.f4.fld.hisr.feif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF6"); + state->u.f4.fld.hisr.dmeif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF6"); + state->u.f4.fld.hisr.teif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF6"); + state->u.f4.fld.hisr.htif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF6"); + state->u.f4.fld.hisr.tcif6 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF6"); + state->u.f4.fld.hisr.feif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "FEIF7"); + state->u.f4.fld.hisr.dmeif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "DMEIF7"); + state->u.f4.fld.hisr.teif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TEIF7"); + state->u.f4.fld.hisr.htif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "HTIF7"); + state->u.f4.fld.hisr.tcif7 = cm_object_get_child_by_name(state->u.f4.reg.hisr, "TCIF7"); + + // LIFCR bitfields. + state->u.f4.fld.lifcr.cfeif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF0"); + state->u.f4.fld.lifcr.cdmeif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF0"); + state->u.f4.fld.lifcr.cteif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF0"); + state->u.f4.fld.lifcr.chtif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF0"); + state->u.f4.fld.lifcr.ctcif0 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF0"); + state->u.f4.fld.lifcr.cfeif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF1"); + state->u.f4.fld.lifcr.cdmeif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF1"); + state->u.f4.fld.lifcr.cteif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF1"); + state->u.f4.fld.lifcr.chtif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF1"); + state->u.f4.fld.lifcr.ctcif1 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF1"); + state->u.f4.fld.lifcr.cfeif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF2"); + state->u.f4.fld.lifcr.cdmeif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF2"); + state->u.f4.fld.lifcr.cteif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF2"); + state->u.f4.fld.lifcr.chtif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF2"); + state->u.f4.fld.lifcr.ctcif2 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF2"); + state->u.f4.fld.lifcr.cfeif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CFEIF3"); + state->u.f4.fld.lifcr.cdmeif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CDMEIF3"); + state->u.f4.fld.lifcr.cteif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTEIF3"); + state->u.f4.fld.lifcr.chtif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CHTIF3"); + state->u.f4.fld.lifcr.ctcif3 = cm_object_get_child_by_name(state->u.f4.reg.lifcr, "CTCIF3"); + + // HIFCR bitfields. + state->u.f4.fld.hifcr.cfeif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF4"); + state->u.f4.fld.hifcr.cdmeif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF4"); + state->u.f4.fld.hifcr.cteif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF4"); + state->u.f4.fld.hifcr.chtif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF4"); + state->u.f4.fld.hifcr.ctcif4 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF4"); + state->u.f4.fld.hifcr.cfeif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF5"); + state->u.f4.fld.hifcr.cdmeif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF5"); + state->u.f4.fld.hifcr.cteif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF5"); + state->u.f4.fld.hifcr.chtif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF5"); + state->u.f4.fld.hifcr.ctcif5 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF5"); + state->u.f4.fld.hifcr.cfeif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF6"); + state->u.f4.fld.hifcr.cdmeif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF6"); + state->u.f4.fld.hifcr.cteif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF6"); + state->u.f4.fld.hifcr.chtif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF6"); + state->u.f4.fld.hifcr.ctcif6 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF6"); + state->u.f4.fld.hifcr.cfeif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CFEIF7"); + state->u.f4.fld.hifcr.cdmeif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CDMEIF7"); + state->u.f4.fld.hifcr.cteif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTEIF7"); + state->u.f4.fld.hifcr.chtif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CHTIF7"); + state->u.f4.fld.hifcr.ctcif7 = cm_object_get_child_by_name(state->u.f4.reg.hifcr, "CTCIF7"); + + // S0CR bitfields. + state->u.f4.fld.s0cr.en = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "EN"); + state->u.f4.fld.s0cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DMEIE"); + state->u.f4.fld.s0cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "TEIE"); + state->u.f4.fld.s0cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "HTIE"); + state->u.f4.fld.s0cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "TCIE"); + state->u.f4.fld.s0cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PFCTRL"); + state->u.f4.fld.s0cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DIR"); + state->u.f4.fld.s0cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CIRC"); + state->u.f4.fld.s0cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PINC"); + state->u.f4.fld.s0cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MINC"); + state->u.f4.fld.s0cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PSIZE"); + state->u.f4.fld.s0cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MSIZE"); + state->u.f4.fld.s0cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PINCOS"); + state->u.f4.fld.s0cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PL"); + state->u.f4.fld.s0cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "DBM"); + state->u.f4.fld.s0cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CT"); + state->u.f4.fld.s0cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "PBURST"); + state->u.f4.fld.s0cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "MBURST"); + state->u.f4.fld.s0cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s0cr, "CHSEL"); + + // S0NDTR bitfields. + state->u.f4.fld.s0ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s0ndtr, "NDT"); + + // S0PAR bitfields. + state->u.f4.fld.s0par.pa = cm_object_get_child_by_name(state->u.f4.reg.s0par, "PA"); + + // S0M0AR bitfields. + state->u.f4.fld.s0m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s0m0ar, "M0A"); + + // S0M1AR bitfields. + state->u.f4.fld.s0m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s0m1ar, "M1A"); + + // S0FCR bitfields. + state->u.f4.fld.s0fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FTH"); + state->u.f4.fld.s0fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "DMDIS"); + state->u.f4.fld.s0fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FS"); + state->u.f4.fld.s0fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s0fcr, "FEIE"); + + // S1CR bitfields. + state->u.f4.fld.s1cr.en = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "EN"); + state->u.f4.fld.s1cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DMEIE"); + state->u.f4.fld.s1cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "TEIE"); + state->u.f4.fld.s1cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "HTIE"); + state->u.f4.fld.s1cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "TCIE"); + state->u.f4.fld.s1cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PFCTRL"); + state->u.f4.fld.s1cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DIR"); + state->u.f4.fld.s1cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CIRC"); + state->u.f4.fld.s1cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PINC"); + state->u.f4.fld.s1cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MINC"); + state->u.f4.fld.s1cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PSIZE"); + state->u.f4.fld.s1cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MSIZE"); + state->u.f4.fld.s1cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PINCOS"); + state->u.f4.fld.s1cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PL"); + state->u.f4.fld.s1cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "DBM"); + state->u.f4.fld.s1cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CT"); + state->u.f4.fld.s1cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "ACK"); + state->u.f4.fld.s1cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "PBURST"); + state->u.f4.fld.s1cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "MBURST"); + state->u.f4.fld.s1cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s1cr, "CHSEL"); + + // S1NDTR bitfields. + state->u.f4.fld.s1ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s1ndtr, "NDT"); + + // S1PAR bitfields. + state->u.f4.fld.s1par.pa = cm_object_get_child_by_name(state->u.f4.reg.s1par, "PA"); + + // S1M0AR bitfields. + state->u.f4.fld.s1m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s1m0ar, "M0A"); + + // S1M1AR bitfields. + state->u.f4.fld.s1m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s1m1ar, "M1A"); + + // S1FCR bitfields. + state->u.f4.fld.s1fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FTH"); + state->u.f4.fld.s1fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "DMDIS"); + state->u.f4.fld.s1fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FS"); + state->u.f4.fld.s1fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s1fcr, "FEIE"); + + // S2CR bitfields. + state->u.f4.fld.s2cr.en = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "EN"); + state->u.f4.fld.s2cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DMEIE"); + state->u.f4.fld.s2cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "TEIE"); + state->u.f4.fld.s2cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "HTIE"); + state->u.f4.fld.s2cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "TCIE"); + state->u.f4.fld.s2cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PFCTRL"); + state->u.f4.fld.s2cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DIR"); + state->u.f4.fld.s2cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CIRC"); + state->u.f4.fld.s2cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PINC"); + state->u.f4.fld.s2cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MINC"); + state->u.f4.fld.s2cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PSIZE"); + state->u.f4.fld.s2cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MSIZE"); + state->u.f4.fld.s2cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PINCOS"); + state->u.f4.fld.s2cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PL"); + state->u.f4.fld.s2cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "DBM"); + state->u.f4.fld.s2cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CT"); + state->u.f4.fld.s2cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "ACK"); + state->u.f4.fld.s2cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "PBURST"); + state->u.f4.fld.s2cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "MBURST"); + state->u.f4.fld.s2cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s2cr, "CHSEL"); + + // S2NDTR bitfields. + state->u.f4.fld.s2ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s2ndtr, "NDT"); + + // S2PAR bitfields. + state->u.f4.fld.s2par.pa = cm_object_get_child_by_name(state->u.f4.reg.s2par, "PA"); + + // S2M0AR bitfields. + state->u.f4.fld.s2m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s2m0ar, "M0A"); + + // S2M1AR bitfields. + state->u.f4.fld.s2m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s2m1ar, "M1A"); + + // S2FCR bitfields. + state->u.f4.fld.s2fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FTH"); + state->u.f4.fld.s2fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "DMDIS"); + state->u.f4.fld.s2fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FS"); + state->u.f4.fld.s2fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s2fcr, "FEIE"); + + // S3CR bitfields. + state->u.f4.fld.s3cr.en = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "EN"); + state->u.f4.fld.s3cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DMEIE"); + state->u.f4.fld.s3cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "TEIE"); + state->u.f4.fld.s3cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "HTIE"); + state->u.f4.fld.s3cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "TCIE"); + state->u.f4.fld.s3cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PFCTRL"); + state->u.f4.fld.s3cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DIR"); + state->u.f4.fld.s3cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CIRC"); + state->u.f4.fld.s3cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PINC"); + state->u.f4.fld.s3cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MINC"); + state->u.f4.fld.s3cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PSIZE"); + state->u.f4.fld.s3cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MSIZE"); + state->u.f4.fld.s3cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PINCOS"); + state->u.f4.fld.s3cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PL"); + state->u.f4.fld.s3cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "DBM"); + state->u.f4.fld.s3cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CT"); + state->u.f4.fld.s3cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "ACK"); + state->u.f4.fld.s3cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "PBURST"); + state->u.f4.fld.s3cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "MBURST"); + state->u.f4.fld.s3cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s3cr, "CHSEL"); + + // S3NDTR bitfields. + state->u.f4.fld.s3ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s3ndtr, "NDT"); + + // S3PAR bitfields. + state->u.f4.fld.s3par.pa = cm_object_get_child_by_name(state->u.f4.reg.s3par, "PA"); + + // S3M0AR bitfields. + state->u.f4.fld.s3m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s3m0ar, "M0A"); + + // S3M1AR bitfields. + state->u.f4.fld.s3m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s3m1ar, "M1A"); + + // S3FCR bitfields. + state->u.f4.fld.s3fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FTH"); + state->u.f4.fld.s3fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "DMDIS"); + state->u.f4.fld.s3fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FS"); + state->u.f4.fld.s3fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s3fcr, "FEIE"); + + // S4CR bitfields. + state->u.f4.fld.s4cr.en = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "EN"); + state->u.f4.fld.s4cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DMEIE"); + state->u.f4.fld.s4cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "TEIE"); + state->u.f4.fld.s4cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "HTIE"); + state->u.f4.fld.s4cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "TCIE"); + state->u.f4.fld.s4cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PFCTRL"); + state->u.f4.fld.s4cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DIR"); + state->u.f4.fld.s4cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CIRC"); + state->u.f4.fld.s4cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PINC"); + state->u.f4.fld.s4cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MINC"); + state->u.f4.fld.s4cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PSIZE"); + state->u.f4.fld.s4cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MSIZE"); + state->u.f4.fld.s4cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PINCOS"); + state->u.f4.fld.s4cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PL"); + state->u.f4.fld.s4cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "DBM"); + state->u.f4.fld.s4cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CT"); + state->u.f4.fld.s4cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "ACK"); + state->u.f4.fld.s4cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "PBURST"); + state->u.f4.fld.s4cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "MBURST"); + state->u.f4.fld.s4cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s4cr, "CHSEL"); + + // S4NDTR bitfields. + state->u.f4.fld.s4ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s4ndtr, "NDT"); + + // S4PAR bitfields. + state->u.f4.fld.s4par.pa = cm_object_get_child_by_name(state->u.f4.reg.s4par, "PA"); + + // S4M0AR bitfields. + state->u.f4.fld.s4m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s4m0ar, "M0A"); + + // S4M1AR bitfields. + state->u.f4.fld.s4m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s4m1ar, "M1A"); + + // S4FCR bitfields. + state->u.f4.fld.s4fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FTH"); + state->u.f4.fld.s4fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "DMDIS"); + state->u.f4.fld.s4fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FS"); + state->u.f4.fld.s4fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s4fcr, "FEIE"); + + // S5CR bitfields. + state->u.f4.fld.s5cr.en = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "EN"); + state->u.f4.fld.s5cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DMEIE"); + state->u.f4.fld.s5cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "TEIE"); + state->u.f4.fld.s5cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "HTIE"); + state->u.f4.fld.s5cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "TCIE"); + state->u.f4.fld.s5cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PFCTRL"); + state->u.f4.fld.s5cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DIR"); + state->u.f4.fld.s5cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CIRC"); + state->u.f4.fld.s5cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PINC"); + state->u.f4.fld.s5cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MINC"); + state->u.f4.fld.s5cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PSIZE"); + state->u.f4.fld.s5cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MSIZE"); + state->u.f4.fld.s5cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PINCOS"); + state->u.f4.fld.s5cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PL"); + state->u.f4.fld.s5cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "DBM"); + state->u.f4.fld.s5cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CT"); + state->u.f4.fld.s5cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "ACK"); + state->u.f4.fld.s5cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "PBURST"); + state->u.f4.fld.s5cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "MBURST"); + state->u.f4.fld.s5cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s5cr, "CHSEL"); + + // S5NDTR bitfields. + state->u.f4.fld.s5ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s5ndtr, "NDT"); + + // S5PAR bitfields. + state->u.f4.fld.s5par.pa = cm_object_get_child_by_name(state->u.f4.reg.s5par, "PA"); + + // S5M0AR bitfields. + state->u.f4.fld.s5m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s5m0ar, "M0A"); + + // S5M1AR bitfields. + state->u.f4.fld.s5m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s5m1ar, "M1A"); + + // S5FCR bitfields. + state->u.f4.fld.s5fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FTH"); + state->u.f4.fld.s5fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "DMDIS"); + state->u.f4.fld.s5fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FS"); + state->u.f4.fld.s5fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s5fcr, "FEIE"); + + // S6CR bitfields. + state->u.f4.fld.s6cr.en = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "EN"); + state->u.f4.fld.s6cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DMEIE"); + state->u.f4.fld.s6cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "TEIE"); + state->u.f4.fld.s6cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "HTIE"); + state->u.f4.fld.s6cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "TCIE"); + state->u.f4.fld.s6cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PFCTRL"); + state->u.f4.fld.s6cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DIR"); + state->u.f4.fld.s6cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CIRC"); + state->u.f4.fld.s6cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PINC"); + state->u.f4.fld.s6cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MINC"); + state->u.f4.fld.s6cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PSIZE"); + state->u.f4.fld.s6cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MSIZE"); + state->u.f4.fld.s6cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PINCOS"); + state->u.f4.fld.s6cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PL"); + state->u.f4.fld.s6cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "DBM"); + state->u.f4.fld.s6cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CT"); + state->u.f4.fld.s6cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "ACK"); + state->u.f4.fld.s6cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "PBURST"); + state->u.f4.fld.s6cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "MBURST"); + state->u.f4.fld.s6cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s6cr, "CHSEL"); + + // S6NDTR bitfields. + state->u.f4.fld.s6ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s6ndtr, "NDT"); + + // S6PAR bitfields. + state->u.f4.fld.s6par.pa = cm_object_get_child_by_name(state->u.f4.reg.s6par, "PA"); + + // S6M0AR bitfields. + state->u.f4.fld.s6m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s6m0ar, "M0A"); + + // S6M1AR bitfields. + state->u.f4.fld.s6m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s6m1ar, "M1A"); + + // S6FCR bitfields. + state->u.f4.fld.s6fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FTH"); + state->u.f4.fld.s6fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "DMDIS"); + state->u.f4.fld.s6fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FS"); + state->u.f4.fld.s6fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s6fcr, "FEIE"); + + // S7CR bitfields. + state->u.f4.fld.s7cr.en = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "EN"); + state->u.f4.fld.s7cr.dmeie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DMEIE"); + state->u.f4.fld.s7cr.teie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "TEIE"); + state->u.f4.fld.s7cr.htie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "HTIE"); + state->u.f4.fld.s7cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "TCIE"); + state->u.f4.fld.s7cr.pfctrl = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PFCTRL"); + state->u.f4.fld.s7cr.dir = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DIR"); + state->u.f4.fld.s7cr.circ = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CIRC"); + state->u.f4.fld.s7cr.pinc = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PINC"); + state->u.f4.fld.s7cr.minc = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MINC"); + state->u.f4.fld.s7cr.psize = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PSIZE"); + state->u.f4.fld.s7cr.msize = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MSIZE"); + state->u.f4.fld.s7cr.pincos = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PINCOS"); + state->u.f4.fld.s7cr.pl = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PL"); + state->u.f4.fld.s7cr.dbm = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "DBM"); + state->u.f4.fld.s7cr.ct = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CT"); + state->u.f4.fld.s7cr.ack = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "ACK"); + state->u.f4.fld.s7cr.pburst = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "PBURST"); + state->u.f4.fld.s7cr.mburst = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "MBURST"); + state->u.f4.fld.s7cr.chsel = cm_object_get_child_by_name(state->u.f4.reg.s7cr, "CHSEL"); + + // S7NDTR bitfields. + state->u.f4.fld.s7ndtr.ndt = cm_object_get_child_by_name(state->u.f4.reg.s7ndtr, "NDT"); + + // S7PAR bitfields. + state->u.f4.fld.s7par.pa = cm_object_get_child_by_name(state->u.f4.reg.s7par, "PA"); + + // S7M0AR bitfields. + state->u.f4.fld.s7m0ar.m0a = cm_object_get_child_by_name(state->u.f4.reg.s7m0ar, "M0A"); + + // S7M1AR bitfields. + state->u.f4.fld.s7m1ar.m1a = cm_object_get_child_by_name(state->u.f4.reg.s7m1ar, "M1A"); + + // S7FCR bitfields. + state->u.f4.fld.s7fcr.fth = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FTH"); + state->u.f4.fld.s7fcr.dmdis = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "DMDIS"); + state->u.f4.fld.s7fcr.fs = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FS"); + state->u.f4.fld.s7fcr.feie = cm_object_get_child_by_name(state->u.f4.reg.s7fcr, "FEIE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMAState *state = STM32_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma_is_enabled(Object *obj) +{ + STM32DMAState *state = STM32_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMAState *state = STM32_DMA_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_DMA_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMAState *state = STM32_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA%dEN", + 1 + state->port_index - STM32_PORT_DMA1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA); +} + +static void stm32_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma_reset_callback; + dc->realize = stm32_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma_is_enabled; +} + +static const TypeInfo stm32_dma_type_info = { + .name = TYPE_STM32_DMA, + .parent = TYPE_STM32_DMA_PARENT, + .instance_init = stm32_dma_instance_init_callback, + .instance_size = sizeof(STM32DMAState), + .class_init = stm32_dma_class_init_callback, + .class_size = sizeof(STM32DMAClass) }; + +static void stm32_dma_register_types(void) +{ + type_register_static(&stm32_dma_type_info); +} + +type_init(stm32_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dma2.h b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2.h new file mode 100644 index 0000000000..b8356b45c9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2.h @@ -0,0 +1,673 @@ +/* + * STM32 - DMA (DMA controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA_H_ +#define STM32_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMA DEVICE_PATH_STM32 "DMA" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_DMA1, + STM32_PORT_DMA2, + STM32_PORT_DMA_UNDEFINED = 0xFF, +} stm32_dma_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMA TYPE_STM32_PREFIX "dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMAParentClass; +typedef PeripheralState STM32DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMAClass, (obj), TYPE_STM32_DMA) +#define STM32_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMAClass, (klass), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentClass parent_class; + // public: + + // None, so far. +} STM32DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA_STATE(obj) \ + OBJECT_CHECK(STM32DMAState, (obj), TYPE_STM32_DMA) + +typedef struct { + // private: + STM32DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_dma_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DMA (DMA controller) registers. + struct { + Object *lisr; // 0x0 (Low interrupt status register) + Object *hisr; // 0x4 (High interrupt status register) + Object *lifcr; // 0x8 (Low interrupt flag clear register) + Object *hifcr; // 0xC (High interrupt flag clear register) + Object *s0cr; // 0x10 (Stream x configuration register) + Object *s0ndtr; // 0x14 (Stream x number of data register) + Object *s0par; // 0x18 (Stream x peripheral address register) + Object *s0m0ar; // 0x1C (Stream x memory 0 address register) + Object *s0m1ar; // 0x20 (Stream x memory 1 address register) + Object *s0fcr; // 0x24 (Stream x FIFO control register) + Object *s1cr; // 0x28 (Stream x configuration register) + Object *s1ndtr; // 0x2C (Stream x number of data register) + Object *s1par; // 0x30 (Stream x peripheral address register) + Object *s1m0ar; // 0x34 (Stream x memory 0 address register) + Object *s1m1ar; // 0x38 (Stream x memory 1 address register) + Object *s1fcr; // 0x3C (Stream x FIFO control register) + Object *s2cr; // 0x40 (Stream x configuration register) + Object *s2ndtr; // 0x44 (Stream x number of data register) + Object *s2par; // 0x48 (Stream x peripheral address register) + Object *s2m0ar; // 0x4C (Stream x memory 0 address register) + Object *s2m1ar; // 0x50 (Stream x memory 1 address register) + Object *s2fcr; // 0x54 (Stream x FIFO control register) + Object *s3cr; // 0x58 (Stream x configuration register) + Object *s3ndtr; // 0x5C (Stream x number of data register) + Object *s3par; // 0x60 (Stream x peripheral address register) + Object *s3m0ar; // 0x64 (Stream x memory 0 address register) + Object *s3m1ar; // 0x68 (Stream x memory 1 address register) + Object *s3fcr; // 0x6C (Stream x FIFO control register) + Object *s4cr; // 0x70 (Stream x configuration register) + Object *s4ndtr; // 0x74 (Stream x number of data register) + Object *s4par; // 0x78 (Stream x peripheral address register) + Object *s4m0ar; // 0x7C (Stream x memory 0 address register) + Object *s4m1ar; // 0x80 (Stream x memory 1 address register) + Object *s4fcr; // 0x84 (Stream x FIFO control register) + Object *s5cr; // 0x88 (Stream x configuration register) + Object *s5ndtr; // 0x8C (Stream x number of data register) + Object *s5par; // 0x90 (Stream x peripheral address register) + Object *s5m0ar; // 0x94 (Stream x memory 0 address register) + Object *s5m1ar; // 0x98 (Stream x memory 1 address register) + Object *s5fcr; // 0x9C (Stream x FIFO control register) + Object *s6cr; // 0xA0 (Stream x configuration register) + Object *s6ndtr; // 0xA4 (Stream x number of data register) + Object *s6par; // 0xA8 (Stream x peripheral address register) + Object *s6m0ar; // 0xAC (Stream x memory 0 address register) + Object *s6m1ar; // 0xB0 (Stream x memory 1 address register) + Object *s6fcr; // 0xB4 (Stream x FIFO control register) + Object *s7cr; // 0xB8 (Stream x configuration register) + Object *s7ndtr; // 0xBC (Stream x number of data register) + Object *s7par; // 0xC0 (Stream x peripheral address register) + Object *s7m0ar; // 0xC4 (Stream x memory 0 address register) + Object *s7m1ar; // 0xC8 (Stream x memory 1 address register) + Object *s7fcr; // 0xCC (Stream x FIFO control register) + } reg; + + struct { + + // LISR (Low interrupt status register) bitfields. + struct { + Object *feif0; // [0:0] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif0; // [2:2] Stream x direct mode error interrupt flag (x=3..0) + Object *teif0; // [3:3] Stream x transfer error interrupt flag (x=3..0) + Object *htif0; // [4:4] Stream x half transfer interrupt flag (x=3..0) + Object *tcif0; // [5:5] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif1; // [6:6] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif1; // [8:8] Stream x direct mode error interrupt flag (x=3..0) + Object *teif1; // [9:9] Stream x transfer error interrupt flag (x=3..0) + Object *htif1; // [10:10] Stream x half transfer interrupt flag (x=3..0) + Object *tcif1; // [11:11] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif2; // [16:16] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif2; // [18:18] Stream x direct mode error interrupt flag (x=3..0) + Object *teif2; // [19:19] Stream x transfer error interrupt flag (x=3..0) + Object *htif2; // [20:20] Stream x half transfer interrupt flag (x=3..0) + Object *tcif2; // [21:21] Stream x transfer complete interrupt flag (x = 3..0) + Object *feif3; // [22:22] Stream x FIFO error interrupt flag (x=3..0) + Object *dmeif3; // [24:24] Stream x direct mode error interrupt flag (x=3..0) + Object *teif3; // [25:25] Stream x transfer error interrupt flag (x=3..0) + Object *htif3; // [26:26] Stream x half transfer interrupt flag (x=3..0) + Object *tcif3; // [27:27] Stream x transfer complete interrupt flag (x = 3..0) + } lisr; + + // HISR (High interrupt status register) bitfields. + struct { + Object *feif4; // [0:0] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif4; // [2:2] Stream x direct mode error interrupt flag (x=7..4) + Object *teif4; // [3:3] Stream x transfer error interrupt flag (x=7..4) + Object *htif4; // [4:4] Stream x half transfer interrupt flag (x=7..4) + Object *tcif4; // [5:5] Stream x transfer complete interrupt flag (x=7..4) + Object *feif5; // [6:6] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif5; // [8:8] Stream x direct mode error interrupt flag (x=7..4) + Object *teif5; // [9:9] Stream x transfer error interrupt flag (x=7..4) + Object *htif5; // [10:10] Stream x half transfer interrupt flag (x=7..4) + Object *tcif5; // [11:11] Stream x transfer complete interrupt flag (x=7..4) + Object *feif6; // [16:16] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif6; // [18:18] Stream x direct mode error interrupt flag (x=7..4) + Object *teif6; // [19:19] Stream x transfer error interrupt flag (x=7..4) + Object *htif6; // [20:20] Stream x half transfer interrupt flag (x=7..4) + Object *tcif6; // [21:21] Stream x transfer complete interrupt flag (x=7..4) + Object *feif7; // [22:22] Stream x FIFO error interrupt flag (x=7..4) + Object *dmeif7; // [24:24] Stream x direct mode error interrupt flag (x=7..4) + Object *teif7; // [25:25] Stream x transfer error interrupt flag (x=7..4) + Object *htif7; // [26:26] Stream x half transfer interrupt flag (x=7..4) + Object *tcif7; // [27:27] Stream x transfer complete interrupt flag (x=7..4) + } hisr; + + // LIFCR (Low interrupt flag clear register) bitfields. + struct { + Object *cfeif0; // [0:0] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif0; // [2:2] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif0; // [3:3] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif0; // [4:4] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif0; // [5:5] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif1; // [6:6] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif1; // [8:8] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif1; // [9:9] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif1; // [10:10] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif1; // [11:11] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif2; // [16:16] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif2; // [18:18] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif2; // [19:19] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif2; // [20:20] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif2; // [21:21] Stream x clear transfer complete interrupt flag (x = 3..0) + Object *cfeif3; // [22:22] Stream x clear FIFO error interrupt flag (x = 3..0) + Object *cdmeif3; // [24:24] Stream x clear direct mode error interrupt flag (x = 3..0) + Object *cteif3; // [25:25] Stream x clear transfer error interrupt flag (x = 3..0) + Object *chtif3; // [26:26] Stream x clear half transfer interrupt flag (x = 3..0) + Object *ctcif3; // [27:27] Stream x clear transfer complete interrupt flag (x = 3..0) + } lifcr; + + // HIFCR (High interrupt flag clear register) bitfields. + struct { + Object *cfeif4; // [0:0] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif4; // [2:2] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif4; // [3:3] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif4; // [4:4] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif4; // [5:5] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif5; // [6:6] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif5; // [8:8] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif5; // [9:9] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif5; // [10:10] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif5; // [11:11] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif6; // [16:16] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif6; // [18:18] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif6; // [19:19] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif6; // [20:20] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif6; // [21:21] Stream x clear transfer complete interrupt flag (x = 7..4) + Object *cfeif7; // [22:22] Stream x clear FIFO error interrupt flag (x = 7..4) + Object *cdmeif7; // [24:24] Stream x clear direct mode error interrupt flag (x = 7..4) + Object *cteif7; // [25:25] Stream x clear transfer error interrupt flag (x = 7..4) + Object *chtif7; // [26:26] Stream x clear half transfer interrupt flag (x = 7..4) + Object *ctcif7; // [27:27] Stream x clear transfer complete interrupt flag (x = 7..4) + } hifcr; + + // S0CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s0cr; + + // S0NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s0ndtr; + + // S0PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s0par; + + // S0M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s0m0ar; + + // S0M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s0m1ar; + + // S0FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s0fcr; + + // S1CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s1cr; + + // S1NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s1ndtr; + + // S1PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s1par; + + // S1M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s1m0ar; + + // S1M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s1m1ar; + + // S1FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s1fcr; + + // S2CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s2cr; + + // S2NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s2ndtr; + + // S2PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s2par; + + // S2M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s2m0ar; + + // S2M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s2m1ar; + + // S2FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s2fcr; + + // S3CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s3cr; + + // S3NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s3ndtr; + + // S3PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s3par; + + // S3M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s3m0ar; + + // S3M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s3m1ar; + + // S3FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s3fcr; + + // S4CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s4cr; + + // S4NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s4ndtr; + + // S4PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s4par; + + // S4M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s4m0ar; + + // S4M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s4m1ar; + + // S4FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s4fcr; + + // S5CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s5cr; + + // S5NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s5ndtr; + + // S5PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s5par; + + // S5M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s5m0ar; + + // S5M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s5m1ar; + + // S5FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s5fcr; + + // S6CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s6cr; + + // S6NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s6ndtr; + + // S6PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s6par; + + // S6M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s6m0ar; + + // S6M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s6m1ar; + + // S6FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s6fcr; + + // S7CR (Stream x configuration register) bitfields. + struct { + Object *en; // [0:0] Stream enable / flag stream ready when read low + Object *dmeie; // [1:1] Direct mode error interrupt enable + Object *teie; // [2:2] Transfer error interrupt enable + Object *htie; // [3:3] Half transfer interrupt enable + Object *tcie; // [4:4] Transfer complete interrupt enable + Object *pfctrl; // [5:5] Peripheral flow controller + Object *dir; // [6:7] Data transfer direction + Object *circ; // [8:8] Circular mode + Object *pinc; // [9:9] Peripheral increment mode + Object *minc; // [10:10] Memory increment mode + Object *psize; // [11:12] Peripheral data size + Object *msize; // [13:14] Memory data size + Object *pincos; // [15:15] Peripheral increment offset size + Object *pl; // [16:17] Priority level + Object *dbm; // [18:18] Double buffer mode + Object *ct; // [19:19] Current target (only in double buffer mode) + Object *ack; // [20:20] ACK + Object *pburst; // [21:22] Peripheral burst transfer configuration + Object *mburst; // [23:24] Memory burst transfer configuration + Object *chsel; // [25:27] Channel selection + } s7cr; + + // S7NDTR (Stream x number of data register) bitfields. + struct { + Object *ndt; // [0:15] Number of data items to transfer + } s7ndtr; + + // S7PAR (Stream x peripheral address register) bitfields. + struct { + Object *pa; // [0:31] Peripheral address + } s7par; + + // S7M0AR (Stream x memory 0 address register) bitfields. + struct { + Object *m0a; // [0:31] Memory 0 address + } s7m0ar; + + // S7M1AR (Stream x memory 1 address register) bitfields. + struct { + Object *m1a; // [0:31] Memory 1 address (used in case of Double buffer mode) + } s7m1ar; + + // S7FCR (Stream x FIFO control register) bitfields. + struct { + Object *fth; // [0:1] FIFO threshold selection + Object *dmdis; // [2:2] Direct mode disable + Object *fs; // [3:5] FIFO status + Object *feie; // [7:7] FIFO error interrupt enable + } s7fcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dma2d.c b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2d.c new file mode 100644 index 0000000000..7d2a8ed307 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2d.c @@ -0,0 +1,366 @@ +/* + * STM32 - DMA2D (DMA2D controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_dma2d_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32DMA2DState *state = STM32_DMA2D_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f4.reg.ifcr = cm_object_get_child_by_name(obj, "IFCR"); + state->u.f4.reg.fgmar = cm_object_get_child_by_name(obj, "FGMAR"); + state->u.f4.reg.fgor = cm_object_get_child_by_name(obj, "FGOR"); + state->u.f4.reg.bgmar = cm_object_get_child_by_name(obj, "BGMAR"); + state->u.f4.reg.bgor = cm_object_get_child_by_name(obj, "BGOR"); + state->u.f4.reg.fgpfccr = cm_object_get_child_by_name(obj, "FGPFCCR"); + state->u.f4.reg.fgcolr = cm_object_get_child_by_name(obj, "FGCOLR"); + state->u.f4.reg.bgpfccr = cm_object_get_child_by_name(obj, "BGPFCCR"); + state->u.f4.reg.bgcolr = cm_object_get_child_by_name(obj, "BGCOLR"); + state->u.f4.reg.fgcmar = cm_object_get_child_by_name(obj, "FGCMAR"); + state->u.f4.reg.bgcmar = cm_object_get_child_by_name(obj, "BGCMAR"); + state->u.f4.reg.opfccr = cm_object_get_child_by_name(obj, "OPFCCR"); + state->u.f4.reg.ocolr = cm_object_get_child_by_name(obj, "OCOLR"); + state->u.f4.reg.omar = cm_object_get_child_by_name(obj, "OMAR"); + state->u.f4.reg.oor = cm_object_get_child_by_name(obj, "OOR"); + state->u.f4.reg.nlr = cm_object_get_child_by_name(obj, "NLR"); + state->u.f4.reg.lwr = cm_object_get_child_by_name(obj, "LWR"); + state->u.f4.reg.amtcr = cm_object_get_child_by_name(obj, "AMTCR"); + state->u.f4.reg.fgclut = cm_object_get_child_by_name(obj, "FGCLUT"); + state->u.f4.reg.bgclut = cm_object_get_child_by_name(obj, "BGCLUT"); + + + // CR bitfields. + state->u.f4.fld.cr.start = cm_object_get_child_by_name(state->u.f4.reg.cr, "START"); + state->u.f4.fld.cr.susp = cm_object_get_child_by_name(state->u.f4.reg.cr, "SUSP"); + state->u.f4.fld.cr.abort = cm_object_get_child_by_name(state->u.f4.reg.cr, "ABORT"); + state->u.f4.fld.cr.teie = cm_object_get_child_by_name(state->u.f4.reg.cr, "TEIE"); + state->u.f4.fld.cr.tcie = cm_object_get_child_by_name(state->u.f4.reg.cr, "TCIE"); + state->u.f4.fld.cr.twie = cm_object_get_child_by_name(state->u.f4.reg.cr, "TWIE"); + state->u.f4.fld.cr.caeie = cm_object_get_child_by_name(state->u.f4.reg.cr, "CAEIE"); + state->u.f4.fld.cr.ctcie = cm_object_get_child_by_name(state->u.f4.reg.cr, "CTCIE"); + state->u.f4.fld.cr.ceie = cm_object_get_child_by_name(state->u.f4.reg.cr, "CEIE"); + state->u.f4.fld.cr.mode = cm_object_get_child_by_name(state->u.f4.reg.cr, "MODE"); + + // ISR bitfields. + state->u.f4.fld.isr.teif = cm_object_get_child_by_name(state->u.f4.reg.isr, "TEIF"); + state->u.f4.fld.isr.tcif = cm_object_get_child_by_name(state->u.f4.reg.isr, "TCIF"); + state->u.f4.fld.isr.twif = cm_object_get_child_by_name(state->u.f4.reg.isr, "TWIF"); + state->u.f4.fld.isr.caeif = cm_object_get_child_by_name(state->u.f4.reg.isr, "CAEIF"); + state->u.f4.fld.isr.ctcif = cm_object_get_child_by_name(state->u.f4.reg.isr, "CTCIF"); + state->u.f4.fld.isr.ceif = cm_object_get_child_by_name(state->u.f4.reg.isr, "CEIF"); + + // IFCR bitfields. + state->u.f4.fld.ifcr.cteif = cm_object_get_child_by_name(state->u.f4.reg.ifcr, "CTEIF"); + state->u.f4.fld.ifcr.ctcif = cm_object_get_child_by_name(state->u.f4.reg.ifcr, "CTCIF"); + state->u.f4.fld.ifcr.ctwif = cm_object_get_child_by_name(state->u.f4.reg.ifcr, "CTWIF"); + state->u.f4.fld.ifcr.caecif = cm_object_get_child_by_name(state->u.f4.reg.ifcr, "CAECIF"); + state->u.f4.fld.ifcr.cctcif = cm_object_get_child_by_name(state->u.f4.reg.ifcr, "CCTCIF"); + state->u.f4.fld.ifcr.cceif = cm_object_get_child_by_name(state->u.f4.reg.ifcr, "CCEIF"); + + // FGMAR bitfields. + state->u.f4.fld.fgmar.ma = cm_object_get_child_by_name(state->u.f4.reg.fgmar, "MA"); + + // FGOR bitfields. + state->u.f4.fld.fgor.lo = cm_object_get_child_by_name(state->u.f4.reg.fgor, "LO"); + + // BGMAR bitfields. + state->u.f4.fld.bgmar.ma = cm_object_get_child_by_name(state->u.f4.reg.bgmar, "MA"); + + // BGOR bitfields. + state->u.f4.fld.bgor.lo = cm_object_get_child_by_name(state->u.f4.reg.bgor, "LO"); + + // FGPFCCR bitfields. + state->u.f4.fld.fgpfccr.cm = cm_object_get_child_by_name(state->u.f4.reg.fgpfccr, "CM"); + state->u.f4.fld.fgpfccr.ccm = cm_object_get_child_by_name(state->u.f4.reg.fgpfccr, "CCM"); + state->u.f4.fld.fgpfccr.start = cm_object_get_child_by_name(state->u.f4.reg.fgpfccr, "START"); + state->u.f4.fld.fgpfccr.cs = cm_object_get_child_by_name(state->u.f4.reg.fgpfccr, "CS"); + state->u.f4.fld.fgpfccr.am = cm_object_get_child_by_name(state->u.f4.reg.fgpfccr, "AM"); + state->u.f4.fld.fgpfccr.alpha = cm_object_get_child_by_name(state->u.f4.reg.fgpfccr, "ALPHA"); + + // FGCOLR bitfields. + state->u.f4.fld.fgcolr.blue = cm_object_get_child_by_name(state->u.f4.reg.fgcolr, "BLUE"); + state->u.f4.fld.fgcolr.green = cm_object_get_child_by_name(state->u.f4.reg.fgcolr, "GREEN"); + state->u.f4.fld.fgcolr.red = cm_object_get_child_by_name(state->u.f4.reg.fgcolr, "RED"); + + // BGPFCCR bitfields. + state->u.f4.fld.bgpfccr.cm = cm_object_get_child_by_name(state->u.f4.reg.bgpfccr, "CM"); + state->u.f4.fld.bgpfccr.ccm = cm_object_get_child_by_name(state->u.f4.reg.bgpfccr, "CCM"); + state->u.f4.fld.bgpfccr.start = cm_object_get_child_by_name(state->u.f4.reg.bgpfccr, "START"); + state->u.f4.fld.bgpfccr.cs = cm_object_get_child_by_name(state->u.f4.reg.bgpfccr, "CS"); + state->u.f4.fld.bgpfccr.am = cm_object_get_child_by_name(state->u.f4.reg.bgpfccr, "AM"); + state->u.f4.fld.bgpfccr.alpha = cm_object_get_child_by_name(state->u.f4.reg.bgpfccr, "ALPHA"); + + // BGCOLR bitfields. + state->u.f4.fld.bgcolr.blue = cm_object_get_child_by_name(state->u.f4.reg.bgcolr, "BLUE"); + state->u.f4.fld.bgcolr.green = cm_object_get_child_by_name(state->u.f4.reg.bgcolr, "GREEN"); + state->u.f4.fld.bgcolr.red = cm_object_get_child_by_name(state->u.f4.reg.bgcolr, "RED"); + + // FGCMAR bitfields. + state->u.f4.fld.fgcmar.ma = cm_object_get_child_by_name(state->u.f4.reg.fgcmar, "MA"); + + // BGCMAR bitfields. + state->u.f4.fld.bgcmar.ma = cm_object_get_child_by_name(state->u.f4.reg.bgcmar, "MA"); + + // OPFCCR bitfields. + state->u.f4.fld.opfccr.cm = cm_object_get_child_by_name(state->u.f4.reg.opfccr, "CM"); + + // OCOLR bitfields. + state->u.f4.fld.ocolr.blue = cm_object_get_child_by_name(state->u.f4.reg.ocolr, "BLUE"); + state->u.f4.fld.ocolr.green = cm_object_get_child_by_name(state->u.f4.reg.ocolr, "GREEN"); + state->u.f4.fld.ocolr.red = cm_object_get_child_by_name(state->u.f4.reg.ocolr, "RED"); + state->u.f4.fld.ocolr.aplha = cm_object_get_child_by_name(state->u.f4.reg.ocolr, "APLHA"); + + // OMAR bitfields. + state->u.f4.fld.omar.ma = cm_object_get_child_by_name(state->u.f4.reg.omar, "MA"); + + // OOR bitfields. + state->u.f4.fld.oor.lo = cm_object_get_child_by_name(state->u.f4.reg.oor, "LO"); + + // NLR bitfields. + state->u.f4.fld.nlr.nl = cm_object_get_child_by_name(state->u.f4.reg.nlr, "NL"); + state->u.f4.fld.nlr.pl = cm_object_get_child_by_name(state->u.f4.reg.nlr, "PL"); + + // LWR bitfields. + state->u.f4.fld.lwr.lw = cm_object_get_child_by_name(state->u.f4.reg.lwr, "LW"); + + // AMTCR bitfields. + state->u.f4.fld.amtcr.en = cm_object_get_child_by_name(state->u.f4.reg.amtcr, "EN"); + state->u.f4.fld.amtcr.dt = cm_object_get_child_by_name(state->u.f4.reg.amtcr, "DT"); + + // FGCLUT bitfields. + state->u.f4.fld.fgclut.blue = cm_object_get_child_by_name(state->u.f4.reg.fgclut, "BLUE"); + state->u.f4.fld.fgclut.green = cm_object_get_child_by_name(state->u.f4.reg.fgclut, "GREEN"); + state->u.f4.fld.fgclut.red = cm_object_get_child_by_name(state->u.f4.reg.fgclut, "RED"); + state->u.f4.fld.fgclut.aplha = cm_object_get_child_by_name(state->u.f4.reg.fgclut, "APLHA"); + + // BGCLUT bitfields. + state->u.f4.fld.bgclut.blue = cm_object_get_child_by_name(state->u.f4.reg.bgclut, "BLUE"); + state->u.f4.fld.bgclut.green = cm_object_get_child_by_name(state->u.f4.reg.bgclut, "GREEN"); + state->u.f4.fld.bgclut.red = cm_object_get_child_by_name(state->u.f4.reg.bgclut, "RED"); + state->u.f4.fld.bgclut.aplha = cm_object_get_child_by_name(state->u.f4.reg.bgclut, "APLHA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_dma2d_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMA2DState *state = STM32_DMA2D_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_dma2d_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32DMA2DState *state = STM32_DMA2D_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_dma2d_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMA2DState *state = STM32_DMA2D_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_dma2d_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32DMA2DState *state = STM32_DMA2D_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_dma2d_is_enabled(Object *obj) +{ + STM32DMA2DState *state = STM32_DMA2D_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_dma2d_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32DMA2DState *state = STM32_DMA2D_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_dma2d_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_DMA2D)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32DMA2DState *state = STM32_DMA2D_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "DMA2D"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_dma2d_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma2d_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_dma2d_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_dma2d_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_dma2d_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/DMA2DEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_dma2d_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_DMA2D); +} + +static void stm32_dma2d_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_dma2d_reset_callback; + dc->realize = stm32_dma2d_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_dma2d_is_enabled; +} + +static const TypeInfo stm32_dma2d_type_info = { + .name = TYPE_STM32_DMA2D, + .parent = TYPE_STM32_DMA2D_PARENT, + .instance_init = stm32_dma2d_instance_init_callback, + .instance_size = sizeof(STM32DMA2DState), + .class_init = stm32_dma2d_class_init_callback, + .class_size = sizeof(STM32DMA2DClass) }; + +static void stm32_dma2d_register_types(void) +{ + type_register_static(&stm32_dma2d_type_info); +} + +type_init(stm32_dma2d_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/dma2d.h b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2d.h new file mode 100644 index 0000000000..21303c2cb8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/dma2d.h @@ -0,0 +1,275 @@ +/* + * STM32 - DMA2D (DMA2D controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_DMA2D_H_ +#define STM32_DMA2D_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_DMA2D DEVICE_PATH_STM32 "DMA2D" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_DMA2D TYPE_STM32_PREFIX "dma2d" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_DMA2D_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32DMA2DParentClass; +typedef PeripheralState STM32DMA2DParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_DMA2D_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32DMA2DClass, (obj), TYPE_STM32_DMA2D) +#define STM32_DMA2D_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32DMA2DClass, (klass), TYPE_STM32_DMA2D) + +typedef struct { + // private: + STM32DMA2DParentClass parent_class; + // public: + + // None, so far. +} STM32DMA2DClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_DMA2D_STATE(obj) \ + OBJECT_CHECK(STM32DMA2DState, (obj), TYPE_STM32_DMA2D) + +typedef struct { + // private: + STM32DMA2DParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 DMA2D (DMA2D controller) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *isr; // 0x4 (Interrupt Status Register) + Object *ifcr; // 0x8 (Interrupt flag clear register) + Object *fgmar; // 0xC (Foreground memory address register) + Object *fgor; // 0x10 (Foreground offset register) + Object *bgmar; // 0x14 (Background memory address register) + Object *bgor; // 0x18 (Background offset register) + Object *fgpfccr; // 0x1C (Foreground PFC control register) + Object *fgcolr; // 0x20 (Foreground color register) + Object *bgpfccr; // 0x24 (Background PFC control register) + Object *bgcolr; // 0x28 (Background color register) + Object *fgcmar; // 0x2C (Foreground CLUT memory address register) + Object *bgcmar; // 0x30 (Background CLUT memory address register) + Object *opfccr; // 0x34 (Output PFC control register) + Object *ocolr; // 0x38 (Output color register) + Object *omar; // 0x3C (Output memory address register) + Object *oor; // 0x40 (Output offset register) + Object *nlr; // 0x44 (Number of line register) + Object *lwr; // 0x48 (Line watermark register) + Object *amtcr; // 0x4C (AHB master timer configuration register) + Object *fgclut; // 0x400 (FGCLUT) + Object *bgclut; // 0x800 (BGCLUT) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *start; // [0:0] Start + Object *susp; // [1:1] Suspend + Object *abort; // [2:2] Abort + Object *teie; // [8:8] Transfer error interrupt enable + Object *tcie; // [9:9] Transfer complete interrupt enable + Object *twie; // [10:10] Transfer watermark interrupt enable + Object *caeie; // [11:11] CLUT access error interrupt enable + Object *ctcie; // [12:12] CLUT transfer complete interrupt enable + Object *ceie; // [13:13] Configuration Error Interrupt Enable + Object *mode; // [16:17] DMA2D mode + } cr; + + // ISR (Interrupt Status Register) bitfields. + struct { + Object *teif; // [0:0] Transfer error interrupt flag + Object *tcif; // [1:1] Transfer complete interrupt flag + Object *twif; // [2:2] Transfer watermark interrupt flag + Object *caeif; // [3:3] CLUT access error interrupt flag + Object *ctcif; // [4:4] CLUT transfer complete interrupt flag + Object *ceif; // [5:5] Configuration error interrupt flag + } isr; + + // IFCR (Interrupt flag clear register) bitfields. + struct { + Object *cteif; // [0:0] Clear Transfer error interrupt flag + Object *ctcif; // [1:1] Clear transfer complete interrupt flag + Object *ctwif; // [2:2] Clear transfer watermark interrupt flag + Object *caecif; // [3:3] Clear CLUT access error interrupt flag + Object *cctcif; // [4:4] Clear CLUT transfer complete interrupt flag + Object *cceif; // [5:5] Clear configuration error interrupt flag + } ifcr; + + // FGMAR (Foreground memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } fgmar; + + // FGOR (Foreground offset register) bitfields. + struct { + Object *lo; // [0:13] Line offset + } fgor; + + // BGMAR (Background memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } bgmar; + + // BGOR (Background offset register) bitfields. + struct { + Object *lo; // [0:13] Line offset + } bgor; + + // FGPFCCR (Foreground PFC control register) bitfields. + struct { + Object *cm; // [0:3] Color mode + Object *ccm; // [4:4] CLUT color mode + Object *start; // [5:5] Start + Object *cs; // [8:15] CLUT size + Object *am; // [16:17] Alpha mode + Object *alpha; // [24:31] Alpha value + } fgpfccr; + + // FGCOLR (Foreground color register) bitfields. + struct { + Object *blue; // [0:7] Blue Value + Object *green; // [8:15] Green Value + Object *red; // [16:23] Red Value + } fgcolr; + + // BGPFCCR (Background PFC control register) bitfields. + struct { + Object *cm; // [0:3] Color mode + Object *ccm; // [4:4] CLUT Color mode + Object *start; // [5:5] Start + Object *cs; // [8:15] CLUT size + Object *am; // [16:17] Alpha mode + Object *alpha; // [24:31] Alpha value + } bgpfccr; + + // BGCOLR (Background color register) bitfields. + struct { + Object *blue; // [0:7] Blue Value + Object *green; // [8:15] Green Value + Object *red; // [16:23] Red Value + } bgcolr; + + // FGCMAR (Foreground CLUT memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory Address + } fgcmar; + + // BGCMAR (Background CLUT memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory address + } bgcmar; + + // OPFCCR (Output PFC control register) bitfields. + struct { + Object *cm; // [0:2] Color mode + } opfccr; + + // OCOLR (Output color register) bitfields. + struct { + Object *blue; // [0:7] Blue Value + Object *green; // [8:15] Green Value + Object *red; // [16:23] Red Value + Object *aplha; // [24:31] Alpha Channel Value + } ocolr; + + // OMAR (Output memory address register) bitfields. + struct { + Object *ma; // [0:31] Memory Address + } omar; + + // OOR (Output offset register) bitfields. + struct { + Object *lo; // [0:13] Line Offset + } oor; + + // NLR (Number of line register) bitfields. + struct { + Object *nl; // [0:15] Number of lines + Object *pl; // [16:29] Pixel per lines + } nlr; + + // LWR (Line watermark register) bitfields. + struct { + Object *lw; // [0:15] Line watermark + } lwr; + + // AMTCR (AHB master timer configuration register) bitfields. + struct { + Object *en; // [0:0] Enable + Object *dt; // [8:15] Dead Time + } amtcr; + + // FGCLUT (FGCLUT) bitfields. + struct { + Object *blue; // [0:7] BLUE + Object *green; // [8:15] GREEN + Object *red; // [16:23] RED + Object *aplha; // [24:31] APLHA + } fgclut; + + // BGCLUT (BGCLUT) bitfields. + struct { + Object *blue; // [0:7] BLUE + Object *green; // [8:15] GREEN + Object *red; // [16:23] RED + Object *aplha; // [24:31] APLHA + } bgclut; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32DMA2DState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_DMA2D_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_dma.c b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_dma.c new file mode 100644 index 0000000000..3765346635 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_dma.c @@ -0,0 +1,349 @@ +/* + * STM32 - Ethernet_DMA (Ethernet: DMA controller operation) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_ethernet_dma_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.dmabmr = cm_object_get_child_by_name(obj, "DMABMR"); + state->u.f4.reg.dmatpdr = cm_object_get_child_by_name(obj, "DMATPDR"); + state->u.f4.reg.dmarpdr = cm_object_get_child_by_name(obj, "DMARPDR"); + state->u.f4.reg.dmardlar = cm_object_get_child_by_name(obj, "DMARDLAR"); + state->u.f4.reg.dmatdlar = cm_object_get_child_by_name(obj, "DMATDLAR"); + state->u.f4.reg.dmasr = cm_object_get_child_by_name(obj, "DMASR"); + state->u.f4.reg.dmaomr = cm_object_get_child_by_name(obj, "DMAOMR"); + state->u.f4.reg.dmaier = cm_object_get_child_by_name(obj, "DMAIER"); + state->u.f4.reg.dmamfbocr = cm_object_get_child_by_name(obj, "DMAMFBOCR"); + state->u.f4.reg.dmarswtr = cm_object_get_child_by_name(obj, "DMARSWTR"); + state->u.f4.reg.dmachtdr = cm_object_get_child_by_name(obj, "DMACHTDR"); + state->u.f4.reg.dmachrdr = cm_object_get_child_by_name(obj, "DMACHRDR"); + state->u.f4.reg.dmachtbar = cm_object_get_child_by_name(obj, "DMACHTBAR"); + state->u.f4.reg.dmachrbar = cm_object_get_child_by_name(obj, "DMACHRBAR"); + + + // DMABMR bitfields. + state->u.f4.fld.dmabmr.sr = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "SR"); + state->u.f4.fld.dmabmr.da = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "DA"); + state->u.f4.fld.dmabmr.dsl = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "DSL"); + state->u.f4.fld.dmabmr.edfe = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "EDFE"); + state->u.f4.fld.dmabmr.pbl = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "PBL"); + state->u.f4.fld.dmabmr.rtpr = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "RTPR"); + state->u.f4.fld.dmabmr.fb = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "FB"); + state->u.f4.fld.dmabmr.rdp = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "RDP"); + state->u.f4.fld.dmabmr.usp = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "USP"); + state->u.f4.fld.dmabmr.fpm = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "FPM"); + state->u.f4.fld.dmabmr.aab = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "AAB"); + state->u.f4.fld.dmabmr.mb = cm_object_get_child_by_name(state->u.f4.reg.dmabmr, "MB"); + + // DMATPDR bitfields. + state->u.f4.fld.dmatpdr.tpd = cm_object_get_child_by_name(state->u.f4.reg.dmatpdr, "TPD"); + + // DMARPDR bitfields. + state->u.f4.fld.dmarpdr.rpd = cm_object_get_child_by_name(state->u.f4.reg.dmarpdr, "RPD"); + + // DMARDLAR bitfields. + state->u.f4.fld.dmardlar.srl = cm_object_get_child_by_name(state->u.f4.reg.dmardlar, "SRL"); + + // DMATDLAR bitfields. + state->u.f4.fld.dmatdlar.stl = cm_object_get_child_by_name(state->u.f4.reg.dmatdlar, "STL"); + + // DMASR bitfields. + state->u.f4.fld.dmasr.ts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TS"); + state->u.f4.fld.dmasr.tpss = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TPSS"); + state->u.f4.fld.dmasr.tbus = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TBUS"); + state->u.f4.fld.dmasr.tjts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TJTS"); + state->u.f4.fld.dmasr.ros = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "ROS"); + state->u.f4.fld.dmasr.tus = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TUS"); + state->u.f4.fld.dmasr.rs = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RS"); + state->u.f4.fld.dmasr.rbus = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RBUS"); + state->u.f4.fld.dmasr.rpss = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RPSS"); + state->u.f4.fld.dmasr.pwts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "PWTS"); + state->u.f4.fld.dmasr.ets = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "ETS"); + state->u.f4.fld.dmasr.fbes = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "FBES"); + state->u.f4.fld.dmasr.ers = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "ERS"); + state->u.f4.fld.dmasr.ais = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "AIS"); + state->u.f4.fld.dmasr.nis = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "NIS"); + state->u.f4.fld.dmasr.rps = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "RPS"); + state->u.f4.fld.dmasr.tps = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TPS"); + state->u.f4.fld.dmasr.ebs = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "EBS"); + state->u.f4.fld.dmasr.mmcs = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "MMCS"); + state->u.f4.fld.dmasr.pmts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "PMTS"); + state->u.f4.fld.dmasr.tsts = cm_object_get_child_by_name(state->u.f4.reg.dmasr, "TSTS"); + + // DMAOMR bitfields. + state->u.f4.fld.dmaomr.sr = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "SR"); + state->u.f4.fld.dmaomr.osf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "OSF"); + state->u.f4.fld.dmaomr.rtc = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "RTC"); + state->u.f4.fld.dmaomr.fugf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "FUGF"); + state->u.f4.fld.dmaomr.fef = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "FEF"); + state->u.f4.fld.dmaomr.st = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "ST"); + state->u.f4.fld.dmaomr.ttc = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "TTC"); + state->u.f4.fld.dmaomr.ftf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "FTF"); + state->u.f4.fld.dmaomr.tsf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "TSF"); + state->u.f4.fld.dmaomr.dfrf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "DFRF"); + state->u.f4.fld.dmaomr.rsf = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "RSF"); + state->u.f4.fld.dmaomr.dtcefd = cm_object_get_child_by_name(state->u.f4.reg.dmaomr, "DTCEFD"); + + // DMAIER bitfields. + state->u.f4.fld.dmaier.tie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TIE"); + state->u.f4.fld.dmaier.tpsie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TPSIE"); + state->u.f4.fld.dmaier.tbuie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TBUIE"); + state->u.f4.fld.dmaier.tjtie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TJTIE"); + state->u.f4.fld.dmaier.roie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "ROIE"); + state->u.f4.fld.dmaier.tuie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "TUIE"); + state->u.f4.fld.dmaier.rie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RIE"); + state->u.f4.fld.dmaier.rbuie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RBUIE"); + state->u.f4.fld.dmaier.rpsie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RPSIE"); + state->u.f4.fld.dmaier.rwtie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "RWTIE"); + state->u.f4.fld.dmaier.etie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "ETIE"); + state->u.f4.fld.dmaier.fbeie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "FBEIE"); + state->u.f4.fld.dmaier.erie = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "ERIE"); + state->u.f4.fld.dmaier.aise = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "AISE"); + state->u.f4.fld.dmaier.nise = cm_object_get_child_by_name(state->u.f4.reg.dmaier, "NISE"); + + // DMAMFBOCR bitfields. + state->u.f4.fld.dmamfbocr.mfc = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "MFC"); + state->u.f4.fld.dmamfbocr.omfc = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "OMFC"); + state->u.f4.fld.dmamfbocr.mfa = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "MFA"); + state->u.f4.fld.dmamfbocr.ofoc = cm_object_get_child_by_name(state->u.f4.reg.dmamfbocr, "OFOC"); + + // DMARSWTR bitfields. + state->u.f4.fld.dmarswtr.rswtc = cm_object_get_child_by_name(state->u.f4.reg.dmarswtr, "RSWTC"); + + // DMACHTDR bitfields. + state->u.f4.fld.dmachtdr.htdap = cm_object_get_child_by_name(state->u.f4.reg.dmachtdr, "HTDAP"); + + // DMACHRDR bitfields. + state->u.f4.fld.dmachrdr.hrdap = cm_object_get_child_by_name(state->u.f4.reg.dmachrdr, "HRDAP"); + + // DMACHTBAR bitfields. + state->u.f4.fld.dmachtbar.htbap = cm_object_get_child_by_name(state->u.f4.reg.dmachtbar, "HTBAP"); + + // DMACHRBAR bitfields. + state->u.f4.fld.dmachrbar.hrbap = cm_object_get_child_by_name(state->u.f4.reg.dmachrbar, "HRBAP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_dma_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_dma_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_dma_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_dma_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_dma_is_enabled(Object *obj) +{ + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_dma_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_dma_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_DMA)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_DMAState *state = STM32_Ethernet_DMA_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_DMA"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_ethernet_dma_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_dma_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_DMAEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_dma_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_DMA); +} + +static void stm32_ethernet_dma_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_dma_reset_callback; + dc->realize = stm32_ethernet_dma_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_dma_is_enabled; +} + +static const TypeInfo stm32_ethernet_dma_type_info = { + .name = TYPE_STM32_Ethernet_DMA, + .parent = TYPE_STM32_Ethernet_DMA_PARENT, + .instance_init = stm32_ethernet_dma_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_DMAState), + .class_init = stm32_ethernet_dma_class_init_callback, + .class_size = sizeof(STM32Ethernet_DMAClass) }; + +static void stm32_ethernet_dma_register_types(void) +{ + type_register_static(&stm32_ethernet_dma_type_info); +} + +type_init(stm32_ethernet_dma_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_dma.h b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_dma.h new file mode 100644 index 0000000000..51d3403ed8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_dma.h @@ -0,0 +1,242 @@ +/* + * STM32 - Ethernet_DMA (Ethernet: DMA controller operation) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_DMA_H_ +#define STM32_Ethernet_DMA_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_DMA DEVICE_PATH_STM32 "Ethernet_DMA" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_DMA TYPE_STM32_PREFIX "ethernet_dma" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_DMA_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_DMAParentClass; +typedef PeripheralState STM32Ethernet_DMAParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_DMA_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_DMAClass, (obj), TYPE_STM32_Ethernet_DMA) +#define STM32_Ethernet_DMA_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_DMAClass, (klass), TYPE_STM32_Ethernet_DMA) + +typedef struct { + // private: + STM32Ethernet_DMAParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_DMAClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_DMA_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_DMAState, (obj), TYPE_STM32_Ethernet_DMA) + +typedef struct { + // private: + STM32Ethernet_DMAParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_DMA (Ethernet: DMA controller operation) registers. + struct { + Object *dmabmr; // 0x0 (Ethernet DMA bus mode register) + Object *dmatpdr; // 0x4 (Ethernet DMA transmit poll demand register) + Object *dmarpdr; // 0x8 (EHERNET DMA receive poll demand register) + Object *dmardlar; // 0xC (Ethernet DMA receive descriptor list address register) + Object *dmatdlar; // 0x10 (Ethernet DMA transmit descriptor list address register) + Object *dmasr; // 0x14 (Ethernet DMA status register) + Object *dmaomr; // 0x18 (Ethernet DMA operation mode register) + Object *dmaier; // 0x1C (Ethernet DMA interrupt enable register) + Object *dmamfbocr; // 0x20 (Ethernet DMA missed frame and buffer overflow counter register) + Object *dmarswtr; // 0x24 (Ethernet DMA receive status watchdog timer register) + Object *dmachtdr; // 0x48 (Ethernet DMA current host transmit descriptor register) + Object *dmachrdr; // 0x4C (Ethernet DMA current host receive descriptor register) + Object *dmachtbar; // 0x50 (Ethernet DMA current host transmit buffer address register) + Object *dmachrbar; // 0x54 (Ethernet DMA current host receive buffer address register) + } reg; + + struct { + + // DMABMR (Ethernet DMA bus mode register) bitfields. + struct { + Object *sr; // [0:0] No description available + Object *da; // [1:1] No description available + Object *dsl; // [2:6] No description available + Object *edfe; // [7:7] No description available + Object *pbl; // [8:13] No description available + Object *rtpr; // [14:15] No description available + Object *fb; // [16:16] No description available + Object *rdp; // [17:22] No description available + Object *usp; // [23:23] No description available + Object *fpm; // [24:24] No description available + Object *aab; // [25:25] No description available + Object *mb; // [26:26] No description available + } dmabmr; + + // DMATPDR (Ethernet DMA transmit poll demand register) bitfields. + struct { + Object *tpd; // [0:31] No description available + } dmatpdr; + + // DMARPDR (EHERNET DMA receive poll demand register) bitfields. + struct { + Object *rpd; // [0:31] RPD + } dmarpdr; + + // DMARDLAR (Ethernet DMA receive descriptor list address register) bitfields. + struct { + Object *srl; // [0:31] No description available + } dmardlar; + + // DMATDLAR (Ethernet DMA transmit descriptor list address register) bitfields. + struct { + Object *stl; // [0:31] No description available + } dmatdlar; + + // DMASR (Ethernet DMA status register) bitfields. + struct { + Object *ts; // [0:0] No description available + Object *tpss; // [1:1] No description available + Object *tbus; // [2:2] No description available + Object *tjts; // [3:3] No description available + Object *ros; // [4:4] No description available + Object *tus; // [5:5] No description available + Object *rs; // [6:6] No description available + Object *rbus; // [7:7] No description available + Object *rpss; // [8:8] No description available + Object *pwts; // [9:9] No description available + Object *ets; // [10:10] No description available + Object *fbes; // [13:13] No description available + Object *ers; // [14:14] No description available + Object *ais; // [15:15] No description available + Object *nis; // [16:16] No description available + Object *rps; // [17:19] No description available + Object *tps; // [20:22] No description available + Object *ebs; // [23:25] No description available + Object *mmcs; // [27:27] No description available + Object *pmts; // [28:28] No description available + Object *tsts; // [29:29] No description available + } dmasr; + + // DMAOMR (Ethernet DMA operation mode register) bitfields. + struct { + Object *sr; // [1:1] SR + Object *osf; // [2:2] OSF + Object *rtc; // [3:4] RTC + Object *fugf; // [6:6] FUGF + Object *fef; // [7:7] FEF + Object *st; // [13:13] ST + Object *ttc; // [14:16] TTC + Object *ftf; // [20:20] FTF + Object *tsf; // [21:21] TSF + Object *dfrf; // [24:24] DFRF + Object *rsf; // [25:25] RSF + Object *dtcefd; // [26:26] DTCEFD + } dmaomr; + + // DMAIER (Ethernet DMA interrupt enable register) bitfields. + struct { + Object *tie; // [0:0] No description available + Object *tpsie; // [1:1] No description available + Object *tbuie; // [2:2] No description available + Object *tjtie; // [3:3] No description available + Object *roie; // [4:4] No description available + Object *tuie; // [5:5] No description available + Object *rie; // [6:6] No description available + Object *rbuie; // [7:7] No description available + Object *rpsie; // [8:8] No description available + Object *rwtie; // [9:9] No description available + Object *etie; // [10:10] No description available + Object *fbeie; // [13:13] No description available + Object *erie; // [14:14] No description available + Object *aise; // [15:15] No description available + Object *nise; // [16:16] No description available + } dmaier; + + // DMAMFBOCR (Ethernet DMA missed frame and buffer overflow counter register) bitfields. + struct { + Object *mfc; // [0:15] No description available + Object *omfc; // [16:16] No description available + Object *mfa; // [17:27] No description available + Object *ofoc; // [28:28] No description available + } dmamfbocr; + + // DMARSWTR (Ethernet DMA receive status watchdog timer register) bitfields. + struct { + Object *rswtc; // [0:7] RSWTC + } dmarswtr; + + // DMACHTDR (Ethernet DMA current host transmit descriptor register) bitfields. + struct { + Object *htdap; // [0:31] HTDAP + } dmachtdr; + + // DMACHRDR (Ethernet DMA current host receive descriptor register) bitfields. + struct { + Object *hrdap; // [0:31] HRDAP + } dmachrdr; + + // DMACHTBAR (Ethernet DMA current host transmit buffer address register) bitfields. + struct { + Object *htbap; // [0:31] No description available + } dmachtbar; + + // DMACHRBAR (Ethernet DMA current host receive buffer address register) bitfields. + struct { + Object *hrbap; // [0:31] No description available + } dmachrbar; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_DMAState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_DMA_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mac.c b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mac.c new file mode 100644 index 0000000000..8385df34c1 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mac.c @@ -0,0 +1,376 @@ +/* + * STM32 - Ethernet_MAC (Ethernet: media access control (MAC)) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_ethernet_mac_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.maccr = cm_object_get_child_by_name(obj, "MACCR"); + state->u.f4.reg.macffr = cm_object_get_child_by_name(obj, "MACFFR"); + state->u.f4.reg.machthr = cm_object_get_child_by_name(obj, "MACHTHR"); + state->u.f4.reg.machtlr = cm_object_get_child_by_name(obj, "MACHTLR"); + state->u.f4.reg.macmiiar = cm_object_get_child_by_name(obj, "MACMIIAR"); + state->u.f4.reg.macmiidr = cm_object_get_child_by_name(obj, "MACMIIDR"); + state->u.f4.reg.macfcr = cm_object_get_child_by_name(obj, "MACFCR"); + state->u.f4.reg.macvlantr = cm_object_get_child_by_name(obj, "MACVLANTR"); + state->u.f4.reg.macpmtcsr = cm_object_get_child_by_name(obj, "MACPMTCSR"); + state->u.f4.reg.macdbgr = cm_object_get_child_by_name(obj, "MACDBGR"); + state->u.f4.reg.macsr = cm_object_get_child_by_name(obj, "MACSR"); + state->u.f4.reg.macimr = cm_object_get_child_by_name(obj, "MACIMR"); + state->u.f4.reg.maca0hr = cm_object_get_child_by_name(obj, "MACA0HR"); + state->u.f4.reg.maca0lr = cm_object_get_child_by_name(obj, "MACA0LR"); + state->u.f4.reg.maca1hr = cm_object_get_child_by_name(obj, "MACA1HR"); + state->u.f4.reg.maca1lr = cm_object_get_child_by_name(obj, "MACA1LR"); + state->u.f4.reg.maca2hr = cm_object_get_child_by_name(obj, "MACA2HR"); + state->u.f4.reg.maca2lr = cm_object_get_child_by_name(obj, "MACA2LR"); + state->u.f4.reg.maca3hr = cm_object_get_child_by_name(obj, "MACA3HR"); + state->u.f4.reg.maca3lr = cm_object_get_child_by_name(obj, "MACA3LR"); + + + // MACCR bitfields. + state->u.f4.fld.maccr.re = cm_object_get_child_by_name(state->u.f4.reg.maccr, "RE"); + state->u.f4.fld.maccr.te = cm_object_get_child_by_name(state->u.f4.reg.maccr, "TE"); + state->u.f4.fld.maccr.dc = cm_object_get_child_by_name(state->u.f4.reg.maccr, "DC"); + state->u.f4.fld.maccr.bl = cm_object_get_child_by_name(state->u.f4.reg.maccr, "BL"); + state->u.f4.fld.maccr.apcs = cm_object_get_child_by_name(state->u.f4.reg.maccr, "APCS"); + state->u.f4.fld.maccr.rd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "RD"); + state->u.f4.fld.maccr.ipco = cm_object_get_child_by_name(state->u.f4.reg.maccr, "IPCO"); + state->u.f4.fld.maccr.dm = cm_object_get_child_by_name(state->u.f4.reg.maccr, "DM"); + state->u.f4.fld.maccr.lm = cm_object_get_child_by_name(state->u.f4.reg.maccr, "LM"); + state->u.f4.fld.maccr.rod = cm_object_get_child_by_name(state->u.f4.reg.maccr, "ROD"); + state->u.f4.fld.maccr.fes = cm_object_get_child_by_name(state->u.f4.reg.maccr, "FES"); + state->u.f4.fld.maccr.csd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "CSD"); + state->u.f4.fld.maccr.ifg = cm_object_get_child_by_name(state->u.f4.reg.maccr, "IFG"); + state->u.f4.fld.maccr.jd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "JD"); + state->u.f4.fld.maccr.wd = cm_object_get_child_by_name(state->u.f4.reg.maccr, "WD"); + state->u.f4.fld.maccr.cstf = cm_object_get_child_by_name(state->u.f4.reg.maccr, "CSTF"); + + // MACFFR bitfields. + state->u.f4.fld.macffr.pm = cm_object_get_child_by_name(state->u.f4.reg.macffr, "PM"); + state->u.f4.fld.macffr.hu = cm_object_get_child_by_name(state->u.f4.reg.macffr, "HU"); + state->u.f4.fld.macffr.hm = cm_object_get_child_by_name(state->u.f4.reg.macffr, "HM"); + state->u.f4.fld.macffr.daif = cm_object_get_child_by_name(state->u.f4.reg.macffr, "DAIF"); + state->u.f4.fld.macffr.ram = cm_object_get_child_by_name(state->u.f4.reg.macffr, "RAM"); + state->u.f4.fld.macffr.bfd = cm_object_get_child_by_name(state->u.f4.reg.macffr, "BFD"); + state->u.f4.fld.macffr.pcf = cm_object_get_child_by_name(state->u.f4.reg.macffr, "PCF"); + state->u.f4.fld.macffr.saif = cm_object_get_child_by_name(state->u.f4.reg.macffr, "SAIF"); + state->u.f4.fld.macffr.saf = cm_object_get_child_by_name(state->u.f4.reg.macffr, "SAF"); + state->u.f4.fld.macffr.hpf = cm_object_get_child_by_name(state->u.f4.reg.macffr, "HPF"); + state->u.f4.fld.macffr.ra = cm_object_get_child_by_name(state->u.f4.reg.macffr, "RA"); + + // MACHTHR bitfields. + state->u.f4.fld.machthr.hth = cm_object_get_child_by_name(state->u.f4.reg.machthr, "HTH"); + + // MACHTLR bitfields. + state->u.f4.fld.machtlr.htl = cm_object_get_child_by_name(state->u.f4.reg.machtlr, "HTL"); + + // MACMIIAR bitfields. + state->u.f4.fld.macmiiar.mb = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "MB"); + state->u.f4.fld.macmiiar.mw = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "MW"); + state->u.f4.fld.macmiiar.cr = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "CR"); + state->u.f4.fld.macmiiar.mr = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "MR"); + state->u.f4.fld.macmiiar.pa = cm_object_get_child_by_name(state->u.f4.reg.macmiiar, "PA"); + + // MACMIIDR bitfields. + state->u.f4.fld.macmiidr.td = cm_object_get_child_by_name(state->u.f4.reg.macmiidr, "TD"); + + // MACFCR bitfields. + state->u.f4.fld.macfcr.fcb = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "FCB"); + state->u.f4.fld.macfcr.tfce = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "TFCE"); + state->u.f4.fld.macfcr.rfce = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "RFCE"); + state->u.f4.fld.macfcr.upfd = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "UPFD"); + state->u.f4.fld.macfcr.plt = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "PLT"); + state->u.f4.fld.macfcr.zqpd = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "ZQPD"); + state->u.f4.fld.macfcr.pt = cm_object_get_child_by_name(state->u.f4.reg.macfcr, "PT"); + + // MACVLANTR bitfields. + state->u.f4.fld.macvlantr.vlanti = cm_object_get_child_by_name(state->u.f4.reg.macvlantr, "VLANTI"); + state->u.f4.fld.macvlantr.vlantc = cm_object_get_child_by_name(state->u.f4.reg.macvlantr, "VLANTC"); + + // MACPMTCSR bitfields. + state->u.f4.fld.macpmtcsr.pd = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "PD"); + state->u.f4.fld.macpmtcsr.mpe = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "MPE"); + state->u.f4.fld.macpmtcsr.wfe = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "WFE"); + state->u.f4.fld.macpmtcsr.mpr = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "MPR"); + state->u.f4.fld.macpmtcsr.wfr = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "WFR"); + state->u.f4.fld.macpmtcsr.gu = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "GU"); + state->u.f4.fld.macpmtcsr.wffrpr = cm_object_get_child_by_name(state->u.f4.reg.macpmtcsr, "WFFRPR"); + + // MACDBGR bitfields. + state->u.f4.fld.macdbgr.cr = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "CR"); + state->u.f4.fld.macdbgr.csr = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "CSR"); + state->u.f4.fld.macdbgr.ror = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "ROR"); + state->u.f4.fld.macdbgr.mcf = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "MCF"); + state->u.f4.fld.macdbgr.mcp = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "MCP"); + state->u.f4.fld.macdbgr.mcfhp = cm_object_get_child_by_name(state->u.f4.reg.macdbgr, "MCFHP"); + + // MACSR bitfields. + state->u.f4.fld.macsr.pmts = cm_object_get_child_by_name(state->u.f4.reg.macsr, "PMTS"); + state->u.f4.fld.macsr.mmcs = cm_object_get_child_by_name(state->u.f4.reg.macsr, "MMCS"); + state->u.f4.fld.macsr.mmcrs = cm_object_get_child_by_name(state->u.f4.reg.macsr, "MMCRS"); + state->u.f4.fld.macsr.mmcts = cm_object_get_child_by_name(state->u.f4.reg.macsr, "MMCTS"); + state->u.f4.fld.macsr.tsts = cm_object_get_child_by_name(state->u.f4.reg.macsr, "TSTS"); + + // MACIMR bitfields. + state->u.f4.fld.macimr.pmtim = cm_object_get_child_by_name(state->u.f4.reg.macimr, "PMTIM"); + state->u.f4.fld.macimr.tstim = cm_object_get_child_by_name(state->u.f4.reg.macimr, "TSTIM"); + + // MACA0HR bitfields. + state->u.f4.fld.maca0hr.maca0h = cm_object_get_child_by_name(state->u.f4.reg.maca0hr, "MACA0H"); + state->u.f4.fld.maca0hr.mo = cm_object_get_child_by_name(state->u.f4.reg.maca0hr, "MO"); + + // MACA0LR bitfields. + state->u.f4.fld.maca0lr.maca0l = cm_object_get_child_by_name(state->u.f4.reg.maca0lr, "MACA0L"); + + // MACA1HR bitfields. + state->u.f4.fld.maca1hr.maca1h = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "MACA1H"); + state->u.f4.fld.maca1hr.mbc = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "MBC"); + state->u.f4.fld.maca1hr.sa = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "SA"); + state->u.f4.fld.maca1hr.ae = cm_object_get_child_by_name(state->u.f4.reg.maca1hr, "AE"); + + // MACA1LR bitfields. + state->u.f4.fld.maca1lr.maca1lr = cm_object_get_child_by_name(state->u.f4.reg.maca1lr, "MACA1LR"); + + // MACA2HR bitfields. + state->u.f4.fld.maca2hr.mac2ah = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "MAC2AH"); + state->u.f4.fld.maca2hr.mbc = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "MBC"); + state->u.f4.fld.maca2hr.sa = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "SA"); + state->u.f4.fld.maca2hr.ae = cm_object_get_child_by_name(state->u.f4.reg.maca2hr, "AE"); + + // MACA2LR bitfields. + state->u.f4.fld.maca2lr.maca2l = cm_object_get_child_by_name(state->u.f4.reg.maca2lr, "MACA2L"); + + // MACA3HR bitfields. + state->u.f4.fld.maca3hr.maca3h = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "MACA3H"); + state->u.f4.fld.maca3hr.mbc = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "MBC"); + state->u.f4.fld.maca3hr.sa = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "SA"); + state->u.f4.fld.maca3hr.ae = cm_object_get_child_by_name(state->u.f4.reg.maca3hr, "AE"); + + // MACA3LR bitfields. + state->u.f4.fld.maca3lr.mbca3l = cm_object_get_child_by_name(state->u.f4.reg.maca3lr, "MBCA3L"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_mac_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_mac_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_mac_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_mac_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_mac_is_enabled(Object *obj) +{ + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_mac_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_mac_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_MAC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_MACState *state = STM32_Ethernet_MAC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_MAC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_ethernet_mac_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_mac_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_MACEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_mac_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_MAC); +} + +static void stm32_ethernet_mac_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_mac_reset_callback; + dc->realize = stm32_ethernet_mac_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_mac_is_enabled; +} + +static const TypeInfo stm32_ethernet_mac_type_info = { + .name = TYPE_STM32_Ethernet_MAC, + .parent = TYPE_STM32_Ethernet_MAC_PARENT, + .instance_init = stm32_ethernet_mac_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_MACState), + .class_init = stm32_ethernet_mac_class_init_callback, + .class_size = sizeof(STM32Ethernet_MACClass) }; + +static void stm32_ethernet_mac_register_types(void) +{ + type_register_static(&stm32_ethernet_mac_type_info); +} + +type_init(stm32_ethernet_mac_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mac.h b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mac.h new file mode 100644 index 0000000000..87220e3fdc --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mac.h @@ -0,0 +1,281 @@ +/* + * STM32 - Ethernet_MAC (Ethernet: media access control (MAC)) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_MAC_H_ +#define STM32_Ethernet_MAC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_MAC DEVICE_PATH_STM32 "Ethernet_MAC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_MAC TYPE_STM32_PREFIX "ethernet_mac" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_MAC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_MACParentClass; +typedef PeripheralState STM32Ethernet_MACParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_MAC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_MACClass, (obj), TYPE_STM32_Ethernet_MAC) +#define STM32_Ethernet_MAC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_MACClass, (klass), TYPE_STM32_Ethernet_MAC) + +typedef struct { + // private: + STM32Ethernet_MACParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_MACClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_MAC_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_MACState, (obj), TYPE_STM32_Ethernet_MAC) + +typedef struct { + // private: + STM32Ethernet_MACParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_MAC (Ethernet: media access control (MAC)) registers. + struct { + Object *maccr; // 0x0 (Ethernet MAC configuration register) + Object *macffr; // 0x4 (Ethernet MAC frame filter register) + Object *machthr; // 0x8 (Ethernet MAC hash table high register) + Object *machtlr; // 0xC (Ethernet MAC hash table low register) + Object *macmiiar; // 0x10 (Ethernet MAC MII address register) + Object *macmiidr; // 0x14 (Ethernet MAC MII data register) + Object *macfcr; // 0x18 (Ethernet MAC flow control register) + Object *macvlantr; // 0x1C (Ethernet MAC VLAN tag register) + Object *macpmtcsr; // 0x2C (Ethernet MAC PMT control and status register) + Object *macdbgr; // 0x34 (Ethernet MAC debug register) + Object *macsr; // 0x38 (Ethernet MAC interrupt status register) + Object *macimr; // 0x3C (Ethernet MAC interrupt mask register) + Object *maca0hr; // 0x40 (Ethernet MAC address 0 high register) + Object *maca0lr; // 0x44 (Ethernet MAC address 0 low register) + Object *maca1hr; // 0x48 (Ethernet MAC address 1 high register) + Object *maca1lr; // 0x4C (Ethernet MAC address1 low register) + Object *maca2hr; // 0x50 (Ethernet MAC address 2 high register) + Object *maca2lr; // 0x54 (Ethernet MAC address 2 low register) + Object *maca3hr; // 0x58 (Ethernet MAC address 3 high register) + Object *maca3lr; // 0x5C (Ethernet MAC address 3 low register) + } reg; + + struct { + + // MACCR (Ethernet MAC configuration register) bitfields. + struct { + Object *re; // [2:2] RE + Object *te; // [3:3] TE + Object *dc; // [4:4] DC + Object *bl; // [5:6] BL + Object *apcs; // [7:7] APCS + Object *rd; // [9:9] RD + Object *ipco; // [10:10] IPCO + Object *dm; // [11:11] DM + Object *lm; // [12:12] LM + Object *rod; // [13:13] ROD + Object *fes; // [14:14] FES + Object *csd; // [16:16] CSD + Object *ifg; // [17:19] IFG + Object *jd; // [22:22] JD + Object *wd; // [23:23] WD + Object *cstf; // [25:25] CSTF + } maccr; + + // MACFFR (Ethernet MAC frame filter register) bitfields. + struct { + Object *pm; // [0:0] No description available + Object *hu; // [1:1] No description available + Object *hm; // [2:2] No description available + Object *daif; // [3:3] No description available + Object *ram; // [4:4] No description available + Object *bfd; // [5:5] No description available + Object *pcf; // [6:6] No description available + Object *saif; // [7:7] No description available + Object *saf; // [8:8] No description available + Object *hpf; // [9:9] No description available + Object *ra; // [31:31] No description available + } macffr; + + // MACHTHR (Ethernet MAC hash table high register) bitfields. + struct { + Object *hth; // [0:31] No description available + } machthr; + + // MACHTLR (Ethernet MAC hash table low register) bitfields. + struct { + Object *htl; // [0:31] No description available + } machtlr; + + // MACMIIAR (Ethernet MAC MII address register) bitfields. + struct { + Object *mb; // [0:0] No description available + Object *mw; // [1:1] No description available + Object *cr; // [2:4] No description available + Object *mr; // [6:10] No description available + Object *pa; // [11:15] No description available + } macmiiar; + + // MACMIIDR (Ethernet MAC MII data register) bitfields. + struct { + Object *td; // [0:15] No description available + } macmiidr; + + // MACFCR (Ethernet MAC flow control register) bitfields. + struct { + Object *fcb; // [0:0] No description available + Object *tfce; // [1:1] No description available + Object *rfce; // [2:2] No description available + Object *upfd; // [3:3] No description available + Object *plt; // [4:5] No description available + Object *zqpd; // [7:7] No description available + Object *pt; // [16:31] No description available + } macfcr; + + // MACVLANTR (Ethernet MAC VLAN tag register) bitfields. + struct { + Object *vlanti; // [0:15] No description available + Object *vlantc; // [16:16] No description available + } macvlantr; + + // MACPMTCSR (Ethernet MAC PMT control and status register) bitfields. + struct { + Object *pd; // [0:0] No description available + Object *mpe; // [1:1] No description available + Object *wfe; // [2:2] No description available + Object *mpr; // [5:5] No description available + Object *wfr; // [6:6] No description available + Object *gu; // [9:9] No description available + Object *wffrpr; // [31:31] No description available + } macpmtcsr; + + // MACDBGR (Ethernet MAC debug register) bitfields. + struct { + Object *cr; // [0:0] CR + Object *csr; // [1:1] CSR + Object *ror; // [2:2] ROR + Object *mcf; // [3:3] MCF + Object *mcp; // [4:4] MCP + Object *mcfhp; // [5:5] MCFHP + } macdbgr; + + // MACSR (Ethernet MAC interrupt status register) bitfields. + struct { + Object *pmts; // [3:3] No description available + Object *mmcs; // [4:4] No description available + Object *mmcrs; // [5:5] No description available + Object *mmcts; // [6:6] No description available + Object *tsts; // [9:9] No description available + } macsr; + + // MACIMR (Ethernet MAC interrupt mask register) bitfields. + struct { + Object *pmtim; // [3:3] No description available + Object *tstim; // [9:9] No description available + } macimr; + + // MACA0HR (Ethernet MAC address 0 high register) bitfields. + struct { + Object *maca0h; // [0:15] MAC address0 high + Object *mo; // [31:31] Always 1 + } maca0hr; + + // MACA0LR (Ethernet MAC address 0 low register) bitfields. + struct { + Object *maca0l; // [0:31] 0 + } maca0lr; + + // MACA1HR (Ethernet MAC address 1 high register) bitfields. + struct { + Object *maca1h; // [0:15] No description available + Object *mbc; // [24:29] No description available + Object *sa; // [30:30] No description available + Object *ae; // [31:31] No description available + } maca1hr; + + // MACA1LR (Ethernet MAC address1 low register) bitfields. + struct { + Object *maca1lr; // [0:31] No description available + } maca1lr; + + // MACA2HR (Ethernet MAC address 2 high register) bitfields. + struct { + Object *mac2ah; // [0:15] No description available + Object *mbc; // [24:29] No description available + Object *sa; // [30:30] No description available + Object *ae; // [31:31] No description available + } maca2hr; + + // MACA2LR (Ethernet MAC address 2 low register) bitfields. + struct { + Object *maca2l; // [0:30] No description available + } maca2lr; + + // MACA3HR (Ethernet MAC address 3 high register) bitfields. + struct { + Object *maca3h; // [0:15] No description available + Object *mbc; // [24:29] No description available + Object *sa; // [30:30] No description available + Object *ae; // [31:31] No description available + } maca3hr; + + // MACA3LR (Ethernet MAC address 3 low register) bitfields. + struct { + Object *mbca3l; // [0:31] No description available + } maca3lr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_MACState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_MAC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mmc.c b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mmc.c new file mode 100644 index 0000000000..dd4ae96f0a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mmc.c @@ -0,0 +1,291 @@ +/* + * STM32 - Ethernet_MMC (Ethernet: MAC management counters) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_ethernet_mmc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.mmccr = cm_object_get_child_by_name(obj, "MMCCR"); + state->u.f4.reg.mmcrir = cm_object_get_child_by_name(obj, "MMCRIR"); + state->u.f4.reg.mmctir = cm_object_get_child_by_name(obj, "MMCTIR"); + state->u.f4.reg.mmcrimr = cm_object_get_child_by_name(obj, "MMCRIMR"); + state->u.f4.reg.mmctimr = cm_object_get_child_by_name(obj, "MMCTIMR"); + state->u.f4.reg.mmctgfsccr = cm_object_get_child_by_name(obj, "MMCTGFSCCR"); + state->u.f4.reg.mmctgfmsccr = cm_object_get_child_by_name(obj, "MMCTGFMSCCR"); + state->u.f4.reg.mmctgfcr = cm_object_get_child_by_name(obj, "MMCTGFCR"); + state->u.f4.reg.mmcrfcecr = cm_object_get_child_by_name(obj, "MMCRFCECR"); + state->u.f4.reg.mmcrfaecr = cm_object_get_child_by_name(obj, "MMCRFAECR"); + state->u.f4.reg.mmcrgufcr = cm_object_get_child_by_name(obj, "MMCRGUFCR"); + + + // MMCCR bitfields. + state->u.f4.fld.mmccr.cr = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "CR"); + state->u.f4.fld.mmccr.csr = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "CSR"); + state->u.f4.fld.mmccr.ror = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "ROR"); + state->u.f4.fld.mmccr.mcf = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "MCF"); + state->u.f4.fld.mmccr.mcp = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "MCP"); + state->u.f4.fld.mmccr.mcfhp = cm_object_get_child_by_name(state->u.f4.reg.mmccr, "MCFHP"); + + // MMCRIR bitfields. + state->u.f4.fld.mmcrir.rfces = cm_object_get_child_by_name(state->u.f4.reg.mmcrir, "RFCES"); + state->u.f4.fld.mmcrir.rfaes = cm_object_get_child_by_name(state->u.f4.reg.mmcrir, "RFAES"); + state->u.f4.fld.mmcrir.rgufs = cm_object_get_child_by_name(state->u.f4.reg.mmcrir, "RGUFS"); + + // MMCTIR bitfields. + state->u.f4.fld.mmctir.tgfscs = cm_object_get_child_by_name(state->u.f4.reg.mmctir, "TGFSCS"); + state->u.f4.fld.mmctir.tgfmscs = cm_object_get_child_by_name(state->u.f4.reg.mmctir, "TGFMSCS"); + state->u.f4.fld.mmctir.tgfs = cm_object_get_child_by_name(state->u.f4.reg.mmctir, "TGFS"); + + // MMCRIMR bitfields. + state->u.f4.fld.mmcrimr.rfcem = cm_object_get_child_by_name(state->u.f4.reg.mmcrimr, "RFCEM"); + state->u.f4.fld.mmcrimr.rfaem = cm_object_get_child_by_name(state->u.f4.reg.mmcrimr, "RFAEM"); + state->u.f4.fld.mmcrimr.rgufm = cm_object_get_child_by_name(state->u.f4.reg.mmcrimr, "RGUFM"); + + // MMCTIMR bitfields. + state->u.f4.fld.mmctimr.tgfscm = cm_object_get_child_by_name(state->u.f4.reg.mmctimr, "TGFSCM"); + state->u.f4.fld.mmctimr.tgfmscm = cm_object_get_child_by_name(state->u.f4.reg.mmctimr, "TGFMSCM"); + state->u.f4.fld.mmctimr.tgfm = cm_object_get_child_by_name(state->u.f4.reg.mmctimr, "TGFM"); + + // MMCTGFSCCR bitfields. + state->u.f4.fld.mmctgfsccr.tgfscc = cm_object_get_child_by_name(state->u.f4.reg.mmctgfsccr, "TGFSCC"); + + // MMCTGFMSCCR bitfields. + state->u.f4.fld.mmctgfmsccr.tgfmscc = cm_object_get_child_by_name(state->u.f4.reg.mmctgfmsccr, "TGFMSCC"); + + // MMCTGFCR bitfields. + state->u.f4.fld.mmctgfcr.tgfc = cm_object_get_child_by_name(state->u.f4.reg.mmctgfcr, "TGFC"); + + // MMCRFCECR bitfields. + state->u.f4.fld.mmcrfcecr.rfcfc = cm_object_get_child_by_name(state->u.f4.reg.mmcrfcecr, "RFCFC"); + + // MMCRFAECR bitfields. + state->u.f4.fld.mmcrfaecr.rfaec = cm_object_get_child_by_name(state->u.f4.reg.mmcrfaecr, "RFAEC"); + + // MMCRGUFCR bitfields. + state->u.f4.fld.mmcrgufcr.rgufc = cm_object_get_child_by_name(state->u.f4.reg.mmcrgufcr, "RGUFC"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_mmc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_mmc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_mmc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_mmc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_mmc_is_enabled(Object *obj) +{ + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_mmc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_mmc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_MMC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_MMCState *state = STM32_Ethernet_MMC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_MMC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_ethernet_mmc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_mmc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_MMCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_mmc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_MMC); +} + +static void stm32_ethernet_mmc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_mmc_reset_callback; + dc->realize = stm32_ethernet_mmc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_mmc_is_enabled; +} + +static const TypeInfo stm32_ethernet_mmc_type_info = { + .name = TYPE_STM32_Ethernet_MMC, + .parent = TYPE_STM32_Ethernet_MMC_PARENT, + .instance_init = stm32_ethernet_mmc_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_MMCState), + .class_init = stm32_ethernet_mmc_class_init_callback, + .class_size = sizeof(STM32Ethernet_MMCClass) }; + +static void stm32_ethernet_mmc_register_types(void) +{ + type_register_static(&stm32_ethernet_mmc_type_info); +} + +type_init(stm32_ethernet_mmc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mmc.h b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mmc.h new file mode 100644 index 0000000000..cf85a7daf5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_mmc.h @@ -0,0 +1,178 @@ +/* + * STM32 - Ethernet_MMC (Ethernet: MAC management counters) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_MMC_H_ +#define STM32_Ethernet_MMC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_MMC DEVICE_PATH_STM32 "Ethernet_MMC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_MMC TYPE_STM32_PREFIX "ethernet_mmc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_MMC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_MMCParentClass; +typedef PeripheralState STM32Ethernet_MMCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_MMC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_MMCClass, (obj), TYPE_STM32_Ethernet_MMC) +#define STM32_Ethernet_MMC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_MMCClass, (klass), TYPE_STM32_Ethernet_MMC) + +typedef struct { + // private: + STM32Ethernet_MMCParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_MMCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_MMC_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_MMCState, (obj), TYPE_STM32_Ethernet_MMC) + +typedef struct { + // private: + STM32Ethernet_MMCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_MMC (Ethernet: MAC management counters) registers. + struct { + Object *mmccr; // 0x0 (Ethernet MMC control register) + Object *mmcrir; // 0x4 (Ethernet MMC receive interrupt register) + Object *mmctir; // 0x8 (Ethernet MMC transmit interrupt register) + Object *mmcrimr; // 0xC (Ethernet MMC receive interrupt mask register) + Object *mmctimr; // 0x10 (Ethernet MMC transmit interrupt mask register) + Object *mmctgfsccr; // 0x4C (Ethernet MMC transmitted good frames after a single collision counter) + Object *mmctgfmsccr; // 0x50 (Ethernet MMC transmitted good frames after more than a single collision) + Object *mmctgfcr; // 0x68 (Ethernet MMC transmitted good frames counter register) + Object *mmcrfcecr; // 0x94 (Ethernet MMC received frames with CRC error counter register) + Object *mmcrfaecr; // 0x98 (Ethernet MMC received frames with alignment error counter register) + Object *mmcrgufcr; // 0xC4 (MMC received good unicast frames counter register) + } reg; + + struct { + + // MMCCR (Ethernet MMC control register) bitfields. + struct { + Object *cr; // [0:0] No description available + Object *csr; // [1:1] No description available + Object *ror; // [2:2] No description available + Object *mcf; // [3:3] No description available + Object *mcp; // [4:4] No description available + Object *mcfhp; // [5:5] No description available + } mmccr; + + // MMCRIR (Ethernet MMC receive interrupt register) bitfields. + struct { + Object *rfces; // [5:5] No description available + Object *rfaes; // [6:6] No description available + Object *rgufs; // [17:17] No description available + } mmcrir; + + // MMCTIR (Ethernet MMC transmit interrupt register) bitfields. + struct { + Object *tgfscs; // [14:14] No description available + Object *tgfmscs; // [15:15] No description available + Object *tgfs; // [21:21] No description available + } mmctir; + + // MMCRIMR (Ethernet MMC receive interrupt mask register) bitfields. + struct { + Object *rfcem; // [5:5] No description available + Object *rfaem; // [6:6] No description available + Object *rgufm; // [17:17] No description available + } mmcrimr; + + // MMCTIMR (Ethernet MMC transmit interrupt mask register) bitfields. + struct { + Object *tgfscm; // [14:14] No description available + Object *tgfmscm; // [15:15] No description available + Object *tgfm; // [16:16] No description available + } mmctimr; + + // MMCTGFSCCR (Ethernet MMC transmitted good frames after a single collision counter) bitfields. + struct { + Object *tgfscc; // [0:31] No description available + } mmctgfsccr; + + // MMCTGFMSCCR (Ethernet MMC transmitted good frames after more than a single collision) bitfields. + struct { + Object *tgfmscc; // [0:31] No description available + } mmctgfmsccr; + + // MMCTGFCR (Ethernet MMC transmitted good frames counter register) bitfields. + struct { + Object *tgfc; // [0:31] HTL + } mmctgfcr; + + // MMCRFCECR (Ethernet MMC received frames with CRC error counter register) bitfields. + struct { + Object *rfcfc; // [0:31] No description available + } mmcrfcecr; + + // MMCRFAECR (Ethernet MMC received frames with alignment error counter register) bitfields. + struct { + Object *rfaec; // [0:31] No description available + } mmcrfaecr; + + // MMCRGUFCR (MMC received good unicast frames counter register) bitfields. + struct { + Object *rgufc; // [0:31] No description available + } mmcrgufcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_MMCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_MMC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_ptp.c b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_ptp.c new file mode 100644 index 0000000000..ff0d2019a7 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_ptp.c @@ -0,0 +1,297 @@ +/* + * STM32 - Ethernet_PTP (Ethernet: Precision time protocol) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_ethernet_ptp_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.ptptscr = cm_object_get_child_by_name(obj, "PTPTSCR"); + state->u.f4.reg.ptpssir = cm_object_get_child_by_name(obj, "PTPSSIR"); + state->u.f4.reg.ptptshr = cm_object_get_child_by_name(obj, "PTPTSHR"); + state->u.f4.reg.ptptslr = cm_object_get_child_by_name(obj, "PTPTSLR"); + state->u.f4.reg.ptptshur = cm_object_get_child_by_name(obj, "PTPTSHUR"); + state->u.f4.reg.ptptslur = cm_object_get_child_by_name(obj, "PTPTSLUR"); + state->u.f4.reg.ptptsar = cm_object_get_child_by_name(obj, "PTPTSAR"); + state->u.f4.reg.ptptthr = cm_object_get_child_by_name(obj, "PTPTTHR"); + state->u.f4.reg.ptpttlr = cm_object_get_child_by_name(obj, "PTPTTLR"); + state->u.f4.reg.ptptssr = cm_object_get_child_by_name(obj, "PTPTSSR"); + state->u.f4.reg.ptpppscr = cm_object_get_child_by_name(obj, "PTPPPSCR"); + + + // PTPTSCR bitfields. + state->u.f4.fld.ptptscr.tse = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSE"); + state->u.f4.fld.ptptscr.tsfcu = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSFCU"); + state->u.f4.fld.ptptscr.tssti = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSTI"); + state->u.f4.fld.ptptscr.tsstu = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSTU"); + state->u.f4.fld.ptptscr.tsite = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSITE"); + state->u.f4.fld.ptptscr.ttsaru = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TTSARU"); + state->u.f4.fld.ptptscr.tssarfe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSARFE"); + state->u.f4.fld.ptptscr.tsssr = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSSR"); + state->u.f4.fld.ptptscr.tsptppsv2e = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSPTPPSV2E"); + state->u.f4.fld.ptptscr.tssptpoefe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSPTPOEFE"); + state->u.f4.fld.ptptscr.tssipv6fe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSIPV6FE"); + state->u.f4.fld.ptptscr.tssipv4fe = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSIPV4FE"); + state->u.f4.fld.ptptscr.tsseme = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSEME"); + state->u.f4.fld.ptptscr.tssmrme = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSSMRME"); + state->u.f4.fld.ptptscr.tscnt = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSCNT"); + state->u.f4.fld.ptptscr.tspffmae = cm_object_get_child_by_name(state->u.f4.reg.ptptscr, "TSPFFMAE"); + + // PTPSSIR bitfields. + state->u.f4.fld.ptpssir.stssi = cm_object_get_child_by_name(state->u.f4.reg.ptpssir, "STSSI"); + + // PTPTSHR bitfields. + state->u.f4.fld.ptptshr.sts = cm_object_get_child_by_name(state->u.f4.reg.ptptshr, "STS"); + + // PTPTSLR bitfields. + state->u.f4.fld.ptptslr.stss = cm_object_get_child_by_name(state->u.f4.reg.ptptslr, "STSS"); + state->u.f4.fld.ptptslr.stpns = cm_object_get_child_by_name(state->u.f4.reg.ptptslr, "STPNS"); + + // PTPTSHUR bitfields. + state->u.f4.fld.ptptshur.tsus = cm_object_get_child_by_name(state->u.f4.reg.ptptshur, "TSUS"); + + // PTPTSLUR bitfields. + state->u.f4.fld.ptptslur.tsuss = cm_object_get_child_by_name(state->u.f4.reg.ptptslur, "TSUSS"); + state->u.f4.fld.ptptslur.tsupns = cm_object_get_child_by_name(state->u.f4.reg.ptptslur, "TSUPNS"); + + // PTPTSAR bitfields. + state->u.f4.fld.ptptsar.tsa = cm_object_get_child_by_name(state->u.f4.reg.ptptsar, "TSA"); + + // PTPTTHR bitfields. + state->u.f4.fld.ptptthr.ttsh = cm_object_get_child_by_name(state->u.f4.reg.ptptthr, "TTSH"); + + // PTPTTLR bitfields. + state->u.f4.fld.ptpttlr.ttsl = cm_object_get_child_by_name(state->u.f4.reg.ptpttlr, "TTSL"); + + // PTPTSSR bitfields. + state->u.f4.fld.ptptssr.tsso = cm_object_get_child_by_name(state->u.f4.reg.ptptssr, "TSSO"); + state->u.f4.fld.ptptssr.tsttr = cm_object_get_child_by_name(state->u.f4.reg.ptptssr, "TSTTR"); + + // PTPPPSCR bitfields. + state->u.f4.fld.ptpppscr.tsso = cm_object_get_child_by_name(state->u.f4.reg.ptpppscr, "TSSO"); + state->u.f4.fld.ptpppscr.tsttr = cm_object_get_child_by_name(state->u.f4.reg.ptpppscr, "TSTTR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ethernet_ptp_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ethernet_ptp_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ethernet_ptp_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ethernet_ptp_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ethernet_ptp_is_enabled(Object *obj) +{ + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ethernet_ptp_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ethernet_ptp_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_Ethernet_PTP)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32Ethernet_PTPState *state = STM32_Ethernet_PTP_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "Ethernet_PTP"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_ethernet_ptp_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ethernet_ptp_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/Ethernet_PTPEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ethernet_ptp_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_Ethernet_PTP); +} + +static void stm32_ethernet_ptp_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ethernet_ptp_reset_callback; + dc->realize = stm32_ethernet_ptp_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ethernet_ptp_is_enabled; +} + +static const TypeInfo stm32_ethernet_ptp_type_info = { + .name = TYPE_STM32_Ethernet_PTP, + .parent = TYPE_STM32_Ethernet_PTP_PARENT, + .instance_init = stm32_ethernet_ptp_instance_init_callback, + .instance_size = sizeof(STM32Ethernet_PTPState), + .class_init = stm32_ethernet_ptp_class_init_callback, + .class_size = sizeof(STM32Ethernet_PTPClass) }; + +static void stm32_ethernet_ptp_register_types(void) +{ + type_register_static(&stm32_ethernet_ptp_type_info); +} + +type_init(stm32_ethernet_ptp_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_ptp.h b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_ptp.h new file mode 100644 index 0000000000..ae192297f5 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ethernet_ptp.h @@ -0,0 +1,184 @@ +/* + * STM32 - Ethernet_PTP (Ethernet: Precision time protocol) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_Ethernet_PTP_H_ +#define STM32_Ethernet_PTP_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_Ethernet_PTP DEVICE_PATH_STM32 "Ethernet_PTP" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_Ethernet_PTP TYPE_STM32_PREFIX "ethernet_ptp" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_Ethernet_PTP_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32Ethernet_PTPParentClass; +typedef PeripheralState STM32Ethernet_PTPParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_Ethernet_PTP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32Ethernet_PTPClass, (obj), TYPE_STM32_Ethernet_PTP) +#define STM32_Ethernet_PTP_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32Ethernet_PTPClass, (klass), TYPE_STM32_Ethernet_PTP) + +typedef struct { + // private: + STM32Ethernet_PTPParentClass parent_class; + // public: + + // None, so far. +} STM32Ethernet_PTPClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_Ethernet_PTP_STATE(obj) \ + OBJECT_CHECK(STM32Ethernet_PTPState, (obj), TYPE_STM32_Ethernet_PTP) + +typedef struct { + // private: + STM32Ethernet_PTPParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 Ethernet_PTP (Ethernet: Precision time protocol) registers. + struct { + Object *ptptscr; // 0x0 (Ethernet PTP time stamp control register) + Object *ptpssir; // 0x4 (Ethernet PTP subsecond increment register) + Object *ptptshr; // 0x8 (Ethernet PTP time stamp high register) + Object *ptptslr; // 0xC (Ethernet PTP time stamp low register) + Object *ptptshur; // 0x10 (Ethernet PTP time stamp high update register) + Object *ptptslur; // 0x14 (Ethernet PTP time stamp low update register) + Object *ptptsar; // 0x18 (Ethernet PTP time stamp addend register) + Object *ptptthr; // 0x1C (Ethernet PTP target time high register) + Object *ptpttlr; // 0x20 (Ethernet PTP target time low register) + Object *ptptssr; // 0x28 (Ethernet PTP time stamp status register) + Object *ptpppscr; // 0x2C (Ethernet PTP PPS control register) + } reg; + + struct { + + // PTPTSCR (Ethernet PTP time stamp control register) bitfields. + struct { + Object *tse; // [0:0] No description available + Object *tsfcu; // [1:1] No description available + Object *tssti; // [2:2] No description available + Object *tsstu; // [3:3] No description available + Object *tsite; // [4:4] No description available + Object *ttsaru; // [5:5] No description available + Object *tssarfe; // [8:8] No description available + Object *tsssr; // [9:9] No description available + Object *tsptppsv2e; // [10:10] No description available + Object *tssptpoefe; // [11:11] No description available + Object *tssipv6fe; // [12:12] No description available + Object *tssipv4fe; // [13:13] No description available + Object *tsseme; // [14:14] No description available + Object *tssmrme; // [15:15] No description available + Object *tscnt; // [16:17] No description available + Object *tspffmae; // [18:18] No description available + } ptptscr; + + // PTPSSIR (Ethernet PTP subsecond increment register) bitfields. + struct { + Object *stssi; // [0:7] No description available + } ptpssir; + + // PTPTSHR (Ethernet PTP time stamp high register) bitfields. + struct { + Object *sts; // [0:31] No description available + } ptptshr; + + // PTPTSLR (Ethernet PTP time stamp low register) bitfields. + struct { + Object *stss; // [0:30] No description available + Object *stpns; // [31:31] No description available + } ptptslr; + + // PTPTSHUR (Ethernet PTP time stamp high update register) bitfields. + struct { + Object *tsus; // [0:31] No description available + } ptptshur; + + // PTPTSLUR (Ethernet PTP time stamp low update register) bitfields. + struct { + Object *tsuss; // [0:30] No description available + Object *tsupns; // [31:31] No description available + } ptptslur; + + // PTPTSAR (Ethernet PTP time stamp addend register) bitfields. + struct { + Object *tsa; // [0:31] No description available + } ptptsar; + + // PTPTTHR (Ethernet PTP target time high register) bitfields. + struct { + Object *ttsh; // [0:31] 0 + } ptptthr; + + // PTPTTLR (Ethernet PTP target time low register) bitfields. + struct { + Object *ttsl; // [0:31] No description available + } ptpttlr; + + // PTPTSSR (Ethernet PTP time stamp status register) bitfields. + struct { + Object *tsso; // [0:0] No description available + Object *tsttr; // [1:1] No description available + } ptptssr; + + // PTPPPSCR (Ethernet PTP PPS control register) bitfields. + struct { + Object *tsso; // [0:0] TSSO + Object *tsttr; // [1:1] TSTTR + } ptpppscr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32Ethernet_PTPState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_Ethernet_PTP_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/exti.c b/gnu-mcu-eclipse/devices/support/STM32F429x/exti.c new file mode 100644 index 0000000000..784a0aae0d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/exti.c @@ -0,0 +1,390 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_exti_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.imr = cm_object_get_child_by_name(obj, "IMR"); + state->u.f4.reg.emr = cm_object_get_child_by_name(obj, "EMR"); + state->u.f4.reg.rtsr = cm_object_get_child_by_name(obj, "RTSR"); + state->u.f4.reg.ftsr = cm_object_get_child_by_name(obj, "FTSR"); + state->u.f4.reg.swier = cm_object_get_child_by_name(obj, "SWIER"); + state->u.f4.reg.pr = cm_object_get_child_by_name(obj, "PR"); + + + // IMR bitfields. + state->u.f4.fld.imr.mr0 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR0"); + state->u.f4.fld.imr.mr1 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR1"); + state->u.f4.fld.imr.mr2 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR2"); + state->u.f4.fld.imr.mr3 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR3"); + state->u.f4.fld.imr.mr4 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR4"); + state->u.f4.fld.imr.mr5 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR5"); + state->u.f4.fld.imr.mr6 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR6"); + state->u.f4.fld.imr.mr7 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR7"); + state->u.f4.fld.imr.mr8 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR8"); + state->u.f4.fld.imr.mr9 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR9"); + state->u.f4.fld.imr.mr10 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR10"); + state->u.f4.fld.imr.mr11 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR11"); + state->u.f4.fld.imr.mr12 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR12"); + state->u.f4.fld.imr.mr13 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR13"); + state->u.f4.fld.imr.mr14 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR14"); + state->u.f4.fld.imr.mr15 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR15"); + state->u.f4.fld.imr.mr16 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR16"); + state->u.f4.fld.imr.mr17 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR17"); + state->u.f4.fld.imr.mr18 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR18"); + state->u.f4.fld.imr.mr19 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR19"); + state->u.f4.fld.imr.mr20 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR20"); + state->u.f4.fld.imr.mr21 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR21"); + state->u.f4.fld.imr.mr22 = cm_object_get_child_by_name(state->u.f4.reg.imr, "MR22"); + + // EMR bitfields. + state->u.f4.fld.emr.mr0 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR0"); + state->u.f4.fld.emr.mr1 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR1"); + state->u.f4.fld.emr.mr2 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR2"); + state->u.f4.fld.emr.mr3 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR3"); + state->u.f4.fld.emr.mr4 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR4"); + state->u.f4.fld.emr.mr5 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR5"); + state->u.f4.fld.emr.mr6 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR6"); + state->u.f4.fld.emr.mr7 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR7"); + state->u.f4.fld.emr.mr8 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR8"); + state->u.f4.fld.emr.mr9 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR9"); + state->u.f4.fld.emr.mr10 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR10"); + state->u.f4.fld.emr.mr11 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR11"); + state->u.f4.fld.emr.mr12 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR12"); + state->u.f4.fld.emr.mr13 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR13"); + state->u.f4.fld.emr.mr14 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR14"); + state->u.f4.fld.emr.mr15 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR15"); + state->u.f4.fld.emr.mr16 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR16"); + state->u.f4.fld.emr.mr17 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR17"); + state->u.f4.fld.emr.mr18 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR18"); + state->u.f4.fld.emr.mr19 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR19"); + state->u.f4.fld.emr.mr20 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR20"); + state->u.f4.fld.emr.mr21 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR21"); + state->u.f4.fld.emr.mr22 = cm_object_get_child_by_name(state->u.f4.reg.emr, "MR22"); + + // RTSR bitfields. + state->u.f4.fld.rtsr.tr0 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR0"); + state->u.f4.fld.rtsr.tr1 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR1"); + state->u.f4.fld.rtsr.tr2 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR2"); + state->u.f4.fld.rtsr.tr3 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR3"); + state->u.f4.fld.rtsr.tr4 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR4"); + state->u.f4.fld.rtsr.tr5 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR5"); + state->u.f4.fld.rtsr.tr6 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR6"); + state->u.f4.fld.rtsr.tr7 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR7"); + state->u.f4.fld.rtsr.tr8 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR8"); + state->u.f4.fld.rtsr.tr9 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR9"); + state->u.f4.fld.rtsr.tr10 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR10"); + state->u.f4.fld.rtsr.tr11 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR11"); + state->u.f4.fld.rtsr.tr12 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR12"); + state->u.f4.fld.rtsr.tr13 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR13"); + state->u.f4.fld.rtsr.tr14 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR14"); + state->u.f4.fld.rtsr.tr15 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR15"); + state->u.f4.fld.rtsr.tr16 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR16"); + state->u.f4.fld.rtsr.tr17 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR17"); + state->u.f4.fld.rtsr.tr18 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR18"); + state->u.f4.fld.rtsr.tr19 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR19"); + state->u.f4.fld.rtsr.tr20 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR20"); + state->u.f4.fld.rtsr.tr21 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR21"); + state->u.f4.fld.rtsr.tr22 = cm_object_get_child_by_name(state->u.f4.reg.rtsr, "TR22"); + + // FTSR bitfields. + state->u.f4.fld.ftsr.tr0 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR0"); + state->u.f4.fld.ftsr.tr1 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR1"); + state->u.f4.fld.ftsr.tr2 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR2"); + state->u.f4.fld.ftsr.tr3 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR3"); + state->u.f4.fld.ftsr.tr4 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR4"); + state->u.f4.fld.ftsr.tr5 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR5"); + state->u.f4.fld.ftsr.tr6 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR6"); + state->u.f4.fld.ftsr.tr7 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR7"); + state->u.f4.fld.ftsr.tr8 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR8"); + state->u.f4.fld.ftsr.tr9 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR9"); + state->u.f4.fld.ftsr.tr10 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR10"); + state->u.f4.fld.ftsr.tr11 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR11"); + state->u.f4.fld.ftsr.tr12 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR12"); + state->u.f4.fld.ftsr.tr13 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR13"); + state->u.f4.fld.ftsr.tr14 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR14"); + state->u.f4.fld.ftsr.tr15 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR15"); + state->u.f4.fld.ftsr.tr16 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR16"); + state->u.f4.fld.ftsr.tr17 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR17"); + state->u.f4.fld.ftsr.tr18 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR18"); + state->u.f4.fld.ftsr.tr19 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR19"); + state->u.f4.fld.ftsr.tr20 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR20"); + state->u.f4.fld.ftsr.tr21 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR21"); + state->u.f4.fld.ftsr.tr22 = cm_object_get_child_by_name(state->u.f4.reg.ftsr, "TR22"); + + // SWIER bitfields. + state->u.f4.fld.swier.swier0 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER0"); + state->u.f4.fld.swier.swier1 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER1"); + state->u.f4.fld.swier.swier2 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER2"); + state->u.f4.fld.swier.swier3 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER3"); + state->u.f4.fld.swier.swier4 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER4"); + state->u.f4.fld.swier.swier5 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER5"); + state->u.f4.fld.swier.swier6 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER6"); + state->u.f4.fld.swier.swier7 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER7"); + state->u.f4.fld.swier.swier8 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER8"); + state->u.f4.fld.swier.swier9 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER9"); + state->u.f4.fld.swier.swier10 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER10"); + state->u.f4.fld.swier.swier11 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER11"); + state->u.f4.fld.swier.swier12 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER12"); + state->u.f4.fld.swier.swier13 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER13"); + state->u.f4.fld.swier.swier14 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER14"); + state->u.f4.fld.swier.swier15 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER15"); + state->u.f4.fld.swier.swier16 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER16"); + state->u.f4.fld.swier.swier17 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER17"); + state->u.f4.fld.swier.swier18 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER18"); + state->u.f4.fld.swier.swier19 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER19"); + state->u.f4.fld.swier.swier20 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER20"); + state->u.f4.fld.swier.swier21 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER21"); + state->u.f4.fld.swier.swier22 = cm_object_get_child_by_name(state->u.f4.reg.swier, "SWIER22"); + + // PR bitfields. + state->u.f4.fld.pr.pr0 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR0"); + state->u.f4.fld.pr.pr1 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR1"); + state->u.f4.fld.pr.pr2 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR2"); + state->u.f4.fld.pr.pr3 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR3"); + state->u.f4.fld.pr.pr4 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR4"); + state->u.f4.fld.pr.pr5 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR5"); + state->u.f4.fld.pr.pr6 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR6"); + state->u.f4.fld.pr.pr7 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR7"); + state->u.f4.fld.pr.pr8 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR8"); + state->u.f4.fld.pr.pr9 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR9"); + state->u.f4.fld.pr.pr10 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR10"); + state->u.f4.fld.pr.pr11 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR11"); + state->u.f4.fld.pr.pr12 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR12"); + state->u.f4.fld.pr.pr13 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR13"); + state->u.f4.fld.pr.pr14 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR14"); + state->u.f4.fld.pr.pr15 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR15"); + state->u.f4.fld.pr.pr16 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR16"); + state->u.f4.fld.pr.pr17 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR17"); + state->u.f4.fld.pr.pr18 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR18"); + state->u.f4.fld.pr.pr19 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR19"); + state->u.f4.fld.pr.pr20 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR20"); + state->u.f4.fld.pr.pr21 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR21"); + state->u.f4.fld.pr.pr22 = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR22"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_exti_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_exti_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_exti_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_exti_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32EXTIState *state = STM32_EXTI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_exti_is_enabled(Object *obj) +{ + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_exti_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32EXTIState *state = STM32_EXTI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_exti_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_EXTI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32EXTIState *state = STM32_EXTI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "EXTI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_exti_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_exti_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_exti_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_exti_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_exti_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/EXTIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_exti_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_EXTI); +} + +static void stm32_exti_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_exti_reset_callback; + dc->realize = stm32_exti_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_exti_is_enabled; +} + +static const TypeInfo stm32_exti_type_info = { + .name = TYPE_STM32_EXTI, + .parent = TYPE_STM32_EXTI_PARENT, + .instance_init = stm32_exti_instance_init_callback, + .instance_size = sizeof(STM32EXTIState), + .class_init = stm32_exti_class_init_callback, + .class_size = sizeof(STM32EXTIClass) }; + +static void stm32_exti_register_types(void) +{ + type_register_static(&stm32_exti_type_info); +} + +type_init(stm32_exti_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/exti.h b/gnu-mcu-eclipse/devices/support/STM32F429x/exti.h new file mode 100644 index 0000000000..c60df55b50 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/exti.h @@ -0,0 +1,267 @@ +/* + * STM32 - EXTI (External interrupt/event controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_EXTI_H_ +#define STM32_EXTI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_EXTI DEVICE_PATH_STM32 "EXTI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_EXTI TYPE_STM32_PREFIX "exti" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_EXTI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32EXTIParentClass; +typedef PeripheralState STM32EXTIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_EXTI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32EXTIClass, (obj), TYPE_STM32_EXTI) +#define STM32_EXTI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32EXTIClass, (klass), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentClass parent_class; + // public: + + // None, so far. +} STM32EXTIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_EXTI_STATE(obj) \ + OBJECT_CHECK(STM32EXTIState, (obj), TYPE_STM32_EXTI) + +typedef struct { + // private: + STM32EXTIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 EXTI (External interrupt/event controller) registers. + struct { + Object *imr; // 0x0 (Interrupt mask register (EXTI_IMR)) + Object *emr; // 0x4 (Event mask register (EXTI_EMR)) + Object *rtsr; // 0x8 (Rising Trigger selection register (EXTI_RTSR)) + Object *ftsr; // 0xC (Falling Trigger selection register (EXTI_FTSR)) + Object *swier; // 0x10 (Software interrupt event register (EXTI_SWIER)) + Object *pr; // 0x14 (Pending register (EXTI_PR)) + } reg; + + struct { + + // IMR (Interrupt mask register (EXTI_IMR)) bitfields. + struct { + Object *mr0; // [0:0] Interrupt Mask on line 0 + Object *mr1; // [1:1] Interrupt Mask on line 1 + Object *mr2; // [2:2] Interrupt Mask on line 2 + Object *mr3; // [3:3] Interrupt Mask on line 3 + Object *mr4; // [4:4] Interrupt Mask on line 4 + Object *mr5; // [5:5] Interrupt Mask on line 5 + Object *mr6; // [6:6] Interrupt Mask on line 6 + Object *mr7; // [7:7] Interrupt Mask on line 7 + Object *mr8; // [8:8] Interrupt Mask on line 8 + Object *mr9; // [9:9] Interrupt Mask on line 9 + Object *mr10; // [10:10] Interrupt Mask on line 10 + Object *mr11; // [11:11] Interrupt Mask on line 11 + Object *mr12; // [12:12] Interrupt Mask on line 12 + Object *mr13; // [13:13] Interrupt Mask on line 13 + Object *mr14; // [14:14] Interrupt Mask on line 14 + Object *mr15; // [15:15] Interrupt Mask on line 15 + Object *mr16; // [16:16] Interrupt Mask on line 16 + Object *mr17; // [17:17] Interrupt Mask on line 17 + Object *mr18; // [18:18] Interrupt Mask on line 18 + Object *mr19; // [19:19] Interrupt Mask on line 19 + Object *mr20; // [20:20] Interrupt Mask on line 20 + Object *mr21; // [21:21] Interrupt Mask on line 21 + Object *mr22; // [22:22] Interrupt Mask on line 22 + } imr; + + // EMR (Event mask register (EXTI_EMR)) bitfields. + struct { + Object *mr0; // [0:0] Event Mask on line 0 + Object *mr1; // [1:1] Event Mask on line 1 + Object *mr2; // [2:2] Event Mask on line 2 + Object *mr3; // [3:3] Event Mask on line 3 + Object *mr4; // [4:4] Event Mask on line 4 + Object *mr5; // [5:5] Event Mask on line 5 + Object *mr6; // [6:6] Event Mask on line 6 + Object *mr7; // [7:7] Event Mask on line 7 + Object *mr8; // [8:8] Event Mask on line 8 + Object *mr9; // [9:9] Event Mask on line 9 + Object *mr10; // [10:10] Event Mask on line 10 + Object *mr11; // [11:11] Event Mask on line 11 + Object *mr12; // [12:12] Event Mask on line 12 + Object *mr13; // [13:13] Event Mask on line 13 + Object *mr14; // [14:14] Event Mask on line 14 + Object *mr15; // [15:15] Event Mask on line 15 + Object *mr16; // [16:16] Event Mask on line 16 + Object *mr17; // [17:17] Event Mask on line 17 + Object *mr18; // [18:18] Event Mask on line 18 + Object *mr19; // [19:19] Event Mask on line 19 + Object *mr20; // [20:20] Event Mask on line 20 + Object *mr21; // [21:21] Event Mask on line 21 + Object *mr22; // [22:22] Event Mask on line 22 + } emr; + + // RTSR (Rising Trigger selection register (EXTI_RTSR)) bitfields. + struct { + Object *tr0; // [0:0] Rising trigger event configuration of line 0 + Object *tr1; // [1:1] Rising trigger event configuration of line 1 + Object *tr2; // [2:2] Rising trigger event configuration of line 2 + Object *tr3; // [3:3] Rising trigger event configuration of line 3 + Object *tr4; // [4:4] Rising trigger event configuration of line 4 + Object *tr5; // [5:5] Rising trigger event configuration of line 5 + Object *tr6; // [6:6] Rising trigger event configuration of line 6 + Object *tr7; // [7:7] Rising trigger event configuration of line 7 + Object *tr8; // [8:8] Rising trigger event configuration of line 8 + Object *tr9; // [9:9] Rising trigger event configuration of line 9 + Object *tr10; // [10:10] Rising trigger event configuration of line 10 + Object *tr11; // [11:11] Rising trigger event configuration of line 11 + Object *tr12; // [12:12] Rising trigger event configuration of line 12 + Object *tr13; // [13:13] Rising trigger event configuration of line 13 + Object *tr14; // [14:14] Rising trigger event configuration of line 14 + Object *tr15; // [15:15] Rising trigger event configuration of line 15 + Object *tr16; // [16:16] Rising trigger event configuration of line 16 + Object *tr17; // [17:17] Rising trigger event configuration of line 17 + Object *tr18; // [18:18] Rising trigger event configuration of line 18 + Object *tr19; // [19:19] Rising trigger event configuration of line 19 + Object *tr20; // [20:20] Rising trigger event configuration of line 20 + Object *tr21; // [21:21] Rising trigger event configuration of line 21 + Object *tr22; // [22:22] Rising trigger event configuration of line 22 + } rtsr; + + // FTSR (Falling Trigger selection register (EXTI_FTSR)) bitfields. + struct { + Object *tr0; // [0:0] Falling trigger event configuration of line 0 + Object *tr1; // [1:1] Falling trigger event configuration of line 1 + Object *tr2; // [2:2] Falling trigger event configuration of line 2 + Object *tr3; // [3:3] Falling trigger event configuration of line 3 + Object *tr4; // [4:4] Falling trigger event configuration of line 4 + Object *tr5; // [5:5] Falling trigger event configuration of line 5 + Object *tr6; // [6:6] Falling trigger event configuration of line 6 + Object *tr7; // [7:7] Falling trigger event configuration of line 7 + Object *tr8; // [8:8] Falling trigger event configuration of line 8 + Object *tr9; // [9:9] Falling trigger event configuration of line 9 + Object *tr10; // [10:10] Falling trigger event configuration of line 10 + Object *tr11; // [11:11] Falling trigger event configuration of line 11 + Object *tr12; // [12:12] Falling trigger event configuration of line 12 + Object *tr13; // [13:13] Falling trigger event configuration of line 13 + Object *tr14; // [14:14] Falling trigger event configuration of line 14 + Object *tr15; // [15:15] Falling trigger event configuration of line 15 + Object *tr16; // [16:16] Falling trigger event configuration of line 16 + Object *tr17; // [17:17] Falling trigger event configuration of line 17 + Object *tr18; // [18:18] Falling trigger event configuration of line 18 + Object *tr19; // [19:19] Falling trigger event configuration of line 19 + Object *tr20; // [20:20] Falling trigger event configuration of line 20 + Object *tr21; // [21:21] Falling trigger event configuration of line 21 + Object *tr22; // [22:22] Falling trigger event configuration of line 22 + } ftsr; + + // SWIER (Software interrupt event register (EXTI_SWIER)) bitfields. + struct { + Object *swier0; // [0:0] Software Interrupt on line 0 + Object *swier1; // [1:1] Software Interrupt on line 1 + Object *swier2; // [2:2] Software Interrupt on line 2 + Object *swier3; // [3:3] Software Interrupt on line 3 + Object *swier4; // [4:4] Software Interrupt on line 4 + Object *swier5; // [5:5] Software Interrupt on line 5 + Object *swier6; // [6:6] Software Interrupt on line 6 + Object *swier7; // [7:7] Software Interrupt on line 7 + Object *swier8; // [8:8] Software Interrupt on line 8 + Object *swier9; // [9:9] Software Interrupt on line 9 + Object *swier10; // [10:10] Software Interrupt on line 10 + Object *swier11; // [11:11] Software Interrupt on line 11 + Object *swier12; // [12:12] Software Interrupt on line 12 + Object *swier13; // [13:13] Software Interrupt on line 13 + Object *swier14; // [14:14] Software Interrupt on line 14 + Object *swier15; // [15:15] Software Interrupt on line 15 + Object *swier16; // [16:16] Software Interrupt on line 16 + Object *swier17; // [17:17] Software Interrupt on line 17 + Object *swier18; // [18:18] Software Interrupt on line 18 + Object *swier19; // [19:19] Software Interrupt on line 19 + Object *swier20; // [20:20] Software Interrupt on line 20 + Object *swier21; // [21:21] Software Interrupt on line 21 + Object *swier22; // [22:22] Software Interrupt on line 22 + } swier; + + // PR (Pending register (EXTI_PR)) bitfields. + struct { + Object *pr0; // [0:0] Pending bit 0 + Object *pr1; // [1:1] Pending bit 1 + Object *pr2; // [2:2] Pending bit 2 + Object *pr3; // [3:3] Pending bit 3 + Object *pr4; // [4:4] Pending bit 4 + Object *pr5; // [5:5] Pending bit 5 + Object *pr6; // [6:6] Pending bit 6 + Object *pr7; // [7:7] Pending bit 7 + Object *pr8; // [8:8] Pending bit 8 + Object *pr9; // [9:9] Pending bit 9 + Object *pr10; // [10:10] Pending bit 10 + Object *pr11; // [11:11] Pending bit 11 + Object *pr12; // [12:12] Pending bit 12 + Object *pr13; // [13:13] Pending bit 13 + Object *pr14; // [14:14] Pending bit 14 + Object *pr15; // [15:15] Pending bit 15 + Object *pr16; // [16:16] Pending bit 16 + Object *pr17; // [17:17] Pending bit 17 + Object *pr18; // [18:18] Pending bit 18 + Object *pr19; // [19:19] Pending bit 19 + Object *pr20; // [20:20] Pending bit 20 + Object *pr21; // [21:21] Pending bit 21 + Object *pr22; // [22:22] Pending bit 22 + } pr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32EXTIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_EXTI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/flash.c b/gnu-mcu-eclipse/devices/support/STM32F429x/flash.c new file mode 100644 index 0000000000..47e5fdfd8e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/flash.c @@ -0,0 +1,289 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_flash_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.acr = cm_object_get_child_by_name(obj, "ACR"); + state->u.f4.reg.keyr = cm_object_get_child_by_name(obj, "KEYR"); + state->u.f4.reg.optkeyr = cm_object_get_child_by_name(obj, "OPTKEYR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.optcr = cm_object_get_child_by_name(obj, "OPTCR"); + state->u.f4.reg.optcr1 = cm_object_get_child_by_name(obj, "OPTCR1"); + + + // ACR bitfields. + state->u.f4.fld.acr.latency = cm_object_get_child_by_name(state->u.f4.reg.acr, "LATENCY"); + state->u.f4.fld.acr.prften = cm_object_get_child_by_name(state->u.f4.reg.acr, "PRFTEN"); + state->u.f4.fld.acr.icen = cm_object_get_child_by_name(state->u.f4.reg.acr, "ICEN"); + state->u.f4.fld.acr.dcen = cm_object_get_child_by_name(state->u.f4.reg.acr, "DCEN"); + state->u.f4.fld.acr.icrst = cm_object_get_child_by_name(state->u.f4.reg.acr, "ICRST"); + state->u.f4.fld.acr.dcrst = cm_object_get_child_by_name(state->u.f4.reg.acr, "DCRST"); + + // KEYR bitfields. + state->u.f4.fld.keyr.key = cm_object_get_child_by_name(state->u.f4.reg.keyr, "KEY"); + + // OPTKEYR bitfields. + state->u.f4.fld.optkeyr.optkey = cm_object_get_child_by_name(state->u.f4.reg.optkeyr, "OPTKEY"); + + // SR bitfields. + state->u.f4.fld.sr.eop = cm_object_get_child_by_name(state->u.f4.reg.sr, "EOP"); + state->u.f4.fld.sr.operr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OPERR"); + state->u.f4.fld.sr.wrperr = cm_object_get_child_by_name(state->u.f4.reg.sr, "WRPERR"); + state->u.f4.fld.sr.pgaerr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGAERR"); + state->u.f4.fld.sr.pgperr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGPERR"); + state->u.f4.fld.sr.pgserr = cm_object_get_child_by_name(state->u.f4.reg.sr, "PGSERR"); + state->u.f4.fld.sr.bsy = cm_object_get_child_by_name(state->u.f4.reg.sr, "BSY"); + + // CR bitfields. + state->u.f4.fld.cr.pg = cm_object_get_child_by_name(state->u.f4.reg.cr, "PG"); + state->u.f4.fld.cr.ser = cm_object_get_child_by_name(state->u.f4.reg.cr, "SER"); + state->u.f4.fld.cr.mer = cm_object_get_child_by_name(state->u.f4.reg.cr, "MER"); + state->u.f4.fld.cr.snb = cm_object_get_child_by_name(state->u.f4.reg.cr, "SNB"); + state->u.f4.fld.cr.psize = cm_object_get_child_by_name(state->u.f4.reg.cr, "PSIZE"); + state->u.f4.fld.cr.mer1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "MER1"); + state->u.f4.fld.cr.strt = cm_object_get_child_by_name(state->u.f4.reg.cr, "STRT"); + state->u.f4.fld.cr.eopie = cm_object_get_child_by_name(state->u.f4.reg.cr, "EOPIE"); + state->u.f4.fld.cr.errie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ERRIE"); + state->u.f4.fld.cr.lock = cm_object_get_child_by_name(state->u.f4.reg.cr, "LOCK"); + + // OPTCR bitfields. + state->u.f4.fld.optcr.optlock = cm_object_get_child_by_name(state->u.f4.reg.optcr, "OPTLOCK"); + state->u.f4.fld.optcr.optstrt = cm_object_get_child_by_name(state->u.f4.reg.optcr, "OPTSTRT"); + state->u.f4.fld.optcr.bor_lev = cm_object_get_child_by_name(state->u.f4.reg.optcr, "BOR_LEV"); + state->u.f4.fld.optcr.wdg_sw = cm_object_get_child_by_name(state->u.f4.reg.optcr, "WDG_SW"); + state->u.f4.fld.optcr.nrst_stop = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nRST_STOP"); + state->u.f4.fld.optcr.nrst_stdby = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nRST_STDBY"); + state->u.f4.fld.optcr.rdp = cm_object_get_child_by_name(state->u.f4.reg.optcr, "RDP"); + state->u.f4.fld.optcr.nwrp = cm_object_get_child_by_name(state->u.f4.reg.optcr, "nWRP"); + + // OPTCR1 bitfields. + state->u.f4.fld.optcr1.nwrp = cm_object_get_child_by_name(state->u.f4.reg.optcr1, "nWRP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_flash_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_flash_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_flash_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_flash_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FLASHState *state = STM32_FLASH_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_flash_is_enabled(Object *obj) +{ + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_flash_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FLASHState *state = STM32_FLASH_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_flash_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FLASH)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FLASHState *state = STM32_FLASH_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FLASH"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_flash_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_flash_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_flash_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_flash_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_flash_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FLASHEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_flash_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FLASH); +} + +static void stm32_flash_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_flash_reset_callback; + dc->realize = stm32_flash_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_flash_is_enabled; +} + +static const TypeInfo stm32_flash_type_info = { + .name = TYPE_STM32_FLASH, + .parent = TYPE_STM32_FLASH_PARENT, + .instance_init = stm32_flash_instance_init_callback, + .instance_size = sizeof(STM32FLASHState), + .class_init = stm32_flash_class_init_callback, + .class_size = sizeof(STM32FLASHClass) }; + +static void stm32_flash_register_types(void) +{ + type_register_static(&stm32_flash_type_info); +} + +type_init(stm32_flash_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/flash.h b/gnu-mcu-eclipse/devices/support/STM32F429x/flash.h new file mode 100644 index 0000000000..9269263c97 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/flash.h @@ -0,0 +1,168 @@ +/* + * STM32 - FLASH (FLASH) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FLASH_H_ +#define STM32_FLASH_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FLASH DEVICE_PATH_STM32 "FLASH" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FLASH TYPE_STM32_PREFIX "flash" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FLASH_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FLASHParentClass; +typedef PeripheralState STM32FLASHParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FLASH_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FLASHClass, (obj), TYPE_STM32_FLASH) +#define STM32_FLASH_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FLASHClass, (klass), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentClass parent_class; + // public: + + // None, so far. +} STM32FLASHClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FLASH_STATE(obj) \ + OBJECT_CHECK(STM32FLASHState, (obj), TYPE_STM32_FLASH) + +typedef struct { + // private: + STM32FLASHParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 FLASH (FLASH) registers. + struct { + Object *acr; // 0x0 (Flash access control register) + Object *keyr; // 0x4 (Flash key register) + Object *optkeyr; // 0x8 (Flash option key register) + Object *sr; // 0xC (Status register) + Object *cr; // 0x10 (Control register) + Object *optcr; // 0x14 (Flash option control register) + Object *optcr1; // 0x18 (Flash option control register 1) + } reg; + + struct { + + // ACR (Flash access control register) bitfields. + struct { + Object *latency; // [0:2] Latency + Object *prften; // [8:8] Prefetch enable + Object *icen; // [9:9] Instruction cache enable + Object *dcen; // [10:10] Data cache enable + Object *icrst; // [11:11] Instruction cache reset + Object *dcrst; // [12:12] Data cache reset + } acr; + + // KEYR (Flash key register) bitfields. + struct { + Object *key; // [0:31] FPEC key + } keyr; + + // OPTKEYR (Flash option key register) bitfields. + struct { + Object *optkey; // [0:31] Option byte key + } optkeyr; + + // SR (Status register) bitfields. + struct { + Object *eop; // [0:0] End of operation + Object *operr; // [1:1] Operation error + Object *wrperr; // [4:4] Write protection error + Object *pgaerr; // [5:5] Programming alignment error + Object *pgperr; // [6:6] Programming parallelism error + Object *pgserr; // [7:7] Programming sequence error + Object *bsy; // [16:16] Busy + } sr; + + // CR (Control register) bitfields. + struct { + Object *pg; // [0:0] Programming + Object *ser; // [1:1] Sector Erase + Object *mer; // [2:2] Mass Erase of sectors 0 to 11 + Object *snb; // [3:7] Sector number + Object *psize; // [8:9] Program size + Object *mer1; // [15:15] Mass Erase of sectors 12 to 23 + Object *strt; // [16:16] Start + Object *eopie; // [24:24] End of operation interrupt enable + Object *errie; // [25:25] Error interrupt enable + Object *lock; // [31:31] Lock + } cr; + + // OPTCR (Flash option control register) bitfields. + struct { + Object *optlock; // [0:0] Option lock + Object *optstrt; // [1:1] Option start + Object *bor_lev; // [2:3] BOR reset Level + Object *wdg_sw; // [5:5] WDG_SW User option bytes + Object *nrst_stop; // [6:6] NRST_STOP User option bytes + Object *nrst_stdby; // [7:7] NRST_STDBY User option bytes + Object *rdp; // [8:15] Read protect + Object *nwrp; // [16:27] Not write protect + } optcr; + + // OPTCR1 (Flash option control register 1) bitfields. + struct { + Object *nwrp; // [16:27] Not write protect + } optcr1; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FLASHState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FLASH_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/fmc.c b/gnu-mcu-eclipse/devices/support/STM32F429x/fmc.c new file mode 100644 index 0000000000..a8f6ecd39c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/fmc.c @@ -0,0 +1,563 @@ +/* + * STM32 - FMC (Flexible memory controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_fmc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32FMCState *state = STM32_FMC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.bcr1 = cm_object_get_child_by_name(obj, "BCR1"); + state->u.f4.reg.btr1 = cm_object_get_child_by_name(obj, "BTR1"); + state->u.f4.reg.bcr2 = cm_object_get_child_by_name(obj, "BCR2"); + state->u.f4.reg.btr2 = cm_object_get_child_by_name(obj, "BTR2"); + state->u.f4.reg.bcr3 = cm_object_get_child_by_name(obj, "BCR3"); + state->u.f4.reg.btr3 = cm_object_get_child_by_name(obj, "BTR3"); + state->u.f4.reg.bcr4 = cm_object_get_child_by_name(obj, "BCR4"); + state->u.f4.reg.btr4 = cm_object_get_child_by_name(obj, "BTR4"); + state->u.f4.reg.pcr2 = cm_object_get_child_by_name(obj, "PCR2"); + state->u.f4.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f4.reg.pmem2 = cm_object_get_child_by_name(obj, "PMEM2"); + state->u.f4.reg.patt2 = cm_object_get_child_by_name(obj, "PATT2"); + state->u.f4.reg.eccr2 = cm_object_get_child_by_name(obj, "ECCR2"); + state->u.f4.reg.pcr3 = cm_object_get_child_by_name(obj, "PCR3"); + state->u.f4.reg.sr3 = cm_object_get_child_by_name(obj, "SR3"); + state->u.f4.reg.pmem3 = cm_object_get_child_by_name(obj, "PMEM3"); + state->u.f4.reg.patt3 = cm_object_get_child_by_name(obj, "PATT3"); + state->u.f4.reg.eccr3 = cm_object_get_child_by_name(obj, "ECCR3"); + state->u.f4.reg.pcr4 = cm_object_get_child_by_name(obj, "PCR4"); + state->u.f4.reg.sr4 = cm_object_get_child_by_name(obj, "SR4"); + state->u.f4.reg.pmem4 = cm_object_get_child_by_name(obj, "PMEM4"); + state->u.f4.reg.patt4 = cm_object_get_child_by_name(obj, "PATT4"); + state->u.f4.reg.pio4 = cm_object_get_child_by_name(obj, "PIO4"); + state->u.f4.reg.bwtr1 = cm_object_get_child_by_name(obj, "BWTR1"); + state->u.f4.reg.bwtr2 = cm_object_get_child_by_name(obj, "BWTR2"); + state->u.f4.reg.bwtr3 = cm_object_get_child_by_name(obj, "BWTR3"); + state->u.f4.reg.bwtr4 = cm_object_get_child_by_name(obj, "BWTR4"); + state->u.f4.reg.sdcr1 = cm_object_get_child_by_name(obj, "SDCR1"); + state->u.f4.reg.sdcr2 = cm_object_get_child_by_name(obj, "SDCR2"); + state->u.f4.reg.sdtr1 = cm_object_get_child_by_name(obj, "SDTR1"); + state->u.f4.reg.sdtr2 = cm_object_get_child_by_name(obj, "SDTR2"); + state->u.f4.reg.sdcmr = cm_object_get_child_by_name(obj, "SDCMR"); + state->u.f4.reg.sdrtr = cm_object_get_child_by_name(obj, "SDRTR"); + state->u.f4.reg.sdsr = cm_object_get_child_by_name(obj, "SDSR"); + + + // BCR1 bitfields. + state->u.f4.fld.bcr1.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MBKEN"); + state->u.f4.fld.bcr1.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MUXEN"); + state->u.f4.fld.bcr1.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MTYP"); + state->u.f4.fld.bcr1.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MWID"); + state->u.f4.fld.bcr1.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "FACCEN"); + state->u.f4.fld.bcr1.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "BURSTEN"); + state->u.f4.fld.bcr1.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WAITPOL"); + state->u.f4.fld.bcr1.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WAITCFG"); + state->u.f4.fld.bcr1.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WREN"); + state->u.f4.fld.bcr1.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "WAITEN"); + state->u.f4.fld.bcr1.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "EXTMOD"); + state->u.f4.fld.bcr1.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "ASYNCWAIT"); + state->u.f4.fld.bcr1.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "CBURSTRW"); + state->u.f4.fld.bcr1.cclken = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "CCLKEN"); + + // BTR1 bitfields. + state->u.f4.fld.btr1.addset = cm_object_get_child_by_name(state->u.f4.reg.btr1, "ADDSET"); + state->u.f4.fld.btr1.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr1, "ADDHLD"); + state->u.f4.fld.btr1.datast = cm_object_get_child_by_name(state->u.f4.reg.btr1, "DATAST"); + state->u.f4.fld.btr1.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr1, "BUSTURN"); + state->u.f4.fld.btr1.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr1, "CLKDIV"); + state->u.f4.fld.btr1.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr1, "DATLAT"); + state->u.f4.fld.btr1.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr1, "ACCMOD"); + + // BCR2 bitfields. + state->u.f4.fld.bcr2.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MBKEN"); + state->u.f4.fld.bcr2.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MUXEN"); + state->u.f4.fld.bcr2.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MTYP"); + state->u.f4.fld.bcr2.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MWID"); + state->u.f4.fld.bcr2.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "FACCEN"); + state->u.f4.fld.bcr2.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "BURSTEN"); + state->u.f4.fld.bcr2.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WAITPOL"); + state->u.f4.fld.bcr2.wrapmod = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WRAPMOD"); + state->u.f4.fld.bcr2.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WAITCFG"); + state->u.f4.fld.bcr2.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WREN"); + state->u.f4.fld.bcr2.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "WAITEN"); + state->u.f4.fld.bcr2.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "EXTMOD"); + state->u.f4.fld.bcr2.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "ASYNCWAIT"); + state->u.f4.fld.bcr2.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "CBURSTRW"); + + // BTR2 bitfields. + state->u.f4.fld.btr2.addset = cm_object_get_child_by_name(state->u.f4.reg.btr2, "ADDSET"); + state->u.f4.fld.btr2.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr2, "ADDHLD"); + state->u.f4.fld.btr2.datast = cm_object_get_child_by_name(state->u.f4.reg.btr2, "DATAST"); + state->u.f4.fld.btr2.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr2, "BUSTURN"); + state->u.f4.fld.btr2.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr2, "CLKDIV"); + state->u.f4.fld.btr2.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr2, "DATLAT"); + state->u.f4.fld.btr2.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr2, "ACCMOD"); + + // BCR3 bitfields. + state->u.f4.fld.bcr3.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MBKEN"); + state->u.f4.fld.bcr3.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MUXEN"); + state->u.f4.fld.bcr3.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MTYP"); + state->u.f4.fld.bcr3.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "MWID"); + state->u.f4.fld.bcr3.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "FACCEN"); + state->u.f4.fld.bcr3.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "BURSTEN"); + state->u.f4.fld.bcr3.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WAITPOL"); + state->u.f4.fld.bcr3.wrapmod = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WRAPMOD"); + state->u.f4.fld.bcr3.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WAITCFG"); + state->u.f4.fld.bcr3.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WREN"); + state->u.f4.fld.bcr3.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "WAITEN"); + state->u.f4.fld.bcr3.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "EXTMOD"); + state->u.f4.fld.bcr3.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "ASYNCWAIT"); + state->u.f4.fld.bcr3.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr3, "CBURSTRW"); + + // BTR3 bitfields. + state->u.f4.fld.btr3.addset = cm_object_get_child_by_name(state->u.f4.reg.btr3, "ADDSET"); + state->u.f4.fld.btr3.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr3, "ADDHLD"); + state->u.f4.fld.btr3.datast = cm_object_get_child_by_name(state->u.f4.reg.btr3, "DATAST"); + state->u.f4.fld.btr3.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr3, "BUSTURN"); + state->u.f4.fld.btr3.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr3, "CLKDIV"); + state->u.f4.fld.btr3.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr3, "DATLAT"); + state->u.f4.fld.btr3.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr3, "ACCMOD"); + + // BCR4 bitfields. + state->u.f4.fld.bcr4.mbken = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MBKEN"); + state->u.f4.fld.bcr4.muxen = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MUXEN"); + state->u.f4.fld.bcr4.mtyp = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MTYP"); + state->u.f4.fld.bcr4.mwid = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "MWID"); + state->u.f4.fld.bcr4.faccen = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "FACCEN"); + state->u.f4.fld.bcr4.bursten = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "BURSTEN"); + state->u.f4.fld.bcr4.waitpol = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WAITPOL"); + state->u.f4.fld.bcr4.wrapmod = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WRAPMOD"); + state->u.f4.fld.bcr4.waitcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WAITCFG"); + state->u.f4.fld.bcr4.wren = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WREN"); + state->u.f4.fld.bcr4.waiten = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "WAITEN"); + state->u.f4.fld.bcr4.extmod = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "EXTMOD"); + state->u.f4.fld.bcr4.asyncwait = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "ASYNCWAIT"); + state->u.f4.fld.bcr4.cburstrw = cm_object_get_child_by_name(state->u.f4.reg.bcr4, "CBURSTRW"); + + // BTR4 bitfields. + state->u.f4.fld.btr4.addset = cm_object_get_child_by_name(state->u.f4.reg.btr4, "ADDSET"); + state->u.f4.fld.btr4.addhld = cm_object_get_child_by_name(state->u.f4.reg.btr4, "ADDHLD"); + state->u.f4.fld.btr4.datast = cm_object_get_child_by_name(state->u.f4.reg.btr4, "DATAST"); + state->u.f4.fld.btr4.busturn = cm_object_get_child_by_name(state->u.f4.reg.btr4, "BUSTURN"); + state->u.f4.fld.btr4.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.btr4, "CLKDIV"); + state->u.f4.fld.btr4.datlat = cm_object_get_child_by_name(state->u.f4.reg.btr4, "DATLAT"); + state->u.f4.fld.btr4.accmod = cm_object_get_child_by_name(state->u.f4.reg.btr4, "ACCMOD"); + + // PCR2 bitfields. + state->u.f4.fld.pcr2.pwaiten = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PWAITEN"); + state->u.f4.fld.pcr2.pbken = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PBKEN"); + state->u.f4.fld.pcr2.ptyp = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PTYP"); + state->u.f4.fld.pcr2.pwid = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "PWID"); + state->u.f4.fld.pcr2.eccen = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "ECCEN"); + state->u.f4.fld.pcr2.tclr = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "TCLR"); + state->u.f4.fld.pcr2.tar = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "TAR"); + state->u.f4.fld.pcr2.eccps = cm_object_get_child_by_name(state->u.f4.reg.pcr2, "ECCPS"); + + // SR2 bitfields. + state->u.f4.fld.sr2.irs = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IRS"); + state->u.f4.fld.sr2.ils = cm_object_get_child_by_name(state->u.f4.reg.sr2, "ILS"); + state->u.f4.fld.sr2.ifs = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IFS"); + state->u.f4.fld.sr2.iren = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IREN"); + state->u.f4.fld.sr2.ilen = cm_object_get_child_by_name(state->u.f4.reg.sr2, "ILEN"); + state->u.f4.fld.sr2.ifen = cm_object_get_child_by_name(state->u.f4.reg.sr2, "IFEN"); + state->u.f4.fld.sr2.fempt = cm_object_get_child_by_name(state->u.f4.reg.sr2, "FEMPT"); + + // PMEM2 bitfields. + state->u.f4.fld.pmem2.memsetx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMSETx"); + state->u.f4.fld.pmem2.memwaitx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMWAITx"); + state->u.f4.fld.pmem2.memholdx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMHOLDx"); + state->u.f4.fld.pmem2.memhizx = cm_object_get_child_by_name(state->u.f4.reg.pmem2, "MEMHIZx"); + + // PATT2 bitfields. + state->u.f4.fld.patt2.attsetx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTSETx"); + state->u.f4.fld.patt2.attwaitx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTWAITx"); + state->u.f4.fld.patt2.attholdx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTHOLDx"); + state->u.f4.fld.patt2.atthizx = cm_object_get_child_by_name(state->u.f4.reg.patt2, "ATTHIZx"); + + // ECCR2 bitfields. + state->u.f4.fld.eccr2.eccx = cm_object_get_child_by_name(state->u.f4.reg.eccr2, "ECCx"); + + // PCR3 bitfields. + state->u.f4.fld.pcr3.pwaiten = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PWAITEN"); + state->u.f4.fld.pcr3.pbken = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PBKEN"); + state->u.f4.fld.pcr3.ptyp = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PTYP"); + state->u.f4.fld.pcr3.pwid = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "PWID"); + state->u.f4.fld.pcr3.eccen = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "ECCEN"); + state->u.f4.fld.pcr3.tclr = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "TCLR"); + state->u.f4.fld.pcr3.tar = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "TAR"); + state->u.f4.fld.pcr3.eccps = cm_object_get_child_by_name(state->u.f4.reg.pcr3, "ECCPS"); + + // SR3 bitfields. + state->u.f4.fld.sr3.irs = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IRS"); + state->u.f4.fld.sr3.ils = cm_object_get_child_by_name(state->u.f4.reg.sr3, "ILS"); + state->u.f4.fld.sr3.ifs = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IFS"); + state->u.f4.fld.sr3.iren = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IREN"); + state->u.f4.fld.sr3.ilen = cm_object_get_child_by_name(state->u.f4.reg.sr3, "ILEN"); + state->u.f4.fld.sr3.ifen = cm_object_get_child_by_name(state->u.f4.reg.sr3, "IFEN"); + state->u.f4.fld.sr3.fempt = cm_object_get_child_by_name(state->u.f4.reg.sr3, "FEMPT"); + + // PMEM3 bitfields. + state->u.f4.fld.pmem3.memsetx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMSETx"); + state->u.f4.fld.pmem3.memwaitx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMWAITx"); + state->u.f4.fld.pmem3.memholdx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMHOLDx"); + state->u.f4.fld.pmem3.memhizx = cm_object_get_child_by_name(state->u.f4.reg.pmem3, "MEMHIZx"); + + // PATT3 bitfields. + state->u.f4.fld.patt3.attsetx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTSETx"); + state->u.f4.fld.patt3.attwaitx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTWAITx"); + state->u.f4.fld.patt3.attholdx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTHOLDx"); + state->u.f4.fld.patt3.atthizx = cm_object_get_child_by_name(state->u.f4.reg.patt3, "ATTHIZx"); + + // ECCR3 bitfields. + state->u.f4.fld.eccr3.eccx = cm_object_get_child_by_name(state->u.f4.reg.eccr3, "ECCx"); + + // PCR4 bitfields. + state->u.f4.fld.pcr4.pwaiten = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PWAITEN"); + state->u.f4.fld.pcr4.pbken = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PBKEN"); + state->u.f4.fld.pcr4.ptyp = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PTYP"); + state->u.f4.fld.pcr4.pwid = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "PWID"); + state->u.f4.fld.pcr4.eccen = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "ECCEN"); + state->u.f4.fld.pcr4.tclr = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "TCLR"); + state->u.f4.fld.pcr4.tar = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "TAR"); + state->u.f4.fld.pcr4.eccps = cm_object_get_child_by_name(state->u.f4.reg.pcr4, "ECCPS"); + + // SR4 bitfields. + state->u.f4.fld.sr4.irs = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IRS"); + state->u.f4.fld.sr4.ils = cm_object_get_child_by_name(state->u.f4.reg.sr4, "ILS"); + state->u.f4.fld.sr4.ifs = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IFS"); + state->u.f4.fld.sr4.iren = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IREN"); + state->u.f4.fld.sr4.ilen = cm_object_get_child_by_name(state->u.f4.reg.sr4, "ILEN"); + state->u.f4.fld.sr4.ifen = cm_object_get_child_by_name(state->u.f4.reg.sr4, "IFEN"); + state->u.f4.fld.sr4.fempt = cm_object_get_child_by_name(state->u.f4.reg.sr4, "FEMPT"); + + // PMEM4 bitfields. + state->u.f4.fld.pmem4.memsetx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMSETx"); + state->u.f4.fld.pmem4.memwaitx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMWAITx"); + state->u.f4.fld.pmem4.memholdx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMHOLDx"); + state->u.f4.fld.pmem4.memhizx = cm_object_get_child_by_name(state->u.f4.reg.pmem4, "MEMHIZx"); + + // PATT4 bitfields. + state->u.f4.fld.patt4.attsetx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTSETx"); + state->u.f4.fld.patt4.attwaitx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTWAITx"); + state->u.f4.fld.patt4.attholdx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTHOLDx"); + state->u.f4.fld.patt4.atthizx = cm_object_get_child_by_name(state->u.f4.reg.patt4, "ATTHIZx"); + + // PIO4 bitfields. + state->u.f4.fld.pio4.iosetx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOSETx"); + state->u.f4.fld.pio4.iowaitx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOWAITx"); + state->u.f4.fld.pio4.ioholdx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOHOLDx"); + state->u.f4.fld.pio4.iohizx = cm_object_get_child_by_name(state->u.f4.reg.pio4, "IOHIZx"); + + // BWTR1 bitfields. + state->u.f4.fld.bwtr1.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "ADDSET"); + state->u.f4.fld.bwtr1.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "ADDHLD"); + state->u.f4.fld.bwtr1.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "DATAST"); + state->u.f4.fld.bwtr1.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "CLKDIV"); + state->u.f4.fld.bwtr1.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "DATLAT"); + state->u.f4.fld.bwtr1.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr1, "ACCMOD"); + + // BWTR2 bitfields. + state->u.f4.fld.bwtr2.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "ADDSET"); + state->u.f4.fld.bwtr2.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "ADDHLD"); + state->u.f4.fld.bwtr2.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "DATAST"); + state->u.f4.fld.bwtr2.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "CLKDIV"); + state->u.f4.fld.bwtr2.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "DATLAT"); + state->u.f4.fld.bwtr2.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr2, "ACCMOD"); + + // BWTR3 bitfields. + state->u.f4.fld.bwtr3.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "ADDSET"); + state->u.f4.fld.bwtr3.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "ADDHLD"); + state->u.f4.fld.bwtr3.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "DATAST"); + state->u.f4.fld.bwtr3.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "CLKDIV"); + state->u.f4.fld.bwtr3.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "DATLAT"); + state->u.f4.fld.bwtr3.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr3, "ACCMOD"); + + // BWTR4 bitfields. + state->u.f4.fld.bwtr4.addset = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "ADDSET"); + state->u.f4.fld.bwtr4.addhld = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "ADDHLD"); + state->u.f4.fld.bwtr4.datast = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "DATAST"); + state->u.f4.fld.bwtr4.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "CLKDIV"); + state->u.f4.fld.bwtr4.datlat = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "DATLAT"); + state->u.f4.fld.bwtr4.accmod = cm_object_get_child_by_name(state->u.f4.reg.bwtr4, "ACCMOD"); + + // SDCR1 bitfields. + state->u.f4.fld.sdcr1.nc = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "NC"); + state->u.f4.fld.sdcr1.nr = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "NR"); + state->u.f4.fld.sdcr1.mwid = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "MWID"); + state->u.f4.fld.sdcr1.nb = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "NB"); + state->u.f4.fld.sdcr1.cas = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "CAS"); + state->u.f4.fld.sdcr1.wp = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "WP"); + state->u.f4.fld.sdcr1.sdclk = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "SDCLK"); + state->u.f4.fld.sdcr1.rburst = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "RBURST"); + state->u.f4.fld.sdcr1.rpipe = cm_object_get_child_by_name(state->u.f4.reg.sdcr1, "RPIPE"); + + // SDCR2 bitfields. + state->u.f4.fld.sdcr2.nc = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "NC"); + state->u.f4.fld.sdcr2.nr = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "NR"); + state->u.f4.fld.sdcr2.mwid = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "MWID"); + state->u.f4.fld.sdcr2.nb = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "NB"); + state->u.f4.fld.sdcr2.cas = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "CAS"); + state->u.f4.fld.sdcr2.wp = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "WP"); + state->u.f4.fld.sdcr2.sdclk = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "SDCLK"); + state->u.f4.fld.sdcr2.rburst = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "RBURST"); + state->u.f4.fld.sdcr2.rpipe = cm_object_get_child_by_name(state->u.f4.reg.sdcr2, "RPIPE"); + + // SDTR1 bitfields. + state->u.f4.fld.sdtr1.tmrd = cm_object_get_child_by_name(state->u.f4.reg.sdtr1, "TMRD"); + state->u.f4.fld.sdtr1.txsr = cm_object_get_child_by_name(state->u.f4.reg.sdtr1, "TXSR"); + state->u.f4.fld.sdtr1.tras = cm_object_get_child_by_name(state->u.f4.reg.sdtr1, "TRAS"); + state->u.f4.fld.sdtr1.trc = cm_object_get_child_by_name(state->u.f4.reg.sdtr1, "TRC"); + state->u.f4.fld.sdtr1.twr = cm_object_get_child_by_name(state->u.f4.reg.sdtr1, "TWR"); + state->u.f4.fld.sdtr1.trp = cm_object_get_child_by_name(state->u.f4.reg.sdtr1, "TRP"); + state->u.f4.fld.sdtr1.trcd = cm_object_get_child_by_name(state->u.f4.reg.sdtr1, "TRCD"); + + // SDTR2 bitfields. + state->u.f4.fld.sdtr2.tmrd = cm_object_get_child_by_name(state->u.f4.reg.sdtr2, "TMRD"); + state->u.f4.fld.sdtr2.txsr = cm_object_get_child_by_name(state->u.f4.reg.sdtr2, "TXSR"); + state->u.f4.fld.sdtr2.tras = cm_object_get_child_by_name(state->u.f4.reg.sdtr2, "TRAS"); + state->u.f4.fld.sdtr2.trc = cm_object_get_child_by_name(state->u.f4.reg.sdtr2, "TRC"); + state->u.f4.fld.sdtr2.twr = cm_object_get_child_by_name(state->u.f4.reg.sdtr2, "TWR"); + state->u.f4.fld.sdtr2.trp = cm_object_get_child_by_name(state->u.f4.reg.sdtr2, "TRP"); + state->u.f4.fld.sdtr2.trcd = cm_object_get_child_by_name(state->u.f4.reg.sdtr2, "TRCD"); + + // SDCMR bitfields. + state->u.f4.fld.sdcmr.mode = cm_object_get_child_by_name(state->u.f4.reg.sdcmr, "MODE"); + state->u.f4.fld.sdcmr.ctb2 = cm_object_get_child_by_name(state->u.f4.reg.sdcmr, "CTB2"); + state->u.f4.fld.sdcmr.ctb1 = cm_object_get_child_by_name(state->u.f4.reg.sdcmr, "CTB1"); + state->u.f4.fld.sdcmr.nrfs = cm_object_get_child_by_name(state->u.f4.reg.sdcmr, "NRFS"); + state->u.f4.fld.sdcmr.mrd = cm_object_get_child_by_name(state->u.f4.reg.sdcmr, "MRD"); + + // SDRTR bitfields. + state->u.f4.fld.sdrtr.cre = cm_object_get_child_by_name(state->u.f4.reg.sdrtr, "CRE"); + state->u.f4.fld.sdrtr.count = cm_object_get_child_by_name(state->u.f4.reg.sdrtr, "COUNT"); + state->u.f4.fld.sdrtr.reie = cm_object_get_child_by_name(state->u.f4.reg.sdrtr, "REIE"); + + // SDSR bitfields. + state->u.f4.fld.sdsr.re = cm_object_get_child_by_name(state->u.f4.reg.sdsr, "RE"); + state->u.f4.fld.sdsr.modes1 = cm_object_get_child_by_name(state->u.f4.reg.sdsr, "MODES1"); + state->u.f4.fld.sdsr.modes2 = cm_object_get_child_by_name(state->u.f4.reg.sdsr, "MODES2"); + state->u.f4.fld.sdsr.busy = cm_object_get_child_by_name(state->u.f4.reg.sdsr, "BUSY"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_fmc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FMCState *state = STM32_FMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_fmc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32FMCState *state = STM32_FMC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_fmc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FMCState *state = STM32_FMC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_fmc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32FMCState *state = STM32_FMC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_fmc_is_enabled(Object *obj) +{ + STM32FMCState *state = STM32_FMC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_fmc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32FMCState *state = STM32_FMC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_fmc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_FMC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32FMCState *state = STM32_FMC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "FMC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_fmc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_fmc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_fmc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_fmc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_fmc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/FMCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_fmc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_FMC); +} + +static void stm32_fmc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_fmc_reset_callback; + dc->realize = stm32_fmc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_fmc_is_enabled; +} + +static const TypeInfo stm32_fmc_type_info = { + .name = TYPE_STM32_FMC, + .parent = TYPE_STM32_FMC_PARENT, + .instance_init = stm32_fmc_instance_init_callback, + .instance_size = sizeof(STM32FMCState), + .class_init = stm32_fmc_class_init_callback, + .class_size = sizeof(STM32FMCClass) }; + +static void stm32_fmc_register_types(void) +{ + type_register_static(&stm32_fmc_type_info); +} + +type_init(stm32_fmc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/fmc.h b/gnu-mcu-eclipse/devices/support/STM32F429x/fmc.h new file mode 100644 index 0000000000..928ade8e16 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/fmc.h @@ -0,0 +1,496 @@ +/* + * STM32 - FMC (Flexible memory controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_FMC_H_ +#define STM32_FMC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_FMC DEVICE_PATH_STM32 "FMC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_FMC TYPE_STM32_PREFIX "fmc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_FMC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32FMCParentClass; +typedef PeripheralState STM32FMCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_FMC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32FMCClass, (obj), TYPE_STM32_FMC) +#define STM32_FMC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32FMCClass, (klass), TYPE_STM32_FMC) + +typedef struct { + // private: + STM32FMCParentClass parent_class; + // public: + + // None, so far. +} STM32FMCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_FMC_STATE(obj) \ + OBJECT_CHECK(STM32FMCState, (obj), TYPE_STM32_FMC) + +typedef struct { + // private: + STM32FMCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 FMC (Flexible memory controller) registers. + struct { + Object *bcr1; // 0x0 (SRAM/NOR-Flash chip-select control register 1) + Object *btr1; // 0x4 (SRAM/NOR-Flash chip-select timing register 1) + Object *bcr2; // 0x8 (SRAM/NOR-Flash chip-select control register 2) + Object *btr2; // 0xC (SRAM/NOR-Flash chip-select timing register 2) + Object *bcr3; // 0x10 (SRAM/NOR-Flash chip-select control register 3) + Object *btr3; // 0x14 (SRAM/NOR-Flash chip-select timing register 3) + Object *bcr4; // 0x18 (SRAM/NOR-Flash chip-select control register 4) + Object *btr4; // 0x1C (SRAM/NOR-Flash chip-select timing register 4) + Object *pcr2; // 0x60 (PC Card/NAND Flash control register 2) + Object *sr2; // 0x64 (FIFO status and interrupt register 2) + Object *pmem2; // 0x68 (Common memory space timing register 2) + Object *patt2; // 0x6C (Attribute memory space timing register 2) + Object *eccr2; // 0x74 (ECC result register 2) + Object *pcr3; // 0x80 (PC Card/NAND Flash control register 3) + Object *sr3; // 0x84 (FIFO status and interrupt register 3) + Object *pmem3; // 0x88 (Common memory space timing register 3) + Object *patt3; // 0x8C (Attribute memory space timing register 3) + Object *eccr3; // 0x94 (ECC result register 3) + Object *pcr4; // 0xA0 (PC Card/NAND Flash control register 4) + Object *sr4; // 0xA4 (FIFO status and interrupt register 4) + Object *pmem4; // 0xA8 (Common memory space timing register 4) + Object *patt4; // 0xAC (Attribute memory space timing register 4) + Object *pio4; // 0xB0 (I/O space timing register 4) + Object *bwtr1; // 0x104 (SRAM/NOR-Flash write timing registers 1) + Object *bwtr2; // 0x10C (SRAM/NOR-Flash write timing registers 2) + Object *bwtr3; // 0x114 (SRAM/NOR-Flash write timing registers 3) + Object *bwtr4; // 0x11C (SRAM/NOR-Flash write timing registers 4) + Object *sdcr1; // 0x140 (SDRAM Control Register 1) + Object *sdcr2; // 0x144 (SDRAM Control Register 2) + Object *sdtr1; // 0x148 (SDRAM Timing register 1) + Object *sdtr2; // 0x14C (SDRAM Timing register 2) + Object *sdcmr; // 0x150 (SDRAM Command Mode register) + Object *sdrtr; // 0x154 (SDRAM Refresh Timer register) + Object *sdsr; // 0x158 (SDRAM Status register) + } reg; + + struct { + + // BCR1 (SRAM/NOR-Flash chip-select control register 1) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + Object *cclken; // [20:20] CCLKEN + } bcr1; + + // BTR1 (SRAM/NOR-Flash chip-select timing register 1) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr1; + + // BCR2 (SRAM/NOR-Flash chip-select control register 2) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr2; + + // BTR2 (SRAM/NOR-Flash chip-select timing register 2) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr2; + + // BCR3 (SRAM/NOR-Flash chip-select control register 3) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr3; + + // BTR3 (SRAM/NOR-Flash chip-select timing register 3) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr3; + + // BCR4 (SRAM/NOR-Flash chip-select control register 4) bitfields. + struct { + Object *mbken; // [0:0] MBKEN + Object *muxen; // [1:1] MUXEN + Object *mtyp; // [2:3] MTYP + Object *mwid; // [4:5] MWID + Object *faccen; // [6:6] FACCEN + Object *bursten; // [8:8] BURSTEN + Object *waitpol; // [9:9] WAITPOL + Object *wrapmod; // [10:10] WRAPMOD + Object *waitcfg; // [11:11] WAITCFG + Object *wren; // [12:12] WREN + Object *waiten; // [13:13] WAITEN + Object *extmod; // [14:14] EXTMOD + Object *asyncwait; // [15:15] ASYNCWAIT + Object *cburstrw; // [19:19] CBURSTRW + } bcr4; + + // BTR4 (SRAM/NOR-Flash chip-select timing register 4) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *busturn; // [16:19] BUSTURN + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } btr4; + + // PCR2 (PC Card/NAND Flash control register 2) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr2; + + // SR2 (FIFO status and interrupt register 2) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr2; + + // PMEM2 (Common memory space timing register 2) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem2; + + // PATT2 (Attribute memory space timing register 2) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt2; + + // ECCR2 (ECC result register 2) bitfields. + struct { + Object *eccx; // [0:31] ECCx + } eccr2; + + // PCR3 (PC Card/NAND Flash control register 3) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr3; + + // SR3 (FIFO status and interrupt register 3) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr3; + + // PMEM3 (Common memory space timing register 3) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem3; + + // PATT3 (Attribute memory space timing register 3) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt3; + + // ECCR3 (ECC result register 3) bitfields. + struct { + Object *eccx; // [0:31] ECCx + } eccr3; + + // PCR4 (PC Card/NAND Flash control register 4) bitfields. + struct { + Object *pwaiten; // [1:1] PWAITEN + Object *pbken; // [2:2] PBKEN + Object *ptyp; // [3:3] PTYP + Object *pwid; // [4:5] PWID + Object *eccen; // [6:6] ECCEN + Object *tclr; // [9:12] TCLR + Object *tar; // [13:16] TAR + Object *eccps; // [17:19] ECCPS + } pcr4; + + // SR4 (FIFO status and interrupt register 4) bitfields. + struct { + Object *irs; // [0:0] IRS + Object *ils; // [1:1] ILS + Object *ifs; // [2:2] IFS + Object *iren; // [3:3] IREN + Object *ilen; // [4:4] ILEN + Object *ifen; // [5:5] IFEN + Object *fempt; // [6:6] FEMPT + } sr4; + + // PMEM4 (Common memory space timing register 4) bitfields. + struct { + Object *memsetx; // [0:7] MEMSETx + Object *memwaitx; // [8:15] MEMWAITx + Object *memholdx; // [16:23] MEMHOLDx + Object *memhizx; // [24:31] MEMHIZx + } pmem4; + + // PATT4 (Attribute memory space timing register 4) bitfields. + struct { + Object *attsetx; // [0:7] ATTSETx + Object *attwaitx; // [8:15] ATTWAITx + Object *attholdx; // [16:23] ATTHOLDx + Object *atthizx; // [24:31] ATTHIZx + } patt4; + + // PIO4 (I/O space timing register 4) bitfields. + struct { + Object *iosetx; // [0:7] IOSETx + Object *iowaitx; // [8:15] IOWAITx + Object *ioholdx; // [16:23] IOHOLDx + Object *iohizx; // [24:31] IOHIZx + } pio4; + + // BWTR1 (SRAM/NOR-Flash write timing registers 1) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr1; + + // BWTR2 (SRAM/NOR-Flash write timing registers 2) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr2; + + // BWTR3 (SRAM/NOR-Flash write timing registers 3) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr3; + + // BWTR4 (SRAM/NOR-Flash write timing registers 4) bitfields. + struct { + Object *addset; // [0:3] ADDSET + Object *addhld; // [4:7] ADDHLD + Object *datast; // [8:15] DATAST + Object *clkdiv; // [20:23] CLKDIV + Object *datlat; // [24:27] DATLAT + Object *accmod; // [28:29] ACCMOD + } bwtr4; + + // SDCR1 (SDRAM Control Register 1) bitfields. + struct { + Object *nc; // [0:1] Number of column address bits + Object *nr; // [2:3] Number of row address bits + Object *mwid; // [4:5] Memory data bus width + Object *nb; // [6:6] Number of internal banks + Object *cas; // [7:8] CAS latency + Object *wp; // [9:9] Write protection + Object *sdclk; // [10:11] SDRAM clock configuration + Object *rburst; // [12:12] Burst read + Object *rpipe; // [13:14] Read pipe + } sdcr1; + + // SDCR2 (SDRAM Control Register 2) bitfields. + struct { + Object *nc; // [0:1] Number of column address bits + Object *nr; // [2:3] Number of row address bits + Object *mwid; // [4:5] Memory data bus width + Object *nb; // [6:6] Number of internal banks + Object *cas; // [7:8] CAS latency + Object *wp; // [9:9] Write protection + Object *sdclk; // [10:11] SDRAM clock configuration + Object *rburst; // [12:12] Burst read + Object *rpipe; // [13:14] Read pipe + } sdcr2; + + // SDTR1 (SDRAM Timing register 1) bitfields. + struct { + Object *tmrd; // [0:3] Load Mode Register to Active + Object *txsr; // [4:7] Exit self-refresh delay + Object *tras; // [8:11] Self refresh time + Object *trc; // [12:15] Row cycle delay + Object *twr; // [16:19] Recovery delay + Object *trp; // [20:23] Row precharge delay + Object *trcd; // [24:27] Row to column delay + } sdtr1; + + // SDTR2 (SDRAM Timing register 2) bitfields. + struct { + Object *tmrd; // [0:3] Load Mode Register to Active + Object *txsr; // [4:7] Exit self-refresh delay + Object *tras; // [8:11] Self refresh time + Object *trc; // [12:15] Row cycle delay + Object *twr; // [16:19] Recovery delay + Object *trp; // [20:23] Row precharge delay + Object *trcd; // [24:27] Row to column delay + } sdtr2; + + // SDCMR (SDRAM Command Mode register) bitfields. + struct { + Object *mode; // [0:2] Command mode + Object *ctb2; // [3:3] Command target bank 2 + Object *ctb1; // [4:4] Command target bank 1 + Object *nrfs; // [5:8] Number of Auto-refresh + Object *mrd; // [9:21] Mode Register definition + } sdcmr; + + // SDRTR (SDRAM Refresh Timer register) bitfields. + struct { + Object *cre; // [0:0] Clear Refresh error flag + Object *count; // [1:13] Refresh Timer Count + Object *reie; // [14:14] RES Interrupt Enable + } sdrtr; + + // SDSR (SDRAM Status register) bitfields. + struct { + Object *re; // [0:0] Refresh error flag + Object *modes1; // [1:2] Status Mode for Bank 1 + Object *modes2; // [3:4] Status Mode for Bank 2 + Object *busy; // [5:5] Busy status + } sdsr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32FMCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_FMC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/gpioa.c b/gnu-mcu-eclipse/devices/support/STM32F429x/gpioa.c new file mode 100644 index 0000000000..bf50fe396a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/gpioa.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/gpioa.h b/gnu-mcu-eclipse/devices/support/STM32F429x/gpioa.h new file mode 100644 index 0000000000..f3c4aa7e29 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/gpioa.h @@ -0,0 +1,330 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIOG, + STM32_PORT_GPIOH, + STM32_PORT_GPIOI, + STM32_PORT_GPIOJ, + STM32_PORT_GPIOK, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/gpiob.c b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiob.c new file mode 100644 index 0000000000..bf50fe396a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiob.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/gpiob.h b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiob.h new file mode 100644 index 0000000000..f3c4aa7e29 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiob.h @@ -0,0 +1,330 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIOG, + STM32_PORT_GPIOH, + STM32_PORT_GPIOI, + STM32_PORT_GPIOJ, + STM32_PORT_GPIOK, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/gpiok.c b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiok.c new file mode 100644 index 0000000000..bf50fe396a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiok.c @@ -0,0 +1,430 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_gpio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.moder = cm_object_get_child_by_name(obj, "MODER"); + state->u.f4.reg.otyper = cm_object_get_child_by_name(obj, "OTYPER"); + state->u.f4.reg.ospeedr = cm_object_get_child_by_name(obj, "OSPEEDR"); + state->u.f4.reg.pupdr = cm_object_get_child_by_name(obj, "PUPDR"); + state->u.f4.reg.idr = cm_object_get_child_by_name(obj, "IDR"); + state->u.f4.reg.odr = cm_object_get_child_by_name(obj, "ODR"); + state->u.f4.reg.bsrr = cm_object_get_child_by_name(obj, "BSRR"); + state->u.f4.reg.lckr = cm_object_get_child_by_name(obj, "LCKR"); + state->u.f4.reg.afrl = cm_object_get_child_by_name(obj, "AFRL"); + state->u.f4.reg.afrh = cm_object_get_child_by_name(obj, "AFRH"); + + + // MODER bitfields. + state->u.f4.fld.moder.moder0 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER0"); + state->u.f4.fld.moder.moder1 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER1"); + state->u.f4.fld.moder.moder2 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER2"); + state->u.f4.fld.moder.moder3 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER3"); + state->u.f4.fld.moder.moder4 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER4"); + state->u.f4.fld.moder.moder5 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER5"); + state->u.f4.fld.moder.moder6 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER6"); + state->u.f4.fld.moder.moder7 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER7"); + state->u.f4.fld.moder.moder8 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER8"); + state->u.f4.fld.moder.moder9 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER9"); + state->u.f4.fld.moder.moder10 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER10"); + state->u.f4.fld.moder.moder11 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER11"); + state->u.f4.fld.moder.moder12 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER12"); + state->u.f4.fld.moder.moder13 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER13"); + state->u.f4.fld.moder.moder14 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER14"); + state->u.f4.fld.moder.moder15 = cm_object_get_child_by_name(state->u.f4.reg.moder, "MODER15"); + + // OTYPER bitfields. + state->u.f4.fld.otyper.ot0 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT0"); + state->u.f4.fld.otyper.ot1 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT1"); + state->u.f4.fld.otyper.ot2 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT2"); + state->u.f4.fld.otyper.ot3 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT3"); + state->u.f4.fld.otyper.ot4 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT4"); + state->u.f4.fld.otyper.ot5 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT5"); + state->u.f4.fld.otyper.ot6 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT6"); + state->u.f4.fld.otyper.ot7 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT7"); + state->u.f4.fld.otyper.ot8 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT8"); + state->u.f4.fld.otyper.ot9 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT9"); + state->u.f4.fld.otyper.ot10 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT10"); + state->u.f4.fld.otyper.ot11 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT11"); + state->u.f4.fld.otyper.ot12 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT12"); + state->u.f4.fld.otyper.ot13 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT13"); + state->u.f4.fld.otyper.ot14 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT14"); + state->u.f4.fld.otyper.ot15 = cm_object_get_child_by_name(state->u.f4.reg.otyper, "OT15"); + + // OSPEEDR bitfields. + state->u.f4.fld.ospeedr.ospeedr0 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR0"); + state->u.f4.fld.ospeedr.ospeedr1 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR1"); + state->u.f4.fld.ospeedr.ospeedr2 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR2"); + state->u.f4.fld.ospeedr.ospeedr3 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR3"); + state->u.f4.fld.ospeedr.ospeedr4 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR4"); + state->u.f4.fld.ospeedr.ospeedr5 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR5"); + state->u.f4.fld.ospeedr.ospeedr6 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR6"); + state->u.f4.fld.ospeedr.ospeedr7 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR7"); + state->u.f4.fld.ospeedr.ospeedr8 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR8"); + state->u.f4.fld.ospeedr.ospeedr9 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR9"); + state->u.f4.fld.ospeedr.ospeedr10 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR10"); + state->u.f4.fld.ospeedr.ospeedr11 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR11"); + state->u.f4.fld.ospeedr.ospeedr12 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR12"); + state->u.f4.fld.ospeedr.ospeedr13 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR13"); + state->u.f4.fld.ospeedr.ospeedr14 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR14"); + state->u.f4.fld.ospeedr.ospeedr15 = cm_object_get_child_by_name(state->u.f4.reg.ospeedr, "OSPEEDR15"); + + // PUPDR bitfields. + state->u.f4.fld.pupdr.pupdr0 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR0"); + state->u.f4.fld.pupdr.pupdr1 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR1"); + state->u.f4.fld.pupdr.pupdr2 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR2"); + state->u.f4.fld.pupdr.pupdr3 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR3"); + state->u.f4.fld.pupdr.pupdr4 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR4"); + state->u.f4.fld.pupdr.pupdr5 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR5"); + state->u.f4.fld.pupdr.pupdr6 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR6"); + state->u.f4.fld.pupdr.pupdr7 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR7"); + state->u.f4.fld.pupdr.pupdr8 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR8"); + state->u.f4.fld.pupdr.pupdr9 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR9"); + state->u.f4.fld.pupdr.pupdr10 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR10"); + state->u.f4.fld.pupdr.pupdr11 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR11"); + state->u.f4.fld.pupdr.pupdr12 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR12"); + state->u.f4.fld.pupdr.pupdr13 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR13"); + state->u.f4.fld.pupdr.pupdr14 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR14"); + state->u.f4.fld.pupdr.pupdr15 = cm_object_get_child_by_name(state->u.f4.reg.pupdr, "PUPDR15"); + + // IDR bitfields. + state->u.f4.fld.idr.idr0 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR0"); + state->u.f4.fld.idr.idr1 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR1"); + state->u.f4.fld.idr.idr2 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR2"); + state->u.f4.fld.idr.idr3 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR3"); + state->u.f4.fld.idr.idr4 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR4"); + state->u.f4.fld.idr.idr5 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR5"); + state->u.f4.fld.idr.idr6 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR6"); + state->u.f4.fld.idr.idr7 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR7"); + state->u.f4.fld.idr.idr8 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR8"); + state->u.f4.fld.idr.idr9 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR9"); + state->u.f4.fld.idr.idr10 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR10"); + state->u.f4.fld.idr.idr11 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR11"); + state->u.f4.fld.idr.idr12 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR12"); + state->u.f4.fld.idr.idr13 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR13"); + state->u.f4.fld.idr.idr14 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR14"); + state->u.f4.fld.idr.idr15 = cm_object_get_child_by_name(state->u.f4.reg.idr, "IDR15"); + + // ODR bitfields. + state->u.f4.fld.odr.odr0 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR0"); + state->u.f4.fld.odr.odr1 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR1"); + state->u.f4.fld.odr.odr2 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR2"); + state->u.f4.fld.odr.odr3 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR3"); + state->u.f4.fld.odr.odr4 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR4"); + state->u.f4.fld.odr.odr5 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR5"); + state->u.f4.fld.odr.odr6 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR6"); + state->u.f4.fld.odr.odr7 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR7"); + state->u.f4.fld.odr.odr8 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR8"); + state->u.f4.fld.odr.odr9 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR9"); + state->u.f4.fld.odr.odr10 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR10"); + state->u.f4.fld.odr.odr11 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR11"); + state->u.f4.fld.odr.odr12 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR12"); + state->u.f4.fld.odr.odr13 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR13"); + state->u.f4.fld.odr.odr14 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR14"); + state->u.f4.fld.odr.odr15 = cm_object_get_child_by_name(state->u.f4.reg.odr, "ODR15"); + + // BSRR bitfields. + state->u.f4.fld.bsrr.bs0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS0"); + state->u.f4.fld.bsrr.bs1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS1"); + state->u.f4.fld.bsrr.bs2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS2"); + state->u.f4.fld.bsrr.bs3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS3"); + state->u.f4.fld.bsrr.bs4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS4"); + state->u.f4.fld.bsrr.bs5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS5"); + state->u.f4.fld.bsrr.bs6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS6"); + state->u.f4.fld.bsrr.bs7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS7"); + state->u.f4.fld.bsrr.bs8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS8"); + state->u.f4.fld.bsrr.bs9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS9"); + state->u.f4.fld.bsrr.bs10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS10"); + state->u.f4.fld.bsrr.bs11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS11"); + state->u.f4.fld.bsrr.bs12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS12"); + state->u.f4.fld.bsrr.bs13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS13"); + state->u.f4.fld.bsrr.bs14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS14"); + state->u.f4.fld.bsrr.bs15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BS15"); + state->u.f4.fld.bsrr.br0 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR0"); + state->u.f4.fld.bsrr.br1 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR1"); + state->u.f4.fld.bsrr.br2 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR2"); + state->u.f4.fld.bsrr.br3 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR3"); + state->u.f4.fld.bsrr.br4 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR4"); + state->u.f4.fld.bsrr.br5 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR5"); + state->u.f4.fld.bsrr.br6 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR6"); + state->u.f4.fld.bsrr.br7 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR7"); + state->u.f4.fld.bsrr.br8 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR8"); + state->u.f4.fld.bsrr.br9 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR9"); + state->u.f4.fld.bsrr.br10 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR10"); + state->u.f4.fld.bsrr.br11 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR11"); + state->u.f4.fld.bsrr.br12 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR12"); + state->u.f4.fld.bsrr.br13 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR13"); + state->u.f4.fld.bsrr.br14 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR14"); + state->u.f4.fld.bsrr.br15 = cm_object_get_child_by_name(state->u.f4.reg.bsrr, "BR15"); + + // LCKR bitfields. + state->u.f4.fld.lckr.lck0 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK0"); + state->u.f4.fld.lckr.lck1 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK1"); + state->u.f4.fld.lckr.lck2 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK2"); + state->u.f4.fld.lckr.lck3 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK3"); + state->u.f4.fld.lckr.lck4 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK4"); + state->u.f4.fld.lckr.lck5 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK5"); + state->u.f4.fld.lckr.lck6 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK6"); + state->u.f4.fld.lckr.lck7 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK7"); + state->u.f4.fld.lckr.lck8 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK8"); + state->u.f4.fld.lckr.lck9 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK9"); + state->u.f4.fld.lckr.lck10 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK10"); + state->u.f4.fld.lckr.lck11 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK11"); + state->u.f4.fld.lckr.lck12 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK12"); + state->u.f4.fld.lckr.lck13 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK13"); + state->u.f4.fld.lckr.lck14 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK14"); + state->u.f4.fld.lckr.lck15 = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCK15"); + state->u.f4.fld.lckr.lckk = cm_object_get_child_by_name(state->u.f4.reg.lckr, "LCKK"); + + // AFRL bitfields. + state->u.f4.fld.afrl.afrl0 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL0"); + state->u.f4.fld.afrl.afrl1 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL1"); + state->u.f4.fld.afrl.afrl2 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL2"); + state->u.f4.fld.afrl.afrl3 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL3"); + state->u.f4.fld.afrl.afrl4 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL4"); + state->u.f4.fld.afrl.afrl5 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL5"); + state->u.f4.fld.afrl.afrl6 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL6"); + state->u.f4.fld.afrl.afrl7 = cm_object_get_child_by_name(state->u.f4.reg.afrl, "AFRL7"); + + // AFRH bitfields. + state->u.f4.fld.afrh.afrh8 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH8"); + state->u.f4.fld.afrh.afrh9 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH9"); + state->u.f4.fld.afrh.afrh10 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH10"); + state->u.f4.fld.afrh.afrh11 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH11"); + state->u.f4.fld.afrh.afrh12 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH12"); + state->u.f4.fld.afrh.afrh13 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH13"); + state->u.f4.fld.afrh.afrh14 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH14"); + state->u.f4.fld.afrh.afrh15 = cm_object_get_child_by_name(state->u.f4.reg.afrh, "AFRH15"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_gpio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_gpio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_gpio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_gpio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32GPIOState *state = STM32_GPIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_gpio_is_enabled(Object *obj) +{ + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_gpio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32GPIOState *state = STM32_GPIO_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_GPIO_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_gpio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_GPIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32GPIOState *state = STM32_GPIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "GPIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_gpio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_gpio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_gpio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_gpio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/GPIO%dEN", + 1 + state->port_index - STM32_PORT_GPIO1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_gpio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_GPIO); +} + +static void stm32_gpio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_gpio_reset_callback; + dc->realize = stm32_gpio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_gpio_is_enabled; +} + +static const TypeInfo stm32_gpio_type_info = { + .name = TYPE_STM32_GPIO, + .parent = TYPE_STM32_GPIO_PARENT, + .instance_init = stm32_gpio_instance_init_callback, + .instance_size = sizeof(STM32GPIOState), + .class_init = stm32_gpio_class_init_callback, + .class_size = sizeof(STM32GPIOClass) }; + +static void stm32_gpio_register_types(void) +{ + type_register_static(&stm32_gpio_type_info); +} + +type_init(stm32_gpio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/gpiok.h b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiok.h new file mode 100644 index 0000000000..f3c4aa7e29 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/gpiok.h @@ -0,0 +1,330 @@ +/* + * STM32 - GPIO (General-purpose I/Os) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_GPIO_H_ +#define STM32_GPIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_GPIO DEVICE_PATH_STM32 "GPIO" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_GPIOA, + STM32_PORT_GPIOB, + STM32_PORT_GPIOC, + STM32_PORT_GPIOD, + STM32_PORT_GPIOE, + STM32_PORT_GPIOF, + STM32_PORT_GPIOG, + STM32_PORT_GPIOH, + STM32_PORT_GPIOI, + STM32_PORT_GPIOJ, + STM32_PORT_GPIOK, + STM32_PORT_GPIO_UNDEFINED = 0xFF, +} stm32_gpio_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_GPIO TYPE_STM32_PREFIX "gpio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_GPIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32GPIOParentClass; +typedef PeripheralState STM32GPIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32GPIOClass, (obj), TYPE_STM32_GPIO) +#define STM32_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32GPIOClass, (klass), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentClass parent_class; + // public: + + // None, so far. +} STM32GPIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_GPIO_STATE(obj) \ + OBJECT_CHECK(STM32GPIOState, (obj), TYPE_STM32_GPIO) + +typedef struct { + // private: + STM32GPIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_gpio_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 GPIO (General-purpose I/Os) registers. + struct { + Object *moder; // 0x0 (GPIO port mode register) + Object *otyper; // 0x4 (GPIO port output type register) + Object *ospeedr; // 0x8 (GPIO port output speed register) + Object *pupdr; // 0xC (GPIO port pull-up/pull-down register) + Object *idr; // 0x10 (GPIO port input data register) + Object *odr; // 0x14 (GPIO port output data register) + Object *bsrr; // 0x18 (GPIO port bit set/reset register) + Object *lckr; // 0x1C (GPIO port configuration lock register) + Object *afrl; // 0x20 (GPIO alternate function low register) + Object *afrh; // 0x24 (GPIO alternate function high register) + } reg; + + struct { + + // MODER (GPIO port mode register) bitfields. + struct { + Object *moder0; // [0:1] Port x configuration bits (y = 0..15) + Object *moder1; // [2:3] Port x configuration bits (y = 0..15) + Object *moder2; // [4:5] Port x configuration bits (y = 0..15) + Object *moder3; // [6:7] Port x configuration bits (y = 0..15) + Object *moder4; // [8:9] Port x configuration bits (y = 0..15) + Object *moder5; // [10:11] Port x configuration bits (y = 0..15) + Object *moder6; // [12:13] Port x configuration bits (y = 0..15) + Object *moder7; // [14:15] Port x configuration bits (y = 0..15) + Object *moder8; // [16:17] Port x configuration bits (y = 0..15) + Object *moder9; // [18:19] Port x configuration bits (y = 0..15) + Object *moder10; // [20:21] Port x configuration bits (y = 0..15) + Object *moder11; // [22:23] Port x configuration bits (y = 0..15) + Object *moder12; // [24:25] Port x configuration bits (y = 0..15) + Object *moder13; // [26:27] Port x configuration bits (y = 0..15) + Object *moder14; // [28:29] Port x configuration bits (y = 0..15) + Object *moder15; // [30:31] Port x configuration bits (y = 0..15) + } moder; + + // OTYPER (GPIO port output type register) bitfields. + struct { + Object *ot0; // [0:0] Port x configuration bits (y = 0..15) + Object *ot1; // [1:1] Port x configuration bits (y = 0..15) + Object *ot2; // [2:2] Port x configuration bits (y = 0..15) + Object *ot3; // [3:3] Port x configuration bits (y = 0..15) + Object *ot4; // [4:4] Port x configuration bits (y = 0..15) + Object *ot5; // [5:5] Port x configuration bits (y = 0..15) + Object *ot6; // [6:6] Port x configuration bits (y = 0..15) + Object *ot7; // [7:7] Port x configuration bits (y = 0..15) + Object *ot8; // [8:8] Port x configuration bits (y = 0..15) + Object *ot9; // [9:9] Port x configuration bits (y = 0..15) + Object *ot10; // [10:10] Port x configuration bits (y = 0..15) + Object *ot11; // [11:11] Port x configuration bits (y = 0..15) + Object *ot12; // [12:12] Port x configuration bits (y = 0..15) + Object *ot13; // [13:13] Port x configuration bits (y = 0..15) + Object *ot14; // [14:14] Port x configuration bits (y = 0..15) + Object *ot15; // [15:15] Port x configuration bits (y = 0..15) + } otyper; + + // OSPEEDR (GPIO port output speed register) bitfields. + struct { + Object *ospeedr0; // [0:1] Port x configuration bits (y = 0..15) + Object *ospeedr1; // [2:3] Port x configuration bits (y = 0..15) + Object *ospeedr2; // [4:5] Port x configuration bits (y = 0..15) + Object *ospeedr3; // [6:7] Port x configuration bits (y = 0..15) + Object *ospeedr4; // [8:9] Port x configuration bits (y = 0..15) + Object *ospeedr5; // [10:11] Port x configuration bits (y = 0..15) + Object *ospeedr6; // [12:13] Port x configuration bits (y = 0..15) + Object *ospeedr7; // [14:15] Port x configuration bits (y = 0..15) + Object *ospeedr8; // [16:17] Port x configuration bits (y = 0..15) + Object *ospeedr9; // [18:19] Port x configuration bits (y = 0..15) + Object *ospeedr10; // [20:21] Port x configuration bits (y = 0..15) + Object *ospeedr11; // [22:23] Port x configuration bits (y = 0..15) + Object *ospeedr12; // [24:25] Port x configuration bits (y = 0..15) + Object *ospeedr13; // [26:27] Port x configuration bits (y = 0..15) + Object *ospeedr14; // [28:29] Port x configuration bits (y = 0..15) + Object *ospeedr15; // [30:31] Port x configuration bits (y = 0..15) + } ospeedr; + + // PUPDR (GPIO port pull-up/pull-down register) bitfields. + struct { + Object *pupdr0; // [0:1] Port x configuration bits (y = 0..15) + Object *pupdr1; // [2:3] Port x configuration bits (y = 0..15) + Object *pupdr2; // [4:5] Port x configuration bits (y = 0..15) + Object *pupdr3; // [6:7] Port x configuration bits (y = 0..15) + Object *pupdr4; // [8:9] Port x configuration bits (y = 0..15) + Object *pupdr5; // [10:11] Port x configuration bits (y = 0..15) + Object *pupdr6; // [12:13] Port x configuration bits (y = 0..15) + Object *pupdr7; // [14:15] Port x configuration bits (y = 0..15) + Object *pupdr8; // [16:17] Port x configuration bits (y = 0..15) + Object *pupdr9; // [18:19] Port x configuration bits (y = 0..15) + Object *pupdr10; // [20:21] Port x configuration bits (y = 0..15) + Object *pupdr11; // [22:23] Port x configuration bits (y = 0..15) + Object *pupdr12; // [24:25] Port x configuration bits (y = 0..15) + Object *pupdr13; // [26:27] Port x configuration bits (y = 0..15) + Object *pupdr14; // [28:29] Port x configuration bits (y = 0..15) + Object *pupdr15; // [30:31] Port x configuration bits (y = 0..15) + } pupdr; + + // IDR (GPIO port input data register) bitfields. + struct { + Object *idr0; // [0:0] Port input data (y = 0..15) + Object *idr1; // [1:1] Port input data (y = 0..15) + Object *idr2; // [2:2] Port input data (y = 0..15) + Object *idr3; // [3:3] Port input data (y = 0..15) + Object *idr4; // [4:4] Port input data (y = 0..15) + Object *idr5; // [5:5] Port input data (y = 0..15) + Object *idr6; // [6:6] Port input data (y = 0..15) + Object *idr7; // [7:7] Port input data (y = 0..15) + Object *idr8; // [8:8] Port input data (y = 0..15) + Object *idr9; // [9:9] Port input data (y = 0..15) + Object *idr10; // [10:10] Port input data (y = 0..15) + Object *idr11; // [11:11] Port input data (y = 0..15) + Object *idr12; // [12:12] Port input data (y = 0..15) + Object *idr13; // [13:13] Port input data (y = 0..15) + Object *idr14; // [14:14] Port input data (y = 0..15) + Object *idr15; // [15:15] Port input data (y = 0..15) + } idr; + + // ODR (GPIO port output data register) bitfields. + struct { + Object *odr0; // [0:0] Port output data (y = 0..15) + Object *odr1; // [1:1] Port output data (y = 0..15) + Object *odr2; // [2:2] Port output data (y = 0..15) + Object *odr3; // [3:3] Port output data (y = 0..15) + Object *odr4; // [4:4] Port output data (y = 0..15) + Object *odr5; // [5:5] Port output data (y = 0..15) + Object *odr6; // [6:6] Port output data (y = 0..15) + Object *odr7; // [7:7] Port output data (y = 0..15) + Object *odr8; // [8:8] Port output data (y = 0..15) + Object *odr9; // [9:9] Port output data (y = 0..15) + Object *odr10; // [10:10] Port output data (y = 0..15) + Object *odr11; // [11:11] Port output data (y = 0..15) + Object *odr12; // [12:12] Port output data (y = 0..15) + Object *odr13; // [13:13] Port output data (y = 0..15) + Object *odr14; // [14:14] Port output data (y = 0..15) + Object *odr15; // [15:15] Port output data (y = 0..15) + } odr; + + // BSRR (GPIO port bit set/reset register) bitfields. + struct { + Object *bs0; // [0:0] Port x set bit y (y= 0..15) + Object *bs1; // [1:1] Port x set bit y (y= 0..15) + Object *bs2; // [2:2] Port x set bit y (y= 0..15) + Object *bs3; // [3:3] Port x set bit y (y= 0..15) + Object *bs4; // [4:4] Port x set bit y (y= 0..15) + Object *bs5; // [5:5] Port x set bit y (y= 0..15) + Object *bs6; // [6:6] Port x set bit y (y= 0..15) + Object *bs7; // [7:7] Port x set bit y (y= 0..15) + Object *bs8; // [8:8] Port x set bit y (y= 0..15) + Object *bs9; // [9:9] Port x set bit y (y= 0..15) + Object *bs10; // [10:10] Port x set bit y (y= 0..15) + Object *bs11; // [11:11] Port x set bit y (y= 0..15) + Object *bs12; // [12:12] Port x set bit y (y= 0..15) + Object *bs13; // [13:13] Port x set bit y (y= 0..15) + Object *bs14; // [14:14] Port x set bit y (y= 0..15) + Object *bs15; // [15:15] Port x set bit y (y= 0..15) + Object *br0; // [16:16] Port x set bit y (y= 0..15) + Object *br1; // [17:17] Port x reset bit y (y = 0..15) + Object *br2; // [18:18] Port x reset bit y (y = 0..15) + Object *br3; // [19:19] Port x reset bit y (y = 0..15) + Object *br4; // [20:20] Port x reset bit y (y = 0..15) + Object *br5; // [21:21] Port x reset bit y (y = 0..15) + Object *br6; // [22:22] Port x reset bit y (y = 0..15) + Object *br7; // [23:23] Port x reset bit y (y = 0..15) + Object *br8; // [24:24] Port x reset bit y (y = 0..15) + Object *br9; // [25:25] Port x reset bit y (y = 0..15) + Object *br10; // [26:26] Port x reset bit y (y = 0..15) + Object *br11; // [27:27] Port x reset bit y (y = 0..15) + Object *br12; // [28:28] Port x reset bit y (y = 0..15) + Object *br13; // [29:29] Port x reset bit y (y = 0..15) + Object *br14; // [30:30] Port x reset bit y (y = 0..15) + Object *br15; // [31:31] Port x reset bit y (y = 0..15) + } bsrr; + + // LCKR (GPIO port configuration lock register) bitfields. + struct { + Object *lck0; // [0:0] Port x lock bit y (y= 0..15) + Object *lck1; // [1:1] Port x lock bit y (y= 0..15) + Object *lck2; // [2:2] Port x lock bit y (y= 0..15) + Object *lck3; // [3:3] Port x lock bit y (y= 0..15) + Object *lck4; // [4:4] Port x lock bit y (y= 0..15) + Object *lck5; // [5:5] Port x lock bit y (y= 0..15) + Object *lck6; // [6:6] Port x lock bit y (y= 0..15) + Object *lck7; // [7:7] Port x lock bit y (y= 0..15) + Object *lck8; // [8:8] Port x lock bit y (y= 0..15) + Object *lck9; // [9:9] Port x lock bit y (y= 0..15) + Object *lck10; // [10:10] Port x lock bit y (y= 0..15) + Object *lck11; // [11:11] Port x lock bit y (y= 0..15) + Object *lck12; // [12:12] Port x lock bit y (y= 0..15) + Object *lck13; // [13:13] Port x lock bit y (y= 0..15) + Object *lck14; // [14:14] Port x lock bit y (y= 0..15) + Object *lck15; // [15:15] Port x lock bit y (y= 0..15) + Object *lckk; // [16:16] Port x lock bit y (y= 0..15) + } lckr; + + // AFRL (GPIO alternate function low register) bitfields. + struct { + Object *afrl0; // [0:3] Alternate function selection for port x bit y (y = 0..7) + Object *afrl1; // [4:7] Alternate function selection for port x bit y (y = 0..7) + Object *afrl2; // [8:11] Alternate function selection for port x bit y (y = 0..7) + Object *afrl3; // [12:15] Alternate function selection for port x bit y (y = 0..7) + Object *afrl4; // [16:19] Alternate function selection for port x bit y (y = 0..7) + Object *afrl5; // [20:23] Alternate function selection for port x bit y (y = 0..7) + Object *afrl6; // [24:27] Alternate function selection for port x bit y (y = 0..7) + Object *afrl7; // [28:31] Alternate function selection for port x bit y (y = 0..7) + } afrl; + + // AFRH (GPIO alternate function high register) bitfields. + struct { + Object *afrh8; // [0:3] Alternate function selection for port x bit y (y = 8..15) + Object *afrh9; // [4:7] Alternate function selection for port x bit y (y = 8..15) + Object *afrh10; // [8:11] Alternate function selection for port x bit y (y = 8..15) + Object *afrh11; // [12:15] Alternate function selection for port x bit y (y = 8..15) + Object *afrh12; // [16:19] Alternate function selection for port x bit y (y = 8..15) + Object *afrh13; // [20:23] Alternate function selection for port x bit y (y = 8..15) + Object *afrh14; // [24:27] Alternate function selection for port x bit y (y = 8..15) + Object *afrh15; // [28:31] Alternate function selection for port x bit y (y = 8..15) + } afrh; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32GPIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_GPIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/i2c3.c b/gnu-mcu-eclipse/devices/support/STM32F429x/i2c3.c new file mode 100644 index 0000000000..45d6cdab74 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/i2c3.c @@ -0,0 +1,324 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_i2c_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.oar1 = cm_object_get_child_by_name(obj, "OAR1"); + state->u.f4.reg.oar2 = cm_object_get_child_by_name(obj, "OAR2"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.sr1 = cm_object_get_child_by_name(obj, "SR1"); + state->u.f4.reg.sr2 = cm_object_get_child_by_name(obj, "SR2"); + state->u.f4.reg.ccr = cm_object_get_child_by_name(obj, "CCR"); + state->u.f4.reg.trise = cm_object_get_child_by_name(obj, "TRISE"); + state->u.f4.reg.fltr = cm_object_get_child_by_name(obj, "FLTR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.pe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PE"); + state->u.f4.fld.cr1.smbus = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SMBUS"); + state->u.f4.fld.cr1.smbtype = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SMBTYPE"); + state->u.f4.fld.cr1.enarp = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENARP"); + state->u.f4.fld.cr1.enpec = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENPEC"); + state->u.f4.fld.cr1.engc = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ENGC"); + state->u.f4.fld.cr1.nostretch = cm_object_get_child_by_name(state->u.f4.reg.cr1, "NOSTRETCH"); + state->u.f4.fld.cr1.start = cm_object_get_child_by_name(state->u.f4.reg.cr1, "START"); + state->u.f4.fld.cr1.stop = cm_object_get_child_by_name(state->u.f4.reg.cr1, "STOP"); + state->u.f4.fld.cr1.ack = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ACK"); + state->u.f4.fld.cr1.pos = cm_object_get_child_by_name(state->u.f4.reg.cr1, "POS"); + state->u.f4.fld.cr1.pec = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEC"); + state->u.f4.fld.cr1.alert = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ALERT"); + state->u.f4.fld.cr1.swrst = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SWRST"); + + // CR2 bitfields. + state->u.f4.fld.cr2.freq = cm_object_get_child_by_name(state->u.f4.reg.cr2, "FREQ"); + state->u.f4.fld.cr2.iterren = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITERREN"); + state->u.f4.fld.cr2.itevten = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITEVTEN"); + state->u.f4.fld.cr2.itbufen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ITBUFEN"); + state->u.f4.fld.cr2.dmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "DMAEN"); + state->u.f4.fld.cr2.last = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LAST"); + + // OAR1 bitfields. + state->u.f4.fld.oar1.add0 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD0"); + state->u.f4.fld.oar1.add7 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD7"); + state->u.f4.fld.oar1.add10 = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADD10"); + state->u.f4.fld.oar1.addmode = cm_object_get_child_by_name(state->u.f4.reg.oar1, "ADDMODE"); + + // OAR2 bitfields. + state->u.f4.fld.oar2.endual = cm_object_get_child_by_name(state->u.f4.reg.oar2, "ENDUAL"); + state->u.f4.fld.oar2.add2 = cm_object_get_child_by_name(state->u.f4.reg.oar2, "ADD2"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // SR1 bitfields. + state->u.f4.fld.sr1.sb = cm_object_get_child_by_name(state->u.f4.reg.sr1, "SB"); + state->u.f4.fld.sr1.addr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ADDR"); + state->u.f4.fld.sr1.btf = cm_object_get_child_by_name(state->u.f4.reg.sr1, "BTF"); + state->u.f4.fld.sr1.add10 = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ADD10"); + state->u.f4.fld.sr1.stopf = cm_object_get_child_by_name(state->u.f4.reg.sr1, "STOPF"); + state->u.f4.fld.sr1.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr1, "RxNE"); + state->u.f4.fld.sr1.txe = cm_object_get_child_by_name(state->u.f4.reg.sr1, "TxE"); + state->u.f4.fld.sr1.berr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "BERR"); + state->u.f4.fld.sr1.arlo = cm_object_get_child_by_name(state->u.f4.reg.sr1, "ARLO"); + state->u.f4.fld.sr1.af = cm_object_get_child_by_name(state->u.f4.reg.sr1, "AF"); + state->u.f4.fld.sr1.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "OVR"); + state->u.f4.fld.sr1.pecerr = cm_object_get_child_by_name(state->u.f4.reg.sr1, "PECERR"); + state->u.f4.fld.sr1.timeout = cm_object_get_child_by_name(state->u.f4.reg.sr1, "TIMEOUT"); + state->u.f4.fld.sr1.smbalert = cm_object_get_child_by_name(state->u.f4.reg.sr1, "SMBALERT"); + + // SR2 bitfields. + state->u.f4.fld.sr2.msl = cm_object_get_child_by_name(state->u.f4.reg.sr2, "MSL"); + state->u.f4.fld.sr2.busy = cm_object_get_child_by_name(state->u.f4.reg.sr2, "BUSY"); + state->u.f4.fld.sr2.tra = cm_object_get_child_by_name(state->u.f4.reg.sr2, "TRA"); + state->u.f4.fld.sr2.gencall = cm_object_get_child_by_name(state->u.f4.reg.sr2, "GENCALL"); + state->u.f4.fld.sr2.smbdefault = cm_object_get_child_by_name(state->u.f4.reg.sr2, "SMBDEFAULT"); + state->u.f4.fld.sr2.smbhost = cm_object_get_child_by_name(state->u.f4.reg.sr2, "SMBHOST"); + state->u.f4.fld.sr2.dualf = cm_object_get_child_by_name(state->u.f4.reg.sr2, "DUALF"); + state->u.f4.fld.sr2.pec = cm_object_get_child_by_name(state->u.f4.reg.sr2, "PEC"); + + // CCR bitfields. + state->u.f4.fld.ccr.ccr = cm_object_get_child_by_name(state->u.f4.reg.ccr, "CCR"); + state->u.f4.fld.ccr.duty = cm_object_get_child_by_name(state->u.f4.reg.ccr, "DUTY"); + state->u.f4.fld.ccr.f_s = cm_object_get_child_by_name(state->u.f4.reg.ccr, "F_S"); + + // TRISE bitfields. + state->u.f4.fld.trise.trise = cm_object_get_child_by_name(state->u.f4.reg.trise, "TRISE"); + + // FLTR bitfields. + state->u.f4.fld.fltr.dnf = cm_object_get_child_by_name(state->u.f4.reg.fltr, "DNF"); + state->u.f4.fld.fltr.anoff = cm_object_get_child_by_name(state->u.f4.reg.fltr, "ANOFF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_i2c_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_i2c_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_i2c_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_i2c_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32I2CState *state = STM32_I2C_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_i2c_is_enabled(Object *obj) +{ + STM32I2CState *state = STM32_I2C_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_i2c_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32I2CState *state = STM32_I2C_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_I2C_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_i2c_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_I2C)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32I2CState *state = STM32_I2C_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "I2C"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_i2c_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2c_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_i2c_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_i2c_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_i2c_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/I2C%dEN", + 1 + state->port_index - STM32_PORT_I2C1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_i2c_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_I2C); +} + +static void stm32_i2c_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_i2c_reset_callback; + dc->realize = stm32_i2c_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_i2c_is_enabled; +} + +static const TypeInfo stm32_i2c_type_info = { + .name = TYPE_STM32_I2C, + .parent = TYPE_STM32_I2C_PARENT, + .instance_init = stm32_i2c_instance_init_callback, + .instance_size = sizeof(STM32I2CState), + .class_init = stm32_i2c_class_init_callback, + .class_size = sizeof(STM32I2CClass) }; + +static void stm32_i2c_register_types(void) +{ + type_register_static(&stm32_i2c_type_info); +} + +type_init(stm32_i2c_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/i2c3.h b/gnu-mcu-eclipse/devices/support/STM32F429x/i2c3.h new file mode 100644 index 0000000000..e30a8d6f1a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/i2c3.h @@ -0,0 +1,216 @@ +/* + * STM32 - I2C (Inter-integrated circuit) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_I2C_H_ +#define STM32_I2C_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_I2C DEVICE_PATH_STM32 "I2C" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_I2C1, + STM32_PORT_I2C2, + STM32_PORT_I2C3, + STM32_PORT_I2C_UNDEFINED = 0xFF, +} stm32_i2c_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_I2C TYPE_STM32_PREFIX "i2c" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_I2C_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32I2CParentClass; +typedef PeripheralState STM32I2CParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_I2C_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32I2CClass, (obj), TYPE_STM32_I2C) +#define STM32_I2C_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32I2CClass, (klass), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentClass parent_class; + // public: + + // None, so far. +} STM32I2CClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_I2C_STATE(obj) \ + OBJECT_CHECK(STM32I2CState, (obj), TYPE_STM32_I2C) + +typedef struct { + // private: + STM32I2CParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_i2c_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 I2C (Inter-integrated circuit) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *oar1; // 0x8 (Own address register 1) + Object *oar2; // 0xC (Own address register 2) + Object *dr; // 0x10 (Data register) + Object *sr1; // 0x14 (Status register 1) + Object *sr2; // 0x18 (Status register 2) + Object *ccr; // 0x1C (Clock control register) + Object *trise; // 0x20 (TRISE register) + Object *fltr; // 0x24 (I2C FLTR register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *pe; // [0:0] Peripheral enable + Object *smbus; // [1:1] SMBus mode + Object *smbtype; // [3:3] SMBus type + Object *enarp; // [4:4] ARP enable + Object *enpec; // [5:5] PEC enable + Object *engc; // [6:6] General call enable + Object *nostretch; // [7:7] Clock stretching disable (Slave mode) + Object *start; // [8:8] Start generation + Object *stop; // [9:9] Stop generation + Object *ack; // [10:10] Acknowledge enable + Object *pos; // [11:11] Acknowledge/PEC Position (for data reception) + Object *pec; // [12:12] Packet error checking + Object *alert; // [13:13] SMBus alert + Object *swrst; // [15:15] Software reset + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *freq; // [0:5] Peripheral clock frequency + Object *iterren; // [8:8] Error interrupt enable + Object *itevten; // [9:9] Event interrupt enable + Object *itbufen; // [10:10] Buffer interrupt enable + Object *dmaen; // [11:11] DMA requests enable + Object *last; // [12:12] DMA last transfer + } cr2; + + // OAR1 (Own address register 1) bitfields. + struct { + Object *add0; // [0:0] Interface address + Object *add7; // [1:7] Interface address + Object *add10; // [8:9] Interface address + Object *addmode; // [15:15] Addressing mode (slave mode) + } oar1; + + // OAR2 (Own address register 2) bitfields. + struct { + Object *endual; // [0:0] Dual addressing mode enable + Object *add2; // [1:7] Interface address + } oar2; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:7] 8-bit data register + } dr; + + // SR1 (Status register 1) bitfields. + struct { + Object *sb; // [0:0] Start bit (Master mode) + Object *addr; // [1:1] Address sent (master mode)/matched (slave mode) + Object *btf; // [2:2] Byte transfer finished + Object *add10; // [3:3] 10-bit header sent (Master mode) + Object *stopf; // [4:4] Stop detection (slave mode) + Object *rxne; // [6:6] Data register not empty (receivers) + Object *txe; // [7:7] Data register empty (transmitters) + Object *berr; // [8:8] Bus error + Object *arlo; // [9:9] Arbitration lost (master mode) + Object *af; // [10:10] Acknowledge failure + Object *ovr; // [11:11] Overrun/Underrun + Object *pecerr; // [12:12] PEC Error in reception + Object *timeout; // [14:14] Timeout or Tlow error + Object *smbalert; // [15:15] SMBus alert + } sr1; + + // SR2 (Status register 2) bitfields. + struct { + Object *msl; // [0:0] Master/slave + Object *busy; // [1:1] Bus busy + Object *tra; // [2:2] Transmitter/receiver + Object *gencall; // [4:4] General call address (Slave mode) + Object *smbdefault; // [5:5] SMBus device default address (Slave mode) + Object *smbhost; // [6:6] SMBus host header (Slave mode) + Object *dualf; // [7:7] Dual flag (Slave mode) + Object *pec; // [8:15] Acket error checking register + } sr2; + + // CCR (Clock control register) bitfields. + struct { + Object *ccr; // [0:11] Clock control register in Fast/Standard mode (Master mode) + Object *duty; // [14:14] Fast mode duty cycle + Object *f_s; // [15:15] I2C master mode selection + } ccr; + + // TRISE (TRISE register) bitfields. + struct { + Object *trise; // [0:5] Maximum rise time in Fast/Standard mode (Master mode) + } trise; + + // FLTR (I2C FLTR register) bitfields. + struct { + Object *dnf; // [0:3] Digital noise filter + Object *anoff; // [4:4] Analog noise filter OFF + } fltr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32I2CState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_I2C_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/iwdg.c b/gnu-mcu-eclipse/devices/support/STM32F429x/iwdg.c new file mode 100644 index 0000000000..85ef654f6b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/iwdg.c @@ -0,0 +1,251 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_iwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.kr = cm_object_get_child_by_name(obj, "KR"); + state->u.f4.reg.pr = cm_object_get_child_by_name(obj, "PR"); + state->u.f4.reg.rlr = cm_object_get_child_by_name(obj, "RLR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // KR bitfields. + state->u.f4.fld.kr.key = cm_object_get_child_by_name(state->u.f4.reg.kr, "KEY"); + + // PR bitfields. + state->u.f4.fld.pr.pr = cm_object_get_child_by_name(state->u.f4.reg.pr, "PR"); + + // RLR bitfields. + state->u.f4.fld.rlr.rl = cm_object_get_child_by_name(state->u.f4.reg.rlr, "RL"); + + // SR bitfields. + state->u.f4.fld.sr.pvu = cm_object_get_child_by_name(state->u.f4.reg.sr, "PVU"); + state->u.f4.fld.sr.rvu = cm_object_get_child_by_name(state->u.f4.reg.sr, "RVU"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_iwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_iwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_iwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_iwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32IWDGState *state = STM32_IWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_iwdg_is_enabled(Object *obj) +{ + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_iwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32IWDGState *state = STM32_IWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_iwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_IWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32IWDGState *state = STM32_IWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "IWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_iwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_iwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_iwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_iwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_iwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/IWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_iwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_IWDG); +} + +static void stm32_iwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_iwdg_reset_callback; + dc->realize = stm32_iwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_iwdg_is_enabled; +} + +static const TypeInfo stm32_iwdg_type_info = { + .name = TYPE_STM32_IWDG, + .parent = TYPE_STM32_IWDG_PARENT, + .instance_init = stm32_iwdg_instance_init_callback, + .instance_size = sizeof(STM32IWDGState), + .class_init = stm32_iwdg_class_init_callback, + .class_size = sizeof(STM32IWDGClass) }; + +static void stm32_iwdg_register_types(void) +{ + type_register_static(&stm32_iwdg_type_info); +} + +type_init(stm32_iwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/iwdg.h b/gnu-mcu-eclipse/devices/support/STM32F429x/iwdg.h new file mode 100644 index 0000000000..76247aafbe --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/iwdg.h @@ -0,0 +1,124 @@ +/* + * STM32 - IWDG (Independent watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_IWDG_H_ +#define STM32_IWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_IWDG DEVICE_PATH_STM32 "IWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_IWDG TYPE_STM32_PREFIX "iwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_IWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32IWDGParentClass; +typedef PeripheralState STM32IWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_IWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32IWDGClass, (obj), TYPE_STM32_IWDG) +#define STM32_IWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32IWDGClass, (klass), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentClass parent_class; + // public: + + // None, so far. +} STM32IWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_IWDG_STATE(obj) \ + OBJECT_CHECK(STM32IWDGState, (obj), TYPE_STM32_IWDG) + +typedef struct { + // private: + STM32IWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 IWDG (Independent watchdog) registers. + struct { + Object *kr; // 0x0 (Key register) + Object *pr; // 0x4 (Prescaler register) + Object *rlr; // 0x8 (Reload register) + Object *sr; // 0xC (Status register) + } reg; + + struct { + + // KR (Key register) bitfields. + struct { + Object *key; // [0:15] Key value (write only, read 0000h) + } kr; + + // PR (Prescaler register) bitfields. + struct { + Object *pr; // [0:2] Prescaler divider + } pr; + + // RLR (Reload register) bitfields. + struct { + Object *rl; // [0:11] Watchdog counter reload value + } rlr; + + // SR (Status register) bitfields. + struct { + Object *pvu; // [0:0] Watchdog prescaler value update + Object *rvu; // [1:1] Watchdog counter reload value update + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32IWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_IWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ltdc.c b/gnu-mcu-eclipse/devices/support/STM32F429x/ltdc.c new file mode 100644 index 0000000000..c810a69d40 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ltdc.c @@ -0,0 +1,436 @@ +/* + * STM32 - LTDC (LCD-TFT Controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_ltdc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32LTDCState *state = STM32_LTDC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sscr = cm_object_get_child_by_name(obj, "SSCR"); + state->u.f4.reg.bpcr = cm_object_get_child_by_name(obj, "BPCR"); + state->u.f4.reg.awcr = cm_object_get_child_by_name(obj, "AWCR"); + state->u.f4.reg.twcr = cm_object_get_child_by_name(obj, "TWCR"); + state->u.f4.reg.gcr = cm_object_get_child_by_name(obj, "GCR"); + state->u.f4.reg.srcr = cm_object_get_child_by_name(obj, "SRCR"); + state->u.f4.reg.bccr = cm_object_get_child_by_name(obj, "BCCR"); + state->u.f4.reg.ier = cm_object_get_child_by_name(obj, "IER"); + state->u.f4.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f4.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f4.reg.lipcr = cm_object_get_child_by_name(obj, "LIPCR"); + state->u.f4.reg.cpsr = cm_object_get_child_by_name(obj, "CPSR"); + state->u.f4.reg.cdsr = cm_object_get_child_by_name(obj, "CDSR"); + state->u.f4.reg.l1cr = cm_object_get_child_by_name(obj, "L1CR"); + state->u.f4.reg.l1whpcr = cm_object_get_child_by_name(obj, "L1WHPCR"); + state->u.f4.reg.l1wvpcr = cm_object_get_child_by_name(obj, "L1WVPCR"); + state->u.f4.reg.l1ckcr = cm_object_get_child_by_name(obj, "L1CKCR"); + state->u.f4.reg.l1pfcr = cm_object_get_child_by_name(obj, "L1PFCR"); + state->u.f4.reg.l1cacr = cm_object_get_child_by_name(obj, "L1CACR"); + state->u.f4.reg.l1dccr = cm_object_get_child_by_name(obj, "L1DCCR"); + state->u.f4.reg.l1bfcr = cm_object_get_child_by_name(obj, "L1BFCR"); + state->u.f4.reg.l1cfbar = cm_object_get_child_by_name(obj, "L1CFBAR"); + state->u.f4.reg.l1cfblr = cm_object_get_child_by_name(obj, "L1CFBLR"); + state->u.f4.reg.l1cfblnr = cm_object_get_child_by_name(obj, "L1CFBLNR"); + state->u.f4.reg.l1clutwr = cm_object_get_child_by_name(obj, "L1CLUTWR"); + state->u.f4.reg.l2cr = cm_object_get_child_by_name(obj, "L2CR"); + state->u.f4.reg.l2whpcr = cm_object_get_child_by_name(obj, "L2WHPCR"); + state->u.f4.reg.l2wvpcr = cm_object_get_child_by_name(obj, "L2WVPCR"); + state->u.f4.reg.l2ckcr = cm_object_get_child_by_name(obj, "L2CKCR"); + state->u.f4.reg.l2pfcr = cm_object_get_child_by_name(obj, "L2PFCR"); + state->u.f4.reg.l2cacr = cm_object_get_child_by_name(obj, "L2CACR"); + state->u.f4.reg.l2dccr = cm_object_get_child_by_name(obj, "L2DCCR"); + state->u.f4.reg.l2bfcr = cm_object_get_child_by_name(obj, "L2BFCR"); + state->u.f4.reg.l2cfbar = cm_object_get_child_by_name(obj, "L2CFBAR"); + state->u.f4.reg.l2cfblr = cm_object_get_child_by_name(obj, "L2CFBLR"); + state->u.f4.reg.l2cfblnr = cm_object_get_child_by_name(obj, "L2CFBLNR"); + state->u.f4.reg.l2clutwr = cm_object_get_child_by_name(obj, "L2CLUTWR"); + + + // SSCR bitfields. + state->u.f4.fld.sscr.vsh = cm_object_get_child_by_name(state->u.f4.reg.sscr, "VSH"); + state->u.f4.fld.sscr.hsw = cm_object_get_child_by_name(state->u.f4.reg.sscr, "HSW"); + + // BPCR bitfields. + state->u.f4.fld.bpcr.avbp = cm_object_get_child_by_name(state->u.f4.reg.bpcr, "AVBP"); + state->u.f4.fld.bpcr.ahbp = cm_object_get_child_by_name(state->u.f4.reg.bpcr, "AHBP"); + + // AWCR bitfields. + state->u.f4.fld.awcr.aah = cm_object_get_child_by_name(state->u.f4.reg.awcr, "AAH"); + state->u.f4.fld.awcr.aaw = cm_object_get_child_by_name(state->u.f4.reg.awcr, "AAW"); + + // TWCR bitfields. + state->u.f4.fld.twcr.totalh = cm_object_get_child_by_name(state->u.f4.reg.twcr, "TOTALH"); + state->u.f4.fld.twcr.totalw = cm_object_get_child_by_name(state->u.f4.reg.twcr, "TOTALW"); + + // GCR bitfields. + state->u.f4.fld.gcr.ltdcen = cm_object_get_child_by_name(state->u.f4.reg.gcr, "LTDCEN"); + state->u.f4.fld.gcr.dbw = cm_object_get_child_by_name(state->u.f4.reg.gcr, "DBW"); + state->u.f4.fld.gcr.dgw = cm_object_get_child_by_name(state->u.f4.reg.gcr, "DGW"); + state->u.f4.fld.gcr.drw = cm_object_get_child_by_name(state->u.f4.reg.gcr, "DRW"); + state->u.f4.fld.gcr.den = cm_object_get_child_by_name(state->u.f4.reg.gcr, "DEN"); + state->u.f4.fld.gcr.pcpol = cm_object_get_child_by_name(state->u.f4.reg.gcr, "PCPOL"); + state->u.f4.fld.gcr.depol = cm_object_get_child_by_name(state->u.f4.reg.gcr, "DEPOL"); + state->u.f4.fld.gcr.vspol = cm_object_get_child_by_name(state->u.f4.reg.gcr, "VSPOL"); + state->u.f4.fld.gcr.hspol = cm_object_get_child_by_name(state->u.f4.reg.gcr, "HSPOL"); + + // SRCR bitfields. + state->u.f4.fld.srcr.imr = cm_object_get_child_by_name(state->u.f4.reg.srcr, "IMR"); + state->u.f4.fld.srcr.vbr = cm_object_get_child_by_name(state->u.f4.reg.srcr, "VBR"); + + // BCCR bitfields. + state->u.f4.fld.bccr.bc = cm_object_get_child_by_name(state->u.f4.reg.bccr, "BC"); + + // IER bitfields. + state->u.f4.fld.ier.lie = cm_object_get_child_by_name(state->u.f4.reg.ier, "LIE"); + state->u.f4.fld.ier.fuie = cm_object_get_child_by_name(state->u.f4.reg.ier, "FUIE"); + state->u.f4.fld.ier.terrie = cm_object_get_child_by_name(state->u.f4.reg.ier, "TERRIE"); + state->u.f4.fld.ier.rrie = cm_object_get_child_by_name(state->u.f4.reg.ier, "RRIE"); + + // ISR bitfields. + state->u.f4.fld.isr.lif = cm_object_get_child_by_name(state->u.f4.reg.isr, "LIF"); + state->u.f4.fld.isr.fuif = cm_object_get_child_by_name(state->u.f4.reg.isr, "FUIF"); + state->u.f4.fld.isr.terrif = cm_object_get_child_by_name(state->u.f4.reg.isr, "TERRIF"); + state->u.f4.fld.isr.rrif = cm_object_get_child_by_name(state->u.f4.reg.isr, "RRIF"); + + // ICR bitfields. + state->u.f4.fld.icr.clif = cm_object_get_child_by_name(state->u.f4.reg.icr, "CLIF"); + state->u.f4.fld.icr.cfuif = cm_object_get_child_by_name(state->u.f4.reg.icr, "CFUIF"); + state->u.f4.fld.icr.cterrif = cm_object_get_child_by_name(state->u.f4.reg.icr, "CTERRIF"); + state->u.f4.fld.icr.crrif = cm_object_get_child_by_name(state->u.f4.reg.icr, "CRRIF"); + + // LIPCR bitfields. + state->u.f4.fld.lipcr.lipos = cm_object_get_child_by_name(state->u.f4.reg.lipcr, "LIPOS"); + + // CPSR bitfields. + state->u.f4.fld.cpsr.cypos = cm_object_get_child_by_name(state->u.f4.reg.cpsr, "CYPOS"); + state->u.f4.fld.cpsr.cxpos = cm_object_get_child_by_name(state->u.f4.reg.cpsr, "CXPOS"); + + // CDSR bitfields. + state->u.f4.fld.cdsr.vdes = cm_object_get_child_by_name(state->u.f4.reg.cdsr, "VDES"); + state->u.f4.fld.cdsr.hdes = cm_object_get_child_by_name(state->u.f4.reg.cdsr, "HDES"); + state->u.f4.fld.cdsr.vsyncs = cm_object_get_child_by_name(state->u.f4.reg.cdsr, "VSYNCS"); + state->u.f4.fld.cdsr.hsyncs = cm_object_get_child_by_name(state->u.f4.reg.cdsr, "HSYNCS"); + + // L1CR bitfields. + state->u.f4.fld.l1cr.len = cm_object_get_child_by_name(state->u.f4.reg.l1cr, "LEN"); + state->u.f4.fld.l1cr.colken = cm_object_get_child_by_name(state->u.f4.reg.l1cr, "COLKEN"); + state->u.f4.fld.l1cr.cluten = cm_object_get_child_by_name(state->u.f4.reg.l1cr, "CLUTEN"); + + // L1WHPCR bitfields. + state->u.f4.fld.l1whpcr.whstpos = cm_object_get_child_by_name(state->u.f4.reg.l1whpcr, "WHSTPOS"); + state->u.f4.fld.l1whpcr.whsppos = cm_object_get_child_by_name(state->u.f4.reg.l1whpcr, "WHSPPOS"); + + // L1WVPCR bitfields. + state->u.f4.fld.l1wvpcr.wvstpos = cm_object_get_child_by_name(state->u.f4.reg.l1wvpcr, "WVSTPOS"); + state->u.f4.fld.l1wvpcr.wvsppos = cm_object_get_child_by_name(state->u.f4.reg.l1wvpcr, "WVSPPOS"); + + // L1CKCR bitfields. + state->u.f4.fld.l1ckcr.ckblue = cm_object_get_child_by_name(state->u.f4.reg.l1ckcr, "CKBLUE"); + state->u.f4.fld.l1ckcr.ckgreen = cm_object_get_child_by_name(state->u.f4.reg.l1ckcr, "CKGREEN"); + state->u.f4.fld.l1ckcr.ckred = cm_object_get_child_by_name(state->u.f4.reg.l1ckcr, "CKRED"); + + // L1PFCR bitfields. + state->u.f4.fld.l1pfcr.pf = cm_object_get_child_by_name(state->u.f4.reg.l1pfcr, "PF"); + + // L1CACR bitfields. + state->u.f4.fld.l1cacr.consta = cm_object_get_child_by_name(state->u.f4.reg.l1cacr, "CONSTA"); + + // L1DCCR bitfields. + state->u.f4.fld.l1dccr.dcblue = cm_object_get_child_by_name(state->u.f4.reg.l1dccr, "DCBLUE"); + state->u.f4.fld.l1dccr.dcgreen = cm_object_get_child_by_name(state->u.f4.reg.l1dccr, "DCGREEN"); + state->u.f4.fld.l1dccr.dcred = cm_object_get_child_by_name(state->u.f4.reg.l1dccr, "DCRED"); + state->u.f4.fld.l1dccr.dcalpha = cm_object_get_child_by_name(state->u.f4.reg.l1dccr, "DCALPHA"); + + // L1BFCR bitfields. + state->u.f4.fld.l1bfcr.bf2 = cm_object_get_child_by_name(state->u.f4.reg.l1bfcr, "BF2"); + state->u.f4.fld.l1bfcr.bf1 = cm_object_get_child_by_name(state->u.f4.reg.l1bfcr, "BF1"); + + // L1CFBAR bitfields. + state->u.f4.fld.l1cfbar.cfbadd = cm_object_get_child_by_name(state->u.f4.reg.l1cfbar, "CFBADD"); + + // L1CFBLR bitfields. + state->u.f4.fld.l1cfblr.cfbll = cm_object_get_child_by_name(state->u.f4.reg.l1cfblr, "CFBLL"); + state->u.f4.fld.l1cfblr.cfbp = cm_object_get_child_by_name(state->u.f4.reg.l1cfblr, "CFBP"); + + // L1CFBLNR bitfields. + state->u.f4.fld.l1cfblnr.cfblnbr = cm_object_get_child_by_name(state->u.f4.reg.l1cfblnr, "CFBLNBR"); + + // L1CLUTWR bitfields. + state->u.f4.fld.l1clutwr.blue = cm_object_get_child_by_name(state->u.f4.reg.l1clutwr, "BLUE"); + state->u.f4.fld.l1clutwr.green = cm_object_get_child_by_name(state->u.f4.reg.l1clutwr, "GREEN"); + state->u.f4.fld.l1clutwr.red = cm_object_get_child_by_name(state->u.f4.reg.l1clutwr, "RED"); + state->u.f4.fld.l1clutwr.clutadd = cm_object_get_child_by_name(state->u.f4.reg.l1clutwr, "CLUTADD"); + + // L2CR bitfields. + state->u.f4.fld.l2cr.len = cm_object_get_child_by_name(state->u.f4.reg.l2cr, "LEN"); + state->u.f4.fld.l2cr.colken = cm_object_get_child_by_name(state->u.f4.reg.l2cr, "COLKEN"); + state->u.f4.fld.l2cr.cluten = cm_object_get_child_by_name(state->u.f4.reg.l2cr, "CLUTEN"); + + // L2WHPCR bitfields. + state->u.f4.fld.l2whpcr.whstpos = cm_object_get_child_by_name(state->u.f4.reg.l2whpcr, "WHSTPOS"); + state->u.f4.fld.l2whpcr.whsppos = cm_object_get_child_by_name(state->u.f4.reg.l2whpcr, "WHSPPOS"); + + // L2WVPCR bitfields. + state->u.f4.fld.l2wvpcr.wvstpos = cm_object_get_child_by_name(state->u.f4.reg.l2wvpcr, "WVSTPOS"); + state->u.f4.fld.l2wvpcr.wvsppos = cm_object_get_child_by_name(state->u.f4.reg.l2wvpcr, "WVSPPOS"); + + // L2CKCR bitfields. + state->u.f4.fld.l2ckcr.ckblue = cm_object_get_child_by_name(state->u.f4.reg.l2ckcr, "CKBLUE"); + state->u.f4.fld.l2ckcr.ckgreen = cm_object_get_child_by_name(state->u.f4.reg.l2ckcr, "CKGREEN"); + state->u.f4.fld.l2ckcr.ckred = cm_object_get_child_by_name(state->u.f4.reg.l2ckcr, "CKRED"); + + // L2PFCR bitfields. + state->u.f4.fld.l2pfcr.pf = cm_object_get_child_by_name(state->u.f4.reg.l2pfcr, "PF"); + + // L2CACR bitfields. + state->u.f4.fld.l2cacr.consta = cm_object_get_child_by_name(state->u.f4.reg.l2cacr, "CONSTA"); + + // L2DCCR bitfields. + state->u.f4.fld.l2dccr.dcblue = cm_object_get_child_by_name(state->u.f4.reg.l2dccr, "DCBLUE"); + state->u.f4.fld.l2dccr.dcgreen = cm_object_get_child_by_name(state->u.f4.reg.l2dccr, "DCGREEN"); + state->u.f4.fld.l2dccr.dcred = cm_object_get_child_by_name(state->u.f4.reg.l2dccr, "DCRED"); + state->u.f4.fld.l2dccr.dcalpha = cm_object_get_child_by_name(state->u.f4.reg.l2dccr, "DCALPHA"); + + // L2BFCR bitfields. + state->u.f4.fld.l2bfcr.bf2 = cm_object_get_child_by_name(state->u.f4.reg.l2bfcr, "BF2"); + state->u.f4.fld.l2bfcr.bf1 = cm_object_get_child_by_name(state->u.f4.reg.l2bfcr, "BF1"); + + // L2CFBAR bitfields. + state->u.f4.fld.l2cfbar.cfbadd = cm_object_get_child_by_name(state->u.f4.reg.l2cfbar, "CFBADD"); + + // L2CFBLR bitfields. + state->u.f4.fld.l2cfblr.cfbll = cm_object_get_child_by_name(state->u.f4.reg.l2cfblr, "CFBLL"); + state->u.f4.fld.l2cfblr.cfbp = cm_object_get_child_by_name(state->u.f4.reg.l2cfblr, "CFBP"); + + // L2CFBLNR bitfields. + state->u.f4.fld.l2cfblnr.cfblnbr = cm_object_get_child_by_name(state->u.f4.reg.l2cfblnr, "CFBLNBR"); + + // L2CLUTWR bitfields. + state->u.f4.fld.l2clutwr.blue = cm_object_get_child_by_name(state->u.f4.reg.l2clutwr, "BLUE"); + state->u.f4.fld.l2clutwr.green = cm_object_get_child_by_name(state->u.f4.reg.l2clutwr, "GREEN"); + state->u.f4.fld.l2clutwr.red = cm_object_get_child_by_name(state->u.f4.reg.l2clutwr, "RED"); + state->u.f4.fld.l2clutwr.clutadd = cm_object_get_child_by_name(state->u.f4.reg.l2clutwr, "CLUTADD"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_ltdc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32LTDCState *state = STM32_LTDC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_ltdc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32LTDCState *state = STM32_LTDC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_ltdc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32LTDCState *state = STM32_LTDC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_ltdc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32LTDCState *state = STM32_LTDC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_ltdc_is_enabled(Object *obj) +{ + STM32LTDCState *state = STM32_LTDC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_ltdc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32LTDCState *state = STM32_LTDC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_ltdc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_LTDC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32LTDCState *state = STM32_LTDC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "LTDC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_ltdc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ltdc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_ltdc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_ltdc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_ltdc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/LTDCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_ltdc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_LTDC); +} + +static void stm32_ltdc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_ltdc_reset_callback; + dc->realize = stm32_ltdc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_ltdc_is_enabled; +} + +static const TypeInfo stm32_ltdc_type_info = { + .name = TYPE_STM32_LTDC, + .parent = TYPE_STM32_LTDC_PARENT, + .instance_init = stm32_ltdc_instance_init_callback, + .instance_size = sizeof(STM32LTDCState), + .class_init = stm32_ltdc_class_init_callback, + .class_size = sizeof(STM32LTDCClass) }; + +static void stm32_ltdc_register_types(void) +{ + type_register_static(&stm32_ltdc_type_info); +} + +type_init(stm32_ltdc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/ltdc.h b/gnu-mcu-eclipse/devices/support/STM32F429x/ltdc.h new file mode 100644 index 0000000000..c775c91d3b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/ltdc.h @@ -0,0 +1,375 @@ +/* + * STM32 - LTDC (LCD-TFT Controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_LTDC_H_ +#define STM32_LTDC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_LTDC DEVICE_PATH_STM32 "LTDC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_LTDC TYPE_STM32_PREFIX "ltdc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_LTDC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32LTDCParentClass; +typedef PeripheralState STM32LTDCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_LTDC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32LTDCClass, (obj), TYPE_STM32_LTDC) +#define STM32_LTDC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32LTDCClass, (klass), TYPE_STM32_LTDC) + +typedef struct { + // private: + STM32LTDCParentClass parent_class; + // public: + + // None, so far. +} STM32LTDCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_LTDC_STATE(obj) \ + OBJECT_CHECK(STM32LTDCState, (obj), TYPE_STM32_LTDC) + +typedef struct { + // private: + STM32LTDCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 LTDC (LCD-TFT Controller) registers. + struct { + Object *sscr; // 0x8 (Synchronization Size Configuration Register) + Object *bpcr; // 0xC (Back Porch Configuration Register) + Object *awcr; // 0x10 (Active Width Configuration Register) + Object *twcr; // 0x14 (Total Width Configuration Register) + Object *gcr; // 0x18 (Global Control Register) + Object *srcr; // 0x24 (Shadow Reload Configuration Register) + Object *bccr; // 0x2C (Background Color Configuration Register) + Object *ier; // 0x34 (Interrupt Enable Register) + Object *isr; // 0x38 (Interrupt Status Register) + Object *icr; // 0x3C (Interrupt Clear Register) + Object *lipcr; // 0x40 (Line Interrupt Position Configuration Register) + Object *cpsr; // 0x44 (Current Position Status Register) + Object *cdsr; // 0x48 (Current Display Status Register) + Object *l1cr; // 0x84 (Layerx Control Register) + Object *l1whpcr; // 0x88 (Layerx Window Horizontal Position Configuration Register) + Object *l1wvpcr; // 0x8C (Layerx Window Vertical Position Configuration Register) + Object *l1ckcr; // 0x90 (Layerx Color Keying Configuration Register) + Object *l1pfcr; // 0x94 (Layerx Pixel Format Configuration Register) + Object *l1cacr; // 0x98 (Layerx Constant Alpha Configuration Register) + Object *l1dccr; // 0x9C (Layerx Default Color Configuration Register) + Object *l1bfcr; // 0xA0 (Layerx Blending Factors Configuration Register) + Object *l1cfbar; // 0xAC (Layerx Color Frame Buffer Address Register) + Object *l1cfblr; // 0xB0 (Layerx Color Frame Buffer Length Register) + Object *l1cfblnr; // 0xB4 (Layerx ColorFrame Buffer Line Number Register) + Object *l1clutwr; // 0xC4 (Layerx CLUT Write Register) + Object *l2cr; // 0x104 (Layerx Control Register) + Object *l2whpcr; // 0x108 (Layerx Window Horizontal Position Configuration Register) + Object *l2wvpcr; // 0x10C (Layerx Window Vertical Position Configuration Register) + Object *l2ckcr; // 0x110 (Layerx Color Keying Configuration Register) + Object *l2pfcr; // 0x114 (Layerx Pixel Format Configuration Register) + Object *l2cacr; // 0x118 (Layerx Constant Alpha Configuration Register) + Object *l2dccr; // 0x11C (Layerx Default Color Configuration Register) + Object *l2bfcr; // 0x120 (Layerx Blending Factors Configuration Register) + Object *l2cfbar; // 0x12C (Layerx Color Frame Buffer Address Register) + Object *l2cfblr; // 0x130 (Layerx Color Frame Buffer Length Register) + Object *l2cfblnr; // 0x134 (Layerx ColorFrame Buffer Line Number Register) + Object *l2clutwr; // 0x144 (Layerx CLUT Write Register) + } reg; + + struct { + + // SSCR (Synchronization Size Configuration Register) bitfields. + struct { + Object *vsh; // [0:10] Vertical Synchronization Height (in units of horizontal scan line) + Object *hsw; // [16:27] Horizontal Synchronization Width (in units of pixel clock period) + } sscr; + + // BPCR (Back Porch Configuration Register) bitfields. + struct { + Object *avbp; // [0:10] Accumulated Vertical back porch (in units of horizontal scan line) + Object *ahbp; // [16:27] Accumulated Horizontal back porch (in units of pixel clock period) + } bpcr; + + // AWCR (Active Width Configuration Register) bitfields. + struct { + Object *aah; // [0:10] Accumulated Active Height (in units of horizontal scan line) + Object *aaw; // [16:27] Accumulated Active Width (in units of pixel clock period) + } awcr; + + // TWCR (Total Width Configuration Register) bitfields. + struct { + Object *totalh; // [0:10] Total Height (in units of horizontal scan line) + Object *totalw; // [16:27] Total Width (in units of pixel clock period) + } twcr; + + // GCR (Global Control Register) bitfields. + struct { + Object *ltdcen; // [0:0] LCD-TFT controller enable bit + Object *dbw; // [4:6] Dither Blue Width + Object *dgw; // [8:10] Dither Green Width + Object *drw; // [12:14] Dither Red Width + Object *den; // [16:16] Dither Enable + Object *pcpol; // [28:28] Pixel Clock Polarity + Object *depol; // [29:29] Data Enable Polarity + Object *vspol; // [30:30] Vertical Synchronization Polarity + Object *hspol; // [31:31] Horizontal Synchronization Polarity + } gcr; + + // SRCR (Shadow Reload Configuration Register) bitfields. + struct { + Object *imr; // [0:0] Immediate Reload + Object *vbr; // [1:1] Vertical Blanking Reload + } srcr; + + // BCCR (Background Color Configuration Register) bitfields. + struct { + Object *bc; // [0:23] Background Color Red value + } bccr; + + // IER (Interrupt Enable Register) bitfields. + struct { + Object *lie; // [0:0] Line Interrupt Enable + Object *fuie; // [1:1] FIFO Underrun Interrupt Enable + Object *terrie; // [2:2] Transfer Error Interrupt Enable + Object *rrie; // [3:3] Register Reload interrupt enable + } ier; + + // ISR (Interrupt Status Register) bitfields. + struct { + Object *lif; // [0:0] Line Interrupt flag + Object *fuif; // [1:1] FIFO Underrun Interrupt flag + Object *terrif; // [2:2] Transfer Error interrupt flag + Object *rrif; // [3:3] Register Reload Interrupt Flag + } isr; + + // ICR (Interrupt Clear Register) bitfields. + struct { + Object *clif; // [0:0] Clears the Line Interrupt Flag + Object *cfuif; // [1:1] Clears the FIFO Underrun Interrupt flag + Object *cterrif; // [2:2] Clears the Transfer Error Interrupt Flag + Object *crrif; // [3:3] Clears Register Reload Interrupt Flag + } icr; + + // LIPCR (Line Interrupt Position Configuration Register) bitfields. + struct { + Object *lipos; // [0:10] Line Interrupt Position + } lipcr; + + // CPSR (Current Position Status Register) bitfields. + struct { + Object *cypos; // [0:15] Current Y Position + Object *cxpos; // [16:31] Current X Position + } cpsr; + + // CDSR (Current Display Status Register) bitfields. + struct { + Object *vdes; // [0:0] Vertical Data Enable display Status + Object *hdes; // [1:1] Horizontal Data Enable display Status + Object *vsyncs; // [2:2] Vertical Synchronization display Status + Object *hsyncs; // [3:3] Horizontal Synchronization display Status + } cdsr; + + // L1CR (Layerx Control Register) bitfields. + struct { + Object *len; // [0:0] Layer Enable + Object *colken; // [1:1] Color Keying Enable + Object *cluten; // [4:4] Color Look-Up Table Enable + } l1cr; + + // L1WHPCR (Layerx Window Horizontal Position Configuration Register) bitfields. + struct { + Object *whstpos; // [0:11] Window Horizontal Start Position + Object *whsppos; // [16:27] Window Horizontal Stop Position + } l1whpcr; + + // L1WVPCR (Layerx Window Vertical Position Configuration Register) bitfields. + struct { + Object *wvstpos; // [0:10] Window Vertical Start Position + Object *wvsppos; // [16:26] Window Vertical Stop Position + } l1wvpcr; + + // L1CKCR (Layerx Color Keying Configuration Register) bitfields. + struct { + Object *ckblue; // [0:7] Color Key Blue value + Object *ckgreen; // [8:15] Color Key Green value + Object *ckred; // [16:23] Color Key Red value + } l1ckcr; + + // L1PFCR (Layerx Pixel Format Configuration Register) bitfields. + struct { + Object *pf; // [0:2] Pixel Format + } l1pfcr; + + // L1CACR (Layerx Constant Alpha Configuration Register) bitfields. + struct { + Object *consta; // [0:7] Constant Alpha + } l1cacr; + + // L1DCCR (Layerx Default Color Configuration Register) bitfields. + struct { + Object *dcblue; // [0:7] Default Color Blue + Object *dcgreen; // [8:15] Default Color Green + Object *dcred; // [16:23] Default Color Red + Object *dcalpha; // [24:31] Default Color Alpha + } l1dccr; + + // L1BFCR (Layerx Blending Factors Configuration Register) bitfields. + struct { + Object *bf2; // [0:2] Blending Factor 2 + Object *bf1; // [8:10] Blending Factor 1 + } l1bfcr; + + // L1CFBAR (Layerx Color Frame Buffer Address Register) bitfields. + struct { + Object *cfbadd; // [0:31] Color Frame Buffer Start Address + } l1cfbar; + + // L1CFBLR (Layerx Color Frame Buffer Length Register) bitfields. + struct { + Object *cfbll; // [0:12] Color Frame Buffer Line Length + Object *cfbp; // [16:28] Color Frame Buffer Pitch in bytes + } l1cfblr; + + // L1CFBLNR (Layerx ColorFrame Buffer Line Number Register) bitfields. + struct { + Object *cfblnbr; // [0:10] Frame Buffer Line Number + } l1cfblnr; + + // L1CLUTWR (Layerx CLUT Write Register) bitfields. + struct { + Object *blue; // [0:7] Blue value + Object *green; // [8:15] Green value + Object *red; // [16:23] Red value + Object *clutadd; // [24:31] CLUT Address + } l1clutwr; + + // L2CR (Layerx Control Register) bitfields. + struct { + Object *len; // [0:0] Layer Enable + Object *colken; // [1:1] Color Keying Enable + Object *cluten; // [4:4] Color Look-Up Table Enable + } l2cr; + + // L2WHPCR (Layerx Window Horizontal Position Configuration Register) bitfields. + struct { + Object *whstpos; // [0:11] Window Horizontal Start Position + Object *whsppos; // [16:27] Window Horizontal Stop Position + } l2whpcr; + + // L2WVPCR (Layerx Window Vertical Position Configuration Register) bitfields. + struct { + Object *wvstpos; // [0:10] Window Vertical Start Position + Object *wvsppos; // [16:26] Window Vertical Stop Position + } l2wvpcr; + + // L2CKCR (Layerx Color Keying Configuration Register) bitfields. + struct { + Object *ckblue; // [0:7] Color Key Blue value + Object *ckgreen; // [8:14] Color Key Green value + Object *ckred; // [15:23] Color Key Red value + } l2ckcr; + + // L2PFCR (Layerx Pixel Format Configuration Register) bitfields. + struct { + Object *pf; // [0:2] Pixel Format + } l2pfcr; + + // L2CACR (Layerx Constant Alpha Configuration Register) bitfields. + struct { + Object *consta; // [0:7] Constant Alpha + } l2cacr; + + // L2DCCR (Layerx Default Color Configuration Register) bitfields. + struct { + Object *dcblue; // [0:7] Default Color Blue + Object *dcgreen; // [8:15] Default Color Green + Object *dcred; // [16:23] Default Color Red + Object *dcalpha; // [24:31] Default Color Alpha + } l2dccr; + + // L2BFCR (Layerx Blending Factors Configuration Register) bitfields. + struct { + Object *bf2; // [0:2] Blending Factor 2 + Object *bf1; // [8:10] Blending Factor 1 + } l2bfcr; + + // L2CFBAR (Layerx Color Frame Buffer Address Register) bitfields. + struct { + Object *cfbadd; // [0:31] Color Frame Buffer Start Address + } l2cfbar; + + // L2CFBLR (Layerx Color Frame Buffer Length Register) bitfields. + struct { + Object *cfbll; // [0:12] Color Frame Buffer Line Length + Object *cfbp; // [16:28] Color Frame Buffer Pitch in bytes + } l2cfblr; + + // L2CFBLNR (Layerx ColorFrame Buffer Line Number Register) bitfields. + struct { + Object *cfblnbr; // [0:10] Frame Buffer Line Number + } l2cfblnr; + + // L2CLUTWR (Layerx CLUT Write Register) bitfields. + struct { + Object *blue; // [0:7] Blue value + Object *green; // [8:15] Green value + Object *red; // [16:23] Red value + Object *clutadd; // [24:31] CLUT Address + } l2clutwr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32LTDCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_LTDC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/nvic.c b/gnu-mcu-eclipse/devices/support/STM32F429x/nvic.c new file mode 100644 index 0000000000..a7fc4afaed --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/nvic.c @@ -0,0 +1,449 @@ +/* + * STM32 - NVIC (Nested Vectored Interrupt Controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_nvic_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32NVICState *state = STM32_NVIC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.ictr = cm_object_get_child_by_name(obj, "ICTR"); + state->u.f4.reg.stir = cm_object_get_child_by_name(obj, "STIR"); + state->u.f4.reg.iser0 = cm_object_get_child_by_name(obj, "ISER0"); + state->u.f4.reg.iser1 = cm_object_get_child_by_name(obj, "ISER1"); + state->u.f4.reg.iser2 = cm_object_get_child_by_name(obj, "ISER2"); + state->u.f4.reg.icer0 = cm_object_get_child_by_name(obj, "ICER0"); + state->u.f4.reg.icer1 = cm_object_get_child_by_name(obj, "ICER1"); + state->u.f4.reg.icer2 = cm_object_get_child_by_name(obj, "ICER2"); + state->u.f4.reg.ispr0 = cm_object_get_child_by_name(obj, "ISPR0"); + state->u.f4.reg.ispr1 = cm_object_get_child_by_name(obj, "ISPR1"); + state->u.f4.reg.ispr2 = cm_object_get_child_by_name(obj, "ISPR2"); + state->u.f4.reg.icpr0 = cm_object_get_child_by_name(obj, "ICPR0"); + state->u.f4.reg.icpr1 = cm_object_get_child_by_name(obj, "ICPR1"); + state->u.f4.reg.icpr2 = cm_object_get_child_by_name(obj, "ICPR2"); + state->u.f4.reg.iabr0 = cm_object_get_child_by_name(obj, "IABR0"); + state->u.f4.reg.iabr1 = cm_object_get_child_by_name(obj, "IABR1"); + state->u.f4.reg.iabr2 = cm_object_get_child_by_name(obj, "IABR2"); + state->u.f4.reg.ipr0 = cm_object_get_child_by_name(obj, "IPR0"); + state->u.f4.reg.ipr1 = cm_object_get_child_by_name(obj, "IPR1"); + state->u.f4.reg.ipr2 = cm_object_get_child_by_name(obj, "IPR2"); + state->u.f4.reg.ipr3 = cm_object_get_child_by_name(obj, "IPR3"); + state->u.f4.reg.ipr4 = cm_object_get_child_by_name(obj, "IPR4"); + state->u.f4.reg.ipr5 = cm_object_get_child_by_name(obj, "IPR5"); + state->u.f4.reg.ipr6 = cm_object_get_child_by_name(obj, "IPR6"); + state->u.f4.reg.ipr7 = cm_object_get_child_by_name(obj, "IPR7"); + state->u.f4.reg.ipr8 = cm_object_get_child_by_name(obj, "IPR8"); + state->u.f4.reg.ipr9 = cm_object_get_child_by_name(obj, "IPR9"); + state->u.f4.reg.ipr10 = cm_object_get_child_by_name(obj, "IPR10"); + state->u.f4.reg.ipr11 = cm_object_get_child_by_name(obj, "IPR11"); + state->u.f4.reg.ipr12 = cm_object_get_child_by_name(obj, "IPR12"); + state->u.f4.reg.ipr13 = cm_object_get_child_by_name(obj, "IPR13"); + state->u.f4.reg.ipr14 = cm_object_get_child_by_name(obj, "IPR14"); + state->u.f4.reg.ipr15 = cm_object_get_child_by_name(obj, "IPR15"); + state->u.f4.reg.ipr16 = cm_object_get_child_by_name(obj, "IPR16"); + state->u.f4.reg.ipr17 = cm_object_get_child_by_name(obj, "IPR17"); + state->u.f4.reg.ipr18 = cm_object_get_child_by_name(obj, "IPR18"); + state->u.f4.reg.ipr19 = cm_object_get_child_by_name(obj, "IPR19"); + state->u.f4.reg.ipr20 = cm_object_get_child_by_name(obj, "IPR20"); + + + // ICTR bitfields. + state->u.f4.fld.ictr.intlinesnum = cm_object_get_child_by_name(state->u.f4.reg.ictr, "INTLINESNUM"); + + // STIR bitfields. + state->u.f4.fld.stir.intid = cm_object_get_child_by_name(state->u.f4.reg.stir, "INTID"); + + // ISER0 bitfields. + state->u.f4.fld.iser0.setena = cm_object_get_child_by_name(state->u.f4.reg.iser0, "SETENA"); + + // ISER1 bitfields. + state->u.f4.fld.iser1.setena = cm_object_get_child_by_name(state->u.f4.reg.iser1, "SETENA"); + + // ISER2 bitfields. + state->u.f4.fld.iser2.setena = cm_object_get_child_by_name(state->u.f4.reg.iser2, "SETENA"); + + // ICER0 bitfields. + state->u.f4.fld.icer0.clrena = cm_object_get_child_by_name(state->u.f4.reg.icer0, "CLRENA"); + + // ICER1 bitfields. + state->u.f4.fld.icer1.clrena = cm_object_get_child_by_name(state->u.f4.reg.icer1, "CLRENA"); + + // ICER2 bitfields. + state->u.f4.fld.icer2.clrena = cm_object_get_child_by_name(state->u.f4.reg.icer2, "CLRENA"); + + // ISPR0 bitfields. + state->u.f4.fld.ispr0.setpend = cm_object_get_child_by_name(state->u.f4.reg.ispr0, "SETPEND"); + + // ISPR1 bitfields. + state->u.f4.fld.ispr1.setpend = cm_object_get_child_by_name(state->u.f4.reg.ispr1, "SETPEND"); + + // ISPR2 bitfields. + state->u.f4.fld.ispr2.setpend = cm_object_get_child_by_name(state->u.f4.reg.ispr2, "SETPEND"); + + // ICPR0 bitfields. + state->u.f4.fld.icpr0.clrpend = cm_object_get_child_by_name(state->u.f4.reg.icpr0, "CLRPEND"); + + // ICPR1 bitfields. + state->u.f4.fld.icpr1.clrpend = cm_object_get_child_by_name(state->u.f4.reg.icpr1, "CLRPEND"); + + // ICPR2 bitfields. + state->u.f4.fld.icpr2.clrpend = cm_object_get_child_by_name(state->u.f4.reg.icpr2, "CLRPEND"); + + // IABR0 bitfields. + state->u.f4.fld.iabr0.active = cm_object_get_child_by_name(state->u.f4.reg.iabr0, "ACTIVE"); + + // IABR1 bitfields. + state->u.f4.fld.iabr1.active = cm_object_get_child_by_name(state->u.f4.reg.iabr1, "ACTIVE"); + + // IABR2 bitfields. + state->u.f4.fld.iabr2.active = cm_object_get_child_by_name(state->u.f4.reg.iabr2, "ACTIVE"); + + // IPR0 bitfields. + state->u.f4.fld.ipr0.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr0, "IPR_N0"); + state->u.f4.fld.ipr0.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr0, "IPR_N1"); + state->u.f4.fld.ipr0.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr0, "IPR_N2"); + state->u.f4.fld.ipr0.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr0, "IPR_N3"); + + // IPR1 bitfields. + state->u.f4.fld.ipr1.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr1, "IPR_N0"); + state->u.f4.fld.ipr1.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr1, "IPR_N1"); + state->u.f4.fld.ipr1.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr1, "IPR_N2"); + state->u.f4.fld.ipr1.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr1, "IPR_N3"); + + // IPR2 bitfields. + state->u.f4.fld.ipr2.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr2, "IPR_N0"); + state->u.f4.fld.ipr2.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr2, "IPR_N1"); + state->u.f4.fld.ipr2.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr2, "IPR_N2"); + state->u.f4.fld.ipr2.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr2, "IPR_N3"); + + // IPR3 bitfields. + state->u.f4.fld.ipr3.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr3, "IPR_N0"); + state->u.f4.fld.ipr3.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr3, "IPR_N1"); + state->u.f4.fld.ipr3.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr3, "IPR_N2"); + state->u.f4.fld.ipr3.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr3, "IPR_N3"); + + // IPR4 bitfields. + state->u.f4.fld.ipr4.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr4, "IPR_N0"); + state->u.f4.fld.ipr4.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr4, "IPR_N1"); + state->u.f4.fld.ipr4.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr4, "IPR_N2"); + state->u.f4.fld.ipr4.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr4, "IPR_N3"); + + // IPR5 bitfields. + state->u.f4.fld.ipr5.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr5, "IPR_N0"); + state->u.f4.fld.ipr5.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr5, "IPR_N1"); + state->u.f4.fld.ipr5.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr5, "IPR_N2"); + state->u.f4.fld.ipr5.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr5, "IPR_N3"); + + // IPR6 bitfields. + state->u.f4.fld.ipr6.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr6, "IPR_N0"); + state->u.f4.fld.ipr6.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr6, "IPR_N1"); + state->u.f4.fld.ipr6.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr6, "IPR_N2"); + state->u.f4.fld.ipr6.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr6, "IPR_N3"); + + // IPR7 bitfields. + state->u.f4.fld.ipr7.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr7, "IPR_N0"); + state->u.f4.fld.ipr7.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr7, "IPR_N1"); + state->u.f4.fld.ipr7.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr7, "IPR_N2"); + state->u.f4.fld.ipr7.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr7, "IPR_N3"); + + // IPR8 bitfields. + state->u.f4.fld.ipr8.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr8, "IPR_N0"); + state->u.f4.fld.ipr8.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr8, "IPR_N1"); + state->u.f4.fld.ipr8.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr8, "IPR_N2"); + state->u.f4.fld.ipr8.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr8, "IPR_N3"); + + // IPR9 bitfields. + state->u.f4.fld.ipr9.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr9, "IPR_N0"); + state->u.f4.fld.ipr9.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr9, "IPR_N1"); + state->u.f4.fld.ipr9.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr9, "IPR_N2"); + state->u.f4.fld.ipr9.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr9, "IPR_N3"); + + // IPR10 bitfields. + state->u.f4.fld.ipr10.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr10, "IPR_N0"); + state->u.f4.fld.ipr10.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr10, "IPR_N1"); + state->u.f4.fld.ipr10.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr10, "IPR_N2"); + state->u.f4.fld.ipr10.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr10, "IPR_N3"); + + // IPR11 bitfields. + state->u.f4.fld.ipr11.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr11, "IPR_N0"); + state->u.f4.fld.ipr11.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr11, "IPR_N1"); + state->u.f4.fld.ipr11.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr11, "IPR_N2"); + state->u.f4.fld.ipr11.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr11, "IPR_N3"); + + // IPR12 bitfields. + state->u.f4.fld.ipr12.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr12, "IPR_N0"); + state->u.f4.fld.ipr12.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr12, "IPR_N1"); + state->u.f4.fld.ipr12.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr12, "IPR_N2"); + state->u.f4.fld.ipr12.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr12, "IPR_N3"); + + // IPR13 bitfields. + state->u.f4.fld.ipr13.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr13, "IPR_N0"); + state->u.f4.fld.ipr13.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr13, "IPR_N1"); + state->u.f4.fld.ipr13.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr13, "IPR_N2"); + state->u.f4.fld.ipr13.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr13, "IPR_N3"); + + // IPR14 bitfields. + state->u.f4.fld.ipr14.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr14, "IPR_N0"); + state->u.f4.fld.ipr14.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr14, "IPR_N1"); + state->u.f4.fld.ipr14.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr14, "IPR_N2"); + state->u.f4.fld.ipr14.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr14, "IPR_N3"); + + // IPR15 bitfields. + state->u.f4.fld.ipr15.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr15, "IPR_N0"); + state->u.f4.fld.ipr15.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr15, "IPR_N1"); + state->u.f4.fld.ipr15.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr15, "IPR_N2"); + state->u.f4.fld.ipr15.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr15, "IPR_N3"); + + // IPR16 bitfields. + state->u.f4.fld.ipr16.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr16, "IPR_N0"); + state->u.f4.fld.ipr16.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr16, "IPR_N1"); + state->u.f4.fld.ipr16.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr16, "IPR_N2"); + state->u.f4.fld.ipr16.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr16, "IPR_N3"); + + // IPR17 bitfields. + state->u.f4.fld.ipr17.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr17, "IPR_N0"); + state->u.f4.fld.ipr17.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr17, "IPR_N1"); + state->u.f4.fld.ipr17.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr17, "IPR_N2"); + state->u.f4.fld.ipr17.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr17, "IPR_N3"); + + // IPR18 bitfields. + state->u.f4.fld.ipr18.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr18, "IPR_N0"); + state->u.f4.fld.ipr18.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr18, "IPR_N1"); + state->u.f4.fld.ipr18.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr18, "IPR_N2"); + state->u.f4.fld.ipr18.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr18, "IPR_N3"); + + // IPR19 bitfields. + state->u.f4.fld.ipr19.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr19, "IPR_N0"); + state->u.f4.fld.ipr19.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr19, "IPR_N1"); + state->u.f4.fld.ipr19.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr19, "IPR_N2"); + state->u.f4.fld.ipr19.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr19, "IPR_N3"); + + // IPR20 bitfields. + state->u.f4.fld.ipr20.ipr_n0 = cm_object_get_child_by_name(state->u.f4.reg.ipr20, "IPR_N0"); + state->u.f4.fld.ipr20.ipr_n1 = cm_object_get_child_by_name(state->u.f4.reg.ipr20, "IPR_N1"); + state->u.f4.fld.ipr20.ipr_n2 = cm_object_get_child_by_name(state->u.f4.reg.ipr20, "IPR_N2"); + state->u.f4.fld.ipr20.ipr_n3 = cm_object_get_child_by_name(state->u.f4.reg.ipr20, "IPR_N3"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_nvic_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32NVICState *state = STM32_NVIC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_nvic_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32NVICState *state = STM32_NVIC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_nvic_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32NVICState *state = STM32_NVIC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_nvic_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32NVICState *state = STM32_NVIC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_nvic_is_enabled(Object *obj) +{ + STM32NVICState *state = STM32_NVIC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_nvic_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32NVICState *state = STM32_NVIC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_nvic_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_NVIC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32NVICState *state = STM32_NVIC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "NVIC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_nvic_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_nvic_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_nvic_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_nvic_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_nvic_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/NVICEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_nvic_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_NVIC); +} + +static void stm32_nvic_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_nvic_reset_callback; + dc->realize = stm32_nvic_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_nvic_is_enabled; +} + +static const TypeInfo stm32_nvic_type_info = { + .name = TYPE_STM32_NVIC, + .parent = TYPE_STM32_NVIC_PARENT, + .instance_init = stm32_nvic_instance_init_callback, + .instance_size = sizeof(STM32NVICState), + .class_init = stm32_nvic_class_init_callback, + .class_size = sizeof(STM32NVICClass) }; + +static void stm32_nvic_register_types(void) +{ + type_register_static(&stm32_nvic_type_info); +} + +type_init(stm32_nvic_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/nvic.h b/gnu-mcu-eclipse/devices/support/STM32F429x/nvic.h new file mode 100644 index 0000000000..30a0f25431 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/nvic.h @@ -0,0 +1,390 @@ +/* + * STM32 - NVIC (Nested Vectored Interrupt Controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_NVIC_H_ +#define STM32_NVIC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_NVIC DEVICE_PATH_STM32 "NVIC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_NVIC TYPE_STM32_PREFIX "nvic" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_NVIC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32NVICParentClass; +typedef PeripheralState STM32NVICParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_NVIC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32NVICClass, (obj), TYPE_STM32_NVIC) +#define STM32_NVIC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32NVICClass, (klass), TYPE_STM32_NVIC) + +typedef struct { + // private: + STM32NVICParentClass parent_class; + // public: + + // None, so far. +} STM32NVICClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_NVIC_STATE(obj) \ + OBJECT_CHECK(STM32NVICState, (obj), TYPE_STM32_NVIC) + +typedef struct { + // private: + STM32NVICParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 NVIC (Nested Vectored Interrupt Controller) registers. + struct { + Object *ictr; // 0x4 (Interrupt Controller Type Register) + Object *stir; // 0xF00 (Software Triggered Interrupt Register) + Object *iser0; // 0x100 (Interrupt Set-Enable Register) + Object *iser1; // 0x104 (Interrupt Set-Enable Register) + Object *iser2; // 0x108 (Interrupt Set-Enable Register) + Object *icer0; // 0x180 (Interrupt Clear-Enable Register) + Object *icer1; // 0x184 (Interrupt Clear-Enable Register) + Object *icer2; // 0x188 (Interrupt Clear-Enable Register) + Object *ispr0; // 0x200 (Interrupt Set-Pending Register) + Object *ispr1; // 0x204 (Interrupt Set-Pending Register) + Object *ispr2; // 0x208 (Interrupt Set-Pending Register) + Object *icpr0; // 0x280 (Interrupt Clear-Pending Register) + Object *icpr1; // 0x284 (Interrupt Clear-Pending Register) + Object *icpr2; // 0x288 (Interrupt Clear-Pending Register) + Object *iabr0; // 0x300 (Interrupt Active Bit Register) + Object *iabr1; // 0x304 (Interrupt Active Bit Register) + Object *iabr2; // 0x308 (Interrupt Active Bit Register) + Object *ipr0; // 0x400 (Interrupt Priority Register) + Object *ipr1; // 0x404 (Interrupt Priority Register) + Object *ipr2; // 0x408 (Interrupt Priority Register) + Object *ipr3; // 0x40C (Interrupt Priority Register) + Object *ipr4; // 0x410 (Interrupt Priority Register) + Object *ipr5; // 0x414 (Interrupt Priority Register) + Object *ipr6; // 0x418 (Interrupt Priority Register) + Object *ipr7; // 0x41C (Interrupt Priority Register) + Object *ipr8; // 0x420 (Interrupt Priority Register) + Object *ipr9; // 0x424 (Interrupt Priority Register) + Object *ipr10; // 0x428 (Interrupt Priority Register) + Object *ipr11; // 0x42C (Interrupt Priority Register) + Object *ipr12; // 0x430 (Interrupt Priority Register) + Object *ipr13; // 0x434 (Interrupt Priority Register) + Object *ipr14; // 0x438 (Interrupt Priority Register) + Object *ipr15; // 0x43C (Interrupt Priority Register) + Object *ipr16; // 0x440 (Interrupt Priority Register) + Object *ipr17; // 0x444 (Interrupt Priority Register) + Object *ipr18; // 0x448 (Interrupt Priority Register) + Object *ipr19; // 0x44C (Interrupt Priority Register) + Object *ipr20; // 0x450 (Interrupt Priority Register) + } reg; + + struct { + + // ICTR (Interrupt Controller Type Register) bitfields. + struct { + Object *intlinesnum; // [0:3] Total number of interrupt lines in groups + } ictr; + + // STIR (Software Triggered Interrupt Register) bitfields. + struct { + Object *intid; // [0:8] Interrupt to be triggered + } stir; + + // ISER0 (Interrupt Set-Enable Register) bitfields. + struct { + Object *setena; // [0:31] SETENA + } iser0; + + // ISER1 (Interrupt Set-Enable Register) bitfields. + struct { + Object *setena; // [0:31] SETENA + } iser1; + + // ISER2 (Interrupt Set-Enable Register) bitfields. + struct { + Object *setena; // [0:31] SETENA + } iser2; + + // ICER0 (Interrupt Clear-Enable Register) bitfields. + struct { + Object *clrena; // [0:31] CLRENA + } icer0; + + // ICER1 (Interrupt Clear-Enable Register) bitfields. + struct { + Object *clrena; // [0:31] CLRENA + } icer1; + + // ICER2 (Interrupt Clear-Enable Register) bitfields. + struct { + Object *clrena; // [0:31] CLRENA + } icer2; + + // ISPR0 (Interrupt Set-Pending Register) bitfields. + struct { + Object *setpend; // [0:31] SETPEND + } ispr0; + + // ISPR1 (Interrupt Set-Pending Register) bitfields. + struct { + Object *setpend; // [0:31] SETPEND + } ispr1; + + // ISPR2 (Interrupt Set-Pending Register) bitfields. + struct { + Object *setpend; // [0:31] SETPEND + } ispr2; + + // ICPR0 (Interrupt Clear-Pending Register) bitfields. + struct { + Object *clrpend; // [0:31] CLRPEND + } icpr0; + + // ICPR1 (Interrupt Clear-Pending Register) bitfields. + struct { + Object *clrpend; // [0:31] CLRPEND + } icpr1; + + // ICPR2 (Interrupt Clear-Pending Register) bitfields. + struct { + Object *clrpend; // [0:31] CLRPEND + } icpr2; + + // IABR0 (Interrupt Active Bit Register) bitfields. + struct { + Object *active; // [0:31] ACTIVE + } iabr0; + + // IABR1 (Interrupt Active Bit Register) bitfields. + struct { + Object *active; // [0:31] ACTIVE + } iabr1; + + // IABR2 (Interrupt Active Bit Register) bitfields. + struct { + Object *active; // [0:31] ACTIVE + } iabr2; + + // IPR0 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr0; + + // IPR1 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr1; + + // IPR2 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr2; + + // IPR3 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr3; + + // IPR4 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr4; + + // IPR5 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr5; + + // IPR6 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr6; + + // IPR7 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr7; + + // IPR8 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr8; + + // IPR9 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr9; + + // IPR10 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr10; + + // IPR11 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr11; + + // IPR12 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr12; + + // IPR13 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr13; + + // IPR14 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr14; + + // IPR15 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr15; + + // IPR16 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr16; + + // IPR17 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr17; + + // IPR18 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr18; + + // IPR19 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr19; + + // IPR20 (Interrupt Priority Register) bitfields. + struct { + Object *ipr_n0; // [0:7] IPR_N0 + Object *ipr_n1; // [8:15] IPR_N1 + Object *ipr_n2; // [16:23] IPR_N2 + Object *ipr_n3; // [24:31] IPR_N3 + } ipr20; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32NVICState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_NVIC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_device.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_device.c new file mode 100644 index 0000000000..4f45cd8348 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_device.c @@ -0,0 +1,552 @@ +/* + * STM32 - OTG_FS_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_fs_device_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_dcfg = cm_object_get_child_by_name(obj, "FS_DCFG"); + state->u.f4.reg.fs_dctl = cm_object_get_child_by_name(obj, "FS_DCTL"); + state->u.f4.reg.fs_dsts = cm_object_get_child_by_name(obj, "FS_DSTS"); + state->u.f4.reg.fs_diepmsk = cm_object_get_child_by_name(obj, "FS_DIEPMSK"); + state->u.f4.reg.fs_doepmsk = cm_object_get_child_by_name(obj, "FS_DOEPMSK"); + state->u.f4.reg.fs_daint = cm_object_get_child_by_name(obj, "FS_DAINT"); + state->u.f4.reg.fs_daintmsk = cm_object_get_child_by_name(obj, "FS_DAINTMSK"); + state->u.f4.reg.dvbusdis = cm_object_get_child_by_name(obj, "DVBUSDIS"); + state->u.f4.reg.dvbuspulse = cm_object_get_child_by_name(obj, "DVBUSPULSE"); + state->u.f4.reg.diepempmsk = cm_object_get_child_by_name(obj, "DIEPEMPMSK"); + state->u.f4.reg.fs_diepctl0 = cm_object_get_child_by_name(obj, "FS_DIEPCTL0"); + state->u.f4.reg.diepctl1 = cm_object_get_child_by_name(obj, "DIEPCTL1"); + state->u.f4.reg.diepctl2 = cm_object_get_child_by_name(obj, "DIEPCTL2"); + state->u.f4.reg.diepctl3 = cm_object_get_child_by_name(obj, "DIEPCTL3"); + state->u.f4.reg.doepctl0 = cm_object_get_child_by_name(obj, "DOEPCTL0"); + state->u.f4.reg.doepctl1 = cm_object_get_child_by_name(obj, "DOEPCTL1"); + state->u.f4.reg.doepctl2 = cm_object_get_child_by_name(obj, "DOEPCTL2"); + state->u.f4.reg.doepctl3 = cm_object_get_child_by_name(obj, "DOEPCTL3"); + state->u.f4.reg.diepint0 = cm_object_get_child_by_name(obj, "DIEPINT0"); + state->u.f4.reg.diepint1 = cm_object_get_child_by_name(obj, "DIEPINT1"); + state->u.f4.reg.diepint2 = cm_object_get_child_by_name(obj, "DIEPINT2"); + state->u.f4.reg.diepint3 = cm_object_get_child_by_name(obj, "DIEPINT3"); + state->u.f4.reg.doepint0 = cm_object_get_child_by_name(obj, "DOEPINT0"); + state->u.f4.reg.doepint1 = cm_object_get_child_by_name(obj, "DOEPINT1"); + state->u.f4.reg.doepint2 = cm_object_get_child_by_name(obj, "DOEPINT2"); + state->u.f4.reg.doepint3 = cm_object_get_child_by_name(obj, "DOEPINT3"); + state->u.f4.reg.dieptsiz0 = cm_object_get_child_by_name(obj, "DIEPTSIZ0"); + state->u.f4.reg.doeptsiz0 = cm_object_get_child_by_name(obj, "DOEPTSIZ0"); + state->u.f4.reg.dieptsiz1 = cm_object_get_child_by_name(obj, "DIEPTSIZ1"); + state->u.f4.reg.dieptsiz2 = cm_object_get_child_by_name(obj, "DIEPTSIZ2"); + state->u.f4.reg.dieptsiz3 = cm_object_get_child_by_name(obj, "DIEPTSIZ3"); + state->u.f4.reg.dtxfsts0 = cm_object_get_child_by_name(obj, "DTXFSTS0"); + state->u.f4.reg.dtxfsts1 = cm_object_get_child_by_name(obj, "DTXFSTS1"); + state->u.f4.reg.dtxfsts2 = cm_object_get_child_by_name(obj, "DTXFSTS2"); + state->u.f4.reg.dtxfsts3 = cm_object_get_child_by_name(obj, "DTXFSTS3"); + state->u.f4.reg.doeptsiz1 = cm_object_get_child_by_name(obj, "DOEPTSIZ1"); + state->u.f4.reg.doeptsiz2 = cm_object_get_child_by_name(obj, "DOEPTSIZ2"); + state->u.f4.reg.doeptsiz3 = cm_object_get_child_by_name(obj, "DOEPTSIZ3"); + + + // FS_DCFG bitfields. + state->u.f4.fld.fs_dcfg.dspd = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "DSPD"); + state->u.f4.fld.fs_dcfg.nzlsohsk = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "NZLSOHSK"); + state->u.f4.fld.fs_dcfg.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "DAD"); + state->u.f4.fld.fs_dcfg.pfivl = cm_object_get_child_by_name(state->u.f4.reg.fs_dcfg, "PFIVL"); + + // FS_DCTL bitfields. + state->u.f4.fld.fs_dctl.rwusig = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "RWUSIG"); + state->u.f4.fld.fs_dctl.sdis = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SDIS"); + state->u.f4.fld.fs_dctl.ginsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "GINSTS"); + state->u.f4.fld.fs_dctl.gonsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "GONSTS"); + state->u.f4.fld.fs_dctl.tctl = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "TCTL"); + state->u.f4.fld.fs_dctl.sginak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SGINAK"); + state->u.f4.fld.fs_dctl.cginak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "CGINAK"); + state->u.f4.fld.fs_dctl.sgonak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "SGONAK"); + state->u.f4.fld.fs_dctl.cgonak = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "CGONAK"); + state->u.f4.fld.fs_dctl.poprgdne = cm_object_get_child_by_name(state->u.f4.reg.fs_dctl, "POPRGDNE"); + + // FS_DSTS bitfields. + state->u.f4.fld.fs_dsts.suspsts = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "SUSPSTS"); + state->u.f4.fld.fs_dsts.enumspd = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "ENUMSPD"); + state->u.f4.fld.fs_dsts.eerr = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "EERR"); + state->u.f4.fld.fs_dsts.fnsof = cm_object_get_child_by_name(state->u.f4.reg.fs_dsts, "FNSOF"); + + // FS_DIEPMSK bitfields. + state->u.f4.fld.fs_diepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "XFRCM"); + state->u.f4.fld.fs_diepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "EPDM"); + state->u.f4.fld.fs_diepmsk.tom = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "TOM"); + state->u.f4.fld.fs_diepmsk.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "ITTXFEMSK"); + state->u.f4.fld.fs_diepmsk.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "INEPNMM"); + state->u.f4.fld.fs_diepmsk.inepnem = cm_object_get_child_by_name(state->u.f4.reg.fs_diepmsk, "INEPNEM"); + + // FS_DOEPMSK bitfields. + state->u.f4.fld.fs_doepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "XFRCM"); + state->u.f4.fld.fs_doepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "EPDM"); + state->u.f4.fld.fs_doepmsk.stupm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "STUPM"); + state->u.f4.fld.fs_doepmsk.otepdm = cm_object_get_child_by_name(state->u.f4.reg.fs_doepmsk, "OTEPDM"); + + // FS_DAINT bitfields. + state->u.f4.fld.fs_daint.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daint, "IEPINT"); + state->u.f4.fld.fs_daint.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daint, "OEPINT"); + + // FS_DAINTMSK bitfields. + state->u.f4.fld.fs_daintmsk.iepm = cm_object_get_child_by_name(state->u.f4.reg.fs_daintmsk, "IEPM"); + state->u.f4.fld.fs_daintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_daintmsk, "OEPINT"); + + // DVBUSDIS bitfields. + state->u.f4.fld.dvbusdis.vbusdt = cm_object_get_child_by_name(state->u.f4.reg.dvbusdis, "VBUSDT"); + + // DVBUSPULSE bitfields. + state->u.f4.fld.dvbuspulse.dvbusp = cm_object_get_child_by_name(state->u.f4.reg.dvbuspulse, "DVBUSP"); + + // DIEPEMPMSK bitfields. + state->u.f4.fld.diepempmsk.ineptxfem = cm_object_get_child_by_name(state->u.f4.reg.diepempmsk, "INEPTXFEM"); + + // FS_DIEPCTL0 bitfields. + state->u.f4.fld.fs_diepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "MPSIZ"); + state->u.f4.fld.fs_diepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "USBAEP"); + state->u.f4.fld.fs_diepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "NAKSTS"); + state->u.f4.fld.fs_diepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPTYP"); + state->u.f4.fld.fs_diepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "STALL"); + state->u.f4.fld.fs_diepctl0.txfnum = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "TXFNUM"); + state->u.f4.fld.fs_diepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "CNAK"); + state->u.f4.fld.fs_diepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "SNAK"); + state->u.f4.fld.fs_diepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPDIS"); + state->u.f4.fld.fs_diepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.fs_diepctl0, "EPENA"); + + // DIEPCTL1 bitfields. + state->u.f4.fld.diepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "MPSIZ"); + state->u.f4.fld.diepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "USBAEP"); + state->u.f4.fld.diepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EONUM_DPID"); + state->u.f4.fld.diepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "NAKSTS"); + state->u.f4.fld.diepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPTYP"); + state->u.f4.fld.diepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "Stall"); + state->u.f4.fld.diepctl1.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "TXFNUM"); + state->u.f4.fld.diepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "CNAK"); + state->u.f4.fld.diepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SNAK"); + state->u.f4.fld.diepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl1.soddfrm_sd1pid = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "SODDFRM_SD1PID"); + state->u.f4.fld.diepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPDIS"); + state->u.f4.fld.diepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl1, "EPENA"); + + // DIEPCTL2 bitfields. + state->u.f4.fld.diepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "MPSIZ"); + state->u.f4.fld.diepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "USBAEP"); + state->u.f4.fld.diepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EONUM_DPID"); + state->u.f4.fld.diepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "NAKSTS"); + state->u.f4.fld.diepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPTYP"); + state->u.f4.fld.diepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "Stall"); + state->u.f4.fld.diepctl2.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "TXFNUM"); + state->u.f4.fld.diepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "CNAK"); + state->u.f4.fld.diepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SNAK"); + state->u.f4.fld.diepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "SODDFRM"); + state->u.f4.fld.diepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPDIS"); + state->u.f4.fld.diepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl2, "EPENA"); + + // DIEPCTL3 bitfields. + state->u.f4.fld.diepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "MPSIZ"); + state->u.f4.fld.diepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "USBAEP"); + state->u.f4.fld.diepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EONUM_DPID"); + state->u.f4.fld.diepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "NAKSTS"); + state->u.f4.fld.diepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPTYP"); + state->u.f4.fld.diepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "Stall"); + state->u.f4.fld.diepctl3.txfnum = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "TXFNUM"); + state->u.f4.fld.diepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "CNAK"); + state->u.f4.fld.diepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SNAK"); + state->u.f4.fld.diepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.diepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "SODDFRM"); + state->u.f4.fld.diepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPDIS"); + state->u.f4.fld.diepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.diepctl3, "EPENA"); + + // DOEPCTL0 bitfields. + state->u.f4.fld.doepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "MPSIZ"); + state->u.f4.fld.doepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "USBAEP"); + state->u.f4.fld.doepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "NAKSTS"); + state->u.f4.fld.doepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPTYP"); + state->u.f4.fld.doepctl0.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "SNPM"); + state->u.f4.fld.doepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "Stall"); + state->u.f4.fld.doepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "CNAK"); + state->u.f4.fld.doepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "SNAK"); + state->u.f4.fld.doepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPDIS"); + state->u.f4.fld.doepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl0, "EPENA"); + + // DOEPCTL1 bitfields. + state->u.f4.fld.doepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "MPSIZ"); + state->u.f4.fld.doepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "USBAEP"); + state->u.f4.fld.doepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EONUM_DPID"); + state->u.f4.fld.doepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "NAKSTS"); + state->u.f4.fld.doepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPTYP"); + state->u.f4.fld.doepctl1.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SNPM"); + state->u.f4.fld.doepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "Stall"); + state->u.f4.fld.doepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "CNAK"); + state->u.f4.fld.doepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SNAK"); + state->u.f4.fld.doepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl1.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "SODDFRM"); + state->u.f4.fld.doepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPDIS"); + state->u.f4.fld.doepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl1, "EPENA"); + + // DOEPCTL2 bitfields. + state->u.f4.fld.doepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "MPSIZ"); + state->u.f4.fld.doepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "USBAEP"); + state->u.f4.fld.doepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EONUM_DPID"); + state->u.f4.fld.doepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "NAKSTS"); + state->u.f4.fld.doepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPTYP"); + state->u.f4.fld.doepctl2.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SNPM"); + state->u.f4.fld.doepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "Stall"); + state->u.f4.fld.doepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "CNAK"); + state->u.f4.fld.doepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SNAK"); + state->u.f4.fld.doepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "SODDFRM"); + state->u.f4.fld.doepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPDIS"); + state->u.f4.fld.doepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl2, "EPENA"); + + // DOEPCTL3 bitfields. + state->u.f4.fld.doepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "MPSIZ"); + state->u.f4.fld.doepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "USBAEP"); + state->u.f4.fld.doepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EONUM_DPID"); + state->u.f4.fld.doepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "NAKSTS"); + state->u.f4.fld.doepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPTYP"); + state->u.f4.fld.doepctl3.snpm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SNPM"); + state->u.f4.fld.doepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "Stall"); + state->u.f4.fld.doepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "CNAK"); + state->u.f4.fld.doepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SNAK"); + state->u.f4.fld.doepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.doepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "SODDFRM"); + state->u.f4.fld.doepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPDIS"); + state->u.f4.fld.doepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.doepctl3, "EPENA"); + + // DIEPINT0 bitfields. + state->u.f4.fld.diepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "XFRC"); + state->u.f4.fld.diepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "EPDISD"); + state->u.f4.fld.diepint0.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "TOC"); + state->u.f4.fld.diepint0.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "ITTXFE"); + state->u.f4.fld.diepint0.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "INEPNE"); + state->u.f4.fld.diepint0.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint0, "TXFE"); + + // DIEPINT1 bitfields. + state->u.f4.fld.diepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "XFRC"); + state->u.f4.fld.diepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "EPDISD"); + state->u.f4.fld.diepint1.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "TOC"); + state->u.f4.fld.diepint1.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "ITTXFE"); + state->u.f4.fld.diepint1.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "INEPNE"); + state->u.f4.fld.diepint1.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint1, "TXFE"); + + // DIEPINT2 bitfields. + state->u.f4.fld.diepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "XFRC"); + state->u.f4.fld.diepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "EPDISD"); + state->u.f4.fld.diepint2.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "TOC"); + state->u.f4.fld.diepint2.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "ITTXFE"); + state->u.f4.fld.diepint2.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "INEPNE"); + state->u.f4.fld.diepint2.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint2, "TXFE"); + + // DIEPINT3 bitfields. + state->u.f4.fld.diepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "XFRC"); + state->u.f4.fld.diepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "EPDISD"); + state->u.f4.fld.diepint3.toc = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "TOC"); + state->u.f4.fld.diepint3.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "ITTXFE"); + state->u.f4.fld.diepint3.inepne = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "INEPNE"); + state->u.f4.fld.diepint3.txfe = cm_object_get_child_by_name(state->u.f4.reg.diepint3, "TXFE"); + + // DOEPINT0 bitfields. + state->u.f4.fld.doepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "XFRC"); + state->u.f4.fld.doepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "EPDISD"); + state->u.f4.fld.doepint0.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "STUP"); + state->u.f4.fld.doepint0.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "OTEPDIS"); + state->u.f4.fld.doepint0.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint0, "B2BSTUP"); + + // DOEPINT1 bitfields. + state->u.f4.fld.doepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "XFRC"); + state->u.f4.fld.doepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "EPDISD"); + state->u.f4.fld.doepint1.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "STUP"); + state->u.f4.fld.doepint1.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "OTEPDIS"); + state->u.f4.fld.doepint1.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint1, "B2BSTUP"); + + // DOEPINT2 bitfields. + state->u.f4.fld.doepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "XFRC"); + state->u.f4.fld.doepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "EPDISD"); + state->u.f4.fld.doepint2.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "STUP"); + state->u.f4.fld.doepint2.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "OTEPDIS"); + state->u.f4.fld.doepint2.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint2, "B2BSTUP"); + + // DOEPINT3 bitfields. + state->u.f4.fld.doepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "XFRC"); + state->u.f4.fld.doepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "EPDISD"); + state->u.f4.fld.doepint3.stup = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "STUP"); + state->u.f4.fld.doepint3.otepdis = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "OTEPDIS"); + state->u.f4.fld.doepint3.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.doepint3, "B2BSTUP"); + + // DIEPTSIZ0 bitfields. + state->u.f4.fld.dieptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz0, "XFRSIZ"); + state->u.f4.fld.dieptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz0, "PKTCNT"); + + // DOEPTSIZ0 bitfields. + state->u.f4.fld.doeptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "XFRSIZ"); + state->u.f4.fld.doeptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "PKTCNT"); + state->u.f4.fld.doeptsiz0.stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz0, "STUPCNT"); + + // DIEPTSIZ1 bitfields. + state->u.f4.fld.dieptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "XFRSIZ"); + state->u.f4.fld.dieptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "PKTCNT"); + state->u.f4.fld.dieptsiz1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz1, "MCNT"); + + // DIEPTSIZ2 bitfields. + state->u.f4.fld.dieptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "XFRSIZ"); + state->u.f4.fld.dieptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "PKTCNT"); + state->u.f4.fld.dieptsiz2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz2, "MCNT"); + + // DIEPTSIZ3 bitfields. + state->u.f4.fld.dieptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "XFRSIZ"); + state->u.f4.fld.dieptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "PKTCNT"); + state->u.f4.fld.dieptsiz3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.dieptsiz3, "MCNT"); + + // DTXFSTS0 bitfields. + state->u.f4.fld.dtxfsts0.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts0, "INEPTFSAV"); + + // DTXFSTS1 bitfields. + state->u.f4.fld.dtxfsts1.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts1, "INEPTFSAV"); + + // DTXFSTS2 bitfields. + state->u.f4.fld.dtxfsts2.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts2, "INEPTFSAV"); + + // DTXFSTS3 bitfields. + state->u.f4.fld.dtxfsts3.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.dtxfsts3, "INEPTFSAV"); + + // DOEPTSIZ1 bitfields. + state->u.f4.fld.doeptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "XFRSIZ"); + state->u.f4.fld.doeptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "PKTCNT"); + state->u.f4.fld.doeptsiz1.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz1, "RXDPID_STUPCNT"); + + // DOEPTSIZ2 bitfields. + state->u.f4.fld.doeptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "XFRSIZ"); + state->u.f4.fld.doeptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "PKTCNT"); + state->u.f4.fld.doeptsiz2.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz2, "RXDPID_STUPCNT"); + + // DOEPTSIZ3 bitfields. + state->u.f4.fld.doeptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "XFRSIZ"); + state->u.f4.fld.doeptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "PKTCNT"); + state->u.f4.fld.doeptsiz3.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.doeptsiz3, "RXDPID_STUPCNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_device_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_device_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_device_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_device_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_device_is_enabled(Object *obj) +{ + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_device_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_device_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_DEVICE)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_DEVICEState *state = STM32_OTG_FS_DEVICE_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_DEVICE"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_fs_device_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_device_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_DEVICEEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_device_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_DEVICE); +} + +static void stm32_otg_fs_device_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_device_reset_callback; + dc->realize = stm32_otg_fs_device_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_device_is_enabled; +} + +static const TypeInfo stm32_otg_fs_device_type_info = { + .name = TYPE_STM32_OTG_FS_DEVICE, + .parent = TYPE_STM32_OTG_FS_DEVICE_PARENT, + .instance_init = stm32_otg_fs_device_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_DEVICEState), + .class_init = stm32_otg_fs_device_class_init_callback, + .class_size = sizeof(STM32OTG_FS_DEVICEClass) }; + +static void stm32_otg_fs_device_register_types(void) +{ + type_register_static(&stm32_otg_fs_device_type_info); +} + +type_init(stm32_otg_fs_device_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_device.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_device.h new file mode 100644 index 0000000000..42475e75f6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_device.h @@ -0,0 +1,493 @@ +/* + * STM32 - OTG_FS_DEVICE (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_DEVICE_H_ +#define STM32_OTG_FS_DEVICE_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_DEVICE DEVICE_PATH_STM32 "OTG_FS_DEVICE" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_DEVICE TYPE_STM32_PREFIX "otg_fs_device" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_DEVICE_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_DEVICEParentClass; +typedef PeripheralState STM32OTG_FS_DEVICEParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_DEVICEClass, (obj), TYPE_STM32_OTG_FS_DEVICE) +#define STM32_OTG_FS_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_DEVICEClass, (klass), TYPE_STM32_OTG_FS_DEVICE) + +typedef struct { + // private: + STM32OTG_FS_DEVICEParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_DEVICEClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_DEVICE_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_DEVICEState, (obj), TYPE_STM32_OTG_FS_DEVICE) + +typedef struct { + // private: + STM32OTG_FS_DEVICEParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_DEVICE (USB on the go full speed) registers. + struct { + Object *fs_dcfg; // 0x0 (OTG_FS device configuration register (OTG_FS_DCFG)) + Object *fs_dctl; // 0x4 (OTG_FS device control register (OTG_FS_DCTL)) + Object *fs_dsts; // 0x8 (OTG_FS device status register (OTG_FS_DSTS)) + Object *fs_diepmsk; // 0x10 (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) + Object *fs_doepmsk; // 0x14 (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) + Object *fs_daint; // 0x18 (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) + Object *fs_daintmsk; // 0x1C (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) + Object *dvbusdis; // 0x28 (OTG_FS device VBUS discharge time register) + Object *dvbuspulse; // 0x2C (OTG_FS device VBUS pulsing time register) + Object *diepempmsk; // 0x34 (OTG_FS device IN endpoint FIFO empty interrupt mask register) + Object *fs_diepctl0; // 0x100 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) + Object *diepctl1; // 0x120 (OTG device endpoint-1 control register) + Object *diepctl2; // 0x140 (OTG device endpoint-2 control register) + Object *diepctl3; // 0x160 (OTG device endpoint-3 control register) + Object *doepctl0; // 0x300 (Device endpoint-0 control register) + Object *doepctl1; // 0x320 (Device endpoint-1 control register) + Object *doepctl2; // 0x340 (Device endpoint-2 control register) + Object *doepctl3; // 0x360 (Device endpoint-3 control register) + Object *diepint0; // 0x108 (Device endpoint-x interrupt register) + Object *diepint1; // 0x128 (Device endpoint-1 interrupt register) + Object *diepint2; // 0x148 (Device endpoint-2 interrupt register) + Object *diepint3; // 0x168 (Device endpoint-3 interrupt register) + Object *doepint0; // 0x308 (Device endpoint-0 interrupt register) + Object *doepint1; // 0x328 (Device endpoint-1 interrupt register) + Object *doepint2; // 0x348 (Device endpoint-2 interrupt register) + Object *doepint3; // 0x368 (Device endpoint-3 interrupt register) + Object *dieptsiz0; // 0x110 (Device endpoint-0 transfer size register) + Object *doeptsiz0; // 0x310 (Device OUT endpoint-0 transfer size register) + Object *dieptsiz1; // 0x130 (Device endpoint-1 transfer size register) + Object *dieptsiz2; // 0x150 (Device endpoint-2 transfer size register) + Object *dieptsiz3; // 0x170 (Device endpoint-3 transfer size register) + Object *dtxfsts0; // 0x118 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts1; // 0x138 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts2; // 0x158 (OTG_FS device IN endpoint transmit FIFO status register) + Object *dtxfsts3; // 0x178 (OTG_FS device IN endpoint transmit FIFO status register) + Object *doeptsiz1; // 0x330 (Device OUT endpoint-1 transfer size register) + Object *doeptsiz2; // 0x350 (Device OUT endpoint-2 transfer size register) + Object *doeptsiz3; // 0x370 (Device OUT endpoint-3 transfer size register) + } reg; + + struct { + + // FS_DCFG (OTG_FS device configuration register (OTG_FS_DCFG)) bitfields. + struct { + Object *dspd; // [0:1] Device speed + Object *nzlsohsk; // [2:2] Non-zero-length status OUT handshake + Object *dad; // [4:10] Device address + Object *pfivl; // [11:12] Periodic frame interval + } fs_dcfg; + + // FS_DCTL (OTG_FS device control register (OTG_FS_DCTL)) bitfields. + struct { + Object *rwusig; // [0:0] Remote wakeup signaling + Object *sdis; // [1:1] Soft disconnect + Object *ginsts; // [2:2] Global IN NAK status + Object *gonsts; // [3:3] Global OUT NAK status + Object *tctl; // [4:6] Test control + Object *sginak; // [7:7] Set global IN NAK + Object *cginak; // [8:8] Clear global IN NAK + Object *sgonak; // [9:9] Set global OUT NAK + Object *cgonak; // [10:10] Clear global OUT NAK + Object *poprgdne; // [11:11] Power-on programming done + } fs_dctl; + + // FS_DSTS (OTG_FS device status register (OTG_FS_DSTS)) bitfields. + struct { + Object *suspsts; // [0:0] Suspend status + Object *enumspd; // [1:2] Enumerated speed + Object *eerr; // [3:3] Erratic error + Object *fnsof; // [8:21] Frame number of the received SOF + } fs_dsts; + + // FS_DIEPMSK (OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (Non-isochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + } fs_diepmsk; + + // FS_DOEPMSK (OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *stupm; // [3:3] SETUP phase done mask + Object *otepdm; // [4:4] OUT token received when endpoint disabled mask + } fs_doepmsk; + + // FS_DAINT (OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)) bitfields. + struct { + Object *iepint; // [0:15] IN endpoint interrupt bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daint; + + // FS_DAINTMSK (OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)) bitfields. + struct { + Object *iepm; // [0:15] IN EP interrupt mask bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } fs_daintmsk; + + // DVBUSDIS (OTG_FS device VBUS discharge time register) bitfields. + struct { + Object *vbusdt; // [0:15] Device VBUS discharge time + } dvbusdis; + + // DVBUSPULSE (OTG_FS device VBUS pulsing time register) bitfields. + struct { + Object *dvbusp; // [0:11] Device VBUS pulsing time + } dvbuspulse; + + // DIEPEMPMSK (OTG_FS device IN endpoint FIFO empty interrupt mask register) bitfields. + struct { + Object *ineptxfem; // [0:15] IN EP Tx FIFO empty interrupt mask bits + } diepempmsk; + + // FS_DIEPCTL0 (OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)) bitfields. + struct { + Object *mpsiz; // [0:1] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } fs_diepctl0; + + // DIEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm_sd1pid; // [29:29] SODDFRM/SD1PID + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl1; + + // DIEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl2; + + // DIEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *stall; // [21:21] Stall + Object *txfnum; // [22:25] TXFNUM + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } diepctl3; + + // DOEPCTL0 (Device endpoint-0 control register) bitfields. + struct { + Object *mpsiz; // [0:1] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl0; + + // DOEPCTL1 (Device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl1; + + // DOEPCTL2 (Device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl2; + + // DOEPCTL3 (Device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] MPSIZ + Object *usbaep; // [15:15] USBAEP + Object *eonum_dpid; // [16:16] EONUM/DPID + Object *naksts; // [17:17] NAKSTS + Object *eptyp; // [18:19] EPTYP + Object *snpm; // [20:20] SNPM + Object *stall; // [21:21] Stall + Object *cnak; // [26:26] CNAK + Object *snak; // [27:27] SNAK + Object *sd0pid_sevnfrm; // [28:28] SD0PID/SEVNFRM + Object *soddfrm; // [29:29] SODDFRM + Object *epdis; // [30:30] EPDIS + Object *epena; // [31:31] EPENA + } doepctl3; + + // DIEPINT0 (Device endpoint-x interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint0; + + // DIEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint1; + + // DIEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint2; + + // DIEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *toc; // [3:3] TOC + Object *ittxfe; // [4:4] ITTXFE + Object *inepne; // [6:6] INEPNE + Object *txfe; // [7:7] TXFE + } diepint3; + + // DOEPINT0 (Device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint0; + + // DOEPINT1 (Device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint1; + + // DOEPINT2 (Device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint2; + + // DOEPINT3 (Device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] XFRC + Object *epdisd; // [1:1] EPDISD + Object *stup; // [3:3] STUP + Object *otepdis; // [4:4] OTEPDIS + Object *b2bstup; // [6:6] B2BSTUP + } doepint3; + + // DIEPTSIZ0 (Device endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:20] Packet count + } dieptsiz0; + + // DOEPTSIZ0 (Device OUT endpoint-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:19] Packet count + Object *stupcnt; // [29:30] SETUP packet count + } doeptsiz0; + + // DIEPTSIZ1 (Device endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz1; + + // DIEPTSIZ2 (Device endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz2; + + // DIEPTSIZ3 (Device endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } dieptsiz3; + + // DTXFSTS0 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts0; + + // DTXFSTS1 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts1; + + // DTXFSTS2 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts2; + + // DTXFSTS3 (OTG_FS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space available + } dtxfsts3; + + // DOEPTSIZ1 (Device OUT endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz1; + + // DOEPTSIZ2 (Device OUT endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz2; + + // DOEPTSIZ3 (Device OUT endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } doeptsiz3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_DEVICEState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_DEVICE_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_global.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_global.c new file mode 100644 index 0000000000..f15617ee40 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_global.c @@ -0,0 +1,406 @@ +/* + * STM32 - OTG_FS_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_fs_global_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_gotgctl = cm_object_get_child_by_name(obj, "FS_GOTGCTL"); + state->u.f4.reg.fs_gotgint = cm_object_get_child_by_name(obj, "FS_GOTGINT"); + state->u.f4.reg.fs_gahbcfg = cm_object_get_child_by_name(obj, "FS_GAHBCFG"); + state->u.f4.reg.fs_gusbcfg = cm_object_get_child_by_name(obj, "FS_GUSBCFG"); + state->u.f4.reg.fs_grstctl = cm_object_get_child_by_name(obj, "FS_GRSTCTL"); + state->u.f4.reg.fs_gintsts = cm_object_get_child_by_name(obj, "FS_GINTSTS"); + state->u.f4.reg.fs_gintmsk = cm_object_get_child_by_name(obj, "FS_GINTMSK"); + state->u.f4.reg.fs_grxstsr_device = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Device"); + state->u.f4.reg.fs_grxstsr_host = cm_object_get_child_by_name(obj, "FS_GRXSTSR_Host"); + state->u.f4.reg.fs_grxfsiz = cm_object_get_child_by_name(obj, "FS_GRXFSIZ"); + state->u.f4.reg.fs_gnptxfsiz_device = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Device"); + state->u.f4.reg.fs_gnptxfsiz_host = cm_object_get_child_by_name(obj, "FS_GNPTXFSIZ_Host"); + state->u.f4.reg.fs_gnptxsts = cm_object_get_child_by_name(obj, "FS_GNPTXSTS"); + state->u.f4.reg.fs_gccfg = cm_object_get_child_by_name(obj, "FS_GCCFG"); + state->u.f4.reg.fs_cid = cm_object_get_child_by_name(obj, "FS_CID"); + state->u.f4.reg.fs_hptxfsiz = cm_object_get_child_by_name(obj, "FS_HPTXFSIZ"); + state->u.f4.reg.fs_dieptxf1 = cm_object_get_child_by_name(obj, "FS_DIEPTXF1"); + state->u.f4.reg.fs_dieptxf2 = cm_object_get_child_by_name(obj, "FS_DIEPTXF2"); + state->u.f4.reg.fs_dieptxf3 = cm_object_get_child_by_name(obj, "FS_DIEPTXF3"); + + + // FS_GOTGCTL bitfields. + state->u.f4.fld.fs_gotgctl.srqscs = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "SRQSCS"); + state->u.f4.fld.fs_gotgctl.srq = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "SRQ"); + state->u.f4.fld.fs_gotgctl.hngscs = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HNGSCS"); + state->u.f4.fld.fs_gotgctl.hnprq = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HNPRQ"); + state->u.f4.fld.fs_gotgctl.hshnpen = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "HSHNPEN"); + state->u.f4.fld.fs_gotgctl.dhnpen = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "DHNPEN"); + state->u.f4.fld.fs_gotgctl.cidsts = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "CIDSTS"); + state->u.f4.fld.fs_gotgctl.dbct = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "DBCT"); + state->u.f4.fld.fs_gotgctl.asvld = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "ASVLD"); + state->u.f4.fld.fs_gotgctl.bsvld = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgctl, "BSVLD"); + + // FS_GOTGINT bitfields. + state->u.f4.fld.fs_gotgint.sedet = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "SEDET"); + state->u.f4.fld.fs_gotgint.srsschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "SRSSCHG"); + state->u.f4.fld.fs_gotgint.hnsschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "HNSSCHG"); + state->u.f4.fld.fs_gotgint.hngdet = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "HNGDET"); + state->u.f4.fld.fs_gotgint.adtochg = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "ADTOCHG"); + state->u.f4.fld.fs_gotgint.dbcdne = cm_object_get_child_by_name(state->u.f4.reg.fs_gotgint, "DBCDNE"); + + // FS_GAHBCFG bitfields. + state->u.f4.fld.fs_gahbcfg.gint = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "GINT"); + state->u.f4.fld.fs_gahbcfg.txfelvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "TXFELVL"); + state->u.f4.fld.fs_gahbcfg.ptxfelvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gahbcfg, "PTXFELVL"); + + // FS_GUSBCFG bitfields. + state->u.f4.fld.fs_gusbcfg.tocal = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "TOCAL"); + state->u.f4.fld.fs_gusbcfg.physel = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "PHYSEL"); + state->u.f4.fld.fs_gusbcfg.srpcap = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "SRPCAP"); + state->u.f4.fld.fs_gusbcfg.hnpcap = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "HNPCAP"); + state->u.f4.fld.fs_gusbcfg.trdt = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "TRDT"); + state->u.f4.fld.fs_gusbcfg.fhmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "FHMOD"); + state->u.f4.fld.fs_gusbcfg.fdmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "FDMOD"); + state->u.f4.fld.fs_gusbcfg.ctxpkt = cm_object_get_child_by_name(state->u.f4.reg.fs_gusbcfg, "CTXPKT"); + + // FS_GRSTCTL bitfields. + state->u.f4.fld.fs_grstctl.csrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "CSRST"); + state->u.f4.fld.fs_grstctl.hsrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "HSRST"); + state->u.f4.fld.fs_grstctl.fcrst = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "FCRST"); + state->u.f4.fld.fs_grstctl.rxfflsh = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "RXFFLSH"); + state->u.f4.fld.fs_grstctl.txfflsh = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "TXFFLSH"); + state->u.f4.fld.fs_grstctl.txfnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "TXFNUM"); + state->u.f4.fld.fs_grstctl.ahbidl = cm_object_get_child_by_name(state->u.f4.reg.fs_grstctl, "AHBIDL"); + + // FS_GINTSTS bitfields. + state->u.f4.fld.fs_gintsts.cmod = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "CMOD"); + state->u.f4.fld.fs_gintsts.mmis = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "MMIS"); + state->u.f4.fld.fs_gintsts.otgint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "OTGINT"); + state->u.f4.fld.fs_gintsts.sof = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "SOF"); + state->u.f4.fld.fs_gintsts.rxflvl = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "RXFLVL"); + state->u.f4.fld.fs_gintsts.nptxfe = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "NPTXFE"); + state->u.f4.fld.fs_gintsts.ginakeff = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "GINAKEFF"); + state->u.f4.fld.fs_gintsts.goutnakeff = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "GOUTNAKEFF"); + state->u.f4.fld.fs_gintsts.esusp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ESUSP"); + state->u.f4.fld.fs_gintsts.usbsusp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "USBSUSP"); + state->u.f4.fld.fs_gintsts.usbrst = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "USBRST"); + state->u.f4.fld.fs_gintsts.enumdne = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ENUMDNE"); + state->u.f4.fld.fs_gintsts.isoodrp = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "ISOODRP"); + state->u.f4.fld.fs_gintsts.eopf = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "EOPF"); + state->u.f4.fld.fs_gintsts.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IEPINT"); + state->u.f4.fld.fs_gintsts.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "OEPINT"); + state->u.f4.fld.fs_gintsts.iisoixfr = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IISOIXFR"); + state->u.f4.fld.fs_gintsts.ipxfr_incompisoout = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "IPXFR_INCOMPISOOUT"); + state->u.f4.fld.fs_gintsts.hprtint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "HPRTINT"); + state->u.f4.fld.fs_gintsts.hcint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "HCINT"); + state->u.f4.fld.fs_gintsts.ptxfe = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "PTXFE"); + state->u.f4.fld.fs_gintsts.cidschg = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "CIDSCHG"); + state->u.f4.fld.fs_gintsts.discint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "DISCINT"); + state->u.f4.fld.fs_gintsts.srqint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "SRQINT"); + state->u.f4.fld.fs_gintsts.wkupint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintsts, "WKUPINT"); + + // FS_GINTMSK bitfields. + state->u.f4.fld.fs_gintmsk.mmism = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "MMISM"); + state->u.f4.fld.fs_gintmsk.otgint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "OTGINT"); + state->u.f4.fld.fs_gintmsk.sofm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "SOFM"); + state->u.f4.fld.fs_gintmsk.rxflvlm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "RXFLVLM"); + state->u.f4.fld.fs_gintmsk.nptxfem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "NPTXFEM"); + state->u.f4.fld.fs_gintmsk.ginakeffm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "GINAKEFFM"); + state->u.f4.fld.fs_gintmsk.gonakeffm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "GONAKEFFM"); + state->u.f4.fld.fs_gintmsk.esuspm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ESUSPM"); + state->u.f4.fld.fs_gintmsk.usbsuspm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "USBSUSPM"); + state->u.f4.fld.fs_gintmsk.usbrst = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "USBRST"); + state->u.f4.fld.fs_gintmsk.enumdnem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ENUMDNEM"); + state->u.f4.fld.fs_gintmsk.isoodrpm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "ISOODRPM"); + state->u.f4.fld.fs_gintmsk.eopfm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "EOPFM"); + state->u.f4.fld.fs_gintmsk.epmism = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "EPMISM"); + state->u.f4.fld.fs_gintmsk.iepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IEPINT"); + state->u.f4.fld.fs_gintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "OEPINT"); + state->u.f4.fld.fs_gintmsk.iisoixfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IISOIXFRM"); + state->u.f4.fld.fs_gintmsk.ipxfrm_iisooxfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "IPXFRM_IISOOXFRM"); + state->u.f4.fld.fs_gintmsk.prtim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "PRTIM"); + state->u.f4.fld.fs_gintmsk.hcim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "HCIM"); + state->u.f4.fld.fs_gintmsk.ptxfem = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "PTXFEM"); + state->u.f4.fld.fs_gintmsk.cidschgm = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "CIDSCHGM"); + state->u.f4.fld.fs_gintmsk.discint = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "DISCINT"); + state->u.f4.fld.fs_gintmsk.srqim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "SRQIM"); + state->u.f4.fld.fs_gintmsk.wuim = cm_object_get_child_by_name(state->u.f4.reg.fs_gintmsk, "WUIM"); + + // FS_GRXSTSR_Device bitfields. + state->u.f4.fld.fs_grxstsr_device.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "EPNUM"); + state->u.f4.fld.fs_grxstsr_device.bcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "BCNT"); + state->u.f4.fld.fs_grxstsr_device.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "DPID"); + state->u.f4.fld.fs_grxstsr_device.pktsts = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "PKTSTS"); + state->u.f4.fld.fs_grxstsr_device.frmnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_device, "FRMNUM"); + + // FS_GRXSTSR_Host bitfields. + state->u.f4.fld.fs_grxstsr_host.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "EPNUM"); + state->u.f4.fld.fs_grxstsr_host.bcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "BCNT"); + state->u.f4.fld.fs_grxstsr_host.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "DPID"); + state->u.f4.fld.fs_grxstsr_host.pktsts = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "PKTSTS"); + state->u.f4.fld.fs_grxstsr_host.frmnum = cm_object_get_child_by_name(state->u.f4.reg.fs_grxstsr_host, "FRMNUM"); + + // FS_GRXFSIZ bitfields. + state->u.f4.fld.fs_grxfsiz.rxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_grxfsiz, "RXFD"); + + // FS_GNPTXFSIZ_Device bitfields. + state->u.f4.fld.fs_gnptxfsiz_device.tx0fsa = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_device, "TX0FSA"); + state->u.f4.fld.fs_gnptxfsiz_device.tx0fd = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_device, "TX0FD"); + + // FS_GNPTXFSIZ_Host bitfields. + state->u.f4.fld.fs_gnptxfsiz_host.nptxfsa = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_host, "NPTXFSA"); + state->u.f4.fld.fs_gnptxfsiz_host.nptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxfsiz_host, "NPTXFD"); + + // FS_GNPTXSTS bitfields. + state->u.f4.fld.fs_gnptxsts.nptxfsav = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTXFSAV"); + state->u.f4.fld.fs_gnptxsts.nptqxsav = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTQXSAV"); + state->u.f4.fld.fs_gnptxsts.nptxqtop = cm_object_get_child_by_name(state->u.f4.reg.fs_gnptxsts, "NPTXQTOP"); + + // FS_GCCFG bitfields. + state->u.f4.fld.fs_gccfg.pwrdwn = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "PWRDWN"); + state->u.f4.fld.fs_gccfg.vbusasen = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "VBUSASEN"); + state->u.f4.fld.fs_gccfg.vbusbsen = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "VBUSBSEN"); + state->u.f4.fld.fs_gccfg.sofouten = cm_object_get_child_by_name(state->u.f4.reg.fs_gccfg, "SOFOUTEN"); + + // FS_CID bitfields. + state->u.f4.fld.fs_cid.product_id = cm_object_get_child_by_name(state->u.f4.reg.fs_cid, "PRODUCT_ID"); + + // FS_HPTXFSIZ bitfields. + state->u.f4.fld.fs_hptxfsiz.ptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxfsiz, "PTXSA"); + state->u.f4.fld.fs_hptxfsiz.ptxfsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxfsiz, "PTXFSIZ"); + + // FS_DIEPTXF1 bitfields. + state->u.f4.fld.fs_dieptxf1.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf1, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf1.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf1, "INEPTXFD"); + + // FS_DIEPTXF2 bitfields. + state->u.f4.fld.fs_dieptxf2.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf2, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf2.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf2, "INEPTXFD"); + + // FS_DIEPTXF3 bitfields. + state->u.f4.fld.fs_dieptxf3.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf3, "INEPTXSA"); + state->u.f4.fld.fs_dieptxf3.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.fs_dieptxf3, "INEPTXFD"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_global_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_global_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_global_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_global_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_global_is_enabled(Object *obj) +{ + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_global_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_global_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_GLOBAL)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_GLOBALState *state = STM32_OTG_FS_GLOBAL_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_GLOBAL"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_fs_global_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_global_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_GLOBALEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_global_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_GLOBAL); +} + +static void stm32_otg_fs_global_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_global_reset_callback; + dc->realize = stm32_otg_fs_global_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_global_is_enabled; +} + +static const TypeInfo stm32_otg_fs_global_type_info = { + .name = TYPE_STM32_OTG_FS_GLOBAL, + .parent = TYPE_STM32_OTG_FS_GLOBAL_PARENT, + .instance_init = stm32_otg_fs_global_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_GLOBALState), + .class_init = stm32_otg_fs_global_class_init_callback, + .class_size = sizeof(STM32OTG_FS_GLOBALClass) }; + +static void stm32_otg_fs_global_register_types(void) +{ + type_register_static(&stm32_otg_fs_global_type_info); +} + +type_init(stm32_otg_fs_global_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_global.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_global.h new file mode 100644 index 0000000000..5dabd26c69 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_global.h @@ -0,0 +1,309 @@ +/* + * STM32 - OTG_FS_GLOBAL (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_GLOBAL_H_ +#define STM32_OTG_FS_GLOBAL_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_GLOBAL DEVICE_PATH_STM32 "OTG_FS_GLOBAL" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_GLOBAL TYPE_STM32_PREFIX "otg_fs_global" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_GLOBAL_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_GLOBALParentClass; +typedef PeripheralState STM32OTG_FS_GLOBALParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_GLOBAL_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_GLOBALClass, (obj), TYPE_STM32_OTG_FS_GLOBAL) +#define STM32_OTG_FS_GLOBAL_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_GLOBALClass, (klass), TYPE_STM32_OTG_FS_GLOBAL) + +typedef struct { + // private: + STM32OTG_FS_GLOBALParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_GLOBALClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_GLOBAL_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_GLOBALState, (obj), TYPE_STM32_OTG_FS_GLOBAL) + +typedef struct { + // private: + STM32OTG_FS_GLOBALParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_GLOBAL (USB on the go full speed) registers. + struct { + Object *fs_gotgctl; // 0x0 (OTG_FS control and status register (OTG_FS_GOTGCTL)) + Object *fs_gotgint; // 0x4 (OTG_FS interrupt register (OTG_FS_GOTGINT)) + Object *fs_gahbcfg; // 0x8 (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) + Object *fs_gusbcfg; // 0xC (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) + Object *fs_grstctl; // 0x10 (OTG_FS reset register (OTG_FS_GRSTCTL)) + Object *fs_gintsts; // 0x14 (OTG_FS core interrupt register (OTG_FS_GINTSTS)) + Object *fs_gintmsk; // 0x18 (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) + Object *fs_grxstsr_device; // 0x1C (OTG_FS Receive status debug read(Device mode)) + Object *fs_grxstsr_host; // 0x1C (OTG_FS Receive status debug read(Host mode)) + Object *fs_grxfsiz; // 0x24 (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) + Object *fs_gnptxfsiz_device; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Device mode)) + Object *fs_gnptxfsiz_host; // 0x28 (OTG_FS non-periodic transmit FIFO size register (Host mode)) + Object *fs_gnptxsts; // 0x2C (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) + Object *fs_gccfg; // 0x38 (OTG_FS general core configuration register (OTG_FS_GCCFG)) + Object *fs_cid; // 0x3C (Core ID register) + Object *fs_hptxfsiz; // 0x100 (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) + Object *fs_dieptxf1; // 0x104 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) + Object *fs_dieptxf2; // 0x108 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) + Object *fs_dieptxf3; // 0x10C (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) + } reg; + + struct { + + // FS_GOTGCTL (OTG_FS control and status register (OTG_FS_GOTGCTL)) bitfields. + struct { + Object *srqscs; // [0:0] Session request success + Object *srq; // [1:1] Session request + Object *hngscs; // [8:8] Host negotiation success + Object *hnprq; // [9:9] HNP request + Object *hshnpen; // [10:10] Host set HNP enable + Object *dhnpen; // [11:11] Device HNP enabled + Object *cidsts; // [16:16] Connector ID status + Object *dbct; // [17:17] Long/short debounce time + Object *asvld; // [18:18] A-session valid + Object *bsvld; // [19:19] B-session valid + } fs_gotgctl; + + // FS_GOTGINT (OTG_FS interrupt register (OTG_FS_GOTGINT)) bitfields. + struct { + Object *sedet; // [2:2] Session end detected + Object *srsschg; // [8:8] Session request success status change + Object *hnsschg; // [9:9] Host negotiation success status change + Object *hngdet; // [17:17] Host negotiation detected + Object *adtochg; // [18:18] A-device timeout change + Object *dbcdne; // [19:19] Debounce done + } fs_gotgint; + + // FS_GAHBCFG (OTG_FS AHB configuration register (OTG_FS_GAHBCFG)) bitfields. + struct { + Object *gint; // [0:0] Global interrupt mask + Object *txfelvl; // [7:7] TxFIFO empty level + Object *ptxfelvl; // [8:8] Periodic TxFIFO empty level + } fs_gahbcfg; + + // FS_GUSBCFG (OTG_FS USB configuration register (OTG_FS_GUSBCFG)) bitfields. + struct { + Object *tocal; // [0:2] FS timeout calibration + Object *physel; // [6:6] Full Speed serial transceiver select + Object *srpcap; // [8:8] SRP-capable + Object *hnpcap; // [9:9] HNP-capable + Object *trdt; // [10:13] USB turnaround time + Object *fhmod; // [29:29] Force host mode + Object *fdmod; // [30:30] Force device mode + Object *ctxpkt; // [31:31] Corrupt Tx packet + } fs_gusbcfg; + + // FS_GRSTCTL (OTG_FS reset register (OTG_FS_GRSTCTL)) bitfields. + struct { + Object *csrst; // [0:0] Core soft reset + Object *hsrst; // [1:1] HCLK soft reset + Object *fcrst; // [2:2] Host frame counter reset + Object *rxfflsh; // [4:4] RxFIFO flush + Object *txfflsh; // [5:5] TxFIFO flush + Object *txfnum; // [6:10] TxFIFO number + Object *ahbidl; // [31:31] AHB master idle + } fs_grstctl; + + // FS_GINTSTS (OTG_FS core interrupt register (OTG_FS_GINTSTS)) bitfields. + struct { + Object *cmod; // [0:0] Current mode of operation + Object *mmis; // [1:1] Mode mismatch interrupt + Object *otgint; // [2:2] OTG interrupt + Object *sof; // [3:3] Start of frame + Object *rxflvl; // [4:4] RxFIFO non-empty + Object *nptxfe; // [5:5] Non-periodic TxFIFO empty + Object *ginakeff; // [6:6] Global IN non-periodic NAK effective + Object *goutnakeff; // [7:7] Global OUT NAK effective + Object *esusp; // [10:10] Early suspend + Object *usbsusp; // [11:11] USB suspend + Object *usbrst; // [12:12] USB reset + Object *enumdne; // [13:13] Enumeration done + Object *isoodrp; // [14:14] Isochronous OUT packet dropped interrupt + Object *eopf; // [15:15] End of periodic frame interrupt + Object *iepint; // [18:18] IN endpoint interrupt + Object *oepint; // [19:19] OUT endpoint interrupt + Object *iisoixfr; // [20:20] Incomplete isochronous IN transfer + Object *ipxfr_incompisoout; // [21:21] Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + Object *hprtint; // [24:24] Host port interrupt + Object *hcint; // [25:25] Host channels interrupt + Object *ptxfe; // [26:26] Periodic TxFIFO empty + Object *cidschg; // [28:28] Connector ID status change + Object *discint; // [29:29] Disconnect detected interrupt + Object *srqint; // [30:30] Session request/new session detected interrupt + Object *wkupint; // [31:31] Resume/remote wakeup detected interrupt + } fs_gintsts; + + // FS_GINTMSK (OTG_FS interrupt mask register (OTG_FS_GINTMSK)) bitfields. + struct { + Object *mmism; // [1:1] Mode mismatch interrupt mask + Object *otgint; // [2:2] OTG interrupt mask + Object *sofm; // [3:3] Start of frame mask + Object *rxflvlm; // [4:4] Receive FIFO non-empty mask + Object *nptxfem; // [5:5] Non-periodic TxFIFO empty mask + Object *ginakeffm; // [6:6] Global non-periodic IN NAK effective mask + Object *gonakeffm; // [7:7] Global OUT NAK effective mask + Object *esuspm; // [10:10] Early suspend mask + Object *usbsuspm; // [11:11] USB suspend mask + Object *usbrst; // [12:12] USB reset mask + Object *enumdnem; // [13:13] Enumeration done mask + Object *isoodrpm; // [14:14] Isochronous OUT packet dropped interrupt mask + Object *eopfm; // [15:15] End of periodic frame interrupt mask + Object *epmism; // [17:17] Endpoint mismatch interrupt mask + Object *iepint; // [18:18] IN endpoints interrupt mask + Object *oepint; // [19:19] OUT endpoints interrupt mask + Object *iisoixfrm; // [20:20] Incomplete isochronous IN transfer mask + Object *ipxfrm_iisooxfrm; // [21:21] Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + Object *prtim; // [24:24] Host port interrupt mask + Object *hcim; // [25:25] Host channels interrupt mask + Object *ptxfem; // [26:26] Periodic TxFIFO empty mask + Object *cidschgm; // [28:28] Connector ID status change mask + Object *discint; // [29:29] Disconnect detected interrupt mask + Object *srqim; // [30:30] Session request/new session detected interrupt mask + Object *wuim; // [31:31] Resume/remote wakeup detected interrupt mask + } fs_gintmsk; + + // FS_GRXSTSR_Device (OTG_FS Receive status debug read(Device mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_device; + + // FS_GRXSTSR_Host (OTG_FS Receive status debug read(Host mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } fs_grxstsr_host; + + // FS_GRXFSIZ (OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)) bitfields. + struct { + Object *rxfd; // [0:15] RxFIFO depth + } fs_grxfsiz; + + // FS_GNPTXFSIZ_Device (OTG_FS non-periodic transmit FIFO size register (Device mode)) bitfields. + struct { + Object *tx0fsa; // [0:15] Endpoint 0 transmit RAM start address + Object *tx0fd; // [16:31] Endpoint 0 TxFIFO depth + } fs_gnptxfsiz_device; + + // FS_GNPTXFSIZ_Host (OTG_FS non-periodic transmit FIFO size register (Host mode)) bitfields. + struct { + Object *nptxfsa; // [0:15] Non-periodic transmit RAM start address + Object *nptxfd; // [16:31] Non-periodic TxFIFO depth + } fs_gnptxfsiz_host; + + // FS_GNPTXSTS (OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)) bitfields. + struct { + Object *nptxfsav; // [0:15] Non-periodic TxFIFO space available + Object *nptqxsav; // [16:23] Non-periodic transmit request queue space available + Object *nptxqtop; // [24:30] Top of the non-periodic transmit request queue + } fs_gnptxsts; + + // FS_GCCFG (OTG_FS general core configuration register (OTG_FS_GCCFG)) bitfields. + struct { + Object *pwrdwn; // [16:16] Power down + Object *vbusasen; // [18:18] Enable the VBUS sensing device + Object *vbusbsen; // [19:19] Enable the VBUS sensing device + Object *sofouten; // [20:20] SOF output enable + } fs_gccfg; + + // FS_CID (Core ID register) bitfields. + struct { + Object *product_id; // [0:31] Product ID field + } fs_cid; + + // FS_HPTXFSIZ (OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)) bitfields. + struct { + Object *ptxsa; // [0:15] Host periodic TxFIFO start address + Object *ptxfsiz; // [16:31] Host periodic TxFIFO depth + } fs_hptxfsiz; + + // FS_DIEPTXF1 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO2 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf1; + + // FS_DIEPTXF2 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO3 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf2; + + // FS_DIEPTXF3 (OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFO4 transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } fs_dieptxf3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_GLOBALState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_GLOBAL_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_host.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_host.c new file mode 100644 index 0000000000..0a347301b3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_host.c @@ -0,0 +1,630 @@ +/* + * STM32 - OTG_FS_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_fs_host_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_hcfg = cm_object_get_child_by_name(obj, "FS_HCFG"); + state->u.f4.reg.hfir = cm_object_get_child_by_name(obj, "HFIR"); + state->u.f4.reg.fs_hfnum = cm_object_get_child_by_name(obj, "FS_HFNUM"); + state->u.f4.reg.fs_hptxsts = cm_object_get_child_by_name(obj, "FS_HPTXSTS"); + state->u.f4.reg.haint = cm_object_get_child_by_name(obj, "HAINT"); + state->u.f4.reg.haintmsk = cm_object_get_child_by_name(obj, "HAINTMSK"); + state->u.f4.reg.fs_hprt = cm_object_get_child_by_name(obj, "FS_HPRT"); + state->u.f4.reg.fs_hcchar0 = cm_object_get_child_by_name(obj, "FS_HCCHAR0"); + state->u.f4.reg.fs_hcchar1 = cm_object_get_child_by_name(obj, "FS_HCCHAR1"); + state->u.f4.reg.fs_hcchar2 = cm_object_get_child_by_name(obj, "FS_HCCHAR2"); + state->u.f4.reg.fs_hcchar3 = cm_object_get_child_by_name(obj, "FS_HCCHAR3"); + state->u.f4.reg.fs_hcchar4 = cm_object_get_child_by_name(obj, "FS_HCCHAR4"); + state->u.f4.reg.fs_hcchar5 = cm_object_get_child_by_name(obj, "FS_HCCHAR5"); + state->u.f4.reg.fs_hcchar6 = cm_object_get_child_by_name(obj, "FS_HCCHAR6"); + state->u.f4.reg.fs_hcchar7 = cm_object_get_child_by_name(obj, "FS_HCCHAR7"); + state->u.f4.reg.fs_hcint0 = cm_object_get_child_by_name(obj, "FS_HCINT0"); + state->u.f4.reg.fs_hcint1 = cm_object_get_child_by_name(obj, "FS_HCINT1"); + state->u.f4.reg.fs_hcint2 = cm_object_get_child_by_name(obj, "FS_HCINT2"); + state->u.f4.reg.fs_hcint3 = cm_object_get_child_by_name(obj, "FS_HCINT3"); + state->u.f4.reg.fs_hcint4 = cm_object_get_child_by_name(obj, "FS_HCINT4"); + state->u.f4.reg.fs_hcint5 = cm_object_get_child_by_name(obj, "FS_HCINT5"); + state->u.f4.reg.fs_hcint6 = cm_object_get_child_by_name(obj, "FS_HCINT6"); + state->u.f4.reg.fs_hcint7 = cm_object_get_child_by_name(obj, "FS_HCINT7"); + state->u.f4.reg.fs_hcintmsk0 = cm_object_get_child_by_name(obj, "FS_HCINTMSK0"); + state->u.f4.reg.fs_hcintmsk1 = cm_object_get_child_by_name(obj, "FS_HCINTMSK1"); + state->u.f4.reg.fs_hcintmsk2 = cm_object_get_child_by_name(obj, "FS_HCINTMSK2"); + state->u.f4.reg.fs_hcintmsk3 = cm_object_get_child_by_name(obj, "FS_HCINTMSK3"); + state->u.f4.reg.fs_hcintmsk4 = cm_object_get_child_by_name(obj, "FS_HCINTMSK4"); + state->u.f4.reg.fs_hcintmsk5 = cm_object_get_child_by_name(obj, "FS_HCINTMSK5"); + state->u.f4.reg.fs_hcintmsk6 = cm_object_get_child_by_name(obj, "FS_HCINTMSK6"); + state->u.f4.reg.fs_hcintmsk7 = cm_object_get_child_by_name(obj, "FS_HCINTMSK7"); + state->u.f4.reg.fs_hctsiz0 = cm_object_get_child_by_name(obj, "FS_HCTSIZ0"); + state->u.f4.reg.fs_hctsiz1 = cm_object_get_child_by_name(obj, "FS_HCTSIZ1"); + state->u.f4.reg.fs_hctsiz2 = cm_object_get_child_by_name(obj, "FS_HCTSIZ2"); + state->u.f4.reg.fs_hctsiz3 = cm_object_get_child_by_name(obj, "FS_HCTSIZ3"); + state->u.f4.reg.fs_hctsiz4 = cm_object_get_child_by_name(obj, "FS_HCTSIZ4"); + state->u.f4.reg.fs_hctsiz5 = cm_object_get_child_by_name(obj, "FS_HCTSIZ5"); + state->u.f4.reg.fs_hctsiz6 = cm_object_get_child_by_name(obj, "FS_HCTSIZ6"); + state->u.f4.reg.fs_hctsiz7 = cm_object_get_child_by_name(obj, "FS_HCTSIZ7"); + + + // FS_HCFG bitfields. + state->u.f4.fld.fs_hcfg.fslspcs = cm_object_get_child_by_name(state->u.f4.reg.fs_hcfg, "FSLSPCS"); + state->u.f4.fld.fs_hcfg.fslss = cm_object_get_child_by_name(state->u.f4.reg.fs_hcfg, "FSLSS"); + + // HFIR bitfields. + state->u.f4.fld.hfir.frivl = cm_object_get_child_by_name(state->u.f4.reg.hfir, "FRIVL"); + + // FS_HFNUM bitfields. + state->u.f4.fld.fs_hfnum.frnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hfnum, "FRNUM"); + state->u.f4.fld.fs_hfnum.ftrem = cm_object_get_child_by_name(state->u.f4.reg.fs_hfnum, "FTREM"); + + // FS_HPTXSTS bitfields. + state->u.f4.fld.fs_hptxsts.ptxfsavl = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXFSAVL"); + state->u.f4.fld.fs_hptxsts.ptxqsav = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXQSAV"); + state->u.f4.fld.fs_hptxsts.ptxqtop = cm_object_get_child_by_name(state->u.f4.reg.fs_hptxsts, "PTXQTOP"); + + // HAINT bitfields. + state->u.f4.fld.haint.haint = cm_object_get_child_by_name(state->u.f4.reg.haint, "HAINT"); + + // HAINTMSK bitfields. + state->u.f4.fld.haintmsk.haintm = cm_object_get_child_by_name(state->u.f4.reg.haintmsk, "HAINTM"); + + // FS_HPRT bitfields. + state->u.f4.fld.fs_hprt.pcsts = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PCSTS"); + state->u.f4.fld.fs_hprt.pcdet = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PCDET"); + state->u.f4.fld.fs_hprt.pena = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PENA"); + state->u.f4.fld.fs_hprt.penchng = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PENCHNG"); + state->u.f4.fld.fs_hprt.poca = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "POCA"); + state->u.f4.fld.fs_hprt.pocchng = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "POCCHNG"); + state->u.f4.fld.fs_hprt.pres = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PRES"); + state->u.f4.fld.fs_hprt.psusp = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PSUSP"); + state->u.f4.fld.fs_hprt.prst = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PRST"); + state->u.f4.fld.fs_hprt.plsts = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PLSTS"); + state->u.f4.fld.fs_hprt.ppwr = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PPWR"); + state->u.f4.fld.fs_hprt.ptctl = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PTCTL"); + state->u.f4.fld.fs_hprt.pspd = cm_object_get_child_by_name(state->u.f4.reg.fs_hprt, "PSPD"); + + // FS_HCCHAR0 bitfields. + state->u.f4.fld.fs_hcchar0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "MPSIZ"); + state->u.f4.fld.fs_hcchar0.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPNUM"); + state->u.f4.fld.fs_hcchar0.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPDIR"); + state->u.f4.fld.fs_hcchar0.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "LSDEV"); + state->u.f4.fld.fs_hcchar0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "EPTYP"); + state->u.f4.fld.fs_hcchar0.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "MCNT"); + state->u.f4.fld.fs_hcchar0.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "DAD"); + state->u.f4.fld.fs_hcchar0.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "ODDFRM"); + state->u.f4.fld.fs_hcchar0.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "CHDIS"); + state->u.f4.fld.fs_hcchar0.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar0, "CHENA"); + + // FS_HCCHAR1 bitfields. + state->u.f4.fld.fs_hcchar1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "MPSIZ"); + state->u.f4.fld.fs_hcchar1.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPNUM"); + state->u.f4.fld.fs_hcchar1.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPDIR"); + state->u.f4.fld.fs_hcchar1.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "LSDEV"); + state->u.f4.fld.fs_hcchar1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "EPTYP"); + state->u.f4.fld.fs_hcchar1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "MCNT"); + state->u.f4.fld.fs_hcchar1.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "DAD"); + state->u.f4.fld.fs_hcchar1.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "ODDFRM"); + state->u.f4.fld.fs_hcchar1.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "CHDIS"); + state->u.f4.fld.fs_hcchar1.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar1, "CHENA"); + + // FS_HCCHAR2 bitfields. + state->u.f4.fld.fs_hcchar2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "MPSIZ"); + state->u.f4.fld.fs_hcchar2.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPNUM"); + state->u.f4.fld.fs_hcchar2.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPDIR"); + state->u.f4.fld.fs_hcchar2.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "LSDEV"); + state->u.f4.fld.fs_hcchar2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "EPTYP"); + state->u.f4.fld.fs_hcchar2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "MCNT"); + state->u.f4.fld.fs_hcchar2.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "DAD"); + state->u.f4.fld.fs_hcchar2.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "ODDFRM"); + state->u.f4.fld.fs_hcchar2.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "CHDIS"); + state->u.f4.fld.fs_hcchar2.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar2, "CHENA"); + + // FS_HCCHAR3 bitfields. + state->u.f4.fld.fs_hcchar3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "MPSIZ"); + state->u.f4.fld.fs_hcchar3.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPNUM"); + state->u.f4.fld.fs_hcchar3.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPDIR"); + state->u.f4.fld.fs_hcchar3.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "LSDEV"); + state->u.f4.fld.fs_hcchar3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "EPTYP"); + state->u.f4.fld.fs_hcchar3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "MCNT"); + state->u.f4.fld.fs_hcchar3.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "DAD"); + state->u.f4.fld.fs_hcchar3.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "ODDFRM"); + state->u.f4.fld.fs_hcchar3.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "CHDIS"); + state->u.f4.fld.fs_hcchar3.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar3, "CHENA"); + + // FS_HCCHAR4 bitfields. + state->u.f4.fld.fs_hcchar4.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "MPSIZ"); + state->u.f4.fld.fs_hcchar4.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPNUM"); + state->u.f4.fld.fs_hcchar4.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPDIR"); + state->u.f4.fld.fs_hcchar4.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "LSDEV"); + state->u.f4.fld.fs_hcchar4.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "EPTYP"); + state->u.f4.fld.fs_hcchar4.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "MCNT"); + state->u.f4.fld.fs_hcchar4.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "DAD"); + state->u.f4.fld.fs_hcchar4.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "ODDFRM"); + state->u.f4.fld.fs_hcchar4.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "CHDIS"); + state->u.f4.fld.fs_hcchar4.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar4, "CHENA"); + + // FS_HCCHAR5 bitfields. + state->u.f4.fld.fs_hcchar5.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "MPSIZ"); + state->u.f4.fld.fs_hcchar5.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPNUM"); + state->u.f4.fld.fs_hcchar5.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPDIR"); + state->u.f4.fld.fs_hcchar5.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "LSDEV"); + state->u.f4.fld.fs_hcchar5.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "EPTYP"); + state->u.f4.fld.fs_hcchar5.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "MCNT"); + state->u.f4.fld.fs_hcchar5.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "DAD"); + state->u.f4.fld.fs_hcchar5.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "ODDFRM"); + state->u.f4.fld.fs_hcchar5.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "CHDIS"); + state->u.f4.fld.fs_hcchar5.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar5, "CHENA"); + + // FS_HCCHAR6 bitfields. + state->u.f4.fld.fs_hcchar6.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "MPSIZ"); + state->u.f4.fld.fs_hcchar6.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPNUM"); + state->u.f4.fld.fs_hcchar6.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPDIR"); + state->u.f4.fld.fs_hcchar6.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "LSDEV"); + state->u.f4.fld.fs_hcchar6.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "EPTYP"); + state->u.f4.fld.fs_hcchar6.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "MCNT"); + state->u.f4.fld.fs_hcchar6.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "DAD"); + state->u.f4.fld.fs_hcchar6.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "ODDFRM"); + state->u.f4.fld.fs_hcchar6.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "CHDIS"); + state->u.f4.fld.fs_hcchar6.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar6, "CHENA"); + + // FS_HCCHAR7 bitfields. + state->u.f4.fld.fs_hcchar7.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "MPSIZ"); + state->u.f4.fld.fs_hcchar7.epnum = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPNUM"); + state->u.f4.fld.fs_hcchar7.epdir = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPDIR"); + state->u.f4.fld.fs_hcchar7.lsdev = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "LSDEV"); + state->u.f4.fld.fs_hcchar7.eptyp = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "EPTYP"); + state->u.f4.fld.fs_hcchar7.mcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "MCNT"); + state->u.f4.fld.fs_hcchar7.dad = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "DAD"); + state->u.f4.fld.fs_hcchar7.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "ODDFRM"); + state->u.f4.fld.fs_hcchar7.chdis = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "CHDIS"); + state->u.f4.fld.fs_hcchar7.chena = cm_object_get_child_by_name(state->u.f4.reg.fs_hcchar7, "CHENA"); + + // FS_HCINT0 bitfields. + state->u.f4.fld.fs_hcint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "XFRC"); + state->u.f4.fld.fs_hcint0.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "CHH"); + state->u.f4.fld.fs_hcint0.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "STALL"); + state->u.f4.fld.fs_hcint0.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "NAK"); + state->u.f4.fld.fs_hcint0.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "ACK"); + state->u.f4.fld.fs_hcint0.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "TXERR"); + state->u.f4.fld.fs_hcint0.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "BBERR"); + state->u.f4.fld.fs_hcint0.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "FRMOR"); + state->u.f4.fld.fs_hcint0.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint0, "DTERR"); + + // FS_HCINT1 bitfields. + state->u.f4.fld.fs_hcint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "XFRC"); + state->u.f4.fld.fs_hcint1.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "CHH"); + state->u.f4.fld.fs_hcint1.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "STALL"); + state->u.f4.fld.fs_hcint1.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "NAK"); + state->u.f4.fld.fs_hcint1.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "ACK"); + state->u.f4.fld.fs_hcint1.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "TXERR"); + state->u.f4.fld.fs_hcint1.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "BBERR"); + state->u.f4.fld.fs_hcint1.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "FRMOR"); + state->u.f4.fld.fs_hcint1.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint1, "DTERR"); + + // FS_HCINT2 bitfields. + state->u.f4.fld.fs_hcint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "XFRC"); + state->u.f4.fld.fs_hcint2.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "CHH"); + state->u.f4.fld.fs_hcint2.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "STALL"); + state->u.f4.fld.fs_hcint2.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "NAK"); + state->u.f4.fld.fs_hcint2.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "ACK"); + state->u.f4.fld.fs_hcint2.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "TXERR"); + state->u.f4.fld.fs_hcint2.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "BBERR"); + state->u.f4.fld.fs_hcint2.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "FRMOR"); + state->u.f4.fld.fs_hcint2.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint2, "DTERR"); + + // FS_HCINT3 bitfields. + state->u.f4.fld.fs_hcint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "XFRC"); + state->u.f4.fld.fs_hcint3.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "CHH"); + state->u.f4.fld.fs_hcint3.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "STALL"); + state->u.f4.fld.fs_hcint3.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "NAK"); + state->u.f4.fld.fs_hcint3.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "ACK"); + state->u.f4.fld.fs_hcint3.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "TXERR"); + state->u.f4.fld.fs_hcint3.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "BBERR"); + state->u.f4.fld.fs_hcint3.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "FRMOR"); + state->u.f4.fld.fs_hcint3.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint3, "DTERR"); + + // FS_HCINT4 bitfields. + state->u.f4.fld.fs_hcint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "XFRC"); + state->u.f4.fld.fs_hcint4.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "CHH"); + state->u.f4.fld.fs_hcint4.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "STALL"); + state->u.f4.fld.fs_hcint4.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "NAK"); + state->u.f4.fld.fs_hcint4.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "ACK"); + state->u.f4.fld.fs_hcint4.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "TXERR"); + state->u.f4.fld.fs_hcint4.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "BBERR"); + state->u.f4.fld.fs_hcint4.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "FRMOR"); + state->u.f4.fld.fs_hcint4.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint4, "DTERR"); + + // FS_HCINT5 bitfields. + state->u.f4.fld.fs_hcint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "XFRC"); + state->u.f4.fld.fs_hcint5.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "CHH"); + state->u.f4.fld.fs_hcint5.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "STALL"); + state->u.f4.fld.fs_hcint5.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "NAK"); + state->u.f4.fld.fs_hcint5.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "ACK"); + state->u.f4.fld.fs_hcint5.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "TXERR"); + state->u.f4.fld.fs_hcint5.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "BBERR"); + state->u.f4.fld.fs_hcint5.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "FRMOR"); + state->u.f4.fld.fs_hcint5.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint5, "DTERR"); + + // FS_HCINT6 bitfields. + state->u.f4.fld.fs_hcint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "XFRC"); + state->u.f4.fld.fs_hcint6.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "CHH"); + state->u.f4.fld.fs_hcint6.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "STALL"); + state->u.f4.fld.fs_hcint6.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "NAK"); + state->u.f4.fld.fs_hcint6.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "ACK"); + state->u.f4.fld.fs_hcint6.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "TXERR"); + state->u.f4.fld.fs_hcint6.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "BBERR"); + state->u.f4.fld.fs_hcint6.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "FRMOR"); + state->u.f4.fld.fs_hcint6.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint6, "DTERR"); + + // FS_HCINT7 bitfields. + state->u.f4.fld.fs_hcint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "XFRC"); + state->u.f4.fld.fs_hcint7.chh = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "CHH"); + state->u.f4.fld.fs_hcint7.stall = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "STALL"); + state->u.f4.fld.fs_hcint7.nak = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "NAK"); + state->u.f4.fld.fs_hcint7.ack = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "ACK"); + state->u.f4.fld.fs_hcint7.txerr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "TXERR"); + state->u.f4.fld.fs_hcint7.bberr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "BBERR"); + state->u.f4.fld.fs_hcint7.frmor = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "FRMOR"); + state->u.f4.fld.fs_hcint7.dterr = cm_object_get_child_by_name(state->u.f4.reg.fs_hcint7, "DTERR"); + + // FS_HCINTMSK0 bitfields. + state->u.f4.fld.fs_hcintmsk0.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "XFRCM"); + state->u.f4.fld.fs_hcintmsk0.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "CHHM"); + state->u.f4.fld.fs_hcintmsk0.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "STALLM"); + state->u.f4.fld.fs_hcintmsk0.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "NAKM"); + state->u.f4.fld.fs_hcintmsk0.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "ACKM"); + state->u.f4.fld.fs_hcintmsk0.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "NYET"); + state->u.f4.fld.fs_hcintmsk0.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "TXERRM"); + state->u.f4.fld.fs_hcintmsk0.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "BBERRM"); + state->u.f4.fld.fs_hcintmsk0.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "FRMORM"); + state->u.f4.fld.fs_hcintmsk0.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk0, "DTERRM"); + + // FS_HCINTMSK1 bitfields. + state->u.f4.fld.fs_hcintmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "XFRCM"); + state->u.f4.fld.fs_hcintmsk1.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "CHHM"); + state->u.f4.fld.fs_hcintmsk1.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "STALLM"); + state->u.f4.fld.fs_hcintmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "NAKM"); + state->u.f4.fld.fs_hcintmsk1.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "ACKM"); + state->u.f4.fld.fs_hcintmsk1.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "NYET"); + state->u.f4.fld.fs_hcintmsk1.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "TXERRM"); + state->u.f4.fld.fs_hcintmsk1.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "BBERRM"); + state->u.f4.fld.fs_hcintmsk1.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "FRMORM"); + state->u.f4.fld.fs_hcintmsk1.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk1, "DTERRM"); + + // FS_HCINTMSK2 bitfields. + state->u.f4.fld.fs_hcintmsk2.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "XFRCM"); + state->u.f4.fld.fs_hcintmsk2.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "CHHM"); + state->u.f4.fld.fs_hcintmsk2.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "STALLM"); + state->u.f4.fld.fs_hcintmsk2.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "NAKM"); + state->u.f4.fld.fs_hcintmsk2.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "ACKM"); + state->u.f4.fld.fs_hcintmsk2.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "NYET"); + state->u.f4.fld.fs_hcintmsk2.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "TXERRM"); + state->u.f4.fld.fs_hcintmsk2.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "BBERRM"); + state->u.f4.fld.fs_hcintmsk2.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "FRMORM"); + state->u.f4.fld.fs_hcintmsk2.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk2, "DTERRM"); + + // FS_HCINTMSK3 bitfields. + state->u.f4.fld.fs_hcintmsk3.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "XFRCM"); + state->u.f4.fld.fs_hcintmsk3.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "CHHM"); + state->u.f4.fld.fs_hcintmsk3.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "STALLM"); + state->u.f4.fld.fs_hcintmsk3.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "NAKM"); + state->u.f4.fld.fs_hcintmsk3.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "ACKM"); + state->u.f4.fld.fs_hcintmsk3.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "NYET"); + state->u.f4.fld.fs_hcintmsk3.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "TXERRM"); + state->u.f4.fld.fs_hcintmsk3.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "BBERRM"); + state->u.f4.fld.fs_hcintmsk3.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "FRMORM"); + state->u.f4.fld.fs_hcintmsk3.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk3, "DTERRM"); + + // FS_HCINTMSK4 bitfields. + state->u.f4.fld.fs_hcintmsk4.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "XFRCM"); + state->u.f4.fld.fs_hcintmsk4.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "CHHM"); + state->u.f4.fld.fs_hcintmsk4.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "STALLM"); + state->u.f4.fld.fs_hcintmsk4.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "NAKM"); + state->u.f4.fld.fs_hcintmsk4.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "ACKM"); + state->u.f4.fld.fs_hcintmsk4.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "NYET"); + state->u.f4.fld.fs_hcintmsk4.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "TXERRM"); + state->u.f4.fld.fs_hcintmsk4.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "BBERRM"); + state->u.f4.fld.fs_hcintmsk4.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "FRMORM"); + state->u.f4.fld.fs_hcintmsk4.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk4, "DTERRM"); + + // FS_HCINTMSK5 bitfields. + state->u.f4.fld.fs_hcintmsk5.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "XFRCM"); + state->u.f4.fld.fs_hcintmsk5.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "CHHM"); + state->u.f4.fld.fs_hcintmsk5.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "STALLM"); + state->u.f4.fld.fs_hcintmsk5.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "NAKM"); + state->u.f4.fld.fs_hcintmsk5.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "ACKM"); + state->u.f4.fld.fs_hcintmsk5.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "NYET"); + state->u.f4.fld.fs_hcintmsk5.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "TXERRM"); + state->u.f4.fld.fs_hcintmsk5.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "BBERRM"); + state->u.f4.fld.fs_hcintmsk5.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "FRMORM"); + state->u.f4.fld.fs_hcintmsk5.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk5, "DTERRM"); + + // FS_HCINTMSK6 bitfields. + state->u.f4.fld.fs_hcintmsk6.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "XFRCM"); + state->u.f4.fld.fs_hcintmsk6.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "CHHM"); + state->u.f4.fld.fs_hcintmsk6.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "STALLM"); + state->u.f4.fld.fs_hcintmsk6.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "NAKM"); + state->u.f4.fld.fs_hcintmsk6.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "ACKM"); + state->u.f4.fld.fs_hcintmsk6.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "NYET"); + state->u.f4.fld.fs_hcintmsk6.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "TXERRM"); + state->u.f4.fld.fs_hcintmsk6.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "BBERRM"); + state->u.f4.fld.fs_hcintmsk6.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "FRMORM"); + state->u.f4.fld.fs_hcintmsk6.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk6, "DTERRM"); + + // FS_HCINTMSK7 bitfields. + state->u.f4.fld.fs_hcintmsk7.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "XFRCM"); + state->u.f4.fld.fs_hcintmsk7.chhm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "CHHM"); + state->u.f4.fld.fs_hcintmsk7.stallm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "STALLM"); + state->u.f4.fld.fs_hcintmsk7.nakm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "NAKM"); + state->u.f4.fld.fs_hcintmsk7.ackm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "ACKM"); + state->u.f4.fld.fs_hcintmsk7.nyet = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "NYET"); + state->u.f4.fld.fs_hcintmsk7.txerrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "TXERRM"); + state->u.f4.fld.fs_hcintmsk7.bberrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "BBERRM"); + state->u.f4.fld.fs_hcintmsk7.frmorm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "FRMORM"); + state->u.f4.fld.fs_hcintmsk7.dterrm = cm_object_get_child_by_name(state->u.f4.reg.fs_hcintmsk7, "DTERRM"); + + // FS_HCTSIZ0 bitfields. + state->u.f4.fld.fs_hctsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "PKTCNT"); + state->u.f4.fld.fs_hctsiz0.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz0, "DPID"); + + // FS_HCTSIZ1 bitfields. + state->u.f4.fld.fs_hctsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "PKTCNT"); + state->u.f4.fld.fs_hctsiz1.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz1, "DPID"); + + // FS_HCTSIZ2 bitfields. + state->u.f4.fld.fs_hctsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "PKTCNT"); + state->u.f4.fld.fs_hctsiz2.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz2, "DPID"); + + // FS_HCTSIZ3 bitfields. + state->u.f4.fld.fs_hctsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "PKTCNT"); + state->u.f4.fld.fs_hctsiz3.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz3, "DPID"); + + // FS_HCTSIZ4 bitfields. + state->u.f4.fld.fs_hctsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "PKTCNT"); + state->u.f4.fld.fs_hctsiz4.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz4, "DPID"); + + // FS_HCTSIZ5 bitfields. + state->u.f4.fld.fs_hctsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz5.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "PKTCNT"); + state->u.f4.fld.fs_hctsiz5.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz5, "DPID"); + + // FS_HCTSIZ6 bitfields. + state->u.f4.fld.fs_hctsiz6.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz6.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "PKTCNT"); + state->u.f4.fld.fs_hctsiz6.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz6, "DPID"); + + // FS_HCTSIZ7 bitfields. + state->u.f4.fld.fs_hctsiz7.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "XFRSIZ"); + state->u.f4.fld.fs_hctsiz7.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "PKTCNT"); + state->u.f4.fld.fs_hctsiz7.dpid = cm_object_get_child_by_name(state->u.f4.reg.fs_hctsiz7, "DPID"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_host_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_host_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_host_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_host_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_host_is_enabled(Object *obj) +{ + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_host_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_host_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_HOST)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_HOSTState *state = STM32_OTG_FS_HOST_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_HOST"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_fs_host_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_host_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_HOSTEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_host_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_HOST); +} + +static void stm32_otg_fs_host_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_host_reset_callback; + dc->realize = stm32_otg_fs_host_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_host_is_enabled; +} + +static const TypeInfo stm32_otg_fs_host_type_info = { + .name = TYPE_STM32_OTG_FS_HOST, + .parent = TYPE_STM32_OTG_FS_HOST_PARENT, + .instance_init = stm32_otg_fs_host_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_HOSTState), + .class_init = stm32_otg_fs_host_class_init_callback, + .class_size = sizeof(STM32OTG_FS_HOSTClass) }; + +static void stm32_otg_fs_host_register_types(void) +{ + type_register_static(&stm32_otg_fs_host_type_info); +} + +type_init(stm32_otg_fs_host_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_host.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_host.h new file mode 100644 index 0000000000..c08c620d0e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_host.h @@ -0,0 +1,573 @@ +/* + * STM32 - OTG_FS_HOST (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_HOST_H_ +#define STM32_OTG_FS_HOST_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_HOST DEVICE_PATH_STM32 "OTG_FS_HOST" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_HOST TYPE_STM32_PREFIX "otg_fs_host" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_HOST_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_HOSTParentClass; +typedef PeripheralState STM32OTG_FS_HOSTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_HOST_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_HOSTClass, (obj), TYPE_STM32_OTG_FS_HOST) +#define STM32_OTG_FS_HOST_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_HOSTClass, (klass), TYPE_STM32_OTG_FS_HOST) + +typedef struct { + // private: + STM32OTG_FS_HOSTParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_HOSTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_HOST_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_HOSTState, (obj), TYPE_STM32_OTG_FS_HOST) + +typedef struct { + // private: + STM32OTG_FS_HOSTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_HOST (USB on the go full speed) registers. + struct { + Object *fs_hcfg; // 0x0 (OTG_FS host configuration register (OTG_FS_HCFG)) + Object *hfir; // 0x4 (OTG_FS Host frame interval register) + Object *fs_hfnum; // 0x8 (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) + Object *fs_hptxsts; // 0x10 (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) + Object *haint; // 0x14 (OTG_FS Host all channels interrupt register) + Object *haintmsk; // 0x18 (OTG_FS host all channels interrupt mask register) + Object *fs_hprt; // 0x40 (OTG_FS host port control and status register (OTG_FS_HPRT)) + Object *fs_hcchar0; // 0x100 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) + Object *fs_hcchar1; // 0x120 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) + Object *fs_hcchar2; // 0x140 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) + Object *fs_hcchar3; // 0x160 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) + Object *fs_hcchar4; // 0x180 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) + Object *fs_hcchar5; // 0x1A0 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) + Object *fs_hcchar6; // 0x1C0 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) + Object *fs_hcchar7; // 0x1E0 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) + Object *fs_hcint0; // 0x108 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) + Object *fs_hcint1; // 0x128 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) + Object *fs_hcint2; // 0x148 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) + Object *fs_hcint3; // 0x168 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) + Object *fs_hcint4; // 0x188 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) + Object *fs_hcint5; // 0x1A8 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) + Object *fs_hcint6; // 0x1C8 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) + Object *fs_hcint7; // 0x1E8 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) + Object *fs_hcintmsk0; // 0x10C (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) + Object *fs_hcintmsk1; // 0x12C (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) + Object *fs_hcintmsk2; // 0x14C (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) + Object *fs_hcintmsk3; // 0x16C (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) + Object *fs_hcintmsk4; // 0x18C (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) + Object *fs_hcintmsk5; // 0x1AC (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) + Object *fs_hcintmsk6; // 0x1CC (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) + Object *fs_hcintmsk7; // 0x1EC (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) + Object *fs_hctsiz0; // 0x110 (OTG_FS host channel-0 transfer size register) + Object *fs_hctsiz1; // 0x130 (OTG_FS host channel-1 transfer size register) + Object *fs_hctsiz2; // 0x150 (OTG_FS host channel-2 transfer size register) + Object *fs_hctsiz3; // 0x170 (OTG_FS host channel-3 transfer size register) + Object *fs_hctsiz4; // 0x190 (OTG_FS host channel-x transfer size register) + Object *fs_hctsiz5; // 0x1B0 (OTG_FS host channel-5 transfer size register) + Object *fs_hctsiz6; // 0x1D0 (OTG_FS host channel-6 transfer size register) + Object *fs_hctsiz7; // 0x1F0 (OTG_FS host channel-7 transfer size register) + } reg; + + struct { + + // FS_HCFG (OTG_FS host configuration register (OTG_FS_HCFG)) bitfields. + struct { + Object *fslspcs; // [0:1] FS/LS PHY clock select + Object *fslss; // [2:2] FS- and LS-only support + } fs_hcfg; + + // HFIR (OTG_FS Host frame interval register) bitfields. + struct { + Object *frivl; // [0:15] Frame interval + } hfir; + + // FS_HFNUM (OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)) bitfields. + struct { + Object *frnum; // [0:15] Frame number + Object *ftrem; // [16:31] Frame time remaining + } fs_hfnum; + + // FS_HPTXSTS (OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)) bitfields. + struct { + Object *ptxfsavl; // [0:15] Periodic transmit data FIFO space available + Object *ptxqsav; // [16:23] Periodic transmit request queue space available + Object *ptxqtop; // [24:31] Top of the periodic transmit request queue + } fs_hptxsts; + + // HAINT (OTG_FS Host all channels interrupt register) bitfields. + struct { + Object *haint; // [0:15] Channel interrupts + } haint; + + // HAINTMSK (OTG_FS host all channels interrupt mask register) bitfields. + struct { + Object *haintm; // [0:15] Channel interrupt mask + } haintmsk; + + // FS_HPRT (OTG_FS host port control and status register (OTG_FS_HPRT)) bitfields. + struct { + Object *pcsts; // [0:0] Port connect status + Object *pcdet; // [1:1] Port connect detected + Object *pena; // [2:2] Port enable + Object *penchng; // [3:3] Port enable/disable change + Object *poca; // [4:4] Port overcurrent active + Object *pocchng; // [5:5] Port overcurrent change + Object *pres; // [6:6] Port resume + Object *psusp; // [7:7] Port suspend + Object *prst; // [8:8] Port reset + Object *plsts; // [10:11] Port line status + Object *ppwr; // [12:12] Port power + Object *ptctl; // [13:16] Port test control + Object *pspd; // [17:18] Port speed + } fs_hprt; + + // FS_HCCHAR0 (OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar0; + + // FS_HCCHAR1 (OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar1; + + // FS_HCCHAR2 (OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar2; + + // FS_HCCHAR3 (OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar3; + + // FS_HCCHAR4 (OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar4; + + // FS_HCCHAR5 (OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar5; + + // FS_HCCHAR6 (OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar6; + + // FS_HCCHAR7 (OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mcnt; // [20:21] Multicount + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } fs_hcchar7; + + // FS_HCINT0 (OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint0; + + // FS_HCINT1 (OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint1; + + // FS_HCINT2 (OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint2; + + // FS_HCINT3 (OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint3; + + // FS_HCINT4 (OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint4; + + // FS_HCINT5 (OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint5; + + // FS_HCINT6 (OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint6; + + // FS_HCINT7 (OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } fs_hcint7; + + // FS_HCINTMSK0 (OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk0; + + // FS_HCINTMSK1 (OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk1; + + // FS_HCINTMSK2 (OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk2; + + // FS_HCINTMSK3 (OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk3; + + // FS_HCINTMSK4 (OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk4; + + // FS_HCINTMSK5 (OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk5; + + // FS_HCINTMSK6 (OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk6; + + // FS_HCINTMSK7 (OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } fs_hcintmsk7; + + // FS_HCTSIZ0 (OTG_FS host channel-0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz0; + + // FS_HCTSIZ1 (OTG_FS host channel-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz1; + + // FS_HCTSIZ2 (OTG_FS host channel-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz2; + + // FS_HCTSIZ3 (OTG_FS host channel-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz3; + + // FS_HCTSIZ4 (OTG_FS host channel-x transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz4; + + // FS_HCTSIZ5 (OTG_FS host channel-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz5; + + // FS_HCTSIZ6 (OTG_FS host channel-6 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz6; + + // FS_HCTSIZ7 (OTG_FS host channel-7 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } fs_hctsiz7; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_HOSTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_HOST_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_pwrclk.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_pwrclk.c new file mode 100644 index 0000000000..bf8867e84d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_pwrclk.c @@ -0,0 +1,240 @@ +/* + * STM32 - OTG_FS_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_fs_pwrclk_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.fs_pcgcctl = cm_object_get_child_by_name(obj, "FS_PCGCCTL"); + + + // FS_PCGCCTL bitfields. + state->u.f4.fld.fs_pcgcctl.stppclk = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "STPPCLK"); + state->u.f4.fld.fs_pcgcctl.gatehclk = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "GATEHCLK"); + state->u.f4.fld.fs_pcgcctl.physusp = cm_object_get_child_by_name(state->u.f4.reg.fs_pcgcctl, "PHYSUSP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_fs_pwrclk_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_fs_pwrclk_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_fs_pwrclk_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_fs_pwrclk_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_fs_pwrclk_is_enabled(Object *obj) +{ + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_fs_pwrclk_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_fs_pwrclk_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_FS_PWRCLK)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_FS_PWRCLKState *state = STM32_OTG_FS_PWRCLK_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_FS_PWRCLK"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_fs_pwrclk_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_fs_pwrclk_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_FS_PWRCLKEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_fs_pwrclk_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_FS_PWRCLK); +} + +static void stm32_otg_fs_pwrclk_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_fs_pwrclk_reset_callback; + dc->realize = stm32_otg_fs_pwrclk_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_fs_pwrclk_is_enabled; +} + +static const TypeInfo stm32_otg_fs_pwrclk_type_info = { + .name = TYPE_STM32_OTG_FS_PWRCLK, + .parent = TYPE_STM32_OTG_FS_PWRCLK_PARENT, + .instance_init = stm32_otg_fs_pwrclk_instance_init_callback, + .instance_size = sizeof(STM32OTG_FS_PWRCLKState), + .class_init = stm32_otg_fs_pwrclk_class_init_callback, + .class_size = sizeof(STM32OTG_FS_PWRCLKClass) }; + +static void stm32_otg_fs_pwrclk_register_types(void) +{ + type_register_static(&stm32_otg_fs_pwrclk_type_info); +} + +type_init(stm32_otg_fs_pwrclk_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_pwrclk.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_pwrclk.h new file mode 100644 index 0000000000..71af66e39b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_fs_pwrclk.h @@ -0,0 +1,107 @@ +/* + * STM32 - OTG_FS_PWRCLK (USB on the go full speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_FS_PWRCLK_H_ +#define STM32_OTG_FS_PWRCLK_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_FS_PWRCLK DEVICE_PATH_STM32 "OTG_FS_PWRCLK" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_FS_PWRCLK TYPE_STM32_PREFIX "otg_fs_pwrclk" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_FS_PWRCLK_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_FS_PWRCLKParentClass; +typedef PeripheralState STM32OTG_FS_PWRCLKParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_FS_PWRCLK_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_FS_PWRCLKClass, (obj), TYPE_STM32_OTG_FS_PWRCLK) +#define STM32_OTG_FS_PWRCLK_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_FS_PWRCLKClass, (klass), TYPE_STM32_OTG_FS_PWRCLK) + +typedef struct { + // private: + STM32OTG_FS_PWRCLKParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_FS_PWRCLKClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_FS_PWRCLK_STATE(obj) \ + OBJECT_CHECK(STM32OTG_FS_PWRCLKState, (obj), TYPE_STM32_OTG_FS_PWRCLK) + +typedef struct { + // private: + STM32OTG_FS_PWRCLKParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_FS_PWRCLK (USB on the go full speed) registers. + struct { + Object *fs_pcgcctl; // 0x0 (OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)) + } reg; + + struct { + + // FS_PCGCCTL (OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)) bitfields. + struct { + Object *stppclk; // [0:0] Stop PHY clock + Object *gatehclk; // [1:1] Gate HCLK + Object *physusp; // [4:4] PHY Suspended + } fs_pcgcctl; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_FS_PWRCLKState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_FS_PWRCLK_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_device.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_device.c new file mode 100644 index 0000000000..a7ff93be1d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_device.c @@ -0,0 +1,832 @@ +/* + * STM32 - OTG_HS_DEVICE (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_hs_device_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_dcfg = cm_object_get_child_by_name(obj, "OTG_HS_DCFG"); + state->u.f4.reg.otg_hs_dctl = cm_object_get_child_by_name(obj, "OTG_HS_DCTL"); + state->u.f4.reg.otg_hs_dsts = cm_object_get_child_by_name(obj, "OTG_HS_DSTS"); + state->u.f4.reg.otg_hs_diepmsk = cm_object_get_child_by_name(obj, "OTG_HS_DIEPMSK"); + state->u.f4.reg.otg_hs_doepmsk = cm_object_get_child_by_name(obj, "OTG_HS_DOEPMSK"); + state->u.f4.reg.otg_hs_daint = cm_object_get_child_by_name(obj, "OTG_HS_DAINT"); + state->u.f4.reg.otg_hs_daintmsk = cm_object_get_child_by_name(obj, "OTG_HS_DAINTMSK"); + state->u.f4.reg.otg_hs_dvbusdis = cm_object_get_child_by_name(obj, "OTG_HS_DVBUSDIS"); + state->u.f4.reg.otg_hs_dvbuspulse = cm_object_get_child_by_name(obj, "OTG_HS_DVBUSPULSE"); + state->u.f4.reg.otg_hs_dthrctl = cm_object_get_child_by_name(obj, "OTG_HS_DTHRCTL"); + state->u.f4.reg.otg_hs_diepempmsk = cm_object_get_child_by_name(obj, "OTG_HS_DIEPEMPMSK"); + state->u.f4.reg.otg_hs_deachint = cm_object_get_child_by_name(obj, "OTG_HS_DEACHINT"); + state->u.f4.reg.otg_hs_deachintmsk = cm_object_get_child_by_name(obj, "OTG_HS_DEACHINTMSK"); + state->u.f4.reg.otg_hs_diepeachmsk1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPEACHMSK1"); + state->u.f4.reg.otg_hs_doepeachmsk1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPEACHMSK1"); + state->u.f4.reg.otg_hs_diepctl0 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL0"); + state->u.f4.reg.otg_hs_diepctl1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL1"); + state->u.f4.reg.otg_hs_diepctl2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL2"); + state->u.f4.reg.otg_hs_diepctl3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL3"); + state->u.f4.reg.otg_hs_diepctl4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL4"); + state->u.f4.reg.otg_hs_diepctl5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL5"); + state->u.f4.reg.otg_hs_diepctl6 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL6"); + state->u.f4.reg.otg_hs_diepctl7 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPCTL7"); + state->u.f4.reg.otg_hs_diepint0 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT0"); + state->u.f4.reg.otg_hs_diepint1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT1"); + state->u.f4.reg.otg_hs_diepint2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT2"); + state->u.f4.reg.otg_hs_diepint3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT3"); + state->u.f4.reg.otg_hs_diepint4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT4"); + state->u.f4.reg.otg_hs_diepint5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT5"); + state->u.f4.reg.otg_hs_diepint6 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT6"); + state->u.f4.reg.otg_hs_diepint7 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPINT7"); + state->u.f4.reg.otg_hs_dieptsiz0 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ0"); + state->u.f4.reg.otg_hs_diepdma1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA1"); + state->u.f4.reg.otg_hs_diepdma2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA2"); + state->u.f4.reg.otg_hs_diepdma3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA3"); + state->u.f4.reg.otg_hs_diepdma4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA4"); + state->u.f4.reg.otg_hs_diepdma5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPDMA5"); + state->u.f4.reg.otg_hs_dtxfsts0 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS0"); + state->u.f4.reg.otg_hs_dtxfsts1 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS1"); + state->u.f4.reg.otg_hs_dtxfsts2 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS2"); + state->u.f4.reg.otg_hs_dtxfsts3 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS3"); + state->u.f4.reg.otg_hs_dtxfsts4 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS4"); + state->u.f4.reg.otg_hs_dtxfsts5 = cm_object_get_child_by_name(obj, "OTG_HS_DTXFSTS5"); + state->u.f4.reg.otg_hs_dieptsiz1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ1"); + state->u.f4.reg.otg_hs_dieptsiz2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ2"); + state->u.f4.reg.otg_hs_dieptsiz3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ3"); + state->u.f4.reg.otg_hs_dieptsiz4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ4"); + state->u.f4.reg.otg_hs_dieptsiz5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTSIZ5"); + state->u.f4.reg.otg_hs_doepctl0 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL0"); + state->u.f4.reg.otg_hs_doepctl1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL1"); + state->u.f4.reg.otg_hs_doepctl2 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL2"); + state->u.f4.reg.otg_hs_doepctl3 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPCTL3"); + state->u.f4.reg.otg_hs_doepint0 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT0"); + state->u.f4.reg.otg_hs_doepint1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT1"); + state->u.f4.reg.otg_hs_doepint2 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT2"); + state->u.f4.reg.otg_hs_doepint3 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT3"); + state->u.f4.reg.otg_hs_doepint4 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT4"); + state->u.f4.reg.otg_hs_doepint5 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT5"); + state->u.f4.reg.otg_hs_doepint6 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT6"); + state->u.f4.reg.otg_hs_doepint7 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPINT7"); + state->u.f4.reg.otg_hs_doeptsiz0 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ0"); + state->u.f4.reg.otg_hs_doeptsiz1 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ1"); + state->u.f4.reg.otg_hs_doeptsiz2 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ2"); + state->u.f4.reg.otg_hs_doeptsiz3 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ3"); + state->u.f4.reg.otg_hs_doeptsiz4 = cm_object_get_child_by_name(obj, "OTG_HS_DOEPTSIZ4"); + + + // OTG_HS_DCFG bitfields. + state->u.f4.fld.otg_hs_dcfg.dspd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "DSPD"); + state->u.f4.fld.otg_hs_dcfg.nzlsohsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "NZLSOHSK"); + state->u.f4.fld.otg_hs_dcfg.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "DAD"); + state->u.f4.fld.otg_hs_dcfg.pfivl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "PFIVL"); + state->u.f4.fld.otg_hs_dcfg.perschivl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dcfg, "PERSCHIVL"); + + // OTG_HS_DCTL bitfields. + state->u.f4.fld.otg_hs_dctl.rwusig = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "RWUSIG"); + state->u.f4.fld.otg_hs_dctl.sdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "SDIS"); + state->u.f4.fld.otg_hs_dctl.ginsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "GINSTS"); + state->u.f4.fld.otg_hs_dctl.gonsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "GONSTS"); + state->u.f4.fld.otg_hs_dctl.tctl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "TCTL"); + state->u.f4.fld.otg_hs_dctl.sginak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "SGINAK"); + state->u.f4.fld.otg_hs_dctl.cginak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "CGINAK"); + state->u.f4.fld.otg_hs_dctl.sgonak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "SGONAK"); + state->u.f4.fld.otg_hs_dctl.cgonak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "CGONAK"); + state->u.f4.fld.otg_hs_dctl.poprgdne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dctl, "POPRGDNE"); + + // OTG_HS_DSTS bitfields. + state->u.f4.fld.otg_hs_dsts.suspsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "SUSPSTS"); + state->u.f4.fld.otg_hs_dsts.enumspd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "ENUMSPD"); + state->u.f4.fld.otg_hs_dsts.eerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "EERR"); + state->u.f4.fld.otg_hs_dsts.fnsof = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dsts, "FNSOF"); + + // OTG_HS_DIEPMSK bitfields. + state->u.f4.fld.otg_hs_diepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "XFRCM"); + state->u.f4.fld.otg_hs_diepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "EPDM"); + state->u.f4.fld.otg_hs_diepmsk.tom = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "TOM"); + state->u.f4.fld.otg_hs_diepmsk.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "ITTXFEMSK"); + state->u.f4.fld.otg_hs_diepmsk.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "INEPNMM"); + state->u.f4.fld.otg_hs_diepmsk.inepnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "INEPNEM"); + state->u.f4.fld.otg_hs_diepmsk.txfurm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "TXFURM"); + state->u.f4.fld.otg_hs_diepmsk.bim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepmsk, "BIM"); + + // OTG_HS_DOEPMSK bitfields. + state->u.f4.fld.otg_hs_doepmsk.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "XFRCM"); + state->u.f4.fld.otg_hs_doepmsk.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "EPDM"); + state->u.f4.fld.otg_hs_doepmsk.stupm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "STUPM"); + state->u.f4.fld.otg_hs_doepmsk.otepdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "OTEPDM"); + state->u.f4.fld.otg_hs_doepmsk.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepmsk.opem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "OPEM"); + state->u.f4.fld.otg_hs_doepmsk.boim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepmsk, "BOIM"); + + // OTG_HS_DAINT bitfields. + state->u.f4.fld.otg_hs_daint.iepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daint, "IEPINT"); + state->u.f4.fld.otg_hs_daint.oepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daint, "OEPINT"); + + // OTG_HS_DAINTMSK bitfields. + state->u.f4.fld.otg_hs_daintmsk.iepm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daintmsk, "IEPM"); + state->u.f4.fld.otg_hs_daintmsk.oepm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_daintmsk, "OEPM"); + + // OTG_HS_DVBUSDIS bitfields. + state->u.f4.fld.otg_hs_dvbusdis.vbusdt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dvbusdis, "VBUSDT"); + + // OTG_HS_DVBUSPULSE bitfields. + state->u.f4.fld.otg_hs_dvbuspulse.dvbusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dvbuspulse, "DVBUSP"); + + // OTG_HS_DTHRCTL bitfields. + state->u.f4.fld.otg_hs_dthrctl.nonisothren = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "NONISOTHREN"); + state->u.f4.fld.otg_hs_dthrctl.isothren = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "ISOTHREN"); + state->u.f4.fld.otg_hs_dthrctl.txthrlen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "TXTHRLEN"); + state->u.f4.fld.otg_hs_dthrctl.rxthren = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "RXTHREN"); + state->u.f4.fld.otg_hs_dthrctl.rxthrlen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "RXTHRLEN"); + state->u.f4.fld.otg_hs_dthrctl.arpen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dthrctl, "ARPEN"); + + // OTG_HS_DIEPEMPMSK bitfields. + state->u.f4.fld.otg_hs_diepempmsk.ineptxfem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepempmsk, "INEPTXFEM"); + + // OTG_HS_DEACHINT bitfields. + state->u.f4.fld.otg_hs_deachint.iep1int = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachint, "IEP1INT"); + state->u.f4.fld.otg_hs_deachint.oep1int = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachint, "OEP1INT"); + + // OTG_HS_DEACHINTMSK bitfields. + state->u.f4.fld.otg_hs_deachintmsk.iep1intm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachintmsk, "IEP1INTM"); + state->u.f4.fld.otg_hs_deachintmsk.oep1intm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_deachintmsk, "OEP1INTM"); + + // OTG_HS_DIEPEACHMSK1 bitfields. + state->u.f4.fld.otg_hs_diepeachmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "XFRCM"); + state->u.f4.fld.otg_hs_diepeachmsk1.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "EPDM"); + state->u.f4.fld.otg_hs_diepeachmsk1.tom = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "TOM"); + state->u.f4.fld.otg_hs_diepeachmsk1.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "ITTXFEMSK"); + state->u.f4.fld.otg_hs_diepeachmsk1.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "INEPNMM"); + state->u.f4.fld.otg_hs_diepeachmsk1.inepnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "INEPNEM"); + state->u.f4.fld.otg_hs_diepeachmsk1.txfurm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "TXFURM"); + state->u.f4.fld.otg_hs_diepeachmsk1.bim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "BIM"); + state->u.f4.fld.otg_hs_diepeachmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepeachmsk1, "NAKM"); + + // OTG_HS_DOEPEACHMSK1 bitfields. + state->u.f4.fld.otg_hs_doepeachmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "XFRCM"); + state->u.f4.fld.otg_hs_doepeachmsk1.epdm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "EPDM"); + state->u.f4.fld.otg_hs_doepeachmsk1.tom = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "TOM"); + state->u.f4.fld.otg_hs_doepeachmsk1.ittxfemsk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "ITTXFEMSK"); + state->u.f4.fld.otg_hs_doepeachmsk1.inepnmm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "INEPNMM"); + state->u.f4.fld.otg_hs_doepeachmsk1.inepnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "INEPNEM"); + state->u.f4.fld.otg_hs_doepeachmsk1.txfurm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "TXFURM"); + state->u.f4.fld.otg_hs_doepeachmsk1.bim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "BIM"); + state->u.f4.fld.otg_hs_doepeachmsk1.berrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "BERRM"); + state->u.f4.fld.otg_hs_doepeachmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "NAKM"); + state->u.f4.fld.otg_hs_doepeachmsk1.nyetm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepeachmsk1, "NYETM"); + + // OTG_HS_DIEPCTL0 bitfields. + state->u.f4.fld.otg_hs_diepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl0.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "Stall"); + state->u.f4.fld.otg_hs_diepctl0.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "CNAK"); + state->u.f4.fld.otg_hs_diepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "SNAK"); + state->u.f4.fld.otg_hs_diepctl0.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl0.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl0, "EPENA"); + + // OTG_HS_DIEPCTL1 bitfields. + state->u.f4.fld.otg_hs_diepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "Stall"); + state->u.f4.fld.otg_hs_diepctl1.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "CNAK"); + state->u.f4.fld.otg_hs_diepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "SNAK"); + state->u.f4.fld.otg_hs_diepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl1.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl1, "EPENA"); + + // OTG_HS_DIEPCTL2 bitfields. + state->u.f4.fld.otg_hs_diepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "Stall"); + state->u.f4.fld.otg_hs_diepctl2.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "CNAK"); + state->u.f4.fld.otg_hs_diepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "SNAK"); + state->u.f4.fld.otg_hs_diepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl2, "EPENA"); + + // OTG_HS_DIEPCTL3 bitfields. + state->u.f4.fld.otg_hs_diepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "Stall"); + state->u.f4.fld.otg_hs_diepctl3.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "CNAK"); + state->u.f4.fld.otg_hs_diepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "SNAK"); + state->u.f4.fld.otg_hs_diepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl3, "EPENA"); + + // OTG_HS_DIEPCTL4 bitfields. + state->u.f4.fld.otg_hs_diepctl4.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl4.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl4.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl4.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl4.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl4.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "Stall"); + state->u.f4.fld.otg_hs_diepctl4.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl4.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "CNAK"); + state->u.f4.fld.otg_hs_diepctl4.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "SNAK"); + state->u.f4.fld.otg_hs_diepctl4.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl4.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl4.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl4.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl4, "EPENA"); + + // OTG_HS_DIEPCTL5 bitfields. + state->u.f4.fld.otg_hs_diepctl5.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl5.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl5.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl5.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl5.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl5.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "Stall"); + state->u.f4.fld.otg_hs_diepctl5.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl5.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "CNAK"); + state->u.f4.fld.otg_hs_diepctl5.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "SNAK"); + state->u.f4.fld.otg_hs_diepctl5.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl5.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl5.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl5.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl5, "EPENA"); + + // OTG_HS_DIEPCTL6 bitfields. + state->u.f4.fld.otg_hs_diepctl6.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl6.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl6.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl6.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl6.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl6.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "Stall"); + state->u.f4.fld.otg_hs_diepctl6.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl6.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "CNAK"); + state->u.f4.fld.otg_hs_diepctl6.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "SNAK"); + state->u.f4.fld.otg_hs_diepctl6.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl6.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl6.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl6.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl6, "EPENA"); + + // OTG_HS_DIEPCTL7 bitfields. + state->u.f4.fld.otg_hs_diepctl7.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "MPSIZ"); + state->u.f4.fld.otg_hs_diepctl7.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "USBAEP"); + state->u.f4.fld.otg_hs_diepctl7.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EONUM_DPID"); + state->u.f4.fld.otg_hs_diepctl7.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "NAKSTS"); + state->u.f4.fld.otg_hs_diepctl7.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EPTYP"); + state->u.f4.fld.otg_hs_diepctl7.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "Stall"); + state->u.f4.fld.otg_hs_diepctl7.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "TXFNUM"); + state->u.f4.fld.otg_hs_diepctl7.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "CNAK"); + state->u.f4.fld.otg_hs_diepctl7.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "SNAK"); + state->u.f4.fld.otg_hs_diepctl7.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_diepctl7.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "SODDFRM"); + state->u.f4.fld.otg_hs_diepctl7.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EPDIS"); + state->u.f4.fld.otg_hs_diepctl7.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepctl7, "EPENA"); + + // OTG_HS_DIEPINT0 bitfields. + state->u.f4.fld.otg_hs_diepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "XFRC"); + state->u.f4.fld.otg_hs_diepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "EPDISD"); + state->u.f4.fld.otg_hs_diepint0.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "TOC"); + state->u.f4.fld.otg_hs_diepint0.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint0.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "INEPNE"); + state->u.f4.fld.otg_hs_diepint0.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "TXFE"); + state->u.f4.fld.otg_hs_diepint0.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint0.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "BNA"); + state->u.f4.fld.otg_hs_diepint0.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint0.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "BERR"); + state->u.f4.fld.otg_hs_diepint0.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint0, "NAK"); + + // OTG_HS_DIEPINT1 bitfields. + state->u.f4.fld.otg_hs_diepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "XFRC"); + state->u.f4.fld.otg_hs_diepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "EPDISD"); + state->u.f4.fld.otg_hs_diepint1.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "TOC"); + state->u.f4.fld.otg_hs_diepint1.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint1.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "INEPNE"); + state->u.f4.fld.otg_hs_diepint1.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "TXFE"); + state->u.f4.fld.otg_hs_diepint1.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint1.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "BNA"); + state->u.f4.fld.otg_hs_diepint1.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint1.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "BERR"); + state->u.f4.fld.otg_hs_diepint1.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint1, "NAK"); + + // OTG_HS_DIEPINT2 bitfields. + state->u.f4.fld.otg_hs_diepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "XFRC"); + state->u.f4.fld.otg_hs_diepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "EPDISD"); + state->u.f4.fld.otg_hs_diepint2.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "TOC"); + state->u.f4.fld.otg_hs_diepint2.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint2.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "INEPNE"); + state->u.f4.fld.otg_hs_diepint2.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "TXFE"); + state->u.f4.fld.otg_hs_diepint2.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint2.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "BNA"); + state->u.f4.fld.otg_hs_diepint2.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint2.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "BERR"); + state->u.f4.fld.otg_hs_diepint2.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint2, "NAK"); + + // OTG_HS_DIEPINT3 bitfields. + state->u.f4.fld.otg_hs_diepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "XFRC"); + state->u.f4.fld.otg_hs_diepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "EPDISD"); + state->u.f4.fld.otg_hs_diepint3.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "TOC"); + state->u.f4.fld.otg_hs_diepint3.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint3.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "INEPNE"); + state->u.f4.fld.otg_hs_diepint3.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "TXFE"); + state->u.f4.fld.otg_hs_diepint3.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint3.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "BNA"); + state->u.f4.fld.otg_hs_diepint3.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint3.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "BERR"); + state->u.f4.fld.otg_hs_diepint3.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint3, "NAK"); + + // OTG_HS_DIEPINT4 bitfields. + state->u.f4.fld.otg_hs_diepint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "XFRC"); + state->u.f4.fld.otg_hs_diepint4.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "EPDISD"); + state->u.f4.fld.otg_hs_diepint4.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "TOC"); + state->u.f4.fld.otg_hs_diepint4.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint4.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "INEPNE"); + state->u.f4.fld.otg_hs_diepint4.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "TXFE"); + state->u.f4.fld.otg_hs_diepint4.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint4.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "BNA"); + state->u.f4.fld.otg_hs_diepint4.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint4.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "BERR"); + state->u.f4.fld.otg_hs_diepint4.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint4, "NAK"); + + // OTG_HS_DIEPINT5 bitfields. + state->u.f4.fld.otg_hs_diepint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "XFRC"); + state->u.f4.fld.otg_hs_diepint5.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "EPDISD"); + state->u.f4.fld.otg_hs_diepint5.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "TOC"); + state->u.f4.fld.otg_hs_diepint5.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint5.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "INEPNE"); + state->u.f4.fld.otg_hs_diepint5.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "TXFE"); + state->u.f4.fld.otg_hs_diepint5.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint5.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "BNA"); + state->u.f4.fld.otg_hs_diepint5.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint5.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "BERR"); + state->u.f4.fld.otg_hs_diepint5.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint5, "NAK"); + + // OTG_HS_DIEPINT6 bitfields. + state->u.f4.fld.otg_hs_diepint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "XFRC"); + state->u.f4.fld.otg_hs_diepint6.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "EPDISD"); + state->u.f4.fld.otg_hs_diepint6.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "TOC"); + state->u.f4.fld.otg_hs_diepint6.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint6.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "INEPNE"); + state->u.f4.fld.otg_hs_diepint6.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "TXFE"); + state->u.f4.fld.otg_hs_diepint6.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint6.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "BNA"); + state->u.f4.fld.otg_hs_diepint6.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint6.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "BERR"); + state->u.f4.fld.otg_hs_diepint6.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint6, "NAK"); + + // OTG_HS_DIEPINT7 bitfields. + state->u.f4.fld.otg_hs_diepint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "XFRC"); + state->u.f4.fld.otg_hs_diepint7.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "EPDISD"); + state->u.f4.fld.otg_hs_diepint7.toc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "TOC"); + state->u.f4.fld.otg_hs_diepint7.ittxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "ITTXFE"); + state->u.f4.fld.otg_hs_diepint7.inepne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "INEPNE"); + state->u.f4.fld.otg_hs_diepint7.txfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "TXFE"); + state->u.f4.fld.otg_hs_diepint7.txfifoudrn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "TXFIFOUDRN"); + state->u.f4.fld.otg_hs_diepint7.bna = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "BNA"); + state->u.f4.fld.otg_hs_diepint7.pktdrpsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "PKTDRPSTS"); + state->u.f4.fld.otg_hs_diepint7.berr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "BERR"); + state->u.f4.fld.otg_hs_diepint7.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepint7, "NAK"); + + // OTG_HS_DIEPTSIZ0 bitfields. + state->u.f4.fld.otg_hs_dieptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz0, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz0, "PKTCNT"); + + // OTG_HS_DIEPDMA1 bitfields. + state->u.f4.fld.otg_hs_diepdma1.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma1, "DMAADDR"); + + // OTG_HS_DIEPDMA2 bitfields. + state->u.f4.fld.otg_hs_diepdma2.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma2, "DMAADDR"); + + // OTG_HS_DIEPDMA3 bitfields. + state->u.f4.fld.otg_hs_diepdma3.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma3, "DMAADDR"); + + // OTG_HS_DIEPDMA4 bitfields. + state->u.f4.fld.otg_hs_diepdma4.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma4, "DMAADDR"); + + // OTG_HS_DIEPDMA5 bitfields. + state->u.f4.fld.otg_hs_diepdma5.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_diepdma5, "DMAADDR"); + + // OTG_HS_DTXFSTS0 bitfields. + state->u.f4.fld.otg_hs_dtxfsts0.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts0, "INEPTFSAV"); + + // OTG_HS_DTXFSTS1 bitfields. + state->u.f4.fld.otg_hs_dtxfsts1.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts1, "INEPTFSAV"); + + // OTG_HS_DTXFSTS2 bitfields. + state->u.f4.fld.otg_hs_dtxfsts2.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts2, "INEPTFSAV"); + + // OTG_HS_DTXFSTS3 bitfields. + state->u.f4.fld.otg_hs_dtxfsts3.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts3, "INEPTFSAV"); + + // OTG_HS_DTXFSTS4 bitfields. + state->u.f4.fld.otg_hs_dtxfsts4.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts4, "INEPTFSAV"); + + // OTG_HS_DTXFSTS5 bitfields. + state->u.f4.fld.otg_hs_dtxfsts5.ineptfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dtxfsts5, "INEPTFSAV"); + + // OTG_HS_DIEPTSIZ1 bitfields. + state->u.f4.fld.otg_hs_dieptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz1, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz1, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz1.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz1, "MCNT"); + + // OTG_HS_DIEPTSIZ2 bitfields. + state->u.f4.fld.otg_hs_dieptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz2, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz2, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz2.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz2, "MCNT"); + + // OTG_HS_DIEPTSIZ3 bitfields. + state->u.f4.fld.otg_hs_dieptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz3, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz3, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz3.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz3, "MCNT"); + + // OTG_HS_DIEPTSIZ4 bitfields. + state->u.f4.fld.otg_hs_dieptsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz4, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz4, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz4.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz4, "MCNT"); + + // OTG_HS_DIEPTSIZ5 bitfields. + state->u.f4.fld.otg_hs_dieptsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz5, "XFRSIZ"); + state->u.f4.fld.otg_hs_dieptsiz5.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz5, "PKTCNT"); + state->u.f4.fld.otg_hs_dieptsiz5.mcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptsiz5, "MCNT"); + + // OTG_HS_DOEPCTL0 bitfields. + state->u.f4.fld.otg_hs_doepctl0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl0.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl0.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl0.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "SNPM"); + state->u.f4.fld.otg_hs_doepctl0.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "Stall"); + state->u.f4.fld.otg_hs_doepctl0.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "CNAK"); + state->u.f4.fld.otg_hs_doepctl0.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "SNAK"); + state->u.f4.fld.otg_hs_doepctl0.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl0.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl0, "EPENA"); + + // OTG_HS_DOEPCTL1 bitfields. + state->u.f4.fld.otg_hs_doepctl1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl1.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl1.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EONUM_DPID"); + state->u.f4.fld.otg_hs_doepctl1.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl1.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SNPM"); + state->u.f4.fld.otg_hs_doepctl1.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "Stall"); + state->u.f4.fld.otg_hs_doepctl1.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "CNAK"); + state->u.f4.fld.otg_hs_doepctl1.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SNAK"); + state->u.f4.fld.otg_hs_doepctl1.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_doepctl1.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "SODDFRM"); + state->u.f4.fld.otg_hs_doepctl1.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl1.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl1, "EPENA"); + + // OTG_HS_DOEPCTL2 bitfields. + state->u.f4.fld.otg_hs_doepctl2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl2.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl2.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EONUM_DPID"); + state->u.f4.fld.otg_hs_doepctl2.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl2.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SNPM"); + state->u.f4.fld.otg_hs_doepctl2.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "Stall"); + state->u.f4.fld.otg_hs_doepctl2.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "CNAK"); + state->u.f4.fld.otg_hs_doepctl2.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SNAK"); + state->u.f4.fld.otg_hs_doepctl2.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_doepctl2.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "SODDFRM"); + state->u.f4.fld.otg_hs_doepctl2.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl2.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl2, "EPENA"); + + // OTG_HS_DOEPCTL3 bitfields. + state->u.f4.fld.otg_hs_doepctl3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "MPSIZ"); + state->u.f4.fld.otg_hs_doepctl3.usbaep = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "USBAEP"); + state->u.f4.fld.otg_hs_doepctl3.eonum_dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EONUM_DPID"); + state->u.f4.fld.otg_hs_doepctl3.naksts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "NAKSTS"); + state->u.f4.fld.otg_hs_doepctl3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EPTYP"); + state->u.f4.fld.otg_hs_doepctl3.snpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SNPM"); + state->u.f4.fld.otg_hs_doepctl3.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "Stall"); + state->u.f4.fld.otg_hs_doepctl3.cnak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "CNAK"); + state->u.f4.fld.otg_hs_doepctl3.snak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SNAK"); + state->u.f4.fld.otg_hs_doepctl3.sd0pid_sevnfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SD0PID_SEVNFRM"); + state->u.f4.fld.otg_hs_doepctl3.soddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "SODDFRM"); + state->u.f4.fld.otg_hs_doepctl3.epdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EPDIS"); + state->u.f4.fld.otg_hs_doepctl3.epena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepctl3, "EPENA"); + + // OTG_HS_DOEPINT0 bitfields. + state->u.f4.fld.otg_hs_doepint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "XFRC"); + state->u.f4.fld.otg_hs_doepint0.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "EPDISD"); + state->u.f4.fld.otg_hs_doepint0.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "STUP"); + state->u.f4.fld.otg_hs_doepint0.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint0.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint0.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint0, "NYET"); + + // OTG_HS_DOEPINT1 bitfields. + state->u.f4.fld.otg_hs_doepint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "XFRC"); + state->u.f4.fld.otg_hs_doepint1.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "EPDISD"); + state->u.f4.fld.otg_hs_doepint1.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "STUP"); + state->u.f4.fld.otg_hs_doepint1.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint1.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint1.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint1, "NYET"); + + // OTG_HS_DOEPINT2 bitfields. + state->u.f4.fld.otg_hs_doepint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "XFRC"); + state->u.f4.fld.otg_hs_doepint2.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "EPDISD"); + state->u.f4.fld.otg_hs_doepint2.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "STUP"); + state->u.f4.fld.otg_hs_doepint2.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint2.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint2.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint2, "NYET"); + + // OTG_HS_DOEPINT3 bitfields. + state->u.f4.fld.otg_hs_doepint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "XFRC"); + state->u.f4.fld.otg_hs_doepint3.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "EPDISD"); + state->u.f4.fld.otg_hs_doepint3.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "STUP"); + state->u.f4.fld.otg_hs_doepint3.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint3.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint3.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint3, "NYET"); + + // OTG_HS_DOEPINT4 bitfields. + state->u.f4.fld.otg_hs_doepint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "XFRC"); + state->u.f4.fld.otg_hs_doepint4.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "EPDISD"); + state->u.f4.fld.otg_hs_doepint4.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "STUP"); + state->u.f4.fld.otg_hs_doepint4.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint4.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint4.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint4, "NYET"); + + // OTG_HS_DOEPINT5 bitfields. + state->u.f4.fld.otg_hs_doepint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "XFRC"); + state->u.f4.fld.otg_hs_doepint5.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "EPDISD"); + state->u.f4.fld.otg_hs_doepint5.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "STUP"); + state->u.f4.fld.otg_hs_doepint5.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint5.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint5.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint5, "NYET"); + + // OTG_HS_DOEPINT6 bitfields. + state->u.f4.fld.otg_hs_doepint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "XFRC"); + state->u.f4.fld.otg_hs_doepint6.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "EPDISD"); + state->u.f4.fld.otg_hs_doepint6.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "STUP"); + state->u.f4.fld.otg_hs_doepint6.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint6.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint6.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint6, "NYET"); + + // OTG_HS_DOEPINT7 bitfields. + state->u.f4.fld.otg_hs_doepint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "XFRC"); + state->u.f4.fld.otg_hs_doepint7.epdisd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "EPDISD"); + state->u.f4.fld.otg_hs_doepint7.stup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "STUP"); + state->u.f4.fld.otg_hs_doepint7.otepdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "OTEPDIS"); + state->u.f4.fld.otg_hs_doepint7.b2bstup = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "B2BSTUP"); + state->u.f4.fld.otg_hs_doepint7.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doepint7, "NYET"); + + // OTG_HS_DOEPTSIZ0 bitfields. + state->u.f4.fld.otg_hs_doeptsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz0, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz0, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz0.stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz0, "STUPCNT"); + + // OTG_HS_DOEPTSIZ1 bitfields. + state->u.f4.fld.otg_hs_doeptsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz1, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz1, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz1.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz1, "RXDPID_STUPCNT"); + + // OTG_HS_DOEPTSIZ2 bitfields. + state->u.f4.fld.otg_hs_doeptsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz2, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz2, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz2.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz2, "RXDPID_STUPCNT"); + + // OTG_HS_DOEPTSIZ3 bitfields. + state->u.f4.fld.otg_hs_doeptsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz3, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz3, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz3.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz3, "RXDPID_STUPCNT"); + + // OTG_HS_DOEPTSIZ4 bitfields. + state->u.f4.fld.otg_hs_doeptsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz4, "XFRSIZ"); + state->u.f4.fld.otg_hs_doeptsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz4, "PKTCNT"); + state->u.f4.fld.otg_hs_doeptsiz4.rxdpid_stupcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_doeptsiz4, "RXDPID_STUPCNT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_device_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_device_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_device_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_device_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_device_is_enabled(Object *obj) +{ + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_device_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_device_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_DEVICE)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_DEVICEState *state = STM32_OTG_HS_DEVICE_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_DEVICE"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_hs_device_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_device_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_DEVICEEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_device_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_DEVICE); +} + +static void stm32_otg_hs_device_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_device_reset_callback; + dc->realize = stm32_otg_hs_device_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_device_is_enabled; +} + +static const TypeInfo stm32_otg_hs_device_type_info = { + .name = TYPE_STM32_OTG_HS_DEVICE, + .parent = TYPE_STM32_OTG_HS_DEVICE_PARENT, + .instance_init = stm32_otg_hs_device_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_DEVICEState), + .class_init = stm32_otg_hs_device_class_init_callback, + .class_size = sizeof(STM32OTG_HS_DEVICEClass) }; + +static void stm32_otg_hs_device_register_types(void) +{ + type_register_static(&stm32_otg_hs_device_type_info); +} + +type_init(stm32_otg_hs_device_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_device.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_device.h new file mode 100644 index 0000000000..85aae4a8a3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_device.h @@ -0,0 +1,827 @@ +/* + * STM32 - OTG_HS_DEVICE (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_DEVICE_H_ +#define STM32_OTG_HS_DEVICE_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_DEVICE DEVICE_PATH_STM32 "OTG_HS_DEVICE" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_DEVICE TYPE_STM32_PREFIX "otg_hs_device" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_DEVICE_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_DEVICEParentClass; +typedef PeripheralState STM32OTG_HS_DEVICEParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_DEVICEClass, (obj), TYPE_STM32_OTG_HS_DEVICE) +#define STM32_OTG_HS_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_DEVICEClass, (klass), TYPE_STM32_OTG_HS_DEVICE) + +typedef struct { + // private: + STM32OTG_HS_DEVICEParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_DEVICEClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_DEVICE_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_DEVICEState, (obj), TYPE_STM32_OTG_HS_DEVICE) + +typedef struct { + // private: + STM32OTG_HS_DEVICEParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_DEVICE (USB on the go high speed) registers. + struct { + Object *otg_hs_dcfg; // 0x0 (OTG_HS device configuration register) + Object *otg_hs_dctl; // 0x4 (OTG_HS device control register) + Object *otg_hs_dsts; // 0x8 (OTG_HS device status register) + Object *otg_hs_diepmsk; // 0x10 (OTG_HS device IN endpoint common interrupt mask register) + Object *otg_hs_doepmsk; // 0x14 (OTG_HS device OUT endpoint common interrupt mask register) + Object *otg_hs_daint; // 0x18 (OTG_HS device all endpoints interrupt register) + Object *otg_hs_daintmsk; // 0x1C (OTG_HS all endpoints interrupt mask register) + Object *otg_hs_dvbusdis; // 0x28 (OTG_HS device VBUS discharge time register) + Object *otg_hs_dvbuspulse; // 0x2C (OTG_HS device VBUS pulsing time register) + Object *otg_hs_dthrctl; // 0x30 (OTG_HS Device threshold control register) + Object *otg_hs_diepempmsk; // 0x34 (OTG_HS device IN endpoint FIFO empty interrupt mask register) + Object *otg_hs_deachint; // 0x38 (OTG_HS device each endpoint interrupt register) + Object *otg_hs_deachintmsk; // 0x3C (OTG_HS device each endpoint interrupt register mask) + Object *otg_hs_diepeachmsk1; // 0x40 (OTG_HS device each in endpoint-1 interrupt register) + Object *otg_hs_doepeachmsk1; // 0x80 (OTG_HS device each OUT endpoint-1 interrupt register) + Object *otg_hs_diepctl0; // 0x100 (OTG device endpoint-0 control register) + Object *otg_hs_diepctl1; // 0x120 (OTG device endpoint-1 control register) + Object *otg_hs_diepctl2; // 0x140 (OTG device endpoint-2 control register) + Object *otg_hs_diepctl3; // 0x160 (OTG device endpoint-3 control register) + Object *otg_hs_diepctl4; // 0x180 (OTG device endpoint-4 control register) + Object *otg_hs_diepctl5; // 0x1A0 (OTG device endpoint-5 control register) + Object *otg_hs_diepctl6; // 0x1C0 (OTG device endpoint-6 control register) + Object *otg_hs_diepctl7; // 0x1E0 (OTG device endpoint-7 control register) + Object *otg_hs_diepint0; // 0x108 (OTG device endpoint-0 interrupt register) + Object *otg_hs_diepint1; // 0x128 (OTG device endpoint-1 interrupt register) + Object *otg_hs_diepint2; // 0x148 (OTG device endpoint-2 interrupt register) + Object *otg_hs_diepint3; // 0x168 (OTG device endpoint-3 interrupt register) + Object *otg_hs_diepint4; // 0x188 (OTG device endpoint-4 interrupt register) + Object *otg_hs_diepint5; // 0x1A8 (OTG device endpoint-5 interrupt register) + Object *otg_hs_diepint6; // 0x1C8 (OTG device endpoint-6 interrupt register) + Object *otg_hs_diepint7; // 0x1E8 (OTG device endpoint-7 interrupt register) + Object *otg_hs_dieptsiz0; // 0x110 (OTG_HS device IN endpoint 0 transfer size register) + Object *otg_hs_diepdma1; // 0x114 (OTG_HS device endpoint-1 DMA address register) + Object *otg_hs_diepdma2; // 0x134 (OTG_HS device endpoint-2 DMA address register) + Object *otg_hs_diepdma3; // 0x154 (OTG_HS device endpoint-3 DMA address register) + Object *otg_hs_diepdma4; // 0x174 (OTG_HS device endpoint-4 DMA address register) + Object *otg_hs_diepdma5; // 0x194 (OTG_HS device endpoint-5 DMA address register) + Object *otg_hs_dtxfsts0; // 0x118 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts1; // 0x138 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts2; // 0x158 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts3; // 0x178 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts4; // 0x198 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dtxfsts5; // 0x1B8 (OTG_HS device IN endpoint transmit FIFO status register) + Object *otg_hs_dieptsiz1; // 0x130 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz2; // 0x150 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz3; // 0x170 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz4; // 0x190 (OTG_HS device endpoint transfer size register) + Object *otg_hs_dieptsiz5; // 0x1B0 (OTG_HS device endpoint transfer size register) + Object *otg_hs_doepctl0; // 0x300 (OTG_HS device control OUT endpoint 0 control register) + Object *otg_hs_doepctl1; // 0x320 (OTG device endpoint-1 control register) + Object *otg_hs_doepctl2; // 0x340 (OTG device endpoint-2 control register) + Object *otg_hs_doepctl3; // 0x360 (OTG device endpoint-3 control register) + Object *otg_hs_doepint0; // 0x308 (OTG_HS device endpoint-0 interrupt register) + Object *otg_hs_doepint1; // 0x328 (OTG_HS device endpoint-1 interrupt register) + Object *otg_hs_doepint2; // 0x348 (OTG_HS device endpoint-2 interrupt register) + Object *otg_hs_doepint3; // 0x368 (OTG_HS device endpoint-3 interrupt register) + Object *otg_hs_doepint4; // 0x388 (OTG_HS device endpoint-4 interrupt register) + Object *otg_hs_doepint5; // 0x3A8 (OTG_HS device endpoint-5 interrupt register) + Object *otg_hs_doepint6; // 0x3C8 (OTG_HS device endpoint-6 interrupt register) + Object *otg_hs_doepint7; // 0x3E8 (OTG_HS device endpoint-7 interrupt register) + Object *otg_hs_doeptsiz0; // 0x310 (OTG_HS device endpoint-1 transfer size register) + Object *otg_hs_doeptsiz1; // 0x330 (OTG_HS device endpoint-2 transfer size register) + Object *otg_hs_doeptsiz2; // 0x350 (OTG_HS device endpoint-3 transfer size register) + Object *otg_hs_doeptsiz3; // 0x370 (OTG_HS device endpoint-4 transfer size register) + Object *otg_hs_doeptsiz4; // 0x390 (OTG_HS device endpoint-5 transfer size register) + } reg; + + struct { + + // OTG_HS_DCFG (OTG_HS device configuration register) bitfields. + struct { + Object *dspd; // [0:1] Device speed + Object *nzlsohsk; // [2:2] Nonzero-length status OUT handshake + Object *dad; // [4:10] Device address + Object *pfivl; // [11:12] Periodic (micro)frame interval + Object *perschivl; // [24:25] Periodic scheduling interval + } otg_hs_dcfg; + + // OTG_HS_DCTL (OTG_HS device control register) bitfields. + struct { + Object *rwusig; // [0:0] Remote wakeup signaling + Object *sdis; // [1:1] Soft disconnect + Object *ginsts; // [2:2] Global IN NAK status + Object *gonsts; // [3:3] Global OUT NAK status + Object *tctl; // [4:6] Test control + Object *sginak; // [7:7] Set global IN NAK + Object *cginak; // [8:8] Clear global IN NAK + Object *sgonak; // [9:9] Set global OUT NAK + Object *cgonak; // [10:10] Clear global OUT NAK + Object *poprgdne; // [11:11] Power-on programming done + } otg_hs_dctl; + + // OTG_HS_DSTS (OTG_HS device status register) bitfields. + struct { + Object *suspsts; // [0:0] Suspend status + Object *enumspd; // [1:2] Enumerated speed + Object *eerr; // [3:3] Erratic error + Object *fnsof; // [8:21] Frame number of the received SOF + } otg_hs_dsts; + + // OTG_HS_DIEPMSK (OTG_HS device IN endpoint common interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (nonisochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + Object *txfurm; // [8:8] FIFO underrun mask + Object *bim; // [9:9] BNA interrupt mask + } otg_hs_diepmsk; + + // OTG_HS_DOEPMSK (OTG_HS device OUT endpoint common interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *stupm; // [3:3] SETUP phase done mask + Object *otepdm; // [4:4] OUT token received when endpoint disabled mask + Object *b2bstup; // [6:6] Back-to-back SETUP packets received mask + Object *opem; // [8:8] OUT packet error mask + Object *boim; // [9:9] BNA interrupt mask + } otg_hs_doepmsk; + + // OTG_HS_DAINT (OTG_HS device all endpoints interrupt register) bitfields. + struct { + Object *iepint; // [0:15] IN endpoint interrupt bits + Object *oepint; // [16:31] OUT endpoint interrupt bits + } otg_hs_daint; + + // OTG_HS_DAINTMSK (OTG_HS all endpoints interrupt mask register) bitfields. + struct { + Object *iepm; // [0:15] IN EP interrupt mask bits + Object *oepm; // [16:31] OUT EP interrupt mask bits + } otg_hs_daintmsk; + + // OTG_HS_DVBUSDIS (OTG_HS device VBUS discharge time register) bitfields. + struct { + Object *vbusdt; // [0:15] Device VBUS discharge time + } otg_hs_dvbusdis; + + // OTG_HS_DVBUSPULSE (OTG_HS device VBUS pulsing time register) bitfields. + struct { + Object *dvbusp; // [0:11] Device VBUS pulsing time + } otg_hs_dvbuspulse; + + // OTG_HS_DTHRCTL (OTG_HS Device threshold control register) bitfields. + struct { + Object *nonisothren; // [0:0] Nonisochronous IN endpoints threshold enable + Object *isothren; // [1:1] ISO IN endpoint threshold enable + Object *txthrlen; // [2:10] Transmit threshold length + Object *rxthren; // [16:16] Receive threshold enable + Object *rxthrlen; // [17:25] Receive threshold length + Object *arpen; // [27:27] Arbiter parking enable + } otg_hs_dthrctl; + + // OTG_HS_DIEPEMPMSK (OTG_HS device IN endpoint FIFO empty interrupt mask register) bitfields. + struct { + Object *ineptxfem; // [0:15] IN EP Tx FIFO empty interrupt mask bits + } otg_hs_diepempmsk; + + // OTG_HS_DEACHINT (OTG_HS device each endpoint interrupt register) bitfields. + struct { + Object *iep1int; // [1:1] IN endpoint 1interrupt bit + Object *oep1int; // [17:17] OUT endpoint 1 interrupt bit + } otg_hs_deachint; + + // OTG_HS_DEACHINTMSK (OTG_HS device each endpoint interrupt register mask) bitfields. + struct { + Object *iep1intm; // [1:1] IN Endpoint 1 interrupt mask bit + Object *oep1intm; // [17:17] OUT Endpoint 1 interrupt mask bit + } otg_hs_deachintmsk; + + // OTG_HS_DIEPEACHMSK1 (OTG_HS device each in endpoint-1 interrupt register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask (nonisochronous endpoints) + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + Object *txfurm; // [8:8] FIFO underrun mask + Object *bim; // [9:9] BNA interrupt mask + Object *nakm; // [13:13] NAK interrupt mask + } otg_hs_diepeachmsk1; + + // OTG_HS_DOEPEACHMSK1 (OTG_HS device each OUT endpoint-1 interrupt register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed interrupt mask + Object *epdm; // [1:1] Endpoint disabled interrupt mask + Object *tom; // [3:3] Timeout condition mask + Object *ittxfemsk; // [4:4] IN token received when TxFIFO empty mask + Object *inepnmm; // [5:5] IN token received with EP mismatch mask + Object *inepnem; // [6:6] IN endpoint NAK effective mask + Object *txfurm; // [8:8] OUT packet error mask + Object *bim; // [9:9] BNA interrupt mask + Object *berrm; // [12:12] Bubble error interrupt mask + Object *nakm; // [13:13] NAK interrupt mask + Object *nyetm; // [14:14] NYET interrupt mask + } otg_hs_doepeachmsk1; + + // OTG_HS_DIEPCTL0 (OTG device endpoint-0 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl0; + + // OTG_HS_DIEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl1; + + // OTG_HS_DIEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl2; + + // OTG_HS_DIEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl3; + + // OTG_HS_DIEPCTL4 (OTG device endpoint-4 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl4; + + // OTG_HS_DIEPCTL5 (OTG device endpoint-5 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl5; + + // OTG_HS_DIEPCTL6 (OTG device endpoint-6 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl6; + + // OTG_HS_DIEPCTL7 (OTG device endpoint-7 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even/odd frame + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *stall; // [21:21] STALL handshake + Object *txfnum; // [22:25] TxFIFO number + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_diepctl7; + + // OTG_HS_DIEPINT0 (OTG device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint0; + + // OTG_HS_DIEPINT1 (OTG device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint1; + + // OTG_HS_DIEPINT2 (OTG device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint2; + + // OTG_HS_DIEPINT3 (OTG device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint3; + + // OTG_HS_DIEPINT4 (OTG device endpoint-4 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint4; + + // OTG_HS_DIEPINT5 (OTG device endpoint-5 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint5; + + // OTG_HS_DIEPINT6 (OTG device endpoint-6 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint6; + + // OTG_HS_DIEPINT7 (OTG device endpoint-7 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *toc; // [3:3] Timeout condition + Object *ittxfe; // [4:4] IN token received when TxFIFO is empty + Object *inepne; // [6:6] IN endpoint NAK effective + Object *txfe; // [7:7] Transmit FIFO empty + Object *txfifoudrn; // [8:8] Transmit Fifo Underrun + Object *bna; // [9:9] Buffer not available interrupt + Object *pktdrpsts; // [11:11] Packet dropped status + Object *berr; // [12:12] Babble error interrupt + Object *nak; // [13:13] NAK interrupt + } otg_hs_diepint7; + + // OTG_HS_DIEPTSIZ0 (OTG_HS device IN endpoint 0 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:20] Packet count + } otg_hs_dieptsiz0; + + // OTG_HS_DIEPDMA1 (OTG_HS device endpoint-1 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma1; + + // OTG_HS_DIEPDMA2 (OTG_HS device endpoint-2 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma2; + + // OTG_HS_DIEPDMA3 (OTG_HS device endpoint-3 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma3; + + // OTG_HS_DIEPDMA4 (OTG_HS device endpoint-4 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma4; + + // OTG_HS_DIEPDMA5 (OTG_HS device endpoint-5 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_diepdma5; + + // OTG_HS_DTXFSTS0 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts0; + + // OTG_HS_DTXFSTS1 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts1; + + // OTG_HS_DTXFSTS2 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts2; + + // OTG_HS_DTXFSTS3 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts3; + + // OTG_HS_DTXFSTS4 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts4; + + // OTG_HS_DTXFSTS5 (OTG_HS device IN endpoint transmit FIFO status register) bitfields. + struct { + Object *ineptfsav; // [0:15] IN endpoint TxFIFO space avail + } otg_hs_dtxfsts5; + + // OTG_HS_DIEPTSIZ1 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz1; + + // OTG_HS_DIEPTSIZ2 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz2; + + // OTG_HS_DIEPTSIZ3 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz3; + + // OTG_HS_DIEPTSIZ4 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz4; + + // OTG_HS_DIEPTSIZ5 (OTG_HS device endpoint transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *mcnt; // [29:30] Multi count + } otg_hs_dieptsiz5; + + // OTG_HS_DOEPCTL0 (OTG_HS device control OUT endpoint 0 control register) bitfields. + struct { + Object *mpsiz; // [0:1] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl0; + + // OTG_HS_DOEPCTL1 (OTG device endpoint-1 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even odd frame/Endpoint data PID + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID/Set even frame + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl1; + + // OTG_HS_DOEPCTL2 (OTG device endpoint-2 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even odd frame/Endpoint data PID + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID/Set even frame + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl2; + + // OTG_HS_DOEPCTL3 (OTG device endpoint-3 control register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *usbaep; // [15:15] USB active endpoint + Object *eonum_dpid; // [16:16] Even odd frame/Endpoint data PID + Object *naksts; // [17:17] NAK status + Object *eptyp; // [18:19] Endpoint type + Object *snpm; // [20:20] Snoop mode + Object *stall; // [21:21] STALL handshake + Object *cnak; // [26:26] Clear NAK + Object *snak; // [27:27] Set NAK + Object *sd0pid_sevnfrm; // [28:28] Set DATA0 PID/Set even frame + Object *soddfrm; // [29:29] Set odd frame + Object *epdis; // [30:30] Endpoint disable + Object *epena; // [31:31] Endpoint enable + } otg_hs_doepctl3; + + // OTG_HS_DOEPINT0 (OTG_HS device endpoint-0 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint0; + + // OTG_HS_DOEPINT1 (OTG_HS device endpoint-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint1; + + // OTG_HS_DOEPINT2 (OTG_HS device endpoint-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint2; + + // OTG_HS_DOEPINT3 (OTG_HS device endpoint-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint3; + + // OTG_HS_DOEPINT4 (OTG_HS device endpoint-4 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint4; + + // OTG_HS_DOEPINT5 (OTG_HS device endpoint-5 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint5; + + // OTG_HS_DOEPINT6 (OTG_HS device endpoint-6 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint6; + + // OTG_HS_DOEPINT7 (OTG_HS device endpoint-7 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed interrupt + Object *epdisd; // [1:1] Endpoint disabled interrupt + Object *stup; // [3:3] SETUP phase done + Object *otepdis; // [4:4] OUT token received when endpoint disabled + Object *b2bstup; // [6:6] Back-to-back SETUP packets received + Object *nyet; // [14:14] NYET interrupt + } otg_hs_doepint7; + + // OTG_HS_DOEPTSIZ0 (OTG_HS device endpoint-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:6] Transfer size + Object *pktcnt; // [19:19] Packet count + Object *stupcnt; // [29:30] SETUP packet count + } otg_hs_doeptsiz0; + + // OTG_HS_DOEPTSIZ1 (OTG_HS device endpoint-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz1; + + // OTG_HS_DOEPTSIZ2 (OTG_HS device endpoint-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz2; + + // OTG_HS_DOEPTSIZ3 (OTG_HS device endpoint-4 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz3; + + // OTG_HS_DOEPTSIZ4 (OTG_HS device endpoint-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *rxdpid_stupcnt; // [29:30] Received data PID/SETUP packet count + } otg_hs_doeptsiz4; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_DEVICEState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_DEVICE_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_global.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_global.c new file mode 100644 index 0000000000..3adf8ae22e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_global.c @@ -0,0 +1,457 @@ +/* + * STM32 - OTG_HS_GLOBAL (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_hs_global_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_gotgctl = cm_object_get_child_by_name(obj, "OTG_HS_GOTGCTL"); + state->u.f4.reg.otg_hs_gotgint = cm_object_get_child_by_name(obj, "OTG_HS_GOTGINT"); + state->u.f4.reg.otg_hs_gahbcfg = cm_object_get_child_by_name(obj, "OTG_HS_GAHBCFG"); + state->u.f4.reg.otg_hs_gusbcfg = cm_object_get_child_by_name(obj, "OTG_HS_GUSBCFG"); + state->u.f4.reg.otg_hs_grstctl = cm_object_get_child_by_name(obj, "OTG_HS_GRSTCTL"); + state->u.f4.reg.otg_hs_gintsts = cm_object_get_child_by_name(obj, "OTG_HS_GINTSTS"); + state->u.f4.reg.otg_hs_gintmsk = cm_object_get_child_by_name(obj, "OTG_HS_GINTMSK"); + state->u.f4.reg.otg_hs_grxstsr_host = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSR_Host"); + state->u.f4.reg.otg_hs_grxstsp_host = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSP_Host"); + state->u.f4.reg.otg_hs_grxfsiz = cm_object_get_child_by_name(obj, "OTG_HS_GRXFSIZ"); + state->u.f4.reg.otg_hs_gnptxfsiz_host = cm_object_get_child_by_name(obj, "OTG_HS_GNPTXFSIZ_Host"); + state->u.f4.reg.otg_hs_tx0fsiz_peripheral = cm_object_get_child_by_name(obj, "OTG_HS_TX0FSIZ_Peripheral"); + state->u.f4.reg.otg_hs_gnptxsts = cm_object_get_child_by_name(obj, "OTG_HS_GNPTXSTS"); + state->u.f4.reg.otg_hs_gccfg = cm_object_get_child_by_name(obj, "OTG_HS_GCCFG"); + state->u.f4.reg.otg_hs_cid = cm_object_get_child_by_name(obj, "OTG_HS_CID"); + state->u.f4.reg.otg_hs_hptxfsiz = cm_object_get_child_by_name(obj, "OTG_HS_HPTXFSIZ"); + state->u.f4.reg.otg_hs_dieptxf1 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF1"); + state->u.f4.reg.otg_hs_dieptxf2 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF2"); + state->u.f4.reg.otg_hs_dieptxf3 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF3"); + state->u.f4.reg.otg_hs_dieptxf4 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF4"); + state->u.f4.reg.otg_hs_dieptxf5 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF5"); + state->u.f4.reg.otg_hs_dieptxf6 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF6"); + state->u.f4.reg.otg_hs_dieptxf7 = cm_object_get_child_by_name(obj, "OTG_HS_DIEPTXF7"); + state->u.f4.reg.otg_hs_grxstsr_peripheral = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSR_Peripheral"); + state->u.f4.reg.otg_hs_grxstsp_peripheral = cm_object_get_child_by_name(obj, "OTG_HS_GRXSTSP_Peripheral"); + + + // OTG_HS_GOTGCTL bitfields. + state->u.f4.fld.otg_hs_gotgctl.srqscs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "SRQSCS"); + state->u.f4.fld.otg_hs_gotgctl.srq = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "SRQ"); + state->u.f4.fld.otg_hs_gotgctl.hngscs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "HNGSCS"); + state->u.f4.fld.otg_hs_gotgctl.hnprq = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "HNPRQ"); + state->u.f4.fld.otg_hs_gotgctl.hshnpen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "HSHNPEN"); + state->u.f4.fld.otg_hs_gotgctl.dhnpen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "DHNPEN"); + state->u.f4.fld.otg_hs_gotgctl.cidsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "CIDSTS"); + state->u.f4.fld.otg_hs_gotgctl.dbct = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "DBCT"); + state->u.f4.fld.otg_hs_gotgctl.asvld = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "ASVLD"); + state->u.f4.fld.otg_hs_gotgctl.bsvld = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgctl, "BSVLD"); + + // OTG_HS_GOTGINT bitfields. + state->u.f4.fld.otg_hs_gotgint.sedet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "SEDET"); + state->u.f4.fld.otg_hs_gotgint.srsschg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "SRSSCHG"); + state->u.f4.fld.otg_hs_gotgint.hnsschg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "HNSSCHG"); + state->u.f4.fld.otg_hs_gotgint.hngdet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "HNGDET"); + state->u.f4.fld.otg_hs_gotgint.adtochg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "ADTOCHG"); + state->u.f4.fld.otg_hs_gotgint.dbcdne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gotgint, "DBCDNE"); + + // OTG_HS_GAHBCFG bitfields. + state->u.f4.fld.otg_hs_gahbcfg.gint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "GINT"); + state->u.f4.fld.otg_hs_gahbcfg.hbstlen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "HBSTLEN"); + state->u.f4.fld.otg_hs_gahbcfg.dmaen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "DMAEN"); + state->u.f4.fld.otg_hs_gahbcfg.txfelvl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "TXFELVL"); + state->u.f4.fld.otg_hs_gahbcfg.ptxfelvl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gahbcfg, "PTXFELVL"); + + // OTG_HS_GUSBCFG bitfields. + state->u.f4.fld.otg_hs_gusbcfg.tocal = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "TOCAL"); + state->u.f4.fld.otg_hs_gusbcfg.physel = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PHYSEL"); + state->u.f4.fld.otg_hs_gusbcfg.srpcap = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "SRPCAP"); + state->u.f4.fld.otg_hs_gusbcfg.hnpcap = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "HNPCAP"); + state->u.f4.fld.otg_hs_gusbcfg.trdt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "TRDT"); + state->u.f4.fld.otg_hs_gusbcfg.phylpcs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PHYLPCS"); + state->u.f4.fld.otg_hs_gusbcfg.ulpifsls = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIFSLS"); + state->u.f4.fld.otg_hs_gusbcfg.ulpiar = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIAR"); + state->u.f4.fld.otg_hs_gusbcfg.ulpicsm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPICSM"); + state->u.f4.fld.otg_hs_gusbcfg.ulpievbusd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIEVBUSD"); + state->u.f4.fld.otg_hs_gusbcfg.ulpievbusi = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIEVBUSI"); + state->u.f4.fld.otg_hs_gusbcfg.tsdps = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "TSDPS"); + state->u.f4.fld.otg_hs_gusbcfg.pcci = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PCCI"); + state->u.f4.fld.otg_hs_gusbcfg.ptci = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "PTCI"); + state->u.f4.fld.otg_hs_gusbcfg.ulpiipd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "ULPIIPD"); + state->u.f4.fld.otg_hs_gusbcfg.fhmod = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "FHMOD"); + state->u.f4.fld.otg_hs_gusbcfg.fdmod = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "FDMOD"); + state->u.f4.fld.otg_hs_gusbcfg.ctxpkt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gusbcfg, "CTXPKT"); + + // OTG_HS_GRSTCTL bitfields. + state->u.f4.fld.otg_hs_grstctl.csrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "CSRST"); + state->u.f4.fld.otg_hs_grstctl.hsrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "HSRST"); + state->u.f4.fld.otg_hs_grstctl.fcrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "FCRST"); + state->u.f4.fld.otg_hs_grstctl.rxfflsh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "RXFFLSH"); + state->u.f4.fld.otg_hs_grstctl.txfflsh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "TXFFLSH"); + state->u.f4.fld.otg_hs_grstctl.txfnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "TXFNUM"); + state->u.f4.fld.otg_hs_grstctl.dmareq = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "DMAREQ"); + state->u.f4.fld.otg_hs_grstctl.ahbidl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grstctl, "AHBIDL"); + + // OTG_HS_GINTSTS bitfields. + state->u.f4.fld.otg_hs_gintsts.cmod = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "CMOD"); + state->u.f4.fld.otg_hs_gintsts.mmis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "MMIS"); + state->u.f4.fld.otg_hs_gintsts.otgint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "OTGINT"); + state->u.f4.fld.otg_hs_gintsts.sof = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "SOF"); + state->u.f4.fld.otg_hs_gintsts.rxflvl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "RXFLVL"); + state->u.f4.fld.otg_hs_gintsts.nptxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "NPTXFE"); + state->u.f4.fld.otg_hs_gintsts.ginakeff = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "GINAKEFF"); + state->u.f4.fld.otg_hs_gintsts.boutnakeff = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "BOUTNAKEFF"); + state->u.f4.fld.otg_hs_gintsts.esusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "ESUSP"); + state->u.f4.fld.otg_hs_gintsts.usbsusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "USBSUSP"); + state->u.f4.fld.otg_hs_gintsts.usbrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "USBRST"); + state->u.f4.fld.otg_hs_gintsts.enumdne = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "ENUMDNE"); + state->u.f4.fld.otg_hs_gintsts.isoodrp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "ISOODRP"); + state->u.f4.fld.otg_hs_gintsts.eopf = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "EOPF"); + state->u.f4.fld.otg_hs_gintsts.iepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "IEPINT"); + state->u.f4.fld.otg_hs_gintsts.oepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "OEPINT"); + state->u.f4.fld.otg_hs_gintsts.iisoixfr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "IISOIXFR"); + state->u.f4.fld.otg_hs_gintsts.pxfr_incompisoout = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "PXFR_INCOMPISOOUT"); + state->u.f4.fld.otg_hs_gintsts.datafsusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "DATAFSUSP"); + state->u.f4.fld.otg_hs_gintsts.hprtint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "HPRTINT"); + state->u.f4.fld.otg_hs_gintsts.hcint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "HCINT"); + state->u.f4.fld.otg_hs_gintsts.ptxfe = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "PTXFE"); + state->u.f4.fld.otg_hs_gintsts.cidschg = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "CIDSCHG"); + state->u.f4.fld.otg_hs_gintsts.discint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "DISCINT"); + state->u.f4.fld.otg_hs_gintsts.srqint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "SRQINT"); + state->u.f4.fld.otg_hs_gintsts.wkuint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintsts, "WKUINT"); + + // OTG_HS_GINTMSK bitfields. + state->u.f4.fld.otg_hs_gintmsk.mmism = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "MMISM"); + state->u.f4.fld.otg_hs_gintmsk.otgint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "OTGINT"); + state->u.f4.fld.otg_hs_gintmsk.sofm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "SOFM"); + state->u.f4.fld.otg_hs_gintmsk.rxflvlm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "RXFLVLM"); + state->u.f4.fld.otg_hs_gintmsk.nptxfem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "NPTXFEM"); + state->u.f4.fld.otg_hs_gintmsk.ginakeffm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "GINAKEFFM"); + state->u.f4.fld.otg_hs_gintmsk.gonakeffm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "GONAKEFFM"); + state->u.f4.fld.otg_hs_gintmsk.esuspm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "ESUSPM"); + state->u.f4.fld.otg_hs_gintmsk.usbsuspm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "USBSUSPM"); + state->u.f4.fld.otg_hs_gintmsk.usbrst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "USBRST"); + state->u.f4.fld.otg_hs_gintmsk.enumdnem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "ENUMDNEM"); + state->u.f4.fld.otg_hs_gintmsk.isoodrpm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "ISOODRPM"); + state->u.f4.fld.otg_hs_gintmsk.eopfm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "EOPFM"); + state->u.f4.fld.otg_hs_gintmsk.epmism = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "EPMISM"); + state->u.f4.fld.otg_hs_gintmsk.iepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "IEPINT"); + state->u.f4.fld.otg_hs_gintmsk.oepint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "OEPINT"); + state->u.f4.fld.otg_hs_gintmsk.iisoixfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "IISOIXFRM"); + state->u.f4.fld.otg_hs_gintmsk.pxfrm_iisooxfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "PXFRM_IISOOXFRM"); + state->u.f4.fld.otg_hs_gintmsk.fsuspm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "FSUSPM"); + state->u.f4.fld.otg_hs_gintmsk.prtim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "PRTIM"); + state->u.f4.fld.otg_hs_gintmsk.hcim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "HCIM"); + state->u.f4.fld.otg_hs_gintmsk.ptxfem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "PTXFEM"); + state->u.f4.fld.otg_hs_gintmsk.cidschgm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "CIDSCHGM"); + state->u.f4.fld.otg_hs_gintmsk.discint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "DISCINT"); + state->u.f4.fld.otg_hs_gintmsk.srqim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "SRQIM"); + state->u.f4.fld.otg_hs_gintmsk.wuim = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gintmsk, "WUIM"); + + // OTG_HS_GRXSTSR_Host bitfields. + state->u.f4.fld.otg_hs_grxstsr_host.chnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "CHNUM"); + state->u.f4.fld.otg_hs_grxstsr_host.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "BCNT"); + state->u.f4.fld.otg_hs_grxstsr_host.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "DPID"); + state->u.f4.fld.otg_hs_grxstsr_host.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_host, "PKTSTS"); + + // OTG_HS_GRXSTSP_Host bitfields. + state->u.f4.fld.otg_hs_grxstsp_host.chnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "CHNUM"); + state->u.f4.fld.otg_hs_grxstsp_host.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "BCNT"); + state->u.f4.fld.otg_hs_grxstsp_host.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "DPID"); + state->u.f4.fld.otg_hs_grxstsp_host.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_host, "PKTSTS"); + + // OTG_HS_GRXFSIZ bitfields. + state->u.f4.fld.otg_hs_grxfsiz.rxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxfsiz, "RXFD"); + + // OTG_HS_GNPTXFSIZ_Host bitfields. + state->u.f4.fld.otg_hs_gnptxfsiz_host.nptxfsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxfsiz_host, "NPTXFSA"); + state->u.f4.fld.otg_hs_gnptxfsiz_host.nptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxfsiz_host, "NPTXFD"); + + // OTG_HS_TX0FSIZ_Peripheral bitfields. + state->u.f4.fld.otg_hs_tx0fsiz_peripheral.tx0fsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_tx0fsiz_peripheral, "TX0FSA"); + state->u.f4.fld.otg_hs_tx0fsiz_peripheral.tx0fd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_tx0fsiz_peripheral, "TX0FD"); + + // OTG_HS_GNPTXSTS bitfields. + state->u.f4.fld.otg_hs_gnptxsts.nptxfsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxsts, "NPTXFSAV"); + state->u.f4.fld.otg_hs_gnptxsts.nptqxsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxsts, "NPTQXSAV"); + state->u.f4.fld.otg_hs_gnptxsts.nptxqtop = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gnptxsts, "NPTXQTOP"); + + // OTG_HS_GCCFG bitfields. + state->u.f4.fld.otg_hs_gccfg.pwrdwn = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "PWRDWN"); + state->u.f4.fld.otg_hs_gccfg.i2cpaden = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "I2CPADEN"); + state->u.f4.fld.otg_hs_gccfg.vbusasen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "VBUSASEN"); + state->u.f4.fld.otg_hs_gccfg.vbusbsen = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "VBUSBSEN"); + state->u.f4.fld.otg_hs_gccfg.sofouten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "SOFOUTEN"); + state->u.f4.fld.otg_hs_gccfg.novbussens = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_gccfg, "NOVBUSSENS"); + + // OTG_HS_CID bitfields. + state->u.f4.fld.otg_hs_cid.product_id = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_cid, "PRODUCT_ID"); + + // OTG_HS_HPTXFSIZ bitfields. + state->u.f4.fld.otg_hs_hptxfsiz.ptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxfsiz, "PTXSA"); + state->u.f4.fld.otg_hs_hptxfsiz.ptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxfsiz, "PTXFD"); + + // OTG_HS_DIEPTXF1 bitfields. + state->u.f4.fld.otg_hs_dieptxf1.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf1, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf1.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf1, "INEPTXFD"); + + // OTG_HS_DIEPTXF2 bitfields. + state->u.f4.fld.otg_hs_dieptxf2.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf2, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf2.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf2, "INEPTXFD"); + + // OTG_HS_DIEPTXF3 bitfields. + state->u.f4.fld.otg_hs_dieptxf3.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf3, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf3.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf3, "INEPTXFD"); + + // OTG_HS_DIEPTXF4 bitfields. + state->u.f4.fld.otg_hs_dieptxf4.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf4, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf4.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf4, "INEPTXFD"); + + // OTG_HS_DIEPTXF5 bitfields. + state->u.f4.fld.otg_hs_dieptxf5.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf5, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf5.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf5, "INEPTXFD"); + + // OTG_HS_DIEPTXF6 bitfields. + state->u.f4.fld.otg_hs_dieptxf6.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf6, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf6.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf6, "INEPTXFD"); + + // OTG_HS_DIEPTXF7 bitfields. + state->u.f4.fld.otg_hs_dieptxf7.ineptxsa = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf7, "INEPTXSA"); + state->u.f4.fld.otg_hs_dieptxf7.ineptxfd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_dieptxf7, "INEPTXFD"); + + // OTG_HS_GRXSTSR_Peripheral bitfields. + state->u.f4.fld.otg_hs_grxstsr_peripheral.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "EPNUM"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "BCNT"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "DPID"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "PKTSTS"); + state->u.f4.fld.otg_hs_grxstsr_peripheral.frmnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsr_peripheral, "FRMNUM"); + + // OTG_HS_GRXSTSP_Peripheral bitfields. + state->u.f4.fld.otg_hs_grxstsp_peripheral.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "EPNUM"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.bcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "BCNT"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "DPID"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.pktsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "PKTSTS"); + state->u.f4.fld.otg_hs_grxstsp_peripheral.frmnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_grxstsp_peripheral, "FRMNUM"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_global_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_global_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_global_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_global_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_global_is_enabled(Object *obj) +{ + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_global_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_global_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_GLOBAL)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_GLOBALState *state = STM32_OTG_HS_GLOBAL_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_GLOBAL"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_hs_global_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_global_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_GLOBALEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_global_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_GLOBAL); +} + +static void stm32_otg_hs_global_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_global_reset_callback; + dc->realize = stm32_otg_hs_global_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_global_is_enabled; +} + +static const TypeInfo stm32_otg_hs_global_type_info = { + .name = TYPE_STM32_OTG_HS_GLOBAL, + .parent = TYPE_STM32_OTG_HS_GLOBAL_PARENT, + .instance_init = stm32_otg_hs_global_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_GLOBALState), + .class_init = stm32_otg_hs_global_class_init_callback, + .class_size = sizeof(STM32OTG_HS_GLOBALClass) }; + +static void stm32_otg_hs_global_register_types(void) +{ + type_register_static(&stm32_otg_hs_global_type_info); +} + +type_init(stm32_otg_hs_global_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_global.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_global.h new file mode 100644 index 0000000000..0af67faafd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_global.h @@ -0,0 +1,372 @@ +/* + * STM32 - OTG_HS_GLOBAL (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_GLOBAL_H_ +#define STM32_OTG_HS_GLOBAL_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_GLOBAL DEVICE_PATH_STM32 "OTG_HS_GLOBAL" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_GLOBAL TYPE_STM32_PREFIX "otg_hs_global" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_GLOBAL_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_GLOBALParentClass; +typedef PeripheralState STM32OTG_HS_GLOBALParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_GLOBAL_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_GLOBALClass, (obj), TYPE_STM32_OTG_HS_GLOBAL) +#define STM32_OTG_HS_GLOBAL_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_GLOBALClass, (klass), TYPE_STM32_OTG_HS_GLOBAL) + +typedef struct { + // private: + STM32OTG_HS_GLOBALParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_GLOBALClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_GLOBAL_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_GLOBALState, (obj), TYPE_STM32_OTG_HS_GLOBAL) + +typedef struct { + // private: + STM32OTG_HS_GLOBALParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_GLOBAL (USB on the go high speed) registers. + struct { + Object *otg_hs_gotgctl; // 0x0 (OTG_HS control and status register) + Object *otg_hs_gotgint; // 0x4 (OTG_HS interrupt register) + Object *otg_hs_gahbcfg; // 0x8 (OTG_HS AHB configuration register) + Object *otg_hs_gusbcfg; // 0xC (OTG_HS USB configuration register) + Object *otg_hs_grstctl; // 0x10 (OTG_HS reset register) + Object *otg_hs_gintsts; // 0x14 (OTG_HS core interrupt register) + Object *otg_hs_gintmsk; // 0x18 (OTG_HS interrupt mask register) + Object *otg_hs_grxstsr_host; // 0x1C (OTG_HS Receive status debug read register (host mode)) + Object *otg_hs_grxstsp_host; // 0x20 (OTG_HS status read and pop register (host mode)) + Object *otg_hs_grxfsiz; // 0x24 (OTG_HS Receive FIFO size register) + Object *otg_hs_gnptxfsiz_host; // 0x28 (OTG_HS nonperiodic transmit FIFO size register (host mode)) + Object *otg_hs_tx0fsiz_peripheral; // 0x28 (Endpoint 0 transmit FIFO size (peripheral mode)) + Object *otg_hs_gnptxsts; // 0x2C (OTG_HS nonperiodic transmit FIFO/queue status register) + Object *otg_hs_gccfg; // 0x38 (OTG_HS general core configuration register) + Object *otg_hs_cid; // 0x3C (OTG_HS core ID register) + Object *otg_hs_hptxfsiz; // 0x100 (OTG_HS Host periodic transmit FIFO size register) + Object *otg_hs_dieptxf1; // 0x104 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf2; // 0x108 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf3; // 0x11C (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf4; // 0x120 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf5; // 0x124 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf6; // 0x128 (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_dieptxf7; // 0x12C (OTG_HS device IN endpoint transmit FIFO size register) + Object *otg_hs_grxstsr_peripheral; // 0x1C (OTG_HS Receive status debug read register (peripheral mode mode)) + Object *otg_hs_grxstsp_peripheral; // 0x20 (OTG_HS status read and pop register (peripheral mode)) + } reg; + + struct { + + // OTG_HS_GOTGCTL (OTG_HS control and status register) bitfields. + struct { + Object *srqscs; // [0:0] Session request success + Object *srq; // [1:1] Session request + Object *hngscs; // [8:8] Host negotiation success + Object *hnprq; // [9:9] HNP request + Object *hshnpen; // [10:10] Host set HNP enable + Object *dhnpen; // [11:11] Device HNP enabled + Object *cidsts; // [16:16] Connector ID status + Object *dbct; // [17:17] Long/short debounce time + Object *asvld; // [18:18] A-session valid + Object *bsvld; // [19:19] B-session valid + } otg_hs_gotgctl; + + // OTG_HS_GOTGINT (OTG_HS interrupt register) bitfields. + struct { + Object *sedet; // [2:2] Session end detected + Object *srsschg; // [8:8] Session request success status change + Object *hnsschg; // [9:9] Host negotiation success status change + Object *hngdet; // [17:17] Host negotiation detected + Object *adtochg; // [18:18] A-device timeout change + Object *dbcdne; // [19:19] Debounce done + } otg_hs_gotgint; + + // OTG_HS_GAHBCFG (OTG_HS AHB configuration register) bitfields. + struct { + Object *gint; // [0:0] Global interrupt mask + Object *hbstlen; // [1:4] Burst length/type + Object *dmaen; // [5:5] DMA enable + Object *txfelvl; // [7:7] TxFIFO empty level + Object *ptxfelvl; // [8:8] Periodic TxFIFO empty level + } otg_hs_gahbcfg; + + // OTG_HS_GUSBCFG (OTG_HS USB configuration register) bitfields. + struct { + Object *tocal; // [0:2] FS timeout calibration + Object *physel; // [6:6] USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select + Object *srpcap; // [8:8] SRP-capable + Object *hnpcap; // [9:9] HNP-capable + Object *trdt; // [10:13] USB turnaround time + Object *phylpcs; // [15:15] PHY Low-power clock select + Object *ulpifsls; // [17:17] ULPI FS/LS select + Object *ulpiar; // [18:18] ULPI Auto-resume + Object *ulpicsm; // [19:19] ULPI Clock SuspendM + Object *ulpievbusd; // [20:20] ULPI External VBUS Drive + Object *ulpievbusi; // [21:21] ULPI external VBUS indicator + Object *tsdps; // [22:22] TermSel DLine pulsing selection + Object *pcci; // [23:23] Indicator complement + Object *ptci; // [24:24] Indicator pass through + Object *ulpiipd; // [25:25] ULPI interface protect disable + Object *fhmod; // [29:29] Forced host mode + Object *fdmod; // [30:30] Forced peripheral mode + Object *ctxpkt; // [31:31] Corrupt Tx packet + } otg_hs_gusbcfg; + + // OTG_HS_GRSTCTL (OTG_HS reset register) bitfields. + struct { + Object *csrst; // [0:0] Core soft reset + Object *hsrst; // [1:1] HCLK soft reset + Object *fcrst; // [2:2] Host frame counter reset + Object *rxfflsh; // [4:4] RxFIFO flush + Object *txfflsh; // [5:5] TxFIFO flush + Object *txfnum; // [6:10] TxFIFO number + Object *dmareq; // [30:30] DMA request signal + Object *ahbidl; // [31:31] AHB master idle + } otg_hs_grstctl; + + // OTG_HS_GINTSTS (OTG_HS core interrupt register) bitfields. + struct { + Object *cmod; // [0:0] Current mode of operation + Object *mmis; // [1:1] Mode mismatch interrupt + Object *otgint; // [2:2] OTG interrupt + Object *sof; // [3:3] Start of frame + Object *rxflvl; // [4:4] RxFIFO nonempty + Object *nptxfe; // [5:5] Nonperiodic TxFIFO empty + Object *ginakeff; // [6:6] Global IN nonperiodic NAK effective + Object *boutnakeff; // [7:7] Global OUT NAK effective + Object *esusp; // [10:10] Early suspend + Object *usbsusp; // [11:11] USB suspend + Object *usbrst; // [12:12] USB reset + Object *enumdne; // [13:13] Enumeration done + Object *isoodrp; // [14:14] Isochronous OUT packet dropped interrupt + Object *eopf; // [15:15] End of periodic frame interrupt + Object *iepint; // [18:18] IN endpoint interrupt + Object *oepint; // [19:19] OUT endpoint interrupt + Object *iisoixfr; // [20:20] Incomplete isochronous IN transfer + Object *pxfr_incompisoout; // [21:21] Incomplete periodic transfer + Object *datafsusp; // [22:22] Data fetch suspended + Object *hprtint; // [24:24] Host port interrupt + Object *hcint; // [25:25] Host channels interrupt + Object *ptxfe; // [26:26] Periodic TxFIFO empty + Object *cidschg; // [28:28] Connector ID status change + Object *discint; // [29:29] Disconnect detected interrupt + Object *srqint; // [30:30] Session request/new session detected interrupt + Object *wkuint; // [31:31] Resume/remote wakeup detected interrupt + } otg_hs_gintsts; + + // OTG_HS_GINTMSK (OTG_HS interrupt mask register) bitfields. + struct { + Object *mmism; // [1:1] Mode mismatch interrupt mask + Object *otgint; // [2:2] OTG interrupt mask + Object *sofm; // [3:3] Start of frame mask + Object *rxflvlm; // [4:4] Receive FIFO nonempty mask + Object *nptxfem; // [5:5] Nonperiodic TxFIFO empty mask + Object *ginakeffm; // [6:6] Global nonperiodic IN NAK effective mask + Object *gonakeffm; // [7:7] Global OUT NAK effective mask + Object *esuspm; // [10:10] Early suspend mask + Object *usbsuspm; // [11:11] USB suspend mask + Object *usbrst; // [12:12] USB reset mask + Object *enumdnem; // [13:13] Enumeration done mask + Object *isoodrpm; // [14:14] Isochronous OUT packet dropped interrupt mask + Object *eopfm; // [15:15] End of periodic frame interrupt mask + Object *epmism; // [17:17] Endpoint mismatch interrupt mask + Object *iepint; // [18:18] IN endpoints interrupt mask + Object *oepint; // [19:19] OUT endpoints interrupt mask + Object *iisoixfrm; // [20:20] Incomplete isochronous IN transfer mask + Object *pxfrm_iisooxfrm; // [21:21] Incomplete periodic transfer mask + Object *fsuspm; // [22:22] Data fetch suspended mask + Object *prtim; // [24:24] Host port interrupt mask + Object *hcim; // [25:25] Host channels interrupt mask + Object *ptxfem; // [26:26] Periodic TxFIFO empty mask + Object *cidschgm; // [28:28] Connector ID status change mask + Object *discint; // [29:29] Disconnect detected interrupt mask + Object *srqim; // [30:30] Session request/new session detected interrupt mask + Object *wuim; // [31:31] Resume/remote wakeup detected interrupt mask + } otg_hs_gintmsk; + + // OTG_HS_GRXSTSR_Host (OTG_HS Receive status debug read register (host mode)) bitfields. + struct { + Object *chnum; // [0:3] Channel number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + } otg_hs_grxstsr_host; + + // OTG_HS_GRXSTSP_Host (OTG_HS status read and pop register (host mode)) bitfields. + struct { + Object *chnum; // [0:3] Channel number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + } otg_hs_grxstsp_host; + + // OTG_HS_GRXFSIZ (OTG_HS Receive FIFO size register) bitfields. + struct { + Object *rxfd; // [0:15] RxFIFO depth + } otg_hs_grxfsiz; + + // OTG_HS_GNPTXFSIZ_Host (OTG_HS nonperiodic transmit FIFO size register (host mode)) bitfields. + struct { + Object *nptxfsa; // [0:15] Nonperiodic transmit RAM start address + Object *nptxfd; // [16:31] Nonperiodic TxFIFO depth + } otg_hs_gnptxfsiz_host; + + // OTG_HS_TX0FSIZ_Peripheral (Endpoint 0 transmit FIFO size (peripheral mode)) bitfields. + struct { + Object *tx0fsa; // [0:15] Endpoint 0 transmit RAM start address + Object *tx0fd; // [16:31] Endpoint 0 TxFIFO depth + } otg_hs_tx0fsiz_peripheral; + + // OTG_HS_GNPTXSTS (OTG_HS nonperiodic transmit FIFO/queue status register) bitfields. + struct { + Object *nptxfsav; // [0:15] Nonperiodic TxFIFO space available + Object *nptqxsav; // [16:23] Nonperiodic transmit request queue space available + Object *nptxqtop; // [24:30] Top of the nonperiodic transmit request queue + } otg_hs_gnptxsts; + + // OTG_HS_GCCFG (OTG_HS general core configuration register) bitfields. + struct { + Object *pwrdwn; // [16:16] Power down + Object *i2cpaden; // [17:17] Enable I2C bus connection for the external I2C PHY interface + Object *vbusasen; // [18:18] Enable the VBUS sensing device + Object *vbusbsen; // [19:19] Enable the VBUS sensing device + Object *sofouten; // [20:20] SOF output enable + Object *novbussens; // [21:21] VBUS sensing disable option + } otg_hs_gccfg; + + // OTG_HS_CID (OTG_HS core ID register) bitfields. + struct { + Object *product_id; // [0:31] Product ID field + } otg_hs_cid; + + // OTG_HS_HPTXFSIZ (OTG_HS Host periodic transmit FIFO size register) bitfields. + struct { + Object *ptxsa; // [0:15] Host periodic TxFIFO start address + Object *ptxfd; // [16:31] Host periodic TxFIFO depth + } otg_hs_hptxfsiz; + + // OTG_HS_DIEPTXF1 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf1; + + // OTG_HS_DIEPTXF2 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf2; + + // OTG_HS_DIEPTXF3 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf3; + + // OTG_HS_DIEPTXF4 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf4; + + // OTG_HS_DIEPTXF5 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf5; + + // OTG_HS_DIEPTXF6 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf6; + + // OTG_HS_DIEPTXF7 (OTG_HS device IN endpoint transmit FIFO size register) bitfields. + struct { + Object *ineptxsa; // [0:15] IN endpoint FIFOx transmit RAM start address + Object *ineptxfd; // [16:31] IN endpoint TxFIFO depth + } otg_hs_dieptxf7; + + // OTG_HS_GRXSTSR_Peripheral (OTG_HS Receive status debug read register (peripheral mode mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } otg_hs_grxstsr_peripheral; + + // OTG_HS_GRXSTSP_Peripheral (OTG_HS status read and pop register (peripheral mode)) bitfields. + struct { + Object *epnum; // [0:3] Endpoint number + Object *bcnt; // [4:14] Byte count + Object *dpid; // [15:16] Data PID + Object *pktsts; // [17:20] Packet status + Object *frmnum; // [21:24] Frame number + } otg_hs_grxstsp_peripheral; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_GLOBALState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_GLOBAL_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_host.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_host.c new file mode 100644 index 0000000000..4067970f43 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_host.c @@ -0,0 +1,986 @@ +/* + * STM32 - OTG_HS_HOST (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_hs_host_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_hcfg = cm_object_get_child_by_name(obj, "OTG_HS_HCFG"); + state->u.f4.reg.otg_hs_hfir = cm_object_get_child_by_name(obj, "OTG_HS_HFIR"); + state->u.f4.reg.otg_hs_hfnum = cm_object_get_child_by_name(obj, "OTG_HS_HFNUM"); + state->u.f4.reg.otg_hs_hptxsts = cm_object_get_child_by_name(obj, "OTG_HS_HPTXSTS"); + state->u.f4.reg.otg_hs_haint = cm_object_get_child_by_name(obj, "OTG_HS_HAINT"); + state->u.f4.reg.otg_hs_haintmsk = cm_object_get_child_by_name(obj, "OTG_HS_HAINTMSK"); + state->u.f4.reg.otg_hs_hprt = cm_object_get_child_by_name(obj, "OTG_HS_HPRT"); + state->u.f4.reg.otg_hs_hcchar0 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR0"); + state->u.f4.reg.otg_hs_hcchar1 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR1"); + state->u.f4.reg.otg_hs_hcchar2 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR2"); + state->u.f4.reg.otg_hs_hcchar3 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR3"); + state->u.f4.reg.otg_hs_hcchar4 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR4"); + state->u.f4.reg.otg_hs_hcchar5 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR5"); + state->u.f4.reg.otg_hs_hcchar6 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR6"); + state->u.f4.reg.otg_hs_hcchar7 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR7"); + state->u.f4.reg.otg_hs_hcchar8 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR8"); + state->u.f4.reg.otg_hs_hcchar9 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR9"); + state->u.f4.reg.otg_hs_hcchar10 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR10"); + state->u.f4.reg.otg_hs_hcchar11 = cm_object_get_child_by_name(obj, "OTG_HS_HCCHAR11"); + state->u.f4.reg.otg_hs_hcsplt0 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT0"); + state->u.f4.reg.otg_hs_hcsplt1 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT1"); + state->u.f4.reg.otg_hs_hcsplt2 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT2"); + state->u.f4.reg.otg_hs_hcsplt3 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT3"); + state->u.f4.reg.otg_hs_hcsplt4 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT4"); + state->u.f4.reg.otg_hs_hcsplt5 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT5"); + state->u.f4.reg.otg_hs_hcsplt6 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT6"); + state->u.f4.reg.otg_hs_hcsplt7 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT7"); + state->u.f4.reg.otg_hs_hcsplt8 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT8"); + state->u.f4.reg.otg_hs_hcsplt9 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT9"); + state->u.f4.reg.otg_hs_hcsplt10 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT10"); + state->u.f4.reg.otg_hs_hcsplt11 = cm_object_get_child_by_name(obj, "OTG_HS_HCSPLT11"); + state->u.f4.reg.otg_hs_hcint0 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT0"); + state->u.f4.reg.otg_hs_hcint1 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT1"); + state->u.f4.reg.otg_hs_hcint2 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT2"); + state->u.f4.reg.otg_hs_hcint3 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT3"); + state->u.f4.reg.otg_hs_hcint4 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT4"); + state->u.f4.reg.otg_hs_hcint5 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT5"); + state->u.f4.reg.otg_hs_hcint6 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT6"); + state->u.f4.reg.otg_hs_hcint7 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT7"); + state->u.f4.reg.otg_hs_hcint8 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT8"); + state->u.f4.reg.otg_hs_hcint9 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT9"); + state->u.f4.reg.otg_hs_hcint10 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT10"); + state->u.f4.reg.otg_hs_hcint11 = cm_object_get_child_by_name(obj, "OTG_HS_HCINT11"); + state->u.f4.reg.otg_hs_hcintmsk0 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK0"); + state->u.f4.reg.otg_hs_hcintmsk1 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK1"); + state->u.f4.reg.otg_hs_hcintmsk2 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK2"); + state->u.f4.reg.otg_hs_hcintmsk3 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK3"); + state->u.f4.reg.otg_hs_hcintmsk4 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK4"); + state->u.f4.reg.otg_hs_hcintmsk5 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK5"); + state->u.f4.reg.otg_hs_hcintmsk6 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK6"); + state->u.f4.reg.otg_hs_hcintmsk7 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK7"); + state->u.f4.reg.otg_hs_hcintmsk8 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK8"); + state->u.f4.reg.otg_hs_hcintmsk9 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK9"); + state->u.f4.reg.otg_hs_hcintmsk10 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK10"); + state->u.f4.reg.otg_hs_hcintmsk11 = cm_object_get_child_by_name(obj, "OTG_HS_HCINTMSK11"); + state->u.f4.reg.otg_hs_hctsiz0 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ0"); + state->u.f4.reg.otg_hs_hctsiz1 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ1"); + state->u.f4.reg.otg_hs_hctsiz2 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ2"); + state->u.f4.reg.otg_hs_hctsiz3 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ3"); + state->u.f4.reg.otg_hs_hctsiz4 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ4"); + state->u.f4.reg.otg_hs_hctsiz5 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ5"); + state->u.f4.reg.otg_hs_hctsiz6 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ6"); + state->u.f4.reg.otg_hs_hctsiz7 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ7"); + state->u.f4.reg.otg_hs_hctsiz8 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ8"); + state->u.f4.reg.otg_hs_hctsiz9 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ9"); + state->u.f4.reg.otg_hs_hctsiz10 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ10"); + state->u.f4.reg.otg_hs_hctsiz11 = cm_object_get_child_by_name(obj, "OTG_HS_HCTSIZ11"); + state->u.f4.reg.otg_hs_hcdma0 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA0"); + state->u.f4.reg.otg_hs_hcdma1 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA1"); + state->u.f4.reg.otg_hs_hcdma2 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA2"); + state->u.f4.reg.otg_hs_hcdma3 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA3"); + state->u.f4.reg.otg_hs_hcdma4 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA4"); + state->u.f4.reg.otg_hs_hcdma5 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA5"); + state->u.f4.reg.otg_hs_hcdma6 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA6"); + state->u.f4.reg.otg_hs_hcdma7 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA7"); + state->u.f4.reg.otg_hs_hcdma8 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA8"); + state->u.f4.reg.otg_hs_hcdma9 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA9"); + state->u.f4.reg.otg_hs_hcdma10 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA10"); + state->u.f4.reg.otg_hs_hcdma11 = cm_object_get_child_by_name(obj, "OTG_HS_HCDMA11"); + + + // OTG_HS_HCFG bitfields. + state->u.f4.fld.otg_hs_hcfg.fslspcs = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcfg, "FSLSPCS"); + state->u.f4.fld.otg_hs_hcfg.fslss = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcfg, "FSLSS"); + + // OTG_HS_HFIR bitfields. + state->u.f4.fld.otg_hs_hfir.frivl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hfir, "FRIVL"); + + // OTG_HS_HFNUM bitfields. + state->u.f4.fld.otg_hs_hfnum.frnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hfnum, "FRNUM"); + state->u.f4.fld.otg_hs_hfnum.ftrem = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hfnum, "FTREM"); + + // OTG_HS_HPTXSTS bitfields. + state->u.f4.fld.otg_hs_hptxsts.ptxfsavl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxsts, "PTXFSAVL"); + state->u.f4.fld.otg_hs_hptxsts.ptxqsav = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxsts, "PTXQSAV"); + state->u.f4.fld.otg_hs_hptxsts.ptxqtop = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hptxsts, "PTXQTOP"); + + // OTG_HS_HAINT bitfields. + state->u.f4.fld.otg_hs_haint.haint = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_haint, "HAINT"); + + // OTG_HS_HAINTMSK bitfields. + state->u.f4.fld.otg_hs_haintmsk.haintm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_haintmsk, "HAINTM"); + + // OTG_HS_HPRT bitfields. + state->u.f4.fld.otg_hs_hprt.pcsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PCSTS"); + state->u.f4.fld.otg_hs_hprt.pcdet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PCDET"); + state->u.f4.fld.otg_hs_hprt.pena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PENA"); + state->u.f4.fld.otg_hs_hprt.penchng = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PENCHNG"); + state->u.f4.fld.otg_hs_hprt.poca = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "POCA"); + state->u.f4.fld.otg_hs_hprt.pocchng = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "POCCHNG"); + state->u.f4.fld.otg_hs_hprt.pres = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PRES"); + state->u.f4.fld.otg_hs_hprt.psusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PSUSP"); + state->u.f4.fld.otg_hs_hprt.prst = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PRST"); + state->u.f4.fld.otg_hs_hprt.plsts = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PLSTS"); + state->u.f4.fld.otg_hs_hprt.ppwr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PPWR"); + state->u.f4.fld.otg_hs_hprt.ptctl = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PTCTL"); + state->u.f4.fld.otg_hs_hprt.pspd = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hprt, "PSPD"); + + // OTG_HS_HCCHAR0 bitfields. + state->u.f4.fld.otg_hs_hcchar0.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar0.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar0.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar0.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar0.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar0.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "MC"); + state->u.f4.fld.otg_hs_hcchar0.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "DAD"); + state->u.f4.fld.otg_hs_hcchar0.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar0.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar0.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar0, "CHENA"); + + // OTG_HS_HCCHAR1 bitfields. + state->u.f4.fld.otg_hs_hcchar1.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar1.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar1.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar1.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar1.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar1.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "MC"); + state->u.f4.fld.otg_hs_hcchar1.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "DAD"); + state->u.f4.fld.otg_hs_hcchar1.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar1.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar1.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar1, "CHENA"); + + // OTG_HS_HCCHAR2 bitfields. + state->u.f4.fld.otg_hs_hcchar2.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar2.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar2.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar2.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar2.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar2.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "MC"); + state->u.f4.fld.otg_hs_hcchar2.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "DAD"); + state->u.f4.fld.otg_hs_hcchar2.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar2.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar2.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar2, "CHENA"); + + // OTG_HS_HCCHAR3 bitfields. + state->u.f4.fld.otg_hs_hcchar3.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar3.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar3.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar3.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar3.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar3.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "MC"); + state->u.f4.fld.otg_hs_hcchar3.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "DAD"); + state->u.f4.fld.otg_hs_hcchar3.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar3.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar3.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar3, "CHENA"); + + // OTG_HS_HCCHAR4 bitfields. + state->u.f4.fld.otg_hs_hcchar4.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar4.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar4.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar4.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar4.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar4.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "MC"); + state->u.f4.fld.otg_hs_hcchar4.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "DAD"); + state->u.f4.fld.otg_hs_hcchar4.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar4.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar4.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar4, "CHENA"); + + // OTG_HS_HCCHAR5 bitfields. + state->u.f4.fld.otg_hs_hcchar5.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar5.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar5.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar5.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar5.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar5.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "MC"); + state->u.f4.fld.otg_hs_hcchar5.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "DAD"); + state->u.f4.fld.otg_hs_hcchar5.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar5.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar5.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar5, "CHENA"); + + // OTG_HS_HCCHAR6 bitfields. + state->u.f4.fld.otg_hs_hcchar6.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar6.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar6.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar6.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar6.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar6.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "MC"); + state->u.f4.fld.otg_hs_hcchar6.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "DAD"); + state->u.f4.fld.otg_hs_hcchar6.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar6.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar6.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar6, "CHENA"); + + // OTG_HS_HCCHAR7 bitfields. + state->u.f4.fld.otg_hs_hcchar7.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar7.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar7.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar7.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar7.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar7.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "MC"); + state->u.f4.fld.otg_hs_hcchar7.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "DAD"); + state->u.f4.fld.otg_hs_hcchar7.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar7.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar7.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar7, "CHENA"); + + // OTG_HS_HCCHAR8 bitfields. + state->u.f4.fld.otg_hs_hcchar8.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar8.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar8.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar8.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar8.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar8.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "MC"); + state->u.f4.fld.otg_hs_hcchar8.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "DAD"); + state->u.f4.fld.otg_hs_hcchar8.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar8.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar8.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar8, "CHENA"); + + // OTG_HS_HCCHAR9 bitfields. + state->u.f4.fld.otg_hs_hcchar9.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar9.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar9.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar9.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar9.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar9.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "MC"); + state->u.f4.fld.otg_hs_hcchar9.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "DAD"); + state->u.f4.fld.otg_hs_hcchar9.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar9.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar9.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar9, "CHENA"); + + // OTG_HS_HCCHAR10 bitfields. + state->u.f4.fld.otg_hs_hcchar10.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar10.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar10.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar10.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar10.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar10.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "MC"); + state->u.f4.fld.otg_hs_hcchar10.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "DAD"); + state->u.f4.fld.otg_hs_hcchar10.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar10.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar10.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar10, "CHENA"); + + // OTG_HS_HCCHAR11 bitfields. + state->u.f4.fld.otg_hs_hcchar11.mpsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "MPSIZ"); + state->u.f4.fld.otg_hs_hcchar11.epnum = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "EPNUM"); + state->u.f4.fld.otg_hs_hcchar11.epdir = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "EPDIR"); + state->u.f4.fld.otg_hs_hcchar11.lsdev = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "LSDEV"); + state->u.f4.fld.otg_hs_hcchar11.eptyp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "EPTYP"); + state->u.f4.fld.otg_hs_hcchar11.mc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "MC"); + state->u.f4.fld.otg_hs_hcchar11.dad = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "DAD"); + state->u.f4.fld.otg_hs_hcchar11.oddfrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "ODDFRM"); + state->u.f4.fld.otg_hs_hcchar11.chdis = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "CHDIS"); + state->u.f4.fld.otg_hs_hcchar11.chena = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcchar11, "CHENA"); + + // OTG_HS_HCSPLT0 bitfields. + state->u.f4.fld.otg_hs_hcsplt0.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt0.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt0.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt0.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt0.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt0, "SPLITEN"); + + // OTG_HS_HCSPLT1 bitfields. + state->u.f4.fld.otg_hs_hcsplt1.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt1.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt1.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt1.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt1.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt1, "SPLITEN"); + + // OTG_HS_HCSPLT2 bitfields. + state->u.f4.fld.otg_hs_hcsplt2.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt2.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt2.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt2.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt2.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt2, "SPLITEN"); + + // OTG_HS_HCSPLT3 bitfields. + state->u.f4.fld.otg_hs_hcsplt3.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt3.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt3.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt3.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt3.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt3, "SPLITEN"); + + // OTG_HS_HCSPLT4 bitfields. + state->u.f4.fld.otg_hs_hcsplt4.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt4.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt4.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt4.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt4.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt4, "SPLITEN"); + + // OTG_HS_HCSPLT5 bitfields. + state->u.f4.fld.otg_hs_hcsplt5.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt5.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt5.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt5.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt5.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt5, "SPLITEN"); + + // OTG_HS_HCSPLT6 bitfields. + state->u.f4.fld.otg_hs_hcsplt6.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt6.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt6.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt6.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt6.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt6, "SPLITEN"); + + // OTG_HS_HCSPLT7 bitfields. + state->u.f4.fld.otg_hs_hcsplt7.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt7.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt7.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt7.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt7.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt7, "SPLITEN"); + + // OTG_HS_HCSPLT8 bitfields. + state->u.f4.fld.otg_hs_hcsplt8.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt8.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt8.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt8.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt8.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt8, "SPLITEN"); + + // OTG_HS_HCSPLT9 bitfields. + state->u.f4.fld.otg_hs_hcsplt9.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt9.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt9.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt9.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt9.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt9, "SPLITEN"); + + // OTG_HS_HCSPLT10 bitfields. + state->u.f4.fld.otg_hs_hcsplt10.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt10.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt10.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt10.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt10.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt10, "SPLITEN"); + + // OTG_HS_HCSPLT11 bitfields. + state->u.f4.fld.otg_hs_hcsplt11.prtaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "PRTADDR"); + state->u.f4.fld.otg_hs_hcsplt11.hubaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "HUBADDR"); + state->u.f4.fld.otg_hs_hcsplt11.xactpos = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "XACTPOS"); + state->u.f4.fld.otg_hs_hcsplt11.complsplt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "COMPLSPLT"); + state->u.f4.fld.otg_hs_hcsplt11.spliten = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcsplt11, "SPLITEN"); + + // OTG_HS_HCINT0 bitfields. + state->u.f4.fld.otg_hs_hcint0.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "XFRC"); + state->u.f4.fld.otg_hs_hcint0.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "CHH"); + state->u.f4.fld.otg_hs_hcint0.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "AHBERR"); + state->u.f4.fld.otg_hs_hcint0.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "STALL"); + state->u.f4.fld.otg_hs_hcint0.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "NAK"); + state->u.f4.fld.otg_hs_hcint0.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "ACK"); + state->u.f4.fld.otg_hs_hcint0.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "NYET"); + state->u.f4.fld.otg_hs_hcint0.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "TXERR"); + state->u.f4.fld.otg_hs_hcint0.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "BBERR"); + state->u.f4.fld.otg_hs_hcint0.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "FRMOR"); + state->u.f4.fld.otg_hs_hcint0.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint0, "DTERR"); + + // OTG_HS_HCINT1 bitfields. + state->u.f4.fld.otg_hs_hcint1.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "XFRC"); + state->u.f4.fld.otg_hs_hcint1.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "CHH"); + state->u.f4.fld.otg_hs_hcint1.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "AHBERR"); + state->u.f4.fld.otg_hs_hcint1.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "STALL"); + state->u.f4.fld.otg_hs_hcint1.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "NAK"); + state->u.f4.fld.otg_hs_hcint1.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "ACK"); + state->u.f4.fld.otg_hs_hcint1.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "NYET"); + state->u.f4.fld.otg_hs_hcint1.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "TXERR"); + state->u.f4.fld.otg_hs_hcint1.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "BBERR"); + state->u.f4.fld.otg_hs_hcint1.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "FRMOR"); + state->u.f4.fld.otg_hs_hcint1.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint1, "DTERR"); + + // OTG_HS_HCINT2 bitfields. + state->u.f4.fld.otg_hs_hcint2.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "XFRC"); + state->u.f4.fld.otg_hs_hcint2.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "CHH"); + state->u.f4.fld.otg_hs_hcint2.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "AHBERR"); + state->u.f4.fld.otg_hs_hcint2.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "STALL"); + state->u.f4.fld.otg_hs_hcint2.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "NAK"); + state->u.f4.fld.otg_hs_hcint2.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "ACK"); + state->u.f4.fld.otg_hs_hcint2.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "NYET"); + state->u.f4.fld.otg_hs_hcint2.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "TXERR"); + state->u.f4.fld.otg_hs_hcint2.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "BBERR"); + state->u.f4.fld.otg_hs_hcint2.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "FRMOR"); + state->u.f4.fld.otg_hs_hcint2.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint2, "DTERR"); + + // OTG_HS_HCINT3 bitfields. + state->u.f4.fld.otg_hs_hcint3.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "XFRC"); + state->u.f4.fld.otg_hs_hcint3.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "CHH"); + state->u.f4.fld.otg_hs_hcint3.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "AHBERR"); + state->u.f4.fld.otg_hs_hcint3.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "STALL"); + state->u.f4.fld.otg_hs_hcint3.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "NAK"); + state->u.f4.fld.otg_hs_hcint3.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "ACK"); + state->u.f4.fld.otg_hs_hcint3.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "NYET"); + state->u.f4.fld.otg_hs_hcint3.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "TXERR"); + state->u.f4.fld.otg_hs_hcint3.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "BBERR"); + state->u.f4.fld.otg_hs_hcint3.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "FRMOR"); + state->u.f4.fld.otg_hs_hcint3.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint3, "DTERR"); + + // OTG_HS_HCINT4 bitfields. + state->u.f4.fld.otg_hs_hcint4.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "XFRC"); + state->u.f4.fld.otg_hs_hcint4.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "CHH"); + state->u.f4.fld.otg_hs_hcint4.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "AHBERR"); + state->u.f4.fld.otg_hs_hcint4.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "STALL"); + state->u.f4.fld.otg_hs_hcint4.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "NAK"); + state->u.f4.fld.otg_hs_hcint4.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "ACK"); + state->u.f4.fld.otg_hs_hcint4.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "NYET"); + state->u.f4.fld.otg_hs_hcint4.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "TXERR"); + state->u.f4.fld.otg_hs_hcint4.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "BBERR"); + state->u.f4.fld.otg_hs_hcint4.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "FRMOR"); + state->u.f4.fld.otg_hs_hcint4.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint4, "DTERR"); + + // OTG_HS_HCINT5 bitfields. + state->u.f4.fld.otg_hs_hcint5.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "XFRC"); + state->u.f4.fld.otg_hs_hcint5.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "CHH"); + state->u.f4.fld.otg_hs_hcint5.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "AHBERR"); + state->u.f4.fld.otg_hs_hcint5.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "STALL"); + state->u.f4.fld.otg_hs_hcint5.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "NAK"); + state->u.f4.fld.otg_hs_hcint5.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "ACK"); + state->u.f4.fld.otg_hs_hcint5.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "NYET"); + state->u.f4.fld.otg_hs_hcint5.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "TXERR"); + state->u.f4.fld.otg_hs_hcint5.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "BBERR"); + state->u.f4.fld.otg_hs_hcint5.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "FRMOR"); + state->u.f4.fld.otg_hs_hcint5.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint5, "DTERR"); + + // OTG_HS_HCINT6 bitfields. + state->u.f4.fld.otg_hs_hcint6.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "XFRC"); + state->u.f4.fld.otg_hs_hcint6.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "CHH"); + state->u.f4.fld.otg_hs_hcint6.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "AHBERR"); + state->u.f4.fld.otg_hs_hcint6.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "STALL"); + state->u.f4.fld.otg_hs_hcint6.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "NAK"); + state->u.f4.fld.otg_hs_hcint6.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "ACK"); + state->u.f4.fld.otg_hs_hcint6.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "NYET"); + state->u.f4.fld.otg_hs_hcint6.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "TXERR"); + state->u.f4.fld.otg_hs_hcint6.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "BBERR"); + state->u.f4.fld.otg_hs_hcint6.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "FRMOR"); + state->u.f4.fld.otg_hs_hcint6.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint6, "DTERR"); + + // OTG_HS_HCINT7 bitfields. + state->u.f4.fld.otg_hs_hcint7.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "XFRC"); + state->u.f4.fld.otg_hs_hcint7.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "CHH"); + state->u.f4.fld.otg_hs_hcint7.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "AHBERR"); + state->u.f4.fld.otg_hs_hcint7.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "STALL"); + state->u.f4.fld.otg_hs_hcint7.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "NAK"); + state->u.f4.fld.otg_hs_hcint7.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "ACK"); + state->u.f4.fld.otg_hs_hcint7.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "NYET"); + state->u.f4.fld.otg_hs_hcint7.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "TXERR"); + state->u.f4.fld.otg_hs_hcint7.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "BBERR"); + state->u.f4.fld.otg_hs_hcint7.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "FRMOR"); + state->u.f4.fld.otg_hs_hcint7.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint7, "DTERR"); + + // OTG_HS_HCINT8 bitfields. + state->u.f4.fld.otg_hs_hcint8.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "XFRC"); + state->u.f4.fld.otg_hs_hcint8.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "CHH"); + state->u.f4.fld.otg_hs_hcint8.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "AHBERR"); + state->u.f4.fld.otg_hs_hcint8.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "STALL"); + state->u.f4.fld.otg_hs_hcint8.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "NAK"); + state->u.f4.fld.otg_hs_hcint8.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "ACK"); + state->u.f4.fld.otg_hs_hcint8.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "NYET"); + state->u.f4.fld.otg_hs_hcint8.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "TXERR"); + state->u.f4.fld.otg_hs_hcint8.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "BBERR"); + state->u.f4.fld.otg_hs_hcint8.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "FRMOR"); + state->u.f4.fld.otg_hs_hcint8.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint8, "DTERR"); + + // OTG_HS_HCINT9 bitfields. + state->u.f4.fld.otg_hs_hcint9.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "XFRC"); + state->u.f4.fld.otg_hs_hcint9.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "CHH"); + state->u.f4.fld.otg_hs_hcint9.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "AHBERR"); + state->u.f4.fld.otg_hs_hcint9.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "STALL"); + state->u.f4.fld.otg_hs_hcint9.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "NAK"); + state->u.f4.fld.otg_hs_hcint9.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "ACK"); + state->u.f4.fld.otg_hs_hcint9.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "NYET"); + state->u.f4.fld.otg_hs_hcint9.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "TXERR"); + state->u.f4.fld.otg_hs_hcint9.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "BBERR"); + state->u.f4.fld.otg_hs_hcint9.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "FRMOR"); + state->u.f4.fld.otg_hs_hcint9.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint9, "DTERR"); + + // OTG_HS_HCINT10 bitfields. + state->u.f4.fld.otg_hs_hcint10.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "XFRC"); + state->u.f4.fld.otg_hs_hcint10.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "CHH"); + state->u.f4.fld.otg_hs_hcint10.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "AHBERR"); + state->u.f4.fld.otg_hs_hcint10.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "STALL"); + state->u.f4.fld.otg_hs_hcint10.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "NAK"); + state->u.f4.fld.otg_hs_hcint10.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "ACK"); + state->u.f4.fld.otg_hs_hcint10.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "NYET"); + state->u.f4.fld.otg_hs_hcint10.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "TXERR"); + state->u.f4.fld.otg_hs_hcint10.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "BBERR"); + state->u.f4.fld.otg_hs_hcint10.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "FRMOR"); + state->u.f4.fld.otg_hs_hcint10.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint10, "DTERR"); + + // OTG_HS_HCINT11 bitfields. + state->u.f4.fld.otg_hs_hcint11.xfrc = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "XFRC"); + state->u.f4.fld.otg_hs_hcint11.chh = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "CHH"); + state->u.f4.fld.otg_hs_hcint11.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "AHBERR"); + state->u.f4.fld.otg_hs_hcint11.stall = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "STALL"); + state->u.f4.fld.otg_hs_hcint11.nak = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "NAK"); + state->u.f4.fld.otg_hs_hcint11.ack = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "ACK"); + state->u.f4.fld.otg_hs_hcint11.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "NYET"); + state->u.f4.fld.otg_hs_hcint11.txerr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "TXERR"); + state->u.f4.fld.otg_hs_hcint11.bberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "BBERR"); + state->u.f4.fld.otg_hs_hcint11.frmor = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "FRMOR"); + state->u.f4.fld.otg_hs_hcint11.dterr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcint11, "DTERR"); + + // OTG_HS_HCINTMSK0 bitfields. + state->u.f4.fld.otg_hs_hcintmsk0.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk0.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk0.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk0.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk0.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk0.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk0.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk0.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk0.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk0.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk0.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk0, "DTERRM"); + + // OTG_HS_HCINTMSK1 bitfields. + state->u.f4.fld.otg_hs_hcintmsk1.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk1.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk1.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk1.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk1.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk1.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk1.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk1.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk1.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk1.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk1.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk1, "DTERRM"); + + // OTG_HS_HCINTMSK2 bitfields. + state->u.f4.fld.otg_hs_hcintmsk2.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk2.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk2.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk2.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk2.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk2.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk2.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk2.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk2.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk2.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk2.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk2, "DTERRM"); + + // OTG_HS_HCINTMSK3 bitfields. + state->u.f4.fld.otg_hs_hcintmsk3.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk3.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk3.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk3.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk3.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk3.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk3.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk3.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk3.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk3.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk3.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk3, "DTERRM"); + + // OTG_HS_HCINTMSK4 bitfields. + state->u.f4.fld.otg_hs_hcintmsk4.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk4.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk4.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk4.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk4.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk4.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk4.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk4.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk4.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk4.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk4.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk4, "DTERRM"); + + // OTG_HS_HCINTMSK5 bitfields. + state->u.f4.fld.otg_hs_hcintmsk5.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk5.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk5.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk5.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk5.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk5.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk5.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk5.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk5.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk5.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk5.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk5, "DTERRM"); + + // OTG_HS_HCINTMSK6 bitfields. + state->u.f4.fld.otg_hs_hcintmsk6.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk6.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk6.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk6.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk6.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk6.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk6.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk6.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk6.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk6.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk6.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk6, "DTERRM"); + + // OTG_HS_HCINTMSK7 bitfields. + state->u.f4.fld.otg_hs_hcintmsk7.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk7.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk7.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk7.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk7.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk7.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk7.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk7.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk7.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk7.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk7.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk7, "DTERRM"); + + // OTG_HS_HCINTMSK8 bitfields. + state->u.f4.fld.otg_hs_hcintmsk8.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk8.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk8.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk8.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk8.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk8.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk8.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk8.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk8.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk8.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk8.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk8, "DTERRM"); + + // OTG_HS_HCINTMSK9 bitfields. + state->u.f4.fld.otg_hs_hcintmsk9.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk9.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk9.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk9.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk9.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk9.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk9.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk9.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk9.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk9.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk9.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk9, "DTERRM"); + + // OTG_HS_HCINTMSK10 bitfields. + state->u.f4.fld.otg_hs_hcintmsk10.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk10.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk10.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk10.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk10.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk10.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk10.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk10.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk10.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk10.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk10.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk10, "DTERRM"); + + // OTG_HS_HCINTMSK11 bitfields. + state->u.f4.fld.otg_hs_hcintmsk11.xfrcm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "XFRCM"); + state->u.f4.fld.otg_hs_hcintmsk11.chhm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "CHHM"); + state->u.f4.fld.otg_hs_hcintmsk11.ahberr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "AHBERR"); + state->u.f4.fld.otg_hs_hcintmsk11.stallm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "STALLM"); + state->u.f4.fld.otg_hs_hcintmsk11.nakm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "NAKM"); + state->u.f4.fld.otg_hs_hcintmsk11.ackm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "ACKM"); + state->u.f4.fld.otg_hs_hcintmsk11.nyet = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "NYET"); + state->u.f4.fld.otg_hs_hcintmsk11.txerrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "TXERRM"); + state->u.f4.fld.otg_hs_hcintmsk11.bberrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "BBERRM"); + state->u.f4.fld.otg_hs_hcintmsk11.frmorm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "FRMORM"); + state->u.f4.fld.otg_hs_hcintmsk11.dterrm = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcintmsk11, "DTERRM"); + + // OTG_HS_HCTSIZ0 bitfields. + state->u.f4.fld.otg_hs_hctsiz0.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz0, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz0.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz0, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz0.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz0, "DPID"); + + // OTG_HS_HCTSIZ1 bitfields. + state->u.f4.fld.otg_hs_hctsiz1.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz1, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz1.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz1, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz1.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz1, "DPID"); + + // OTG_HS_HCTSIZ2 bitfields. + state->u.f4.fld.otg_hs_hctsiz2.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz2, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz2.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz2, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz2.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz2, "DPID"); + + // OTG_HS_HCTSIZ3 bitfields. + state->u.f4.fld.otg_hs_hctsiz3.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz3, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz3.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz3, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz3.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz3, "DPID"); + + // OTG_HS_HCTSIZ4 bitfields. + state->u.f4.fld.otg_hs_hctsiz4.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz4, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz4.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz4, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz4.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz4, "DPID"); + + // OTG_HS_HCTSIZ5 bitfields. + state->u.f4.fld.otg_hs_hctsiz5.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz5, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz5.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz5, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz5.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz5, "DPID"); + + // OTG_HS_HCTSIZ6 bitfields. + state->u.f4.fld.otg_hs_hctsiz6.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz6, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz6.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz6, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz6.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz6, "DPID"); + + // OTG_HS_HCTSIZ7 bitfields. + state->u.f4.fld.otg_hs_hctsiz7.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz7, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz7.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz7, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz7.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz7, "DPID"); + + // OTG_HS_HCTSIZ8 bitfields. + state->u.f4.fld.otg_hs_hctsiz8.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz8, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz8.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz8, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz8.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz8, "DPID"); + + // OTG_HS_HCTSIZ9 bitfields. + state->u.f4.fld.otg_hs_hctsiz9.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz9, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz9.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz9, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz9.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz9, "DPID"); + + // OTG_HS_HCTSIZ10 bitfields. + state->u.f4.fld.otg_hs_hctsiz10.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz10, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz10.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz10, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz10.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz10, "DPID"); + + // OTG_HS_HCTSIZ11 bitfields. + state->u.f4.fld.otg_hs_hctsiz11.xfrsiz = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz11, "XFRSIZ"); + state->u.f4.fld.otg_hs_hctsiz11.pktcnt = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz11, "PKTCNT"); + state->u.f4.fld.otg_hs_hctsiz11.dpid = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hctsiz11, "DPID"); + + // OTG_HS_HCDMA0 bitfields. + state->u.f4.fld.otg_hs_hcdma0.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma0, "DMAADDR"); + + // OTG_HS_HCDMA1 bitfields. + state->u.f4.fld.otg_hs_hcdma1.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma1, "DMAADDR"); + + // OTG_HS_HCDMA2 bitfields. + state->u.f4.fld.otg_hs_hcdma2.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma2, "DMAADDR"); + + // OTG_HS_HCDMA3 bitfields. + state->u.f4.fld.otg_hs_hcdma3.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma3, "DMAADDR"); + + // OTG_HS_HCDMA4 bitfields. + state->u.f4.fld.otg_hs_hcdma4.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma4, "DMAADDR"); + + // OTG_HS_HCDMA5 bitfields. + state->u.f4.fld.otg_hs_hcdma5.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma5, "DMAADDR"); + + // OTG_HS_HCDMA6 bitfields. + state->u.f4.fld.otg_hs_hcdma6.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma6, "DMAADDR"); + + // OTG_HS_HCDMA7 bitfields. + state->u.f4.fld.otg_hs_hcdma7.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma7, "DMAADDR"); + + // OTG_HS_HCDMA8 bitfields. + state->u.f4.fld.otg_hs_hcdma8.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma8, "DMAADDR"); + + // OTG_HS_HCDMA9 bitfields. + state->u.f4.fld.otg_hs_hcdma9.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma9, "DMAADDR"); + + // OTG_HS_HCDMA10 bitfields. + state->u.f4.fld.otg_hs_hcdma10.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma10, "DMAADDR"); + + // OTG_HS_HCDMA11 bitfields. + state->u.f4.fld.otg_hs_hcdma11.dmaaddr = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_hcdma11, "DMAADDR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_host_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_host_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_host_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_host_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_host_is_enabled(Object *obj) +{ + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_host_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_host_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_HOST)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_HOSTState *state = STM32_OTG_HS_HOST_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_HOST"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_hs_host_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_host_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_HOSTEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_host_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_HOST); +} + +static void stm32_otg_hs_host_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_host_reset_callback; + dc->realize = stm32_otg_hs_host_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_host_is_enabled; +} + +static const TypeInfo stm32_otg_hs_host_type_info = { + .name = TYPE_STM32_OTG_HS_HOST, + .parent = TYPE_STM32_OTG_HS_HOST_PARENT, + .instance_init = stm32_otg_hs_host_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_HOSTState), + .class_init = stm32_otg_hs_host_class_init_callback, + .class_size = sizeof(STM32OTG_HS_HOSTClass) }; + +static void stm32_otg_hs_host_register_types(void) +{ + type_register_static(&stm32_otg_hs_host_type_info); +} + +type_init(stm32_otg_hs_host_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_host.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_host.h new file mode 100644 index 0000000000..bea043abc9 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_host.h @@ -0,0 +1,1009 @@ +/* + * STM32 - OTG_HS_HOST (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_HOST_H_ +#define STM32_OTG_HS_HOST_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_HOST DEVICE_PATH_STM32 "OTG_HS_HOST" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_HOST TYPE_STM32_PREFIX "otg_hs_host" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_HOST_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_HOSTParentClass; +typedef PeripheralState STM32OTG_HS_HOSTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_HOST_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_HOSTClass, (obj), TYPE_STM32_OTG_HS_HOST) +#define STM32_OTG_HS_HOST_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_HOSTClass, (klass), TYPE_STM32_OTG_HS_HOST) + +typedef struct { + // private: + STM32OTG_HS_HOSTParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_HOSTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_HOST_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_HOSTState, (obj), TYPE_STM32_OTG_HS_HOST) + +typedef struct { + // private: + STM32OTG_HS_HOSTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_HOST (USB on the go high speed) registers. + struct { + Object *otg_hs_hcfg; // 0x0 (OTG_HS host configuration register) + Object *otg_hs_hfir; // 0x4 (OTG_HS Host frame interval register) + Object *otg_hs_hfnum; // 0x8 (OTG_HS host frame number/frame time remaining register) + Object *otg_hs_hptxsts; // 0x10 (OTG_HS_Host periodic transmit FIFO/queue status register) + Object *otg_hs_haint; // 0x14 (OTG_HS Host all channels interrupt register) + Object *otg_hs_haintmsk; // 0x18 (OTG_HS host all channels interrupt mask register) + Object *otg_hs_hprt; // 0x40 (OTG_HS host port control and status register) + Object *otg_hs_hcchar0; // 0x100 (OTG_HS host channel-0 characteristics register) + Object *otg_hs_hcchar1; // 0x120 (OTG_HS host channel-1 characteristics register) + Object *otg_hs_hcchar2; // 0x140 (OTG_HS host channel-2 characteristics register) + Object *otg_hs_hcchar3; // 0x160 (OTG_HS host channel-3 characteristics register) + Object *otg_hs_hcchar4; // 0x180 (OTG_HS host channel-4 characteristics register) + Object *otg_hs_hcchar5; // 0x1A0 (OTG_HS host channel-5 characteristics register) + Object *otg_hs_hcchar6; // 0x1C0 (OTG_HS host channel-6 characteristics register) + Object *otg_hs_hcchar7; // 0x1E0 (OTG_HS host channel-7 characteristics register) + Object *otg_hs_hcchar8; // 0x200 (OTG_HS host channel-8 characteristics register) + Object *otg_hs_hcchar9; // 0x220 (OTG_HS host channel-9 characteristics register) + Object *otg_hs_hcchar10; // 0x240 (OTG_HS host channel-10 characteristics register) + Object *otg_hs_hcchar11; // 0x260 (OTG_HS host channel-11 characteristics register) + Object *otg_hs_hcsplt0; // 0x104 (OTG_HS host channel-0 split control register) + Object *otg_hs_hcsplt1; // 0x124 (OTG_HS host channel-1 split control register) + Object *otg_hs_hcsplt2; // 0x144 (OTG_HS host channel-2 split control register) + Object *otg_hs_hcsplt3; // 0x164 (OTG_HS host channel-3 split control register) + Object *otg_hs_hcsplt4; // 0x184 (OTG_HS host channel-4 split control register) + Object *otg_hs_hcsplt5; // 0x1A4 (OTG_HS host channel-5 split control register) + Object *otg_hs_hcsplt6; // 0x1C4 (OTG_HS host channel-6 split control register) + Object *otg_hs_hcsplt7; // 0x1E4 (OTG_HS host channel-7 split control register) + Object *otg_hs_hcsplt8; // 0x204 (OTG_HS host channel-8 split control register) + Object *otg_hs_hcsplt9; // 0x224 (OTG_HS host channel-9 split control register) + Object *otg_hs_hcsplt10; // 0x244 (OTG_HS host channel-10 split control register) + Object *otg_hs_hcsplt11; // 0x264 (OTG_HS host channel-11 split control register) + Object *otg_hs_hcint0; // 0x108 (OTG_HS host channel-11 interrupt register) + Object *otg_hs_hcint1; // 0x128 (OTG_HS host channel-1 interrupt register) + Object *otg_hs_hcint2; // 0x148 (OTG_HS host channel-2 interrupt register) + Object *otg_hs_hcint3; // 0x168 (OTG_HS host channel-3 interrupt register) + Object *otg_hs_hcint4; // 0x188 (OTG_HS host channel-4 interrupt register) + Object *otg_hs_hcint5; // 0x1A8 (OTG_HS host channel-5 interrupt register) + Object *otg_hs_hcint6; // 0x1C8 (OTG_HS host channel-6 interrupt register) + Object *otg_hs_hcint7; // 0x1E8 (OTG_HS host channel-7 interrupt register) + Object *otg_hs_hcint8; // 0x208 (OTG_HS host channel-8 interrupt register) + Object *otg_hs_hcint9; // 0x228 (OTG_HS host channel-9 interrupt register) + Object *otg_hs_hcint10; // 0x248 (OTG_HS host channel-10 interrupt register) + Object *otg_hs_hcint11; // 0x268 (OTG_HS host channel-11 interrupt register) + Object *otg_hs_hcintmsk0; // 0x10C (OTG_HS host channel-11 interrupt mask register) + Object *otg_hs_hcintmsk1; // 0x12C (OTG_HS host channel-1 interrupt mask register) + Object *otg_hs_hcintmsk2; // 0x14C (OTG_HS host channel-2 interrupt mask register) + Object *otg_hs_hcintmsk3; // 0x16C (OTG_HS host channel-3 interrupt mask register) + Object *otg_hs_hcintmsk4; // 0x18C (OTG_HS host channel-4 interrupt mask register) + Object *otg_hs_hcintmsk5; // 0x1AC (OTG_HS host channel-5 interrupt mask register) + Object *otg_hs_hcintmsk6; // 0x1CC (OTG_HS host channel-6 interrupt mask register) + Object *otg_hs_hcintmsk7; // 0x1EC (OTG_HS host channel-7 interrupt mask register) + Object *otg_hs_hcintmsk8; // 0x20C (OTG_HS host channel-8 interrupt mask register) + Object *otg_hs_hcintmsk9; // 0x22C (OTG_HS host channel-9 interrupt mask register) + Object *otg_hs_hcintmsk10; // 0x24C (OTG_HS host channel-10 interrupt mask register) + Object *otg_hs_hcintmsk11; // 0x26C (OTG_HS host channel-11 interrupt mask register) + Object *otg_hs_hctsiz0; // 0x110 (OTG_HS host channel-11 transfer size register) + Object *otg_hs_hctsiz1; // 0x130 (OTG_HS host channel-1 transfer size register) + Object *otg_hs_hctsiz2; // 0x150 (OTG_HS host channel-2 transfer size register) + Object *otg_hs_hctsiz3; // 0x170 (OTG_HS host channel-3 transfer size register) + Object *otg_hs_hctsiz4; // 0x190 (OTG_HS host channel-4 transfer size register) + Object *otg_hs_hctsiz5; // 0x1B0 (OTG_HS host channel-5 transfer size register) + Object *otg_hs_hctsiz6; // 0x1D0 (OTG_HS host channel-6 transfer size register) + Object *otg_hs_hctsiz7; // 0x1F0 (OTG_HS host channel-7 transfer size register) + Object *otg_hs_hctsiz8; // 0x210 (OTG_HS host channel-8 transfer size register) + Object *otg_hs_hctsiz9; // 0x230 (OTG_HS host channel-9 transfer size register) + Object *otg_hs_hctsiz10; // 0x250 (OTG_HS host channel-10 transfer size register) + Object *otg_hs_hctsiz11; // 0x270 (OTG_HS host channel-11 transfer size register) + Object *otg_hs_hcdma0; // 0x114 (OTG_HS host channel-0 DMA address register) + Object *otg_hs_hcdma1; // 0x134 (OTG_HS host channel-1 DMA address register) + Object *otg_hs_hcdma2; // 0x154 (OTG_HS host channel-2 DMA address register) + Object *otg_hs_hcdma3; // 0x174 (OTG_HS host channel-3 DMA address register) + Object *otg_hs_hcdma4; // 0x194 (OTG_HS host channel-4 DMA address register) + Object *otg_hs_hcdma5; // 0x1B4 (OTG_HS host channel-5 DMA address register) + Object *otg_hs_hcdma6; // 0x1D4 (OTG_HS host channel-6 DMA address register) + Object *otg_hs_hcdma7; // 0x1F4 (OTG_HS host channel-7 DMA address register) + Object *otg_hs_hcdma8; // 0x214 (OTG_HS host channel-8 DMA address register) + Object *otg_hs_hcdma9; // 0x234 (OTG_HS host channel-9 DMA address register) + Object *otg_hs_hcdma10; // 0x254 (OTG_HS host channel-10 DMA address register) + Object *otg_hs_hcdma11; // 0x274 (OTG_HS host channel-11 DMA address register) + } reg; + + struct { + + // OTG_HS_HCFG (OTG_HS host configuration register) bitfields. + struct { + Object *fslspcs; // [0:1] FS/LS PHY clock select + Object *fslss; // [2:2] FS- and LS-only support + } otg_hs_hcfg; + + // OTG_HS_HFIR (OTG_HS Host frame interval register) bitfields. + struct { + Object *frivl; // [0:15] Frame interval + } otg_hs_hfir; + + // OTG_HS_HFNUM (OTG_HS host frame number/frame time remaining register) bitfields. + struct { + Object *frnum; // [0:15] Frame number + Object *ftrem; // [16:31] Frame time remaining + } otg_hs_hfnum; + + // OTG_HS_HPTXSTS (OTG_HS_Host periodic transmit FIFO/queue status register) bitfields. + struct { + Object *ptxfsavl; // [0:15] Periodic transmit data FIFO space available + Object *ptxqsav; // [16:23] Periodic transmit request queue space available + Object *ptxqtop; // [24:31] Top of the periodic transmit request queue + } otg_hs_hptxsts; + + // OTG_HS_HAINT (OTG_HS Host all channels interrupt register) bitfields. + struct { + Object *haint; // [0:15] Channel interrupts + } otg_hs_haint; + + // OTG_HS_HAINTMSK (OTG_HS host all channels interrupt mask register) bitfields. + struct { + Object *haintm; // [0:15] Channel interrupt mask + } otg_hs_haintmsk; + + // OTG_HS_HPRT (OTG_HS host port control and status register) bitfields. + struct { + Object *pcsts; // [0:0] Port connect status + Object *pcdet; // [1:1] Port connect detected + Object *pena; // [2:2] Port enable + Object *penchng; // [3:3] Port enable/disable change + Object *poca; // [4:4] Port overcurrent active + Object *pocchng; // [5:5] Port overcurrent change + Object *pres; // [6:6] Port resume + Object *psusp; // [7:7] Port suspend + Object *prst; // [8:8] Port reset + Object *plsts; // [10:11] Port line status + Object *ppwr; // [12:12] Port power + Object *ptctl; // [13:16] Port test control + Object *pspd; // [17:18] Port speed + } otg_hs_hprt; + + // OTG_HS_HCCHAR0 (OTG_HS host channel-0 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar0; + + // OTG_HS_HCCHAR1 (OTG_HS host channel-1 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar1; + + // OTG_HS_HCCHAR2 (OTG_HS host channel-2 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar2; + + // OTG_HS_HCCHAR3 (OTG_HS host channel-3 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar3; + + // OTG_HS_HCCHAR4 (OTG_HS host channel-4 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar4; + + // OTG_HS_HCCHAR5 (OTG_HS host channel-5 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar5; + + // OTG_HS_HCCHAR6 (OTG_HS host channel-6 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar6; + + // OTG_HS_HCCHAR7 (OTG_HS host channel-7 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar7; + + // OTG_HS_HCCHAR8 (OTG_HS host channel-8 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar8; + + // OTG_HS_HCCHAR9 (OTG_HS host channel-9 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar9; + + // OTG_HS_HCCHAR10 (OTG_HS host channel-10 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar10; + + // OTG_HS_HCCHAR11 (OTG_HS host channel-11 characteristics register) bitfields. + struct { + Object *mpsiz; // [0:10] Maximum packet size + Object *epnum; // [11:14] Endpoint number + Object *epdir; // [15:15] Endpoint direction + Object *lsdev; // [17:17] Low-speed device + Object *eptyp; // [18:19] Endpoint type + Object *mc; // [20:21] Multi Count (MC) / Error Count (EC) + Object *dad; // [22:28] Device address + Object *oddfrm; // [29:29] Odd frame + Object *chdis; // [30:30] Channel disable + Object *chena; // [31:31] Channel enable + } otg_hs_hcchar11; + + // OTG_HS_HCSPLT0 (OTG_HS host channel-0 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt0; + + // OTG_HS_HCSPLT1 (OTG_HS host channel-1 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt1; + + // OTG_HS_HCSPLT2 (OTG_HS host channel-2 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt2; + + // OTG_HS_HCSPLT3 (OTG_HS host channel-3 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt3; + + // OTG_HS_HCSPLT4 (OTG_HS host channel-4 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt4; + + // OTG_HS_HCSPLT5 (OTG_HS host channel-5 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt5; + + // OTG_HS_HCSPLT6 (OTG_HS host channel-6 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt6; + + // OTG_HS_HCSPLT7 (OTG_HS host channel-7 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt7; + + // OTG_HS_HCSPLT8 (OTG_HS host channel-8 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt8; + + // OTG_HS_HCSPLT9 (OTG_HS host channel-9 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt9; + + // OTG_HS_HCSPLT10 (OTG_HS host channel-10 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt10; + + // OTG_HS_HCSPLT11 (OTG_HS host channel-11 split control register) bitfields. + struct { + Object *prtaddr; // [0:6] Port address + Object *hubaddr; // [7:13] Hub address + Object *xactpos; // [14:15] XACTPOS + Object *complsplt; // [16:16] Do complete split + Object *spliten; // [31:31] Split enable + } otg_hs_hcsplt11; + + // OTG_HS_HCINT0 (OTG_HS host channel-11 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint0; + + // OTG_HS_HCINT1 (OTG_HS host channel-1 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint1; + + // OTG_HS_HCINT2 (OTG_HS host channel-2 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint2; + + // OTG_HS_HCINT3 (OTG_HS host channel-3 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint3; + + // OTG_HS_HCINT4 (OTG_HS host channel-4 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint4; + + // OTG_HS_HCINT5 (OTG_HS host channel-5 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint5; + + // OTG_HS_HCINT6 (OTG_HS host channel-6 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint6; + + // OTG_HS_HCINT7 (OTG_HS host channel-7 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint7; + + // OTG_HS_HCINT8 (OTG_HS host channel-8 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint8; + + // OTG_HS_HCINT9 (OTG_HS host channel-9 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint9; + + // OTG_HS_HCINT10 (OTG_HS host channel-10 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint10; + + // OTG_HS_HCINT11 (OTG_HS host channel-11 interrupt register) bitfields. + struct { + Object *xfrc; // [0:0] Transfer completed + Object *chh; // [1:1] Channel halted + Object *ahberr; // [2:2] AHB error + Object *stall; // [3:3] STALL response received interrupt + Object *nak; // [4:4] NAK response received interrupt + Object *ack; // [5:5] ACK response received/transmitted interrupt + Object *nyet; // [6:6] Response received interrupt + Object *txerr; // [7:7] Transaction error + Object *bberr; // [8:8] Babble error + Object *frmor; // [9:9] Frame overrun + Object *dterr; // [10:10] Data toggle error + } otg_hs_hcint11; + + // OTG_HS_HCINTMSK0 (OTG_HS host channel-11 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk0; + + // OTG_HS_HCINTMSK1 (OTG_HS host channel-1 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk1; + + // OTG_HS_HCINTMSK2 (OTG_HS host channel-2 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk2; + + // OTG_HS_HCINTMSK3 (OTG_HS host channel-3 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk3; + + // OTG_HS_HCINTMSK4 (OTG_HS host channel-4 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk4; + + // OTG_HS_HCINTMSK5 (OTG_HS host channel-5 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk5; + + // OTG_HS_HCINTMSK6 (OTG_HS host channel-6 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk6; + + // OTG_HS_HCINTMSK7 (OTG_HS host channel-7 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk7; + + // OTG_HS_HCINTMSK8 (OTG_HS host channel-8 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk8; + + // OTG_HS_HCINTMSK9 (OTG_HS host channel-9 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk9; + + // OTG_HS_HCINTMSK10 (OTG_HS host channel-10 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk10; + + // OTG_HS_HCINTMSK11 (OTG_HS host channel-11 interrupt mask register) bitfields. + struct { + Object *xfrcm; // [0:0] Transfer completed mask + Object *chhm; // [1:1] Channel halted mask + Object *ahberr; // [2:2] AHB error + Object *stallm; // [3:3] STALL response received interrupt mask + Object *nakm; // [4:4] NAK response received interrupt mask + Object *ackm; // [5:5] ACK response received/transmitted interrupt mask + Object *nyet; // [6:6] Response received interrupt mask + Object *txerrm; // [7:7] Transaction error mask + Object *bberrm; // [8:8] Babble error mask + Object *frmorm; // [9:9] Frame overrun mask + Object *dterrm; // [10:10] Data toggle error mask + } otg_hs_hcintmsk11; + + // OTG_HS_HCTSIZ0 (OTG_HS host channel-11 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz0; + + // OTG_HS_HCTSIZ1 (OTG_HS host channel-1 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz1; + + // OTG_HS_HCTSIZ2 (OTG_HS host channel-2 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz2; + + // OTG_HS_HCTSIZ3 (OTG_HS host channel-3 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz3; + + // OTG_HS_HCTSIZ4 (OTG_HS host channel-4 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz4; + + // OTG_HS_HCTSIZ5 (OTG_HS host channel-5 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz5; + + // OTG_HS_HCTSIZ6 (OTG_HS host channel-6 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz6; + + // OTG_HS_HCTSIZ7 (OTG_HS host channel-7 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz7; + + // OTG_HS_HCTSIZ8 (OTG_HS host channel-8 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz8; + + // OTG_HS_HCTSIZ9 (OTG_HS host channel-9 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz9; + + // OTG_HS_HCTSIZ10 (OTG_HS host channel-10 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz10; + + // OTG_HS_HCTSIZ11 (OTG_HS host channel-11 transfer size register) bitfields. + struct { + Object *xfrsiz; // [0:18] Transfer size + Object *pktcnt; // [19:28] Packet count + Object *dpid; // [29:30] Data PID + } otg_hs_hctsiz11; + + // OTG_HS_HCDMA0 (OTG_HS host channel-0 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma0; + + // OTG_HS_HCDMA1 (OTG_HS host channel-1 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma1; + + // OTG_HS_HCDMA2 (OTG_HS host channel-2 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma2; + + // OTG_HS_HCDMA3 (OTG_HS host channel-3 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma3; + + // OTG_HS_HCDMA4 (OTG_HS host channel-4 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma4; + + // OTG_HS_HCDMA5 (OTG_HS host channel-5 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma5; + + // OTG_HS_HCDMA6 (OTG_HS host channel-6 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma6; + + // OTG_HS_HCDMA7 (OTG_HS host channel-7 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma7; + + // OTG_HS_HCDMA8 (OTG_HS host channel-8 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma8; + + // OTG_HS_HCDMA9 (OTG_HS host channel-9 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma9; + + // OTG_HS_HCDMA10 (OTG_HS host channel-10 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma10; + + // OTG_HS_HCDMA11 (OTG_HS host channel-11 DMA address register) bitfields. + struct { + Object *dmaaddr; // [0:31] DMA address + } otg_hs_hcdma11; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_HOSTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_HOST_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_pwrclk.c b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_pwrclk.c new file mode 100644 index 0000000000..0d27666a81 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_pwrclk.c @@ -0,0 +1,240 @@ +/* + * STM32 - OTG_HS_PWRCLK (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_otg_hs_pwrclk_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.otg_hs_pcgcr = cm_object_get_child_by_name(obj, "OTG_HS_PCGCR"); + + + // OTG_HS_PCGCR bitfields. + state->u.f4.fld.otg_hs_pcgcr.stppclk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_pcgcr, "STPPCLK"); + state->u.f4.fld.otg_hs_pcgcr.gatehclk = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_pcgcr, "GATEHCLK"); + state->u.f4.fld.otg_hs_pcgcr.physusp = cm_object_get_child_by_name(state->u.f4.reg.otg_hs_pcgcr, "PHYSUSP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_otg_hs_pwrclk_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_otg_hs_pwrclk_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_otg_hs_pwrclk_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_otg_hs_pwrclk_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_otg_hs_pwrclk_is_enabled(Object *obj) +{ + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_otg_hs_pwrclk_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_otg_hs_pwrclk_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_OTG_HS_PWRCLK)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32OTG_HS_PWRCLKState *state = STM32_OTG_HS_PWRCLK_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "OTG_HS_PWRCLK"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_otg_hs_pwrclk_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_otg_hs_pwrclk_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/OTG_HS_PWRCLKEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_otg_hs_pwrclk_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_OTG_HS_PWRCLK); +} + +static void stm32_otg_hs_pwrclk_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_otg_hs_pwrclk_reset_callback; + dc->realize = stm32_otg_hs_pwrclk_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_otg_hs_pwrclk_is_enabled; +} + +static const TypeInfo stm32_otg_hs_pwrclk_type_info = { + .name = TYPE_STM32_OTG_HS_PWRCLK, + .parent = TYPE_STM32_OTG_HS_PWRCLK_PARENT, + .instance_init = stm32_otg_hs_pwrclk_instance_init_callback, + .instance_size = sizeof(STM32OTG_HS_PWRCLKState), + .class_init = stm32_otg_hs_pwrclk_class_init_callback, + .class_size = sizeof(STM32OTG_HS_PWRCLKClass) }; + +static void stm32_otg_hs_pwrclk_register_types(void) +{ + type_register_static(&stm32_otg_hs_pwrclk_type_info); +} + +type_init(stm32_otg_hs_pwrclk_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_pwrclk.h b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_pwrclk.h new file mode 100644 index 0000000000..e4920732c0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/otg_hs_pwrclk.h @@ -0,0 +1,107 @@ +/* + * STM32 - OTG_HS_PWRCLK (USB on the go high speed) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_OTG_HS_PWRCLK_H_ +#define STM32_OTG_HS_PWRCLK_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_OTG_HS_PWRCLK DEVICE_PATH_STM32 "OTG_HS_PWRCLK" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_OTG_HS_PWRCLK TYPE_STM32_PREFIX "otg_hs_pwrclk" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_OTG_HS_PWRCLK_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32OTG_HS_PWRCLKParentClass; +typedef PeripheralState STM32OTG_HS_PWRCLKParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_OTG_HS_PWRCLK_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32OTG_HS_PWRCLKClass, (obj), TYPE_STM32_OTG_HS_PWRCLK) +#define STM32_OTG_HS_PWRCLK_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32OTG_HS_PWRCLKClass, (klass), TYPE_STM32_OTG_HS_PWRCLK) + +typedef struct { + // private: + STM32OTG_HS_PWRCLKParentClass parent_class; + // public: + + // None, so far. +} STM32OTG_HS_PWRCLKClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_OTG_HS_PWRCLK_STATE(obj) \ + OBJECT_CHECK(STM32OTG_HS_PWRCLKState, (obj), TYPE_STM32_OTG_HS_PWRCLK) + +typedef struct { + // private: + STM32OTG_HS_PWRCLKParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 OTG_HS_PWRCLK (USB on the go high speed) registers. + struct { + Object *otg_hs_pcgcr; // 0x0 (Power and clock gating control register) + } reg; + + struct { + + // OTG_HS_PCGCR (Power and clock gating control register) bitfields. + struct { + Object *stppclk; // [0:0] Stop PHY clock + Object *gatehclk; // [1:1] Gate HCLK + Object *physusp; // [4:4] PHY suspended + } otg_hs_pcgcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32OTG_HS_PWRCLKState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_OTG_HS_PWRCLK_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/pwr.c b/gnu-mcu-eclipse/devices/support/STM32F429x/pwr.c new file mode 100644 index 0000000000..5d879784db --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/pwr.c @@ -0,0 +1,265 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_pwr_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + + + // CR bitfields. + state->u.f4.fld.cr.lpds = cm_object_get_child_by_name(state->u.f4.reg.cr, "LPDS"); + state->u.f4.fld.cr.pdds = cm_object_get_child_by_name(state->u.f4.reg.cr, "PDDS"); + state->u.f4.fld.cr.cwuf = cm_object_get_child_by_name(state->u.f4.reg.cr, "CWUF"); + state->u.f4.fld.cr.csbf = cm_object_get_child_by_name(state->u.f4.reg.cr, "CSBF"); + state->u.f4.fld.cr.pvde = cm_object_get_child_by_name(state->u.f4.reg.cr, "PVDE"); + state->u.f4.fld.cr.pls = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLS"); + state->u.f4.fld.cr.dbp = cm_object_get_child_by_name(state->u.f4.reg.cr, "DBP"); + state->u.f4.fld.cr.fpds = cm_object_get_child_by_name(state->u.f4.reg.cr, "FPDS"); + state->u.f4.fld.cr.lpuds = cm_object_get_child_by_name(state->u.f4.reg.cr, "LPUDS"); + state->u.f4.fld.cr.mruds = cm_object_get_child_by_name(state->u.f4.reg.cr, "MRUDS"); + state->u.f4.fld.cr.adcdc1 = cm_object_get_child_by_name(state->u.f4.reg.cr, "ADCDC1"); + state->u.f4.fld.cr.vos = cm_object_get_child_by_name(state->u.f4.reg.cr, "VOS"); + state->u.f4.fld.cr.oden = cm_object_get_child_by_name(state->u.f4.reg.cr, "ODEN"); + state->u.f4.fld.cr.odswen = cm_object_get_child_by_name(state->u.f4.reg.cr, "ODSWEN"); + state->u.f4.fld.cr.uden = cm_object_get_child_by_name(state->u.f4.reg.cr, "UDEN"); + + // CSR bitfields. + state->u.f4.fld.csr.wuf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WUF"); + state->u.f4.fld.csr.sbf = cm_object_get_child_by_name(state->u.f4.reg.csr, "SBF"); + state->u.f4.fld.csr.pvdo = cm_object_get_child_by_name(state->u.f4.reg.csr, "PVDO"); + state->u.f4.fld.csr.brr = cm_object_get_child_by_name(state->u.f4.reg.csr, "BRR"); + state->u.f4.fld.csr.ewup = cm_object_get_child_by_name(state->u.f4.reg.csr, "EWUP"); + state->u.f4.fld.csr.bre = cm_object_get_child_by_name(state->u.f4.reg.csr, "BRE"); + state->u.f4.fld.csr.vosrdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "VOSRDY"); + state->u.f4.fld.csr.odrdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "ODRDY"); + state->u.f4.fld.csr.odswrdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "ODSWRDY"); + state->u.f4.fld.csr.udrdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "UDRDY"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_pwr_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_pwr_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_pwr_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_pwr_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32PWRState *state = STM32_PWR_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_pwr_is_enabled(Object *obj) +{ + STM32PWRState *state = STM32_PWR_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_pwr_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32PWRState *state = STM32_PWR_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_pwr_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_PWR)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32PWRState *state = STM32_PWR_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "PWR"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_pwr_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_pwr_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_pwr_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_pwr_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_pwr_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/PWREN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_pwr_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_PWR); +} + +static void stm32_pwr_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_pwr_reset_callback; + dc->realize = stm32_pwr_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_pwr_is_enabled; +} + +static const TypeInfo stm32_pwr_type_info = { + .name = TYPE_STM32_PWR, + .parent = TYPE_STM32_PWR_PARENT, + .instance_init = stm32_pwr_instance_init_callback, + .instance_size = sizeof(STM32PWRState), + .class_init = stm32_pwr_class_init_callback, + .class_size = sizeof(STM32PWRClass) }; + +static void stm32_pwr_register_types(void) +{ + type_register_static(&stm32_pwr_type_info); +} + +type_init(stm32_pwr_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/pwr.h b/gnu-mcu-eclipse/devices/support/STM32F429x/pwr.h new file mode 100644 index 0000000000..52066ef782 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/pwr.h @@ -0,0 +1,134 @@ +/* + * STM32 - PWR (Power control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_PWR_H_ +#define STM32_PWR_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_PWR DEVICE_PATH_STM32 "PWR" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_PWR TYPE_STM32_PREFIX "pwr" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_PWR_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32PWRParentClass; +typedef PeripheralState STM32PWRParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_PWR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32PWRClass, (obj), TYPE_STM32_PWR) +#define STM32_PWR_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32PWRClass, (klass), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentClass parent_class; + // public: + + // None, so far. +} STM32PWRClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_PWR_STATE(obj) \ + OBJECT_CHECK(STM32PWRState, (obj), TYPE_STM32_PWR) + +typedef struct { + // private: + STM32PWRParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 PWR (Power control) registers. + struct { + Object *cr; // 0x0 (Power control register) + Object *csr; // 0x4 (Power control/status register) + } reg; + + struct { + + // CR (Power control register) bitfields. + struct { + Object *lpds; // [0:0] Low-power deep sleep + Object *pdds; // [1:1] Power down deepsleep + Object *cwuf; // [2:2] Clear wakeup flag + Object *csbf; // [3:3] Clear standby flag + Object *pvde; // [4:4] Power voltage detector enable + Object *pls; // [5:7] PVD level selection + Object *dbp; // [8:8] Disable backup domain write protection + Object *fpds; // [9:9] Flash power down in Stop mode + Object *lpuds; // [10:10] Low-Power Regulator Low Voltage in deepsleep + Object *mruds; // [11:11] Main regulator low voltage in deepsleep mode + Object *adcdc1; // [13:13] ADCDC1 + Object *vos; // [14:15] Regulator voltage scaling output selection + Object *oden; // [16:16] Over-drive enable + Object *odswen; // [17:17] Over-drive switching enabled + Object *uden; // [18:19] Under-drive enable in stop mode + } cr; + + // CSR (Power control/status register) bitfields. + struct { + Object *wuf; // [0:0] Wakeup flag + Object *sbf; // [1:1] Standby flag + Object *pvdo; // [2:2] PVD output + Object *brr; // [3:3] Backup regulator ready + Object *ewup; // [8:8] Enable WKUP pin + Object *bre; // [9:9] Backup regulator enable + Object *vosrdy; // [14:14] Regulator voltage scaling output selection ready bit + Object *odrdy; // [16:16] Over-drive mode ready + Object *odswrdy; // [17:17] Over-drive mode switching ready + Object *udrdy; // [18:19] Under-drive ready flag + } csr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32PWRState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_PWR_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/rcc.c b/gnu-mcu-eclipse/devices/support/STM32F429x/rcc.c new file mode 100644 index 0000000000..dc1d89451c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/rcc.c @@ -0,0 +1,597 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_rcc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.pllcfgr = cm_object_get_child_by_name(obj, "PLLCFGR"); + state->u.f4.reg.cfgr = cm_object_get_child_by_name(obj, "CFGR"); + state->u.f4.reg.cir = cm_object_get_child_by_name(obj, "CIR"); + state->u.f4.reg.ahb1rstr = cm_object_get_child_by_name(obj, "AHB1RSTR"); + state->u.f4.reg.ahb2rstr = cm_object_get_child_by_name(obj, "AHB2RSTR"); + state->u.f4.reg.ahb3rstr = cm_object_get_child_by_name(obj, "AHB3RSTR"); + state->u.f4.reg.apb1rstr = cm_object_get_child_by_name(obj, "APB1RSTR"); + state->u.f4.reg.apb2rstr = cm_object_get_child_by_name(obj, "APB2RSTR"); + state->u.f4.reg.ahb1enr = cm_object_get_child_by_name(obj, "AHB1ENR"); + state->u.f4.reg.ahb2enr = cm_object_get_child_by_name(obj, "AHB2ENR"); + state->u.f4.reg.ahb3enr = cm_object_get_child_by_name(obj, "AHB3ENR"); + state->u.f4.reg.apb1enr = cm_object_get_child_by_name(obj, "APB1ENR"); + state->u.f4.reg.apb2enr = cm_object_get_child_by_name(obj, "APB2ENR"); + state->u.f4.reg.ahb1lpenr = cm_object_get_child_by_name(obj, "AHB1LPENR"); + state->u.f4.reg.ahb2lpenr = cm_object_get_child_by_name(obj, "AHB2LPENR"); + state->u.f4.reg.ahb3lpenr = cm_object_get_child_by_name(obj, "AHB3LPENR"); + state->u.f4.reg.apb1lpenr = cm_object_get_child_by_name(obj, "APB1LPENR"); + state->u.f4.reg.apb2lpenr = cm_object_get_child_by_name(obj, "APB2LPENR"); + state->u.f4.reg.bdcr = cm_object_get_child_by_name(obj, "BDCR"); + state->u.f4.reg.csr = cm_object_get_child_by_name(obj, "CSR"); + state->u.f4.reg.sscgr = cm_object_get_child_by_name(obj, "SSCGR"); + state->u.f4.reg.plli2scfgr = cm_object_get_child_by_name(obj, "PLLI2SCFGR"); + state->u.f4.reg.pllsaicfgr = cm_object_get_child_by_name(obj, "PLLSAICFGR"); + state->u.f4.reg.dckcfgr = cm_object_get_child_by_name(obj, "DCKCFGR"); + + + // CR bitfields. + state->u.f4.fld.cr.hsion = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSION"); + state->u.f4.fld.cr.hsirdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSIRDY"); + state->u.f4.fld.cr.hsitrim = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSITRIM"); + state->u.f4.fld.cr.hsical = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSICAL"); + state->u.f4.fld.cr.hseon = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSEON"); + state->u.f4.fld.cr.hserdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSERDY"); + state->u.f4.fld.cr.hsebyp = cm_object_get_child_by_name(state->u.f4.reg.cr, "HSEBYP"); + state->u.f4.fld.cr.csson = cm_object_get_child_by_name(state->u.f4.reg.cr, "CSSON"); + state->u.f4.fld.cr.pllon = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLON"); + state->u.f4.fld.cr.pllrdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLRDY"); + state->u.f4.fld.cr.plli2son = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLI2SON"); + state->u.f4.fld.cr.plli2srdy = cm_object_get_child_by_name(state->u.f4.reg.cr, "PLLI2SRDY"); + + // PLLCFGR bitfields. + state->u.f4.fld.pllcfgr.pllm = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLM"); + state->u.f4.fld.pllcfgr.plln = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLN"); + state->u.f4.fld.pllcfgr.pllp = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLP"); + state->u.f4.fld.pllcfgr.pllsrc = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLSRC"); + state->u.f4.fld.pllcfgr.pllq = cm_object_get_child_by_name(state->u.f4.reg.pllcfgr, "PLLQ"); + + // CFGR bitfields. + state->u.f4.fld.cfgr.sw = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "SW"); + state->u.f4.fld.cfgr.sws = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "SWS"); + state->u.f4.fld.cfgr.hpre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "HPRE"); + state->u.f4.fld.cfgr.ppre1 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "PPRE1"); + state->u.f4.fld.cfgr.ppre2 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "PPRE2"); + state->u.f4.fld.cfgr.rtcpre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "RTCPRE"); + state->u.f4.fld.cfgr.mco1 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO1"); + state->u.f4.fld.cfgr.i2ssrc = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "I2SSRC"); + state->u.f4.fld.cfgr.mco1pre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO1PRE"); + state->u.f4.fld.cfgr.mco2pre = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO2PRE"); + state->u.f4.fld.cfgr.mco2 = cm_object_get_child_by_name(state->u.f4.reg.cfgr, "MCO2"); + + // CIR bitfields. + state->u.f4.fld.cir.lsirdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYF"); + state->u.f4.fld.cir.lserdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYF"); + state->u.f4.fld.cir.hsirdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYF"); + state->u.f4.fld.cir.hserdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYF"); + state->u.f4.fld.cir.pllrdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYF"); + state->u.f4.fld.cir.plli2srdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYF"); + state->u.f4.fld.cir.pllsairdyf = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLSAIRDYF"); + state->u.f4.fld.cir.cssf = cm_object_get_child_by_name(state->u.f4.reg.cir, "CSSF"); + state->u.f4.fld.cir.lsirdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYIE"); + state->u.f4.fld.cir.lserdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYIE"); + state->u.f4.fld.cir.hsirdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYIE"); + state->u.f4.fld.cir.hserdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYIE"); + state->u.f4.fld.cir.pllrdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYIE"); + state->u.f4.fld.cir.plli2srdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYIE"); + state->u.f4.fld.cir.pllsairdyie = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLSAIRDYIE"); + state->u.f4.fld.cir.lsirdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSIRDYC"); + state->u.f4.fld.cir.lserdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "LSERDYC"); + state->u.f4.fld.cir.hsirdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSIRDYC"); + state->u.f4.fld.cir.hserdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "HSERDYC"); + state->u.f4.fld.cir.pllrdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLRDYC"); + state->u.f4.fld.cir.plli2srdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLI2SRDYC"); + state->u.f4.fld.cir.pllsairdyc = cm_object_get_child_by_name(state->u.f4.reg.cir, "PLLSAIRDYC"); + state->u.f4.fld.cir.cssc = cm_object_get_child_by_name(state->u.f4.reg.cir, "CSSC"); + + // AHB1RSTR bitfields. + state->u.f4.fld.ahb1rstr.gpioarst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOARST"); + state->u.f4.fld.ahb1rstr.gpiobrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOBRST"); + state->u.f4.fld.ahb1rstr.gpiocrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOCRST"); + state->u.f4.fld.ahb1rstr.gpiodrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIODRST"); + state->u.f4.fld.ahb1rstr.gpioerst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOERST"); + state->u.f4.fld.ahb1rstr.gpiofrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOFRST"); + state->u.f4.fld.ahb1rstr.gpiogrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOGRST"); + state->u.f4.fld.ahb1rstr.gpiohrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOHRST"); + state->u.f4.fld.ahb1rstr.gpioirst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOIRST"); + state->u.f4.fld.ahb1rstr.gpiojrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOJRST"); + state->u.f4.fld.ahb1rstr.gpiokrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "GPIOKRST"); + state->u.f4.fld.ahb1rstr.crcrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "CRCRST"); + state->u.f4.fld.ahb1rstr.dma1rst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "DMA1RST"); + state->u.f4.fld.ahb1rstr.dma2rst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "DMA2RST"); + state->u.f4.fld.ahb1rstr.dma2drst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "DMA2DRST"); + state->u.f4.fld.ahb1rstr.ethmacrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "ETHMACRST"); + state->u.f4.fld.ahb1rstr.otghsrst = cm_object_get_child_by_name(state->u.f4.reg.ahb1rstr, "OTGHSRST"); + + // AHB2RSTR bitfields. + state->u.f4.fld.ahb2rstr.dcmirst = cm_object_get_child_by_name(state->u.f4.reg.ahb2rstr, "DCMIRST"); + state->u.f4.fld.ahb2rstr.rngrst = cm_object_get_child_by_name(state->u.f4.reg.ahb2rstr, "RNGRST"); + state->u.f4.fld.ahb2rstr.otgfsrst = cm_object_get_child_by_name(state->u.f4.reg.ahb2rstr, "OTGFSRST"); + + // AHB3RSTR bitfields. + state->u.f4.fld.ahb3rstr.fmcrst = cm_object_get_child_by_name(state->u.f4.reg.ahb3rstr, "FMCRST"); + + // APB1RSTR bitfields. + state->u.f4.fld.apb1rstr.tim2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM2RST"); + state->u.f4.fld.apb1rstr.tim3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM3RST"); + state->u.f4.fld.apb1rstr.tim4rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM4RST"); + state->u.f4.fld.apb1rstr.tim5rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM5RST"); + state->u.f4.fld.apb1rstr.tim6rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM6RST"); + state->u.f4.fld.apb1rstr.tim7rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM7RST"); + state->u.f4.fld.apb1rstr.tim12rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM12RST"); + state->u.f4.fld.apb1rstr.tim13rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM13RST"); + state->u.f4.fld.apb1rstr.tim14rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "TIM14RST"); + state->u.f4.fld.apb1rstr.wwdgrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "WWDGRST"); + state->u.f4.fld.apb1rstr.spi2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "SPI2RST"); + state->u.f4.fld.apb1rstr.spi3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "SPI3RST"); + state->u.f4.fld.apb1rstr.uart2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART2RST"); + state->u.f4.fld.apb1rstr.uart3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART3RST"); + state->u.f4.fld.apb1rstr.uart4rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART4RST"); + state->u.f4.fld.apb1rstr.uart5rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART5RST"); + state->u.f4.fld.apb1rstr.i2c1rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C1RST"); + state->u.f4.fld.apb1rstr.i2c2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C2RST"); + state->u.f4.fld.apb1rstr.i2c3rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "I2C3RST"); + state->u.f4.fld.apb1rstr.can1rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "CAN1RST"); + state->u.f4.fld.apb1rstr.can2rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "CAN2RST"); + state->u.f4.fld.apb1rstr.pwrrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "PWRRST"); + state->u.f4.fld.apb1rstr.dacrst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "DACRST"); + state->u.f4.fld.apb1rstr.uart7rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART7RST"); + state->u.f4.fld.apb1rstr.uart8rst = cm_object_get_child_by_name(state->u.f4.reg.apb1rstr, "UART8RST"); + + // APB2RSTR bitfields. + state->u.f4.fld.apb2rstr.tim1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM1RST"); + state->u.f4.fld.apb2rstr.tim8rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM8RST"); + state->u.f4.fld.apb2rstr.usart1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "USART1RST"); + state->u.f4.fld.apb2rstr.usart6rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "USART6RST"); + state->u.f4.fld.apb2rstr.adcrst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "ADCRST"); + state->u.f4.fld.apb2rstr.sdiorst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SDIORST"); + state->u.f4.fld.apb2rstr.spi1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SPI1RST"); + state->u.f4.fld.apb2rstr.spi4rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SPI4RST"); + state->u.f4.fld.apb2rstr.syscfgrst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SYSCFGRST"); + state->u.f4.fld.apb2rstr.tim9rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM9RST"); + state->u.f4.fld.apb2rstr.tim10rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM10RST"); + state->u.f4.fld.apb2rstr.tim11rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "TIM11RST"); + state->u.f4.fld.apb2rstr.spi5rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SPI5RST"); + state->u.f4.fld.apb2rstr.spi6rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SPI6RST"); + state->u.f4.fld.apb2rstr.sai1rst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "SAI1RST"); + state->u.f4.fld.apb2rstr.ltdcrst = cm_object_get_child_by_name(state->u.f4.reg.apb2rstr, "LTDCRST"); + + // AHB1ENR bitfields. + state->u.f4.fld.ahb1enr.gpioaen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOAEN"); + state->u.f4.fld.ahb1enr.gpioben = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOBEN"); + state->u.f4.fld.ahb1enr.gpiocen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOCEN"); + state->u.f4.fld.ahb1enr.gpioden = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIODEN"); + state->u.f4.fld.ahb1enr.gpioeen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOEEN"); + state->u.f4.fld.ahb1enr.gpiofen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOFEN"); + state->u.f4.fld.ahb1enr.gpiogen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOGEN"); + state->u.f4.fld.ahb1enr.gpiohen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOHEN"); + state->u.f4.fld.ahb1enr.gpioien = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOIEN"); + state->u.f4.fld.ahb1enr.gpiojen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOJEN"); + state->u.f4.fld.ahb1enr.gpioken = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "GPIOKEN"); + state->u.f4.fld.ahb1enr.crcen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "CRCEN"); + state->u.f4.fld.ahb1enr.bkpsramen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "BKPSRAMEN"); + state->u.f4.fld.ahb1enr.ccmdataramen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "CCMDATARAMEN"); + state->u.f4.fld.ahb1enr.dma1en = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "DMA1EN"); + state->u.f4.fld.ahb1enr.dma2en = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "DMA2EN"); + state->u.f4.fld.ahb1enr.dma2den = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "DMA2DEN"); + state->u.f4.fld.ahb1enr.ethmacen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACEN"); + state->u.f4.fld.ahb1enr.ethmactxen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACTXEN"); + state->u.f4.fld.ahb1enr.ethmacrxen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACRXEN"); + state->u.f4.fld.ahb1enr.ethmacptpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "ETHMACPTPEN"); + state->u.f4.fld.ahb1enr.otghsen = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "OTGHSEN"); + state->u.f4.fld.ahb1enr.otghsulpien = cm_object_get_child_by_name(state->u.f4.reg.ahb1enr, "OTGHSULPIEN"); + + // AHB2ENR bitfields. + state->u.f4.fld.ahb2enr.dcmien = cm_object_get_child_by_name(state->u.f4.reg.ahb2enr, "DCMIEN"); + state->u.f4.fld.ahb2enr.rngen = cm_object_get_child_by_name(state->u.f4.reg.ahb2enr, "RNGEN"); + state->u.f4.fld.ahb2enr.otgfsen = cm_object_get_child_by_name(state->u.f4.reg.ahb2enr, "OTGFSEN"); + + // AHB3ENR bitfields. + state->u.f4.fld.ahb3enr.fmcen = cm_object_get_child_by_name(state->u.f4.reg.ahb3enr, "FMCEN"); + + // APB1ENR bitfields. + state->u.f4.fld.apb1enr.tim2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM2EN"); + state->u.f4.fld.apb1enr.tim3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM3EN"); + state->u.f4.fld.apb1enr.tim4en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM4EN"); + state->u.f4.fld.apb1enr.tim5en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM5EN"); + state->u.f4.fld.apb1enr.tim6en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM6EN"); + state->u.f4.fld.apb1enr.tim7en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM7EN"); + state->u.f4.fld.apb1enr.tim12en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM12EN"); + state->u.f4.fld.apb1enr.tim13en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM13EN"); + state->u.f4.fld.apb1enr.tim14en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "TIM14EN"); + state->u.f4.fld.apb1enr.wwdgen = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "WWDGEN"); + state->u.f4.fld.apb1enr.spi2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "SPI2EN"); + state->u.f4.fld.apb1enr.spi3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "SPI3EN"); + state->u.f4.fld.apb1enr.usart2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "USART2EN"); + state->u.f4.fld.apb1enr.usart3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "USART3EN"); + state->u.f4.fld.apb1enr.uart4en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "UART4EN"); + state->u.f4.fld.apb1enr.uart5en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "UART5EN"); + state->u.f4.fld.apb1enr.i2c1en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C1EN"); + state->u.f4.fld.apb1enr.i2c2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C2EN"); + state->u.f4.fld.apb1enr.i2c3en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "I2C3EN"); + state->u.f4.fld.apb1enr.can1en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "CAN1EN"); + state->u.f4.fld.apb1enr.can2en = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "CAN2EN"); + state->u.f4.fld.apb1enr.pwren = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "PWREN"); + state->u.f4.fld.apb1enr.dacen = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "DACEN"); + state->u.f4.fld.apb1enr.uart7enr = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "UART7ENR"); + state->u.f4.fld.apb1enr.uart8enr = cm_object_get_child_by_name(state->u.f4.reg.apb1enr, "UART8ENR"); + + // APB2ENR bitfields. + state->u.f4.fld.apb2enr.tim1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM1EN"); + state->u.f4.fld.apb2enr.tim8en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM8EN"); + state->u.f4.fld.apb2enr.usart1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "USART1EN"); + state->u.f4.fld.apb2enr.usart6en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "USART6EN"); + state->u.f4.fld.apb2enr.adc1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "ADC1EN"); + state->u.f4.fld.apb2enr.adc2en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "ADC2EN"); + state->u.f4.fld.apb2enr.adc3en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "ADC3EN"); + state->u.f4.fld.apb2enr.sdioen = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SDIOEN"); + state->u.f4.fld.apb2enr.spi1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SPI1EN"); + state->u.f4.fld.apb2enr.spi4enr = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SPI4ENR"); + state->u.f4.fld.apb2enr.syscfgen = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SYSCFGEN"); + state->u.f4.fld.apb2enr.tim9en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM9EN"); + state->u.f4.fld.apb2enr.tim10en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM10EN"); + state->u.f4.fld.apb2enr.tim11en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "TIM11EN"); + state->u.f4.fld.apb2enr.spi5enr = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SPI5ENR"); + state->u.f4.fld.apb2enr.spi6enr = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SPI6ENR"); + state->u.f4.fld.apb2enr.sai1en = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "SAI1EN"); + state->u.f4.fld.apb2enr.ltdcen = cm_object_get_child_by_name(state->u.f4.reg.apb2enr, "LTDCEN"); + + // AHB1LPENR bitfields. + state->u.f4.fld.ahb1lpenr.gpioalpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOALPEN"); + state->u.f4.fld.ahb1lpenr.gpioblpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOBLPEN"); + state->u.f4.fld.ahb1lpenr.gpioclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOCLPEN"); + state->u.f4.fld.ahb1lpenr.gpiodlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIODLPEN"); + state->u.f4.fld.ahb1lpenr.gpioelpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOELPEN"); + state->u.f4.fld.ahb1lpenr.gpioflpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOFLPEN"); + state->u.f4.fld.ahb1lpenr.gpioglpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOGLPEN"); + state->u.f4.fld.ahb1lpenr.gpiohlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOHLPEN"); + state->u.f4.fld.ahb1lpenr.gpioilpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOILPEN"); + state->u.f4.fld.ahb1lpenr.gpiojlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOJLPEN"); + state->u.f4.fld.ahb1lpenr.gpioklpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "GPIOKLPEN"); + state->u.f4.fld.ahb1lpenr.crclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "CRCLPEN"); + state->u.f4.fld.ahb1lpenr.flitflpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "FLITFLPEN"); + state->u.f4.fld.ahb1lpenr.sram1lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "SRAM1LPEN"); + state->u.f4.fld.ahb1lpenr.sram2lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "SRAM2LPEN"); + state->u.f4.fld.ahb1lpenr.bkpsramlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "BKPSRAMLPEN"); + state->u.f4.fld.ahb1lpenr.sram3lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "SRAM3LPEN"); + state->u.f4.fld.ahb1lpenr.dma1lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "DMA1LPEN"); + state->u.f4.fld.ahb1lpenr.dma2lpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "DMA2LPEN"); + state->u.f4.fld.ahb1lpenr.dma2dlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "DMA2DLPEN"); + state->u.f4.fld.ahb1lpenr.ethmaclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACLPEN"); + state->u.f4.fld.ahb1lpenr.ethmactxlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACTXLPEN"); + state->u.f4.fld.ahb1lpenr.ethmacrxlpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACRXLPEN"); + state->u.f4.fld.ahb1lpenr.ethmacptplpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "ETHMACPTPLPEN"); + state->u.f4.fld.ahb1lpenr.otghslpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "OTGHSLPEN"); + state->u.f4.fld.ahb1lpenr.otghsulpilpen = cm_object_get_child_by_name(state->u.f4.reg.ahb1lpenr, "OTGHSULPILPEN"); + + // AHB2LPENR bitfields. + state->u.f4.fld.ahb2lpenr.dcmilpen = cm_object_get_child_by_name(state->u.f4.reg.ahb2lpenr, "DCMILPEN"); + state->u.f4.fld.ahb2lpenr.rnglpen = cm_object_get_child_by_name(state->u.f4.reg.ahb2lpenr, "RNGLPEN"); + state->u.f4.fld.ahb2lpenr.otgfslpen = cm_object_get_child_by_name(state->u.f4.reg.ahb2lpenr, "OTGFSLPEN"); + + // AHB3LPENR bitfields. + state->u.f4.fld.ahb3lpenr.fmclpen = cm_object_get_child_by_name(state->u.f4.reg.ahb3lpenr, "FMCLPEN"); + + // APB1LPENR bitfields. + state->u.f4.fld.apb1lpenr.tim2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM2LPEN"); + state->u.f4.fld.apb1lpenr.tim3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM3LPEN"); + state->u.f4.fld.apb1lpenr.tim4lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM4LPEN"); + state->u.f4.fld.apb1lpenr.tim5lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM5LPEN"); + state->u.f4.fld.apb1lpenr.tim6lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM6LPEN"); + state->u.f4.fld.apb1lpenr.tim7lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM7LPEN"); + state->u.f4.fld.apb1lpenr.tim12lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM12LPEN"); + state->u.f4.fld.apb1lpenr.tim13lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM13LPEN"); + state->u.f4.fld.apb1lpenr.tim14lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "TIM14LPEN"); + state->u.f4.fld.apb1lpenr.wwdglpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "WWDGLPEN"); + state->u.f4.fld.apb1lpenr.spi2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "SPI2LPEN"); + state->u.f4.fld.apb1lpenr.spi3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "SPI3LPEN"); + state->u.f4.fld.apb1lpenr.usart2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "USART2LPEN"); + state->u.f4.fld.apb1lpenr.usart3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "USART3LPEN"); + state->u.f4.fld.apb1lpenr.uart4lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "UART4LPEN"); + state->u.f4.fld.apb1lpenr.uart5lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "UART5LPEN"); + state->u.f4.fld.apb1lpenr.i2c1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C1LPEN"); + state->u.f4.fld.apb1lpenr.i2c2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C2LPEN"); + state->u.f4.fld.apb1lpenr.i2c3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "I2C3LPEN"); + state->u.f4.fld.apb1lpenr.can1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "CAN1LPEN"); + state->u.f4.fld.apb1lpenr.can2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "CAN2LPEN"); + state->u.f4.fld.apb1lpenr.pwrlpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "PWRLPEN"); + state->u.f4.fld.apb1lpenr.daclpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "DACLPEN"); + state->u.f4.fld.apb1lpenr.uart7lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "UART7LPEN"); + state->u.f4.fld.apb1lpenr.uart8lpen = cm_object_get_child_by_name(state->u.f4.reg.apb1lpenr, "UART8LPEN"); + + // APB2LPENR bitfields. + state->u.f4.fld.apb2lpenr.tim1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM1LPEN"); + state->u.f4.fld.apb2lpenr.tim8lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM8LPEN"); + state->u.f4.fld.apb2lpenr.usart1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "USART1LPEN"); + state->u.f4.fld.apb2lpenr.usart6lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "USART6LPEN"); + state->u.f4.fld.apb2lpenr.adc1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "ADC1LPEN"); + state->u.f4.fld.apb2lpenr.adc2lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "ADC2LPEN"); + state->u.f4.fld.apb2lpenr.adc3lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "ADC3LPEN"); + state->u.f4.fld.apb2lpenr.sdiolpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SDIOLPEN"); + state->u.f4.fld.apb2lpenr.spi1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SPI1LPEN"); + state->u.f4.fld.apb2lpenr.spi4lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SPI4LPEN"); + state->u.f4.fld.apb2lpenr.syscfglpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SYSCFGLPEN"); + state->u.f4.fld.apb2lpenr.tim9lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM9LPEN"); + state->u.f4.fld.apb2lpenr.tim10lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM10LPEN"); + state->u.f4.fld.apb2lpenr.tim11lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "TIM11LPEN"); + state->u.f4.fld.apb2lpenr.spi5lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SPI5LPEN"); + state->u.f4.fld.apb2lpenr.spi6lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SPI6LPEN"); + state->u.f4.fld.apb2lpenr.sai1lpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "SAI1LPEN"); + state->u.f4.fld.apb2lpenr.ltdclpen = cm_object_get_child_by_name(state->u.f4.reg.apb2lpenr, "LTDCLPEN"); + + // BDCR bitfields. + state->u.f4.fld.bdcr.lseon = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSEON"); + state->u.f4.fld.bdcr.lserdy = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSERDY"); + state->u.f4.fld.bdcr.lsebyp = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "LSEBYP"); + state->u.f4.fld.bdcr.rtcsel = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "RTCSEL"); + state->u.f4.fld.bdcr.rtcen = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "RTCEN"); + state->u.f4.fld.bdcr.bdrst = cm_object_get_child_by_name(state->u.f4.reg.bdcr, "BDRST"); + + // CSR bitfields. + state->u.f4.fld.csr.lsion = cm_object_get_child_by_name(state->u.f4.reg.csr, "LSION"); + state->u.f4.fld.csr.lsirdy = cm_object_get_child_by_name(state->u.f4.reg.csr, "LSIRDY"); + state->u.f4.fld.csr.rmvf = cm_object_get_child_by_name(state->u.f4.reg.csr, "RMVF"); + state->u.f4.fld.csr.borrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "BORRSTF"); + state->u.f4.fld.csr.padrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "PADRSTF"); + state->u.f4.fld.csr.porrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "PORRSTF"); + state->u.f4.fld.csr.sftrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "SFTRSTF"); + state->u.f4.fld.csr.wdgrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WDGRSTF"); + state->u.f4.fld.csr.wwdgrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "WWDGRSTF"); + state->u.f4.fld.csr.lpwrrstf = cm_object_get_child_by_name(state->u.f4.reg.csr, "LPWRRSTF"); + + // SSCGR bitfields. + state->u.f4.fld.sscgr.modper = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "MODPER"); + state->u.f4.fld.sscgr.incstep = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "INCSTEP"); + state->u.f4.fld.sscgr.spreadsel = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "SPREADSEL"); + state->u.f4.fld.sscgr.sscgen = cm_object_get_child_by_name(state->u.f4.reg.sscgr, "SSCGEN"); + + // PLLI2SCFGR bitfields. + state->u.f4.fld.plli2scfgr.plli2sn = cm_object_get_child_by_name(state->u.f4.reg.plli2scfgr, "PLLI2SN"); + state->u.f4.fld.plli2scfgr.plli2sq = cm_object_get_child_by_name(state->u.f4.reg.plli2scfgr, "PLLI2SQ"); + state->u.f4.fld.plli2scfgr.plli2sr = cm_object_get_child_by_name(state->u.f4.reg.plli2scfgr, "PLLI2SR"); + + // PLLSAICFGR bitfields. + state->u.f4.fld.pllsaicfgr.pllsain = cm_object_get_child_by_name(state->u.f4.reg.pllsaicfgr, "PLLSAIN"); + state->u.f4.fld.pllsaicfgr.pllsaiq = cm_object_get_child_by_name(state->u.f4.reg.pllsaicfgr, "PLLSAIQ"); + state->u.f4.fld.pllsaicfgr.pllsair = cm_object_get_child_by_name(state->u.f4.reg.pllsaicfgr, "PLLSAIR"); + + // DCKCFGR bitfields. + state->u.f4.fld.dckcfgr.plli2sdivq = cm_object_get_child_by_name(state->u.f4.reg.dckcfgr, "PLLI2SDIVQ"); + state->u.f4.fld.dckcfgr.pllsaidivq = cm_object_get_child_by_name(state->u.f4.reg.dckcfgr, "PLLSAIDIVQ"); + state->u.f4.fld.dckcfgr.pllsaidivr = cm_object_get_child_by_name(state->u.f4.reg.dckcfgr, "PLLSAIDIVR"); + state->u.f4.fld.dckcfgr.sai1asrc = cm_object_get_child_by_name(state->u.f4.reg.dckcfgr, "SAI1ASRC"); + state->u.f4.fld.dckcfgr.sai1bsrc = cm_object_get_child_by_name(state->u.f4.reg.dckcfgr, "SAI1BSRC"); + state->u.f4.fld.dckcfgr.timpre = cm_object_get_child_by_name(state->u.f4.reg.dckcfgr, "TIMPRE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rcc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rcc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rcc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rcc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RCCState *state = STM32_RCC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rcc_is_enabled(Object *obj) +{ + STM32RCCState *state = STM32_RCC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rcc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RCCState *state = STM32_RCC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rcc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RCC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RCCState *state = STM32_RCC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RCC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_rcc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rcc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rcc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rcc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rcc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RCCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rcc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RCC); +} + +static void stm32_rcc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rcc_reset_callback; + dc->realize = stm32_rcc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rcc_is_enabled; +} + +static const TypeInfo stm32_rcc_type_info = { + .name = TYPE_STM32_RCC, + .parent = TYPE_STM32_RCC_PARENT, + .instance_init = stm32_rcc_instance_init_callback, + .instance_size = sizeof(STM32RCCState), + .class_init = stm32_rcc_class_init_callback, + .class_size = sizeof(STM32RCCClass) }; + +static void stm32_rcc_register_types(void) +{ + type_register_static(&stm32_rcc_type_info); +} + +type_init(stm32_rcc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/rcc.h b/gnu-mcu-eclipse/devices/support/STM32F429x/rcc.h new file mode 100644 index 0000000000..ae99386f2b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/rcc.h @@ -0,0 +1,512 @@ +/* + * STM32 - RCC (Reset and clock control) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RCC_H_ +#define STM32_RCC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RCC DEVICE_PATH_STM32 "RCC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RCC TYPE_STM32_PREFIX "rcc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RCC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RCCParentClass; +typedef PeripheralState STM32RCCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RCCClass, (obj), TYPE_STM32_RCC) +#define STM32_RCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RCCClass, (klass), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentClass parent_class; + // public: + + // None, so far. +} STM32RCCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RCC_STATE(obj) \ + OBJECT_CHECK(STM32RCCState, (obj), TYPE_STM32_RCC) + +typedef struct { + // private: + STM32RCCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RCC (Reset and clock control) registers. + struct { + Object *cr; // 0x0 (Clock control register) + Object *pllcfgr; // 0x4 (PLL configuration register) + Object *cfgr; // 0x8 (Clock configuration register) + Object *cir; // 0xC (Clock interrupt register) + Object *ahb1rstr; // 0x10 (AHB1 peripheral reset register) + Object *ahb2rstr; // 0x14 (AHB2 peripheral reset register) + Object *ahb3rstr; // 0x18 (AHB3 peripheral reset register) + Object *apb1rstr; // 0x20 (APB1 peripheral reset register) + Object *apb2rstr; // 0x24 (APB2 peripheral reset register) + Object *ahb1enr; // 0x30 (AHB1 peripheral clock register) + Object *ahb2enr; // 0x34 (AHB2 peripheral clock enable register) + Object *ahb3enr; // 0x38 (AHB3 peripheral clock enable register) + Object *apb1enr; // 0x40 (APB1 peripheral clock enable register) + Object *apb2enr; // 0x44 (APB2 peripheral clock enable register) + Object *ahb1lpenr; // 0x50 (AHB1 peripheral clock enable in low power mode register) + Object *ahb2lpenr; // 0x54 (AHB2 peripheral clock enable in low power mode register) + Object *ahb3lpenr; // 0x58 (AHB3 peripheral clock enable in low power mode register) + Object *apb1lpenr; // 0x60 (APB1 peripheral clock enable in low power mode register) + Object *apb2lpenr; // 0x64 (APB2 peripheral clock enabled in low power mode register) + Object *bdcr; // 0x70 (Backup domain control register) + Object *csr; // 0x74 (Clock control & status register) + Object *sscgr; // 0x80 (Spread spectrum clock generation register) + Object *plli2scfgr; // 0x84 (PLLI2S configuration register) + Object *pllsaicfgr; // 0x88 (PLLSAICFGR) + Object *dckcfgr; // 0x8C (DCKCFGR) + } reg; + + struct { + + // CR (Clock control register) bitfields. + struct { + Object *hsion; // [0:0] Internal high-speed clock enable + Object *hsirdy; // [1:1] Internal high-speed clock ready flag + Object *hsitrim; // [3:7] Internal high-speed clock trimming + Object *hsical; // [8:15] Internal high-speed clock calibration + Object *hseon; // [16:16] HSE clock enable + Object *hserdy; // [17:17] HSE clock ready flag + Object *hsebyp; // [18:18] HSE clock bypass + Object *csson; // [19:19] Clock security system enable + Object *pllon; // [24:24] Main PLL (PLL) enable + Object *pllrdy; // [25:25] Main PLL (PLL) clock ready flag + Object *plli2son; // [26:26] PLLI2S enable + Object *plli2srdy; // [27:27] PLLI2S clock ready flag + } cr; + + // PLLCFGR (PLL configuration register) bitfields. + struct { + Object *pllm; // [0:5] Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + Object *plln; // [6:14] Main PLL (PLL) multiplication factor for VCO + Object *pllp; // [16:17] Main PLL (PLL) division factor for main system clock + Object *pllsrc; // [22:22] Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + Object *pllq; // [24:27] Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + } pllcfgr; + + // CFGR (Clock configuration register) bitfields. + struct { + Object *sw; // [0:1] System clock switch + Object *sws; // [2:3] System clock switch status + Object *hpre; // [4:7] AHB prescaler + Object *ppre1; // [10:12] APB Low speed prescaler (APB1) + Object *ppre2; // [13:15] APB high-speed prescaler (APB2) + Object *rtcpre; // [16:20] HSE division factor for RTC clock + Object *mco1; // [21:22] Microcontroller clock output 1 + Object *i2ssrc; // [23:23] I2S clock selection + Object *mco1pre; // [24:26] MCO1 prescaler + Object *mco2pre; // [27:29] MCO2 prescaler + Object *mco2; // [30:31] Microcontroller clock output 2 + } cfgr; + + // CIR (Clock interrupt register) bitfields. + struct { + Object *lsirdyf; // [0:0] LSI ready interrupt flag + Object *lserdyf; // [1:1] LSE ready interrupt flag + Object *hsirdyf; // [2:2] HSI ready interrupt flag + Object *hserdyf; // [3:3] HSE ready interrupt flag + Object *pllrdyf; // [4:4] Main PLL (PLL) ready interrupt flag + Object *plli2srdyf; // [5:5] PLLI2S ready interrupt flag + Object *pllsairdyf; // [6:6] PLLSAI ready interrupt flag + Object *cssf; // [7:7] Clock security system interrupt flag + Object *lsirdyie; // [8:8] LSI ready interrupt enable + Object *lserdyie; // [9:9] LSE ready interrupt enable + Object *hsirdyie; // [10:10] HSI ready interrupt enable + Object *hserdyie; // [11:11] HSE ready interrupt enable + Object *pllrdyie; // [12:12] Main PLL (PLL) ready interrupt enable + Object *plli2srdyie; // [13:13] PLLI2S ready interrupt enable + Object *pllsairdyie; // [14:14] PLLSAI Ready Interrupt Enable + Object *lsirdyc; // [16:16] LSI ready interrupt clear + Object *lserdyc; // [17:17] LSE ready interrupt clear + Object *hsirdyc; // [18:18] HSI ready interrupt clear + Object *hserdyc; // [19:19] HSE ready interrupt clear + Object *pllrdyc; // [20:20] Main PLL(PLL) ready interrupt clear + Object *plli2srdyc; // [21:21] PLLI2S ready interrupt clear + Object *pllsairdyc; // [22:22] PLLSAI Ready Interrupt Clear + Object *cssc; // [23:23] Clock security system interrupt clear + } cir; + + // AHB1RSTR (AHB1 peripheral reset register) bitfields. + struct { + Object *gpioarst; // [0:0] IO port A reset + Object *gpiobrst; // [1:1] IO port B reset + Object *gpiocrst; // [2:2] IO port C reset + Object *gpiodrst; // [3:3] IO port D reset + Object *gpioerst; // [4:4] IO port E reset + Object *gpiofrst; // [5:5] IO port F reset + Object *gpiogrst; // [6:6] IO port G reset + Object *gpiohrst; // [7:7] IO port H reset + Object *gpioirst; // [8:8] IO port I reset + Object *gpiojrst; // [9:9] IO port J reset + Object *gpiokrst; // [10:10] IO port K reset + Object *crcrst; // [12:12] CRC reset + Object *dma1rst; // [21:21] DMA2 reset + Object *dma2rst; // [22:22] DMA2 reset + Object *dma2drst; // [23:23] DMA2D reset + Object *ethmacrst; // [25:25] Ethernet MAC reset + Object *otghsrst; // [29:29] USB OTG HS module reset + } ahb1rstr; + + // AHB2RSTR (AHB2 peripheral reset register) bitfields. + struct { + Object *dcmirst; // [0:0] Camera interface reset + Object *rngrst; // [6:6] Random number generator module reset + Object *otgfsrst; // [7:7] USB OTG FS module reset + } ahb2rstr; + + // AHB3RSTR (AHB3 peripheral reset register) bitfields. + struct { + Object *fmcrst; // [0:0] Flexible memory controller module reset + } ahb3rstr; + + // APB1RSTR (APB1 peripheral reset register) bitfields. + struct { + Object *tim2rst; // [0:0] TIM2 reset + Object *tim3rst; // [1:1] TIM3 reset + Object *tim4rst; // [2:2] TIM4 reset + Object *tim5rst; // [3:3] TIM5 reset + Object *tim6rst; // [4:4] TIM6 reset + Object *tim7rst; // [5:5] TIM7 reset + Object *tim12rst; // [6:6] TIM12 reset + Object *tim13rst; // [7:7] TIM13 reset + Object *tim14rst; // [8:8] TIM14 reset + Object *wwdgrst; // [11:11] Window watchdog reset + Object *spi2rst; // [14:14] SPI 2 reset + Object *spi3rst; // [15:15] SPI 3 reset + Object *uart2rst; // [17:17] USART 2 reset + Object *uart3rst; // [18:18] USART 3 reset + Object *uart4rst; // [19:19] USART 4 reset + Object *uart5rst; // [20:20] USART 5 reset + Object *i2c1rst; // [21:21] I2C 1 reset + Object *i2c2rst; // [22:22] I2C 2 reset + Object *i2c3rst; // [23:23] I2C3 reset + Object *can1rst; // [25:25] CAN1 reset + Object *can2rst; // [26:26] CAN2 reset + Object *pwrrst; // [28:28] Power interface reset + Object *dacrst; // [29:29] DAC reset + Object *uart7rst; // [30:30] UART7 reset + Object *uart8rst; // [31:31] UART8 reset + } apb1rstr; + + // APB2RSTR (APB2 peripheral reset register) bitfields. + struct { + Object *tim1rst; // [0:0] TIM1 reset + Object *tim8rst; // [1:1] TIM8 reset + Object *usart1rst; // [4:4] USART1 reset + Object *usart6rst; // [5:5] USART6 reset + Object *adcrst; // [8:8] ADC interface reset (common to all ADCs) + Object *sdiorst; // [11:11] SDIO reset + Object *spi1rst; // [12:12] SPI 1 reset + Object *spi4rst; // [13:13] SPI4 reset + Object *syscfgrst; // [14:14] System configuration controller reset + Object *tim9rst; // [16:16] TIM9 reset + Object *tim10rst; // [17:17] TIM10 reset + Object *tim11rst; // [18:18] TIM11 reset + Object *spi5rst; // [20:20] SPI5 reset + Object *spi6rst; // [21:21] SPI6 reset + Object *sai1rst; // [22:22] SAI1 reset + Object *ltdcrst; // [26:26] LTDC reset + } apb2rstr; + + // AHB1ENR (AHB1 peripheral clock register) bitfields. + struct { + Object *gpioaen; // [0:0] IO port A clock enable + Object *gpioben; // [1:1] IO port B clock enable + Object *gpiocen; // [2:2] IO port C clock enable + Object *gpioden; // [3:3] IO port D clock enable + Object *gpioeen; // [4:4] IO port E clock enable + Object *gpiofen; // [5:5] IO port F clock enable + Object *gpiogen; // [6:6] IO port G clock enable + Object *gpiohen; // [7:7] IO port H clock enable + Object *gpioien; // [8:8] IO port I clock enable + Object *gpiojen; // [9:9] IO port J clock enable + Object *gpioken; // [10:10] IO port K clock enable + Object *crcen; // [12:12] CRC clock enable + Object *bkpsramen; // [18:18] Backup SRAM interface clock enable + Object *ccmdataramen; // [20:20] CCM data RAM clock enable + Object *dma1en; // [21:21] DMA1 clock enable + Object *dma2en; // [22:22] DMA2 clock enable + Object *dma2den; // [23:23] DMA2D clock enable + Object *ethmacen; // [25:25] Ethernet MAC clock enable + Object *ethmactxen; // [26:26] Ethernet Transmission clock enable + Object *ethmacrxen; // [27:27] Ethernet Reception clock enable + Object *ethmacptpen; // [28:28] Ethernet PTP clock enable + Object *otghsen; // [29:29] USB OTG HS clock enable + Object *otghsulpien; // [30:30] USB OTG HSULPI clock enable + } ahb1enr; + + // AHB2ENR (AHB2 peripheral clock enable register) bitfields. + struct { + Object *dcmien; // [0:0] Camera interface enable + Object *rngen; // [6:6] Random number generator clock enable + Object *otgfsen; // [7:7] USB OTG FS clock enable + } ahb2enr; + + // AHB3ENR (AHB3 peripheral clock enable register) bitfields. + struct { + Object *fmcen; // [0:0] Flexible memory controller module clock enable + } ahb3enr; + + // APB1ENR (APB1 peripheral clock enable register) bitfields. + struct { + Object *tim2en; // [0:0] TIM2 clock enable + Object *tim3en; // [1:1] TIM3 clock enable + Object *tim4en; // [2:2] TIM4 clock enable + Object *tim5en; // [3:3] TIM5 clock enable + Object *tim6en; // [4:4] TIM6 clock enable + Object *tim7en; // [5:5] TIM7 clock enable + Object *tim12en; // [6:6] TIM12 clock enable + Object *tim13en; // [7:7] TIM13 clock enable + Object *tim14en; // [8:8] TIM14 clock enable + Object *wwdgen; // [11:11] Window watchdog clock enable + Object *spi2en; // [14:14] SPI2 clock enable + Object *spi3en; // [15:15] SPI3 clock enable + Object *usart2en; // [17:17] USART 2 clock enable + Object *usart3en; // [18:18] USART3 clock enable + Object *uart4en; // [19:19] UART4 clock enable + Object *uart5en; // [20:20] UART5 clock enable + Object *i2c1en; // [21:21] I2C1 clock enable + Object *i2c2en; // [22:22] I2C2 clock enable + Object *i2c3en; // [23:23] I2C3 clock enable + Object *can1en; // [25:25] CAN 1 clock enable + Object *can2en; // [26:26] CAN 2 clock enable + Object *pwren; // [28:28] Power interface clock enable + Object *dacen; // [29:29] DAC interface clock enable + Object *uart7enr; // [30:30] UART7 clock enable + Object *uart8enr; // [31:31] UART8 clock enable + } apb1enr; + + // APB2ENR (APB2 peripheral clock enable register) bitfields. + struct { + Object *tim1en; // [0:0] TIM1 clock enable + Object *tim8en; // [1:1] TIM8 clock enable + Object *usart1en; // [4:4] USART1 clock enable + Object *usart6en; // [5:5] USART6 clock enable + Object *adc1en; // [8:8] ADC1 clock enable + Object *adc2en; // [9:9] ADC2 clock enable + Object *adc3en; // [10:10] ADC3 clock enable + Object *sdioen; // [11:11] SDIO clock enable + Object *spi1en; // [12:12] SPI1 clock enable + Object *spi4enr; // [13:13] SPI4 clock enable + Object *syscfgen; // [14:14] System configuration controller clock enable + Object *tim9en; // [16:16] TIM9 clock enable + Object *tim10en; // [17:17] TIM10 clock enable + Object *tim11en; // [18:18] TIM11 clock enable + Object *spi5enr; // [20:20] SPI5 clock enable + Object *spi6enr; // [21:21] SPI6 clock enable + Object *sai1en; // [22:22] SAI1 clock enable + Object *ltdcen; // [26:26] LTDC clock enable + } apb2enr; + + // AHB1LPENR (AHB1 peripheral clock enable in low power mode register) bitfields. + struct { + Object *gpioalpen; // [0:0] IO port A clock enable during sleep mode + Object *gpioblpen; // [1:1] IO port B clock enable during Sleep mode + Object *gpioclpen; // [2:2] IO port C clock enable during Sleep mode + Object *gpiodlpen; // [3:3] IO port D clock enable during Sleep mode + Object *gpioelpen; // [4:4] IO port E clock enable during Sleep mode + Object *gpioflpen; // [5:5] IO port F clock enable during Sleep mode + Object *gpioglpen; // [6:6] IO port G clock enable during Sleep mode + Object *gpiohlpen; // [7:7] IO port H clock enable during Sleep mode + Object *gpioilpen; // [8:8] IO port I clock enable during Sleep mode + Object *gpiojlpen; // [9:9] IO port J clock enable during Sleep mode + Object *gpioklpen; // [10:10] IO port K clock enable during Sleep mode + Object *crclpen; // [12:12] CRC clock enable during Sleep mode + Object *flitflpen; // [15:15] Flash interface clock enable during Sleep mode + Object *sram1lpen; // [16:16] SRAM 1interface clock enable during Sleep mode + Object *sram2lpen; // [17:17] SRAM 2 interface clock enable during Sleep mode + Object *bkpsramlpen; // [18:18] Backup SRAM interface clock enable during Sleep mode + Object *sram3lpen; // [19:19] SRAM 3 interface clock enable during Sleep mode + Object *dma1lpen; // [21:21] DMA1 clock enable during Sleep mode + Object *dma2lpen; // [22:22] DMA2 clock enable during Sleep mode + Object *dma2dlpen; // [23:23] DMA2D clock enable during Sleep mode + Object *ethmaclpen; // [25:25] Ethernet MAC clock enable during Sleep mode + Object *ethmactxlpen; // [26:26] Ethernet transmission clock enable during Sleep mode + Object *ethmacrxlpen; // [27:27] Ethernet reception clock enable during Sleep mode + Object *ethmacptplpen; // [28:28] Ethernet PTP clock enable during Sleep mode + Object *otghslpen; // [29:29] USB OTG HS clock enable during Sleep mode + Object *otghsulpilpen; // [30:30] USB OTG HS ULPI clock enable during Sleep mode + } ahb1lpenr; + + // AHB2LPENR (AHB2 peripheral clock enable in low power mode register) bitfields. + struct { + Object *dcmilpen; // [0:0] Camera interface enable during Sleep mode + Object *rnglpen; // [6:6] Random number generator clock enable during Sleep mode + Object *otgfslpen; // [7:7] USB OTG FS clock enable during Sleep mode + } ahb2lpenr; + + // AHB3LPENR (AHB3 peripheral clock enable in low power mode register) bitfields. + struct { + Object *fmclpen; // [0:0] Flexible memory controller module clock enable during Sleep mode + } ahb3lpenr; + + // APB1LPENR (APB1 peripheral clock enable in low power mode register) bitfields. + struct { + Object *tim2lpen; // [0:0] TIM2 clock enable during Sleep mode + Object *tim3lpen; // [1:1] TIM3 clock enable during Sleep mode + Object *tim4lpen; // [2:2] TIM4 clock enable during Sleep mode + Object *tim5lpen; // [3:3] TIM5 clock enable during Sleep mode + Object *tim6lpen; // [4:4] TIM6 clock enable during Sleep mode + Object *tim7lpen; // [5:5] TIM7 clock enable during Sleep mode + Object *tim12lpen; // [6:6] TIM12 clock enable during Sleep mode + Object *tim13lpen; // [7:7] TIM13 clock enable during Sleep mode + Object *tim14lpen; // [8:8] TIM14 clock enable during Sleep mode + Object *wwdglpen; // [11:11] Window watchdog clock enable during Sleep mode + Object *spi2lpen; // [14:14] SPI2 clock enable during Sleep mode + Object *spi3lpen; // [15:15] SPI3 clock enable during Sleep mode + Object *usart2lpen; // [17:17] USART2 clock enable during Sleep mode + Object *usart3lpen; // [18:18] USART3 clock enable during Sleep mode + Object *uart4lpen; // [19:19] UART4 clock enable during Sleep mode + Object *uart5lpen; // [20:20] UART5 clock enable during Sleep mode + Object *i2c1lpen; // [21:21] I2C1 clock enable during Sleep mode + Object *i2c2lpen; // [22:22] I2C2 clock enable during Sleep mode + Object *i2c3lpen; // [23:23] I2C3 clock enable during Sleep mode + Object *can1lpen; // [25:25] CAN 1 clock enable during Sleep mode + Object *can2lpen; // [26:26] CAN 2 clock enable during Sleep mode + Object *pwrlpen; // [28:28] Power interface clock enable during Sleep mode + Object *daclpen; // [29:29] DAC interface clock enable during Sleep mode + Object *uart7lpen; // [30:30] UART7 clock enable during Sleep mode + Object *uart8lpen; // [31:31] UART8 clock enable during Sleep mode + } apb1lpenr; + + // APB2LPENR (APB2 peripheral clock enabled in low power mode register) bitfields. + struct { + Object *tim1lpen; // [0:0] TIM1 clock enable during Sleep mode + Object *tim8lpen; // [1:1] TIM8 clock enable during Sleep mode + Object *usart1lpen; // [4:4] USART1 clock enable during Sleep mode + Object *usart6lpen; // [5:5] USART6 clock enable during Sleep mode + Object *adc1lpen; // [8:8] ADC1 clock enable during Sleep mode + Object *adc2lpen; // [9:9] ADC2 clock enable during Sleep mode + Object *adc3lpen; // [10:10] ADC 3 clock enable during Sleep mode + Object *sdiolpen; // [11:11] SDIO clock enable during Sleep mode + Object *spi1lpen; // [12:12] SPI 1 clock enable during Sleep mode + Object *spi4lpen; // [13:13] SPI 4 clock enable during Sleep mode + Object *syscfglpen; // [14:14] System configuration controller clock enable during Sleep mode + Object *tim9lpen; // [16:16] TIM9 clock enable during sleep mode + Object *tim10lpen; // [17:17] TIM10 clock enable during Sleep mode + Object *tim11lpen; // [18:18] TIM11 clock enable during Sleep mode + Object *spi5lpen; // [20:20] SPI 5 clock enable during Sleep mode + Object *spi6lpen; // [21:21] SPI 6 clock enable during Sleep mode + Object *sai1lpen; // [22:22] SAI1 clock enable + Object *ltdclpen; // [26:26] LTDC clock enable + } apb2lpenr; + + // BDCR (Backup domain control register) bitfields. + struct { + Object *lseon; // [0:0] External low-speed oscillator enable + Object *lserdy; // [1:1] External low-speed oscillator ready + Object *lsebyp; // [2:2] External low-speed oscillator bypass + Object *rtcsel; // [8:9] RTC clock source selection + Object *rtcen; // [15:15] RTC clock enable + Object *bdrst; // [16:16] Backup domain software reset + } bdcr; + + // CSR (Clock control & status register) bitfields. + struct { + Object *lsion; // [0:0] Internal low-speed oscillator enable + Object *lsirdy; // [1:1] Internal low-speed oscillator ready + Object *rmvf; // [24:24] Remove reset flag + Object *borrstf; // [25:25] BOR reset flag + Object *padrstf; // [26:26] PIN reset flag + Object *porrstf; // [27:27] POR/PDR reset flag + Object *sftrstf; // [28:28] Software reset flag + Object *wdgrstf; // [29:29] Independent watchdog reset flag + Object *wwdgrstf; // [30:30] Window watchdog reset flag + Object *lpwrrstf; // [31:31] Low-power reset flag + } csr; + + // SSCGR (Spread spectrum clock generation register) bitfields. + struct { + Object *modper; // [0:12] Modulation period + Object *incstep; // [13:27] Incrementation step + Object *spreadsel; // [30:30] Spread Select + Object *sscgen; // [31:31] Spread spectrum modulation enable + } sscgr; + + // PLLI2SCFGR (PLLI2S configuration register) bitfields. + struct { + Object *plli2sn; // [6:14] PLLI2S multiplication factor for VCO + Object *plli2sq; // [24:27] PLLI2S division factor for SAI1 clock + Object *plli2sr; // [28:30] PLLI2S division factor for I2S clocks + } plli2scfgr; + + // PLLSAICFGR (PLLSAICFGR) bitfields. + struct { + Object *pllsain; // [6:14] PLLSAIN + Object *pllsaiq; // [24:27] PLLSAIN + Object *pllsair; // [28:30] PLLSAIN + } pllsaicfgr; + + // DCKCFGR (DCKCFGR) bitfields. + struct { + Object *plli2sdivq; // [0:4] PLLI2SDIVQ + Object *pllsaidivq; // [8:12] PLLSAIDIVQ + Object *pllsaidivr; // [16:17] PLLSAIDIVR + Object *sai1asrc; // [20:21] SAI1ASRC + Object *sai1bsrc; // [22:23] SAI1BSRC + Object *timpre; // [24:24] TIMPRE + } dckcfgr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RCCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RCC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/rng.c b/gnu-mcu-eclipse/devices/support/STM32F429x/rng.c new file mode 100644 index 0000000000..044616e34a --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/rng.c @@ -0,0 +1,251 @@ +/* + * STM32 - RNG (Random number generator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_rng_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RNGState *state = STM32_RNG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + + + // CR bitfields. + state->u.f4.fld.cr.rngen = cm_object_get_child_by_name(state->u.f4.reg.cr, "RNGEN"); + state->u.f4.fld.cr.ie = cm_object_get_child_by_name(state->u.f4.reg.cr, "IE"); + + // SR bitfields. + state->u.f4.fld.sr.drdy = cm_object_get_child_by_name(state->u.f4.reg.sr, "DRDY"); + state->u.f4.fld.sr.cecs = cm_object_get_child_by_name(state->u.f4.reg.sr, "CECS"); + state->u.f4.fld.sr.secs = cm_object_get_child_by_name(state->u.f4.reg.sr, "SECS"); + state->u.f4.fld.sr.ceis = cm_object_get_child_by_name(state->u.f4.reg.sr, "CEIS"); + state->u.f4.fld.sr.seis = cm_object_get_child_by_name(state->u.f4.reg.sr, "SEIS"); + + // DR bitfields. + state->u.f4.fld.dr.rndata = cm_object_get_child_by_name(state->u.f4.reg.dr, "RNDATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rng_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rng_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rng_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rng_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RNGState *state = STM32_RNG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rng_is_enabled(Object *obj) +{ + STM32RNGState *state = STM32_RNG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rng_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RNGState *state = STM32_RNG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rng_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RNG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RNGState *state = STM32_RNG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RNG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_rng_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rng_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rng_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rng_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rng_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RNGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rng_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RNG); +} + +static void stm32_rng_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rng_reset_callback; + dc->realize = stm32_rng_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rng_is_enabled; +} + +static const TypeInfo stm32_rng_type_info = { + .name = TYPE_STM32_RNG, + .parent = TYPE_STM32_RNG_PARENT, + .instance_init = stm32_rng_instance_init_callback, + .instance_size = sizeof(STM32RNGState), + .class_init = stm32_rng_class_init_callback, + .class_size = sizeof(STM32RNGClass) }; + +static void stm32_rng_register_types(void) +{ + type_register_static(&stm32_rng_type_info); +} + +type_init(stm32_rng_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/rng.h b/gnu-mcu-eclipse/devices/support/STM32F429x/rng.h new file mode 100644 index 0000000000..0bbc556a66 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/rng.h @@ -0,0 +1,122 @@ +/* + * STM32 - RNG (Random number generator) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RNG_H_ +#define STM32_RNG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RNG DEVICE_PATH_STM32 "RNG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RNG TYPE_STM32_PREFIX "rng" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RNG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RNGParentClass; +typedef PeripheralState STM32RNGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RNG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RNGClass, (obj), TYPE_STM32_RNG) +#define STM32_RNG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RNGClass, (klass), TYPE_STM32_RNG) + +typedef struct { + // private: + STM32RNGParentClass parent_class; + // public: + + // None, so far. +} STM32RNGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RNG_STATE(obj) \ + OBJECT_CHECK(STM32RNGState, (obj), TYPE_STM32_RNG) + +typedef struct { + // private: + STM32RNGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RNG (Random number generator) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *sr; // 0x4 (Status register) + Object *dr; // 0x8 (Data register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *rngen; // [2:2] Random number generator enable + Object *ie; // [3:3] Interrupt enable + } cr; + + // SR (Status register) bitfields. + struct { + Object *drdy; // [0:0] Data ready + Object *cecs; // [1:1] Clock error current status + Object *secs; // [2:2] Seed error current status + Object *ceis; // [5:5] Clock error interrupt status + Object *seis; // [6:6] Seed error interrupt status + } sr; + + // DR (Data register) bitfields. + struct { + Object *rndata; // [0:31] Random data + } dr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RNGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RNG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/rtc.c b/gnu-mcu-eclipse/devices/support/STM32F429x/rtc.c new file mode 100644 index 0000000000..1b873207e6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/rtc.c @@ -0,0 +1,490 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_rtc_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.tr = cm_object_get_child_by_name(obj, "TR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.isr = cm_object_get_child_by_name(obj, "ISR"); + state->u.f4.reg.prer = cm_object_get_child_by_name(obj, "PRER"); + state->u.f4.reg.wutr = cm_object_get_child_by_name(obj, "WUTR"); + state->u.f4.reg.calibr = cm_object_get_child_by_name(obj, "CALIBR"); + state->u.f4.reg.alrmar = cm_object_get_child_by_name(obj, "ALRMAR"); + state->u.f4.reg.alrmbr = cm_object_get_child_by_name(obj, "ALRMBR"); + state->u.f4.reg.wpr = cm_object_get_child_by_name(obj, "WPR"); + state->u.f4.reg.ssr = cm_object_get_child_by_name(obj, "SSR"); + state->u.f4.reg.shiftr = cm_object_get_child_by_name(obj, "SHIFTR"); + state->u.f4.reg.tstr = cm_object_get_child_by_name(obj, "TSTR"); + state->u.f4.reg.tsdr = cm_object_get_child_by_name(obj, "TSDR"); + state->u.f4.reg.tsssr = cm_object_get_child_by_name(obj, "TSSSR"); + state->u.f4.reg.calr = cm_object_get_child_by_name(obj, "CALR"); + state->u.f4.reg.tafcr = cm_object_get_child_by_name(obj, "TAFCR"); + state->u.f4.reg.alrmassr = cm_object_get_child_by_name(obj, "ALRMASSR"); + state->u.f4.reg.alrmbssr = cm_object_get_child_by_name(obj, "ALRMBSSR"); + state->u.f4.reg.bkp0r = cm_object_get_child_by_name(obj, "BKP0R"); + state->u.f4.reg.bkp1r = cm_object_get_child_by_name(obj, "BKP1R"); + state->u.f4.reg.bkp2r = cm_object_get_child_by_name(obj, "BKP2R"); + state->u.f4.reg.bkp3r = cm_object_get_child_by_name(obj, "BKP3R"); + state->u.f4.reg.bkp4r = cm_object_get_child_by_name(obj, "BKP4R"); + state->u.f4.reg.bkp5r = cm_object_get_child_by_name(obj, "BKP5R"); + state->u.f4.reg.bkp6r = cm_object_get_child_by_name(obj, "BKP6R"); + state->u.f4.reg.bkp7r = cm_object_get_child_by_name(obj, "BKP7R"); + state->u.f4.reg.bkp8r = cm_object_get_child_by_name(obj, "BKP8R"); + state->u.f4.reg.bkp9r = cm_object_get_child_by_name(obj, "BKP9R"); + state->u.f4.reg.bkp10r = cm_object_get_child_by_name(obj, "BKP10R"); + state->u.f4.reg.bkp11r = cm_object_get_child_by_name(obj, "BKP11R"); + state->u.f4.reg.bkp12r = cm_object_get_child_by_name(obj, "BKP12R"); + state->u.f4.reg.bkp13r = cm_object_get_child_by_name(obj, "BKP13R"); + state->u.f4.reg.bkp14r = cm_object_get_child_by_name(obj, "BKP14R"); + state->u.f4.reg.bkp15r = cm_object_get_child_by_name(obj, "BKP15R"); + state->u.f4.reg.bkp16r = cm_object_get_child_by_name(obj, "BKP16R"); + state->u.f4.reg.bkp17r = cm_object_get_child_by_name(obj, "BKP17R"); + state->u.f4.reg.bkp18r = cm_object_get_child_by_name(obj, "BKP18R"); + state->u.f4.reg.bkp19r = cm_object_get_child_by_name(obj, "BKP19R"); + + + // TR bitfields. + state->u.f4.fld.tr.su = cm_object_get_child_by_name(state->u.f4.reg.tr, "SU"); + state->u.f4.fld.tr.st = cm_object_get_child_by_name(state->u.f4.reg.tr, "ST"); + state->u.f4.fld.tr.mnu = cm_object_get_child_by_name(state->u.f4.reg.tr, "MNU"); + state->u.f4.fld.tr.mnt = cm_object_get_child_by_name(state->u.f4.reg.tr, "MNT"); + state->u.f4.fld.tr.hu = cm_object_get_child_by_name(state->u.f4.reg.tr, "HU"); + state->u.f4.fld.tr.ht = cm_object_get_child_by_name(state->u.f4.reg.tr, "HT"); + state->u.f4.fld.tr.pm = cm_object_get_child_by_name(state->u.f4.reg.tr, "PM"); + + // DR bitfields. + state->u.f4.fld.dr.du = cm_object_get_child_by_name(state->u.f4.reg.dr, "DU"); + state->u.f4.fld.dr.dt = cm_object_get_child_by_name(state->u.f4.reg.dr, "DT"); + state->u.f4.fld.dr.mu = cm_object_get_child_by_name(state->u.f4.reg.dr, "MU"); + state->u.f4.fld.dr.mt = cm_object_get_child_by_name(state->u.f4.reg.dr, "MT"); + state->u.f4.fld.dr.wdu = cm_object_get_child_by_name(state->u.f4.reg.dr, "WDU"); + state->u.f4.fld.dr.yu = cm_object_get_child_by_name(state->u.f4.reg.dr, "YU"); + state->u.f4.fld.dr.yt = cm_object_get_child_by_name(state->u.f4.reg.dr, "YT"); + + // CR bitfields. + state->u.f4.fld.cr.wcksel = cm_object_get_child_by_name(state->u.f4.reg.cr, "WCKSEL"); + state->u.f4.fld.cr.tsedge = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSEDGE"); + state->u.f4.fld.cr.refckon = cm_object_get_child_by_name(state->u.f4.reg.cr, "REFCKON"); + state->u.f4.fld.cr.fmt = cm_object_get_child_by_name(state->u.f4.reg.cr, "FMT"); + state->u.f4.fld.cr.dce = cm_object_get_child_by_name(state->u.f4.reg.cr, "DCE"); + state->u.f4.fld.cr.alrae = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRAE"); + state->u.f4.fld.cr.alrbe = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRBE"); + state->u.f4.fld.cr.wute = cm_object_get_child_by_name(state->u.f4.reg.cr, "WUTE"); + state->u.f4.fld.cr.tse = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSE"); + state->u.f4.fld.cr.alraie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRAIE"); + state->u.f4.fld.cr.alrbie = cm_object_get_child_by_name(state->u.f4.reg.cr, "ALRBIE"); + state->u.f4.fld.cr.wutie = cm_object_get_child_by_name(state->u.f4.reg.cr, "WUTIE"); + state->u.f4.fld.cr.tsie = cm_object_get_child_by_name(state->u.f4.reg.cr, "TSIE"); + state->u.f4.fld.cr.add1h = cm_object_get_child_by_name(state->u.f4.reg.cr, "ADD1H"); + state->u.f4.fld.cr.sub1h = cm_object_get_child_by_name(state->u.f4.reg.cr, "SUB1H"); + state->u.f4.fld.cr.bkp = cm_object_get_child_by_name(state->u.f4.reg.cr, "BKP"); + state->u.f4.fld.cr.pol = cm_object_get_child_by_name(state->u.f4.reg.cr, "POL"); + state->u.f4.fld.cr.osel = cm_object_get_child_by_name(state->u.f4.reg.cr, "OSEL"); + state->u.f4.fld.cr.coe = cm_object_get_child_by_name(state->u.f4.reg.cr, "COE"); + + // ISR bitfields. + state->u.f4.fld.isr.alrawf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRAWF"); + state->u.f4.fld.isr.alrbwf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRBWF"); + state->u.f4.fld.isr.wutwf = cm_object_get_child_by_name(state->u.f4.reg.isr, "WUTWF"); + state->u.f4.fld.isr.shpf = cm_object_get_child_by_name(state->u.f4.reg.isr, "SHPF"); + state->u.f4.fld.isr.inits = cm_object_get_child_by_name(state->u.f4.reg.isr, "INITS"); + state->u.f4.fld.isr.rsf = cm_object_get_child_by_name(state->u.f4.reg.isr, "RSF"); + state->u.f4.fld.isr.initf = cm_object_get_child_by_name(state->u.f4.reg.isr, "INITF"); + state->u.f4.fld.isr.init = cm_object_get_child_by_name(state->u.f4.reg.isr, "INIT"); + state->u.f4.fld.isr.alraf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRAF"); + state->u.f4.fld.isr.alrbf = cm_object_get_child_by_name(state->u.f4.reg.isr, "ALRBF"); + state->u.f4.fld.isr.wutf = cm_object_get_child_by_name(state->u.f4.reg.isr, "WUTF"); + state->u.f4.fld.isr.tsf = cm_object_get_child_by_name(state->u.f4.reg.isr, "TSF"); + state->u.f4.fld.isr.tsovf = cm_object_get_child_by_name(state->u.f4.reg.isr, "TSOVF"); + state->u.f4.fld.isr.tamp1f = cm_object_get_child_by_name(state->u.f4.reg.isr, "TAMP1F"); + state->u.f4.fld.isr.tamp2f = cm_object_get_child_by_name(state->u.f4.reg.isr, "TAMP2F"); + state->u.f4.fld.isr.recalpf = cm_object_get_child_by_name(state->u.f4.reg.isr, "RECALPF"); + + // PRER bitfields. + state->u.f4.fld.prer.prediv_s = cm_object_get_child_by_name(state->u.f4.reg.prer, "PREDIV_S"); + state->u.f4.fld.prer.prediv_a = cm_object_get_child_by_name(state->u.f4.reg.prer, "PREDIV_A"); + + // WUTR bitfields. + state->u.f4.fld.wutr.wut = cm_object_get_child_by_name(state->u.f4.reg.wutr, "WUT"); + + // CALIBR bitfields. + state->u.f4.fld.calibr.dc = cm_object_get_child_by_name(state->u.f4.reg.calibr, "DC"); + state->u.f4.fld.calibr.dcs = cm_object_get_child_by_name(state->u.f4.reg.calibr, "DCS"); + + // ALRMAR bitfields. + state->u.f4.fld.alrmar.su = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "SU"); + state->u.f4.fld.alrmar.st = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "ST"); + state->u.f4.fld.alrmar.msk1 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK1"); + state->u.f4.fld.alrmar.mnu = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MNU"); + state->u.f4.fld.alrmar.mnt = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MNT"); + state->u.f4.fld.alrmar.msk2 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK2"); + state->u.f4.fld.alrmar.hu = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "HU"); + state->u.f4.fld.alrmar.ht = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "HT"); + state->u.f4.fld.alrmar.pm = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "PM"); + state->u.f4.fld.alrmar.msk3 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK3"); + state->u.f4.fld.alrmar.du = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "DU"); + state->u.f4.fld.alrmar.dt = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "DT"); + state->u.f4.fld.alrmar.wdsel = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "WDSEL"); + state->u.f4.fld.alrmar.msk4 = cm_object_get_child_by_name(state->u.f4.reg.alrmar, "MSK4"); + + // ALRMBR bitfields. + state->u.f4.fld.alrmbr.su = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "SU"); + state->u.f4.fld.alrmbr.st = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "ST"); + state->u.f4.fld.alrmbr.msk1 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK1"); + state->u.f4.fld.alrmbr.mnu = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MNU"); + state->u.f4.fld.alrmbr.mnt = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MNT"); + state->u.f4.fld.alrmbr.msk2 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK2"); + state->u.f4.fld.alrmbr.hu = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "HU"); + state->u.f4.fld.alrmbr.ht = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "HT"); + state->u.f4.fld.alrmbr.pm = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "PM"); + state->u.f4.fld.alrmbr.msk3 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK3"); + state->u.f4.fld.alrmbr.du = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "DU"); + state->u.f4.fld.alrmbr.dt = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "DT"); + state->u.f4.fld.alrmbr.wdsel = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "WDSEL"); + state->u.f4.fld.alrmbr.msk4 = cm_object_get_child_by_name(state->u.f4.reg.alrmbr, "MSK4"); + + // WPR bitfields. + state->u.f4.fld.wpr.key = cm_object_get_child_by_name(state->u.f4.reg.wpr, "KEY"); + + // SSR bitfields. + state->u.f4.fld.ssr.ss = cm_object_get_child_by_name(state->u.f4.reg.ssr, "SS"); + + // SHIFTR bitfields. + state->u.f4.fld.shiftr.subfs = cm_object_get_child_by_name(state->u.f4.reg.shiftr, "SUBFS"); + state->u.f4.fld.shiftr.add1s = cm_object_get_child_by_name(state->u.f4.reg.shiftr, "ADD1S"); + + // TSTR bitfields. + state->u.f4.fld.tstr.tamp1e = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMP1E"); + state->u.f4.fld.tstr.tamp1trg = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMP1TRG"); + state->u.f4.fld.tstr.tampie = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMPIE"); + state->u.f4.fld.tstr.tamp1insel = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TAMP1INSEL"); + state->u.f4.fld.tstr.tsinsel = cm_object_get_child_by_name(state->u.f4.reg.tstr, "TSINSEL"); + state->u.f4.fld.tstr.alarmouttype = cm_object_get_child_by_name(state->u.f4.reg.tstr, "ALARMOUTTYPE"); + + // TSDR bitfields. + state->u.f4.fld.tsdr.du = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "DU"); + state->u.f4.fld.tsdr.dt = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "DT"); + state->u.f4.fld.tsdr.mu = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "MU"); + state->u.f4.fld.tsdr.mt = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "MT"); + state->u.f4.fld.tsdr.wdu = cm_object_get_child_by_name(state->u.f4.reg.tsdr, "WDU"); + + // TSSSR bitfields. + state->u.f4.fld.tsssr.ss = cm_object_get_child_by_name(state->u.f4.reg.tsssr, "SS"); + + // CALR bitfields. + state->u.f4.fld.calr.calm = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALM"); + state->u.f4.fld.calr.calw16 = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALW16"); + state->u.f4.fld.calr.calw8 = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALW8"); + state->u.f4.fld.calr.calp = cm_object_get_child_by_name(state->u.f4.reg.calr, "CALP"); + + // TAFCR bitfields. + state->u.f4.fld.tafcr.tamp1e = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1E"); + state->u.f4.fld.tafcr.tamp1trg = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1TRG"); + state->u.f4.fld.tafcr.tampie = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPIE"); + state->u.f4.fld.tafcr.tamp2e = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP2E"); + state->u.f4.fld.tafcr.tamp2trg = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP2TRG"); + state->u.f4.fld.tafcr.tampts = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPTS"); + state->u.f4.fld.tafcr.tampfreq = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPFREQ"); + state->u.f4.fld.tafcr.tampflt = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPFLT"); + state->u.f4.fld.tafcr.tampprch = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPPRCH"); + state->u.f4.fld.tafcr.tamppudis = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMPPUDIS"); + state->u.f4.fld.tafcr.tamp1insel = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TAMP1INSEL"); + state->u.f4.fld.tafcr.tsinsel = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "TSINSEL"); + state->u.f4.fld.tafcr.alarmouttype = cm_object_get_child_by_name(state->u.f4.reg.tafcr, "ALARMOUTTYPE"); + + // ALRMASSR bitfields. + state->u.f4.fld.alrmassr.ss = cm_object_get_child_by_name(state->u.f4.reg.alrmassr, "SS"); + state->u.f4.fld.alrmassr.maskss = cm_object_get_child_by_name(state->u.f4.reg.alrmassr, "MASKSS"); + + // ALRMBSSR bitfields. + state->u.f4.fld.alrmbssr.ss = cm_object_get_child_by_name(state->u.f4.reg.alrmbssr, "SS"); + state->u.f4.fld.alrmbssr.maskss = cm_object_get_child_by_name(state->u.f4.reg.alrmbssr, "MASKSS"); + + // BKP0R bitfields. + state->u.f4.fld.bkp0r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp0r, "BKP"); + + // BKP1R bitfields. + state->u.f4.fld.bkp1r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp1r, "BKP"); + + // BKP2R bitfields. + state->u.f4.fld.bkp2r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp2r, "BKP"); + + // BKP3R bitfields. + state->u.f4.fld.bkp3r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp3r, "BKP"); + + // BKP4R bitfields. + state->u.f4.fld.bkp4r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp4r, "BKP"); + + // BKP5R bitfields. + state->u.f4.fld.bkp5r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp5r, "BKP"); + + // BKP6R bitfields. + state->u.f4.fld.bkp6r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp6r, "BKP"); + + // BKP7R bitfields. + state->u.f4.fld.bkp7r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp7r, "BKP"); + + // BKP8R bitfields. + state->u.f4.fld.bkp8r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp8r, "BKP"); + + // BKP9R bitfields. + state->u.f4.fld.bkp9r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp9r, "BKP"); + + // BKP10R bitfields. + state->u.f4.fld.bkp10r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp10r, "BKP"); + + // BKP11R bitfields. + state->u.f4.fld.bkp11r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp11r, "BKP"); + + // BKP12R bitfields. + state->u.f4.fld.bkp12r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp12r, "BKP"); + + // BKP13R bitfields. + state->u.f4.fld.bkp13r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp13r, "BKP"); + + // BKP14R bitfields. + state->u.f4.fld.bkp14r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp14r, "BKP"); + + // BKP15R bitfields. + state->u.f4.fld.bkp15r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp15r, "BKP"); + + // BKP16R bitfields. + state->u.f4.fld.bkp16r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp16r, "BKP"); + + // BKP17R bitfields. + state->u.f4.fld.bkp17r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp17r, "BKP"); + + // BKP18R bitfields. + state->u.f4.fld.bkp18r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp18r, "BKP"); + + // BKP19R bitfields. + state->u.f4.fld.bkp19r.bkp = cm_object_get_child_by_name(state->u.f4.reg.bkp19r, "BKP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_rtc_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_rtc_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_rtc_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_rtc_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32RTCState *state = STM32_RTC_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_rtc_is_enabled(Object *obj) +{ + STM32RTCState *state = STM32_RTC_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_rtc_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32RTCState *state = STM32_RTC_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_rtc_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_RTC)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32RTCState *state = STM32_RTC_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "RTC"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_rtc_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rtc_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_rtc_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_rtc_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_rtc_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/RTCEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_rtc_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_RTC); +} + +static void stm32_rtc_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_rtc_reset_callback; + dc->realize = stm32_rtc_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_rtc_is_enabled; +} + +static const TypeInfo stm32_rtc_type_info = { + .name = TYPE_STM32_RTC, + .parent = TYPE_STM32_RTC_PARENT, + .instance_init = stm32_rtc_instance_init_callback, + .instance_size = sizeof(STM32RTCState), + .class_init = stm32_rtc_class_init_callback, + .class_size = sizeof(STM32RTCClass) }; + +static void stm32_rtc_register_types(void) +{ + type_register_static(&stm32_rtc_type_info); +} + +type_init(stm32_rtc_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/rtc.h b/gnu-mcu-eclipse/devices/support/STM32F429x/rtc.h new file mode 100644 index 0000000000..a4f892896e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/rtc.h @@ -0,0 +1,433 @@ +/* + * STM32 - RTC (Real-time clock) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_RTC_H_ +#define STM32_RTC_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_RTC DEVICE_PATH_STM32 "RTC" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_RTC TYPE_STM32_PREFIX "rtc" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_RTC_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32RTCParentClass; +typedef PeripheralState STM32RTCParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_RTC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32RTCClass, (obj), TYPE_STM32_RTC) +#define STM32_RTC_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32RTCClass, (klass), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentClass parent_class; + // public: + + // None, so far. +} STM32RTCClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_RTC_STATE(obj) \ + OBJECT_CHECK(STM32RTCState, (obj), TYPE_STM32_RTC) + +typedef struct { + // private: + STM32RTCParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 RTC (Real-time clock) registers. + struct { + Object *tr; // 0x0 (Time register) + Object *dr; // 0x4 (Date register) + Object *cr; // 0x8 (Control register) + Object *isr; // 0xC (Initialization and status register) + Object *prer; // 0x10 (Prescaler register) + Object *wutr; // 0x14 (Wakeup timer register) + Object *calibr; // 0x18 (Calibration register) + Object *alrmar; // 0x1C (Alarm A register) + Object *alrmbr; // 0x20 (Alarm B register) + Object *wpr; // 0x24 (Write protection register) + Object *ssr; // 0x28 (Sub second register) + Object *shiftr; // 0x2C (Shift control register) + Object *tstr; // 0x30 (Time stamp time register) + Object *tsdr; // 0x34 (Time stamp date register) + Object *tsssr; // 0x38 (Timestamp sub second register) + Object *calr; // 0x3C (Calibration register) + Object *tafcr; // 0x40 (Tamper and alternate function configuration register) + Object *alrmassr; // 0x44 (Alarm A sub second register) + Object *alrmbssr; // 0x48 (Alarm B sub second register) + Object *bkp0r; // 0x50 (Backup register) + Object *bkp1r; // 0x54 (Backup register) + Object *bkp2r; // 0x58 (Backup register) + Object *bkp3r; // 0x5C (Backup register) + Object *bkp4r; // 0x60 (Backup register) + Object *bkp5r; // 0x64 (Backup register) + Object *bkp6r; // 0x68 (Backup register) + Object *bkp7r; // 0x6C (Backup register) + Object *bkp8r; // 0x70 (Backup register) + Object *bkp9r; // 0x74 (Backup register) + Object *bkp10r; // 0x78 (Backup register) + Object *bkp11r; // 0x7C (Backup register) + Object *bkp12r; // 0x80 (Backup register) + Object *bkp13r; // 0x84 (Backup register) + Object *bkp14r; // 0x88 (Backup register) + Object *bkp15r; // 0x8C (Backup register) + Object *bkp16r; // 0x90 (Backup register) + Object *bkp17r; // 0x94 (Backup register) + Object *bkp18r; // 0x98 (Backup register) + Object *bkp19r; // 0x9C (Backup register) + } reg; + + struct { + + // TR (Time register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + } tr; + + // DR (Date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + Object *yu; // [16:19] Year units in BCD format + Object *yt; // [20:23] Year tens in BCD format + } dr; + + // CR (Control register) bitfields. + struct { + Object *wcksel; // [0:2] Wakeup clock selection + Object *tsedge; // [3:3] Time-stamp event active edge + Object *refckon; // [4:4] Reference clock detection enable (50 or 60 Hz) + Object *fmt; // [6:6] Hour format + Object *dce; // [7:7] Coarse digital calibration enable + Object *alrae; // [8:8] Alarm A enable + Object *alrbe; // [9:9] Alarm B enable + Object *wute; // [10:10] Wakeup timer enable + Object *tse; // [11:11] Time stamp enable + Object *alraie; // [12:12] Alarm A interrupt enable + Object *alrbie; // [13:13] Alarm B interrupt enable + Object *wutie; // [14:14] Wakeup timer interrupt enable + Object *tsie; // [15:15] Time-stamp interrupt enable + Object *add1h; // [16:16] Add 1 hour (summer time change) + Object *sub1h; // [17:17] Subtract 1 hour (winter time change) + Object *bkp; // [18:18] Backup + Object *pol; // [20:20] Output polarity + Object *osel; // [21:22] Output selection + Object *coe; // [23:23] Calibration output enable + } cr; + + // ISR (Initialization and status register) bitfields. + struct { + Object *alrawf; // [0:0] Alarm A write flag + Object *alrbwf; // [1:1] Alarm B write flag + Object *wutwf; // [2:2] Wakeup timer write flag + Object *shpf; // [3:3] Shift operation pending + Object *inits; // [4:4] Initialization status flag + Object *rsf; // [5:5] Registers synchronization flag + Object *initf; // [6:6] Initialization flag + Object *init; // [7:7] Initialization mode + Object *alraf; // [8:8] Alarm A flag + Object *alrbf; // [9:9] Alarm B flag + Object *wutf; // [10:10] Wakeup timer flag + Object *tsf; // [11:11] Time-stamp flag + Object *tsovf; // [12:12] Time-stamp overflow flag + Object *tamp1f; // [13:13] Tamper detection flag + Object *tamp2f; // [14:14] TAMPER2 detection flag + Object *recalpf; // [16:16] Recalibration pending Flag + } isr; + + // PRER (Prescaler register) bitfields. + struct { + Object *prediv_s; // [0:14] Synchronous prescaler factor + Object *prediv_a; // [16:22] Asynchronous prescaler factor + } prer; + + // WUTR (Wakeup timer register) bitfields. + struct { + Object *wut; // [0:15] Wakeup auto-reload value bits + } wutr; + + // CALIBR (Calibration register) bitfields. + struct { + Object *dc; // [0:4] Digital calibration + Object *dcs; // [7:7] Digital calibration sign + } calibr; + + // ALRMAR (Alarm A register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *msk1; // [7:7] Alarm A seconds mask + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *msk2; // [15:15] Alarm A minutes mask + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + Object *msk3; // [23:23] Alarm A hours mask + Object *du; // [24:27] Date units or day in BCD format + Object *dt; // [28:29] Date tens in BCD format + Object *wdsel; // [30:30] Week day selection + Object *msk4; // [31:31] Alarm A date mask + } alrmar; + + // ALRMBR (Alarm B register) bitfields. + struct { + Object *su; // [0:3] Second units in BCD format + Object *st; // [4:6] Second tens in BCD format + Object *msk1; // [7:7] Alarm B seconds mask + Object *mnu; // [8:11] Minute units in BCD format + Object *mnt; // [12:14] Minute tens in BCD format + Object *msk2; // [15:15] Alarm B minutes mask + Object *hu; // [16:19] Hour units in BCD format + Object *ht; // [20:21] Hour tens in BCD format + Object *pm; // [22:22] AM/PM notation + Object *msk3; // [23:23] Alarm B hours mask + Object *du; // [24:27] Date units or day in BCD format + Object *dt; // [28:29] Date tens in BCD format + Object *wdsel; // [30:30] Week day selection + Object *msk4; // [31:31] Alarm B date mask + } alrmbr; + + // WPR (Write protection register) bitfields. + struct { + Object *key; // [0:7] Write protection key + } wpr; + + // SSR (Sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } ssr; + + // SHIFTR (Shift control register) bitfields. + struct { + Object *subfs; // [0:14] Subtract a fraction of a second + Object *add1s; // [31:31] Add one second + } shiftr; + + // TSTR (Time stamp time register) bitfields. + struct { + Object *tamp1e; // [0:0] Tamper 1 detection enable + Object *tamp1trg; // [1:1] Active level for tamper 1 + Object *tampie; // [2:2] Tamper interrupt enable + Object *tamp1insel; // [16:16] TAMPER1 mapping + Object *tsinsel; // [17:17] TIMESTAMP mapping + Object *alarmouttype; // [18:18] AFO_ALARM output type + } tstr; + + // TSDR (Time stamp date register) bitfields. + struct { + Object *du; // [0:3] Date units in BCD format + Object *dt; // [4:5] Date tens in BCD format + Object *mu; // [8:11] Month units in BCD format + Object *mt; // [12:12] Month tens in BCD format + Object *wdu; // [13:15] Week day units + } tsdr; + + // TSSSR (Timestamp sub second register) bitfields. + struct { + Object *ss; // [0:15] Sub second value + } tsssr; + + // CALR (Calibration register) bitfields. + struct { + Object *calm; // [0:8] Calibration minus + Object *calw16; // [13:13] Use a 16-second calibration cycle period + Object *calw8; // [14:14] Use an 8-second calibration cycle period + Object *calp; // [15:15] Increase frequency of RTC by 488.5 ppm + } calr; + + // TAFCR (Tamper and alternate function configuration register) bitfields. + struct { + Object *tamp1e; // [0:0] Tamper 1 detection enable + Object *tamp1trg; // [1:1] Active level for tamper 1 + Object *tampie; // [2:2] Tamper interrupt enable + Object *tamp2e; // [3:3] Tamper 2 detection enable + Object *tamp2trg; // [4:4] Active level for tamper 2 + Object *tampts; // [7:7] Activate timestamp on tamper detection event + Object *tampfreq; // [8:10] Tamper sampling frequency + Object *tampflt; // [11:12] Tamper filter count + Object *tampprch; // [13:14] Tamper precharge duration + Object *tamppudis; // [15:15] TAMPER pull-up disable + Object *tamp1insel; // [16:16] TAMPER1 mapping + Object *tsinsel; // [17:17] TIMESTAMP mapping + Object *alarmouttype; // [18:18] AFO_ALARM output type + } tafcr; + + // ALRMASSR (Alarm A sub second register) bitfields. + struct { + Object *ss; // [0:14] Sub seconds value + Object *maskss; // [24:27] Mask the most-significant bits starting at this bit + } alrmassr; + + // ALRMBSSR (Alarm B sub second register) bitfields. + struct { + Object *ss; // [0:14] Sub seconds value + Object *maskss; // [24:27] Mask the most-significant bits starting at this bit + } alrmbssr; + + // BKP0R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp0r; + + // BKP1R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp1r; + + // BKP2R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp2r; + + // BKP3R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp3r; + + // BKP4R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp4r; + + // BKP5R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp5r; + + // BKP6R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp6r; + + // BKP7R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp7r; + + // BKP8R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp8r; + + // BKP9R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp9r; + + // BKP10R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp10r; + + // BKP11R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp11r; + + // BKP12R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp12r; + + // BKP13R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp13r; + + // BKP14R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp14r; + + // BKP15R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp15r; + + // BKP16R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp16r; + + // BKP17R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp17r; + + // BKP18R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp18r; + + // BKP19R (Backup register) bitfields. + struct { + Object *bkp; // [0:31] BKP + } bkp19r; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32RTCState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_RTC_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/sai.c b/gnu-mcu-eclipse/devices/support/STM32F429x/sai.c new file mode 100644 index 0000000000..a8eee5e6f2 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/sai.c @@ -0,0 +1,384 @@ +/* + * STM32 - SAI (Serial audio interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_sai_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SAIState *state = STM32_SAI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.bcr1 = cm_object_get_child_by_name(obj, "BCR1"); + state->u.f4.reg.bcr2 = cm_object_get_child_by_name(obj, "BCR2"); + state->u.f4.reg.bfrcr = cm_object_get_child_by_name(obj, "BFRCR"); + state->u.f4.reg.bslotr = cm_object_get_child_by_name(obj, "BSLOTR"); + state->u.f4.reg.bim = cm_object_get_child_by_name(obj, "BIM"); + state->u.f4.reg.bsr = cm_object_get_child_by_name(obj, "BSR"); + state->u.f4.reg.bclrfr = cm_object_get_child_by_name(obj, "BCLRFR"); + state->u.f4.reg.bdr = cm_object_get_child_by_name(obj, "BDR"); + state->u.f4.reg.acr1 = cm_object_get_child_by_name(obj, "ACR1"); + state->u.f4.reg.acr2 = cm_object_get_child_by_name(obj, "ACR2"); + state->u.f4.reg.afrcr = cm_object_get_child_by_name(obj, "AFRCR"); + state->u.f4.reg.aslotr = cm_object_get_child_by_name(obj, "ASLOTR"); + state->u.f4.reg.aim = cm_object_get_child_by_name(obj, "AIM"); + state->u.f4.reg.asr = cm_object_get_child_by_name(obj, "ASR"); + state->u.f4.reg.aclrfr = cm_object_get_child_by_name(obj, "ACLRFR"); + state->u.f4.reg.adr = cm_object_get_child_by_name(obj, "ADR"); + + + // BCR1 bitfields. + state->u.f4.fld.bcr1.mode = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MODE"); + state->u.f4.fld.bcr1.prtcfg = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "PRTCFG"); + state->u.f4.fld.bcr1.ds = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "DS"); + state->u.f4.fld.bcr1.lsbfirst = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "LSBFIRST"); + state->u.f4.fld.bcr1.ckstr = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "CKSTR"); + state->u.f4.fld.bcr1.syncen = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "SYNCEN"); + state->u.f4.fld.bcr1.mono = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MONO"); + state->u.f4.fld.bcr1.outdri = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "OutDri"); + state->u.f4.fld.bcr1.saiben = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "SAIBEN"); + state->u.f4.fld.bcr1.dmaen = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "DMAEN"); + state->u.f4.fld.bcr1.nodiv = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "NODIV"); + state->u.f4.fld.bcr1.mcjdiv = cm_object_get_child_by_name(state->u.f4.reg.bcr1, "MCJDIV"); + + // BCR2 bitfields. + state->u.f4.fld.bcr2.fth = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "FTH"); + state->u.f4.fld.bcr2.fflus = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "FFLUS"); + state->u.f4.fld.bcr2.tris = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "TRIS"); + state->u.f4.fld.bcr2.mute = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MUTE"); + state->u.f4.fld.bcr2.muteval = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MUTEVAL"); + state->u.f4.fld.bcr2.mutecn = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "MUTECN"); + state->u.f4.fld.bcr2.cpl = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "CPL"); + state->u.f4.fld.bcr2.comp = cm_object_get_child_by_name(state->u.f4.reg.bcr2, "COMP"); + + // BFRCR bitfields. + state->u.f4.fld.bfrcr.frl = cm_object_get_child_by_name(state->u.f4.reg.bfrcr, "FRL"); + state->u.f4.fld.bfrcr.fsall = cm_object_get_child_by_name(state->u.f4.reg.bfrcr, "FSALL"); + state->u.f4.fld.bfrcr.fsdef = cm_object_get_child_by_name(state->u.f4.reg.bfrcr, "FSDEF"); + state->u.f4.fld.bfrcr.fspol = cm_object_get_child_by_name(state->u.f4.reg.bfrcr, "FSPOL"); + state->u.f4.fld.bfrcr.fsoff = cm_object_get_child_by_name(state->u.f4.reg.bfrcr, "FSOFF"); + + // BSLOTR bitfields. + state->u.f4.fld.bslotr.fboff = cm_object_get_child_by_name(state->u.f4.reg.bslotr, "FBOFF"); + state->u.f4.fld.bslotr.slotsz = cm_object_get_child_by_name(state->u.f4.reg.bslotr, "SLOTSZ"); + state->u.f4.fld.bslotr.nbslot = cm_object_get_child_by_name(state->u.f4.reg.bslotr, "NBSLOT"); + state->u.f4.fld.bslotr.sloten = cm_object_get_child_by_name(state->u.f4.reg.bslotr, "SLOTEN"); + + // BIM bitfields. + state->u.f4.fld.bim.ovrudrie = cm_object_get_child_by_name(state->u.f4.reg.bim, "OVRUDRIE"); + state->u.f4.fld.bim.mutedet = cm_object_get_child_by_name(state->u.f4.reg.bim, "MUTEDET"); + state->u.f4.fld.bim.wckcfg = cm_object_get_child_by_name(state->u.f4.reg.bim, "WCKCFG"); + state->u.f4.fld.bim.freqie = cm_object_get_child_by_name(state->u.f4.reg.bim, "FREQIE"); + state->u.f4.fld.bim.cnrdyie = cm_object_get_child_by_name(state->u.f4.reg.bim, "CNRDYIE"); + state->u.f4.fld.bim.afsdetie = cm_object_get_child_by_name(state->u.f4.reg.bim, "AFSDETIE"); + state->u.f4.fld.bim.lfsdetie = cm_object_get_child_by_name(state->u.f4.reg.bim, "LFSDETIE"); + + // BSR bitfields. + state->u.f4.fld.bsr.ovrudr = cm_object_get_child_by_name(state->u.f4.reg.bsr, "OVRUDR"); + state->u.f4.fld.bsr.mutedet = cm_object_get_child_by_name(state->u.f4.reg.bsr, "MUTEDET"); + state->u.f4.fld.bsr.wckcfg = cm_object_get_child_by_name(state->u.f4.reg.bsr, "WCKCFG"); + state->u.f4.fld.bsr.freq = cm_object_get_child_by_name(state->u.f4.reg.bsr, "FREQ"); + state->u.f4.fld.bsr.cnrdy = cm_object_get_child_by_name(state->u.f4.reg.bsr, "CNRDY"); + state->u.f4.fld.bsr.afsdet = cm_object_get_child_by_name(state->u.f4.reg.bsr, "AFSDET"); + state->u.f4.fld.bsr.lfsdet = cm_object_get_child_by_name(state->u.f4.reg.bsr, "LFSDET"); + state->u.f4.fld.bsr.flvl = cm_object_get_child_by_name(state->u.f4.reg.bsr, "FLVL"); + + // BCLRFR bitfields. + state->u.f4.fld.bclrfr.ovrudr = cm_object_get_child_by_name(state->u.f4.reg.bclrfr, "OVRUDR"); + state->u.f4.fld.bclrfr.mutedet = cm_object_get_child_by_name(state->u.f4.reg.bclrfr, "MUTEDET"); + state->u.f4.fld.bclrfr.wckcfg = cm_object_get_child_by_name(state->u.f4.reg.bclrfr, "WCKCFG"); + state->u.f4.fld.bclrfr.cnrdy = cm_object_get_child_by_name(state->u.f4.reg.bclrfr, "CNRDY"); + state->u.f4.fld.bclrfr.cafsdet = cm_object_get_child_by_name(state->u.f4.reg.bclrfr, "CAFSDET"); + state->u.f4.fld.bclrfr.lfsdet = cm_object_get_child_by_name(state->u.f4.reg.bclrfr, "LFSDET"); + + // BDR bitfields. + state->u.f4.fld.bdr.data = cm_object_get_child_by_name(state->u.f4.reg.bdr, "DATA"); + + // ACR1 bitfields. + state->u.f4.fld.acr1.mode = cm_object_get_child_by_name(state->u.f4.reg.acr1, "MODE"); + state->u.f4.fld.acr1.prtcfg = cm_object_get_child_by_name(state->u.f4.reg.acr1, "PRTCFG"); + state->u.f4.fld.acr1.ds = cm_object_get_child_by_name(state->u.f4.reg.acr1, "DS"); + state->u.f4.fld.acr1.lsbfirst = cm_object_get_child_by_name(state->u.f4.reg.acr1, "LSBFIRST"); + state->u.f4.fld.acr1.ckstr = cm_object_get_child_by_name(state->u.f4.reg.acr1, "CKSTR"); + state->u.f4.fld.acr1.syncen = cm_object_get_child_by_name(state->u.f4.reg.acr1, "SYNCEN"); + state->u.f4.fld.acr1.mono = cm_object_get_child_by_name(state->u.f4.reg.acr1, "MONO"); + state->u.f4.fld.acr1.outdri = cm_object_get_child_by_name(state->u.f4.reg.acr1, "OutDri"); + state->u.f4.fld.acr1.saiaen = cm_object_get_child_by_name(state->u.f4.reg.acr1, "SAIAEN"); + state->u.f4.fld.acr1.dmaen = cm_object_get_child_by_name(state->u.f4.reg.acr1, "DMAEN"); + state->u.f4.fld.acr1.nodiv = cm_object_get_child_by_name(state->u.f4.reg.acr1, "NODIV"); + state->u.f4.fld.acr1.mcjdiv = cm_object_get_child_by_name(state->u.f4.reg.acr1, "MCJDIV"); + + // ACR2 bitfields. + state->u.f4.fld.acr2.fth = cm_object_get_child_by_name(state->u.f4.reg.acr2, "FTH"); + state->u.f4.fld.acr2.fflus = cm_object_get_child_by_name(state->u.f4.reg.acr2, "FFLUS"); + state->u.f4.fld.acr2.tris = cm_object_get_child_by_name(state->u.f4.reg.acr2, "TRIS"); + state->u.f4.fld.acr2.mute = cm_object_get_child_by_name(state->u.f4.reg.acr2, "MUTE"); + state->u.f4.fld.acr2.muteval = cm_object_get_child_by_name(state->u.f4.reg.acr2, "MUTEVAL"); + state->u.f4.fld.acr2.mutecn = cm_object_get_child_by_name(state->u.f4.reg.acr2, "MUTECN"); + state->u.f4.fld.acr2.cpl = cm_object_get_child_by_name(state->u.f4.reg.acr2, "CPL"); + state->u.f4.fld.acr2.comp = cm_object_get_child_by_name(state->u.f4.reg.acr2, "COMP"); + + // AFRCR bitfields. + state->u.f4.fld.afrcr.frl = cm_object_get_child_by_name(state->u.f4.reg.afrcr, "FRL"); + state->u.f4.fld.afrcr.fsall = cm_object_get_child_by_name(state->u.f4.reg.afrcr, "FSALL"); + state->u.f4.fld.afrcr.fsdef = cm_object_get_child_by_name(state->u.f4.reg.afrcr, "FSDEF"); + state->u.f4.fld.afrcr.fspol = cm_object_get_child_by_name(state->u.f4.reg.afrcr, "FSPOL"); + state->u.f4.fld.afrcr.fsoff = cm_object_get_child_by_name(state->u.f4.reg.afrcr, "FSOFF"); + + // ASLOTR bitfields. + state->u.f4.fld.aslotr.fboff = cm_object_get_child_by_name(state->u.f4.reg.aslotr, "FBOFF"); + state->u.f4.fld.aslotr.slotsz = cm_object_get_child_by_name(state->u.f4.reg.aslotr, "SLOTSZ"); + state->u.f4.fld.aslotr.nbslot = cm_object_get_child_by_name(state->u.f4.reg.aslotr, "NBSLOT"); + state->u.f4.fld.aslotr.sloten = cm_object_get_child_by_name(state->u.f4.reg.aslotr, "SLOTEN"); + + // AIM bitfields. + state->u.f4.fld.aim.ovrudrie = cm_object_get_child_by_name(state->u.f4.reg.aim, "OVRUDRIE"); + state->u.f4.fld.aim.mutedet = cm_object_get_child_by_name(state->u.f4.reg.aim, "MUTEDET"); + state->u.f4.fld.aim.wckcfg = cm_object_get_child_by_name(state->u.f4.reg.aim, "WCKCFG"); + state->u.f4.fld.aim.freqie = cm_object_get_child_by_name(state->u.f4.reg.aim, "FREQIE"); + state->u.f4.fld.aim.cnrdyie = cm_object_get_child_by_name(state->u.f4.reg.aim, "CNRDYIE"); + state->u.f4.fld.aim.afsdetie = cm_object_get_child_by_name(state->u.f4.reg.aim, "AFSDETIE"); + state->u.f4.fld.aim.lfsdet = cm_object_get_child_by_name(state->u.f4.reg.aim, "LFSDET"); + + // ASR bitfields. + state->u.f4.fld.asr.ovrudr = cm_object_get_child_by_name(state->u.f4.reg.asr, "OVRUDR"); + state->u.f4.fld.asr.mutedet = cm_object_get_child_by_name(state->u.f4.reg.asr, "MUTEDET"); + state->u.f4.fld.asr.wckcfg = cm_object_get_child_by_name(state->u.f4.reg.asr, "WCKCFG"); + state->u.f4.fld.asr.freq = cm_object_get_child_by_name(state->u.f4.reg.asr, "FREQ"); + state->u.f4.fld.asr.cnrdy = cm_object_get_child_by_name(state->u.f4.reg.asr, "CNRDY"); + state->u.f4.fld.asr.afsdet = cm_object_get_child_by_name(state->u.f4.reg.asr, "AFSDET"); + state->u.f4.fld.asr.lfsdet = cm_object_get_child_by_name(state->u.f4.reg.asr, "LFSDET"); + state->u.f4.fld.asr.flvl = cm_object_get_child_by_name(state->u.f4.reg.asr, "FLVL"); + + // ACLRFR bitfields. + state->u.f4.fld.aclrfr.ovrudr = cm_object_get_child_by_name(state->u.f4.reg.aclrfr, "OVRUDR"); + state->u.f4.fld.aclrfr.mutedet = cm_object_get_child_by_name(state->u.f4.reg.aclrfr, "MUTEDET"); + state->u.f4.fld.aclrfr.wckcfg = cm_object_get_child_by_name(state->u.f4.reg.aclrfr, "WCKCFG"); + state->u.f4.fld.aclrfr.cnrdy = cm_object_get_child_by_name(state->u.f4.reg.aclrfr, "CNRDY"); + state->u.f4.fld.aclrfr.cafsdet = cm_object_get_child_by_name(state->u.f4.reg.aclrfr, "CAFSDET"); + state->u.f4.fld.aclrfr.lfsdet = cm_object_get_child_by_name(state->u.f4.reg.aclrfr, "LFSDET"); + + // ADR bitfields. + state->u.f4.fld.adr.data = cm_object_get_child_by_name(state->u.f4.reg.adr, "DATA"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_sai_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SAIState *state = STM32_SAI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_sai_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SAIState *state = STM32_SAI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_sai_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SAIState *state = STM32_SAI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_sai_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SAIState *state = STM32_SAI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_sai_is_enabled(Object *obj) +{ + STM32SAIState *state = STM32_SAI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_sai_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SAIState *state = STM32_SAI_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_sai_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SAI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SAIState *state = STM32_SAI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SAI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_sai_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sai_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_sai_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sai_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_sai_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SAIEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_sai_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SAI); +} + +static void stm32_sai_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_sai_reset_callback; + dc->realize = stm32_sai_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_sai_is_enabled; +} + +static const TypeInfo stm32_sai_type_info = { + .name = TYPE_STM32_SAI, + .parent = TYPE_STM32_SAI_PARENT, + .instance_init = stm32_sai_instance_init_callback, + .instance_size = sizeof(STM32SAIState), + .class_init = stm32_sai_class_init_callback, + .class_size = sizeof(STM32SAIClass) }; + +static void stm32_sai_register_types(void) +{ + type_register_static(&stm32_sai_type_info); +} + +type_init(stm32_sai_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/sai.h b/gnu-mcu-eclipse/devices/support/STM32F429x/sai.h new file mode 100644 index 0000000000..473bf02f70 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/sai.h @@ -0,0 +1,281 @@ +/* + * STM32 - SAI (Serial audio interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SAI_H_ +#define STM32_SAI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SAI DEVICE_PATH_STM32 "SAI" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SAI TYPE_STM32_PREFIX "sai" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SAI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SAIParentClass; +typedef PeripheralState STM32SAIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SAI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SAIClass, (obj), TYPE_STM32_SAI) +#define STM32_SAI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SAIClass, (klass), TYPE_STM32_SAI) + +typedef struct { + // private: + STM32SAIParentClass parent_class; + // public: + + // None, so far. +} STM32SAIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SAI_STATE(obj) \ + OBJECT_CHECK(STM32SAIState, (obj), TYPE_STM32_SAI) + +typedef struct { + // private: + STM32SAIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SAI (Serial audio interface) registers. + struct { + Object *bcr1; // 0x24 (BConfiguration register 1) + Object *bcr2; // 0x28 (BConfiguration register 2) + Object *bfrcr; // 0x2C (BFRCR) + Object *bslotr; // 0x30 (BSlot register) + Object *bim; // 0x34 (BInterrupt mask register2) + Object *bsr; // 0x38 (BStatus register) + Object *bclrfr; // 0x3C (BClear flag register) + Object *bdr; // 0x40 (BData register) + Object *acr1; // 0x4 (AConfiguration register 1) + Object *acr2; // 0x8 (AConfiguration register 2) + Object *afrcr; // 0xC (AFRCR) + Object *aslotr; // 0x10 (ASlot register) + Object *aim; // 0x14 (AInterrupt mask register2) + Object *asr; // 0x18 (AStatus register) + Object *aclrfr; // 0x1C (AClear flag register) + Object *adr; // 0x20 (AData register) + } reg; + + struct { + + // BCR1 (BConfiguration register 1) bitfields. + struct { + Object *mode; // [0:1] Audio block mode + Object *prtcfg; // [2:3] Protocol configuration + Object *ds; // [5:7] Data size + Object *lsbfirst; // [8:8] Least significant bit first + Object *ckstr; // [9:9] Clock strobing edge + Object *syncen; // [10:11] Synchronization enable + Object *mono; // [12:12] Mono mode + Object *outdri; // [13:13] Output drive + Object *saiben; // [16:16] Audio block B enable + Object *dmaen; // [17:17] DMA enable + Object *nodiv; // [19:19] No divider + Object *mcjdiv; // [20:23] Master clock divider + } bcr1; + + // BCR2 (BConfiguration register 2) bitfields. + struct { + Object *fth; // [0:2] FIFO threshold + Object *fflus; // [3:3] FIFO flush + Object *tris; // [4:4] Tristate management on data line + Object *mute; // [5:5] Mute + Object *muteval; // [6:6] Mute value + Object *mutecn; // [7:12] Mute counter + Object *cpl; // [13:13] Complement bit + Object *comp; // [14:15] Companding mode + } bcr2; + + // BFRCR (BFRCR) bitfields. + struct { + Object *frl; // [0:7] Frame length + Object *fsall; // [8:14] Frame synchronization active level length + Object *fsdef; // [16:16] Frame synchronization definition + Object *fspol; // [17:17] Frame synchronization polarity + Object *fsoff; // [18:18] Frame synchronization offset + } bfrcr; + + // BSLOTR (BSlot register) bitfields. + struct { + Object *fboff; // [0:4] First bit offset + Object *slotsz; // [6:7] Slot size + Object *nbslot; // [8:11] Number of slots in an audio frame + Object *sloten; // [16:31] Slot enable + } bslotr; + + // BIM (BInterrupt mask register2) bitfields. + struct { + Object *ovrudrie; // [0:0] Overrun/underrun interrupt enable + Object *mutedet; // [1:1] Mute detection interrupt enable + Object *wckcfg; // [2:2] Wrong clock configuration interrupt enable + Object *freqie; // [3:3] FIFO request interrupt enable + Object *cnrdyie; // [4:4] Codec not ready interrupt enable + Object *afsdetie; // [5:5] Anticipated frame synchronization detection interrupt enable + Object *lfsdetie; // [6:6] Late frame synchronization detection interrupt enable + } bim; + + // BSR (BStatus register) bitfields. + struct { + Object *ovrudr; // [0:0] Overrun / underrun + Object *mutedet; // [1:1] Mute detection + Object *wckcfg; // [2:2] Wrong clock configuration flag + Object *freq; // [3:3] FIFO request + Object *cnrdy; // [4:4] Codec not ready + Object *afsdet; // [5:5] Anticipated frame synchronization detection + Object *lfsdet; // [6:6] Late frame synchronization detection + Object *flvl; // [16:18] FIFO level threshold + } bsr; + + // BCLRFR (BClear flag register) bitfields. + struct { + Object *ovrudr; // [0:0] Clear overrun / underrun + Object *mutedet; // [1:1] Mute detection flag + Object *wckcfg; // [2:2] Clear wrong clock configuration flag + Object *cnrdy; // [4:4] Clear codec not ready flag + Object *cafsdet; // [5:5] Clear anticipated frame synchronization detection flag + Object *lfsdet; // [6:6] Clear late frame synchronization detection flag + } bclrfr; + + // BDR (BData register) bitfields. + struct { + Object *data; // [0:31] Data + } bdr; + + // ACR1 (AConfiguration register 1) bitfields. + struct { + Object *mode; // [0:1] Audio block mode + Object *prtcfg; // [2:3] Protocol configuration + Object *ds; // [5:7] Data size + Object *lsbfirst; // [8:8] Least significant bit first + Object *ckstr; // [9:9] Clock strobing edge + Object *syncen; // [10:11] Synchronization enable + Object *mono; // [12:12] Mono mode + Object *outdri; // [13:13] Output drive + Object *saiaen; // [16:16] Audio block A enable + Object *dmaen; // [17:17] DMA enable + Object *nodiv; // [19:19] No divider + Object *mcjdiv; // [20:23] Master clock divider + } acr1; + + // ACR2 (AConfiguration register 2) bitfields. + struct { + Object *fth; // [0:2] FIFO threshold + Object *fflus; // [3:3] FIFO flush + Object *tris; // [4:4] Tristate management on data line + Object *mute; // [5:5] Mute + Object *muteval; // [6:6] Mute value + Object *mutecn; // [7:12] Mute counter + Object *cpl; // [13:13] Complement bit + Object *comp; // [14:15] Companding mode + } acr2; + + // AFRCR (AFRCR) bitfields. + struct { + Object *frl; // [0:7] Frame length + Object *fsall; // [8:14] Frame synchronization active level length + Object *fsdef; // [16:16] Frame synchronization definition + Object *fspol; // [17:17] Frame synchronization polarity + Object *fsoff; // [18:18] Frame synchronization offset + } afrcr; + + // ASLOTR (ASlot register) bitfields. + struct { + Object *fboff; // [0:4] First bit offset + Object *slotsz; // [6:7] Slot size + Object *nbslot; // [8:11] Number of slots in an audio frame + Object *sloten; // [16:31] Slot enable + } aslotr; + + // AIM (AInterrupt mask register2) bitfields. + struct { + Object *ovrudrie; // [0:0] Overrun/underrun interrupt enable + Object *mutedet; // [1:1] Mute detection interrupt enable + Object *wckcfg; // [2:2] Wrong clock configuration interrupt enable + Object *freqie; // [3:3] FIFO request interrupt enable + Object *cnrdyie; // [4:4] Codec not ready interrupt enable + Object *afsdetie; // [5:5] Anticipated frame synchronization detection interrupt enable + Object *lfsdet; // [6:6] Late frame synchronization detection interrupt enable + } aim; + + // ASR (AStatus register) bitfields. + struct { + Object *ovrudr; // [0:0] Overrun / underrun + Object *mutedet; // [1:1] Mute detection + Object *wckcfg; // [2:2] Wrong clock configuration flag. This bit is read only. + Object *freq; // [3:3] FIFO request + Object *cnrdy; // [4:4] Codec not ready + Object *afsdet; // [5:5] Anticipated frame synchronization detection + Object *lfsdet; // [6:6] Late frame synchronization detection + Object *flvl; // [16:18] FIFO level threshold + } asr; + + // ACLRFR (AClear flag register) bitfields. + struct { + Object *ovrudr; // [0:0] Clear overrun / underrun + Object *mutedet; // [1:1] Mute detection flag + Object *wckcfg; // [2:2] Clear wrong clock configuration flag + Object *cnrdy; // [4:4] Clear codec not ready flag + Object *cafsdet; // [5:5] Clear anticipated frame synchronization detection flag. + Object *lfsdet; // [6:6] Clear late frame synchronization detection flag + } aclrfr; + + // ADR (AData register) bitfields. + struct { + Object *data; // [0:31] Data + } adr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SAIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SAI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/sdio.c b/gnu-mcu-eclipse/devices/support/STM32F429x/sdio.c new file mode 100644 index 0000000000..6b2caea5e3 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/sdio.c @@ -0,0 +1,386 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_sdio_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.power = cm_object_get_child_by_name(obj, "POWER"); + state->u.f4.reg.clkcr = cm_object_get_child_by_name(obj, "CLKCR"); + state->u.f4.reg.arg = cm_object_get_child_by_name(obj, "ARG"); + state->u.f4.reg.cmd = cm_object_get_child_by_name(obj, "CMD"); + state->u.f4.reg.respcmd = cm_object_get_child_by_name(obj, "RESPCMD"); + state->u.f4.reg.resp1 = cm_object_get_child_by_name(obj, "RESP1"); + state->u.f4.reg.resp2 = cm_object_get_child_by_name(obj, "RESP2"); + state->u.f4.reg.resp3 = cm_object_get_child_by_name(obj, "RESP3"); + state->u.f4.reg.resp4 = cm_object_get_child_by_name(obj, "RESP4"); + state->u.f4.reg.dtimer = cm_object_get_child_by_name(obj, "DTIMER"); + state->u.f4.reg.dlen = cm_object_get_child_by_name(obj, "DLEN"); + state->u.f4.reg.dctrl = cm_object_get_child_by_name(obj, "DCTRL"); + state->u.f4.reg.dcount = cm_object_get_child_by_name(obj, "DCOUNT"); + state->u.f4.reg.sta = cm_object_get_child_by_name(obj, "STA"); + state->u.f4.reg.icr = cm_object_get_child_by_name(obj, "ICR"); + state->u.f4.reg.mask = cm_object_get_child_by_name(obj, "MASK"); + state->u.f4.reg.fifocnt = cm_object_get_child_by_name(obj, "FIFOCNT"); + state->u.f4.reg.fifo = cm_object_get_child_by_name(obj, "FIFO"); + + + // POWER bitfields. + state->u.f4.fld.power.pwrctrl = cm_object_get_child_by_name(state->u.f4.reg.power, "PWRCTRL"); + + // CLKCR bitfields. + state->u.f4.fld.clkcr.clkdiv = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "CLKDIV"); + state->u.f4.fld.clkcr.clken = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "CLKEN"); + state->u.f4.fld.clkcr.pwrsav = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "PWRSAV"); + state->u.f4.fld.clkcr.bypass = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "BYPASS"); + state->u.f4.fld.clkcr.widbus = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "WIDBUS"); + state->u.f4.fld.clkcr.negedge = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "NEGEDGE"); + state->u.f4.fld.clkcr.hwfc_en = cm_object_get_child_by_name(state->u.f4.reg.clkcr, "HWFC_EN"); + + // ARG bitfields. + state->u.f4.fld.arg.cmdarg = cm_object_get_child_by_name(state->u.f4.reg.arg, "CMDARG"); + + // CMD bitfields. + state->u.f4.fld.cmd.cmdindex = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CMDINDEX"); + state->u.f4.fld.cmd.waitresp = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITRESP"); + state->u.f4.fld.cmd.waitint = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITINT"); + state->u.f4.fld.cmd.waitpend = cm_object_get_child_by_name(state->u.f4.reg.cmd, "WAITPEND"); + state->u.f4.fld.cmd.cpsmen = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CPSMEN"); + state->u.f4.fld.cmd.sdiosuspend = cm_object_get_child_by_name(state->u.f4.reg.cmd, "SDIOSuspend"); + state->u.f4.fld.cmd.encmdcompl = cm_object_get_child_by_name(state->u.f4.reg.cmd, "ENCMDcompl"); + state->u.f4.fld.cmd.nien = cm_object_get_child_by_name(state->u.f4.reg.cmd, "nIEN"); + state->u.f4.fld.cmd.ce_atacmd = cm_object_get_child_by_name(state->u.f4.reg.cmd, "CE_ATACMD"); + + // RESPCMD bitfields. + state->u.f4.fld.respcmd.respcmd = cm_object_get_child_by_name(state->u.f4.reg.respcmd, "RESPCMD"); + + // RESP1 bitfields. + state->u.f4.fld.resp1.cardstatus1 = cm_object_get_child_by_name(state->u.f4.reg.resp1, "CARDSTATUS1"); + + // RESP2 bitfields. + state->u.f4.fld.resp2.cardstatus2 = cm_object_get_child_by_name(state->u.f4.reg.resp2, "CARDSTATUS2"); + + // RESP3 bitfields. + state->u.f4.fld.resp3.cardstatus3 = cm_object_get_child_by_name(state->u.f4.reg.resp3, "CARDSTATUS3"); + + // RESP4 bitfields. + state->u.f4.fld.resp4.cardstatus4 = cm_object_get_child_by_name(state->u.f4.reg.resp4, "CARDSTATUS4"); + + // DTIMER bitfields. + state->u.f4.fld.dtimer.datatime = cm_object_get_child_by_name(state->u.f4.reg.dtimer, "DATATIME"); + + // DLEN bitfields. + state->u.f4.fld.dlen.datalength = cm_object_get_child_by_name(state->u.f4.reg.dlen, "DATALENGTH"); + + // DCTRL bitfields. + state->u.f4.fld.dctrl.dten = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTEN"); + state->u.f4.fld.dctrl.dtdir = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTDIR"); + state->u.f4.fld.dctrl.dtmode = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DTMODE"); + state->u.f4.fld.dctrl.dmaen = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DMAEN"); + state->u.f4.fld.dctrl.dblocksize = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "DBLOCKSIZE"); + state->u.f4.fld.dctrl.rwstart = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWSTART"); + state->u.f4.fld.dctrl.rwstop = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWSTOP"); + state->u.f4.fld.dctrl.rwmod = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "RWMOD"); + state->u.f4.fld.dctrl.sdioen = cm_object_get_child_by_name(state->u.f4.reg.dctrl, "SDIOEN"); + + // DCOUNT bitfields. + state->u.f4.fld.dcount.datacount = cm_object_get_child_by_name(state->u.f4.reg.dcount, "DATACOUNT"); + + // STA bitfields. + state->u.f4.fld.sta.ccrcfail = cm_object_get_child_by_name(state->u.f4.reg.sta, "CCRCFAIL"); + state->u.f4.fld.sta.dcrcfail = cm_object_get_child_by_name(state->u.f4.reg.sta, "DCRCFAIL"); + state->u.f4.fld.sta.ctimeout = cm_object_get_child_by_name(state->u.f4.reg.sta, "CTIMEOUT"); + state->u.f4.fld.sta.dtimeout = cm_object_get_child_by_name(state->u.f4.reg.sta, "DTIMEOUT"); + state->u.f4.fld.sta.txunderr = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXUNDERR"); + state->u.f4.fld.sta.rxoverr = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXOVERR"); + state->u.f4.fld.sta.cmdrend = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDREND"); + state->u.f4.fld.sta.cmdsent = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDSENT"); + state->u.f4.fld.sta.dataend = cm_object_get_child_by_name(state->u.f4.reg.sta, "DATAEND"); + state->u.f4.fld.sta.stbiterr = cm_object_get_child_by_name(state->u.f4.reg.sta, "STBITERR"); + state->u.f4.fld.sta.dbckend = cm_object_get_child_by_name(state->u.f4.reg.sta, "DBCKEND"); + state->u.f4.fld.sta.cmdact = cm_object_get_child_by_name(state->u.f4.reg.sta, "CMDACT"); + state->u.f4.fld.sta.txact = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXACT"); + state->u.f4.fld.sta.rxact = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXACT"); + state->u.f4.fld.sta.txfifohe = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOHE"); + state->u.f4.fld.sta.rxfifohf = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOHF"); + state->u.f4.fld.sta.txfifof = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOF"); + state->u.f4.fld.sta.rxfifof = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOF"); + state->u.f4.fld.sta.txfifoe = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXFIFOE"); + state->u.f4.fld.sta.rxfifoe = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXFIFOE"); + state->u.f4.fld.sta.txdavl = cm_object_get_child_by_name(state->u.f4.reg.sta, "TXDAVL"); + state->u.f4.fld.sta.rxdavl = cm_object_get_child_by_name(state->u.f4.reg.sta, "RXDAVL"); + state->u.f4.fld.sta.sdioit = cm_object_get_child_by_name(state->u.f4.reg.sta, "SDIOIT"); + state->u.f4.fld.sta.ceataend = cm_object_get_child_by_name(state->u.f4.reg.sta, "CEATAEND"); + + // ICR bitfields. + state->u.f4.fld.icr.ccrcfailc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CCRCFAILC"); + state->u.f4.fld.icr.dcrcfailc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DCRCFAILC"); + state->u.f4.fld.icr.ctimeoutc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CTIMEOUTC"); + state->u.f4.fld.icr.dtimeoutc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DTIMEOUTC"); + state->u.f4.fld.icr.txunderrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "TXUNDERRC"); + state->u.f4.fld.icr.rxoverrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "RXOVERRC"); + state->u.f4.fld.icr.cmdrendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CMDRENDC"); + state->u.f4.fld.icr.cmdsentc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CMDSENTC"); + state->u.f4.fld.icr.dataendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DATAENDC"); + state->u.f4.fld.icr.stbiterrc = cm_object_get_child_by_name(state->u.f4.reg.icr, "STBITERRC"); + state->u.f4.fld.icr.dbckendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "DBCKENDC"); + state->u.f4.fld.icr.sdioitc = cm_object_get_child_by_name(state->u.f4.reg.icr, "SDIOITC"); + state->u.f4.fld.icr.ceataendc = cm_object_get_child_by_name(state->u.f4.reg.icr, "CEATAENDC"); + + // MASK bitfields. + state->u.f4.fld.mask.ccrcfailie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CCRCFAILIE"); + state->u.f4.fld.mask.dcrcfailie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DCRCFAILIE"); + state->u.f4.fld.mask.ctimeoutie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CTIMEOUTIE"); + state->u.f4.fld.mask.dtimeoutie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DTIMEOUTIE"); + state->u.f4.fld.mask.txunderrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXUNDERRIE"); + state->u.f4.fld.mask.rxoverrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXOVERRIE"); + state->u.f4.fld.mask.cmdrendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDRENDIE"); + state->u.f4.fld.mask.cmdsentie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDSENTIE"); + state->u.f4.fld.mask.dataendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DATAENDIE"); + state->u.f4.fld.mask.stbiterrie = cm_object_get_child_by_name(state->u.f4.reg.mask, "STBITERRIE"); + state->u.f4.fld.mask.dbckendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "DBCKENDIE"); + state->u.f4.fld.mask.cmdactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CMDACTIE"); + state->u.f4.fld.mask.txactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXACTIE"); + state->u.f4.fld.mask.rxactie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXACTIE"); + state->u.f4.fld.mask.txfifoheie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOHEIE"); + state->u.f4.fld.mask.rxfifohfie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOHFIE"); + state->u.f4.fld.mask.txfifofie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOFIE"); + state->u.f4.fld.mask.rxfifofie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOFIE"); + state->u.f4.fld.mask.txfifoeie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXFIFOEIE"); + state->u.f4.fld.mask.rxfifoeie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXFIFOEIE"); + state->u.f4.fld.mask.txdavlie = cm_object_get_child_by_name(state->u.f4.reg.mask, "TXDAVLIE"); + state->u.f4.fld.mask.rxdavlie = cm_object_get_child_by_name(state->u.f4.reg.mask, "RXDAVLIE"); + state->u.f4.fld.mask.sdioitie = cm_object_get_child_by_name(state->u.f4.reg.mask, "SDIOITIE"); + state->u.f4.fld.mask.ceataendie = cm_object_get_child_by_name(state->u.f4.reg.mask, "CEATAENDIE"); + + // FIFOCNT bitfields. + state->u.f4.fld.fifocnt.fifocount = cm_object_get_child_by_name(state->u.f4.reg.fifocnt, "FIFOCOUNT"); + + // FIFO bitfields. + state->u.f4.fld.fifo.fifodata = cm_object_get_child_by_name(state->u.f4.reg.fifo, "FIFOData"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_sdio_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_sdio_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_sdio_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_sdio_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SDIOState *state = STM32_SDIO_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_sdio_is_enabled(Object *obj) +{ + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_sdio_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SDIOState *state = STM32_SDIO_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_sdio_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SDIO)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SDIOState *state = STM32_SDIO_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SDIO"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_sdio_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sdio_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_sdio_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_sdio_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_sdio_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SDIOEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_sdio_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SDIO); +} + +static void stm32_sdio_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_sdio_reset_callback; + dc->realize = stm32_sdio_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_sdio_is_enabled; +} + +static const TypeInfo stm32_sdio_type_info = { + .name = TYPE_STM32_SDIO, + .parent = TYPE_STM32_SDIO_PARENT, + .instance_init = stm32_sdio_instance_init_callback, + .instance_size = sizeof(STM32SDIOState), + .class_init = stm32_sdio_class_init_callback, + .class_size = sizeof(STM32SDIOClass) }; + +static void stm32_sdio_register_types(void) +{ + type_register_static(&stm32_sdio_type_info); +} + +type_init(stm32_sdio_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/sdio.h b/gnu-mcu-eclipse/devices/support/STM32F429x/sdio.h new file mode 100644 index 0000000000..b50b00c946 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/sdio.h @@ -0,0 +1,287 @@ +/* + * STM32 - SDIO (Secure digital input/output interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SDIO_H_ +#define STM32_SDIO_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SDIO DEVICE_PATH_STM32 "SDIO" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SDIO TYPE_STM32_PREFIX "sdio" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SDIO_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SDIOParentClass; +typedef PeripheralState STM32SDIOParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SDIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SDIOClass, (obj), TYPE_STM32_SDIO) +#define STM32_SDIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SDIOClass, (klass), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentClass parent_class; + // public: + + // None, so far. +} STM32SDIOClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SDIO_STATE(obj) \ + OBJECT_CHECK(STM32SDIOState, (obj), TYPE_STM32_SDIO) + +typedef struct { + // private: + STM32SDIOParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SDIO (Secure digital input/output interface) registers. + struct { + Object *power; // 0x0 (Power control register) + Object *clkcr; // 0x4 (SDI clock control register) + Object *arg; // 0x8 (Argument register) + Object *cmd; // 0xC (Command register) + Object *respcmd; // 0x10 (Command response register) + Object *resp1; // 0x14 (Response 1..4 register) + Object *resp2; // 0x18 (Response 1..4 register) + Object *resp3; // 0x1C (Response 1..4 register) + Object *resp4; // 0x20 (Response 1..4 register) + Object *dtimer; // 0x24 (Data timer register) + Object *dlen; // 0x28 (Data length register) + Object *dctrl; // 0x2C (Data control register) + Object *dcount; // 0x30 (Data counter register) + Object *sta; // 0x34 (Status register) + Object *icr; // 0x38 (Interrupt clear register) + Object *mask; // 0x3C (Mask register) + Object *fifocnt; // 0x48 (FIFO counter register) + Object *fifo; // 0x80 (Data FIFO register) + } reg; + + struct { + + // POWER (Power control register) bitfields. + struct { + Object *pwrctrl; // [0:1] PWRCTRL + } power; + + // CLKCR (SDI clock control register) bitfields. + struct { + Object *clkdiv; // [0:7] Clock divide factor + Object *clken; // [8:8] Clock enable bit + Object *pwrsav; // [9:9] Power saving configuration bit + Object *bypass; // [10:10] Clock divider bypass enable bit + Object *widbus; // [11:12] Wide bus mode enable bit + Object *negedge; // [13:13] SDIO_CK dephasing selection bit + Object *hwfc_en; // [14:14] HW Flow Control enable + } clkcr; + + // ARG (Argument register) bitfields. + struct { + Object *cmdarg; // [0:31] Command argument + } arg; + + // CMD (Command register) bitfields. + struct { + Object *cmdindex; // [0:5] Command index + Object *waitresp; // [6:7] Wait for response bits + Object *waitint; // [8:8] CPSM waits for interrupt request + Object *waitpend; // [9:9] CPSM Waits for ends of data transfer (CmdPend internal signal). + Object *cpsmen; // [10:10] Command path state machine (CPSM) Enable bit + Object *sdiosuspend; // [11:11] SD I/O suspend command + Object *encmdcompl; // [12:12] Enable CMD completion + Object *nien; // [13:13] Not Interrupt Enable + Object *ce_atacmd; // [14:14] CE-ATA command + } cmd; + + // RESPCMD (Command response register) bitfields. + struct { + Object *respcmd; // [0:5] Response command index + } respcmd; + + // RESP1 (Response 1..4 register) bitfields. + struct { + Object *cardstatus1; // [0:31] See Table 132. + } resp1; + + // RESP2 (Response 1..4 register) bitfields. + struct { + Object *cardstatus2; // [0:31] See Table 132. + } resp2; + + // RESP3 (Response 1..4 register) bitfields. + struct { + Object *cardstatus3; // [0:31] See Table 132. + } resp3; + + // RESP4 (Response 1..4 register) bitfields. + struct { + Object *cardstatus4; // [0:31] See Table 132. + } resp4; + + // DTIMER (Data timer register) bitfields. + struct { + Object *datatime; // [0:31] Data timeout period + } dtimer; + + // DLEN (Data length register) bitfields. + struct { + Object *datalength; // [0:24] Data length value + } dlen; + + // DCTRL (Data control register) bitfields. + struct { + Object *dten; // [0:0] DTEN + Object *dtdir; // [1:1] Data transfer direction selection + Object *dtmode; // [2:2] Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + Object *dmaen; // [3:3] DMA enable bit + Object *dblocksize; // [4:7] Data block size + Object *rwstart; // [8:8] Read wait start + Object *rwstop; // [9:9] Read wait stop + Object *rwmod; // [10:10] Read wait mode + Object *sdioen; // [11:11] SD I/O enable functions + } dctrl; + + // DCOUNT (Data counter register) bitfields. + struct { + Object *datacount; // [0:24] Data count value + } dcount; + + // STA (Status register) bitfields. + struct { + Object *ccrcfail; // [0:0] Command response received (CRC check failed) + Object *dcrcfail; // [1:1] Data block sent/received (CRC check failed) + Object *ctimeout; // [2:2] Command response timeout + Object *dtimeout; // [3:3] Data timeout + Object *txunderr; // [4:4] Transmit FIFO underrun error + Object *rxoverr; // [5:5] Received FIFO overrun error + Object *cmdrend; // [6:6] Command response received (CRC check passed) + Object *cmdsent; // [7:7] Command sent (no response required) + Object *dataend; // [8:8] Data end (data counter, SDIDCOUNT, is zero) + Object *stbiterr; // [9:9] Start bit not detected on all data signals in wide bus mode + Object *dbckend; // [10:10] Data block sent/received (CRC check passed) + Object *cmdact; // [11:11] Command transfer in progress + Object *txact; // [12:12] Data transmit in progress + Object *rxact; // [13:13] Data receive in progress + Object *txfifohe; // [14:14] Transmit FIFO half empty: at least 8 words can be written into the FIFO + Object *rxfifohf; // [15:15] Receive FIFO half full: there are at least 8 words in the FIFO + Object *txfifof; // [16:16] Transmit FIFO full + Object *rxfifof; // [17:17] Receive FIFO full + Object *txfifoe; // [18:18] Transmit FIFO empty + Object *rxfifoe; // [19:19] Receive FIFO empty + Object *txdavl; // [20:20] Data available in transmit FIFO + Object *rxdavl; // [21:21] Data available in receive FIFO + Object *sdioit; // [22:22] SDIO interrupt received + Object *ceataend; // [23:23] CE-ATA command completion signal received for CMD61 + } sta; + + // ICR (Interrupt clear register) bitfields. + struct { + Object *ccrcfailc; // [0:0] CCRCFAIL flag clear bit + Object *dcrcfailc; // [1:1] DCRCFAIL flag clear bit + Object *ctimeoutc; // [2:2] CTIMEOUT flag clear bit + Object *dtimeoutc; // [3:3] DTIMEOUT flag clear bit + Object *txunderrc; // [4:4] TXUNDERR flag clear bit + Object *rxoverrc; // [5:5] RXOVERR flag clear bit + Object *cmdrendc; // [6:6] CMDREND flag clear bit + Object *cmdsentc; // [7:7] CMDSENT flag clear bit + Object *dataendc; // [8:8] DATAEND flag clear bit + Object *stbiterrc; // [9:9] STBITERR flag clear bit + Object *dbckendc; // [10:10] DBCKEND flag clear bit + Object *sdioitc; // [22:22] SDIOIT flag clear bit + Object *ceataendc; // [23:23] CEATAEND flag clear bit + } icr; + + // MASK (Mask register) bitfields. + struct { + Object *ccrcfailie; // [0:0] Command CRC fail interrupt enable + Object *dcrcfailie; // [1:1] Data CRC fail interrupt enable + Object *ctimeoutie; // [2:2] Command timeout interrupt enable + Object *dtimeoutie; // [3:3] Data timeout interrupt enable + Object *txunderrie; // [4:4] Tx FIFO underrun error interrupt enable + Object *rxoverrie; // [5:5] Rx FIFO overrun error interrupt enable + Object *cmdrendie; // [6:6] Command response received interrupt enable + Object *cmdsentie; // [7:7] Command sent interrupt enable + Object *dataendie; // [8:8] Data end interrupt enable + Object *stbiterrie; // [9:9] Start bit error interrupt enable + Object *dbckendie; // [10:10] Data block end interrupt enable + Object *cmdactie; // [11:11] Command acting interrupt enable + Object *txactie; // [12:12] Data transmit acting interrupt enable + Object *rxactie; // [13:13] Data receive acting interrupt enable + Object *txfifoheie; // [14:14] Tx FIFO half empty interrupt enable + Object *rxfifohfie; // [15:15] Rx FIFO half full interrupt enable + Object *txfifofie; // [16:16] Tx FIFO full interrupt enable + Object *rxfifofie; // [17:17] Rx FIFO full interrupt enable + Object *txfifoeie; // [18:18] Tx FIFO empty interrupt enable + Object *rxfifoeie; // [19:19] Rx FIFO empty interrupt enable + Object *txdavlie; // [20:20] Data available in Tx FIFO interrupt enable + Object *rxdavlie; // [21:21] Data available in Rx FIFO interrupt enable + Object *sdioitie; // [22:22] SDIO mode interrupt received interrupt enable + Object *ceataendie; // [23:23] CE-ATA command completion signal received interrupt enable + } mask; + + // FIFOCNT (FIFO counter register) bitfields. + struct { + Object *fifocount; // [0:23] Remaining number of words to be written to or read from the FIFO. + } fifocnt; + + // FIFO (Data FIFO register) bitfields. + struct { + Object *fifodata; // [0:31] Receive and transmit FIFO data + } fifo; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SDIOState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SDIO_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/spi1.c b/gnu-mcu-eclipse/devices/support/STM32F429x/spi1.c new file mode 100644 index 0000000000..2cc9be1aa8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/spi1.c @@ -0,0 +1,311 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_spi_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.crcpr = cm_object_get_child_by_name(obj, "CRCPR"); + state->u.f4.reg.rxcrcr = cm_object_get_child_by_name(obj, "RXCRCR"); + state->u.f4.reg.txcrcr = cm_object_get_child_by_name(obj, "TXCRCR"); + state->u.f4.reg.i2scfgr = cm_object_get_child_by_name(obj, "I2SCFGR"); + state->u.f4.reg.i2spr = cm_object_get_child_by_name(obj, "I2SPR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cpha = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CPHA"); + state->u.f4.fld.cr1.cpol = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CPOL"); + state->u.f4.fld.cr1.mstr = cm_object_get_child_by_name(state->u.f4.reg.cr1, "MSTR"); + state->u.f4.fld.cr1.br = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BR"); + state->u.f4.fld.cr1.spe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SPE"); + state->u.f4.fld.cr1.lsbfirst = cm_object_get_child_by_name(state->u.f4.reg.cr1, "LSBFIRST"); + state->u.f4.fld.cr1.ssi = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SSI"); + state->u.f4.fld.cr1.ssm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SSM"); + state->u.f4.fld.cr1.rxonly = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXONLY"); + state->u.f4.fld.cr1.dff = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DFF"); + state->u.f4.fld.cr1.crcnext = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CRCNEXT"); + state->u.f4.fld.cr1.crcen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CRCEN"); + state->u.f4.fld.cr1.bidioe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BIDIOE"); + state->u.f4.fld.cr1.bidimode = cm_object_get_child_by_name(state->u.f4.reg.cr1, "BIDIMODE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.rxdmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "RXDMAEN"); + state->u.f4.fld.cr2.txdmaen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TXDMAEN"); + state->u.f4.fld.cr2.ssoe = cm_object_get_child_by_name(state->u.f4.reg.cr2, "SSOE"); + state->u.f4.fld.cr2.frf = cm_object_get_child_by_name(state->u.f4.reg.cr2, "FRF"); + state->u.f4.fld.cr2.errie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ERRIE"); + state->u.f4.fld.cr2.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "RXNEIE"); + state->u.f4.fld.cr2.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TXEIE"); + + // SR bitfields. + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.chside = cm_object_get_child_by_name(state->u.f4.reg.sr, "CHSIDE"); + state->u.f4.fld.sr.udr = cm_object_get_child_by_name(state->u.f4.reg.sr, "UDR"); + state->u.f4.fld.sr.crcerr = cm_object_get_child_by_name(state->u.f4.reg.sr, "CRCERR"); + state->u.f4.fld.sr.modf = cm_object_get_child_by_name(state->u.f4.reg.sr, "MODF"); + state->u.f4.fld.sr.ovr = cm_object_get_child_by_name(state->u.f4.reg.sr, "OVR"); + state->u.f4.fld.sr.bsy = cm_object_get_child_by_name(state->u.f4.reg.sr, "BSY"); + state->u.f4.fld.sr.tifrfe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIFRFE"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // CRCPR bitfields. + state->u.f4.fld.crcpr.crcpoly = cm_object_get_child_by_name(state->u.f4.reg.crcpr, "CRCPOLY"); + + // RXCRCR bitfields. + state->u.f4.fld.rxcrcr.rxcrc = cm_object_get_child_by_name(state->u.f4.reg.rxcrcr, "RxCRC"); + + // TXCRCR bitfields. + state->u.f4.fld.txcrcr.txcrc = cm_object_get_child_by_name(state->u.f4.reg.txcrcr, "TxCRC"); + + // I2SCFGR bitfields. + state->u.f4.fld.i2scfgr.chlen = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "CHLEN"); + state->u.f4.fld.i2scfgr.datlen = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "DATLEN"); + state->u.f4.fld.i2scfgr.ckpol = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "CKPOL"); + state->u.f4.fld.i2scfgr.i2sstd = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SSTD"); + state->u.f4.fld.i2scfgr.pcmsync = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "PCMSYNC"); + state->u.f4.fld.i2scfgr.i2scfg = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SCFG"); + state->u.f4.fld.i2scfgr.i2se = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SE"); + state->u.f4.fld.i2scfgr.i2smod = cm_object_get_child_by_name(state->u.f4.reg.i2scfgr, "I2SMOD"); + + // I2SPR bitfields. + state->u.f4.fld.i2spr.i2sdiv = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "I2SDIV"); + state->u.f4.fld.i2spr.odd = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "ODD"); + state->u.f4.fld.i2spr.mckoe = cm_object_get_child_by_name(state->u.f4.reg.i2spr, "MCKOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_spi_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_spi_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_spi_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_spi_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SPIState *state = STM32_SPI_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_spi_is_enabled(Object *obj) +{ + STM32SPIState *state = STM32_SPI_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_spi_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SPIState *state = STM32_SPI_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_SPI_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_spi_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SPI)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SPIState *state = STM32_SPI_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SPI"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_spi_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_spi_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_spi_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_spi_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_spi_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SPI%dEN", + 1 + state->port_index - STM32_PORT_SPI1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_spi_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SPI); +} + +static void stm32_spi_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_spi_reset_callback; + dc->realize = stm32_spi_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_spi_is_enabled; +} + +static const TypeInfo stm32_spi_type_info = { + .name = TYPE_STM32_SPI, + .parent = TYPE_STM32_SPI_PARENT, + .instance_init = stm32_spi_instance_init_callback, + .instance_size = sizeof(STM32SPIState), + .class_init = stm32_spi_class_init_callback, + .class_size = sizeof(STM32SPIClass) }; + +static void stm32_spi_register_types(void) +{ + type_register_static(&stm32_spi_type_info); +} + +type_init(stm32_spi_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/spi1.h b/gnu-mcu-eclipse/devices/support/STM32F429x/spi1.h new file mode 100644 index 0000000000..29194debcd --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/spi1.h @@ -0,0 +1,201 @@ +/* + * STM32 - SPI (Serial peripheral interface) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SPI_H_ +#define STM32_SPI_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SPI DEVICE_PATH_STM32 "SPI" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_SPI1, + STM32_PORT_SPI2, + STM32_PORT_SPI3, + STM32_PORT_SPI_UNDEFINED = 0xFF, +} stm32_spi_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SPI TYPE_STM32_PREFIX "spi" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SPI_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SPIParentClass; +typedef PeripheralState STM32SPIParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SPI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SPIClass, (obj), TYPE_STM32_SPI) +#define STM32_SPI_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SPIClass, (klass), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentClass parent_class; + // public: + + // None, so far. +} STM32SPIClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SPI_STATE(obj) \ + OBJECT_CHECK(STM32SPIState, (obj), TYPE_STM32_SPI) + +typedef struct { + // private: + STM32SPIParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_spi_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SPI (Serial peripheral interface) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *sr; // 0x8 (Status register) + Object *dr; // 0xC (Data register) + Object *crcpr; // 0x10 (CRC polynomial register) + Object *rxcrcr; // 0x14 (RX CRC register) + Object *txcrcr; // 0x18 (TX CRC register) + Object *i2scfgr; // 0x1C (I2S configuration register) + Object *i2spr; // 0x20 (I2S prescaler register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cpha; // [0:0] Clock phase + Object *cpol; // [1:1] Clock polarity + Object *mstr; // [2:2] Master selection + Object *br; // [3:5] Baud rate control + Object *spe; // [6:6] SPI enable + Object *lsbfirst; // [7:7] Frame format + Object *ssi; // [8:8] Internal slave select + Object *ssm; // [9:9] Software slave management + Object *rxonly; // [10:10] Receive only + Object *dff; // [11:11] Data frame format + Object *crcnext; // [12:12] CRC transfer next + Object *crcen; // [13:13] Hardware CRC calculation enable + Object *bidioe; // [14:14] Output enable in bidirectional mode + Object *bidimode; // [15:15] Bidirectional data mode enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *rxdmaen; // [0:0] Rx buffer DMA enable + Object *txdmaen; // [1:1] Tx buffer DMA enable + Object *ssoe; // [2:2] SS output enable + Object *frf; // [4:4] Frame format + Object *errie; // [5:5] Error interrupt enable + Object *rxneie; // [6:6] RX buffer not empty interrupt enable + Object *txeie; // [7:7] Tx buffer empty interrupt enable + } cr2; + + // SR (Status register) bitfields. + struct { + Object *rxne; // [0:0] Receive buffer not empty + Object *txe; // [1:1] Transmit buffer empty + Object *chside; // [2:2] Channel side + Object *udr; // [3:3] Underrun flag + Object *crcerr; // [4:4] CRC error flag + Object *modf; // [5:5] Mode fault + Object *ovr; // [6:6] Overrun flag + Object *bsy; // [7:7] Busy flag + Object *tifrfe; // [8:8] TI frame format error + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:15] Data register + } dr; + + // CRCPR (CRC polynomial register) bitfields. + struct { + Object *crcpoly; // [0:15] CRC polynomial register + } crcpr; + + // RXCRCR (RX CRC register) bitfields. + struct { + Object *rxcrc; // [0:15] Rx CRC register + } rxcrcr; + + // TXCRCR (TX CRC register) bitfields. + struct { + Object *txcrc; // [0:15] Tx CRC register + } txcrcr; + + // I2SCFGR (I2S configuration register) bitfields. + struct { + Object *chlen; // [0:0] Channel length (number of bits per audio channel) + Object *datlen; // [1:2] Data length to be transferred + Object *ckpol; // [3:3] Steady state clock polarity + Object *i2sstd; // [4:5] I2S standard selection + Object *pcmsync; // [7:7] PCM frame synchronization + Object *i2scfg; // [8:9] I2S configuration mode + Object *i2se; // [10:10] I2S Enable + Object *i2smod; // [11:11] I2S mode selection + } i2scfgr; + + // I2SPR (I2S prescaler register) bitfields. + struct { + Object *i2sdiv; // [0:7] I2S Linear prescaler + Object *odd; // [8:8] Odd factor for the prescaler + Object *mckoe; // [9:9] Master clock output enable + } i2spr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SPIState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SPI_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/syscfg.c b/gnu-mcu-eclipse/devices/support/STM32F429x/syscfg.c new file mode 100644 index 0000000000..8701dfa313 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/syscfg.c @@ -0,0 +1,280 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_syscfg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.memrm = cm_object_get_child_by_name(obj, "MEMRM"); + state->u.f4.reg.pmc = cm_object_get_child_by_name(obj, "PMC"); + state->u.f4.reg.exticr1 = cm_object_get_child_by_name(obj, "EXTICR1"); + state->u.f4.reg.exticr2 = cm_object_get_child_by_name(obj, "EXTICR2"); + state->u.f4.reg.exticr3 = cm_object_get_child_by_name(obj, "EXTICR3"); + state->u.f4.reg.exticr4 = cm_object_get_child_by_name(obj, "EXTICR4"); + state->u.f4.reg.cmpcr = cm_object_get_child_by_name(obj, "CMPCR"); + + + // MEMRM bitfields. + state->u.f4.fld.memrm.mem_mode = cm_object_get_child_by_name(state->u.f4.reg.memrm, "MEM_MODE"); + state->u.f4.fld.memrm.fb_mode = cm_object_get_child_by_name(state->u.f4.reg.memrm, "FB_MODE"); + state->u.f4.fld.memrm.swp_fmc = cm_object_get_child_by_name(state->u.f4.reg.memrm, "SWP_FMC"); + + // PMC bitfields. + state->u.f4.fld.pmc.adc1dc2 = cm_object_get_child_by_name(state->u.f4.reg.pmc, "ADC1DC2"); + state->u.f4.fld.pmc.adc2dc2 = cm_object_get_child_by_name(state->u.f4.reg.pmc, "ADC2DC2"); + state->u.f4.fld.pmc.adc3dc2 = cm_object_get_child_by_name(state->u.f4.reg.pmc, "ADC3DC2"); + state->u.f4.fld.pmc.mii_rmii_sel = cm_object_get_child_by_name(state->u.f4.reg.pmc, "MII_RMII_SEL"); + + // EXTICR1 bitfields. + state->u.f4.fld.exticr1.exti0 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI0"); + state->u.f4.fld.exticr1.exti1 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI1"); + state->u.f4.fld.exticr1.exti2 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI2"); + state->u.f4.fld.exticr1.exti3 = cm_object_get_child_by_name(state->u.f4.reg.exticr1, "EXTI3"); + + // EXTICR2 bitfields. + state->u.f4.fld.exticr2.exti4 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI4"); + state->u.f4.fld.exticr2.exti5 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI5"); + state->u.f4.fld.exticr2.exti6 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI6"); + state->u.f4.fld.exticr2.exti7 = cm_object_get_child_by_name(state->u.f4.reg.exticr2, "EXTI7"); + + // EXTICR3 bitfields. + state->u.f4.fld.exticr3.exti8 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI8"); + state->u.f4.fld.exticr3.exti9 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI9"); + state->u.f4.fld.exticr3.exti10 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI10"); + state->u.f4.fld.exticr3.exti11 = cm_object_get_child_by_name(state->u.f4.reg.exticr3, "EXTI11"); + + // EXTICR4 bitfields. + state->u.f4.fld.exticr4.exti12 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI12"); + state->u.f4.fld.exticr4.exti13 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI13"); + state->u.f4.fld.exticr4.exti14 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI14"); + state->u.f4.fld.exticr4.exti15 = cm_object_get_child_by_name(state->u.f4.reg.exticr4, "EXTI15"); + + // CMPCR bitfields. + state->u.f4.fld.cmpcr.cmp_pd = cm_object_get_child_by_name(state->u.f4.reg.cmpcr, "CMP_PD"); + state->u.f4.fld.cmpcr.ready = cm_object_get_child_by_name(state->u.f4.reg.cmpcr, "READY"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_syscfg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_syscfg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_syscfg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_syscfg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_syscfg_is_enabled(Object *obj) +{ + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_syscfg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_syscfg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_SYSCFG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32SYSCFGState *state = STM32_SYSCFG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "SYSCFG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_syscfg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_syscfg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_syscfg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_syscfg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_syscfg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/SYSCFGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_syscfg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_SYSCFG); +} + +static void stm32_syscfg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_syscfg_reset_callback; + dc->realize = stm32_syscfg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_syscfg_is_enabled; +} + +static const TypeInfo stm32_syscfg_type_info = { + .name = TYPE_STM32_SYSCFG, + .parent = TYPE_STM32_SYSCFG_PARENT, + .instance_init = stm32_syscfg_instance_init_callback, + .instance_size = sizeof(STM32SYSCFGState), + .class_init = stm32_syscfg_class_init_callback, + .class_size = sizeof(STM32SYSCFGClass) }; + +static void stm32_syscfg_register_types(void) +{ + type_register_static(&stm32_syscfg_type_info); +} + +type_init(stm32_syscfg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/syscfg.h b/gnu-mcu-eclipse/devices/support/STM32F429x/syscfg.h new file mode 100644 index 0000000000..5c1a460ba8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/syscfg.h @@ -0,0 +1,159 @@ +/* + * STM32 - SYSCFG (System configuration controller) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_SYSCFG_H_ +#define STM32_SYSCFG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_SYSCFG DEVICE_PATH_STM32 "SYSCFG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_SYSCFG TYPE_STM32_PREFIX "syscfg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_SYSCFG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32SYSCFGParentClass; +typedef PeripheralState STM32SYSCFGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_SYSCFG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32SYSCFGClass, (obj), TYPE_STM32_SYSCFG) +#define STM32_SYSCFG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32SYSCFGClass, (klass), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentClass parent_class; + // public: + + // None, so far. +} STM32SYSCFGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_SYSCFG_STATE(obj) \ + OBJECT_CHECK(STM32SYSCFGState, (obj), TYPE_STM32_SYSCFG) + +typedef struct { + // private: + STM32SYSCFGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 SYSCFG (System configuration controller) registers. + struct { + Object *memrm; // 0x0 (Memory remap register) + Object *pmc; // 0x4 (Peripheral mode configuration register) + Object *exticr1; // 0x8 (External interrupt configuration register 1) + Object *exticr2; // 0xC (External interrupt configuration register 2) + Object *exticr3; // 0x10 (External interrupt configuration register 3) + Object *exticr4; // 0x14 (External interrupt configuration register 4) + Object *cmpcr; // 0x20 (Compensation cell control register) + } reg; + + struct { + + // MEMRM (Memory remap register) bitfields. + struct { + Object *mem_mode; // [0:2] Memory mapping selection + Object *fb_mode; // [8:8] Flash bank mode selection + Object *swp_fmc; // [10:11] FMC memory mapping swap + } memrm; + + // PMC (Peripheral mode configuration register) bitfields. + struct { + Object *adc1dc2; // [16:16] ADC1DC2 + Object *adc2dc2; // [17:17] ADC2DC2 + Object *adc3dc2; // [18:18] ADC3DC2 + Object *mii_rmii_sel; // [23:23] Ethernet PHY interface selection + } pmc; + + // EXTICR1 (External interrupt configuration register 1) bitfields. + struct { + Object *exti0; // [0:3] EXTI x configuration (x = 0 to 3) + Object *exti1; // [4:7] EXTI x configuration (x = 0 to 3) + Object *exti2; // [8:11] EXTI x configuration (x = 0 to 3) + Object *exti3; // [12:15] EXTI x configuration (x = 0 to 3) + } exticr1; + + // EXTICR2 (External interrupt configuration register 2) bitfields. + struct { + Object *exti4; // [0:3] EXTI x configuration (x = 4 to 7) + Object *exti5; // [4:7] EXTI x configuration (x = 4 to 7) + Object *exti6; // [8:11] EXTI x configuration (x = 4 to 7) + Object *exti7; // [12:15] EXTI x configuration (x = 4 to 7) + } exticr2; + + // EXTICR3 (External interrupt configuration register 3) bitfields. + struct { + Object *exti8; // [0:3] EXTI x configuration (x = 8 to 11) + Object *exti9; // [4:7] EXTI x configuration (x = 8 to 11) + Object *exti10; // [8:11] EXTI10 + Object *exti11; // [12:15] EXTI x configuration (x = 8 to 11) + } exticr3; + + // EXTICR4 (External interrupt configuration register 4) bitfields. + struct { + Object *exti12; // [0:3] EXTI x configuration (x = 12 to 15) + Object *exti13; // [4:7] EXTI x configuration (x = 12 to 15) + Object *exti14; // [8:11] EXTI x configuration (x = 12 to 15) + Object *exti15; // [12:15] EXTI x configuration (x = 12 to 15) + } exticr4; + + // CMPCR (Compensation cell control register) bitfields. + struct { + Object *cmp_pd; // [0:0] Compensation cell power-down + Object *ready; // [8:8] READY + } cmpcr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32SYSCFGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_SYSCFG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim1.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim1.c new file mode 100644 index 0000000000..25a7c61cfe --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim1.c @@ -0,0 +1,427 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim1_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.rcr = cm_object_get_child_by_name(obj, "RCR"); + state->u.f4.reg.bdtr = cm_object_get_child_by_name(obj, "BDTR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccpc = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCPC"); + state->u.f4.fld.cr2.ccus = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCUS"); + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + state->u.f4.fld.cr2.ois1 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS1"); + state->u.f4.fld.cr2.ois1n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS1N"); + state->u.f4.fld.cr2.ois2 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS2"); + state->u.f4.fld.cr2.ois2n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS2N"); + state->u.f4.fld.cr2.ois3 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS3"); + state->u.f4.fld.cr2.ois3n = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS3N"); + state->u.f4.fld.cr2.ois4 = cm_object_get_child_by_name(state->u.f4.reg.cr2, "OIS4"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.comie = cm_object_get_child_by_name(state->u.f4.reg.dier, "COMIE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.bie = cm_object_get_child_by_name(state->u.f4.reg.dier, "BIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.comde = cm_object_get_child_by_name(state->u.f4.reg.dier, "COMDE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.comif = cm_object_get_child_by_name(state->u.f4.reg.sr, "COMIF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.bif = cm_object_get_child_by_name(state->u.f4.reg.sr, "BIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.comg = cm_object_get_child_by_name(state->u.f4.reg.egr, "COMG"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + state->u.f4.fld.egr.bg = cm_object_get_child_by_name(state->u.f4.reg.egr, "BG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.oc4ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NE"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NE"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3ne = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NE"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3 = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4 = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // RCR bitfields. + state->u.f4.fld.rcr.rep = cm_object_get_child_by_name(state->u.f4.reg.rcr, "REP"); + + // BDTR bitfields. + state->u.f4.fld.bdtr.dtg = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "DTG"); + state->u.f4.fld.bdtr.lock = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "LOCK"); + state->u.f4.fld.bdtr.ossi = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "OSSI"); + state->u.f4.fld.bdtr.ossr = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "OSSR"); + state->u.f4.fld.bdtr.bke = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "BKE"); + state->u.f4.fld.bdtr.bkp = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "BKP"); + state->u.f4.fld.bdtr.aoe = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "AOE"); + state->u.f4.fld.bdtr.moe = cm_object_get_child_by_name(state->u.f4.reg.bdtr, "MOE"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim1_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim1_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim1_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim1_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM1State *state = STM32_TIM1_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim1_is_enabled(Object *obj) +{ + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim1_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM1State *state = STM32_TIM1_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim1_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM1)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM1State *state = STM32_TIM1_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM1"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim1_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim1_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim1_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim1_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim1_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM1EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim1_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM1); +} + +static void stm32_tim1_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim1_reset_callback; + dc->realize = stm32_tim1_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim1_is_enabled; +} + +static const TypeInfo stm32_tim1_type_info = { + .name = TYPE_STM32_TIM1, + .parent = TYPE_STM32_TIM1_PARENT, + .instance_init = stm32_tim1_instance_init_callback, + .instance_size = sizeof(STM32TIM1State), + .class_init = stm32_tim1_class_init_callback, + .class_size = sizeof(STM32TIM1Class) }; + +static void stm32_tim1_register_types(void) +{ + type_register_static(&stm32_tim1_type_info); +} + +type_init(stm32_tim1_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim1.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim1.h new file mode 100644 index 0000000000..de5c1bbab8 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim1.h @@ -0,0 +1,336 @@ +/* + * STM32 - TIM1 (Advanced-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM1_H_ +#define STM32_TIM1_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM1 DEVICE_PATH_STM32 "TIM1" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM1 TYPE_STM32_PREFIX "tim1" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM1_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM1ParentClass; +typedef PeripheralState STM32TIM1ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM1_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM1Class, (obj), TYPE_STM32_TIM1) +#define STM32_TIM1_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM1Class, (klass), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM1Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM1_STATE(obj) \ + OBJECT_CHECK(STM32TIM1State, (obj), TYPE_STM32_TIM1) + +typedef struct { + // private: + STM32TIM1ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM1 (Advanced-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *rcr; // 0x30 (Repetition counter register) + Object *bdtr; // 0x44 (Break and dead-time register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccpc; // [0:0] Capture/compare preloaded control + Object *ccus; // [2:2] Capture/compare control update selection + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + Object *ois1; // [8:8] Output Idle state 1 + Object *ois1n; // [9:9] Output Idle state 1 + Object *ois2; // [10:10] Output Idle state 2 + Object *ois2n; // [11:11] Output Idle state 2 + Object *ois3; // [12:12] Output Idle state 3 + Object *ois3n; // [13:13] Output Idle state 3 + Object *ois4; // [14:14] Output Idle state 4 + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *comie; // [5:5] COM interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *bie; // [7:7] Break interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *comde; // [13:13] COM DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *comif; // [5:5] COM interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *bif; // [7:7] Break interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *comg; // [5:5] Capture/Compare control update generation + Object *tg; // [6:6] Trigger generation + Object *bg; // [7:7] Break generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *oc1ce; // [7:7] Output Compare 1 clear enable + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + Object *oc2ce; // [15:15] Output Compare 2 clear enable + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/Compare 3 selection + Object *oc3fe; // [2:2] Output compare 3 fast enable + Object *oc3pe; // [3:3] Output compare 3 preload enable + Object *oc3m; // [4:6] Output compare 3 mode + Object *oc3ce; // [7:7] Output compare 3 clear enable + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *oc4fe; // [10:10] Output compare 4 fast enable + Object *oc4pe; // [11:11] Output compare 4 preload enable + Object *oc4m; // [12:14] Output compare 4 mode + Object *oc4ce; // [15:15] Output compare 4 clear enable + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1ne; // [2:2] Capture/Compare 1 complementary output enable + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2ne; // [6:6] Capture/Compare 2 complementary output enable + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3ne; // [10:10] Capture/Compare 3 complementary output enable + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3; // [0:15] Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4; // [0:15] Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // RCR (Repetition counter register) bitfields. + struct { + Object *rep; // [0:7] Repetition counter value + } rcr; + + // BDTR (Break and dead-time register) bitfields. + struct { + Object *dtg; // [0:7] Dead-time generator setup + Object *lock; // [8:9] Lock configuration + Object *ossi; // [10:10] Off-state selection for Idle mode + Object *ossr; // [11:11] Off-state selection for Run mode + Object *bke; // [12:12] Break enable + Object *bkp; // [13:13] Break polarity + Object *aoe; // [14:14] Automatic output enable + Object *moe; // [15:15] Main output enable + } bdtr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM1State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM1_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim10.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim10.c new file mode 100644 index 0000000000..7581271142 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim10.c @@ -0,0 +1,293 @@ +/* + * STM32 - TIM10 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim10_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim10_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim10_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim10_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim10_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM10State *state = STM32_TIM10_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim10_is_enabled(Object *obj) +{ + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim10_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM10State *state = STM32_TIM10_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim10_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM10)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM10State *state = STM32_TIM10_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM10"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim10_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim10_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim10_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim10_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim10_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM10EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim10_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM10); +} + +static void stm32_tim10_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim10_reset_callback; + dc->realize = stm32_tim10_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim10_is_enabled; +} + +static const TypeInfo stm32_tim10_type_info = { + .name = TYPE_STM32_TIM10, + .parent = TYPE_STM32_TIM10_PARENT, + .instance_init = stm32_tim10_instance_init_callback, + .instance_size = sizeof(STM32TIM10State), + .class_init = stm32_tim10_class_init_callback, + .class_size = sizeof(STM32TIM10Class) }; + +static void stm32_tim10_register_types(void) +{ + type_register_static(&stm32_tim10_type_info); +} + +type_init(stm32_tim10_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim10.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim10.h new file mode 100644 index 0000000000..db54c1c071 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim10.h @@ -0,0 +1,180 @@ +/* + * STM32 - TIM10 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM10_H_ +#define STM32_TIM10_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM10 DEVICE_PATH_STM32 "TIM10" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM10 TYPE_STM32_PREFIX "tim10" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM10_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM10ParentClass; +typedef PeripheralState STM32TIM10ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM10_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM10Class, (obj), TYPE_STM32_TIM10) +#define STM32_TIM10_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM10Class, (klass), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM10Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM10_STATE(obj) \ + OBJECT_CHECK(STM32TIM10State, (obj), TYPE_STM32_TIM10) + +typedef struct { + // private: + STM32TIM10ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM10 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM10State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM10_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim11.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim11.c new file mode 100644 index 0000000000..209b7efe70 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim11.c @@ -0,0 +1,297 @@ +/* + * STM32 - TIM11 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim11_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // OR bitfields. + state->u.f4.fld.or_.rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim11_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim11_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim11_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim11_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM11State *state = STM32_TIM11_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim11_is_enabled(Object *obj) +{ + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim11_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM11State *state = STM32_TIM11_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim11_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM11)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM11State *state = STM32_TIM11_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM11"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim11_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim11_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim11_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim11_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim11_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM11EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim11_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM11); +} + +static void stm32_tim11_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim11_reset_callback; + dc->realize = stm32_tim11_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim11_is_enabled; +} + +static const TypeInfo stm32_tim11_type_info = { + .name = TYPE_STM32_TIM11, + .parent = TYPE_STM32_TIM11_PARENT, + .instance_init = stm32_tim11_instance_init_callback, + .instance_size = sizeof(STM32TIM11State), + .class_init = stm32_tim11_class_init_callback, + .class_size = sizeof(STM32TIM11Class) }; + +static void stm32_tim11_register_types(void) +{ + type_register_static(&stm32_tim11_type_info); +} + +type_init(stm32_tim11_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim11.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim11.h new file mode 100644 index 0000000000..22f02a5127 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim11.h @@ -0,0 +1,186 @@ +/* + * STM32 - TIM11 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM11_H_ +#define STM32_TIM11_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM11 DEVICE_PATH_STM32 "TIM11" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM11 TYPE_STM32_PREFIX "tim11" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM11_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM11ParentClass; +typedef PeripheralState STM32TIM11ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM11_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM11Class, (obj), TYPE_STM32_TIM11) +#define STM32_TIM11_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM11Class, (klass), TYPE_STM32_TIM11) + +typedef struct { + // private: + STM32TIM11ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM11Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM11_STATE(obj) \ + OBJECT_CHECK(STM32TIM11State, (obj), TYPE_STM32_TIM11) + +typedef struct { + // private: + STM32TIM11ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM11 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *or_; // 0x50 (Option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // OR (Option register) bitfields. + struct { + Object *rmp; // [0:1] Input 1 remapping capability + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM11State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM11_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim2.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim2.c new file mode 100644 index 0000000000..198f1eb412 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim2.c @@ -0,0 +1,404 @@ +/* + * STM32 - TIM2 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim2_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // OR bitfields. + state->u.f4.fld.or_.itr1_rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "ITR1_RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim2_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim2_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim2_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim2_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM2State *state = STM32_TIM2_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim2_is_enabled(Object *obj) +{ + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim2_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM2State *state = STM32_TIM2_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim2_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM2)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM2State *state = STM32_TIM2_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM2"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim2_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim2_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim2_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim2_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim2_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM2EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim2_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM2); +} + +static void stm32_tim2_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim2_reset_callback; + dc->realize = stm32_tim2_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim2_is_enabled; +} + +static const TypeInfo stm32_tim2_type_info = { + .name = TYPE_STM32_TIM2, + .parent = TYPE_STM32_TIM2_PARENT, + .instance_init = stm32_tim2_instance_init_callback, + .instance_size = sizeof(STM32TIM2State), + .class_init = stm32_tim2_class_init_callback, + .class_size = sizeof(STM32TIM2Class) }; + +static void stm32_tim2_register_types(void) +{ + type_register_static(&stm32_tim2_type_info); +} + +type_init(stm32_tim2_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim2.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim2.h new file mode 100644 index 0000000000..142585db3d --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim2.h @@ -0,0 +1,311 @@ +/* + * STM32 - TIM2 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM2_H_ +#define STM32_TIM2_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM2 DEVICE_PATH_STM32 "TIM2" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM2 TYPE_STM32_PREFIX "tim2" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM2_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM2ParentClass; +typedef PeripheralState STM32TIM2ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM2_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM2Class, (obj), TYPE_STM32_TIM2) +#define STM32_TIM2_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM2Class, (klass), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM2Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM2_STATE(obj) \ + OBJECT_CHECK(STM32TIM2State, (obj), TYPE_STM32_TIM2) + +typedef struct { + // private: + STM32TIM2ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM2 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *or_; // 0x50 (TIM5 option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // OR (TIM5 option register) bitfields. + struct { + Object *itr1_rmp; // [10:11] Timer Input 4 remap + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM2State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM2_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim3.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim3.c new file mode 100644 index 0000000000..bb6eba214c --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim3.c @@ -0,0 +1,400 @@ +/* + * STM32 - TIM3 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim3_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim3_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim3_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim3_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim3_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM3State *state = STM32_TIM3_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim3_is_enabled(Object *obj) +{ + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim3_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM3State *state = STM32_TIM3_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim3_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM3)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM3State *state = STM32_TIM3_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM3"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim3_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim3_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim3_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim3_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim3_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM3EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim3_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM3); +} + +static void stm32_tim3_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim3_reset_callback; + dc->realize = stm32_tim3_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim3_is_enabled; +} + +static const TypeInfo stm32_tim3_type_info = { + .name = TYPE_STM32_TIM3, + .parent = TYPE_STM32_TIM3_PARENT, + .instance_init = stm32_tim3_instance_init_callback, + .instance_size = sizeof(STM32TIM3State), + .class_init = stm32_tim3_class_init_callback, + .class_size = sizeof(STM32TIM3Class) }; + +static void stm32_tim3_register_types(void) +{ + type_register_static(&stm32_tim3_type_info); +} + +type_init(stm32_tim3_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim3.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim3.h new file mode 100644 index 0000000000..7f70acd7eb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim3.h @@ -0,0 +1,305 @@ +/* + * STM32 - TIM3 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM3_H_ +#define STM32_TIM3_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM3 DEVICE_PATH_STM32 "TIM3" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM3 TYPE_STM32_PREFIX "tim3" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM3_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM3ParentClass; +typedef PeripheralState STM32TIM3ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM3_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM3Class, (obj), TYPE_STM32_TIM3) +#define STM32_TIM3_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM3Class, (klass), TYPE_STM32_TIM3) + +typedef struct { + // private: + STM32TIM3ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM3Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM3_STATE(obj) \ + OBJECT_CHECK(STM32TIM3State, (obj), TYPE_STM32_TIM3) + +typedef struct { + // private: + STM32TIM3ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM3 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM3State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM3_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim5.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim5.c new file mode 100644 index 0000000000..0d10f1ef39 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim5.c @@ -0,0 +1,404 @@ +/* + * STM32 - TIM5 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim5_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccmr2_output = cm_object_get_child_by_name(obj, "CCMR2_Output"); + state->u.f4.reg.ccmr2_input = cm_object_get_child_by_name(obj, "CCMR2_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + state->u.f4.reg.ccr3 = cm_object_get_child_by_name(obj, "CCR3"); + state->u.f4.reg.ccr4 = cm_object_get_child_by_name(obj, "CCR4"); + state->u.f4.reg.dcr = cm_object_get_child_by_name(obj, "DCR"); + state->u.f4.reg.dmar = cm_object_get_child_by_name(obj, "DMAR"); + state->u.f4.reg.or_ = cm_object_get_child_by_name(obj, "OR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.dir = cm_object_get_child_by_name(state->u.f4.reg.cr1, "DIR"); + state->u.f4.fld.cr1.cms = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CMS"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.ccds = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CCDS"); + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + state->u.f4.fld.cr2.ti1s = cm_object_get_child_by_name(state->u.f4.reg.cr2, "TI1S"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + state->u.f4.fld.smcr.etf = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETF"); + state->u.f4.fld.smcr.etps = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETPS"); + state->u.f4.fld.smcr.ece = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ECE"); + state->u.f4.fld.smcr.etp = cm_object_get_child_by_name(state->u.f4.reg.smcr, "ETP"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.cc3ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3IE"); + state->u.f4.fld.dier.cc4ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + state->u.f4.fld.dier.cc1de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1DE"); + state->u.f4.fld.dier.cc2de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2DE"); + state->u.f4.fld.dier.cc3de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC3DE"); + state->u.f4.fld.dier.cc4de = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC4DE"); + state->u.f4.fld.dier.tde = cm_object_get_child_by_name(state->u.f4.reg.dier, "TDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.cc3if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3IF"); + state->u.f4.fld.sr.cc4if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + state->u.f4.fld.sr.cc3of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC3OF"); + state->u.f4.fld.sr.cc4of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC4OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.cc3g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC3G"); + state->u.f4.fld.egr.cc4g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC4G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.oc1ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1CE"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + state->u.f4.fld.ccmr1_output.oc2ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2CE"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCMR2_Output bitfields. + state->u.f4.fld.ccmr2_output.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC3S"); + state->u.f4.fld.ccmr2_output.oc3fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3FE"); + state->u.f4.fld.ccmr2_output.oc3pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3PE"); + state->u.f4.fld.ccmr2_output.oc3m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3M"); + state->u.f4.fld.ccmr2_output.oc3ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC3CE"); + state->u.f4.fld.ccmr2_output.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "CC4S"); + state->u.f4.fld.ccmr2_output.oc4fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4FE"); + state->u.f4.fld.ccmr2_output.oc4pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4PE"); + state->u.f4.fld.ccmr2_output.oc4m = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "OC4M"); + state->u.f4.fld.ccmr2_output.o24ce = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_output, "O24CE"); + + // CCMR2_Input bitfields. + state->u.f4.fld.ccmr2_input.cc3s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC3S"); + state->u.f4.fld.ccmr2_input.ic3psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3PSC"); + state->u.f4.fld.ccmr2_input.ic3f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC3F"); + state->u.f4.fld.ccmr2_input.cc4s = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "CC4S"); + state->u.f4.fld.ccmr2_input.ic4psc = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4PSC"); + state->u.f4.fld.ccmr2_input.ic4f = cm_object_get_child_by_name(state->u.f4.reg.ccmr2_input, "IC4F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + state->u.f4.fld.ccer.cc3e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3E"); + state->u.f4.fld.ccer.cc3p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3P"); + state->u.f4.fld.ccer.cc3np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC3NP"); + state->u.f4.fld.ccer.cc4e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4E"); + state->u.f4.fld.ccer.cc4p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4P"); + state->u.f4.fld.ccer.cc4np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC4NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt_l = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_L"); + state->u.f4.fld.cnt.cnt_h = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT_H"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr_l = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_L"); + state->u.f4.fld.arr.arr_h = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR_H"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1_l = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_L"); + state->u.f4.fld.ccr1.ccr1_h = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1_H"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2_l = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_L"); + state->u.f4.fld.ccr2.ccr2_h = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2_H"); + + // CCR3 bitfields. + state->u.f4.fld.ccr3.ccr3_l = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_L"); + state->u.f4.fld.ccr3.ccr3_h = cm_object_get_child_by_name(state->u.f4.reg.ccr3, "CCR3_H"); + + // CCR4 bitfields. + state->u.f4.fld.ccr4.ccr4_l = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_L"); + state->u.f4.fld.ccr4.ccr4_h = cm_object_get_child_by_name(state->u.f4.reg.ccr4, "CCR4_H"); + + // DCR bitfields. + state->u.f4.fld.dcr.dba = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBA"); + state->u.f4.fld.dcr.dbl = cm_object_get_child_by_name(state->u.f4.reg.dcr, "DBL"); + + // DMAR bitfields. + state->u.f4.fld.dmar.dmab = cm_object_get_child_by_name(state->u.f4.reg.dmar, "DMAB"); + + // OR bitfields. + state->u.f4.fld.or_.it4_rmp = cm_object_get_child_by_name(state->u.f4.reg.or_, "IT4_RMP"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim5_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim5_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim5_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim5_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM5State *state = STM32_TIM5_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim5_is_enabled(Object *obj) +{ + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim5_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM5State *state = STM32_TIM5_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim5_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM5)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM5State *state = STM32_TIM5_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM5"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim5_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim5_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim5_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim5_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim5_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM5EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim5_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM5); +} + +static void stm32_tim5_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim5_reset_callback; + dc->realize = stm32_tim5_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim5_is_enabled; +} + +static const TypeInfo stm32_tim5_type_info = { + .name = TYPE_STM32_TIM5, + .parent = TYPE_STM32_TIM5_PARENT, + .instance_init = stm32_tim5_instance_init_callback, + .instance_size = sizeof(STM32TIM5State), + .class_init = stm32_tim5_class_init_callback, + .class_size = sizeof(STM32TIM5Class) }; + +static void stm32_tim5_register_types(void) +{ + type_register_static(&stm32_tim5_type_info); +} + +type_init(stm32_tim5_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim5.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim5.h new file mode 100644 index 0000000000..41d6bcf531 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim5.h @@ -0,0 +1,311 @@ +/* + * STM32 - TIM5 (General-purpose-timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM5_H_ +#define STM32_TIM5_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM5 DEVICE_PATH_STM32 "TIM5" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM5 TYPE_STM32_PREFIX "tim5" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM5_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM5ParentClass; +typedef PeripheralState STM32TIM5ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM5_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM5Class, (obj), TYPE_STM32_TIM5) +#define STM32_TIM5_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM5Class, (klass), TYPE_STM32_TIM5) + +typedef struct { + // private: + STM32TIM5ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM5Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM5_STATE(obj) \ + OBJECT_CHECK(STM32TIM5State, (obj), TYPE_STM32_TIM5) + +typedef struct { + // private: + STM32TIM5ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM5 (General-purpose-timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccmr2_output; // 0x1C (Capture/compare mode register 2 (output mode)) + Object *ccmr2_input; // 0x1C (Capture/compare mode register 2 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + Object *ccr3; // 0x3C (Capture/compare register 3) + Object *ccr4; // 0x40 (Capture/compare register 4) + Object *dcr; // 0x48 (DMA control register) + Object *dmar; // 0x4C (DMA address for full transfer) + Object *or_; // 0x50 (TIM5 option register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *dir; // [4:4] Direction + Object *cms; // [5:6] Center-aligned mode selection + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *ccds; // [3:3] Capture/compare DMA selection + Object *mms; // [4:6] Master mode selection + Object *ti1s; // [7:7] TI1 selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + Object *etf; // [8:11] External trigger filter + Object *etps; // [12:13] External trigger prescaler + Object *ece; // [14:14] External clock enable + Object *etp; // [15:15] External trigger polarity + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *cc3ie; // [3:3] Capture/Compare 3 interrupt enable + Object *cc4ie; // [4:4] Capture/Compare 4 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + Object *ude; // [8:8] Update DMA request enable + Object *cc1de; // [9:9] Capture/Compare 1 DMA request enable + Object *cc2de; // [10:10] Capture/Compare 2 DMA request enable + Object *cc3de; // [11:11] Capture/Compare 3 DMA request enable + Object *cc4de; // [12:12] Capture/Compare 4 DMA request enable + Object *tde; // [14:14] Trigger DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *cc3if; // [3:3] Capture/Compare 3 interrupt flag + Object *cc4if; // [4:4] Capture/Compare 4 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + Object *cc3of; // [11:11] Capture/Compare 3 overcapture flag + Object *cc4of; // [12:12] Capture/Compare 4 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *cc3g; // [3:3] Capture/compare 3 generation + Object *cc4g; // [4:4] Capture/compare 4 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] CC1S + Object *oc1fe; // [2:2] OC1FE + Object *oc1pe; // [3:3] OC1PE + Object *oc1m; // [4:6] OC1M + Object *oc1ce; // [7:7] OC1CE + Object *cc2s; // [8:9] CC2S + Object *oc2fe; // [10:10] OC2FE + Object *oc2pe; // [11:11] OC2PE + Object *oc2m; // [12:14] OC2M + Object *oc2ce; // [15:15] OC2CE + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:7] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:15] Input capture 2 filter + } ccmr1_input; + + // CCMR2_Output (Capture/compare mode register 2 (output mode)) bitfields. + struct { + Object *cc3s; // [0:1] CC3S + Object *oc3fe; // [2:2] OC3FE + Object *oc3pe; // [3:3] OC3PE + Object *oc3m; // [4:6] OC3M + Object *oc3ce; // [7:7] OC3CE + Object *cc4s; // [8:9] CC4S + Object *oc4fe; // [10:10] OC4FE + Object *oc4pe; // [11:11] OC4PE + Object *oc4m; // [12:14] OC4M + Object *o24ce; // [15:15] O24CE + } ccmr2_output; + + // CCMR2_Input (Capture/compare mode register 2 (input mode)) bitfields. + struct { + Object *cc3s; // [0:1] Capture/compare 3 selection + Object *ic3psc; // [2:3] Input capture 3 prescaler + Object *ic3f; // [4:7] Input capture 3 filter + Object *cc4s; // [8:9] Capture/Compare 4 selection + Object *ic4psc; // [10:11] Input capture 4 prescaler + Object *ic4f; // [12:15] Input capture 4 filter + } ccmr2_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + Object *cc3e; // [8:8] Capture/Compare 3 output enable + Object *cc3p; // [9:9] Capture/Compare 3 output Polarity + Object *cc3np; // [11:11] Capture/Compare 3 output Polarity + Object *cc4e; // [12:12] Capture/Compare 4 output enable + Object *cc4p; // [13:13] Capture/Compare 3 output Polarity + Object *cc4np; // [15:15] Capture/Compare 4 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt_l; // [0:15] Low counter value + Object *cnt_h; // [16:31] High counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr_l; // [0:15] Low Auto-reload value + Object *arr_h; // [16:31] High Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1_l; // [0:15] Low Capture/Compare 1 value + Object *ccr1_h; // [16:31] High Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2_l; // [0:15] Low Capture/Compare 2 value + Object *ccr2_h; // [16:31] High Capture/Compare 2 value + } ccr2; + + // CCR3 (Capture/compare register 3) bitfields. + struct { + Object *ccr3_l; // [0:15] Low Capture/Compare value + Object *ccr3_h; // [16:31] High Capture/Compare value + } ccr3; + + // CCR4 (Capture/compare register 4) bitfields. + struct { + Object *ccr4_l; // [0:15] Low Capture/Compare value + Object *ccr4_h; // [16:31] High Capture/Compare value + } ccr4; + + // DCR (DMA control register) bitfields. + struct { + Object *dba; // [0:4] DMA base address + Object *dbl; // [8:12] DMA burst length + } dcr; + + // DMAR (DMA address for full transfer) bitfields. + struct { + Object *dmab; // [0:15] DMA register for burst accesses + } dmar; + + // OR (TIM5 option register) bitfields. + struct { + Object *it4_rmp; // [6:7] Timer Input 4 remap + } or_; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM5State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM5_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim6.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim6.c new file mode 100644 index 0000000000..5333aae121 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim6.c @@ -0,0 +1,271 @@ +/* + * STM32 - TIM6 (Basic timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim6_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + + // CR2 bitfields. + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.ude = cm_object_get_child_by_name(state->u.f4.reg.dier, "UDE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim6_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim6_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim6_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim6_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM6State *state = STM32_TIM6_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim6_is_enabled(Object *obj) +{ + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim6_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM6State *state = STM32_TIM6_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim6_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM6)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM6State *state = STM32_TIM6_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM6"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim6_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim6_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim6_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim6_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim6_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM6EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim6_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM6); +} + +static void stm32_tim6_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim6_reset_callback; + dc->realize = stm32_tim6_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim6_is_enabled; +} + +static const TypeInfo stm32_tim6_type_info = { + .name = TYPE_STM32_TIM6, + .parent = TYPE_STM32_TIM6_PARENT, + .instance_init = stm32_tim6_instance_init_callback, + .instance_size = sizeof(STM32TIM6State), + .class_init = stm32_tim6_class_init_callback, + .class_size = sizeof(STM32TIM6Class) }; + +static void stm32_tim6_register_types(void) +{ + type_register_static(&stm32_tim6_type_info); +} + +type_init(stm32_tim6_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim6.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim6.h new file mode 100644 index 0000000000..01ec26bc05 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim6.h @@ -0,0 +1,152 @@ +/* + * STM32 - TIM6 (Basic timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM6_H_ +#define STM32_TIM6_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM6 DEVICE_PATH_STM32 "TIM6" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM6 TYPE_STM32_PREFIX "tim6" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM6_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM6ParentClass; +typedef PeripheralState STM32TIM6ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM6_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM6Class, (obj), TYPE_STM32_TIM6) +#define STM32_TIM6_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM6Class, (klass), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM6Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM6_STATE(obj) \ + OBJECT_CHECK(STM32TIM6State, (obj), TYPE_STM32_TIM6) + +typedef struct { + // private: + STM32TIM6ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM6 (Basic timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *ude; // [8:8] Update DMA request enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + } egr; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Low counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Low Auto-reload value + } arr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM6State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM6_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim9.c b/gnu-mcu-eclipse/devices/support/STM32F429x/tim9.c new file mode 100644 index 0000000000..976c62c597 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim9.c @@ -0,0 +1,325 @@ +/* + * STM32 - TIM9 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_tim9_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.smcr = cm_object_get_child_by_name(obj, "SMCR"); + state->u.f4.reg.dier = cm_object_get_child_by_name(obj, "DIER"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.egr = cm_object_get_child_by_name(obj, "EGR"); + state->u.f4.reg.ccmr1_output = cm_object_get_child_by_name(obj, "CCMR1_Output"); + state->u.f4.reg.ccmr1_input = cm_object_get_child_by_name(obj, "CCMR1_Input"); + state->u.f4.reg.ccer = cm_object_get_child_by_name(obj, "CCER"); + state->u.f4.reg.cnt = cm_object_get_child_by_name(obj, "CNT"); + state->u.f4.reg.psc = cm_object_get_child_by_name(obj, "PSC"); + state->u.f4.reg.arr = cm_object_get_child_by_name(obj, "ARR"); + state->u.f4.reg.ccr1 = cm_object_get_child_by_name(obj, "CCR1"); + state->u.f4.reg.ccr2 = cm_object_get_child_by_name(obj, "CCR2"); + + + // CR1 bitfields. + state->u.f4.fld.cr1.cen = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CEN"); + state->u.f4.fld.cr1.udis = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UDIS"); + state->u.f4.fld.cr1.urs = cm_object_get_child_by_name(state->u.f4.reg.cr1, "URS"); + state->u.f4.fld.cr1.opm = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OPM"); + state->u.f4.fld.cr1.arpe = cm_object_get_child_by_name(state->u.f4.reg.cr1, "ARPE"); + state->u.f4.fld.cr1.ckd = cm_object_get_child_by_name(state->u.f4.reg.cr1, "CKD"); + + // CR2 bitfields. + state->u.f4.fld.cr2.mms = cm_object_get_child_by_name(state->u.f4.reg.cr2, "MMS"); + + // SMCR bitfields. + state->u.f4.fld.smcr.sms = cm_object_get_child_by_name(state->u.f4.reg.smcr, "SMS"); + state->u.f4.fld.smcr.ts = cm_object_get_child_by_name(state->u.f4.reg.smcr, "TS"); + state->u.f4.fld.smcr.msm = cm_object_get_child_by_name(state->u.f4.reg.smcr, "MSM"); + + // DIER bitfields. + state->u.f4.fld.dier.uie = cm_object_get_child_by_name(state->u.f4.reg.dier, "UIE"); + state->u.f4.fld.dier.cc1ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC1IE"); + state->u.f4.fld.dier.cc2ie = cm_object_get_child_by_name(state->u.f4.reg.dier, "CC2IE"); + state->u.f4.fld.dier.tie = cm_object_get_child_by_name(state->u.f4.reg.dier, "TIE"); + + // SR bitfields. + state->u.f4.fld.sr.uif = cm_object_get_child_by_name(state->u.f4.reg.sr, "UIF"); + state->u.f4.fld.sr.cc1if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1IF"); + state->u.f4.fld.sr.cc2if = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2IF"); + state->u.f4.fld.sr.tif = cm_object_get_child_by_name(state->u.f4.reg.sr, "TIF"); + state->u.f4.fld.sr.cc1of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC1OF"); + state->u.f4.fld.sr.cc2of = cm_object_get_child_by_name(state->u.f4.reg.sr, "CC2OF"); + + // EGR bitfields. + state->u.f4.fld.egr.ug = cm_object_get_child_by_name(state->u.f4.reg.egr, "UG"); + state->u.f4.fld.egr.cc1g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC1G"); + state->u.f4.fld.egr.cc2g = cm_object_get_child_by_name(state->u.f4.reg.egr, "CC2G"); + state->u.f4.fld.egr.tg = cm_object_get_child_by_name(state->u.f4.reg.egr, "TG"); + + // CCMR1_Output bitfields. + state->u.f4.fld.ccmr1_output.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC1S"); + state->u.f4.fld.ccmr1_output.oc1fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1FE"); + state->u.f4.fld.ccmr1_output.oc1pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1PE"); + state->u.f4.fld.ccmr1_output.oc1m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC1M"); + state->u.f4.fld.ccmr1_output.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "CC2S"); + state->u.f4.fld.ccmr1_output.oc2fe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2FE"); + state->u.f4.fld.ccmr1_output.oc2pe = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2PE"); + state->u.f4.fld.ccmr1_output.oc2m = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_output, "OC2M"); + + // CCMR1_Input bitfields. + state->u.f4.fld.ccmr1_input.cc1s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC1S"); + state->u.f4.fld.ccmr1_input.icpcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "ICPCS"); + state->u.f4.fld.ccmr1_input.ic1f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC1F"); + state->u.f4.fld.ccmr1_input.cc2s = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "CC2S"); + state->u.f4.fld.ccmr1_input.ic2pcs = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2PCS"); + state->u.f4.fld.ccmr1_input.ic2f = cm_object_get_child_by_name(state->u.f4.reg.ccmr1_input, "IC2F"); + + // CCER bitfields. + state->u.f4.fld.ccer.cc1e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1E"); + state->u.f4.fld.ccer.cc1p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1P"); + state->u.f4.fld.ccer.cc1np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC1NP"); + state->u.f4.fld.ccer.cc2e = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2E"); + state->u.f4.fld.ccer.cc2p = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2P"); + state->u.f4.fld.ccer.cc2np = cm_object_get_child_by_name(state->u.f4.reg.ccer, "CC2NP"); + + // CNT bitfields. + state->u.f4.fld.cnt.cnt = cm_object_get_child_by_name(state->u.f4.reg.cnt, "CNT"); + + // PSC bitfields. + state->u.f4.fld.psc.psc = cm_object_get_child_by_name(state->u.f4.reg.psc, "PSC"); + + // ARR bitfields. + state->u.f4.fld.arr.arr = cm_object_get_child_by_name(state->u.f4.reg.arr, "ARR"); + + // CCR1 bitfields. + state->u.f4.fld.ccr1.ccr1 = cm_object_get_child_by_name(state->u.f4.reg.ccr1, "CCR1"); + + // CCR2 bitfields. + state->u.f4.fld.ccr2.ccr2 = cm_object_get_child_by_name(state->u.f4.reg.ccr2, "CCR2"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_tim9_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_tim9_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_tim9_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_tim9_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32TIM9State *state = STM32_TIM9_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_tim9_is_enabled(Object *obj) +{ + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_tim9_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32TIM9State *state = STM32_TIM9_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_tim9_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_TIM9)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32TIM9State *state = STM32_TIM9_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "TIM9"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_tim9_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim9_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_tim9_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_tim9_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_tim9_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/TIM9EN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_tim9_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_TIM9); +} + +static void stm32_tim9_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_tim9_reset_callback; + dc->realize = stm32_tim9_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_tim9_is_enabled; +} + +static const TypeInfo stm32_tim9_type_info = { + .name = TYPE_STM32_TIM9, + .parent = TYPE_STM32_TIM9_PARENT, + .instance_init = stm32_tim9_instance_init_callback, + .instance_size = sizeof(STM32TIM9State), + .class_init = stm32_tim9_class_init_callback, + .class_size = sizeof(STM32TIM9Class) }; + +static void stm32_tim9_register_types(void) +{ + type_register_static(&stm32_tim9_type_info); +} + +type_init(stm32_tim9_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/tim9.h b/gnu-mcu-eclipse/devices/support/STM32F429x/tim9.h new file mode 100644 index 0000000000..c05086f65e --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/tim9.h @@ -0,0 +1,218 @@ +/* + * STM32 - TIM9 (General purpose timers) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_TIM9_H_ +#define STM32_TIM9_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_TIM9 DEVICE_PATH_STM32 "TIM9" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_TIM9 TYPE_STM32_PREFIX "tim9" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_TIM9_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32TIM9ParentClass; +typedef PeripheralState STM32TIM9ParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_TIM9_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32TIM9Class, (obj), TYPE_STM32_TIM9) +#define STM32_TIM9_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32TIM9Class, (klass), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentClass parent_class; + // public: + + // None, so far. +} STM32TIM9Class; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_TIM9_STATE(obj) \ + OBJECT_CHECK(STM32TIM9State, (obj), TYPE_STM32_TIM9) + +typedef struct { + // private: + STM32TIM9ParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 TIM9 (General purpose timers) registers. + struct { + Object *cr1; // 0x0 (Control register 1) + Object *cr2; // 0x4 (Control register 2) + Object *smcr; // 0x8 (Slave mode control register) + Object *dier; // 0xC (DMA/Interrupt enable register) + Object *sr; // 0x10 (Status register) + Object *egr; // 0x14 (Event generation register) + Object *ccmr1_output; // 0x18 (Capture/compare mode register 1 (output mode)) + Object *ccmr1_input; // 0x18 (Capture/compare mode register 1 (input mode)) + Object *ccer; // 0x20 (Capture/compare enable register) + Object *cnt; // 0x24 (Counter) + Object *psc; // 0x28 (Prescaler) + Object *arr; // 0x2C (Auto-reload register) + Object *ccr1; // 0x34 (Capture/compare register 1) + Object *ccr2; // 0x38 (Capture/compare register 2) + } reg; + + struct { + + // CR1 (Control register 1) bitfields. + struct { + Object *cen; // [0:0] Counter enable + Object *udis; // [1:1] Update disable + Object *urs; // [2:2] Update request source + Object *opm; // [3:3] One-pulse mode + Object *arpe; // [7:7] Auto-reload preload enable + Object *ckd; // [8:9] Clock division + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *mms; // [4:6] Master mode selection + } cr2; + + // SMCR (Slave mode control register) bitfields. + struct { + Object *sms; // [0:2] Slave mode selection + Object *ts; // [4:6] Trigger selection + Object *msm; // [7:7] Master/Slave mode + } smcr; + + // DIER (DMA/Interrupt enable register) bitfields. + struct { + Object *uie; // [0:0] Update interrupt enable + Object *cc1ie; // [1:1] Capture/Compare 1 interrupt enable + Object *cc2ie; // [2:2] Capture/Compare 2 interrupt enable + Object *tie; // [6:6] Trigger interrupt enable + } dier; + + // SR (Status register) bitfields. + struct { + Object *uif; // [0:0] Update interrupt flag + Object *cc1if; // [1:1] Capture/compare 1 interrupt flag + Object *cc2if; // [2:2] Capture/Compare 2 interrupt flag + Object *tif; // [6:6] Trigger interrupt flag + Object *cc1of; // [9:9] Capture/Compare 1 overcapture flag + Object *cc2of; // [10:10] Capture/compare 2 overcapture flag + } sr; + + // EGR (Event generation register) bitfields. + struct { + Object *ug; // [0:0] Update generation + Object *cc1g; // [1:1] Capture/compare 1 generation + Object *cc2g; // [2:2] Capture/compare 2 generation + Object *tg; // [6:6] Trigger generation + } egr; + + // CCMR1_Output (Capture/compare mode register 1 (output mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *oc1fe; // [2:2] Output Compare 1 fast enable + Object *oc1pe; // [3:3] Output Compare 1 preload enable + Object *oc1m; // [4:6] Output Compare 1 mode + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *oc2fe; // [10:10] Output Compare 2 fast enable + Object *oc2pe; // [11:11] Output Compare 2 preload enable + Object *oc2m; // [12:14] Output Compare 2 mode + } ccmr1_output; + + // CCMR1_Input (Capture/compare mode register 1 (input mode)) bitfields. + struct { + Object *cc1s; // [0:1] Capture/Compare 1 selection + Object *icpcs; // [2:3] Input capture 1 prescaler + Object *ic1f; // [4:6] Input capture 1 filter + Object *cc2s; // [8:9] Capture/Compare 2 selection + Object *ic2pcs; // [10:11] Input capture 2 prescaler + Object *ic2f; // [12:14] Input capture 2 filter + } ccmr1_input; + + // CCER (Capture/compare enable register) bitfields. + struct { + Object *cc1e; // [0:0] Capture/Compare 1 output enable + Object *cc1p; // [1:1] Capture/Compare 1 output Polarity + Object *cc1np; // [3:3] Capture/Compare 1 output Polarity + Object *cc2e; // [4:4] Capture/Compare 2 output enable + Object *cc2p; // [5:5] Capture/Compare 2 output Polarity + Object *cc2np; // [7:7] Capture/Compare 2 output Polarity + } ccer; + + // CNT (Counter) bitfields. + struct { + Object *cnt; // [0:15] Counter value + } cnt; + + // PSC (Prescaler) bitfields. + struct { + Object *psc; // [0:15] Prescaler value + } psc; + + // ARR (Auto-reload register) bitfields. + struct { + Object *arr; // [0:15] Auto-reload value + } arr; + + // CCR1 (Capture/compare register 1) bitfields. + struct { + Object *ccr1; // [0:15] Capture/Compare 1 value + } ccr1; + + // CCR2 (Capture/compare register 2) bitfields. + struct { + Object *ccr2; // [0:15] Capture/Compare 2 value + } ccr2; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32TIM9State; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_TIM9_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/uart4.c b/gnu-mcu-eclipse/devices/support/STM32F429x/uart4.c new file mode 100644 index 0000000000..a88a0de2a0 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/uart4.c @@ -0,0 +1,296 @@ +/* + * STM32 - UART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_uart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + + + // SR bitfields. + state->u.f4.fld.sr.pe = cm_object_get_child_by_name(state->u.f4.reg.sr, "PE"); + state->u.f4.fld.sr.fe = cm_object_get_child_by_name(state->u.f4.reg.sr, "FE"); + state->u.f4.fld.sr.nf = cm_object_get_child_by_name(state->u.f4.reg.sr, "NF"); + state->u.f4.fld.sr.ore = cm_object_get_child_by_name(state->u.f4.reg.sr, "ORE"); + state->u.f4.fld.sr.idle = cm_object_get_child_by_name(state->u.f4.reg.sr, "IDLE"); + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.tc = cm_object_get_child_by_name(state->u.f4.reg.sr, "TC"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.lbd = cm_object_get_child_by_name(state->u.f4.reg.sr, "LBD"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // BRR bitfields. + state->u.f4.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Fraction"); + state->u.f4.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f4.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SBK"); + state->u.f4.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RWU"); + state->u.f4.fld.cr1.re = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RE"); + state->u.f4.fld.cr1.te = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TE"); + state->u.f4.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "IDLEIE"); + state->u.f4.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXNEIE"); + state->u.f4.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TCIE"); + state->u.f4.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TXEIE"); + state->u.f4.fld.cr1.peie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEIE"); + state->u.f4.fld.cr1.ps = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PS"); + state->u.f4.fld.cr1.pce = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PCE"); + state->u.f4.fld.cr1.wake = cm_object_get_child_by_name(state->u.f4.reg.cr1, "WAKE"); + state->u.f4.fld.cr1.m = cm_object_get_child_by_name(state->u.f4.reg.cr1, "M"); + state->u.f4.fld.cr1.ue = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UE"); + state->u.f4.fld.cr1.over8 = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVER8"); + + // CR2 bitfields. + state->u.f4.fld.cr2.add = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADD"); + state->u.f4.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDL"); + state->u.f4.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDIE"); + state->u.f4.fld.cr2.stop = cm_object_get_child_by_name(state->u.f4.reg.cr2, "STOP"); + state->u.f4.fld.cr2.linen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f4.fld.cr3.eie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "EIE"); + state->u.f4.fld.cr3.iren = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IREN"); + state->u.f4.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IRLP"); + state->u.f4.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f4.reg.cr3, "HDSEL"); + state->u.f4.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAR"); + state->u.f4.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAT"); + state->u.f4.fld.cr3.onebit = cm_object_get_child_by_name(state->u.f4.reg.cr3, "ONEBIT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_uart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_uart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_uart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_uart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32UARTState *state = STM32_UART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_uart_is_enabled(Object *obj) +{ + STM32UARTState *state = STM32_UART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_uart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32UARTState *state = STM32_UART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_UART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_uart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_UART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32UARTState *state = STM32_UART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "UART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_uart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_uart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_uart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_uart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_uart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/UART%dEN", + 1 + state->port_index - STM32_PORT_UART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_uart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_UART); +} + +static void stm32_uart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_uart_reset_callback; + dc->realize = stm32_uart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_uart_is_enabled; +} + +static const TypeInfo stm32_uart_type_info = { + .name = TYPE_STM32_UART, + .parent = TYPE_STM32_UART_PARENT, + .instance_init = stm32_uart_instance_init_callback, + .instance_size = sizeof(STM32UARTState), + .class_init = stm32_uart_class_init_callback, + .class_size = sizeof(STM32UARTClass) }; + +static void stm32_uart_register_types(void) +{ + type_register_static(&stm32_uart_type_info); +} + +type_init(stm32_uart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/uart4.h b/gnu-mcu-eclipse/devices/support/STM32F429x/uart4.h new file mode 100644 index 0000000000..827b5d2935 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/uart4.h @@ -0,0 +1,179 @@ +/* + * STM32 - UART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_UART_H_ +#define STM32_UART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_UART DEVICE_PATH_STM32 "UART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_UART4, + STM32_PORT_UART5, + STM32_PORT_UART_UNDEFINED = 0xFF, +} stm32_uart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_UART TYPE_STM32_PREFIX "uart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_UART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32UARTParentClass; +typedef PeripheralState STM32UARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32UARTClass, (obj), TYPE_STM32_UART) +#define STM32_UART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32UARTClass, (klass), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentClass parent_class; + // public: + + // None, so far. +} STM32UARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_UART_STATE(obj) \ + OBJECT_CHECK(STM32UARTState, (obj), TYPE_STM32_UART) + +typedef struct { + // private: + STM32UARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_uart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 UART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *dr; // 0x4 (Data register) + Object *brr; // 0x8 (Baud rate register) + Object *cr1; // 0xC (Control register 1) + Object *cr2; // 0x10 (Control register 2) + Object *cr3; // 0x14 (Control register 3) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *nf; // [2:2] Noise detected flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:8] Data value + } dr; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // CR1 (Control register 1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + Object *over8; // [15:15] Oversampling mode + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *onebit; // [11:11] One sample bit method enable + } cr3; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32UARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_UART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/usart6.c b/gnu-mcu-eclipse/devices/support/STM32F429x/usart6.c new file mode 100644 index 0000000000..32f6350335 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/usart6.c @@ -0,0 +1,311 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_usart_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR"); + state->u.f4.reg.brr = cm_object_get_child_by_name(obj, "BRR"); + state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1"); + state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2"); + state->u.f4.reg.cr3 = cm_object_get_child_by_name(obj, "CR3"); + state->u.f4.reg.gtpr = cm_object_get_child_by_name(obj, "GTPR"); + + + // SR bitfields. + state->u.f4.fld.sr.pe = cm_object_get_child_by_name(state->u.f4.reg.sr, "PE"); + state->u.f4.fld.sr.fe = cm_object_get_child_by_name(state->u.f4.reg.sr, "FE"); + state->u.f4.fld.sr.nf = cm_object_get_child_by_name(state->u.f4.reg.sr, "NF"); + state->u.f4.fld.sr.ore = cm_object_get_child_by_name(state->u.f4.reg.sr, "ORE"); + state->u.f4.fld.sr.idle = cm_object_get_child_by_name(state->u.f4.reg.sr, "IDLE"); + state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr, "RXNE"); + state->u.f4.fld.sr.tc = cm_object_get_child_by_name(state->u.f4.reg.sr, "TC"); + state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr, "TXE"); + state->u.f4.fld.sr.lbd = cm_object_get_child_by_name(state->u.f4.reg.sr, "LBD"); + state->u.f4.fld.sr.cts = cm_object_get_child_by_name(state->u.f4.reg.sr, "CTS"); + + // DR bitfields. + state->u.f4.fld.dr.dr = cm_object_get_child_by_name(state->u.f4.reg.dr, "DR"); + + // BRR bitfields. + state->u.f4.fld.brr.div_fraction = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Fraction"); + state->u.f4.fld.brr.div_mantissa = cm_object_get_child_by_name(state->u.f4.reg.brr, "DIV_Mantissa"); + + // CR1 bitfields. + state->u.f4.fld.cr1.sbk = cm_object_get_child_by_name(state->u.f4.reg.cr1, "SBK"); + state->u.f4.fld.cr1.rwu = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RWU"); + state->u.f4.fld.cr1.re = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RE"); + state->u.f4.fld.cr1.te = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TE"); + state->u.f4.fld.cr1.idleie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "IDLEIE"); + state->u.f4.fld.cr1.rxneie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "RXNEIE"); + state->u.f4.fld.cr1.tcie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TCIE"); + state->u.f4.fld.cr1.txeie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "TXEIE"); + state->u.f4.fld.cr1.peie = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PEIE"); + state->u.f4.fld.cr1.ps = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PS"); + state->u.f4.fld.cr1.pce = cm_object_get_child_by_name(state->u.f4.reg.cr1, "PCE"); + state->u.f4.fld.cr1.wake = cm_object_get_child_by_name(state->u.f4.reg.cr1, "WAKE"); + state->u.f4.fld.cr1.m = cm_object_get_child_by_name(state->u.f4.reg.cr1, "M"); + state->u.f4.fld.cr1.ue = cm_object_get_child_by_name(state->u.f4.reg.cr1, "UE"); + state->u.f4.fld.cr1.over8 = cm_object_get_child_by_name(state->u.f4.reg.cr1, "OVER8"); + + // CR2 bitfields. + state->u.f4.fld.cr2.add = cm_object_get_child_by_name(state->u.f4.reg.cr2, "ADD"); + state->u.f4.fld.cr2.lbdl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDL"); + state->u.f4.fld.cr2.lbdie = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBDIE"); + state->u.f4.fld.cr2.lbcl = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LBCL"); + state->u.f4.fld.cr2.cpha = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CPHA"); + state->u.f4.fld.cr2.cpol = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CPOL"); + state->u.f4.fld.cr2.clken = cm_object_get_child_by_name(state->u.f4.reg.cr2, "CLKEN"); + state->u.f4.fld.cr2.stop = cm_object_get_child_by_name(state->u.f4.reg.cr2, "STOP"); + state->u.f4.fld.cr2.linen = cm_object_get_child_by_name(state->u.f4.reg.cr2, "LINEN"); + + // CR3 bitfields. + state->u.f4.fld.cr3.eie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "EIE"); + state->u.f4.fld.cr3.iren = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IREN"); + state->u.f4.fld.cr3.irlp = cm_object_get_child_by_name(state->u.f4.reg.cr3, "IRLP"); + state->u.f4.fld.cr3.hdsel = cm_object_get_child_by_name(state->u.f4.reg.cr3, "HDSEL"); + state->u.f4.fld.cr3.nack = cm_object_get_child_by_name(state->u.f4.reg.cr3, "NACK"); + state->u.f4.fld.cr3.scen = cm_object_get_child_by_name(state->u.f4.reg.cr3, "SCEN"); + state->u.f4.fld.cr3.dmar = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAR"); + state->u.f4.fld.cr3.dmat = cm_object_get_child_by_name(state->u.f4.reg.cr3, "DMAT"); + state->u.f4.fld.cr3.rtse = cm_object_get_child_by_name(state->u.f4.reg.cr3, "RTSE"); + state->u.f4.fld.cr3.ctse = cm_object_get_child_by_name(state->u.f4.reg.cr3, "CTSE"); + state->u.f4.fld.cr3.ctsie = cm_object_get_child_by_name(state->u.f4.reg.cr3, "CTSIE"); + state->u.f4.fld.cr3.onebit = cm_object_get_child_by_name(state->u.f4.reg.cr3, "ONEBIT"); + + // GTPR bitfields. + state->u.f4.fld.gtpr.psc = cm_object_get_child_by_name(state->u.f4.reg.gtpr, "PSC"); + state->u.f4.fld.gtpr.gt = cm_object_get_child_by_name(state->u.f4.reg.gtpr, "GT"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_usart_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_usart_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_usart_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_usart_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32USARTState *state = STM32_USART_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_usart_is_enabled(Object *obj) +{ + STM32USARTState *state = STM32_USART_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_usart_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32USARTState *state = STM32_USART_STATE(obj); + + // Capabilities are not yet available. + + cm_object_property_add_int(obj, "port-index", + (const int *) &state->port_index); + state->port_index = STM32_PORT_USART_UNDEFINED; + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_usart_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_USART)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32USARTState *state = STM32_USART_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "USART"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_usart_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_usart_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_usart_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_usart_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_usart_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/USART%dEN", + 1 + state->port_index - STM32_PORT_USART1); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_usart_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_USART); +} + +static void stm32_usart_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_usart_reset_callback; + dc->realize = stm32_usart_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_usart_is_enabled; +} + +static const TypeInfo stm32_usart_type_info = { + .name = TYPE_STM32_USART, + .parent = TYPE_STM32_USART_PARENT, + .instance_init = stm32_usart_instance_init_callback, + .instance_size = sizeof(STM32USARTState), + .class_init = stm32_usart_class_init_callback, + .class_size = sizeof(STM32USARTClass) }; + +static void stm32_usart_register_types(void) +{ + type_register_static(&stm32_usart_type_info); +} + +type_init(stm32_usart_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/usart6.h b/gnu-mcu-eclipse/devices/support/STM32F429x/usart6.h new file mode 100644 index 0000000000..327edc7d66 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/usart6.h @@ -0,0 +1,198 @@ +/* + * STM32 - USART (Universal synchronous asynchronous receiver transmitter) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_USART_H_ +#define STM32_USART_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_USART DEVICE_PATH_STM32 "USART" + +// ---------------------------------------------------------------------------- + +// Note: the "port-index" property has type "int". +typedef enum { + // TODO: keep this list in ascending order. + STM32_PORT_USART1, + STM32_PORT_USART2, + STM32_PORT_USART3, + STM32_PORT_USART6, + STM32_PORT_USART_UNDEFINED = 0xFF, +} stm32_usart_index_t; + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_USART TYPE_STM32_PREFIX "usart" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_USART_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32USARTParentClass; +typedef PeripheralState STM32USARTParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_USART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32USARTClass, (obj), TYPE_STM32_USART) +#define STM32_USART_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32USARTClass, (klass), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentClass parent_class; + // public: + + // None, so far. +} STM32USARTClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_USART_STATE(obj) \ + OBJECT_CHECK(STM32USARTState, (obj), TYPE_STM32_USART) + +typedef struct { + // private: + STM32USARTParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + // Remove it if there is only one port + stm32_usart_index_t port_index; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 USART (Universal synchronous asynchronous receiver transmitter) registers. + struct { + Object *sr; // 0x0 (Status register) + Object *dr; // 0x4 (Data register) + Object *brr; // 0x8 (Baud rate register) + Object *cr1; // 0xC (Control register 1) + Object *cr2; // 0x10 (Control register 2) + Object *cr3; // 0x14 (Control register 3) + Object *gtpr; // 0x18 (Guard time and prescaler register) + } reg; + + struct { + + // SR (Status register) bitfields. + struct { + Object *pe; // [0:0] Parity error + Object *fe; // [1:1] Framing error + Object *nf; // [2:2] Noise detected flag + Object *ore; // [3:3] Overrun error + Object *idle; // [4:4] IDLE line detected + Object *rxne; // [5:5] Read data register not empty + Object *tc; // [6:6] Transmission complete + Object *txe; // [7:7] Transmit data register empty + Object *lbd; // [8:8] LIN break detection flag + Object *cts; // [9:9] CTS flag + } sr; + + // DR (Data register) bitfields. + struct { + Object *dr; // [0:8] Data value + } dr; + + // BRR (Baud rate register) bitfields. + struct { + Object *div_fraction; // [0:3] Fraction of USARTDIV + Object *div_mantissa; // [4:15] Mantissa of USARTDIV + } brr; + + // CR1 (Control register 1) bitfields. + struct { + Object *sbk; // [0:0] Send break + Object *rwu; // [1:1] Receiver wakeup + Object *re; // [2:2] Receiver enable + Object *te; // [3:3] Transmitter enable + Object *idleie; // [4:4] IDLE interrupt enable + Object *rxneie; // [5:5] RXNE interrupt enable + Object *tcie; // [6:6] Transmission complete interrupt enable + Object *txeie; // [7:7] TXE interrupt enable + Object *peie; // [8:8] PE interrupt enable + Object *ps; // [9:9] Parity selection + Object *pce; // [10:10] Parity control enable + Object *wake; // [11:11] Wakeup method + Object *m; // [12:12] Word length + Object *ue; // [13:13] USART enable + Object *over8; // [15:15] Oversampling mode + } cr1; + + // CR2 (Control register 2) bitfields. + struct { + Object *add; // [0:3] Address of the USART node + Object *lbdl; // [5:5] Lin break detection length + Object *lbdie; // [6:6] LIN break detection interrupt enable + Object *lbcl; // [8:8] Last bit clock pulse + Object *cpha; // [9:9] Clock phase + Object *cpol; // [10:10] Clock polarity + Object *clken; // [11:11] Clock enable + Object *stop; // [12:13] STOP bits + Object *linen; // [14:14] LIN mode enable + } cr2; + + // CR3 (Control register 3) bitfields. + struct { + Object *eie; // [0:0] Error interrupt enable + Object *iren; // [1:1] IrDA mode enable + Object *irlp; // [2:2] IrDA low-power + Object *hdsel; // [3:3] Half-duplex selection + Object *nack; // [4:4] Smartcard NACK enable + Object *scen; // [5:5] Smartcard mode enable + Object *dmar; // [6:6] DMA enable receiver + Object *dmat; // [7:7] DMA enable transmitter + Object *rtse; // [8:8] RTS enable + Object *ctse; // [9:9] CTS enable + Object *ctsie; // [10:10] CTS interrupt enable + Object *onebit; // [11:11] One sample bit method enable + } cr3; + + // GTPR (Guard time and prescaler register) bitfields. + struct { + Object *psc; // [0:7] Prescaler value + Object *gt; // [8:15] Guard time value + } gtpr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32USARTState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_USART_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/wwdg.c b/gnu-mcu-eclipse/devices/support/STM32F429x/wwdg.c new file mode 100644 index 0000000000..682eb40f14 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/wwdg.c @@ -0,0 +1,250 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include +#include +#include +#include + +// ----- Generated code ------------------------------------------------------- +// +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// DO NOT EDIT! Automatically generated! +static void stm32f429x_wwdg_create_objects(Object *obj, JSON_Object *svd, const char *name) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + JSON_Object *periph = svd_get_peripheral_by_name(svd, name); + svd_add_peripheral_properties_and_children(obj, periph, svd); + + // Registers. + state->u.f4.reg.cr = cm_object_get_child_by_name(obj, "CR"); + state->u.f4.reg.cfr = cm_object_get_child_by_name(obj, "CFR"); + state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR"); + + + // CR bitfields. + state->u.f4.fld.cr.t = cm_object_get_child_by_name(state->u.f4.reg.cr, "T"); + state->u.f4.fld.cr.wdga = cm_object_get_child_by_name(state->u.f4.reg.cr, "WDGA"); + + // CFR bitfields. + state->u.f4.fld.cfr.w = cm_object_get_child_by_name(state->u.f4.reg.cfr, "W"); + state->u.f4.fld.cfr.wdgtb0 = cm_object_get_child_by_name(state->u.f4.reg.cfr, "WDGTB0"); + state->u.f4.fld.cfr.wdgtb1 = cm_object_get_child_by_name(state->u.f4.reg.cfr, "WDGTB1"); + state->u.f4.fld.cfr.ewi = cm_object_get_child_by_name(state->u.f4.reg.cfr, "EWI"); + + // SR bitfields. + state->u.f4.fld.sr.ewif = cm_object_get_child_by_name(state->u.f4.reg.sr, "EWIF"); +} + +// ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + +// ----- Private -------------------------------------------------------------- + +#if 0 +static peripheral_register_t stm32_wwdg_xxx_pre_write_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + + // TODO: Add code to adjust the value (like applying some masks, + // for example prevent setting interrupts not enabled). + // Also process cleared/set by write 1/0 bits. + // The returned value will be stored in the register value. + + return full_value; +} + +static void stm32_wwdg_xxx_post_write_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size, + peripheral_register_t value, peripheral_register_t full_value) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t prev_value = peripheral_register_get_raw_prev_value(reg); + // The new register value is full_value, the old one is prev_value. + + // TODO: Add code to send the value to the consumer. +} + +static peripheral_register_t stm32_wwdg_xxx_pre_read_callback(Object *reg, + Object *periph, uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = 0; + + // Add code to get the value from the producer, and return it. + + // This value, possibly masked, will be stored in the register + // and returned when the register is read. + return value; +} + +static void stm32_wwdg_xxx_post_read_callback(Object *reg, Object *periph, + uint32_t addr, uint32_t offset, unsigned size) +{ + STM32WWDGState *state = STM32_WWDG_STATE(periph); + + peripheral_register_t value = peripheral_register_get_raw_value(reg); + + // TODO: add code to perform the post read actions, like clearing some bits. +} +#endif + +// ---------------------------------------------------------------------------- + +// TODO: remove this if the peripheral is always enabled. +static bool stm32_wwdg_is_enabled(Object *obj) +{ + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + if (register_bitfield_is_non_zero(state->enabling_bit)) { + return true; // Positive logic, bit == 1 means enabled. + } + + // Not enabled + return false; +} + +static void stm32_wwdg_instance_init_callback(Object *obj) +{ + qemu_log_function_name(); + + STM32WWDGState *state = STM32_WWDG_STATE(obj); + + // Capabilities are not yet available. + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = NULL; + + // TODO: Add code to initialise all members. +} + +static void stm32_wwdg_realize_callback(DeviceState *dev, Error **errp) +{ + qemu_log_function_name(); + + // Call parent realize(). + if (!cm_device_parent_realize(dev, errp, TYPE_STM32_WWDG)) { + return; + } + + STM32MCUState *mcu = stm32_mcu_get(); + CortexMState *cm_state = CORTEXM_MCU_STATE(mcu); + + STM32WWDGState *state = STM32_WWDG_STATE(dev); + // First thing first: get capabilities from MCU, needed everywhere. + state->capabilities = mcu->capabilities; + + // Also keep a local pointer, to access them easier. + const STM32Capabilities *capabilities = state->capabilities; + assert(capabilities != NULL); + + Object *obj = OBJECT(dev); + + const char *periph_name = "WWDG"; + + svd_set_peripheral_address_block(cm_state->svd_json, periph_name, obj); + peripheral_create_memory_region(obj); + + // TODO: remove this if the peripheral is always enabled. + char enabling_bit_name[STM32_RCC_SIZEOF_ENABLING_BITFIELD]; + + switch (capabilities->family) { + case STM32_FAMILY_F4: + + if (capabilities->f4.is_429x ) { + + stm32f429x_wwdg_create_objects(obj, cm_state->svd_json, periph_name); + + // TODO: add actions. + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "follows"); + // cm_object_property_set_str(state->u.f4.fld.xxx.fff, "GGG", "cleared-by"); + + // TODO: add callbacks. + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_wwdg_xxx_pre_read_callback); + // peripheral_register_set_post_read(state->f4.reg.xxx, &stm32_wwdg_xxx_post_read_callback); + // peripheral_register_set_pre_read(state->f4.reg.xxx, &stm32_wwdg_xxx_pret_read_callback); + // peripheral_register_set_post_write(state->f4.reg.xxx, &stm32_wwdg_xxx_post_write_callback); + + // TODO: add interrupts. + + // TODO: remove this if the peripheral is always enabled. + snprintf(enabling_bit_name, sizeof(enabling_bit_name) - 1, + DEVICE_PATH_STM32_RCC "/AHB1ENR/WWDGEN"); + + + } else { + assert(false); + } + + break; + + default: + assert(false); + break; + } + + // TODO: remove this if the peripheral is always enabled. + state->enabling_bit = OBJECT(cm_device_by_name(enabling_bit_name)); + + peripheral_prepare_registers(obj); +} + +static void stm32_wwdg_reset_callback(DeviceState *dev) +{ + qemu_log_function_name(); + + // Call parent reset(); this will reset all children registers. + cm_device_parent_reset(dev, TYPE_STM32_WWDG); +} + +static void stm32_wwdg_class_init_callback(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32_wwdg_reset_callback; + dc->realize = stm32_wwdg_realize_callback; + + // TODO: remove this if the peripheral is always enabled. + PeripheralClass *per_class = PERIPHERAL_CLASS(klass); + per_class->is_enabled = stm32_wwdg_is_enabled; +} + +static const TypeInfo stm32_wwdg_type_info = { + .name = TYPE_STM32_WWDG, + .parent = TYPE_STM32_WWDG_PARENT, + .instance_init = stm32_wwdg_instance_init_callback, + .instance_size = sizeof(STM32WWDGState), + .class_init = stm32_wwdg_class_init_callback, + .class_size = sizeof(STM32WWDGClass) }; + +static void stm32_wwdg_register_types(void) +{ + type_register_static(&stm32_wwdg_type_info); +} + +type_init(stm32_wwdg_register_types); + +// ---------------------------------------------------------------------------- diff --git a/gnu-mcu-eclipse/devices/support/STM32F429x/wwdg.h b/gnu-mcu-eclipse/devices/support/STM32F429x/wwdg.h new file mode 100644 index 0000000000..9e32867abb --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/STM32F429x/wwdg.h @@ -0,0 +1,121 @@ +/* + * STM32 - WWDG (Window watchdog) emulation. + * + * Copyright (c) 2016 Liviu Ionescu. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef STM32_WWDG_H_ +#define STM32_WWDG_H_ + +#include "qemu/osdep.h" + +#include +#include + +// ---------------------------------------------------------------------------- + +#define DEVICE_PATH_STM32_WWDG DEVICE_PATH_STM32 "WWDG" + + + +// ---------------------------------------------------------------------------- + +#define TYPE_STM32_WWDG TYPE_STM32_PREFIX "wwdg" TYPE_PERIPHERAL_SUFFIX + +// ---------------------------------------------------------------------------- + +// Parent definitions. +#define TYPE_STM32_WWDG_PARENT TYPE_PERIPHERAL +typedef PeripheralClass STM32WWDGParentClass; +typedef PeripheralState STM32WWDGParentState; + +// ---------------------------------------------------------------------------- + +// Class definitions. +#define STM32_WWDG_GET_CLASS(obj) \ + OBJECT_GET_CLASS(STM32WWDGClass, (obj), TYPE_STM32_WWDG) +#define STM32_WWDG_CLASS(klass) \ + OBJECT_CLASS_CHECK(STM32WWDGClass, (klass), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentClass parent_class; + // public: + + // None, so far. +} STM32WWDGClass; + +// ---------------------------------------------------------------------------- + +// Instance definitions. +#define STM32_WWDG_STATE(obj) \ + OBJECT_CHECK(STM32WWDGState, (obj), TYPE_STM32_WWDG) + +typedef struct { + // private: + STM32WWDGParentState parent_obj; + // public: + + const STM32Capabilities *capabilities; + + // TODO: remove this if the peripheral is always enabled. + // Points to the bitfield that enables the peripheral. + Object *enabling_bit; + + union { + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + + // DO NOT REMOVE FIELDS! Automatically generated! + // Merge fields from different family members. + struct { + // F4 WWDG (Window watchdog) registers. + struct { + Object *cr; // 0x0 (Control register) + Object *cfr; // 0x4 (Configuration register) + Object *sr; // 0x8 (Status register) + } reg; + + struct { + + // CR (Control register) bitfields. + struct { + Object *t; // [0:6] 7-bit counter (MSB to LSB) + Object *wdga; // [7:7] Activation bit + } cr; + + // CFR (Configuration register) bitfields. + struct { + Object *w; // [0:6] 7-bit window value + Object *wdgtb0; // [7:7] Timer base + Object *wdgtb1; // [8:8] Timer base + Object *ewi; // [9:9] Early wakeup interrupt + } cfr; + + // SR (Status register) bitfields. + struct { + Object *ewif; // [0:0] Early wakeup interrupt flag + } sr; + } fld; + } f4; + + // ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- 8< ----- + } u; + +} STM32WWDGState; + +// ---------------------------------------------------------------------------- + +#endif /* STM32_WWDG_H_ */ diff --git a/gnu-mcu-eclipse/devices/support/code.sh b/gnu-mcu-eclipse/devices/support/code.sh new file mode 100644 index 0000000000..e68f3f68c6 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/code.sh @@ -0,0 +1,56 @@ +#!/usr/bin/env bash + +# ----------------------------------------------------------------------------- +# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d). + +if [[ ! -z ${DEBUG} ]] +then + set ${DEBUG} # Activate the expand mode if DEBUG is -x. +else + DEBUG="" +fi + +set -o errexit # Exit if command failed. +set -o pipefail # Exit if pipe failed. +set -o nounset # Exit if variable not set. + +# Remove the initial space and instead use '\n'. +IFS=$'\n\t' + +# ------------------------------------------------------------------ + +cd "$(dirname "$0")" + +echo +xsvd code \ +--file "../STM32F0x1-qemu.json" \ +--verbose + +echo +xsvd code \ +--file "../STM32F0x2-qemu.json" \ +--verbose + +echo +xsvd code \ +--file "../STM32F103xx-qemu.json" \ +--verbose + +echo +xsvd code \ +--file "../STM32F107xx-qemu.json" \ +--verbose + +echo +xsvd code \ +--file "../STM32F40x-qemu.json" \ +--verbose + +echo +xsvd code \ +--file "../STM32F429x-qemu.json" \ +--verbose + +echo + + diff --git a/gnu-mcu-eclipse/devices/support/code.sh.command b/gnu-mcu-eclipse/devices/support/code.sh.command new file mode 100755 index 0000000000..64f37e0a79 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/code.sh.command @@ -0,0 +1,6 @@ +#! /bin/bash + +cd "$(dirname "$0")" + +bash code.sh + diff --git a/gnu-mcu-eclipse/devices/support/convert.sh b/gnu-mcu-eclipse/devices/support/convert.sh new file mode 100644 index 0000000000..2fff707bdf --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/convert.sh @@ -0,0 +1,62 @@ +#!/usr/bin/env bash + +# ----------------------------------------------------------------------------- +# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d). + +if [[ ! -z ${DEBUG} ]] +then + set ${DEBUG} # Activate the expand mode if DEBUG is -x. +else + DEBUG="" +fi + +set -o errexit # Exit if command failed. +set -o pipefail # Exit if pipe failed. +set -o nounset # Exit if variable not set. + +# Remove the initial space and instead use '\n'. +IFS=$'\n\t' + +# ------------------------------------------------------------------ + +cd "$(dirname "$0")" + +XPACKS_FOLDER=${XPACKS_FOLDER:-"$HOME/Library/xPacks"} + +echo +xsvd convert \ +--file "${XPACKS_FOLDER}/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x1.svd" \ +--output "STM32F0x1-xsvd.json" \ +--verbose + +echo +xsvd convert \ +--file "${XPACKS_FOLDER}/Keil/STM32F0xx_DFP/1.5.0/SVD/STM32F0x2.svd" \ +--output "STM32F0x2-xsvd.json" \ +--verbose + +echo +xsvd convert \ +--file "${XPACKS_FOLDER}/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F103xx.svd" \ +--output "STM32F103xx-xsvd.json" \ +--verbose + +echo +xsvd convert \ +--file "${XPACKS_FOLDER}/Keil/STM32F1xx_DFP/2.1.0/SVD/STM32F107xx.svd" \ +--output "STM32F107xx-xsvd.json" \ +--verbose + +echo +xsvd convert \ +--file "${XPACKS_FOLDER}/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F40x.svd" \ +--output "STM32F40x-xsvd.json" \ +--verbose + +echo +xsvd convert \ +--file "${XPACKS_FOLDER}/Keil/STM32F4xx_DFP/2.9.0/CMSIS/SVD/STM32F429x.svd" \ +--output "STM32F429x-xsvd.json" \ +--verbose + +echo diff --git a/gnu-mcu-eclipse/devices/support/convert.sh.command b/gnu-mcu-eclipse/devices/support/convert.sh.command new file mode 100755 index 0000000000..65316f079b --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/convert.sh.command @@ -0,0 +1,6 @@ +#! /bin/bash + +cd "$(dirname "$0")" + +bash convert.sh + diff --git a/gnu-mcu-eclipse/devices/support/patch.sh b/gnu-mcu-eclipse/devices/support/patch.sh new file mode 100644 index 0000000000..cea9b52884 --- /dev/null +++ b/gnu-mcu-eclipse/devices/support/patch.sh @@ -0,0 +1,88 @@ +#!/usr/bin/env bash + +# ----------------------------------------------------------------------------- +# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d). + +if [[ ! -z ${DEBUG} ]] +then + set ${DEBUG} # Activate the expand mode if DEBUG is -x. +else + DEBUG="" +fi + +set -o errexit # Exit if command failed. +set -o pipefail # Exit if pipe failed. +set -o nounset # Exit if variable not set. + +# Remove the initial space and instead use '\n'. +IFS=$'\n\t' + +# ------------------------------------------------------------------ + +cd "$(dirname "$0")" + +echo +xsvd patch \ +--file "STM32F0x1-xsvd.json" \ +--patch "STM32F0x1-patch.json" \ +--output "../STM32F0x1-qemu.json" \ +--remove "NVIC" \ +--verbose + +echo +xsvd patch \ +--file "STM32F0x2-xsvd.json" \ +--patch "STM32F0x2-patch.json" \ +--output "../STM32F0x2-qemu.json" \ +--remove "NVIC" \ +--verbose + +echo +xsvd patch \ +--file "STM32F103xx-xsvd.json" \ +--patch "STM32F103xx-patch.json" \ +--output "../STM32F103xx-qemu.json" \ +--remove "NVIC" \ +--verbose + +echo +xsvd patch \ +--file "STM32F107xx-xsvd.json" \ +--patch "STM32F107xx-patch.json" \ +--output "../STM32F107xx-qemu.json" \ +--remove "NVIC" \ +--verbose + +echo +xsvd patch \ +--file "STM32F40x-xsvd.json" \ +--patch "STM32F40x-patch.json" \ +--output "../STM32F40x-qemu.json" \ +--remove "NVIC" \ +--group-bitfield "RCC/PLLCFGR/PLLQ" \ +--group-bitfield "RCC/PLLCFGR/PLLP" \ +--group-bitfield "RCC/PLLCFGR/PLLN" \ +--group-bitfield "RCC/PLLCFGR/PLLM" \ +--group-bitfield "RCC/CFGR/SWS" \ +--group-bitfield "RCC/CFGR/SW" \ +--group-bitfield "RCC/BDCR/RTCSEL" \ +--verbose + +echo +xsvd patch \ +--file "STM32F429x-xsvd.json" \ +--patch "STM32F429x-patch.json" \ +--output "../STM32F429x-qemu.json" \ +--remove "NVIC" \ +--group-bitfield "RCC/PLLCFGR/PLLQ" \ +--group-bitfield "RCC/PLLCFGR/PLLP" \ +--group-bitfield "RCC/PLLCFGR/PLLN" \ +--group-bitfield "RCC/PLLCFGR/PLLM" \ +--group-bitfield "RCC/CFGR/SWS" \ +--group-bitfield "RCC/CFGR/SW" \ +--group-bitfield "RCC/BDCR/RTCSEL" \ +--verbose + +echo + + diff --git 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